blob: 9fb3d03477c99099f530fac111c46851fcf61198 [file] [log] [blame]
Bill Schmidte0bc3752012-10-10 22:25:11 +00001; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s
2; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s
Bill Schmidt26160f42012-10-10 21:25:01 +00003
4; This verifies that we generate correct spill/reload code for vector regs.
5
6define void @addrtaken(i32 %i, <4 x float> %w) nounwind {
7entry:
8 %i.addr = alloca i32, align 4
9 %w.addr = alloca <4 x float>, align 16
10 store i32 %i, i32* %i.addr, align 4
11 store <4 x float> %w, <4 x float>* %w.addr, align 16
12 call void @foo(i32* %i.addr)
13 ret void
14}
15
Hal Finkel32497292013-03-17 04:43:44 +000016; CHECK: stvx 2, 1,
17; CHECK: lvx 2, 1,
Bill Schmidt26160f42012-10-10 21:25:01 +000018
19declare void @foo(i32*)