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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Evan Cheng957840b2007-02-21 02:22:03 +000030#include "llvm/ADT/BitVector.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000031#include "llvm/ADT/Statistic.h"
32#include "llvm/ADT/STLExtras.h"
Chris Lattner08a4d5a2007-01-23 00:59:48 +000033#include "llvm/ADT/SmallSet.h"
Chris Lattner27f29162004-10-26 15:35:58 +000034#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000035using namespace llvm;
36
Chris Lattnercd3245a2006-12-19 22:41:21 +000037STATISTIC(NumSpills, "Number of register spills");
Evan Cheng2638e1a2007-03-20 08:13:50 +000038STATISTIC(NumReMats, "Number of re-materialization");
Evan Chengb6ca4b32007-08-14 23:25:37 +000039STATISTIC(NumDRM , "Number of re-materializable defs elided");
Chris Lattnercd3245a2006-12-19 22:41:21 +000040STATISTIC(NumStores, "Number of stores added");
41STATISTIC(NumLoads , "Number of loads added");
42STATISTIC(NumReused, "Number of values reused");
43STATISTIC(NumDSE , "Number of dead stores elided");
44STATISTIC(NumDCE , "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000045
Chris Lattnercd3245a2006-12-19 22:41:21 +000046namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000047 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000048
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000049 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000050 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000051 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000052 cl::Prefix,
53 cl::values(clEnumVal(simple, " simple spiller"),
54 clEnumVal(local, " local spiller"),
55 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000056 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000057}
58
Chris Lattner8c4d88d2004-09-30 01:54:45 +000059//===----------------------------------------------------------------------===//
60// VirtRegMap implementation
61//===----------------------------------------------------------------------===//
62
Chris Lattner29268692006-09-05 02:12:02 +000063VirtRegMap::VirtRegMap(MachineFunction &mf)
64 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
Evan Cheng2638e1a2007-03-20 08:13:50 +000065 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT),
Evan Cheng549f27d32007-08-13 23:45:17 +000066 Virt2ReMatIdMap(NO_STACK_SLOT), ReMatMap(NULL),
Evan Cheng2638e1a2007-03-20 08:13:50 +000067 ReMatId(MAX_STACK_SLOT+1) {
Chris Lattner29268692006-09-05 02:12:02 +000068 grow();
69}
70
Chris Lattner8c4d88d2004-09-30 01:54:45 +000071void VirtRegMap::grow() {
Evan Cheng549f27d32007-08-13 23:45:17 +000072 unsigned LastVirtReg = MF.getSSARegMap()->getLastVirtReg();
73 Virt2PhysMap.grow(LastVirtReg);
74 Virt2StackSlotMap.grow(LastVirtReg);
75 Virt2ReMatIdMap.grow(LastVirtReg);
76 ReMatMap.grow(LastVirtReg);
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000077}
78
Chris Lattner8c4d88d2004-09-30 01:54:45 +000079int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
80 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000081 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000082 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000083 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
84 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
85 RC->getAlignment());
86 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000087 ++NumSpills;
88 return frameIndex;
89}
90
91void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
92 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000093 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000094 "attempt to assign stack slot to already spilled register");
Evan Cheng91935142007-04-04 07:40:01 +000095 assert((frameIndex >= 0 ||
96 (frameIndex >= MF.getFrameInfo()->getObjectIndexBegin())) &&
97 "illegal fixed frame index");
Chris Lattner7f690e62004-09-30 02:15:18 +000098 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000099}
100
Evan Cheng2638e1a2007-03-20 08:13:50 +0000101int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
102 assert(MRegisterInfo::isVirtualRegister(virtReg));
Evan Cheng549f27d32007-08-13 23:45:17 +0000103 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
Evan Cheng2638e1a2007-03-20 08:13:50 +0000104 "attempt to assign re-mat id to already spilled register");
Evan Cheng549f27d32007-08-13 23:45:17 +0000105 Virt2ReMatIdMap[virtReg] = ReMatId;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000106 return ReMatId++;
107}
108
Evan Cheng549f27d32007-08-13 23:45:17 +0000109void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
110 assert(MRegisterInfo::isVirtualRegister(virtReg));
111 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
112 "attempt to assign re-mat id to already spilled register");
113 Virt2ReMatIdMap[virtReg] = id;
114}
115
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000116void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +0000117 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000118 // Move previous memory references folded to new instruction.
119 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000120 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000121 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
122 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +0000123 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000124 }
Chris Lattnerdbea9732004-09-30 16:35:08 +0000125
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000126 ModRef MRInfo;
Evan Cheng5c2a4602006-12-08 08:02:34 +0000127 const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor();
128 if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 ||
Evan Chengcc22a7a2006-12-08 18:45:48 +0000129 TID->findTiedToSrcOperand(OpNo) != -1) {
Chris Lattner29268692006-09-05 02:12:02 +0000130 // Folded a two-address operand.
131 MRInfo = isModRef;
132 } else if (OldMI->getOperand(OpNo).isDef()) {
133 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000134 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000135 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000136 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000137
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000138 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000139 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000140}
141
Chris Lattner7f690e62004-09-30 02:15:18 +0000142void VirtRegMap::print(std::ostream &OS) const {
143 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000144
Chris Lattner7f690e62004-09-30 02:15:18 +0000145 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000146 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000147 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
148 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
149 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000150
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000151 }
152
153 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000154 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
155 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
156 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
157 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000158}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000159
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000160void VirtRegMap::dump() const {
Bill Wendling5c7e3262006-12-17 05:15:13 +0000161 print(DOUT);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000162}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000163
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000164
165//===----------------------------------------------------------------------===//
166// Simple Spiller Implementation
167//===----------------------------------------------------------------------===//
168
169Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000170
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000171namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000172 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000173 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000174 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000175}
176
Chris Lattner35f27052006-05-01 21:16:03 +0000177bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000178 DOUT << "********** REWRITE MACHINE CODE **********\n";
179 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000180 const TargetMachine &TM = MF.getTarget();
181 const MRegisterInfo &MRI = *TM.getRegisterInfo();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000182
Chris Lattner4ea1b822004-09-30 02:33:48 +0000183 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
184 // each vreg once (in the case where a spilled vreg is used by multiple
185 // operands). This is always smaller than the number of operands to the
186 // current machine instr, so it should be small.
187 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000188
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000189 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
190 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000191 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000192 MachineBasicBlock &MBB = *MBBI;
193 for (MachineBasicBlock::iterator MII = MBB.begin(),
194 E = MBB.end(); MII != E; ++MII) {
195 MachineInstr &MI = *MII;
196 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000197 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000198 if (MO.isRegister() && MO.getReg())
199 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
200 unsigned VirtReg = MO.getReg();
201 unsigned PhysReg = VRM.getPhys(VirtReg);
Evan Cheng549f27d32007-08-13 23:45:17 +0000202 if (!VRM.isAssignedReg(VirtReg)) {
Chris Lattner886dd912005-04-04 21:35:34 +0000203 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000204 const TargetRegisterClass* RC =
205 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000206
Chris Lattner886dd912005-04-04 21:35:34 +0000207 if (MO.isUse() &&
208 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
209 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000210 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000211 LoadedRegs.push_back(VirtReg);
212 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000213 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000214 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000215
Chris Lattner886dd912005-04-04 21:35:34 +0000216 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000217 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000218 ++NumStores;
219 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000220 }
Evan Cheng6c087e52007-04-25 22:13:27 +0000221 MF.setPhysRegUsed(PhysReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000222 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000223 } else {
Evan Cheng6c087e52007-04-25 22:13:27 +0000224 MF.setPhysRegUsed(MO.getReg());
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000225 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000226 }
Chris Lattner886dd912005-04-04 21:35:34 +0000227
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000228 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000229 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000230 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000231 }
232 return true;
233}
234
235//===----------------------------------------------------------------------===//
236// Local Spiller Implementation
237//===----------------------------------------------------------------------===//
238
239namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000240 /// LocalSpiller - This spiller does a simple pass over the machine basic
241 /// block to attempt to keep spills in registers as much as possible for
242 /// blocks that have low register pressure (the vreg may be spilled due to
243 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000244 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Evan Cheng32dfbea2007-10-12 08:50:34 +0000245 SSARegMap *RegMap;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000246 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000247 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000248 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000249 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Evan Cheng32dfbea2007-10-12 08:50:34 +0000250 RegMap = MF.getSSARegMap();
Chris Lattner7fb64342004-10-01 19:04:51 +0000251 MRI = MF.getTarget().getRegisterInfo();
252 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000253 DOUT << "\n**** Local spiller rewriting function '"
254 << MF.getFunction()->getName() << "':\n";
David Greene04fa32f2007-09-06 16:36:39 +0000255 DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!) ****\n";
256 DEBUG(MF.dump());
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000257
Chris Lattner7fb64342004-10-01 19:04:51 +0000258 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
259 MBB != E; ++MBB)
Evan Cheng549f27d32007-08-13 23:45:17 +0000260 RewriteMBB(*MBB, VRM);
David Greene04fa32f2007-09-06 16:36:39 +0000261
262 DOUT << "**** Post Machine Instrs ****\n";
263 DEBUG(MF.dump());
264
Chris Lattner7fb64342004-10-01 19:04:51 +0000265 return true;
266 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000267 private:
Evan Cheng549f27d32007-08-13 23:45:17 +0000268 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000269 };
270}
271
Chris Lattner66cf80f2006-02-03 23:13:58 +0000272/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
Evan Cheng549f27d32007-08-13 23:45:17 +0000273/// top down, keep track of which spills slots or remat are available in each
274/// register.
Chris Lattner593c9582006-02-03 23:28:46 +0000275///
276/// Note that not all physregs are created equal here. In particular, some
277/// physregs are reloads that we are allowed to clobber or ignore at any time.
278/// Other physregs are values that the register allocated program is using that
279/// we cannot CHANGE, but we can read if we like. We keep track of this on a
Evan Cheng549f27d32007-08-13 23:45:17 +0000280/// per-stack-slot / remat id basis as the low bit in the value of the
281/// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks
282/// this bit and addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000283namespace {
284class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000285 const MRegisterInfo *MRI;
286 const TargetInstrInfo *TII;
287
Evan Cheng549f27d32007-08-13 23:45:17 +0000288 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled
289 // or remat'ed virtual register values that are still available, due to being
290 // loaded or stored to, but not invalidated yet.
291 std::map<int, unsigned> SpillSlotsOrReMatsAvailable;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000292
Evan Cheng549f27d32007-08-13 23:45:17 +0000293 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable,
294 // indicating which stack slot values are currently held by a physreg. This
295 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a
296 // physreg is modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000297 std::multimap<unsigned, int> PhysRegsAvailable;
298
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000299 void disallowClobberPhysRegOnly(unsigned PhysReg);
300
Chris Lattner66cf80f2006-02-03 23:13:58 +0000301 void ClobberPhysRegOnly(unsigned PhysReg);
302public:
303 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
304 : MRI(mri), TII(tii) {
305 }
306
Evan Cheng91e23902007-02-23 01:13:26 +0000307 const MRegisterInfo *getRegInfo() const { return MRI; }
308
Evan Cheng549f27d32007-08-13 23:45:17 +0000309 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is
310 /// available in a physical register, return that PhysReg, otherwise
311 /// return 0.
312 unsigned getSpillSlotOrReMatPhysReg(int Slot) const {
313 std::map<int, unsigned>::const_iterator I =
314 SpillSlotsOrReMatsAvailable.find(Slot);
315 if (I != SpillSlotsOrReMatsAvailable.end()) {
Evan Chengb9591c62007-07-11 08:47:44 +0000316 return I->second >> 1; // Remove the CanClobber bit.
Evan Cheng91e23902007-02-23 01:13:26 +0000317 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000318 return 0;
319 }
Evan Chengde4e9422007-02-25 09:51:27 +0000320
Evan Cheng549f27d32007-08-13 23:45:17 +0000321 /// addAvailable - Mark that the specified stack slot / remat is available in
322 /// the specified physreg. If CanClobber is true, the physreg can be modified
323 /// at any time without changing the semantics of the program.
324 void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg,
Evan Cheng91e23902007-02-23 01:13:26 +0000325 bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000326 // If this stack slot is thought to be available in some other physreg,
327 // remove its record.
Evan Cheng549f27d32007-08-13 23:45:17 +0000328 ModifyStackSlotOrReMat(SlotOrReMat);
Chris Lattner86662492006-02-03 23:50:46 +0000329
Evan Cheng549f27d32007-08-13 23:45:17 +0000330 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat));
Evan Cheng90a43c32007-08-15 20:20:34 +0000331 SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) | (unsigned)CanClobber;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000332
Evan Cheng549f27d32007-08-13 23:45:17 +0000333 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
334 DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000335 else
Evan Cheng549f27d32007-08-13 23:45:17 +0000336 DOUT << "Remembering SS#" << SlotOrReMat;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000337 DOUT << " in physreg " << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000338 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000339
Chris Lattner593c9582006-02-03 23:28:46 +0000340 /// canClobberPhysReg - Return true if the spiller is allowed to change the
341 /// value of the specified stackslot register if it desires. The specified
342 /// stack slot must be available in a physreg for this query to make sense.
Evan Cheng549f27d32007-08-13 23:45:17 +0000343 bool canClobberPhysReg(int SlotOrReMat) const {
Evan Cheng90a43c32007-08-15 20:20:34 +0000344 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) &&
345 "Value not available!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000346 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1;
Chris Lattner593c9582006-02-03 23:28:46 +0000347 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000348
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000349 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
350 /// stackslot register. The register is still available but is no longer
351 /// allowed to be modifed.
352 void disallowClobberPhysReg(unsigned PhysReg);
353
Chris Lattner66cf80f2006-02-03 23:13:58 +0000354 /// ClobberPhysReg - This is called when the specified physreg changes
355 /// value. We use this to invalidate any info about stuff we thing lives in
356 /// it and any of its aliases.
357 void ClobberPhysReg(unsigned PhysReg);
358
Evan Cheng90a43c32007-08-15 20:20:34 +0000359 /// ModifyStackSlotOrReMat - This method is called when the value in a stack
360 /// slot changes. This removes information about which register the previous
361 /// value for this slot lives in (as the previous value is dead now).
Evan Cheng549f27d32007-08-13 23:45:17 +0000362 void ModifyStackSlotOrReMat(int SlotOrReMat);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000363};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000364}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000365
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000366/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
367/// stackslot register. The register is still available but is no longer
368/// allowed to be modifed.
369void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
370 std::multimap<unsigned, int>::iterator I =
371 PhysRegsAvailable.lower_bound(PhysReg);
372 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Evan Cheng549f27d32007-08-13 23:45:17 +0000373 int SlotOrReMat = I->second;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000374 I++;
Evan Cheng549f27d32007-08-13 23:45:17 +0000375 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000376 "Bidirectional map mismatch!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000377 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000378 DOUT << "PhysReg " << MRI->getName(PhysReg)
379 << " copied, it is available for use but can no longer be modified\n";
380 }
381}
382
383/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
384/// stackslot register and its aliases. The register and its aliases may
385/// still available but is no longer allowed to be modifed.
386void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
387 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
388 disallowClobberPhysRegOnly(*AS);
389 disallowClobberPhysRegOnly(PhysReg);
390}
391
Chris Lattner66cf80f2006-02-03 23:13:58 +0000392/// ClobberPhysRegOnly - This is called when the specified physreg changes
393/// value. We use this to invalidate any info about stuff we thing lives in it.
394void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
395 std::multimap<unsigned, int>::iterator I =
396 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000397 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Evan Cheng549f27d32007-08-13 23:45:17 +0000398 int SlotOrReMat = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000399 PhysRegsAvailable.erase(I++);
Evan Cheng549f27d32007-08-13 23:45:17 +0000400 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000401 "Bidirectional map mismatch!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000402 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000403 DOUT << "PhysReg " << MRI->getName(PhysReg)
Evan Cheng2638e1a2007-03-20 08:13:50 +0000404 << " clobbered, invalidating ";
Evan Cheng549f27d32007-08-13 23:45:17 +0000405 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
406 DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
Evan Cheng2638e1a2007-03-20 08:13:50 +0000407 else
Evan Cheng549f27d32007-08-13 23:45:17 +0000408 DOUT << "SS#" << SlotOrReMat << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000409 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000410}
411
Chris Lattner66cf80f2006-02-03 23:13:58 +0000412/// ClobberPhysReg - This is called when the specified physreg changes
413/// value. We use this to invalidate any info about stuff we thing lives in
414/// it and any of its aliases.
415void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000416 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000417 ClobberPhysRegOnly(*AS);
418 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000419}
420
Evan Cheng90a43c32007-08-15 20:20:34 +0000421/// ModifyStackSlotOrReMat - This method is called when the value in a stack
422/// slot changes. This removes information about which register the previous
423/// value for this slot lives in (as the previous value is dead now).
Evan Cheng549f27d32007-08-13 23:45:17 +0000424void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) {
Evan Cheng90a43c32007-08-15 20:20:34 +0000425 std::map<int, unsigned>::iterator It =
426 SpillSlotsOrReMatsAvailable.find(SlotOrReMat);
Evan Cheng549f27d32007-08-13 23:45:17 +0000427 if (It == SpillSlotsOrReMatsAvailable.end()) return;
Evan Chengb9591c62007-07-11 08:47:44 +0000428 unsigned Reg = It->second >> 1;
Evan Cheng549f27d32007-08-13 23:45:17 +0000429 SpillSlotsOrReMatsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000430
431 // This register may hold the value of multiple stack slots, only remove this
432 // stack slot from the set of values the register contains.
433 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
434 for (; ; ++I) {
435 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
436 "Map inverse broken!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000437 if (I->second == SlotOrReMat) break;
Chris Lattner07cf1412006-02-03 00:36:31 +0000438 }
439 PhysRegsAvailable.erase(I);
440}
441
442
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000443
Evan Cheng28bb4622007-07-11 19:17:18 +0000444/// InvalidateKills - MI is going to be deleted. If any of its operands are
445/// marked kill, then invalidate the information.
446static void InvalidateKills(MachineInstr &MI, BitVector &RegKills,
Evan Chengc91f0b82007-08-14 20:23:13 +0000447 std::vector<MachineOperand*> &KillOps,
Evan Chengb6ca4b32007-08-14 23:25:37 +0000448 SmallVector<unsigned, 1> *KillRegs = NULL) {
Evan Cheng28bb4622007-07-11 19:17:18 +0000449 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
450 MachineOperand &MO = MI.getOperand(i);
Dan Gohman92dfe202007-09-14 20:33:02 +0000451 if (!MO.isRegister() || !MO.isUse() || !MO.isKill())
Evan Cheng28bb4622007-07-11 19:17:18 +0000452 continue;
453 unsigned Reg = MO.getReg();
Evan Chengb6ca4b32007-08-14 23:25:37 +0000454 if (KillRegs)
455 KillRegs->push_back(Reg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000456 if (KillOps[Reg] == &MO) {
457 RegKills.reset(Reg);
458 KillOps[Reg] = NULL;
459 }
460 }
461}
462
Evan Chengb6ca4b32007-08-14 23:25:37 +0000463/// InvalidateRegDef - If the def operand of the specified def MI is now dead
464/// (since it's spill instruction is removed), mark it isDead. Also checks if
465/// the def MI has other definition operands that are not dead. Returns it by
466/// reference.
467static bool InvalidateRegDef(MachineBasicBlock::iterator I,
468 MachineInstr &NewDef, unsigned Reg,
469 bool &HasLiveDef) {
470 // Due to remat, it's possible this reg isn't being reused. That is,
471 // the def of this reg (by prev MI) is now dead.
472 MachineInstr *DefMI = I;
473 MachineOperand *DefOp = NULL;
474 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
475 MachineOperand &MO = DefMI->getOperand(i);
Dan Gohman92dfe202007-09-14 20:33:02 +0000476 if (MO.isRegister() && MO.isDef()) {
Evan Chengb6ca4b32007-08-14 23:25:37 +0000477 if (MO.getReg() == Reg)
478 DefOp = &MO;
479 else if (!MO.isDead())
480 HasLiveDef = true;
481 }
482 }
483 if (!DefOp)
484 return false;
485
486 bool FoundUse = false, Done = false;
487 MachineBasicBlock::iterator E = NewDef;
488 ++I; ++E;
489 for (; !Done && I != E; ++I) {
490 MachineInstr *NMI = I;
491 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) {
492 MachineOperand &MO = NMI->getOperand(j);
Dan Gohman92dfe202007-09-14 20:33:02 +0000493 if (!MO.isRegister() || MO.getReg() != Reg)
Evan Chengb6ca4b32007-08-14 23:25:37 +0000494 continue;
495 if (MO.isUse())
496 FoundUse = true;
497 Done = true; // Stop after scanning all the operands of this MI.
498 }
499 }
500 if (!FoundUse) {
501 // Def is dead!
502 DefOp->setIsDead();
503 return true;
504 }
505 return false;
506}
507
Evan Cheng28bb4622007-07-11 19:17:18 +0000508/// UpdateKills - Track and update kill info. If a MI reads a register that is
509/// marked kill, then it must be due to register reuse. Transfer the kill info
510/// over.
511static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
512 std::vector<MachineOperand*> &KillOps) {
513 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
514 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
515 MachineOperand &MO = MI.getOperand(i);
Dan Gohman92dfe202007-09-14 20:33:02 +0000516 if (!MO.isRegister() || !MO.isUse())
Evan Cheng28bb4622007-07-11 19:17:18 +0000517 continue;
518 unsigned Reg = MO.getReg();
519 if (Reg == 0)
520 continue;
521
522 if (RegKills[Reg]) {
523 // That can't be right. Register is killed but not re-defined and it's
524 // being reused. Let's fix that.
525 KillOps[Reg]->unsetIsKill();
526 if (i < TID->numOperands &&
527 TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
528 // Unless it's a two-address operand, this is the new kill.
529 MO.setIsKill();
530 }
531
532 if (MO.isKill()) {
533 RegKills.set(Reg);
534 KillOps[Reg] = &MO;
535 }
536 }
537
538 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
539 const MachineOperand &MO = MI.getOperand(i);
Dan Gohman92dfe202007-09-14 20:33:02 +0000540 if (!MO.isRegister() || !MO.isDef())
Evan Cheng28bb4622007-07-11 19:17:18 +0000541 continue;
542 unsigned Reg = MO.getReg();
543 RegKills.reset(Reg);
544 KillOps[Reg] = NULL;
545 }
546}
547
548
Chris Lattner7fb64342004-10-01 19:04:51 +0000549// ReusedOp - For each reused operand, we keep track of a bit of information, in
550// case we need to rollback upon processing a new operand. See comments below.
551namespace {
552 struct ReusedOp {
553 // The MachineInstr operand that reused an available value.
554 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000555
Evan Cheng549f27d32007-08-13 23:45:17 +0000556 // StackSlotOrReMat - The spill slot or remat id of the value being reused.
557 unsigned StackSlotOrReMat;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000558
Chris Lattner7fb64342004-10-01 19:04:51 +0000559 // PhysRegReused - The physical register the value was available in.
560 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000561
Chris Lattner7fb64342004-10-01 19:04:51 +0000562 // AssignedPhysReg - The physreg that was assigned for use by the reload.
563 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000564
565 // VirtReg - The virtual register itself.
566 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000567
Chris Lattner8a61a752005-10-06 17:19:06 +0000568 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
569 unsigned vreg)
Evan Cheng90a43c32007-08-15 20:20:34 +0000570 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr),
571 AssignedPhysReg(apr), VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000572 };
Chris Lattner540fec62006-02-25 01:51:33 +0000573
574 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
575 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000576 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000577 MachineInstr &MI;
578 std::vector<ReusedOp> Reuses;
Evan Cheng957840b2007-02-21 02:22:03 +0000579 BitVector PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000580 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000581 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
Evan Cheng957840b2007-02-21 02:22:03 +0000582 PhysRegsClobbered.resize(mri->getNumRegs());
Evan Chenge077ef62006-11-04 00:21:55 +0000583 }
Chris Lattner540fec62006-02-25 01:51:33 +0000584
585 bool hasReuses() const {
586 return !Reuses.empty();
587 }
588
589 /// addReuse - If we choose to reuse a virtual register that is already
590 /// available instead of reloading it, remember that we did so.
Evan Cheng549f27d32007-08-13 23:45:17 +0000591 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat,
Chris Lattner540fec62006-02-25 01:51:33 +0000592 unsigned PhysRegReused, unsigned AssignedPhysReg,
593 unsigned VirtReg) {
594 // If the reload is to the assigned register anyway, no undo will be
595 // required.
596 if (PhysRegReused == AssignedPhysReg) return;
597
598 // Otherwise, remember this.
Evan Cheng549f27d32007-08-13 23:45:17 +0000599 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused,
Chris Lattner540fec62006-02-25 01:51:33 +0000600 AssignedPhysReg, VirtReg));
601 }
Evan Chenge077ef62006-11-04 00:21:55 +0000602
603 void markClobbered(unsigned PhysReg) {
Evan Cheng957840b2007-02-21 02:22:03 +0000604 PhysRegsClobbered.set(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000605 }
606
607 bool isClobbered(unsigned PhysReg) const {
Evan Cheng957840b2007-02-21 02:22:03 +0000608 return PhysRegsClobbered.test(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000609 }
Chris Lattner540fec62006-02-25 01:51:33 +0000610
611 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
612 /// is some other operand that is using the specified register, either pick
613 /// a new register to use, or evict the previous reload and use this reg.
614 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
615 AvailableSpills &Spills,
Evan Chengfff3e192007-08-14 09:11:18 +0000616 std::vector<MachineInstr*> &MaybeDeadStores,
Evan Cheng28bb4622007-07-11 19:17:18 +0000617 SmallSet<unsigned, 8> &Rejected,
618 BitVector &RegKills,
Evan Cheng549f27d32007-08-13 23:45:17 +0000619 std::vector<MachineOperand*> &KillOps,
620 VirtRegMap &VRM) {
Chris Lattner540fec62006-02-25 01:51:33 +0000621 if (Reuses.empty()) return PhysReg; // This is most often empty.
622
623 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
624 ReusedOp &Op = Reuses[ro];
625 // If we find some other reuse that was supposed to use this register
626 // exactly for its reload, we can change this reload to use ITS reload
Evan Cheng3c82cab2007-01-19 22:40:14 +0000627 // register. That is, unless its reload register has already been
628 // considered and subsequently rejected because it has also been reused
629 // by another operand.
630 if (Op.PhysRegReused == PhysReg &&
631 Rejected.count(Op.AssignedPhysReg) == 0) {
Chris Lattner540fec62006-02-25 01:51:33 +0000632 // Yup, use the reload register that we didn't use before.
Evan Cheng3c82cab2007-01-19 22:40:14 +0000633 unsigned NewReg = Op.AssignedPhysReg;
634 Rejected.insert(PhysReg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000635 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected,
Evan Cheng549f27d32007-08-13 23:45:17 +0000636 RegKills, KillOps, VRM);
Chris Lattner540fec62006-02-25 01:51:33 +0000637 } else {
638 // Otherwise, we might also have a problem if a previously reused
639 // value aliases the new register. If so, codegen the previous reload
640 // and use this one.
641 unsigned PRRU = Op.PhysRegReused;
642 const MRegisterInfo *MRI = Spills.getRegInfo();
643 if (MRI->areAliases(PRRU, PhysReg)) {
644 // Okay, we found out that an alias of a reused register
645 // was used. This isn't good because it means we have
646 // to undo a previous reuse.
647 MachineBasicBlock *MBB = MI->getParent();
648 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000649 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
650
651 // Copy Op out of the vector and remove it, we're going to insert an
652 // explicit load for it.
653 ReusedOp NewOp = Op;
654 Reuses.erase(Reuses.begin()+ro);
655
656 // Ok, we're going to try to reload the assigned physreg into the
657 // slot that we were supposed to in the first place. However, that
658 // register could hold a reuse. Check to see if it conflicts or
659 // would prefer us to use a different register.
660 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
Evan Cheng28bb4622007-07-11 19:17:18 +0000661 MI, Spills, MaybeDeadStores,
Evan Cheng549f27d32007-08-13 23:45:17 +0000662 Rejected, RegKills, KillOps, VRM);
Chris Lattner28bad082006-02-25 02:17:31 +0000663
Evan Cheng549f27d32007-08-13 23:45:17 +0000664 if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) {
665 MRI->reMaterialize(*MBB, MI, NewPhysReg,
666 VRM.getReMaterializedMI(NewOp.VirtReg));
667 ++NumReMats;
668 } else {
669 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
670 NewOp.StackSlotOrReMat, AliasRC);
Evan Chengfff3e192007-08-14 09:11:18 +0000671 // Any stores to this stack slot are not dead anymore.
672 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
Evan Cheng549f27d32007-08-13 23:45:17 +0000673 ++NumLoads;
674 }
Chris Lattner28bad082006-02-25 02:17:31 +0000675 Spills.ClobberPhysReg(NewPhysReg);
676 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000677
Chris Lattnere53f4a02006-05-04 17:52:23 +0000678 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000679
Evan Cheng549f27d32007-08-13 23:45:17 +0000680 Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000681 MachineBasicBlock::iterator MII = MI;
682 --MII;
683 UpdateKills(*MII, RegKills, KillOps);
684 DOUT << '\t' << *MII;
Chris Lattner540fec62006-02-25 01:51:33 +0000685
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000686 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000687 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000688
689 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000690 return PhysReg;
691 }
692 }
693 }
694 return PhysReg;
695 }
Evan Cheng3c82cab2007-01-19 22:40:14 +0000696
697 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
698 /// 'Rejected' set to remember which registers have been considered and
699 /// rejected for the reload. This avoids infinite looping in case like
700 /// this:
701 /// t1 := op t2, t3
702 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
703 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
704 /// t1 <- desires r1
705 /// sees r1 is taken by t2, tries t2's reload register r0
706 /// sees r0 is taken by t3, tries t3's reload register r1
707 /// sees r1 is taken by t2, tries t2's reload register r0 ...
708 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
709 AvailableSpills &Spills,
Evan Chengfff3e192007-08-14 09:11:18 +0000710 std::vector<MachineInstr*> &MaybeDeadStores,
Evan Cheng28bb4622007-07-11 19:17:18 +0000711 BitVector &RegKills,
Evan Cheng549f27d32007-08-13 23:45:17 +0000712 std::vector<MachineOperand*> &KillOps,
713 VirtRegMap &VRM) {
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000714 SmallSet<unsigned, 8> Rejected;
Evan Cheng28bb4622007-07-11 19:17:18 +0000715 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected,
Evan Cheng549f27d32007-08-13 23:45:17 +0000716 RegKills, KillOps, VRM);
Evan Cheng3c82cab2007-01-19 22:40:14 +0000717 }
Chris Lattner540fec62006-02-25 01:51:33 +0000718 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000719}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000720
Chris Lattner7fb64342004-10-01 19:04:51 +0000721
722/// rewriteMBB - Keep track of which spills are available even after the
723/// register allocator is done with them. If possible, avoid reloading vregs.
Evan Cheng549f27d32007-08-13 23:45:17 +0000724void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000725 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000726
Evan Chengfff3e192007-08-14 09:11:18 +0000727 MachineFunction &MF = *MBB.getParent();
728
Chris Lattner66cf80f2006-02-03 23:13:58 +0000729 // Spills - Keep track of which spilled values are available in physregs so
730 // that we can choose to reuse the physregs instead of emitting reloads.
731 AvailableSpills Spills(MRI, TII);
732
Chris Lattner52b25db2004-10-01 19:47:12 +0000733 // MaybeDeadStores - When we need to write a value back into a stack slot,
734 // keep track of the inserted store. If the stack slot value is never read
735 // (because the value was used from some available register, for example), and
736 // subsequently stored to, the original store is dead. This map keeps track
737 // of inserted stores that are not used. If we see a subsequent store to the
738 // same stack slot, the original store is deleted.
Evan Chengfff3e192007-08-14 09:11:18 +0000739 std::vector<MachineInstr*> MaybeDeadStores;
740 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL);
Chris Lattner52b25db2004-10-01 19:47:12 +0000741
Evan Chengb6ca4b32007-08-14 23:25:37 +0000742 // ReMatDefs - These are rematerializable def MIs which are not deleted.
743 SmallSet<MachineInstr*, 4> ReMatDefs;
744
Evan Cheng0c40d722007-07-11 05:28:39 +0000745 // Keep track of kill information.
746 BitVector RegKills(MRI->getNumRegs());
747 std::vector<MachineOperand*> KillOps;
748 KillOps.resize(MRI->getNumRegs(), NULL);
749
Chris Lattner7fb64342004-10-01 19:04:51 +0000750 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
751 MII != E; ) {
752 MachineInstr &MI = *MII;
753 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
Evan Cheng0c40d722007-07-11 05:28:39 +0000754 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
755
756 bool Erased = false;
757 bool BackTracked = false;
Chris Lattner7fb64342004-10-01 19:04:51 +0000758
Chris Lattner540fec62006-02-25 01:51:33 +0000759 /// ReusedOperands - Keep track of operand reuse in case we need to undo
760 /// reuse.
Evan Chenge077ef62006-11-04 00:21:55 +0000761 ReuseInfo ReusedOperands(MI, MRI);
762
763 // Loop over all of the implicit defs, clearing them from our available
764 // sets.
Evan Cheng86facc22006-12-15 06:41:01 +0000765 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
Evan Cheng0c40d722007-07-11 05:28:39 +0000766 if (TID->ImplicitDefs) {
767 const unsigned *ImpDef = TID->ImplicitDefs;
Evan Chenge077ef62006-11-04 00:21:55 +0000768 for ( ; *ImpDef; ++ImpDef) {
Evan Cheng6c087e52007-04-25 22:13:27 +0000769 MF.setPhysRegUsed(*ImpDef);
Evan Chenge077ef62006-11-04 00:21:55 +0000770 ReusedOperands.markClobbered(*ImpDef);
771 Spills.ClobberPhysReg(*ImpDef);
772 }
773 }
774
Chris Lattner7fb64342004-10-01 19:04:51 +0000775 // Process all of the spilled uses and all non spilled reg references.
776 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
777 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000778 if (!MO.isRegister() || MO.getReg() == 0)
779 continue; // Ignore non-register operands.
780
Evan Cheng32dfbea2007-10-12 08:50:34 +0000781 unsigned VirtReg = MO.getReg();
782 if (MRegisterInfo::isPhysicalRegister(VirtReg)) {
Chris Lattner50ea01e2005-09-09 20:29:51 +0000783 // Ignore physregs for spilling, but remember that it is used by this
784 // function.
Evan Cheng32dfbea2007-10-12 08:50:34 +0000785 MF.setPhysRegUsed(VirtReg);
786 ReusedOperands.markClobbered(VirtReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000787 continue;
788 }
789
Evan Cheng32dfbea2007-10-12 08:50:34 +0000790 assert(MRegisterInfo::isVirtualRegister(VirtReg) &&
Chris Lattner50ea01e2005-09-09 20:29:51 +0000791 "Not a virtual or a physical register?");
792
Evan Cheng32dfbea2007-10-12 08:50:34 +0000793 unsigned SubIdx = 0;
794 bool isSubReg = RegMap->isSubRegister(VirtReg);
795 if (isSubReg) {
796 SubIdx = RegMap->getSubRegisterIndex(VirtReg);
797 VirtReg = RegMap->getSuperRegister(VirtReg);
798 }
799
Evan Cheng549f27d32007-08-13 23:45:17 +0000800 if (VRM.isAssignedReg(VirtReg)) {
Chris Lattner50ea01e2005-09-09 20:29:51 +0000801 // This virtual register was assigned a physreg!
802 unsigned Phys = VRM.getPhys(VirtReg);
Evan Cheng6c087e52007-04-25 22:13:27 +0000803 MF.setPhysRegUsed(Phys);
Evan Chenge077ef62006-11-04 00:21:55 +0000804 if (MO.isDef())
805 ReusedOperands.markClobbered(Phys);
Evan Cheng32dfbea2007-10-12 08:50:34 +0000806 unsigned RReg = isSubReg ? MRI->getSubReg(Phys, SubIdx) : Phys;
807 MI.getOperand(i).setReg(RReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000808 continue;
809 }
810
811 // This virtual register is now known to be a spilled value.
812 if (!MO.isUse())
813 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000814
Evan Cheng549f27d32007-08-13 23:45:17 +0000815 bool DoReMat = VRM.isReMaterialized(VirtReg);
816 int SSorRMId = DoReMat
817 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
Evan Chengdc6be192007-08-14 05:42:54 +0000818 int ReuseSlot = SSorRMId;
Chris Lattner7fb64342004-10-01 19:04:51 +0000819
Chris Lattner50ea01e2005-09-09 20:29:51 +0000820 // Check to see if this stack slot is available.
Evan Chengdc6be192007-08-14 05:42:54 +0000821 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
822 if (!PhysReg && DoReMat) {
823 // This use is rematerializable. But perhaps the value is available in
824 // stack if the definition is not deleted. If so, check if we can
825 // reuse the value.
826 ReuseSlot = VRM.getStackSlot(VirtReg);
827 if (ReuseSlot != VirtRegMap::NO_STACK_SLOT)
828 PhysReg = Spills.getSpillSlotOrReMatPhysReg(ReuseSlot);
829 }
Evan Cheng32dfbea2007-10-12 08:50:34 +0000830
831 // If this is a sub-register use, make sure the reuse register is in the
832 // right register class. For example, for x86 not all of the 32-bit
833 // registers have accessible sub-registers.
834 // Similarly so for EXTRACT_SUBREG. Consider this:
835 // EDI = op
836 // MOV32_mr fi#1, EDI
837 // ...
838 // = EXTRACT_SUBREG fi#1
839 // fi#1 is available in EDI, but it cannot be reused because it's not in
840 // the right register file.
841 if (PhysReg &&
842 (isSubReg || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) {
843 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
844 if (!RC->contains(PhysReg))
845 PhysReg = 0;
846 }
847
Evan Chengdc6be192007-08-14 05:42:54 +0000848 if (PhysReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000849 // This spilled operand might be part of a two-address operand. If this
850 // is the case, then changing it will necessarily require changing the
851 // def part of the instruction as well. However, in some cases, we
852 // aren't allowed to modify the reused register. If none of these cases
853 // apply, reuse it.
854 bool CanReuse = true;
Evan Cheng32dfbea2007-10-12 08:50:34 +0000855
Evan Cheng86facc22006-12-15 06:41:01 +0000856 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000857 if (ti != -1 &&
Dan Gohman92dfe202007-09-14 20:33:02 +0000858 MI.getOperand(ti).isRegister() &&
Evan Cheng360c2dd2006-11-01 23:06:55 +0000859 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000860 // Okay, we have a two address operand. We can reuse this physreg as
Evan Cheng3c82cab2007-01-19 22:40:14 +0000861 // long as we are allowed to clobber the value and there isn't an
862 // earlier def that has already clobbered the physreg.
Evan Chengdc6be192007-08-14 05:42:54 +0000863 CanReuse = Spills.canClobberPhysReg(ReuseSlot) &&
Evan Chenge077ef62006-11-04 00:21:55 +0000864 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +0000865 }
866
867 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000868 // If this stack slot value is already available, reuse it!
Evan Chengdc6be192007-08-14 05:42:54 +0000869 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
870 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000871 else
Evan Chengdc6be192007-08-14 05:42:54 +0000872 DOUT << "Reusing SS#" << ReuseSlot;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000873 DOUT << " from physreg "
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000874 << MRI->getName(PhysReg) << " for vreg"
875 << VirtReg <<" instead of reloading into physreg "
876 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Evan Cheng32dfbea2007-10-12 08:50:34 +0000877 unsigned RReg = isSubReg ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
878 MI.getOperand(i).setReg(RReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000879
880 // The only technical detail we have is that we don't know that
881 // PhysReg won't be clobbered by a reloaded stack slot that occurs
882 // later in the instruction. In particular, consider 'op V1, V2'.
883 // If V1 is available in physreg R0, we would choose to reuse it
884 // here, instead of reloading it into the register the allocator
885 // indicated (say R1). However, V2 might have to be reloaded
886 // later, and it might indicate that it needs to live in R0. When
887 // this occurs, we need to have information available that
888 // indicates it is safe to use R1 for the reload instead of R0.
889 //
890 // To further complicate matters, we might conflict with an alias,
891 // or R0 and R1 might not be compatible with each other. In this
892 // case, we actually insert a reload for V1 in R1, ensuring that
893 // we can get at R0 or its alias.
Evan Chengdc6be192007-08-14 05:42:54 +0000894 ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
Chris Lattneraddc55a2006-04-28 01:46:50 +0000895 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000896 if (ti != -1)
897 // Only mark it clobbered if this is a use&def operand.
898 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000899 ++NumReused;
Evan Chengfff3e192007-08-14 09:11:18 +0000900
901 if (MI.getOperand(i).isKill() &&
902 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) {
903 // This was the last use and the spilled value is still available
904 // for reuse. That means the spill was unnecessary!
905 MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot];
906 if (DeadStore) {
907 DOUT << "Removed dead store:\t" << *DeadStore;
908 InvalidateKills(*DeadStore, RegKills, KillOps);
909 MBB.erase(DeadStore);
910 VRM.RemoveFromFoldedVirtMap(DeadStore);
911 MaybeDeadStores[ReuseSlot] = NULL;
912 ++NumDSE;
913 }
914 }
Chris Lattneraddc55a2006-04-28 01:46:50 +0000915 continue;
Evan Cheng32dfbea2007-10-12 08:50:34 +0000916 } // CanReuse
Chris Lattneraddc55a2006-04-28 01:46:50 +0000917
918 // Otherwise we have a situation where we have a two-address instruction
919 // whose mod/ref operand needs to be reloaded. This reload is already
920 // available in some register "PhysReg", but if we used PhysReg as the
921 // operand to our 2-addr instruction, the instruction would modify
922 // PhysReg. This isn't cool if something later uses PhysReg and expects
923 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000924 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000925 // To avoid this problem, and to avoid doing a load right after a store,
926 // we emit a copy from PhysReg into the designated register for this
927 // operand.
928 unsigned DesignatedReg = VRM.getPhys(VirtReg);
929 assert(DesignatedReg && "Must map virtreg to physreg!");
930
931 // Note that, if we reused a register for a previous operand, the
932 // register we want to reload into might not actually be
933 // available. If this occurs, use the register indicated by the
934 // reuser.
935 if (ReusedOperands.hasReuses())
936 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +0000937 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000938
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000939 // If the mapped designated register is actually the physreg we have
940 // incoming, we don't need to inserted a dead copy.
941 if (DesignatedReg == PhysReg) {
942 // If this stack slot value is already available, reuse it!
Evan Chengdc6be192007-08-14 05:42:54 +0000943 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
944 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000945 else
Evan Chengdc6be192007-08-14 05:42:54 +0000946 DOUT << "Reusing SS#" << ReuseSlot;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000947 DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg"
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000948 << VirtReg
949 << " instead of reloading into same physreg.\n";
Evan Cheng32dfbea2007-10-12 08:50:34 +0000950 unsigned RReg = isSubReg ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
951 MI.getOperand(i).setReg(RReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000952 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000953 ++NumReused;
954 continue;
955 }
956
Evan Cheng32dfbea2007-10-12 08:50:34 +0000957 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
Evan Cheng6c087e52007-04-25 22:13:27 +0000958 MF.setPhysRegUsed(DesignatedReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000959 ReusedOperands.markClobbered(DesignatedReg);
Evan Cheng9efce632007-09-26 06:25:56 +0000960 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC);
Evan Chengde4e9422007-02-25 09:51:27 +0000961
Evan Cheng6b448092007-03-02 08:52:00 +0000962 MachineInstr *CopyMI = prior(MII);
Evan Cheng0c40d722007-07-11 05:28:39 +0000963 UpdateKills(*CopyMI, RegKills, KillOps);
Evan Chengde4e9422007-02-25 09:51:27 +0000964
Chris Lattneraddc55a2006-04-28 01:46:50 +0000965 // This invalidates DesignatedReg.
966 Spills.ClobberPhysReg(DesignatedReg);
967
Evan Chengdc6be192007-08-14 05:42:54 +0000968 Spills.addAvailable(ReuseSlot, &MI, DesignatedReg);
Evan Cheng32dfbea2007-10-12 08:50:34 +0000969 unsigned RReg =
970 isSubReg ? MRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
971 MI.getOperand(i).setReg(RReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000972 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000973 ++NumReused;
974 continue;
Evan Cheng32dfbea2007-10-12 08:50:34 +0000975 } // is (PhysReg)
Chris Lattner50ea01e2005-09-09 20:29:51 +0000976
977 // Otherwise, reload it and remember that we have it.
978 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000979 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattner7fb64342004-10-01 19:04:51 +0000980
Chris Lattner50ea01e2005-09-09 20:29:51 +0000981 // Note that, if we reused a register for a previous operand, the
982 // register we want to reload into might not actually be
983 // available. If this occurs, use the register indicated by the
984 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000985 if (ReusedOperands.hasReuses())
986 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +0000987 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Chris Lattner540fec62006-02-25 01:51:33 +0000988
Evan Cheng6c087e52007-04-25 22:13:27 +0000989 MF.setPhysRegUsed(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000990 ReusedOperands.markClobbered(PhysReg);
Evan Cheng549f27d32007-08-13 23:45:17 +0000991 if (DoReMat) {
Evan Cheng2638e1a2007-03-20 08:13:50 +0000992 MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
Evan Cheng91935142007-04-04 07:40:01 +0000993 ++NumReMats;
994 } else {
Evan Cheng32dfbea2007-10-12 08:50:34 +0000995 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
Evan Cheng549f27d32007-08-13 23:45:17 +0000996 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
Evan Cheng91935142007-04-04 07:40:01 +0000997 ++NumLoads;
998 }
Chris Lattner50ea01e2005-09-09 20:29:51 +0000999 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +00001000 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +00001001
1002 // Any stores to this stack slot are not dead anymore.
Evan Cheng549f27d32007-08-13 23:45:17 +00001003 if (!DoReMat)
Evan Chengfff3e192007-08-14 09:11:18 +00001004 MaybeDeadStores[SSorRMId] = NULL;
Evan Cheng549f27d32007-08-13 23:45:17 +00001005 Spills.addAvailable(SSorRMId, &MI, PhysReg);
Evan Chengde4e9422007-02-25 09:51:27 +00001006 // Assumes this is the last use. IsKill will be unset if reg is reused
1007 // unless it's a two-address operand.
1008 if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
1009 MI.getOperand(i).setIsKill();
Evan Cheng32dfbea2007-10-12 08:50:34 +00001010 unsigned RReg = isSubReg ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
1011 MI.getOperand(i).setReg(RReg);
Evan Cheng0c40d722007-07-11 05:28:39 +00001012 UpdateKills(*prior(MII), RegKills, KillOps);
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001013 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001014 }
1015
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001016 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001017
Chris Lattner7fb64342004-10-01 19:04:51 +00001018 // If we have folded references to memory operands, make sure we clear all
1019 // physical registers that may contain the value of the spilled virtual
1020 // register
Evan Cheng90a43c32007-08-15 20:20:34 +00001021 SmallSet<int, 1> FoldedSS;
Chris Lattner8f1d6402005-01-14 15:54:24 +00001022 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001023 DOUT << "Folded vreg: " << I->second.first << " MR: "
1024 << I->second.second;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +00001025 unsigned VirtReg = I->second.first;
1026 VirtRegMap::ModRef MR = I->second.second;
Evan Cheng549f27d32007-08-13 23:45:17 +00001027 if (VRM.isAssignedReg(VirtReg)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001028 DOUT << ": No stack slot!\n";
Chris Lattnercea86882005-09-19 06:56:21 +00001029 continue;
1030 }
1031 int SS = VRM.getStackSlot(VirtReg);
Evan Cheng90a43c32007-08-15 20:20:34 +00001032 FoldedSS.insert(SS);
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001033 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +00001034
1035 // If this folded instruction is just a use, check to see if it's a
1036 // straight load from the virt reg slot.
1037 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
1038 int FrameIdx;
Evan Cheng32dfbea2007-10-12 08:50:34 +00001039 unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx);
1040 if (DestReg && FrameIdx == SS) {
1041 // If this spill slot is available, turn it into a copy (or nothing)
1042 // instead of leaving it as a load!
1043 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
1044 DOUT << "Promoted Load To Copy: " << MI;
1045 if (DestReg != InReg) {
1046 const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg);
1047 MRI->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
1048 // Revisit the copy so we make sure to notice the effects of the
1049 // operation on the destreg (either needing to RA it if it's
1050 // virtual or needing to clobber any values if it's physical).
1051 NextMII = &MI;
1052 --NextMII; // backtrack to the copy.
1053 BackTracked = true;
1054 } else
1055 DOUT << "Removing now-noop copy: " << MI;
Evan Chengde4e9422007-02-25 09:51:27 +00001056
Evan Cheng32dfbea2007-10-12 08:50:34 +00001057 VRM.RemoveFromFoldedVirtMap(&MI);
1058 MBB.erase(&MI);
1059 Erased = true;
1060 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +00001061 }
1062 }
1063 }
1064
1065 // If this reference is not a use, any previous store is now dead.
1066 // Otherwise, the store to this stack slot is not dead anymore.
Evan Chengfff3e192007-08-14 09:11:18 +00001067 MachineInstr* DeadStore = MaybeDeadStores[SS];
1068 if (DeadStore) {
1069 if (!(MR & VirtRegMap::isRef)) { // Previous store is dead.
Chris Lattnercea86882005-09-19 06:56:21 +00001070 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +00001071 assert(VirtRegMap::isMod && "Can't be modref!");
Evan Chengfff3e192007-08-14 09:11:18 +00001072 DOUT << "Removed dead store:\t" << *DeadStore;
1073 InvalidateKills(*DeadStore, RegKills, KillOps);
1074 MBB.erase(DeadStore);
1075 VRM.RemoveFromFoldedVirtMap(DeadStore);
Chris Lattner35f27052006-05-01 21:16:03 +00001076 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +00001077 }
Evan Chengfff3e192007-08-14 09:11:18 +00001078 MaybeDeadStores[SS] = NULL;
Chris Lattnercea86882005-09-19 06:56:21 +00001079 }
1080
1081 // If the spill slot value is available, and this is a new definition of
1082 // the value, the value is not available anymore.
1083 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +00001084 // Notice that the value in this stack slot has been modified.
Evan Cheng549f27d32007-08-13 23:45:17 +00001085 Spills.ModifyStackSlotOrReMat(SS);
Chris Lattnercd816392006-02-02 23:29:36 +00001086
1087 // If this is *just* a mod of the value, check to see if this is just a
1088 // store to the spill slot (i.e. the spill got merged into the copy). If
1089 // so, realize that the vreg is available now, and add the store to the
1090 // MaybeDeadStore info.
1091 int StackSlot;
1092 if (!(MR & VirtRegMap::isRef)) {
1093 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
1094 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
1095 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +00001096 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +00001097 // this as a potentially dead store in case there is a subsequent
1098 // store into the stack slot without a read from it.
1099 MaybeDeadStores[StackSlot] = &MI;
1100
Chris Lattnercd816392006-02-02 23:29:36 +00001101 // If the stack slot value was previously available in some other
1102 // register, change it now. Otherwise, make the register available,
1103 // in PhysReg.
Evan Cheng91e23902007-02-23 01:13:26 +00001104 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +00001105 }
1106 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001107 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001108 }
1109
Chris Lattner7fb64342004-10-01 19:04:51 +00001110 // Process all of the spilled defs.
1111 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1112 MachineOperand &MO = MI.getOperand(i);
1113 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
1114 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001115
Chris Lattner7fb64342004-10-01 19:04:51 +00001116 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +00001117 // Check to see if this is a noop copy. If so, eliminate the
1118 // instruction before considering the dest reg to be changed.
1119 unsigned Src, Dst;
1120 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1121 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001122 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner29268692006-09-05 02:12:02 +00001123 MBB.erase(&MI);
Evan Cheng0c40d722007-07-11 05:28:39 +00001124 Erased = true;
Chris Lattner29268692006-09-05 02:12:02 +00001125 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng7a0d51c2006-12-14 07:54:05 +00001126 Spills.disallowClobberPhysReg(VirtReg);
Chris Lattner29268692006-09-05 02:12:02 +00001127 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +00001128 }
Chris Lattner6ec36262006-10-12 17:45:38 +00001129
1130 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +00001131 Spills.ClobberPhysReg(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001132 ReusedOperands.markClobbered(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +00001133
1134 // Check to see if this instruction is a load from a stack slot into
1135 // a register. If so, this provides the stack slot value in the reg.
1136 int FrameIdx;
1137 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
1138 assert(DestReg == VirtReg && "Unknown load situation!");
Evan Cheng90a43c32007-08-15 20:20:34 +00001139
1140 // If it is a folded reference, then it's not safe to clobber.
1141 bool Folded = FoldedSS.count(FrameIdx);
Chris Lattner6ec36262006-10-12 17:45:38 +00001142 // Otherwise, if it wasn't available, remember that it is now!
Evan Cheng90a43c32007-08-15 20:20:34 +00001143 Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded);
Chris Lattner6ec36262006-10-12 17:45:38 +00001144 goto ProcessNextInst;
1145 }
1146
Chris Lattner29268692006-09-05 02:12:02 +00001147 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +00001148 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001149
Evan Chengb6ca4b32007-08-14 23:25:37 +00001150 bool DoReMat = VRM.isReMaterialized(VirtReg);
1151 if (DoReMat)
1152 ReMatDefs.insert(&MI);
1153
Chris Lattner84e752a2006-02-03 03:06:49 +00001154 // The only vregs left are stack slot definitions.
1155 int StackSlot = VRM.getStackSlot(VirtReg);
Evan Cheng32dfbea2007-10-12 08:50:34 +00001156 const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001157
Chris Lattner29268692006-09-05 02:12:02 +00001158 // If this def is part of a two-address operand, make sure to execute
1159 // the store from the correct physical register.
1160 unsigned PhysReg;
Evan Chengcc22a7a2006-12-08 18:45:48 +00001161 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
Evan Cheng360c2dd2006-11-01 23:06:55 +00001162 if (TiedOp != -1)
1163 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chenge077ef62006-11-04 00:21:55 +00001164 else {
Chris Lattner29268692006-09-05 02:12:02 +00001165 PhysReg = VRM.getPhys(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001166 if (ReusedOperands.isClobbered(PhysReg)) {
1167 // Another def has taken the assigned physreg. It must have been a
1168 // use&def which got it due to reuse. Undo the reuse!
1169 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +00001170 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Evan Chenge077ef62006-11-04 00:21:55 +00001171 }
1172 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001173
Evan Cheng6c087e52007-04-25 22:13:27 +00001174 MF.setPhysRegUsed(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001175 ReusedOperands.markClobbered(PhysReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +00001176 MI.getOperand(i).setReg(PhysReg);
Evan Chengb6ca4b32007-08-14 23:25:37 +00001177 if (!MO.isDead()) {
1178 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
1179 DOUT << "Store:\t" << *next(MII);
Chris Lattner7fb64342004-10-01 19:04:51 +00001180
Evan Chengb6ca4b32007-08-14 23:25:37 +00001181 // If there is a dead store to this stack slot, nuke it now.
1182 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
1183 if (LastStore) {
1184 DOUT << "Removed dead store:\t" << *LastStore;
1185 ++NumDSE;
1186 SmallVector<unsigned, 1> KillRegs;
1187 InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs);
1188 MachineBasicBlock::iterator PrevMII = LastStore;
1189 bool CheckDef = PrevMII != MBB.begin();
1190 if (CheckDef)
1191 --PrevMII;
1192 MBB.erase(LastStore);
1193 VRM.RemoveFromFoldedVirtMap(LastStore);
1194 if (CheckDef) {
1195 // Look at defs of killed registers on the store. Mark the defs
1196 // as dead since the store has been deleted and they aren't
1197 // being reused.
1198 for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) {
1199 bool HasOtherDef = false;
1200 if (InvalidateRegDef(PrevMII, MI, KillRegs[j], HasOtherDef)) {
1201 MachineInstr *DeadDef = PrevMII;
1202 if (ReMatDefs.count(DeadDef) && !HasOtherDef) {
1203 // FIXME: This assumes a remat def does not have side
1204 // effects.
1205 MBB.erase(DeadDef);
1206 VRM.RemoveFromFoldedVirtMap(DeadDef);
1207 ++NumDRM;
1208 }
1209 }
1210 }
1211 }
Evan Chengf50d09a2007-02-08 06:04:54 +00001212 }
Evan Chengb6ca4b32007-08-14 23:25:37 +00001213 LastStore = next(MII);
1214
1215 // If the stack slot value was previously available in some other
1216 // register, change it now. Otherwise, make the register available,
1217 // in PhysReg.
1218 Spills.ModifyStackSlotOrReMat(StackSlot);
1219 Spills.ClobberPhysReg(PhysReg);
1220 Spills.addAvailable(StackSlot, LastStore, PhysReg);
1221 ++NumStores;
1222
1223 // Check to see if this is a noop copy. If so, eliminate the
1224 // instruction before considering the dest reg to be changed.
1225 {
1226 unsigned Src, Dst;
1227 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1228 ++NumDCE;
1229 DOUT << "Removing now-noop copy: " << MI;
1230 MBB.erase(&MI);
1231 Erased = true;
1232 VRM.RemoveFromFoldedVirtMap(&MI);
1233 UpdateKills(*LastStore, RegKills, KillOps);
1234 goto ProcessNextInst;
1235 }
1236 }
1237 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001238 }
1239 }
Chris Lattnercea86882005-09-19 06:56:21 +00001240 ProcessNextInst:
Evan Cheng0c40d722007-07-11 05:28:39 +00001241 if (!Erased && !BackTracked)
1242 for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II)
1243 UpdateKills(*II, RegKills, KillOps);
Chris Lattner7fb64342004-10-01 19:04:51 +00001244 MII = NextMII;
1245 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001246}
1247
Chris Lattnerf7da2c72006-08-24 22:43:55 +00001248
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001249llvm::Spiller* llvm::createSpiller() {
1250 switch (SpillerOpt) {
1251 default: assert(0 && "Unreachable!");
1252 case local:
1253 return new LocalSpiller();
1254 case simple:
1255 return new SimpleSpiller();
1256 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +00001257}