Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 1 | //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by Chris Lattner and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 10 | // This file implements the PPCISelLowering class. |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Chris Lattner | 16e71f2 | 2005-10-14 23:59:06 +0000 | [diff] [blame] | 14 | #include "PPCISelLowering.h" |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 15 | #include "PPCMachineFunctionInfo.h" |
Chris Lattner | df4ed63 | 2006-11-17 22:10:59 +0000 | [diff] [blame] | 16 | #include "PPCPredicates.h" |
Chris Lattner | 16e71f2 | 2005-10-14 23:59:06 +0000 | [diff] [blame] | 17 | #include "PPCTargetMachine.h" |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 18 | #include "PPCPerfectShuffle.h" |
Owen Anderson | 718cb66 | 2007-09-07 04:06:50 +0000 | [diff] [blame] | 19 | #include "llvm/ADT/STLExtras.h" |
Nate Begeman | 750ac1b | 2006-02-01 07:19:44 +0000 | [diff] [blame] | 20 | #include "llvm/ADT/VectorExtras.h" |
Evan Cheng | c4c6257 | 2006-03-13 23:20:37 +0000 | [diff] [blame] | 21 | #include "llvm/Analysis/ScalarEvolutionExpressions.h" |
Chris Lattner | b9a7bea | 2007-03-06 00:59:59 +0000 | [diff] [blame] | 22 | #include "llvm/CodeGen/CallingConvLower.h" |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 24 | #include "llvm/CodeGen/MachineFunction.h" |
Chris Lattner | 8a2d3ca | 2005-08-26 21:23:58 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 26 | #include "llvm/CodeGen/SelectionDAG.h" |
Chris Lattner | 7b73834 | 2005-09-13 19:33:40 +0000 | [diff] [blame] | 27 | #include "llvm/CodeGen/SSARegMap.h" |
Chris Lattner | 0b1e4e5 | 2005-08-26 17:36:52 +0000 | [diff] [blame] | 28 | #include "llvm/Constants.h" |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 29 | #include "llvm/Function.h" |
Chris Lattner | 6d92cad | 2006-03-26 10:06:40 +0000 | [diff] [blame] | 30 | #include "llvm/Intrinsics.h" |
Nate Begeman | 750ac1b | 2006-02-01 07:19:44 +0000 | [diff] [blame] | 31 | #include "llvm/Support/MathExtras.h" |
Evan Cheng | d2ee218 | 2006-02-18 00:08:58 +0000 | [diff] [blame] | 32 | #include "llvm/Target/TargetOptions.h" |
Chris Lattner | 4eab714 | 2006-11-10 02:08:47 +0000 | [diff] [blame] | 33 | #include "llvm/Support/CommandLine.h" |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 34 | using namespace llvm; |
| 35 | |
Chris Lattner | 3ee7740 | 2007-06-19 05:46:06 +0000 | [diff] [blame] | 36 | static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", |
| 37 | cl::desc("enable preincrement load/store generation on PPC (experimental)"), |
| 38 | cl::Hidden); |
Chris Lattner | 4eab714 | 2006-11-10 02:08:47 +0000 | [diff] [blame] | 39 | |
Chris Lattner | 331d1bc | 2006-11-02 01:44:04 +0000 | [diff] [blame] | 40 | PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) |
| 41 | : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 42 | |
Nate Begeman | 405e3ec | 2005-10-21 00:02:42 +0000 | [diff] [blame] | 43 | setPow2DivIsCheap(); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 44 | |
Chris Lattner | d145a61 | 2005-09-27 22:18:25 +0000 | [diff] [blame] | 45 | // Use _setjmp/_longjmp instead of setjmp/longjmp. |
Anton Korobeynikov | d27a258 | 2006-12-10 23:12:42 +0000 | [diff] [blame] | 46 | setUseUnderscoreSetJmp(true); |
| 47 | setUseUnderscoreLongJmp(true); |
Chris Lattner | d145a61 | 2005-09-27 22:18:25 +0000 | [diff] [blame] | 48 | |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 49 | // Set up the register classes. |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 50 | addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); |
| 51 | addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); |
| 52 | addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 53 | |
Evan Cheng | c548428 | 2006-10-04 00:56:09 +0000 | [diff] [blame] | 54 | // PowerPC has an i16 but no i8 (or i1) SEXTLOAD |
| 55 | setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); |
| 56 | setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); |
| 57 | |
Evan Cheng | 8b2794a | 2006-10-13 21:14:26 +0000 | [diff] [blame] | 58 | // PowerPC does not have truncstore for i1. |
| 59 | setStoreXAction(MVT::i1, Promote); |
| 60 | |
Chris Lattner | 94e509c | 2006-11-10 23:58:45 +0000 | [diff] [blame] | 61 | // PowerPC has pre-inc load and store's. |
| 62 | setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); |
| 63 | setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); |
| 64 | setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); |
Evan Cheng | cd63319 | 2006-11-09 19:11:50 +0000 | [diff] [blame] | 65 | setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); |
| 66 | setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); |
Chris Lattner | 94e509c | 2006-11-10 23:58:45 +0000 | [diff] [blame] | 67 | setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); |
| 68 | setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); |
| 69 | setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); |
Evan Cheng | cd63319 | 2006-11-09 19:11:50 +0000 | [diff] [blame] | 70 | setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); |
| 71 | setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); |
| 72 | |
Chris Lattner | a54aa94 | 2006-01-29 06:26:08 +0000 | [diff] [blame] | 73 | setOperationAction(ISD::ConstantFP, MVT::f64, Expand); |
| 74 | setOperationAction(ISD::ConstantFP, MVT::f32, Expand); |
| 75 | |
Dale Johannesen | 638ccd5 | 2007-10-06 01:24:11 +0000 | [diff] [blame] | 76 | // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg) |
| 77 | setConvertAction(MVT::ppcf128, MVT::f64, Expand); |
| 78 | setConvertAction(MVT::ppcf128, MVT::f32, Expand); |
Dale Johannesen | 6eaeff2 | 2007-10-10 01:01:31 +0000 | [diff] [blame] | 79 | // This is used in the ppcf128->int sequence. Note it has different semantics |
| 80 | // from FP_ROUND: that rounds to nearest, this rounds to zero. |
| 81 | setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); |
Dale Johannesen | 638ccd5 | 2007-10-06 01:24:11 +0000 | [diff] [blame] | 82 | |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 83 | // PowerPC has no intrinsics for these particular operations |
| 84 | setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); |
| 85 | setOperationAction(ISD::MEMSET, MVT::Other, Expand); |
| 86 | setOperationAction(ISD::MEMCPY, MVT::Other, Expand); |
| 87 | |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 88 | // PowerPC has no SREM/UREM instructions |
| 89 | setOperationAction(ISD::SREM, MVT::i32, Expand); |
| 90 | setOperationAction(ISD::UREM, MVT::i32, Expand); |
Chris Lattner | 563ecfb | 2006-06-27 18:18:41 +0000 | [diff] [blame] | 91 | setOperationAction(ISD::SREM, MVT::i64, Expand); |
| 92 | setOperationAction(ISD::UREM, MVT::i64, Expand); |
Dan Gohman | 3ce990d | 2007-10-08 17:28:24 +0000 | [diff] [blame] | 93 | |
| 94 | // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. |
| 95 | setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); |
| 96 | setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); |
| 97 | setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); |
| 98 | setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); |
| 99 | setOperationAction(ISD::UDIVREM, MVT::i32, Expand); |
| 100 | setOperationAction(ISD::SDIVREM, MVT::i32, Expand); |
| 101 | setOperationAction(ISD::UDIVREM, MVT::i64, Expand); |
| 102 | setOperationAction(ISD::SDIVREM, MVT::i64, Expand); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 103 | |
Dan Gohman | f96e4de | 2007-10-11 23:21:31 +0000 | [diff] [blame] | 104 | // We don't support sin/cos/sqrt/fmod/pow |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 105 | setOperationAction(ISD::FSIN , MVT::f64, Expand); |
| 106 | setOperationAction(ISD::FCOS , MVT::f64, Expand); |
Chris Lattner | 615c2d0 | 2005-09-28 22:29:58 +0000 | [diff] [blame] | 107 | setOperationAction(ISD::FREM , MVT::f64, Expand); |
Dan Gohman | f96e4de | 2007-10-11 23:21:31 +0000 | [diff] [blame] | 108 | setOperationAction(ISD::FPOW , MVT::f64, Expand); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 109 | setOperationAction(ISD::FSIN , MVT::f32, Expand); |
| 110 | setOperationAction(ISD::FCOS , MVT::f32, Expand); |
Chris Lattner | 615c2d0 | 2005-09-28 22:29:58 +0000 | [diff] [blame] | 111 | setOperationAction(ISD::FREM , MVT::f32, Expand); |
Dan Gohman | f96e4de | 2007-10-11 23:21:31 +0000 | [diff] [blame] | 112 | setOperationAction(ISD::FPOW , MVT::f32, Expand); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 113 | |
| 114 | // If we're enabling GP optimizations, use hardware square root |
Chris Lattner | 1e9de3e | 2005-09-02 18:33:05 +0000 | [diff] [blame] | 115 | if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 116 | setOperationAction(ISD::FSQRT, MVT::f64, Expand); |
| 117 | setOperationAction(ISD::FSQRT, MVT::f32, Expand); |
| 118 | } |
| 119 | |
Chris Lattner | 9601a86 | 2006-03-05 05:08:37 +0000 | [diff] [blame] | 120 | setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); |
| 121 | setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); |
| 122 | |
Nate Begeman | d88fc03 | 2006-01-14 03:14:10 +0000 | [diff] [blame] | 123 | // PowerPC does not have BSWAP, CTPOP or CTTZ |
| 124 | setOperationAction(ISD::BSWAP, MVT::i32 , Expand); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 125 | setOperationAction(ISD::CTPOP, MVT::i32 , Expand); |
| 126 | setOperationAction(ISD::CTTZ , MVT::i32 , Expand); |
Chris Lattner | f89437d | 2006-06-27 20:14:52 +0000 | [diff] [blame] | 127 | setOperationAction(ISD::BSWAP, MVT::i64 , Expand); |
| 128 | setOperationAction(ISD::CTPOP, MVT::i64 , Expand); |
| 129 | setOperationAction(ISD::CTTZ , MVT::i64 , Expand); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 130 | |
Nate Begeman | 35ef913 | 2006-01-11 21:21:00 +0000 | [diff] [blame] | 131 | // PowerPC does not have ROTR |
| 132 | setOperationAction(ISD::ROTR, MVT::i32 , Expand); |
| 133 | |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 134 | // PowerPC does not have Select |
| 135 | setOperationAction(ISD::SELECT, MVT::i32, Expand); |
Chris Lattner | f89437d | 2006-06-27 20:14:52 +0000 | [diff] [blame] | 136 | setOperationAction(ISD::SELECT, MVT::i64, Expand); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 137 | setOperationAction(ISD::SELECT, MVT::f32, Expand); |
| 138 | setOperationAction(ISD::SELECT, MVT::f64, Expand); |
Chris Lattner | e4bc9ea | 2005-08-26 00:52:45 +0000 | [diff] [blame] | 139 | |
Chris Lattner | 0b1e4e5 | 2005-08-26 17:36:52 +0000 | [diff] [blame] | 140 | // PowerPC wants to turn select_cc of FP into fsel when possible. |
| 141 | setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); |
| 142 | setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); |
Nate Begeman | 4477590 | 2006-01-31 08:17:29 +0000 | [diff] [blame] | 143 | |
Nate Begeman | 750ac1b | 2006-02-01 07:19:44 +0000 | [diff] [blame] | 144 | // PowerPC wants to optimize integer setcc a bit |
Nate Begeman | 4477590 | 2006-01-31 08:17:29 +0000 | [diff] [blame] | 145 | setOperationAction(ISD::SETCC, MVT::i32, Custom); |
Chris Lattner | eb9b62e | 2005-08-31 19:09:57 +0000 | [diff] [blame] | 146 | |
Nate Begeman | 81e8097 | 2006-03-17 01:40:33 +0000 | [diff] [blame] | 147 | // PowerPC does not have BRCOND which requires SetCC |
| 148 | setOperationAction(ISD::BRCOND, MVT::Other, Expand); |
Evan Cheng | c35497f | 2006-10-30 08:02:39 +0000 | [diff] [blame] | 149 | |
| 150 | setOperationAction(ISD::BR_JT, MVT::Other, Expand); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 151 | |
Chris Lattner | f760532 | 2005-08-31 21:09:52 +0000 | [diff] [blame] | 152 | // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. |
| 153 | setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); |
Nate Begeman | c09eeec | 2005-09-06 22:03:27 +0000 | [diff] [blame] | 154 | |
Jim Laskey | ad23c9d | 2005-08-17 00:40:22 +0000 | [diff] [blame] | 155 | // PowerPC does not have [U|S]INT_TO_FP |
| 156 | setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); |
| 157 | setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); |
| 158 | |
Chris Lattner | 53e8845 | 2005-12-23 05:13:35 +0000 | [diff] [blame] | 159 | setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); |
| 160 | setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); |
Chris Lattner | 5f9faea | 2006-06-27 18:40:08 +0000 | [diff] [blame] | 161 | setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); |
| 162 | setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); |
Chris Lattner | 53e8845 | 2005-12-23 05:13:35 +0000 | [diff] [blame] | 163 | |
Chris Lattner | 25b8b8c | 2006-04-28 21:56:10 +0000 | [diff] [blame] | 164 | // We cannot sextinreg(i1). Expand to shifts. |
| 165 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); |
Jim Laskey | 2ad9f17 | 2007-02-22 14:56:36 +0000 | [diff] [blame] | 166 | |
Jim Laskey | abf6d17 | 2006-01-05 01:25:28 +0000 | [diff] [blame] | 167 | // Support label based line numbers. |
Chris Lattner | f73bae1 | 2005-11-29 06:16:21 +0000 | [diff] [blame] | 168 | setOperationAction(ISD::LOCATION, MVT::Other, Expand); |
Jim Laskey | e0bce71 | 2006-01-05 01:47:43 +0000 | [diff] [blame] | 169 | setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); |
Jim Laskey | 2ad9f17 | 2007-02-22 14:56:36 +0000 | [diff] [blame] | 170 | if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) { |
Jim Laskey | 1ee2925 | 2007-01-26 14:34:52 +0000 | [diff] [blame] | 171 | setOperationAction(ISD::LABEL, MVT::Other, Expand); |
Jim Laskey | 2ad9f17 | 2007-02-22 14:56:36 +0000 | [diff] [blame] | 172 | } else { |
| 173 | setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); |
| 174 | setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); |
| 175 | setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); |
| 176 | setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); |
| 177 | } |
Chris Lattner | e6ec9f2 | 2005-09-10 00:21:06 +0000 | [diff] [blame] | 178 | |
Nate Begeman | 28a6b02 | 2005-12-10 02:36:00 +0000 | [diff] [blame] | 179 | // We want to legalize GlobalAddress and ConstantPool nodes into the |
| 180 | // appropriate instructions to materialize the address. |
Chris Lattner | 3eef4e3 | 2005-11-17 18:26:56 +0000 | [diff] [blame] | 181 | setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); |
Lauro Ramos Venancio | 75ce010 | 2007-07-11 17:19:51 +0000 | [diff] [blame] | 182 | setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); |
Nate Begeman | 28a6b02 | 2005-12-10 02:36:00 +0000 | [diff] [blame] | 183 | setOperationAction(ISD::ConstantPool, MVT::i32, Custom); |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 184 | setOperationAction(ISD::JumpTable, MVT::i32, Custom); |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 185 | setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); |
Lauro Ramos Venancio | 75ce010 | 2007-07-11 17:19:51 +0000 | [diff] [blame] | 186 | setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 187 | setOperationAction(ISD::ConstantPool, MVT::i64, Custom); |
| 188 | setOperationAction(ISD::JumpTable, MVT::i64, Custom); |
| 189 | |
Nate Begeman | ee62557 | 2006-01-27 21:09:22 +0000 | [diff] [blame] | 190 | // RET must be custom lowered, to meet ABI requirements |
| 191 | setOperationAction(ISD::RET , MVT::Other, Custom); |
Duncan Sands | 36397f5 | 2007-07-27 12:58:54 +0000 | [diff] [blame] | 192 | |
Nate Begeman | acc398c | 2006-01-25 18:21:52 +0000 | [diff] [blame] | 193 | // VASTART needs to be custom lowered to use the VarArgsFrameIndex |
| 194 | setOperationAction(ISD::VASTART , MVT::Other, Custom); |
| 195 | |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 196 | // VAARG is custom lowered with ELF 32 ABI |
| 197 | if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI()) |
| 198 | setOperationAction(ISD::VAARG, MVT::Other, Custom); |
| 199 | else |
| 200 | setOperationAction(ISD::VAARG, MVT::Other, Expand); |
| 201 | |
Chris Lattner | b22c08b | 2006-01-15 09:02:48 +0000 | [diff] [blame] | 202 | // Use the default implementation. |
Nate Begeman | acc398c | 2006-01-25 18:21:52 +0000 | [diff] [blame] | 203 | setOperationAction(ISD::VACOPY , MVT::Other, Expand); |
| 204 | setOperationAction(ISD::VAEND , MVT::Other, Expand); |
Chris Lattner | b22c08b | 2006-01-15 09:02:48 +0000 | [diff] [blame] | 205 | setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); |
Jim Laskey | efc7e52 | 2006-12-04 22:04:42 +0000 | [diff] [blame] | 206 | setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 207 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); |
| 208 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); |
Chris Lattner | 56a752e | 2006-10-18 01:18:48 +0000 | [diff] [blame] | 209 | |
Chris Lattner | 6d92cad | 2006-03-26 10:06:40 +0000 | [diff] [blame] | 210 | // We want to custom lower some of our intrinsics. |
Chris Lattner | 48b61a7 | 2006-03-28 00:40:33 +0000 | [diff] [blame] | 211 | setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); |
Chris Lattner | 6d92cad | 2006-03-26 10:06:40 +0000 | [diff] [blame] | 212 | |
Chris Lattner | a7a5854 | 2006-06-16 17:34:12 +0000 | [diff] [blame] | 213 | if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 214 | // They also have instructions for converting between i64 and fp. |
Nate Begeman | c09eeec | 2005-09-06 22:03:27 +0000 | [diff] [blame] | 215 | setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); |
Jim Laskey | ca367b4 | 2006-12-15 14:32:57 +0000 | [diff] [blame] | 216 | setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); |
Nate Begeman | c09eeec | 2005-09-06 22:03:27 +0000 | [diff] [blame] | 217 | setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); |
Chris Lattner | 85c671b | 2006-12-07 01:24:16 +0000 | [diff] [blame] | 218 | setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); |
Jim Laskey | ca367b4 | 2006-12-15 14:32:57 +0000 | [diff] [blame] | 219 | setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); |
| 220 | |
Chris Lattner | 7fbcef7 | 2006-03-24 07:53:47 +0000 | [diff] [blame] | 221 | // FIXME: disable this lowered code. This generates 64-bit register values, |
| 222 | // and we don't model the fact that the top part is clobbered by calls. We |
| 223 | // need to flag these together so that the value isn't live across a call. |
| 224 | //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); |
| 225 | |
Nate Begeman | ae749a9 | 2005-10-25 23:48:36 +0000 | [diff] [blame] | 226 | // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT |
| 227 | setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); |
| 228 | } else { |
Chris Lattner | 860e886 | 2005-11-17 07:30:41 +0000 | [diff] [blame] | 229 | // PowerPC does not have FP_TO_UINT on 32-bit implementations. |
Nate Begeman | ae749a9 | 2005-10-25 23:48:36 +0000 | [diff] [blame] | 230 | setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); |
Nate Begeman | 9d2b817 | 2005-10-18 00:56:42 +0000 | [diff] [blame] | 231 | } |
| 232 | |
Chris Lattner | a7a5854 | 2006-06-16 17:34:12 +0000 | [diff] [blame] | 233 | if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { |
Chris Lattner | 26cb286 | 2007-10-19 04:08:28 +0000 | [diff] [blame] | 234 | // 64-bit PowerPC implementations can support i64 types directly |
Nate Begeman | 9d2b817 | 2005-10-18 00:56:42 +0000 | [diff] [blame] | 235 | addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 236 | // BUILD_PAIR can't be handled natively, and should be expanded to shl/or |
| 237 | setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 238 | } else { |
Chris Lattner | 26cb286 | 2007-10-19 04:08:28 +0000 | [diff] [blame] | 239 | // 32-bit PowerPC wants to expand i64 shifts itself. |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 240 | setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); |
| 241 | setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); |
| 242 | setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); |
Nate Begeman | c09eeec | 2005-09-06 22:03:27 +0000 | [diff] [blame] | 243 | } |
Evan Cheng | d30bf01 | 2006-03-01 01:11:20 +0000 | [diff] [blame] | 244 | |
Nate Begeman | 425a969 | 2005-11-29 08:17:20 +0000 | [diff] [blame] | 245 | if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { |
Chris Lattner | e3fea5a | 2006-03-31 19:52:36 +0000 | [diff] [blame] | 246 | // First set operation action for all vector types to expand. Then we |
| 247 | // will selectively turn on ones that can be effectively codegen'd. |
| 248 | for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; |
Dan Gohman | f5135be | 2007-05-18 23:21:46 +0000 | [diff] [blame] | 249 | VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { |
Chris Lattner | f3f69de | 2006-04-16 01:37:57 +0000 | [diff] [blame] | 250 | // add/sub are legal for all supported vector VT's. |
Chris Lattner | e3fea5a | 2006-03-31 19:52:36 +0000 | [diff] [blame] | 251 | setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); |
| 252 | setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); |
Chris Lattner | e3fea5a | 2006-03-31 19:52:36 +0000 | [diff] [blame] | 253 | |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 254 | // We promote all shuffles to v16i8. |
| 255 | setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); |
Chris Lattner | f3f69de | 2006-04-16 01:37:57 +0000 | [diff] [blame] | 256 | AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); |
| 257 | |
| 258 | // We promote all non-typed operations to v4i32. |
| 259 | setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote); |
| 260 | AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32); |
| 261 | setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote); |
| 262 | AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32); |
| 263 | setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote); |
| 264 | AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32); |
| 265 | setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote); |
| 266 | AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32); |
| 267 | setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); |
| 268 | AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32); |
| 269 | setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote); |
| 270 | AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32); |
Chris Lattner | e3fea5a | 2006-03-31 19:52:36 +0000 | [diff] [blame] | 271 | |
Chris Lattner | f3f69de | 2006-04-16 01:37:57 +0000 | [diff] [blame] | 272 | // No other operations are legal. |
Chris Lattner | e3fea5a | 2006-03-31 19:52:36 +0000 | [diff] [blame] | 273 | setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); |
| 274 | setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); |
| 275 | setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); |
| 276 | setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); |
| 277 | setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); |
Chris Lattner | 2ef5e89 | 2006-05-24 00:15:25 +0000 | [diff] [blame] | 278 | setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); |
Evan Cheng | 66ffe6b | 2007-07-30 07:51:22 +0000 | [diff] [blame] | 279 | setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand); |
Chris Lattner | e3fea5a | 2006-03-31 19:52:36 +0000 | [diff] [blame] | 280 | setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); |
| 281 | setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); |
| 282 | setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); |
Dan Gohman | 3ce990d | 2007-10-08 17:28:24 +0000 | [diff] [blame] | 283 | setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand); |
| 284 | setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand); |
| 285 | setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand); |
| 286 | setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand); |
Chris Lattner | 01cae07 | 2006-04-03 23:55:43 +0000 | [diff] [blame] | 287 | setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); |
Dan Gohman | a3f269f | 2007-10-12 14:08:57 +0000 | [diff] [blame] | 288 | setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand); |
| 289 | setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand); |
| 290 | setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand); |
| 291 | setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand); |
Chris Lattner | e3fea5a | 2006-03-31 19:52:36 +0000 | [diff] [blame] | 292 | } |
| 293 | |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 294 | // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle |
| 295 | // with merges, splats, etc. |
| 296 | setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); |
| 297 | |
Chris Lattner | f3f69de | 2006-04-16 01:37:57 +0000 | [diff] [blame] | 298 | setOperationAction(ISD::AND , MVT::v4i32, Legal); |
| 299 | setOperationAction(ISD::OR , MVT::v4i32, Legal); |
| 300 | setOperationAction(ISD::XOR , MVT::v4i32, Legal); |
| 301 | setOperationAction(ISD::LOAD , MVT::v4i32, Legal); |
| 302 | setOperationAction(ISD::SELECT, MVT::v4i32, Expand); |
| 303 | setOperationAction(ISD::STORE , MVT::v4i32, Legal); |
| 304 | |
Nate Begeman | 425a969 | 2005-11-29 08:17:20 +0000 | [diff] [blame] | 305 | addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); |
Nate Begeman | 7fd1edd | 2005-12-19 23:25:09 +0000 | [diff] [blame] | 306 | addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); |
Chris Lattner | 8d052bc | 2006-03-25 07:39:07 +0000 | [diff] [blame] | 307 | addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); |
| 308 | addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); |
Chris Lattner | ec4a0c7 | 2006-01-29 06:32:58 +0000 | [diff] [blame] | 309 | |
Chris Lattner | e3fea5a | 2006-03-31 19:52:36 +0000 | [diff] [blame] | 310 | setOperationAction(ISD::MUL, MVT::v4f32, Legal); |
Chris Lattner | e7c768e | 2006-04-18 03:24:30 +0000 | [diff] [blame] | 311 | setOperationAction(ISD::MUL, MVT::v4i32, Custom); |
Chris Lattner | 72dd9bd | 2006-04-18 03:43:48 +0000 | [diff] [blame] | 312 | setOperationAction(ISD::MUL, MVT::v8i16, Custom); |
Chris Lattner | 19a8152 | 2006-04-18 03:57:35 +0000 | [diff] [blame] | 313 | setOperationAction(ISD::MUL, MVT::v16i8, Custom); |
Chris Lattner | f1d0b2b | 2006-03-20 01:53:53 +0000 | [diff] [blame] | 314 | |
Chris Lattner | b2177b9 | 2006-03-19 06:55:52 +0000 | [diff] [blame] | 315 | setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); |
| 316 | setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); |
Chris Lattner | 64b3a08 | 2006-03-24 07:48:08 +0000 | [diff] [blame] | 317 | |
Chris Lattner | 541f91b | 2006-04-02 00:43:36 +0000 | [diff] [blame] | 318 | setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); |
| 319 | setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); |
Chris Lattner | 64b3a08 | 2006-03-24 07:48:08 +0000 | [diff] [blame] | 320 | setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); |
| 321 | setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); |
Nate Begeman | 425a969 | 2005-11-29 08:17:20 +0000 | [diff] [blame] | 322 | } |
| 323 | |
Chris Lattner | c08f902 | 2006-06-27 00:04:13 +0000 | [diff] [blame] | 324 | setSetCCResultType(MVT::i32); |
Chris Lattner | 7b0c58c | 2006-06-27 17:34:57 +0000 | [diff] [blame] | 325 | setShiftAmountType(MVT::i32); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 326 | setSetCCResultContents(ZeroOrOneSetCCResult); |
Chris Lattner | 10da957 | 2006-10-18 01:20:43 +0000 | [diff] [blame] | 327 | |
Jim Laskey | 2ad9f17 | 2007-02-22 14:56:36 +0000 | [diff] [blame] | 328 | if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { |
Chris Lattner | 10da957 | 2006-10-18 01:20:43 +0000 | [diff] [blame] | 329 | setStackPointerRegisterToSaveRestore(PPC::X1); |
Jim Laskey | 2ad9f17 | 2007-02-22 14:56:36 +0000 | [diff] [blame] | 330 | setExceptionPointerRegister(PPC::X3); |
| 331 | setExceptionSelectorRegister(PPC::X4); |
| 332 | } else { |
Chris Lattner | 10da957 | 2006-10-18 01:20:43 +0000 | [diff] [blame] | 333 | setStackPointerRegisterToSaveRestore(PPC::R1); |
Jim Laskey | 2ad9f17 | 2007-02-22 14:56:36 +0000 | [diff] [blame] | 334 | setExceptionPointerRegister(PPC::R3); |
| 335 | setExceptionSelectorRegister(PPC::R4); |
| 336 | } |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 337 | |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 338 | // We have target-specific dag combine patterns for the following nodes: |
| 339 | setTargetDAGCombine(ISD::SINT_TO_FP); |
Chris Lattner | 5126984 | 2006-03-01 05:50:56 +0000 | [diff] [blame] | 340 | setTargetDAGCombine(ISD::STORE); |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 341 | setTargetDAGCombine(ISD::BR_CC); |
Chris Lattner | d998938 | 2006-07-10 20:56:58 +0000 | [diff] [blame] | 342 | setTargetDAGCombine(ISD::BSWAP); |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 343 | |
Dale Johannesen | fabd32d | 2007-10-19 00:59:18 +0000 | [diff] [blame] | 344 | // Darwin long double math library functions have $LDBL128 appended. |
| 345 | if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { |
| 346 | setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); |
| 347 | setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); |
| 348 | setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); |
| 349 | } |
| 350 | |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 351 | computeRegisterProperties(); |
| 352 | } |
| 353 | |
Chris Lattner | da6d20f | 2006-01-09 23:52:17 +0000 | [diff] [blame] | 354 | const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { |
| 355 | switch (Opcode) { |
| 356 | default: return 0; |
| 357 | case PPCISD::FSEL: return "PPCISD::FSEL"; |
| 358 | case PPCISD::FCFID: return "PPCISD::FCFID"; |
| 359 | case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; |
| 360 | case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; |
Chris Lattner | 5126984 | 2006-03-01 05:50:56 +0000 | [diff] [blame] | 361 | case PPCISD::STFIWX: return "PPCISD::STFIWX"; |
Chris Lattner | da6d20f | 2006-01-09 23:52:17 +0000 | [diff] [blame] | 362 | case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; |
| 363 | case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; |
Chris Lattner | f1d0b2b | 2006-03-20 01:53:53 +0000 | [diff] [blame] | 364 | case PPCISD::VPERM: return "PPCISD::VPERM"; |
Chris Lattner | da6d20f | 2006-01-09 23:52:17 +0000 | [diff] [blame] | 365 | case PPCISD::Hi: return "PPCISD::Hi"; |
| 366 | case PPCISD::Lo: return "PPCISD::Lo"; |
Jim Laskey | 2060a82 | 2006-12-11 18:45:56 +0000 | [diff] [blame] | 367 | case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; |
Chris Lattner | da6d20f | 2006-01-09 23:52:17 +0000 | [diff] [blame] | 368 | case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; |
| 369 | case PPCISD::SRL: return "PPCISD::SRL"; |
| 370 | case PPCISD::SRA: return "PPCISD::SRA"; |
| 371 | case PPCISD::SHL: return "PPCISD::SHL"; |
Chris Lattner | ecfe55e | 2006-03-22 05:30:33 +0000 | [diff] [blame] | 372 | case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; |
| 373 | case PPCISD::STD_32: return "PPCISD::STD_32"; |
Nicolas Geoffray | 63f8fb1 | 2007-02-27 13:01:19 +0000 | [diff] [blame] | 374 | case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF"; |
| 375 | case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho"; |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 376 | case PPCISD::MTCTR: return "PPCISD::MTCTR"; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 377 | case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; |
| 378 | case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; |
Chris Lattner | da6d20f | 2006-01-09 23:52:17 +0000 | [diff] [blame] | 379 | case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; |
Chris Lattner | 6d92cad | 2006-03-26 10:06:40 +0000 | [diff] [blame] | 380 | case PPCISD::MFCR: return "PPCISD::MFCR"; |
Chris Lattner | a17b155 | 2006-03-31 05:13:27 +0000 | [diff] [blame] | 381 | case PPCISD::VCMP: return "PPCISD::VCMP"; |
Chris Lattner | 6d92cad | 2006-03-26 10:06:40 +0000 | [diff] [blame] | 382 | case PPCISD::VCMPo: return "PPCISD::VCMPo"; |
Chris Lattner | d998938 | 2006-07-10 20:56:58 +0000 | [diff] [blame] | 383 | case PPCISD::LBRX: return "PPCISD::LBRX"; |
| 384 | case PPCISD::STBRX: return "PPCISD::STBRX"; |
Chris Lattner | f70f8d9 | 2006-04-18 18:05:58 +0000 | [diff] [blame] | 385 | case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; |
Chris Lattner | da6d20f | 2006-01-09 23:52:17 +0000 | [diff] [blame] | 386 | } |
| 387 | } |
| 388 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 389 | //===----------------------------------------------------------------------===// |
| 390 | // Node matching predicates, for use by the tblgen matching code. |
| 391 | //===----------------------------------------------------------------------===// |
| 392 | |
Chris Lattner | 0b1e4e5 | 2005-08-26 17:36:52 +0000 | [diff] [blame] | 393 | /// isFloatingPointZero - Return true if this is 0.0 or -0.0. |
| 394 | static bool isFloatingPointZero(SDOperand Op) { |
| 395 | if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) |
Dale Johannesen | eaf0894 | 2007-08-31 04:03:46 +0000 | [diff] [blame] | 396 | return CFP->getValueAPF().isZero(); |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 397 | else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { |
Chris Lattner | 0b1e4e5 | 2005-08-26 17:36:52 +0000 | [diff] [blame] | 398 | // Maybe this has already been legalized into the constant pool? |
| 399 | if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) |
Evan Cheng | c356a57 | 2006-09-12 21:04:05 +0000 | [diff] [blame] | 400 | if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) |
Dale Johannesen | eaf0894 | 2007-08-31 04:03:46 +0000 | [diff] [blame] | 401 | return CFP->getValueAPF().isZero(); |
Chris Lattner | 0b1e4e5 | 2005-08-26 17:36:52 +0000 | [diff] [blame] | 402 | } |
| 403 | return false; |
| 404 | } |
| 405 | |
Chris Lattner | ddb739e | 2006-04-06 17:23:16 +0000 | [diff] [blame] | 406 | /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return |
| 407 | /// true if Op is undef or if it matches the specified value. |
| 408 | static bool isConstantOrUndef(SDOperand Op, unsigned Val) { |
| 409 | return Op.getOpcode() == ISD::UNDEF || |
| 410 | cast<ConstantSDNode>(Op)->getValue() == Val; |
| 411 | } |
| 412 | |
| 413 | /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a |
| 414 | /// VPKUHUM instruction. |
Chris Lattner | f24380e | 2006-04-06 22:28:36 +0000 | [diff] [blame] | 415 | bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { |
| 416 | if (!isUnary) { |
| 417 | for (unsigned i = 0; i != 16; ++i) |
| 418 | if (!isConstantOrUndef(N->getOperand(i), i*2+1)) |
| 419 | return false; |
| 420 | } else { |
| 421 | for (unsigned i = 0; i != 8; ++i) |
| 422 | if (!isConstantOrUndef(N->getOperand(i), i*2+1) || |
| 423 | !isConstantOrUndef(N->getOperand(i+8), i*2+1)) |
| 424 | return false; |
| 425 | } |
Chris Lattner | d0608e1 | 2006-04-06 18:26:28 +0000 | [diff] [blame] | 426 | return true; |
Chris Lattner | ddb739e | 2006-04-06 17:23:16 +0000 | [diff] [blame] | 427 | } |
| 428 | |
| 429 | /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a |
| 430 | /// VPKUWUM instruction. |
Chris Lattner | f24380e | 2006-04-06 22:28:36 +0000 | [diff] [blame] | 431 | bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { |
| 432 | if (!isUnary) { |
| 433 | for (unsigned i = 0; i != 16; i += 2) |
| 434 | if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || |
| 435 | !isConstantOrUndef(N->getOperand(i+1), i*2+3)) |
| 436 | return false; |
| 437 | } else { |
| 438 | for (unsigned i = 0; i != 8; i += 2) |
| 439 | if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || |
| 440 | !isConstantOrUndef(N->getOperand(i+1), i*2+3) || |
| 441 | !isConstantOrUndef(N->getOperand(i+8), i*2+2) || |
| 442 | !isConstantOrUndef(N->getOperand(i+9), i*2+3)) |
| 443 | return false; |
| 444 | } |
Chris Lattner | d0608e1 | 2006-04-06 18:26:28 +0000 | [diff] [blame] | 445 | return true; |
Chris Lattner | ddb739e | 2006-04-06 17:23:16 +0000 | [diff] [blame] | 446 | } |
| 447 | |
Chris Lattner | caad163 | 2006-04-06 22:02:42 +0000 | [diff] [blame] | 448 | /// isVMerge - Common function, used to match vmrg* shuffles. |
| 449 | /// |
| 450 | static bool isVMerge(SDNode *N, unsigned UnitSize, |
| 451 | unsigned LHSStart, unsigned RHSStart) { |
Chris Lattner | 116cc48 | 2006-04-06 21:11:54 +0000 | [diff] [blame] | 452 | assert(N->getOpcode() == ISD::BUILD_VECTOR && |
| 453 | N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); |
| 454 | assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && |
| 455 | "Unsupported merge size!"); |
| 456 | |
| 457 | for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units |
| 458 | for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit |
| 459 | if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), |
Chris Lattner | caad163 | 2006-04-06 22:02:42 +0000 | [diff] [blame] | 460 | LHSStart+j+i*UnitSize) || |
Chris Lattner | 116cc48 | 2006-04-06 21:11:54 +0000 | [diff] [blame] | 461 | !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), |
Chris Lattner | caad163 | 2006-04-06 22:02:42 +0000 | [diff] [blame] | 462 | RHSStart+j+i*UnitSize)) |
Chris Lattner | 116cc48 | 2006-04-06 21:11:54 +0000 | [diff] [blame] | 463 | return false; |
| 464 | } |
Chris Lattner | caad163 | 2006-04-06 22:02:42 +0000 | [diff] [blame] | 465 | return true; |
| 466 | } |
| 467 | |
| 468 | /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for |
| 469 | /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). |
| 470 | bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { |
| 471 | if (!isUnary) |
| 472 | return isVMerge(N, UnitSize, 8, 24); |
| 473 | return isVMerge(N, UnitSize, 8, 8); |
Chris Lattner | 116cc48 | 2006-04-06 21:11:54 +0000 | [diff] [blame] | 474 | } |
| 475 | |
| 476 | /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for |
| 477 | /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). |
Chris Lattner | caad163 | 2006-04-06 22:02:42 +0000 | [diff] [blame] | 478 | bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { |
| 479 | if (!isUnary) |
| 480 | return isVMerge(N, UnitSize, 0, 16); |
| 481 | return isVMerge(N, UnitSize, 0, 0); |
Chris Lattner | 116cc48 | 2006-04-06 21:11:54 +0000 | [diff] [blame] | 482 | } |
| 483 | |
| 484 | |
Chris Lattner | d0608e1 | 2006-04-06 18:26:28 +0000 | [diff] [blame] | 485 | /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift |
| 486 | /// amount, otherwise return -1. |
Chris Lattner | f24380e | 2006-04-06 22:28:36 +0000 | [diff] [blame] | 487 | int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { |
Chris Lattner | 116cc48 | 2006-04-06 21:11:54 +0000 | [diff] [blame] | 488 | assert(N->getOpcode() == ISD::BUILD_VECTOR && |
| 489 | N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); |
Chris Lattner | d0608e1 | 2006-04-06 18:26:28 +0000 | [diff] [blame] | 490 | // Find the first non-undef value in the shuffle mask. |
| 491 | unsigned i; |
| 492 | for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) |
| 493 | /*search*/; |
| 494 | |
| 495 | if (i == 16) return -1; // all undef. |
| 496 | |
| 497 | // Otherwise, check to see if the rest of the elements are consequtively |
| 498 | // numbered from this value. |
| 499 | unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue(); |
| 500 | if (ShiftAmt < i) return -1; |
| 501 | ShiftAmt -= i; |
Chris Lattner | ddb739e | 2006-04-06 17:23:16 +0000 | [diff] [blame] | 502 | |
Chris Lattner | f24380e | 2006-04-06 22:28:36 +0000 | [diff] [blame] | 503 | if (!isUnary) { |
| 504 | // Check the rest of the elements to see if they are consequtive. |
| 505 | for (++i; i != 16; ++i) |
| 506 | if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) |
| 507 | return -1; |
| 508 | } else { |
| 509 | // Check the rest of the elements to see if they are consequtive. |
| 510 | for (++i; i != 16; ++i) |
| 511 | if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) |
| 512 | return -1; |
| 513 | } |
Chris Lattner | d0608e1 | 2006-04-06 18:26:28 +0000 | [diff] [blame] | 514 | |
| 515 | return ShiftAmt; |
| 516 | } |
Chris Lattner | ef819f8 | 2006-03-20 06:33:01 +0000 | [diff] [blame] | 517 | |
| 518 | /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand |
| 519 | /// specifies a splat of a single element that is suitable for input to |
| 520 | /// VSPLTB/VSPLTH/VSPLTW. |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 521 | bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { |
| 522 | assert(N->getOpcode() == ISD::BUILD_VECTOR && |
| 523 | N->getNumOperands() == 16 && |
| 524 | (EltSize == 1 || EltSize == 2 || EltSize == 4)); |
Chris Lattner | dd4d2d0 | 2006-03-20 06:51:10 +0000 | [diff] [blame] | 525 | |
Chris Lattner | 88a99ef | 2006-03-20 06:37:44 +0000 | [diff] [blame] | 526 | // This is a splat operation if each element of the permute is the same, and |
| 527 | // if the value doesn't reference the second vector. |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 528 | unsigned ElementBase = 0; |
Chris Lattner | 88a99ef | 2006-03-20 06:37:44 +0000 | [diff] [blame] | 529 | SDOperand Elt = N->getOperand(0); |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 530 | if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) |
| 531 | ElementBase = EltV->getValue(); |
| 532 | else |
| 533 | return false; // FIXME: Handle UNDEF elements too! |
| 534 | |
| 535 | if (cast<ConstantSDNode>(Elt)->getValue() >= 16) |
| 536 | return false; |
| 537 | |
| 538 | // Check that they are consequtive. |
| 539 | for (unsigned i = 1; i != EltSize; ++i) { |
| 540 | if (!isa<ConstantSDNode>(N->getOperand(i)) || |
| 541 | cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase) |
| 542 | return false; |
| 543 | } |
| 544 | |
Chris Lattner | 88a99ef | 2006-03-20 06:37:44 +0000 | [diff] [blame] | 545 | assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 546 | for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { |
Chris Lattner | b097aa9 | 2006-04-14 23:19:08 +0000 | [diff] [blame] | 547 | if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; |
Chris Lattner | 88a99ef | 2006-03-20 06:37:44 +0000 | [diff] [blame] | 548 | assert(isa<ConstantSDNode>(N->getOperand(i)) && |
| 549 | "Invalid VECTOR_SHUFFLE mask!"); |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 550 | for (unsigned j = 0; j != EltSize; ++j) |
| 551 | if (N->getOperand(i+j) != N->getOperand(j)) |
| 552 | return false; |
Chris Lattner | 88a99ef | 2006-03-20 06:37:44 +0000 | [diff] [blame] | 553 | } |
| 554 | |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 555 | return true; |
Chris Lattner | ef819f8 | 2006-03-20 06:33:01 +0000 | [diff] [blame] | 556 | } |
| 557 | |
Evan Cheng | 66ffe6b | 2007-07-30 07:51:22 +0000 | [diff] [blame] | 558 | /// isAllNegativeZeroVector - Returns true if all elements of build_vector |
| 559 | /// are -0.0. |
| 560 | bool PPC::isAllNegativeZeroVector(SDNode *N) { |
| 561 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
| 562 | if (PPC::isSplatShuffleMask(N, N->getNumOperands())) |
| 563 | if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N)) |
Dale Johannesen | eaf0894 | 2007-08-31 04:03:46 +0000 | [diff] [blame] | 564 | return CFP->getValueAPF().isNegZero(); |
Evan Cheng | 66ffe6b | 2007-07-30 07:51:22 +0000 | [diff] [blame] | 565 | return false; |
| 566 | } |
| 567 | |
Chris Lattner | ef819f8 | 2006-03-20 06:33:01 +0000 | [diff] [blame] | 568 | /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the |
| 569 | /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 570 | unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { |
| 571 | assert(isSplatShuffleMask(N, EltSize)); |
| 572 | return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize; |
Chris Lattner | ef819f8 | 2006-03-20 06:33:01 +0000 | [diff] [blame] | 573 | } |
| 574 | |
Chris Lattner | e87192a | 2006-04-12 17:37:20 +0000 | [diff] [blame] | 575 | /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed |
Chris Lattner | 140a58f | 2006-04-08 06:46:53 +0000 | [diff] [blame] | 576 | /// by using a vspltis[bhw] instruction of the specified element size, return |
| 577 | /// the constant being splatted. The ByteSize field indicates the number of |
| 578 | /// bytes of each element [124] -> [bhw]. |
Chris Lattner | e87192a | 2006-04-12 17:37:20 +0000 | [diff] [blame] | 579 | SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 580 | SDOperand OpVal(0, 0); |
Chris Lattner | 79d9a88 | 2006-04-08 07:14:26 +0000 | [diff] [blame] | 581 | |
| 582 | // If ByteSize of the splat is bigger than the element size of the |
| 583 | // build_vector, then we have a case where we are checking for a splat where |
| 584 | // multiple elements of the buildvector are folded together into a single |
| 585 | // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). |
| 586 | unsigned EltSize = 16/N->getNumOperands(); |
| 587 | if (EltSize < ByteSize) { |
| 588 | unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. |
| 589 | SDOperand UniquedVals[4]; |
| 590 | assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); |
| 591 | |
| 592 | // See if all of the elements in the buildvector agree across. |
| 593 | for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { |
| 594 | if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; |
| 595 | // If the element isn't a constant, bail fully out. |
| 596 | if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand(); |
| 597 | |
| 598 | |
| 599 | if (UniquedVals[i&(Multiple-1)].Val == 0) |
| 600 | UniquedVals[i&(Multiple-1)] = N->getOperand(i); |
| 601 | else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) |
| 602 | return SDOperand(); // no match. |
| 603 | } |
| 604 | |
| 605 | // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains |
| 606 | // either constant or undef values that are identical for each chunk. See |
| 607 | // if these chunks can form into a larger vspltis*. |
| 608 | |
| 609 | // Check to see if all of the leading entries are either 0 or -1. If |
| 610 | // neither, then this won't fit into the immediate field. |
| 611 | bool LeadingZero = true; |
| 612 | bool LeadingOnes = true; |
| 613 | for (unsigned i = 0; i != Multiple-1; ++i) { |
| 614 | if (UniquedVals[i].Val == 0) continue; // Must have been undefs. |
| 615 | |
| 616 | LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); |
| 617 | LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); |
| 618 | } |
| 619 | // Finally, check the least significant entry. |
| 620 | if (LeadingZero) { |
| 621 | if (UniquedVals[Multiple-1].Val == 0) |
| 622 | return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef |
| 623 | int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue(); |
| 624 | if (Val < 16) |
| 625 | return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) |
| 626 | } |
| 627 | if (LeadingOnes) { |
| 628 | if (UniquedVals[Multiple-1].Val == 0) |
| 629 | return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef |
| 630 | int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); |
| 631 | if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) |
| 632 | return DAG.getTargetConstant(Val, MVT::i32); |
| 633 | } |
| 634 | |
| 635 | return SDOperand(); |
| 636 | } |
| 637 | |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 638 | // Check to see if this buildvec has a single non-undef value in its elements. |
| 639 | for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { |
| 640 | if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; |
| 641 | if (OpVal.Val == 0) |
| 642 | OpVal = N->getOperand(i); |
| 643 | else if (OpVal != N->getOperand(i)) |
Chris Lattner | 140a58f | 2006-04-08 06:46:53 +0000 | [diff] [blame] | 644 | return SDOperand(); |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 645 | } |
| 646 | |
Chris Lattner | 140a58f | 2006-04-08 06:46:53 +0000 | [diff] [blame] | 647 | if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def. |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 648 | |
Nate Begeman | 98e70cc | 2006-03-28 04:15:58 +0000 | [diff] [blame] | 649 | unsigned ValSizeInBytes = 0; |
| 650 | uint64_t Value = 0; |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 651 | if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { |
| 652 | Value = CN->getValue(); |
| 653 | ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8; |
| 654 | } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { |
| 655 | assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); |
Dale Johannesen | eaf0894 | 2007-08-31 04:03:46 +0000 | [diff] [blame] | 656 | Value = FloatToBits(CN->getValueAPF().convertToFloat()); |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 657 | ValSizeInBytes = 4; |
| 658 | } |
| 659 | |
| 660 | // If the splat value is larger than the element value, then we can never do |
| 661 | // this splat. The only case that we could fit the replicated bits into our |
| 662 | // immediate field for would be zero, and we prefer to use vxor for it. |
Chris Lattner | 140a58f | 2006-04-08 06:46:53 +0000 | [diff] [blame] | 663 | if (ValSizeInBytes < ByteSize) return SDOperand(); |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 664 | |
| 665 | // If the element value is larger than the splat value, cut it in half and |
| 666 | // check to see if the two halves are equal. Continue doing this until we |
| 667 | // get to ByteSize. This allows us to handle 0x01010101 as 0x01. |
| 668 | while (ValSizeInBytes > ByteSize) { |
| 669 | ValSizeInBytes >>= 1; |
| 670 | |
| 671 | // If the top half equals the bottom half, we're still ok. |
Chris Lattner | 9b42bdd | 2006-04-05 17:39:25 +0000 | [diff] [blame] | 672 | if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != |
| 673 | (Value & ((1 << (8*ValSizeInBytes))-1))) |
Chris Lattner | 140a58f | 2006-04-08 06:46:53 +0000 | [diff] [blame] | 674 | return SDOperand(); |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 675 | } |
| 676 | |
| 677 | // Properly sign extend the value. |
| 678 | int ShAmt = (4-ByteSize)*8; |
| 679 | int MaskVal = ((int)Value << ShAmt) >> ShAmt; |
| 680 | |
Evan Cheng | 5b6a01b | 2006-03-26 09:52:32 +0000 | [diff] [blame] | 681 | // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. |
Chris Lattner | 140a58f | 2006-04-08 06:46:53 +0000 | [diff] [blame] | 682 | if (MaskVal == 0) return SDOperand(); |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 683 | |
Chris Lattner | 140a58f | 2006-04-08 06:46:53 +0000 | [diff] [blame] | 684 | // Finally, if this value fits in a 5 bit sext field, return it |
| 685 | if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) |
| 686 | return DAG.getTargetConstant(MaskVal, MVT::i32); |
| 687 | return SDOperand(); |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 688 | } |
| 689 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 690 | //===----------------------------------------------------------------------===// |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 691 | // Addressing Mode Selection |
| 692 | //===----------------------------------------------------------------------===// |
| 693 | |
| 694 | /// isIntS16Immediate - This method tests to see if the node is either a 32-bit |
| 695 | /// or 64-bit immediate, and if the value can be accurately represented as a |
| 696 | /// sign extension from a 16-bit value. If so, this returns true and the |
| 697 | /// immediate. |
| 698 | static bool isIntS16Immediate(SDNode *N, short &Imm) { |
| 699 | if (N->getOpcode() != ISD::Constant) |
| 700 | return false; |
| 701 | |
| 702 | Imm = (short)cast<ConstantSDNode>(N)->getValue(); |
| 703 | if (N->getValueType(0) == MVT::i32) |
| 704 | return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue(); |
| 705 | else |
| 706 | return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue(); |
| 707 | } |
| 708 | static bool isIntS16Immediate(SDOperand Op, short &Imm) { |
| 709 | return isIntS16Immediate(Op.Val, Imm); |
| 710 | } |
| 711 | |
| 712 | |
| 713 | /// SelectAddressRegReg - Given the specified addressed, check to see if it |
| 714 | /// can be represented as an indexed [r+r] operation. Returns false if it |
| 715 | /// can be more efficiently represented with [r+imm]. |
| 716 | bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base, |
| 717 | SDOperand &Index, |
| 718 | SelectionDAG &DAG) { |
| 719 | short imm = 0; |
| 720 | if (N.getOpcode() == ISD::ADD) { |
| 721 | if (isIntS16Immediate(N.getOperand(1), imm)) |
| 722 | return false; // r+i |
| 723 | if (N.getOperand(1).getOpcode() == PPCISD::Lo) |
| 724 | return false; // r+i |
| 725 | |
| 726 | Base = N.getOperand(0); |
| 727 | Index = N.getOperand(1); |
| 728 | return true; |
| 729 | } else if (N.getOpcode() == ISD::OR) { |
| 730 | if (isIntS16Immediate(N.getOperand(1), imm)) |
| 731 | return false; // r+i can fold it if we can. |
| 732 | |
| 733 | // If this is an or of disjoint bitfields, we can codegen this as an add |
| 734 | // (for better address arithmetic) if the LHS and RHS of the OR are provably |
| 735 | // disjoint. |
| 736 | uint64_t LHSKnownZero, LHSKnownOne; |
| 737 | uint64_t RHSKnownZero, RHSKnownOne; |
Dan Gohman | ea859be | 2007-06-22 14:59:07 +0000 | [diff] [blame] | 738 | DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 739 | |
| 740 | if (LHSKnownZero) { |
Dan Gohman | ea859be | 2007-06-22 14:59:07 +0000 | [diff] [blame] | 741 | DAG.ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne); |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 742 | // If all of the bits are known zero on the LHS or RHS, the add won't |
| 743 | // carry. |
| 744 | if ((LHSKnownZero | RHSKnownZero) == ~0U) { |
| 745 | Base = N.getOperand(0); |
| 746 | Index = N.getOperand(1); |
| 747 | return true; |
| 748 | } |
| 749 | } |
| 750 | } |
| 751 | |
| 752 | return false; |
| 753 | } |
| 754 | |
| 755 | /// Returns true if the address N can be represented by a base register plus |
| 756 | /// a signed 16-bit displacement [r+imm], and if it is not better |
| 757 | /// represented as reg+reg. |
| 758 | bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp, |
| 759 | SDOperand &Base, SelectionDAG &DAG){ |
| 760 | // If this can be more profitably realized as r+r, fail. |
| 761 | if (SelectAddressRegReg(N, Disp, Base, DAG)) |
| 762 | return false; |
| 763 | |
| 764 | if (N.getOpcode() == ISD::ADD) { |
| 765 | short imm = 0; |
| 766 | if (isIntS16Immediate(N.getOperand(1), imm)) { |
| 767 | Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); |
| 768 | if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { |
| 769 | Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); |
| 770 | } else { |
| 771 | Base = N.getOperand(0); |
| 772 | } |
| 773 | return true; // [r+i] |
| 774 | } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { |
| 775 | // Match LOAD (ADD (X, Lo(G))). |
| 776 | assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() |
| 777 | && "Cannot handle constant offsets yet!"); |
| 778 | Disp = N.getOperand(1).getOperand(0); // The global address. |
| 779 | assert(Disp.getOpcode() == ISD::TargetGlobalAddress || |
| 780 | Disp.getOpcode() == ISD::TargetConstantPool || |
| 781 | Disp.getOpcode() == ISD::TargetJumpTable); |
| 782 | Base = N.getOperand(0); |
| 783 | return true; // [&g+r] |
| 784 | } |
| 785 | } else if (N.getOpcode() == ISD::OR) { |
| 786 | short imm = 0; |
| 787 | if (isIntS16Immediate(N.getOperand(1), imm)) { |
| 788 | // If this is an or of disjoint bitfields, we can codegen this as an add |
| 789 | // (for better address arithmetic) if the LHS and RHS of the OR are |
| 790 | // provably disjoint. |
| 791 | uint64_t LHSKnownZero, LHSKnownOne; |
Dan Gohman | ea859be | 2007-06-22 14:59:07 +0000 | [diff] [blame] | 792 | DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 793 | if ((LHSKnownZero|~(unsigned)imm) == ~0U) { |
| 794 | // If all of the bits are known zero on the LHS or RHS, the add won't |
| 795 | // carry. |
| 796 | Base = N.getOperand(0); |
| 797 | Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); |
| 798 | return true; |
| 799 | } |
| 800 | } |
| 801 | } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { |
| 802 | // Loading from a constant address. |
| 803 | |
| 804 | // If this address fits entirely in a 16-bit sext immediate field, codegen |
| 805 | // this as "d, 0" |
| 806 | short Imm; |
| 807 | if (isIntS16Immediate(CN, Imm)) { |
| 808 | Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); |
| 809 | Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); |
| 810 | return true; |
| 811 | } |
Chris Lattner | bc681d6 | 2007-02-17 06:44:03 +0000 | [diff] [blame] | 812 | |
| 813 | // Handle 32-bit sext immediates with LIS + addr mode. |
| 814 | if (CN->getValueType(0) == MVT::i32 || |
| 815 | (int64_t)CN->getValue() == (int)CN->getValue()) { |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 816 | int Addr = (int)CN->getValue(); |
| 817 | |
| 818 | // Otherwise, break this down into an LIS + disp. |
Chris Lattner | bc681d6 | 2007-02-17 06:44:03 +0000 | [diff] [blame] | 819 | Disp = DAG.getTargetConstant((short)Addr, MVT::i32); |
| 820 | |
| 821 | Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); |
| 822 | unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; |
| 823 | Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 824 | return true; |
| 825 | } |
| 826 | } |
| 827 | |
| 828 | Disp = DAG.getTargetConstant(0, getPointerTy()); |
| 829 | if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) |
| 830 | Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); |
| 831 | else |
| 832 | Base = N; |
| 833 | return true; // [r+0] |
| 834 | } |
| 835 | |
| 836 | /// SelectAddressRegRegOnly - Given the specified addressed, force it to be |
| 837 | /// represented as an indexed [r+r] operation. |
| 838 | bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, |
| 839 | SDOperand &Index, |
| 840 | SelectionDAG &DAG) { |
| 841 | // Check to see if we can easily represent this as an [r+r] address. This |
| 842 | // will fail if it thinks that the address is more profitably represented as |
| 843 | // reg+imm, e.g. where imm = 0. |
| 844 | if (SelectAddressRegReg(N, Base, Index, DAG)) |
| 845 | return true; |
| 846 | |
| 847 | // If the operand is an addition, always emit this as [r+r], since this is |
| 848 | // better (for code size, and execution, as the memop does the add for free) |
| 849 | // than emitting an explicit add. |
| 850 | if (N.getOpcode() == ISD::ADD) { |
| 851 | Base = N.getOperand(0); |
| 852 | Index = N.getOperand(1); |
| 853 | return true; |
| 854 | } |
| 855 | |
| 856 | // Otherwise, do it the hard way, using R0 as the base register. |
| 857 | Base = DAG.getRegister(PPC::R0, N.getValueType()); |
| 858 | Index = N; |
| 859 | return true; |
| 860 | } |
| 861 | |
| 862 | /// SelectAddressRegImmShift - Returns true if the address N can be |
| 863 | /// represented by a base register plus a signed 14-bit displacement |
| 864 | /// [r+imm*4]. Suitable for use by STD and friends. |
| 865 | bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, |
| 866 | SDOperand &Base, |
| 867 | SelectionDAG &DAG) { |
| 868 | // If this can be more profitably realized as r+r, fail. |
| 869 | if (SelectAddressRegReg(N, Disp, Base, DAG)) |
| 870 | return false; |
| 871 | |
| 872 | if (N.getOpcode() == ISD::ADD) { |
| 873 | short imm = 0; |
| 874 | if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { |
| 875 | Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); |
| 876 | if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { |
| 877 | Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); |
| 878 | } else { |
| 879 | Base = N.getOperand(0); |
| 880 | } |
| 881 | return true; // [r+i] |
| 882 | } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { |
| 883 | // Match LOAD (ADD (X, Lo(G))). |
| 884 | assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() |
| 885 | && "Cannot handle constant offsets yet!"); |
| 886 | Disp = N.getOperand(1).getOperand(0); // The global address. |
| 887 | assert(Disp.getOpcode() == ISD::TargetGlobalAddress || |
| 888 | Disp.getOpcode() == ISD::TargetConstantPool || |
| 889 | Disp.getOpcode() == ISD::TargetJumpTable); |
| 890 | Base = N.getOperand(0); |
| 891 | return true; // [&g+r] |
| 892 | } |
| 893 | } else if (N.getOpcode() == ISD::OR) { |
| 894 | short imm = 0; |
| 895 | if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { |
| 896 | // If this is an or of disjoint bitfields, we can codegen this as an add |
| 897 | // (for better address arithmetic) if the LHS and RHS of the OR are |
| 898 | // provably disjoint. |
| 899 | uint64_t LHSKnownZero, LHSKnownOne; |
Dan Gohman | ea859be | 2007-06-22 14:59:07 +0000 | [diff] [blame] | 900 | DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 901 | if ((LHSKnownZero|~(unsigned)imm) == ~0U) { |
| 902 | // If all of the bits are known zero on the LHS or RHS, the add won't |
| 903 | // carry. |
| 904 | Base = N.getOperand(0); |
| 905 | Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); |
| 906 | return true; |
| 907 | } |
| 908 | } |
| 909 | } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { |
Chris Lattner | dee5a5a | 2007-02-17 06:57:26 +0000 | [diff] [blame] | 910 | // Loading from a constant address. Verify low two bits are clear. |
| 911 | if ((CN->getValue() & 3) == 0) { |
| 912 | // If this address fits entirely in a 14-bit sext immediate field, codegen |
| 913 | // this as "d, 0" |
| 914 | short Imm; |
| 915 | if (isIntS16Immediate(CN, Imm)) { |
| 916 | Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); |
| 917 | Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); |
| 918 | return true; |
| 919 | } |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 920 | |
Chris Lattner | dee5a5a | 2007-02-17 06:57:26 +0000 | [diff] [blame] | 921 | // Fold the low-part of 32-bit absolute addresses into addr mode. |
| 922 | if (CN->getValueType(0) == MVT::i32 || |
| 923 | (int64_t)CN->getValue() == (int)CN->getValue()) { |
| 924 | int Addr = (int)CN->getValue(); |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 925 | |
Chris Lattner | dee5a5a | 2007-02-17 06:57:26 +0000 | [diff] [blame] | 926 | // Otherwise, break this down into an LIS + disp. |
| 927 | Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); |
| 928 | |
| 929 | Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); |
| 930 | unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; |
| 931 | Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); |
| 932 | return true; |
| 933 | } |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 934 | } |
| 935 | } |
| 936 | |
| 937 | Disp = DAG.getTargetConstant(0, getPointerTy()); |
| 938 | if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) |
| 939 | Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); |
| 940 | else |
| 941 | Base = N; |
| 942 | return true; // [r+0] |
| 943 | } |
| 944 | |
| 945 | |
| 946 | /// getPreIndexedAddressParts - returns true by value, base pointer and |
| 947 | /// offset pointer and addressing mode by reference if the node's address |
| 948 | /// can be legally represented as pre-indexed load / store address. |
| 949 | bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, |
| 950 | SDOperand &Offset, |
Evan Cheng | 144d8f0 | 2006-11-09 17:55:04 +0000 | [diff] [blame] | 951 | ISD::MemIndexedMode &AM, |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 952 | SelectionDAG &DAG) { |
Chris Lattner | 4eab714 | 2006-11-10 02:08:47 +0000 | [diff] [blame] | 953 | // Disabled by default for now. |
| 954 | if (!EnablePPCPreinc) return false; |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 955 | |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 956 | SDOperand Ptr; |
Chris Lattner | 2fe4bf4 | 2006-11-14 01:38:31 +0000 | [diff] [blame] | 957 | MVT::ValueType VT; |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 958 | if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { |
| 959 | Ptr = LD->getBasePtr(); |
Chris Lattner | 0851b4f | 2006-11-15 19:55:13 +0000 | [diff] [blame] | 960 | VT = LD->getLoadedVT(); |
| 961 | |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 962 | } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { |
Chris Lattner | 4eab714 | 2006-11-10 02:08:47 +0000 | [diff] [blame] | 963 | ST = ST; |
Chris Lattner | 2fe4bf4 | 2006-11-14 01:38:31 +0000 | [diff] [blame] | 964 | Ptr = ST->getBasePtr(); |
| 965 | VT = ST->getStoredVT(); |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 966 | } else |
| 967 | return false; |
| 968 | |
Chris Lattner | 2fe4bf4 | 2006-11-14 01:38:31 +0000 | [diff] [blame] | 969 | // PowerPC doesn't have preinc load/store instructions for vectors. |
| 970 | if (MVT::isVector(VT)) |
| 971 | return false; |
| 972 | |
Chris Lattner | 0851b4f | 2006-11-15 19:55:13 +0000 | [diff] [blame] | 973 | // TODO: Check reg+reg first. |
| 974 | |
| 975 | // LDU/STU use reg+imm*4, others use reg+imm. |
| 976 | if (VT != MVT::i64) { |
| 977 | // reg + imm |
| 978 | if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) |
| 979 | return false; |
| 980 | } else { |
| 981 | // reg + imm * 4. |
| 982 | if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) |
| 983 | return false; |
| 984 | } |
Chris Lattner | f6edf4d | 2006-11-11 00:08:42 +0000 | [diff] [blame] | 985 | |
Chris Lattner | f6edf4d | 2006-11-11 00:08:42 +0000 | [diff] [blame] | 986 | if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { |
Chris Lattner | 0851b4f | 2006-11-15 19:55:13 +0000 | [diff] [blame] | 987 | // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of |
| 988 | // sext i32 to i64 when addr mode is r+i. |
Chris Lattner | f6edf4d | 2006-11-11 00:08:42 +0000 | [diff] [blame] | 989 | if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 && |
| 990 | LD->getExtensionType() == ISD::SEXTLOAD && |
| 991 | isa<ConstantSDNode>(Offset)) |
| 992 | return false; |
Chris Lattner | 0851b4f | 2006-11-15 19:55:13 +0000 | [diff] [blame] | 993 | } |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 994 | |
Chris Lattner | 4eab714 | 2006-11-10 02:08:47 +0000 | [diff] [blame] | 995 | AM = ISD::PRE_INC; |
| 996 | return true; |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 997 | } |
| 998 | |
| 999 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1000 | // LowerOperation implementation |
| 1001 | //===----------------------------------------------------------------------===// |
| 1002 | |
| 1003 | static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1004 | MVT::ValueType PtrVT = Op.getValueType(); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1005 | ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); |
Evan Cheng | c356a57 | 2006-09-12 21:04:05 +0000 | [diff] [blame] | 1006 | Constant *C = CP->getConstVal(); |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1007 | SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); |
| 1008 | SDOperand Zero = DAG.getConstant(0, PtrVT); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1009 | |
| 1010 | const TargetMachine &TM = DAG.getTarget(); |
| 1011 | |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1012 | SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); |
| 1013 | SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); |
| 1014 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1015 | // If this is a non-darwin platform, we don't support non-static relo models |
| 1016 | // yet. |
| 1017 | if (TM.getRelocationModel() == Reloc::Static || |
| 1018 | !TM.getSubtarget<PPCSubtarget>().isDarwin()) { |
| 1019 | // Generate non-pic code that has direct accesses to the constant pool. |
| 1020 | // The address of the global is just (hi(&g)+lo(&g)). |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1021 | return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1022 | } |
| 1023 | |
Chris Lattner | 35d86fe | 2006-07-26 21:12:04 +0000 | [diff] [blame] | 1024 | if (TM.getRelocationModel() == Reloc::PIC_) { |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1025 | // With PIC, the first instruction is actually "GR+hi(&G)". |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1026 | Hi = DAG.getNode(ISD::ADD, PtrVT, |
| 1027 | DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1028 | } |
| 1029 | |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1030 | Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1031 | return Lo; |
| 1032 | } |
| 1033 | |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 1034 | static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1035 | MVT::ValueType PtrVT = Op.getValueType(); |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 1036 | JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1037 | SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); |
| 1038 | SDOperand Zero = DAG.getConstant(0, PtrVT); |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 1039 | |
| 1040 | const TargetMachine &TM = DAG.getTarget(); |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1041 | |
| 1042 | SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); |
| 1043 | SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); |
| 1044 | |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 1045 | // If this is a non-darwin platform, we don't support non-static relo models |
| 1046 | // yet. |
| 1047 | if (TM.getRelocationModel() == Reloc::Static || |
| 1048 | !TM.getSubtarget<PPCSubtarget>().isDarwin()) { |
| 1049 | // Generate non-pic code that has direct accesses to the constant pool. |
| 1050 | // The address of the global is just (hi(&g)+lo(&g)). |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1051 | return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 1052 | } |
| 1053 | |
Chris Lattner | 35d86fe | 2006-07-26 21:12:04 +0000 | [diff] [blame] | 1054 | if (TM.getRelocationModel() == Reloc::PIC_) { |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 1055 | // With PIC, the first instruction is actually "GR+hi(&G)". |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1056 | Hi = DAG.getNode(ISD::ADD, PtrVT, |
Chris Lattner | 0d72a20 | 2006-07-28 16:45:47 +0000 | [diff] [blame] | 1057 | DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 1058 | } |
| 1059 | |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1060 | Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 1061 | return Lo; |
| 1062 | } |
| 1063 | |
Lauro Ramos Venancio | 75ce010 | 2007-07-11 17:19:51 +0000 | [diff] [blame] | 1064 | static SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { |
| 1065 | assert(0 && "TLS not implemented for PPC."); |
| 1066 | } |
| 1067 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1068 | static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1069 | MVT::ValueType PtrVT = Op.getValueType(); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1070 | GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); |
| 1071 | GlobalValue *GV = GSDN->getGlobal(); |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1072 | SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); |
| 1073 | SDOperand Zero = DAG.getConstant(0, PtrVT); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1074 | |
| 1075 | const TargetMachine &TM = DAG.getTarget(); |
| 1076 | |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1077 | SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); |
| 1078 | SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); |
| 1079 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1080 | // If this is a non-darwin platform, we don't support non-static relo models |
| 1081 | // yet. |
| 1082 | if (TM.getRelocationModel() == Reloc::Static || |
| 1083 | !TM.getSubtarget<PPCSubtarget>().isDarwin()) { |
| 1084 | // Generate non-pic code that has direct accesses to globals. |
| 1085 | // The address of the global is just (hi(&g)+lo(&g)). |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1086 | return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1087 | } |
| 1088 | |
Chris Lattner | 35d86fe | 2006-07-26 21:12:04 +0000 | [diff] [blame] | 1089 | if (TM.getRelocationModel() == Reloc::PIC_) { |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1090 | // With PIC, the first instruction is actually "GR+hi(&G)". |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1091 | Hi = DAG.getNode(ISD::ADD, PtrVT, |
| 1092 | DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1093 | } |
| 1094 | |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1095 | Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1096 | |
Chris Lattner | 57fc62c | 2006-12-11 23:22:45 +0000 | [diff] [blame] | 1097 | if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV)) |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1098 | return Lo; |
| 1099 | |
| 1100 | // If the global is weak or external, we have to go through the lazy |
| 1101 | // resolution stub. |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 1102 | return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1103 | } |
| 1104 | |
| 1105 | static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) { |
| 1106 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); |
| 1107 | |
| 1108 | // If we're comparing for equality to zero, expose the fact that this is |
| 1109 | // implented as a ctlz/srl pair on ppc, so that the dag combiner can |
| 1110 | // fold the new nodes. |
| 1111 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { |
| 1112 | if (C->isNullValue() && CC == ISD::SETEQ) { |
| 1113 | MVT::ValueType VT = Op.getOperand(0).getValueType(); |
| 1114 | SDOperand Zext = Op.getOperand(0); |
| 1115 | if (VT < MVT::i32) { |
| 1116 | VT = MVT::i32; |
| 1117 | Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); |
| 1118 | } |
| 1119 | unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); |
| 1120 | SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); |
| 1121 | SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, |
| 1122 | DAG.getConstant(Log2b, MVT::i32)); |
| 1123 | return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); |
| 1124 | } |
| 1125 | // Leave comparisons against 0 and -1 alone for now, since they're usually |
| 1126 | // optimized. FIXME: revisit this when we can custom lower all setcc |
| 1127 | // optimizations. |
| 1128 | if (C->isAllOnesValue() || C->isNullValue()) |
| 1129 | return SDOperand(); |
| 1130 | } |
| 1131 | |
| 1132 | // If we have an integer seteq/setne, turn it into a compare against zero |
Chris Lattner | ac011bc | 2006-11-14 05:28:08 +0000 | [diff] [blame] | 1133 | // by xor'ing the rhs with the lhs, which is faster than setting a |
| 1134 | // condition register, reading it back out, and masking the correct bit. The |
| 1135 | // normal approach here uses sub to do this instead of xor. Using xor exposes |
| 1136 | // the result to other bit-twiddling opportunities. |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1137 | MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); |
| 1138 | if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { |
| 1139 | MVT::ValueType VT = Op.getValueType(); |
Chris Lattner | ac011bc | 2006-11-14 05:28:08 +0000 | [diff] [blame] | 1140 | SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1141 | Op.getOperand(1)); |
| 1142 | return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); |
| 1143 | } |
| 1144 | return SDOperand(); |
| 1145 | } |
| 1146 | |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1147 | static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG, |
| 1148 | int VarArgsFrameIndex, |
| 1149 | int VarArgsStackOffset, |
| 1150 | unsigned VarArgsNumGPR, |
| 1151 | unsigned VarArgsNumFPR, |
| 1152 | const PPCSubtarget &Subtarget) { |
| 1153 | |
| 1154 | assert(0 && "VAARG in ELF32 ABI not implemented yet!"); |
| 1155 | } |
| 1156 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1157 | static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1158 | int VarArgsFrameIndex, |
| 1159 | int VarArgsStackOffset, |
| 1160 | unsigned VarArgsNumGPR, |
| 1161 | unsigned VarArgsNumFPR, |
| 1162 | const PPCSubtarget &Subtarget) { |
| 1163 | |
| 1164 | if (Subtarget.isMachoABI()) { |
| 1165 | // vastart just stores the address of the VarArgsFrameIndex slot into the |
| 1166 | // memory location argument. |
| 1167 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 1168 | SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); |
| 1169 | SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); |
| 1170 | return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), |
| 1171 | SV->getOffset()); |
| 1172 | } |
| 1173 | |
| 1174 | // For ELF 32 ABI we follow the layout of the va_list struct. |
| 1175 | // We suppose the given va_list is already allocated. |
| 1176 | // |
| 1177 | // typedef struct { |
| 1178 | // char gpr; /* index into the array of 8 GPRs |
| 1179 | // * stored in the register save area |
| 1180 | // * gpr=0 corresponds to r3, |
| 1181 | // * gpr=1 to r4, etc. |
| 1182 | // */ |
| 1183 | // char fpr; /* index into the array of 8 FPRs |
| 1184 | // * stored in the register save area |
| 1185 | // * fpr=0 corresponds to f1, |
| 1186 | // * fpr=1 to f2, etc. |
| 1187 | // */ |
| 1188 | // char *overflow_arg_area; |
| 1189 | // /* location on stack that holds |
| 1190 | // * the next overflow argument |
| 1191 | // */ |
| 1192 | // char *reg_save_area; |
| 1193 | // /* where r3:r10 and f1:f8 (if saved) |
| 1194 | // * are stored |
| 1195 | // */ |
| 1196 | // } va_list[1]; |
| 1197 | |
| 1198 | |
| 1199 | SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8); |
| 1200 | SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8); |
| 1201 | |
| 1202 | |
Chris Lattner | 0d72a20 | 2006-07-28 16:45:47 +0000 | [diff] [blame] | 1203 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1204 | |
| 1205 | SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); |
Chris Lattner | 0d72a20 | 2006-07-28 16:45:47 +0000 | [diff] [blame] | 1206 | SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1207 | |
| 1208 | SDOperand ConstFrameOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, |
| 1209 | PtrVT); |
| 1210 | SDOperand ConstStackOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1, |
| 1211 | PtrVT); |
| 1212 | SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT); |
| 1213 | |
Evan Cheng | 8b2794a | 2006-10-13 21:14:26 +0000 | [diff] [blame] | 1214 | SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1215 | |
| 1216 | // Store first byte : number of int regs |
| 1217 | SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, |
| 1218 | Op.getOperand(1), SV->getValue(), |
| 1219 | SV->getOffset()); |
| 1220 | SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), |
| 1221 | ConstFPROffset); |
| 1222 | |
| 1223 | // Store second byte : number of float regs |
| 1224 | SDOperand secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr, |
| 1225 | SV->getValue(), SV->getOffset()); |
| 1226 | nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); |
| 1227 | |
| 1228 | // Store second word : arguments given on stack |
| 1229 | SDOperand thirdStore = DAG.getStore(secondStore, StackOffset, nextPtr, |
| 1230 | SV->getValue(), SV->getOffset()); |
| 1231 | nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); |
| 1232 | |
| 1233 | // Store third word : arguments given in registers |
| 1234 | return DAG.getStore(thirdStore, FR, nextPtr, SV->getValue(), |
Evan Cheng | 8b2794a | 2006-10-13 21:14:26 +0000 | [diff] [blame] | 1235 | SV->getOffset()); |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1236 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1237 | } |
| 1238 | |
Chris Lattner | b9a7bea | 2007-03-06 00:59:59 +0000 | [diff] [blame] | 1239 | #include "PPCGenCallingConv.inc" |
| 1240 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1241 | /// GetFPR - Get the set of FP registers that should be allocated for arguments, |
| 1242 | /// depending on which subtarget is selected. |
| 1243 | static const unsigned *GetFPR(const PPCSubtarget &Subtarget) { |
| 1244 | if (Subtarget.isMachoABI()) { |
| 1245 | static const unsigned FPR[] = { |
| 1246 | PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, |
| 1247 | PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 |
| 1248 | }; |
| 1249 | return FPR; |
| 1250 | } |
| 1251 | |
| 1252 | |
| 1253 | static const unsigned FPR[] = { |
| 1254 | PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, |
Nicolas Geoffray | ef3c030 | 2007-04-03 10:27:07 +0000 | [diff] [blame] | 1255 | PPC::F8 |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1256 | }; |
| 1257 | return FPR; |
| 1258 | } |
| 1259 | |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1260 | static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1261 | int &VarArgsFrameIndex, |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1262 | int &VarArgsStackOffset, |
| 1263 | unsigned &VarArgsNumGPR, |
| 1264 | unsigned &VarArgsNumFPR, |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1265 | const PPCSubtarget &Subtarget) { |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1266 | // TODO: add description of PPC stack frame format, or at least some docs. |
| 1267 | // |
| 1268 | MachineFunction &MF = DAG.getMachineFunction(); |
| 1269 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 1270 | SSARegMap *RegMap = MF.getSSARegMap(); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 1271 | SmallVector<SDOperand, 8> ArgValues; |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1272 | SDOperand Root = Op.getOperand(0); |
| 1273 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1274 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 1275 | bool isPPC64 = PtrVT == MVT::i64; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1276 | bool isMachoABI = Subtarget.isMachoABI(); |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1277 | bool isELF32_ABI = Subtarget.isELF32_ABI(); |
Jim Laskey | e9bd7b2 | 2006-11-28 14:53:52 +0000 | [diff] [blame] | 1278 | unsigned PtrByteSize = isPPC64 ? 8 : 4; |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1279 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1280 | unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1281 | |
| 1282 | static const unsigned GPR_32[] = { // 32-bit registers. |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1283 | PPC::R3, PPC::R4, PPC::R5, PPC::R6, |
| 1284 | PPC::R7, PPC::R8, PPC::R9, PPC::R10, |
| 1285 | }; |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1286 | static const unsigned GPR_64[] = { // 64-bit registers. |
| 1287 | PPC::X3, PPC::X4, PPC::X5, PPC::X6, |
| 1288 | PPC::X7, PPC::X8, PPC::X9, PPC::X10, |
| 1289 | }; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1290 | |
| 1291 | static const unsigned *FPR = GetFPR(Subtarget); |
| 1292 | |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1293 | static const unsigned VR[] = { |
| 1294 | PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, |
| 1295 | PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 |
| 1296 | }; |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1297 | |
Owen Anderson | 718cb66 | 2007-09-07 04:06:50 +0000 | [diff] [blame] | 1298 | const unsigned Num_GPR_Regs = array_lengthof(GPR_32); |
Nicolas Geoffray | ef3c030 | 2007-04-03 10:27:07 +0000 | [diff] [blame] | 1299 | const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8; |
Owen Anderson | 718cb66 | 2007-09-07 04:06:50 +0000 | [diff] [blame] | 1300 | const unsigned Num_VR_Regs = array_lengthof( VR); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1301 | |
| 1302 | unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; |
| 1303 | |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1304 | const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1305 | |
| 1306 | // Add DAG nodes to load the arguments or copy them out of registers. On |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1307 | // entry to a function on PPC, the arguments start after the linkage area, |
| 1308 | // although the first ones are often in registers. |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1309 | // |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1310 | // In the ELF 32 ABI, GPRs and stack are double word align: an argument |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1311 | // represented with two words (long long or double) must be copied to an |
| 1312 | // even GPR_idx value or to an even ArgOffset value. |
| 1313 | |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1314 | for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { |
| 1315 | SDOperand ArgVal; |
| 1316 | bool needsLoad = false; |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1317 | MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); |
| 1318 | unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; |
Jim Laskey | 619965d | 2006-11-29 13:37:09 +0000 | [diff] [blame] | 1319 | unsigned ArgSize = ObjSize; |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1320 | unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue(); |
| 1321 | unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs; |
| 1322 | // See if next argument requires stack alignment in ELF |
| 1323 | bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) && |
| 1324 | (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) && |
| 1325 | (!(Flags & AlignFlag))); |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1326 | |
Chris Lattner | be4849a | 2006-05-16 18:51:52 +0000 | [diff] [blame] | 1327 | unsigned CurArgOffset = ArgOffset; |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1328 | switch (ObjectVT) { |
| 1329 | default: assert(0 && "Unhandled argument type!"); |
| 1330 | case MVT::i32: |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1331 | // Double word align in ELF |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1332 | if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2); |
Chris Lattner | af4ec0c | 2006-05-16 18:58:15 +0000 | [diff] [blame] | 1333 | if (GPR_idx != Num_GPR_Regs) { |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1334 | unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); |
| 1335 | MF.addLiveIn(GPR[GPR_idx], VReg); |
| 1336 | ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); |
Chris Lattner | be4849a | 2006-05-16 18:51:52 +0000 | [diff] [blame] | 1337 | ++GPR_idx; |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1338 | } else { |
| 1339 | needsLoad = true; |
Jim Laskey | 619965d | 2006-11-29 13:37:09 +0000 | [diff] [blame] | 1340 | ArgSize = PtrByteSize; |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1341 | } |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1342 | // Stack align in ELF |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1343 | if (needsLoad && Expand && isELF32_ABI) |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1344 | ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1345 | // All int arguments reserve stack space in Macho ABI. |
| 1346 | if (isMachoABI || needsLoad) ArgOffset += PtrByteSize; |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1347 | break; |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1348 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1349 | case MVT::i64: // PPC64 |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1350 | if (GPR_idx != Num_GPR_Regs) { |
| 1351 | unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); |
| 1352 | MF.addLiveIn(GPR[GPR_idx], VReg); |
| 1353 | ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); |
| 1354 | ++GPR_idx; |
| 1355 | } else { |
| 1356 | needsLoad = true; |
| 1357 | } |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1358 | // All int arguments reserve stack space in Macho ABI. |
| 1359 | if (isMachoABI || needsLoad) ArgOffset += 8; |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1360 | break; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1361 | |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1362 | case MVT::f32: |
| 1363 | case MVT::f64: |
Chris Lattner | be4849a | 2006-05-16 18:51:52 +0000 | [diff] [blame] | 1364 | // Every 4 bytes of argument space consumes one of the GPRs available for |
| 1365 | // argument passing. |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1366 | if (GPR_idx != Num_GPR_Regs && isMachoABI) { |
Chris Lattner | af4ec0c | 2006-05-16 18:58:15 +0000 | [diff] [blame] | 1367 | ++GPR_idx; |
Chris Lattner | b1eb987 | 2006-11-18 01:57:19 +0000 | [diff] [blame] | 1368 | if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) |
Chris Lattner | af4ec0c | 2006-05-16 18:58:15 +0000 | [diff] [blame] | 1369 | ++GPR_idx; |
Chris Lattner | be4849a | 2006-05-16 18:51:52 +0000 | [diff] [blame] | 1370 | } |
Chris Lattner | af4ec0c | 2006-05-16 18:58:15 +0000 | [diff] [blame] | 1371 | if (FPR_idx != Num_FPR_Regs) { |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1372 | unsigned VReg; |
| 1373 | if (ObjectVT == MVT::f32) |
| 1374 | VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); |
| 1375 | else |
| 1376 | VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); |
| 1377 | MF.addLiveIn(FPR[FPR_idx], VReg); |
| 1378 | ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1379 | ++FPR_idx; |
| 1380 | } else { |
| 1381 | needsLoad = true; |
| 1382 | } |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1383 | |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1384 | // Stack align in ELF |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1385 | if (needsLoad && Expand && isELF32_ABI) |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1386 | ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1387 | // All FP arguments reserve stack space in Macho ABI. |
| 1388 | if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize; |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1389 | break; |
| 1390 | case MVT::v4f32: |
| 1391 | case MVT::v4i32: |
| 1392 | case MVT::v8i16: |
| 1393 | case MVT::v16i8: |
Chris Lattner | be4849a | 2006-05-16 18:51:52 +0000 | [diff] [blame] | 1394 | // Note that vector arguments in registers don't reserve stack space. |
Chris Lattner | af4ec0c | 2006-05-16 18:58:15 +0000 | [diff] [blame] | 1395 | if (VR_idx != Num_VR_Regs) { |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1396 | unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass); |
| 1397 | MF.addLiveIn(VR[VR_idx], VReg); |
| 1398 | ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1399 | ++VR_idx; |
| 1400 | } else { |
| 1401 | // This should be simple, but requires getting 16-byte aligned stack |
| 1402 | // values. |
| 1403 | assert(0 && "Loading VR argument not implemented yet!"); |
| 1404 | needsLoad = true; |
| 1405 | } |
| 1406 | break; |
| 1407 | } |
| 1408 | |
| 1409 | // We need to load the argument to a virtual register if we determined above |
| 1410 | // that we ran out of physical registers of the appropriate type |
| 1411 | if (needsLoad) { |
Chris Lattner | b375b5e | 2006-05-16 18:54:32 +0000 | [diff] [blame] | 1412 | // If the argument is actually used, emit a load from the right stack |
| 1413 | // slot. |
| 1414 | if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { |
Jim Laskey | 619965d | 2006-11-29 13:37:09 +0000 | [diff] [blame] | 1415 | int FI = MFI->CreateFixedObject(ObjSize, |
| 1416 | CurArgOffset + (ArgSize - ObjSize)); |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1417 | SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 1418 | ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); |
Chris Lattner | b375b5e | 2006-05-16 18:54:32 +0000 | [diff] [blame] | 1419 | } else { |
| 1420 | // Don't emit a dead load. |
| 1421 | ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT); |
| 1422 | } |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1423 | } |
| 1424 | |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1425 | ArgValues.push_back(ArgVal); |
| 1426 | } |
| 1427 | |
| 1428 | // If the function takes variable number of arguments, make a frame index for |
| 1429 | // the start of the first vararg value... for expansion of llvm.va_start. |
| 1430 | bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; |
| 1431 | if (isVarArg) { |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1432 | |
| 1433 | int depth; |
| 1434 | if (isELF32_ABI) { |
| 1435 | VarArgsNumGPR = GPR_idx; |
| 1436 | VarArgsNumFPR = FPR_idx; |
| 1437 | |
| 1438 | // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame |
| 1439 | // pointer. |
| 1440 | depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 + |
| 1441 | Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 + |
| 1442 | MVT::getSizeInBits(PtrVT)/8); |
| 1443 | |
| 1444 | VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, |
| 1445 | ArgOffset); |
| 1446 | |
| 1447 | } |
| 1448 | else |
| 1449 | depth = ArgOffset; |
| 1450 | |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1451 | VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1452 | depth); |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1453 | SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1454 | |
| 1455 | SmallVector<SDOperand, 8> MemOps; |
| 1456 | |
| 1457 | // In ELF 32 ABI, the fixed integer arguments of a variadic function are |
| 1458 | // stored to the VarArgsFrameIndex on the stack. |
| 1459 | if (isELF32_ABI) { |
| 1460 | for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) { |
| 1461 | SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT); |
| 1462 | SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); |
| 1463 | MemOps.push_back(Store); |
| 1464 | // Increment the address by four for the next argument to store |
| 1465 | SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); |
| 1466 | FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); |
| 1467 | } |
| 1468 | } |
| 1469 | |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1470 | // If this function is vararg, store any remaining integer argument regs |
| 1471 | // to their spots on the stack so that they may be loaded by deferencing the |
| 1472 | // result of va_next. |
Chris Lattner | af4ec0c | 2006-05-16 18:58:15 +0000 | [diff] [blame] | 1473 | for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { |
Chris Lattner | b1eb987 | 2006-11-18 01:57:19 +0000 | [diff] [blame] | 1474 | unsigned VReg; |
| 1475 | if (isPPC64) |
| 1476 | VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); |
| 1477 | else |
| 1478 | VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); |
| 1479 | |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1480 | MF.addLiveIn(GPR[GPR_idx], VReg); |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1481 | SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); |
Evan Cheng | 8b2794a | 2006-10-13 21:14:26 +0000 | [diff] [blame] | 1482 | SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1483 | MemOps.push_back(Store); |
| 1484 | // Increment the address by four for the next argument to store |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1485 | SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); |
| 1486 | FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1487 | } |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1488 | |
| 1489 | // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex |
| 1490 | // on the stack. |
| 1491 | if (isELF32_ABI) { |
| 1492 | for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) { |
| 1493 | SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64); |
| 1494 | SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); |
| 1495 | MemOps.push_back(Store); |
| 1496 | // Increment the address by eight for the next argument to store |
| 1497 | SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, |
| 1498 | PtrVT); |
| 1499 | FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); |
| 1500 | } |
| 1501 | |
| 1502 | for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) { |
| 1503 | unsigned VReg; |
| 1504 | VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); |
| 1505 | |
| 1506 | MF.addLiveIn(FPR[FPR_idx], VReg); |
| 1507 | SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64); |
| 1508 | SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); |
| 1509 | MemOps.push_back(Store); |
| 1510 | // Increment the address by eight for the next argument to store |
| 1511 | SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, |
| 1512 | PtrVT); |
| 1513 | FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); |
| 1514 | } |
| 1515 | } |
| 1516 | |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1517 | if (!MemOps.empty()) |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 1518 | Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1519 | } |
| 1520 | |
| 1521 | ArgValues.push_back(Root); |
| 1522 | |
| 1523 | // Return the new list of results. |
| 1524 | std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), |
| 1525 | Op.Val->value_end()); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 1526 | return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1527 | } |
| 1528 | |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 1529 | /// isCallCompatibleAddress - Return the immediate to use if the specified |
| 1530 | /// 32-bit value is representable in the immediate field of a BxA instruction. |
| 1531 | static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) { |
| 1532 | ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); |
| 1533 | if (!C) return 0; |
| 1534 | |
| 1535 | int Addr = C->getValue(); |
| 1536 | if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. |
| 1537 | (Addr << 6 >> 6) != Addr) |
| 1538 | return 0; // Top 6 bits have to be sext of immediate. |
| 1539 | |
| 1540 | return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val; |
| 1541 | } |
| 1542 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1543 | |
| 1544 | static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, |
| 1545 | const PPCSubtarget &Subtarget) { |
| 1546 | SDOperand Chain = Op.getOperand(0); |
| 1547 | bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; |
| 1548 | SDOperand Callee = Op.getOperand(4); |
| 1549 | unsigned NumOps = (Op.getNumOperands() - 5) / 2; |
| 1550 | |
| 1551 | bool isMachoABI = Subtarget.isMachoABI(); |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1552 | bool isELF32_ABI = Subtarget.isELF32_ABI(); |
Evan Cheng | 4360bdc | 2006-05-25 00:57:32 +0000 | [diff] [blame] | 1553 | |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1554 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 1555 | bool isPPC64 = PtrVT == MVT::i64; |
| 1556 | unsigned PtrByteSize = isPPC64 ? 8 : 4; |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1557 | |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 1558 | // args_to_use will accumulate outgoing args for the PPCISD::CALL case in |
| 1559 | // SelectExpr to use to put the arguments in the appropriate registers. |
| 1560 | std::vector<SDOperand> args_to_use; |
| 1561 | |
| 1562 | // Count how many bytes are to be pushed on the stack, including the linkage |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1563 | // area, and parameter passing area. We start with 24/48 bytes, which is |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1564 | // prereserved space for [SP][CR][LR][3 x unused]. |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1565 | unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 1566 | |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1567 | // Add up all the space actually used. |
Jim Laskey | e9bd7b2 | 2006-11-28 14:53:52 +0000 | [diff] [blame] | 1568 | for (unsigned i = 0; i != NumOps; ++i) { |
| 1569 | unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8; |
| 1570 | ArgSize = std::max(ArgSize, PtrByteSize); |
| 1571 | NumBytes += ArgSize; |
| 1572 | } |
Chris Lattner | c04ba7a | 2006-05-16 23:54:25 +0000 | [diff] [blame] | 1573 | |
Chris Lattner | 7b05350 | 2006-05-30 21:21:04 +0000 | [diff] [blame] | 1574 | // The prolog code of the callee may store up to 8 GPR argument registers to |
| 1575 | // the stack, allowing va_start to index over them in memory if its varargs. |
| 1576 | // Because we cannot tell if this is needed on the caller side, we have to |
| 1577 | // conservatively assume that it is needed. As such, make sure we have at |
| 1578 | // least enough stack space for the caller to store the 8 GPRs. |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1579 | NumBytes = std::max(NumBytes, |
| 1580 | PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI)); |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1581 | |
| 1582 | // Adjust the stack pointer for the new arguments... |
| 1583 | // These operations are automatically eliminated by the prolog/epilog pass |
| 1584 | Chain = DAG.getCALLSEQ_START(Chain, |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1585 | DAG.getConstant(NumBytes, PtrVT)); |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1586 | |
| 1587 | // Set up a copy of the stack pointer for use loading and storing any |
| 1588 | // arguments that may not fit in the registers available for argument |
| 1589 | // passing. |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1590 | SDOperand StackPtr; |
| 1591 | if (isPPC64) |
| 1592 | StackPtr = DAG.getRegister(PPC::X1, MVT::i64); |
| 1593 | else |
| 1594 | StackPtr = DAG.getRegister(PPC::R1, MVT::i32); |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1595 | |
| 1596 | // Figure out which arguments are going to go in registers, and which in |
| 1597 | // memory. Also, if this is a vararg function, floating point operations |
| 1598 | // must be stored to our stack, and loaded into integer regs as well, if |
| 1599 | // any integer regs are available for argument passing. |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1600 | unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1601 | unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1602 | |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1603 | static const unsigned GPR_32[] = { // 32-bit registers. |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1604 | PPC::R3, PPC::R4, PPC::R5, PPC::R6, |
| 1605 | PPC::R7, PPC::R8, PPC::R9, PPC::R10, |
| 1606 | }; |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1607 | static const unsigned GPR_64[] = { // 64-bit registers. |
| 1608 | PPC::X3, PPC::X4, PPC::X5, PPC::X6, |
| 1609 | PPC::X7, PPC::X8, PPC::X9, PPC::X10, |
| 1610 | }; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1611 | static const unsigned *FPR = GetFPR(Subtarget); |
| 1612 | |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1613 | static const unsigned VR[] = { |
| 1614 | PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, |
| 1615 | PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 |
| 1616 | }; |
Owen Anderson | 718cb66 | 2007-09-07 04:06:50 +0000 | [diff] [blame] | 1617 | const unsigned NumGPRs = array_lengthof(GPR_32); |
Nicolas Geoffray | ef3c030 | 2007-04-03 10:27:07 +0000 | [diff] [blame] | 1618 | const unsigned NumFPRs = isMachoABI ? 13 : 8; |
Owen Anderson | 718cb66 | 2007-09-07 04:06:50 +0000 | [diff] [blame] | 1619 | const unsigned NumVRs = array_lengthof( VR); |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1620 | |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1621 | const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; |
| 1622 | |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1623 | std::vector<std::pair<unsigned, SDOperand> > RegsToPass; |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 1624 | SmallVector<SDOperand, 8> MemOpChains; |
Evan Cheng | 4360bdc | 2006-05-25 00:57:32 +0000 | [diff] [blame] | 1625 | for (unsigned i = 0; i != NumOps; ++i) { |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1626 | bool inMem = false; |
Evan Cheng | 4360bdc | 2006-05-25 00:57:32 +0000 | [diff] [blame] | 1627 | SDOperand Arg = Op.getOperand(5+2*i); |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1628 | unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue(); |
| 1629 | unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs; |
| 1630 | // See if next argument requires stack alignment in ELF |
| 1631 | unsigned next = 5+2*(i+1)+1; |
| 1632 | bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) && |
| 1633 | (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) && |
| 1634 | (!(Flags & AlignFlag))); |
| 1635 | |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1636 | // PtrOff will be used to store the current argument to the stack if a |
| 1637 | // register cannot be found for it. |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1638 | SDOperand PtrOff; |
| 1639 | |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1640 | // Stack align in ELF 32 |
| 1641 | if (isELF32_ABI && Expand) |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1642 | PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize, |
| 1643 | StackPtr.getValueType()); |
| 1644 | else |
| 1645 | PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); |
| 1646 | |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1647 | PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); |
| 1648 | |
| 1649 | // On PPC64, promote integers to 64-bit values. |
| 1650 | if (isPPC64 && Arg.getValueType() == MVT::i32) { |
Anton Korobeynikov | b10308e | 2007-01-28 13:31:35 +0000 | [diff] [blame] | 1651 | unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; |
| 1652 | |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1653 | Arg = DAG.getNode(ExtOp, MVT::i64, Arg); |
| 1654 | } |
| 1655 | |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1656 | switch (Arg.getValueType()) { |
| 1657 | default: assert(0 && "Unexpected ValueType for argument!"); |
| 1658 | case MVT::i32: |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1659 | case MVT::i64: |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1660 | // Double word align in ELF |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1661 | if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2); |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1662 | if (GPR_idx != NumGPRs) { |
| 1663 | RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1664 | } else { |
Evan Cheng | 8b2794a | 2006-10-13 21:14:26 +0000 | [diff] [blame] | 1665 | MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1666 | inMem = true; |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1667 | } |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1668 | if (inMem || isMachoABI) { |
| 1669 | // Stack align in ELF |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1670 | if (isELF32_ABI && Expand) |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1671 | ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; |
| 1672 | |
| 1673 | ArgOffset += PtrByteSize; |
| 1674 | } |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1675 | break; |
| 1676 | case MVT::f32: |
| 1677 | case MVT::f64: |
Chris Lattner | 4ddf7a4 | 2007-02-25 20:01:40 +0000 | [diff] [blame] | 1678 | if (isVarArg) { |
Jim Laskey | fbb74e6 | 2006-12-01 16:30:47 +0000 | [diff] [blame] | 1679 | // Float varargs need to be promoted to double. |
| 1680 | if (Arg.getValueType() == MVT::f32) |
| 1681 | Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg); |
| 1682 | } |
| 1683 | |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1684 | if (FPR_idx != NumFPRs) { |
| 1685 | RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); |
| 1686 | |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1687 | if (isVarArg) { |
Evan Cheng | 8b2794a | 2006-10-13 21:14:26 +0000 | [diff] [blame] | 1688 | SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1689 | MemOpChains.push_back(Store); |
| 1690 | |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1691 | // Float varargs are always shadowed in available integer registers |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1692 | if (GPR_idx != NumGPRs) { |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 1693 | SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1694 | MemOpChains.push_back(Load.getValue(1)); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1695 | if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], |
| 1696 | Load)); |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1697 | } |
Jim Laskey | fbb74e6 | 2006-12-01 16:30:47 +0000 | [diff] [blame] | 1698 | if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1699 | SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1700 | PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 1701 | SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1702 | MemOpChains.push_back(Load.getValue(1)); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1703 | if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], |
| 1704 | Load)); |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 1705 | } |
| 1706 | } else { |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1707 | // If we have any FPRs remaining, we may also have GPRs remaining. |
| 1708 | // Args passed in FPRs consume either 1 (f32) or 2 (f64) available |
| 1709 | // GPRs. |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1710 | if (isMachoABI) { |
| 1711 | if (GPR_idx != NumGPRs) |
| 1712 | ++GPR_idx; |
| 1713 | if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && |
| 1714 | !isPPC64) // PPC64 has 64-bit GPR's obviously :) |
| 1715 | ++GPR_idx; |
| 1716 | } |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 1717 | } |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1718 | } else { |
Evan Cheng | 8b2794a | 2006-10-13 21:14:26 +0000 | [diff] [blame] | 1719 | MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1720 | inMem = true; |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 1721 | } |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1722 | if (inMem || isMachoABI) { |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1723 | // Stack align in ELF |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1724 | if (isELF32_ABI && Expand) |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1725 | ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1726 | if (isPPC64) |
| 1727 | ArgOffset += 8; |
| 1728 | else |
| 1729 | ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; |
| 1730 | } |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1731 | break; |
| 1732 | case MVT::v4f32: |
| 1733 | case MVT::v4i32: |
| 1734 | case MVT::v8i16: |
| 1735 | case MVT::v16i8: |
| 1736 | assert(!isVarArg && "Don't support passing vectors to varargs yet!"); |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1737 | assert(VR_idx != NumVRs && |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1738 | "Don't support passing more than 12 vector args yet!"); |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1739 | RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1740 | break; |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 1741 | } |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 1742 | } |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1743 | if (!MemOpChains.empty()) |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 1744 | Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, |
| 1745 | &MemOpChains[0], MemOpChains.size()); |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 1746 | |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1747 | // Build a sequence of copy-to-reg nodes chained together with token chain |
| 1748 | // and flag operands which copy the outgoing args into the appropriate regs. |
| 1749 | SDOperand InFlag; |
| 1750 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { |
| 1751 | Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, |
| 1752 | InFlag); |
| 1753 | InFlag = Chain.getValue(1); |
| 1754 | } |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1755 | |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1756 | // With the ELF 32 ABI, set CR6 to true if this is a vararg call. |
| 1757 | if (isVarArg && isELF32_ABI) { |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1758 | SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0); |
| 1759 | Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag); |
| 1760 | InFlag = Chain.getValue(1); |
| 1761 | } |
| 1762 | |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 1763 | std::vector<MVT::ValueType> NodeTys; |
Chris Lattner | 4a45abf | 2006-06-10 01:14:28 +0000 | [diff] [blame] | 1764 | NodeTys.push_back(MVT::Other); // Returns a chain |
| 1765 | NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. |
| 1766 | |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 1767 | SmallVector<SDOperand, 8> Ops; |
Nicolas Geoffray | 63f8fb1 | 2007-02-27 13:01:19 +0000 | [diff] [blame] | 1768 | unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF; |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 1769 | |
| 1770 | // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every |
| 1771 | // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol |
| 1772 | // node so that legalize doesn't hack it. |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 1773 | if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1774 | Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 1775 | else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) |
| 1776 | Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); |
| 1777 | else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) |
| 1778 | // If this is an absolute destination address, use the munged value. |
| 1779 | Callee = SDOperand(Dest, 0); |
| 1780 | else { |
| 1781 | // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair |
| 1782 | // to do the call, we can't use PPCISD::CALL. |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 1783 | SDOperand MTCTROps[] = {Chain, Callee, InFlag}; |
| 1784 | Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0)); |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 1785 | InFlag = Chain.getValue(1); |
| 1786 | |
| 1787 | // Copy the callee address into R12 on darwin. |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1788 | if (isMachoABI) { |
| 1789 | Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag); |
| 1790 | InFlag = Chain.getValue(1); |
| 1791 | } |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 1792 | |
| 1793 | NodeTys.clear(); |
| 1794 | NodeTys.push_back(MVT::Other); |
| 1795 | NodeTys.push_back(MVT::Flag); |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 1796 | Ops.push_back(Chain); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1797 | CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF; |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 1798 | Callee.Val = 0; |
| 1799 | } |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1800 | |
Chris Lattner | 4a45abf | 2006-06-10 01:14:28 +0000 | [diff] [blame] | 1801 | // If this is a direct call, pass the chain and the callee. |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 1802 | if (Callee.Val) { |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 1803 | Ops.push_back(Chain); |
| 1804 | Ops.push_back(Callee); |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 1805 | } |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 1806 | |
Chris Lattner | 4a45abf | 2006-06-10 01:14:28 +0000 | [diff] [blame] | 1807 | // Add argument registers to the end of the list so that they are known live |
| 1808 | // into the call. |
| 1809 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) |
| 1810 | Ops.push_back(DAG.getRegister(RegsToPass[i].first, |
| 1811 | RegsToPass[i].second.getValueType())); |
| 1812 | |
| 1813 | if (InFlag.Val) |
| 1814 | Ops.push_back(InFlag); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 1815 | Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); |
Chris Lattner | 4a45abf | 2006-06-10 01:14:28 +0000 | [diff] [blame] | 1816 | InFlag = Chain.getValue(1); |
| 1817 | |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 1818 | SDOperand ResultVals[3]; |
| 1819 | unsigned NumResults = 0; |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1820 | NodeTys.clear(); |
| 1821 | |
| 1822 | // If the call has results, copy the values out of the ret val registers. |
| 1823 | switch (Op.Val->getValueType(0)) { |
| 1824 | default: assert(0 && "Unexpected ret value!"); |
| 1825 | case MVT::Other: break; |
| 1826 | case MVT::i32: |
| 1827 | if (Op.Val->getValueType(1) == MVT::i32) { |
Dan Gohman | 532dc2e | 2007-07-09 20:59:04 +0000 | [diff] [blame] | 1828 | Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 1829 | ResultVals[0] = Chain.getValue(0); |
Dan Gohman | 532dc2e | 2007-07-09 20:59:04 +0000 | [diff] [blame] | 1830 | Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1831 | Chain.getValue(2)).getValue(1); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 1832 | ResultVals[1] = Chain.getValue(0); |
| 1833 | NumResults = 2; |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1834 | NodeTys.push_back(MVT::i32); |
| 1835 | } else { |
| 1836 | Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 1837 | ResultVals[0] = Chain.getValue(0); |
| 1838 | NumResults = 1; |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1839 | } |
| 1840 | NodeTys.push_back(MVT::i32); |
| 1841 | break; |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1842 | case MVT::i64: |
| 1843 | Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 1844 | ResultVals[0] = Chain.getValue(0); |
| 1845 | NumResults = 1; |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1846 | NodeTys.push_back(MVT::i64); |
| 1847 | break; |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1848 | case MVT::f64: |
Dale Johannesen | 161e897 | 2007-10-05 20:04:43 +0000 | [diff] [blame] | 1849 | if (Op.Val->getValueType(1) == MVT::f64) { |
| 1850 | Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1); |
| 1851 | ResultVals[0] = Chain.getValue(0); |
| 1852 | Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64, |
| 1853 | Chain.getValue(2)).getValue(1); |
| 1854 | ResultVals[1] = Chain.getValue(0); |
| 1855 | NumResults = 2; |
| 1856 | NodeTys.push_back(MVT::f64); |
| 1857 | NodeTys.push_back(MVT::f64); |
| 1858 | break; |
| 1859 | } |
| 1860 | // else fall through |
| 1861 | case MVT::f32: |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1862 | Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0), |
| 1863 | InFlag).getValue(1); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 1864 | ResultVals[0] = Chain.getValue(0); |
| 1865 | NumResults = 1; |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1866 | NodeTys.push_back(Op.Val->getValueType(0)); |
| 1867 | break; |
| 1868 | case MVT::v4f32: |
| 1869 | case MVT::v4i32: |
| 1870 | case MVT::v8i16: |
| 1871 | case MVT::v16i8: |
| 1872 | Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0), |
| 1873 | InFlag).getValue(1); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 1874 | ResultVals[0] = Chain.getValue(0); |
| 1875 | NumResults = 1; |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1876 | NodeTys.push_back(Op.Val->getValueType(0)); |
| 1877 | break; |
| 1878 | } |
| 1879 | |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 1880 | Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1881 | DAG.getConstant(NumBytes, PtrVT)); |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1882 | NodeTys.push_back(MVT::Other); |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 1883 | |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 1884 | // If the function returns void, just return the chain. |
Chris Lattner | f6e190f | 2006-08-12 07:20:05 +0000 | [diff] [blame] | 1885 | if (NumResults == 0) |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 1886 | return Chain; |
| 1887 | |
| 1888 | // Otherwise, merge everything together with a MERGE_VALUES node. |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 1889 | ResultVals[NumResults++] = Chain; |
| 1890 | SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, |
| 1891 | ResultVals, NumResults); |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 1892 | return Res.getValue(Op.ResNo); |
| 1893 | } |
| 1894 | |
Chris Lattner | b9a7bea | 2007-03-06 00:59:59 +0000 | [diff] [blame] | 1895 | static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) { |
| 1896 | SmallVector<CCValAssign, 16> RVLocs; |
| 1897 | unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); |
Chris Lattner | 52387be | 2007-06-19 00:13:10 +0000 | [diff] [blame] | 1898 | bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); |
| 1899 | CCState CCInfo(CC, isVarArg, TM, RVLocs); |
Chris Lattner | b9a7bea | 2007-03-06 00:59:59 +0000 | [diff] [blame] | 1900 | CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC); |
| 1901 | |
| 1902 | // If this is the first return lowered for this function, add the regs to the |
| 1903 | // liveout set for the function. |
| 1904 | if (DAG.getMachineFunction().liveout_empty()) { |
| 1905 | for (unsigned i = 0; i != RVLocs.size(); ++i) |
| 1906 | DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg()); |
| 1907 | } |
| 1908 | |
Chris Lattner | caddd44 | 2007-02-26 19:44:02 +0000 | [diff] [blame] | 1909 | SDOperand Chain = Op.getOperand(0); |
Chris Lattner | b9a7bea | 2007-03-06 00:59:59 +0000 | [diff] [blame] | 1910 | SDOperand Flag; |
| 1911 | |
| 1912 | // Copy the result values into the output registers. |
| 1913 | for (unsigned i = 0; i != RVLocs.size(); ++i) { |
| 1914 | CCValAssign &VA = RVLocs[i]; |
| 1915 | assert(VA.isRegLoc() && "Can only return in registers!"); |
| 1916 | Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); |
| 1917 | Flag = Chain.getValue(1); |
| 1918 | } |
| 1919 | |
| 1920 | if (Flag.Val) |
| 1921 | return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag); |
| 1922 | else |
Chris Lattner | caddd44 | 2007-02-26 19:44:02 +0000 | [diff] [blame] | 1923 | return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1924 | } |
| 1925 | |
Jim Laskey | efc7e52 | 2006-12-04 22:04:42 +0000 | [diff] [blame] | 1926 | static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, |
| 1927 | const PPCSubtarget &Subtarget) { |
| 1928 | // When we pop the dynamic allocation we need to restore the SP link. |
| 1929 | |
| 1930 | // Get the corect type for pointers. |
| 1931 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 1932 | |
| 1933 | // Construct the stack pointer operand. |
| 1934 | bool IsPPC64 = Subtarget.isPPC64(); |
| 1935 | unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1; |
| 1936 | SDOperand StackPtr = DAG.getRegister(SP, PtrVT); |
| 1937 | |
| 1938 | // Get the operands for the STACKRESTORE. |
| 1939 | SDOperand Chain = Op.getOperand(0); |
| 1940 | SDOperand SaveSP = Op.getOperand(1); |
| 1941 | |
| 1942 | // Load the old link SP. |
| 1943 | SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); |
| 1944 | |
| 1945 | // Restore the stack pointer. |
| 1946 | Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP); |
| 1947 | |
| 1948 | // Store the old link SP. |
| 1949 | return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0); |
| 1950 | } |
| 1951 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1952 | static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG, |
| 1953 | const PPCSubtarget &Subtarget) { |
| 1954 | MachineFunction &MF = DAG.getMachineFunction(); |
| 1955 | bool IsPPC64 = Subtarget.isPPC64(); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1956 | bool isMachoABI = Subtarget.isMachoABI(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1957 | |
| 1958 | // Get current frame pointer save index. The users of this index will be |
| 1959 | // primarily DYNALLOC instructions. |
| 1960 | PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); |
| 1961 | int FPSI = FI->getFramePointerSaveIndex(); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1962 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1963 | // If the frame pointer save index hasn't been defined yet. |
| 1964 | if (!FPSI) { |
| 1965 | // Find out what the fix offset of the frame pointer save area. |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1966 | int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI); |
| 1967 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1968 | // Allocate the frame index for frame pointer save area. |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1969 | FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1970 | // Save the result. |
| 1971 | FI->setFramePointerSaveIndex(FPSI); |
| 1972 | } |
| 1973 | |
| 1974 | // Get the inputs. |
| 1975 | SDOperand Chain = Op.getOperand(0); |
| 1976 | SDOperand Size = Op.getOperand(1); |
| 1977 | |
| 1978 | // Get the corect type for pointers. |
| 1979 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 1980 | // Negate the size. |
| 1981 | SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT, |
| 1982 | DAG.getConstant(0, PtrVT), Size); |
| 1983 | // Construct a node for the frame pointer save index. |
| 1984 | SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT); |
| 1985 | // Build a DYNALLOC node. |
| 1986 | SDOperand Ops[3] = { Chain, NegSize, FPSIdx }; |
| 1987 | SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); |
| 1988 | return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3); |
| 1989 | } |
| 1990 | |
| 1991 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1992 | /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when |
| 1993 | /// possible. |
| 1994 | static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { |
| 1995 | // Not FP? Not a fsel. |
| 1996 | if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || |
| 1997 | !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) |
| 1998 | return SDOperand(); |
| 1999 | |
| 2000 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); |
| 2001 | |
| 2002 | // Cannot handle SETEQ/SETNE. |
| 2003 | if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand(); |
| 2004 | |
| 2005 | MVT::ValueType ResVT = Op.getValueType(); |
| 2006 | MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); |
| 2007 | SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); |
| 2008 | SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); |
| 2009 | |
| 2010 | // If the RHS of the comparison is a 0.0, we don't need to do the |
| 2011 | // subtraction at all. |
| 2012 | if (isFloatingPointZero(RHS)) |
| 2013 | switch (CC) { |
| 2014 | default: break; // SETUO etc aren't handled by fsel. |
| 2015 | case ISD::SETULT: |
Chris Lattner | 5734012 | 2006-05-24 00:06:44 +0000 | [diff] [blame] | 2016 | case ISD::SETOLT: |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2017 | case ISD::SETLT: |
| 2018 | std::swap(TV, FV); // fsel is natively setge, swap operands for setlt |
| 2019 | case ISD::SETUGE: |
Chris Lattner | 5734012 | 2006-05-24 00:06:44 +0000 | [diff] [blame] | 2020 | case ISD::SETOGE: |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2021 | case ISD::SETGE: |
| 2022 | if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits |
| 2023 | LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); |
| 2024 | return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); |
| 2025 | case ISD::SETUGT: |
Chris Lattner | 5734012 | 2006-05-24 00:06:44 +0000 | [diff] [blame] | 2026 | case ISD::SETOGT: |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2027 | case ISD::SETGT: |
| 2028 | std::swap(TV, FV); // fsel is natively setge, swap operands for setlt |
| 2029 | case ISD::SETULE: |
Chris Lattner | 5734012 | 2006-05-24 00:06:44 +0000 | [diff] [blame] | 2030 | case ISD::SETOLE: |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2031 | case ISD::SETLE: |
| 2032 | if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits |
| 2033 | LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); |
| 2034 | return DAG.getNode(PPCISD::FSEL, ResVT, |
| 2035 | DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); |
| 2036 | } |
| 2037 | |
Chris Lattner | 1de7c1d | 2007-10-15 20:14:52 +0000 | [diff] [blame] | 2038 | SDOperand Cmp; |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2039 | switch (CC) { |
| 2040 | default: break; // SETUO etc aren't handled by fsel. |
| 2041 | case ISD::SETULT: |
Chris Lattner | 5734012 | 2006-05-24 00:06:44 +0000 | [diff] [blame] | 2042 | case ISD::SETOLT: |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2043 | case ISD::SETLT: |
| 2044 | Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); |
| 2045 | if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits |
| 2046 | Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); |
| 2047 | return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); |
| 2048 | case ISD::SETUGE: |
Chris Lattner | 5734012 | 2006-05-24 00:06:44 +0000 | [diff] [blame] | 2049 | case ISD::SETOGE: |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2050 | case ISD::SETGE: |
| 2051 | Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); |
| 2052 | if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits |
| 2053 | Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); |
| 2054 | return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); |
| 2055 | case ISD::SETUGT: |
Chris Lattner | 5734012 | 2006-05-24 00:06:44 +0000 | [diff] [blame] | 2056 | case ISD::SETOGT: |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2057 | case ISD::SETGT: |
| 2058 | Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); |
| 2059 | if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits |
| 2060 | Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); |
| 2061 | return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); |
| 2062 | case ISD::SETULE: |
Chris Lattner | 5734012 | 2006-05-24 00:06:44 +0000 | [diff] [blame] | 2063 | case ISD::SETOLE: |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2064 | case ISD::SETLE: |
| 2065 | Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); |
| 2066 | if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits |
| 2067 | Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); |
| 2068 | return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); |
| 2069 | } |
| 2070 | return SDOperand(); |
| 2071 | } |
| 2072 | |
| 2073 | static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { |
| 2074 | assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); |
| 2075 | SDOperand Src = Op.getOperand(0); |
| 2076 | if (Src.getValueType() == MVT::f32) |
| 2077 | Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); |
| 2078 | |
| 2079 | SDOperand Tmp; |
| 2080 | switch (Op.getValueType()) { |
| 2081 | default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); |
| 2082 | case MVT::i32: |
| 2083 | Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); |
| 2084 | break; |
| 2085 | case MVT::i64: |
| 2086 | Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); |
| 2087 | break; |
| 2088 | } |
| 2089 | |
| 2090 | // Convert the FP value to an int value through memory. |
Chris Lattner | 1de7c1d | 2007-10-15 20:14:52 +0000 | [diff] [blame] | 2091 | SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64); |
| 2092 | |
| 2093 | // Emit a store to the stack slot. |
| 2094 | SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0); |
| 2095 | |
| 2096 | // Result is a load from the stack slot. If loading 4 bytes, make sure to |
| 2097 | // add in a bias. |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2098 | if (Op.getValueType() == MVT::i32) |
Chris Lattner | 1de7c1d | 2007-10-15 20:14:52 +0000 | [diff] [blame] | 2099 | FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, |
| 2100 | DAG.getConstant(4, FIPtr.getValueType())); |
| 2101 | return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2102 | } |
| 2103 | |
Dale Johannesen | 6eaeff2 | 2007-10-10 01:01:31 +0000 | [diff] [blame] | 2104 | static SDOperand LowerFP_ROUND_INREG(SDOperand Op, SelectionDAG &DAG) { |
| 2105 | assert(Op.getValueType() == MVT::ppcf128); |
| 2106 | SDNode *Node = Op.Val; |
| 2107 | assert(Node->getOperand(0).getValueType() == MVT::ppcf128); |
Chris Lattner | 26cb286 | 2007-10-19 04:08:28 +0000 | [diff] [blame] | 2108 | assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR); |
Dale Johannesen | 6eaeff2 | 2007-10-10 01:01:31 +0000 | [diff] [blame] | 2109 | SDOperand Lo = Node->getOperand(0).Val->getOperand(0); |
| 2110 | SDOperand Hi = Node->getOperand(0).Val->getOperand(1); |
| 2111 | |
| 2112 | // This sequence changes FPSCR to do round-to-zero, adds the two halves |
| 2113 | // of the long double, and puts FPSCR back the way it was. We do not |
| 2114 | // actually model FPSCR. |
| 2115 | std::vector<MVT::ValueType> NodeTys; |
| 2116 | SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg; |
| 2117 | |
| 2118 | NodeTys.push_back(MVT::f64); // Return register |
| 2119 | NodeTys.push_back(MVT::Flag); // Returns a flag for later insns |
| 2120 | Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); |
| 2121 | MFFSreg = Result.getValue(0); |
| 2122 | InFlag = Result.getValue(1); |
| 2123 | |
| 2124 | NodeTys.clear(); |
| 2125 | NodeTys.push_back(MVT::Flag); // Returns a flag |
| 2126 | Ops[0] = DAG.getConstant(31, MVT::i32); |
| 2127 | Ops[1] = InFlag; |
| 2128 | Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2); |
| 2129 | InFlag = Result.getValue(0); |
| 2130 | |
| 2131 | NodeTys.clear(); |
| 2132 | NodeTys.push_back(MVT::Flag); // Returns a flag |
| 2133 | Ops[0] = DAG.getConstant(30, MVT::i32); |
| 2134 | Ops[1] = InFlag; |
| 2135 | Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2); |
| 2136 | InFlag = Result.getValue(0); |
| 2137 | |
| 2138 | NodeTys.clear(); |
| 2139 | NodeTys.push_back(MVT::f64); // result of add |
| 2140 | NodeTys.push_back(MVT::Flag); // Returns a flag |
| 2141 | Ops[0] = Lo; |
| 2142 | Ops[1] = Hi; |
| 2143 | Ops[2] = InFlag; |
| 2144 | Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3); |
| 2145 | FPreg = Result.getValue(0); |
| 2146 | InFlag = Result.getValue(1); |
| 2147 | |
| 2148 | NodeTys.clear(); |
| 2149 | NodeTys.push_back(MVT::f64); |
| 2150 | Ops[0] = DAG.getConstant(1, MVT::i32); |
| 2151 | Ops[1] = MFFSreg; |
| 2152 | Ops[2] = FPreg; |
| 2153 | Ops[3] = InFlag; |
| 2154 | Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4); |
| 2155 | FPreg = Result.getValue(0); |
| 2156 | |
| 2157 | // We know the low half is about to be thrown away, so just use something |
| 2158 | // convenient. |
| 2159 | return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg); |
| 2160 | } |
| 2161 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2162 | static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { |
| 2163 | if (Op.getOperand(0).getValueType() == MVT::i64) { |
| 2164 | SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); |
| 2165 | SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); |
| 2166 | if (Op.getValueType() == MVT::f32) |
| 2167 | FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); |
| 2168 | return FP; |
| 2169 | } |
| 2170 | |
| 2171 | assert(Op.getOperand(0).getValueType() == MVT::i32 && |
| 2172 | "Unhandled SINT_TO_FP type in custom expander!"); |
| 2173 | // Since we only generate this in 64-bit mode, we can take advantage of |
| 2174 | // 64-bit registers. In particular, sign extend the input value into the |
| 2175 | // 64-bit register with extsw, store the WHOLE 64-bit value into the stack |
| 2176 | // then lfd it and fcfid it. |
| 2177 | MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); |
| 2178 | int FrameIdx = FrameInfo->CreateStackObject(8, 8); |
Chris Lattner | 0d72a20 | 2006-07-28 16:45:47 +0000 | [diff] [blame] | 2179 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 2180 | SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2181 | |
| 2182 | SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, |
| 2183 | Op.getOperand(0)); |
| 2184 | |
| 2185 | // STD the extended value into the stack slot. |
| 2186 | SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, |
| 2187 | DAG.getEntryNode(), Ext64, FIdx, |
| 2188 | DAG.getSrcValue(NULL)); |
| 2189 | // Load the value as a double. |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 2190 | SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2191 | |
| 2192 | // FCFID it and return it. |
| 2193 | SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); |
| 2194 | if (Op.getValueType() == MVT::f32) |
| 2195 | FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); |
| 2196 | return FP; |
| 2197 | } |
| 2198 | |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2199 | static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { |
| 2200 | assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2201 | Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2202 | |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2203 | // Expand into a bunch of logical ops. Note that these ops |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2204 | // depend on the PPC behavior for oversized shift amounts. |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2205 | SDOperand Lo = Op.getOperand(0); |
| 2206 | SDOperand Hi = Op.getOperand(1); |
| 2207 | SDOperand Amt = Op.getOperand(2); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2208 | |
| 2209 | SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, |
| 2210 | DAG.getConstant(32, MVT::i32), Amt); |
| 2211 | SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); |
| 2212 | SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); |
| 2213 | SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); |
| 2214 | SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, |
| 2215 | DAG.getConstant(-32U, MVT::i32)); |
| 2216 | SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); |
| 2217 | SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); |
| 2218 | SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2219 | SDOperand OutOps[] = { OutLo, OutHi }; |
| 2220 | return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), |
| 2221 | OutOps, 2); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2222 | } |
| 2223 | |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2224 | static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { |
| 2225 | assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && |
| 2226 | Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!"); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2227 | |
| 2228 | // Otherwise, expand into a bunch of logical ops. Note that these ops |
| 2229 | // depend on the PPC behavior for oversized shift amounts. |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2230 | SDOperand Lo = Op.getOperand(0); |
| 2231 | SDOperand Hi = Op.getOperand(1); |
| 2232 | SDOperand Amt = Op.getOperand(2); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2233 | |
| 2234 | SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, |
| 2235 | DAG.getConstant(32, MVT::i32), Amt); |
| 2236 | SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); |
| 2237 | SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); |
| 2238 | SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); |
| 2239 | SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, |
| 2240 | DAG.getConstant(-32U, MVT::i32)); |
| 2241 | SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); |
| 2242 | SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); |
| 2243 | SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2244 | SDOperand OutOps[] = { OutLo, OutHi }; |
| 2245 | return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), |
| 2246 | OutOps, 2); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2247 | } |
| 2248 | |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2249 | static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { |
| 2250 | assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2251 | Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2252 | |
| 2253 | // Otherwise, expand into a bunch of logical ops, followed by a select_cc. |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2254 | SDOperand Lo = Op.getOperand(0); |
| 2255 | SDOperand Hi = Op.getOperand(1); |
| 2256 | SDOperand Amt = Op.getOperand(2); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2257 | |
| 2258 | SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, |
| 2259 | DAG.getConstant(32, MVT::i32), Amt); |
| 2260 | SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); |
| 2261 | SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); |
| 2262 | SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); |
| 2263 | SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, |
| 2264 | DAG.getConstant(-32U, MVT::i32)); |
| 2265 | SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); |
| 2266 | SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); |
| 2267 | SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), |
| 2268 | Tmp4, Tmp6, ISD::SETLE); |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2269 | SDOperand OutOps[] = { OutLo, OutHi }; |
| 2270 | return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), |
| 2271 | OutOps, 2); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2272 | } |
| 2273 | |
| 2274 | //===----------------------------------------------------------------------===// |
| 2275 | // Vector related lowering. |
| 2276 | // |
| 2277 | |
Chris Lattner | ac225ca | 2006-04-12 19:07:14 +0000 | [diff] [blame] | 2278 | // If this is a vector of constants or undefs, get the bits. A bit in |
| 2279 | // UndefBits is set if the corresponding element of the vector is an |
| 2280 | // ISD::UNDEF value. For undefs, the corresponding VectorBits values are |
| 2281 | // zero. Return true if this is not an array of constants, false if it is. |
| 2282 | // |
Chris Lattner | ac225ca | 2006-04-12 19:07:14 +0000 | [diff] [blame] | 2283 | static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], |
| 2284 | uint64_t UndefBits[2]) { |
| 2285 | // Start with zero'd results. |
| 2286 | VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; |
| 2287 | |
| 2288 | unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); |
| 2289 | for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { |
| 2290 | SDOperand OpVal = BV->getOperand(i); |
| 2291 | |
| 2292 | unsigned PartNo = i >= e/2; // In the upper 128 bits? |
Chris Lattner | b17f167 | 2006-04-16 01:01:29 +0000 | [diff] [blame] | 2293 | unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. |
Chris Lattner | ac225ca | 2006-04-12 19:07:14 +0000 | [diff] [blame] | 2294 | |
| 2295 | uint64_t EltBits = 0; |
| 2296 | if (OpVal.getOpcode() == ISD::UNDEF) { |
| 2297 | uint64_t EltUndefBits = ~0U >> (32-EltBitSize); |
| 2298 | UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); |
| 2299 | continue; |
| 2300 | } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { |
| 2301 | EltBits = CN->getValue() & (~0U >> (32-EltBitSize)); |
| 2302 | } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { |
| 2303 | assert(CN->getValueType(0) == MVT::f32 && |
| 2304 | "Only one legal FP vector type!"); |
Dale Johannesen | eaf0894 | 2007-08-31 04:03:46 +0000 | [diff] [blame] | 2305 | EltBits = FloatToBits(CN->getValueAPF().convertToFloat()); |
Chris Lattner | ac225ca | 2006-04-12 19:07:14 +0000 | [diff] [blame] | 2306 | } else { |
| 2307 | // Nonconstant element. |
| 2308 | return true; |
| 2309 | } |
| 2310 | |
| 2311 | VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); |
| 2312 | } |
| 2313 | |
| 2314 | //printf("%llx %llx %llx %llx\n", |
| 2315 | // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); |
| 2316 | return false; |
| 2317 | } |
Chris Lattner | ef819f8 | 2006-03-20 06:33:01 +0000 | [diff] [blame] | 2318 | |
Chris Lattner | b17f167 | 2006-04-16 01:01:29 +0000 | [diff] [blame] | 2319 | // If this is a splat (repetition) of a value across the whole vector, return |
| 2320 | // the smallest size that splats it. For example, "0x01010101010101..." is a |
| 2321 | // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and |
| 2322 | // SplatSize = 1 byte. |
| 2323 | static bool isConstantSplat(const uint64_t Bits128[2], |
| 2324 | const uint64_t Undef128[2], |
| 2325 | unsigned &SplatBits, unsigned &SplatUndef, |
| 2326 | unsigned &SplatSize) { |
| 2327 | |
| 2328 | // Don't let undefs prevent splats from matching. See if the top 64-bits are |
| 2329 | // the same as the lower 64-bits, ignoring undefs. |
| 2330 | if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) |
| 2331 | return false; // Can't be a splat if two pieces don't match. |
| 2332 | |
| 2333 | uint64_t Bits64 = Bits128[0] | Bits128[1]; |
| 2334 | uint64_t Undef64 = Undef128[0] & Undef128[1]; |
| 2335 | |
| 2336 | // Check that the top 32-bits are the same as the lower 32-bits, ignoring |
| 2337 | // undefs. |
| 2338 | if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) |
| 2339 | return false; // Can't be a splat if two pieces don't match. |
| 2340 | |
| 2341 | uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); |
| 2342 | uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); |
| 2343 | |
| 2344 | // If the top 16-bits are different than the lower 16-bits, ignoring |
| 2345 | // undefs, we have an i32 splat. |
| 2346 | if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { |
| 2347 | SplatBits = Bits32; |
| 2348 | SplatUndef = Undef32; |
| 2349 | SplatSize = 4; |
| 2350 | return true; |
| 2351 | } |
| 2352 | |
| 2353 | uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); |
| 2354 | uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); |
| 2355 | |
| 2356 | // If the top 8-bits are different than the lower 8-bits, ignoring |
| 2357 | // undefs, we have an i16 splat. |
| 2358 | if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { |
| 2359 | SplatBits = Bits16; |
| 2360 | SplatUndef = Undef16; |
| 2361 | SplatSize = 2; |
| 2362 | return true; |
| 2363 | } |
| 2364 | |
| 2365 | // Otherwise, we have an 8-bit splat. |
| 2366 | SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); |
| 2367 | SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); |
| 2368 | SplatSize = 1; |
| 2369 | return true; |
| 2370 | } |
| 2371 | |
Chris Lattner | 4a998b9 | 2006-04-17 06:00:21 +0000 | [diff] [blame] | 2372 | /// BuildSplatI - Build a canonical splati of Val with an element size of |
| 2373 | /// SplatSize. Cast the result to VT. |
| 2374 | static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT, |
| 2375 | SelectionDAG &DAG) { |
| 2376 | assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); |
Chris Lattner | 70fa493 | 2006-12-01 01:45:39 +0000 | [diff] [blame] | 2377 | |
Chris Lattner | 4a998b9 | 2006-04-17 06:00:21 +0000 | [diff] [blame] | 2378 | static const MVT::ValueType VTys[] = { // canonical VT to use for each size. |
| 2379 | MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 |
| 2380 | }; |
Chris Lattner | 70fa493 | 2006-12-01 01:45:39 +0000 | [diff] [blame] | 2381 | |
| 2382 | MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; |
| 2383 | |
| 2384 | // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. |
| 2385 | if (Val == -1) |
| 2386 | SplatSize = 1; |
| 2387 | |
Chris Lattner | 4a998b9 | 2006-04-17 06:00:21 +0000 | [diff] [blame] | 2388 | MVT::ValueType CanonicalVT = VTys[SplatSize-1]; |
| 2389 | |
| 2390 | // Build a canonical splat for this value. |
Dan Gohman | 51eaa86 | 2007-06-14 22:58:02 +0000 | [diff] [blame] | 2391 | SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT)); |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 2392 | SmallVector<SDOperand, 8> Ops; |
| 2393 | Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt); |
| 2394 | SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, |
| 2395 | &Ops[0], Ops.size()); |
Chris Lattner | 70fa493 | 2006-12-01 01:45:39 +0000 | [diff] [blame] | 2396 | return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res); |
Chris Lattner | 4a998b9 | 2006-04-17 06:00:21 +0000 | [diff] [blame] | 2397 | } |
| 2398 | |
Chris Lattner | e7c768e | 2006-04-18 03:24:30 +0000 | [diff] [blame] | 2399 | /// BuildIntrinsicOp - Return a binary operator intrinsic node with the |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2400 | /// specified intrinsic ID. |
Chris Lattner | e7c768e | 2006-04-18 03:24:30 +0000 | [diff] [blame] | 2401 | static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS, |
| 2402 | SelectionDAG &DAG, |
| 2403 | MVT::ValueType DestVT = MVT::Other) { |
| 2404 | if (DestVT == MVT::Other) DestVT = LHS.getValueType(); |
| 2405 | return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2406 | DAG.getConstant(IID, MVT::i32), LHS, RHS); |
| 2407 | } |
| 2408 | |
Chris Lattner | e7c768e | 2006-04-18 03:24:30 +0000 | [diff] [blame] | 2409 | /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the |
| 2410 | /// specified intrinsic ID. |
| 2411 | static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1, |
| 2412 | SDOperand Op2, SelectionDAG &DAG, |
| 2413 | MVT::ValueType DestVT = MVT::Other) { |
| 2414 | if (DestVT == MVT::Other) DestVT = Op0.getValueType(); |
| 2415 | return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, |
| 2416 | DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); |
| 2417 | } |
| 2418 | |
| 2419 | |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 2420 | /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified |
| 2421 | /// amount. The result has the specified value type. |
| 2422 | static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, |
| 2423 | MVT::ValueType VT, SelectionDAG &DAG) { |
| 2424 | // Force LHS/RHS to be the right type. |
| 2425 | LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); |
| 2426 | RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); |
| 2427 | |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 2428 | SDOperand Ops[16]; |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 2429 | for (unsigned i = 0; i != 16; ++i) |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 2430 | Ops[i] = DAG.getConstant(i+Amt, MVT::i32); |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 2431 | SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 2432 | DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 2433 | return DAG.getNode(ISD::BIT_CONVERT, VT, T); |
| 2434 | } |
| 2435 | |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 2436 | // If this is a case we can't handle, return null and let the default |
| 2437 | // expansion code take care of it. If we CAN select this case, and if it |
| 2438 | // selects to a single instruction, return Op. Otherwise, if we can codegen |
| 2439 | // this case more efficiently than a constant pool load, lower it to the |
| 2440 | // sequence of ops that should be used. |
| 2441 | static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { |
| 2442 | // If this is a vector of constants or undefs, get the bits. A bit in |
| 2443 | // UndefBits is set if the corresponding element of the vector is an |
| 2444 | // ISD::UNDEF value. For undefs, the corresponding VectorBits values are |
| 2445 | // zero. |
| 2446 | uint64_t VectorBits[2]; |
| 2447 | uint64_t UndefBits[2]; |
| 2448 | if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) |
| 2449 | return SDOperand(); // Not a constant vector. |
| 2450 | |
Chris Lattner | b17f167 | 2006-04-16 01:01:29 +0000 | [diff] [blame] | 2451 | // If this is a splat (repetition) of a value across the whole vector, return |
| 2452 | // the smallest size that splats it. For example, "0x01010101010101..." is a |
| 2453 | // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and |
| 2454 | // SplatSize = 1 byte. |
| 2455 | unsigned SplatBits, SplatUndef, SplatSize; |
| 2456 | if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ |
| 2457 | bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; |
| 2458 | |
| 2459 | // First, handle single instruction cases. |
| 2460 | |
| 2461 | // All zeros? |
| 2462 | if (SplatBits == 0) { |
| 2463 | // Canonicalize all zero vectors to be v4i32. |
| 2464 | if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { |
| 2465 | SDOperand Z = DAG.getConstant(0, MVT::i32); |
| 2466 | Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); |
| 2467 | Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); |
| 2468 | } |
| 2469 | return Op; |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 2470 | } |
Chris Lattner | b17f167 | 2006-04-16 01:01:29 +0000 | [diff] [blame] | 2471 | |
| 2472 | // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. |
| 2473 | int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); |
Chris Lattner | 4a998b9 | 2006-04-17 06:00:21 +0000 | [diff] [blame] | 2474 | if (SextVal >= -16 && SextVal <= 15) |
| 2475 | return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG); |
Chris Lattner | b17f167 | 2006-04-16 01:01:29 +0000 | [diff] [blame] | 2476 | |
Chris Lattner | dbce85d | 2006-04-17 18:09:22 +0000 | [diff] [blame] | 2477 | |
| 2478 | // Two instruction sequences. |
| 2479 | |
Chris Lattner | 4a998b9 | 2006-04-17 06:00:21 +0000 | [diff] [blame] | 2480 | // If this value is in the range [-32,30] and is even, use: |
| 2481 | // tmp = VSPLTI[bhw], result = add tmp, tmp |
| 2482 | if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { |
| 2483 | Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG); |
| 2484 | return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op); |
| 2485 | } |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2486 | |
| 2487 | // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is |
| 2488 | // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important |
| 2489 | // for fneg/fabs. |
| 2490 | if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { |
| 2491 | // Make -1 and vspltisw -1: |
| 2492 | SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); |
| 2493 | |
| 2494 | // Make the VSLW intrinsic, computing 0x8000_0000. |
Chris Lattner | e7c768e | 2006-04-18 03:24:30 +0000 | [diff] [blame] | 2495 | SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, |
| 2496 | OnesV, DAG); |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2497 | |
| 2498 | // xor by OnesV to invert it. |
| 2499 | Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); |
| 2500 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); |
| 2501 | } |
| 2502 | |
| 2503 | // Check to see if this is a wide variety of vsplti*, binop self cases. |
| 2504 | unsigned SplatBitSize = SplatSize*8; |
Lauro Ramos Venancio | 1baa197 | 2007-03-27 16:33:08 +0000 | [diff] [blame] | 2505 | static const signed char SplatCsts[] = { |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2506 | -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, |
Chris Lattner | dbce85d | 2006-04-17 18:09:22 +0000 | [diff] [blame] | 2507 | -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2508 | }; |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 2509 | |
Owen Anderson | 718cb66 | 2007-09-07 04:06:50 +0000 | [diff] [blame] | 2510 | for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2511 | // Indirect through the SplatCsts array so that we favor 'vsplti -1' for |
| 2512 | // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' |
| 2513 | int i = SplatCsts[idx]; |
| 2514 | |
| 2515 | // Figure out what shift amount will be used by altivec if shifted by i in |
| 2516 | // this splat size. |
| 2517 | unsigned TypeShiftAmt = i & (SplatBitSize-1); |
| 2518 | |
| 2519 | // vsplti + shl self. |
| 2520 | if (SextVal == (i << (int)TypeShiftAmt)) { |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 2521 | SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2522 | static const unsigned IIDs[] = { // Intrinsic to use for each size. |
| 2523 | Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, |
| 2524 | Intrinsic::ppc_altivec_vslw |
| 2525 | }; |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 2526 | Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); |
| 2527 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2528 | } |
| 2529 | |
| 2530 | // vsplti + srl self. |
| 2531 | if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 2532 | SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2533 | static const unsigned IIDs[] = { // Intrinsic to use for each size. |
| 2534 | Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, |
| 2535 | Intrinsic::ppc_altivec_vsrw |
| 2536 | }; |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 2537 | Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); |
| 2538 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2539 | } |
| 2540 | |
| 2541 | // vsplti + sra self. |
| 2542 | if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 2543 | SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2544 | static const unsigned IIDs[] = { // Intrinsic to use for each size. |
| 2545 | Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, |
| 2546 | Intrinsic::ppc_altivec_vsraw |
| 2547 | }; |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 2548 | Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); |
| 2549 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2550 | } |
| 2551 | |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 2552 | // vsplti + rol self. |
| 2553 | if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | |
| 2554 | ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 2555 | SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 2556 | static const unsigned IIDs[] = { // Intrinsic to use for each size. |
| 2557 | Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, |
| 2558 | Intrinsic::ppc_altivec_vrlw |
| 2559 | }; |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 2560 | Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); |
| 2561 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 2562 | } |
| 2563 | |
| 2564 | // t = vsplti c, result = vsldoi t, t, 1 |
| 2565 | if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { |
| 2566 | SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); |
| 2567 | return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); |
| 2568 | } |
| 2569 | // t = vsplti c, result = vsldoi t, t, 2 |
| 2570 | if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { |
| 2571 | SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); |
| 2572 | return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); |
| 2573 | } |
| 2574 | // t = vsplti c, result = vsldoi t, t, 3 |
| 2575 | if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { |
| 2576 | SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); |
| 2577 | return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); |
| 2578 | } |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2579 | } |
| 2580 | |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2581 | // Three instruction sequences. |
| 2582 | |
Chris Lattner | dbce85d | 2006-04-17 18:09:22 +0000 | [diff] [blame] | 2583 | // Odd, in range [17,31]: (vsplti C)-(vsplti -16). |
| 2584 | if (SextVal >= 0 && SextVal <= 31) { |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 2585 | SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); |
| 2586 | SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); |
Dale Johannesen | 296c176 | 2007-10-14 01:58:32 +0000 | [diff] [blame] | 2587 | LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS); |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 2588 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); |
Chris Lattner | dbce85d | 2006-04-17 18:09:22 +0000 | [diff] [blame] | 2589 | } |
| 2590 | // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). |
| 2591 | if (SextVal >= -31 && SextVal <= 0) { |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 2592 | SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); |
| 2593 | SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); |
Dale Johannesen | 296c176 | 2007-10-14 01:58:32 +0000 | [diff] [blame] | 2594 | LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS); |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 2595 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 2596 | } |
| 2597 | } |
Chris Lattner | b17f167 | 2006-04-16 01:01:29 +0000 | [diff] [blame] | 2598 | |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 2599 | return SDOperand(); |
| 2600 | } |
| 2601 | |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 2602 | /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit |
| 2603 | /// the specified operations to build the shuffle. |
| 2604 | static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, |
| 2605 | SDOperand RHS, SelectionDAG &DAG) { |
| 2606 | unsigned OpNum = (PFEntry >> 26) & 0x0F; |
| 2607 | unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); |
| 2608 | unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); |
| 2609 | |
| 2610 | enum { |
Chris Lattner | 00402c7 | 2006-05-16 04:20:24 +0000 | [diff] [blame] | 2611 | OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 2612 | OP_VMRGHW, |
| 2613 | OP_VMRGLW, |
| 2614 | OP_VSPLTISW0, |
| 2615 | OP_VSPLTISW1, |
| 2616 | OP_VSPLTISW2, |
| 2617 | OP_VSPLTISW3, |
| 2618 | OP_VSLDOI4, |
| 2619 | OP_VSLDOI8, |
Chris Lattner | d74ea2b | 2006-05-24 17:04:05 +0000 | [diff] [blame] | 2620 | OP_VSLDOI12 |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 2621 | }; |
| 2622 | |
| 2623 | if (OpNum == OP_COPY) { |
| 2624 | if (LHSID == (1*9+2)*9+3) return LHS; |
| 2625 | assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); |
| 2626 | return RHS; |
| 2627 | } |
| 2628 | |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 2629 | SDOperand OpLHS, OpRHS; |
| 2630 | OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); |
| 2631 | OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); |
| 2632 | |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 2633 | unsigned ShufIdxs[16]; |
| 2634 | switch (OpNum) { |
| 2635 | default: assert(0 && "Unknown i32 permute!"); |
| 2636 | case OP_VMRGHW: |
| 2637 | ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; |
| 2638 | ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; |
| 2639 | ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; |
| 2640 | ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; |
| 2641 | break; |
| 2642 | case OP_VMRGLW: |
| 2643 | ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; |
| 2644 | ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; |
| 2645 | ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; |
| 2646 | ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; |
| 2647 | break; |
| 2648 | case OP_VSPLTISW0: |
| 2649 | for (unsigned i = 0; i != 16; ++i) |
| 2650 | ShufIdxs[i] = (i&3)+0; |
| 2651 | break; |
| 2652 | case OP_VSPLTISW1: |
| 2653 | for (unsigned i = 0; i != 16; ++i) |
| 2654 | ShufIdxs[i] = (i&3)+4; |
| 2655 | break; |
| 2656 | case OP_VSPLTISW2: |
| 2657 | for (unsigned i = 0; i != 16; ++i) |
| 2658 | ShufIdxs[i] = (i&3)+8; |
| 2659 | break; |
| 2660 | case OP_VSPLTISW3: |
| 2661 | for (unsigned i = 0; i != 16; ++i) |
| 2662 | ShufIdxs[i] = (i&3)+12; |
| 2663 | break; |
| 2664 | case OP_VSLDOI4: |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 2665 | return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG); |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 2666 | case OP_VSLDOI8: |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 2667 | return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG); |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 2668 | case OP_VSLDOI12: |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 2669 | return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 2670 | } |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 2671 | SDOperand Ops[16]; |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 2672 | for (unsigned i = 0; i != 16; ++i) |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 2673 | Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32); |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 2674 | |
| 2675 | return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 2676 | DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 2677 | } |
| 2678 | |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 2679 | /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this |
| 2680 | /// is a shuffle we can handle in a single instruction, return it. Otherwise, |
| 2681 | /// return the code it can be lowered into. Worst case, it can always be |
| 2682 | /// lowered into a vperm. |
| 2683 | static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { |
| 2684 | SDOperand V1 = Op.getOperand(0); |
| 2685 | SDOperand V2 = Op.getOperand(1); |
| 2686 | SDOperand PermMask = Op.getOperand(2); |
| 2687 | |
| 2688 | // Cases that are handled by instructions that take permute immediates |
| 2689 | // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be |
| 2690 | // selected by the instruction selector. |
| 2691 | if (V2.getOpcode() == ISD::UNDEF) { |
| 2692 | if (PPC::isSplatShuffleMask(PermMask.Val, 1) || |
| 2693 | PPC::isSplatShuffleMask(PermMask.Val, 2) || |
| 2694 | PPC::isSplatShuffleMask(PermMask.Val, 4) || |
| 2695 | PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || |
| 2696 | PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || |
| 2697 | PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || |
| 2698 | PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || |
| 2699 | PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || |
| 2700 | PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || |
| 2701 | PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || |
| 2702 | PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || |
| 2703 | PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { |
| 2704 | return Op; |
| 2705 | } |
| 2706 | } |
| 2707 | |
| 2708 | // Altivec has a variety of "shuffle immediates" that take two vector inputs |
| 2709 | // and produce a fixed permutation. If any of these match, do not lower to |
| 2710 | // VPERM. |
| 2711 | if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || |
| 2712 | PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || |
| 2713 | PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || |
| 2714 | PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || |
| 2715 | PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || |
| 2716 | PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || |
| 2717 | PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || |
| 2718 | PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || |
| 2719 | PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) |
| 2720 | return Op; |
| 2721 | |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 2722 | // Check to see if this is a shuffle of 4-byte values. If so, we can use our |
| 2723 | // perfect shuffle table to emit an optimal matching sequence. |
| 2724 | unsigned PFIndexes[4]; |
| 2725 | bool isFourElementShuffle = true; |
| 2726 | for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number |
| 2727 | unsigned EltNo = 8; // Start out undef. |
| 2728 | for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. |
| 2729 | if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF) |
| 2730 | continue; // Undef, ignore it. |
| 2731 | |
| 2732 | unsigned ByteSource = |
| 2733 | cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue(); |
| 2734 | if ((ByteSource & 3) != j) { |
| 2735 | isFourElementShuffle = false; |
| 2736 | break; |
| 2737 | } |
| 2738 | |
| 2739 | if (EltNo == 8) { |
| 2740 | EltNo = ByteSource/4; |
| 2741 | } else if (EltNo != ByteSource/4) { |
| 2742 | isFourElementShuffle = false; |
| 2743 | break; |
| 2744 | } |
| 2745 | } |
| 2746 | PFIndexes[i] = EltNo; |
| 2747 | } |
| 2748 | |
| 2749 | // If this shuffle can be expressed as a shuffle of 4-byte elements, use the |
| 2750 | // perfect shuffle vector to determine if it is cost effective to do this as |
| 2751 | // discrete instructions, or whether we should use a vperm. |
| 2752 | if (isFourElementShuffle) { |
| 2753 | // Compute the index in the perfect shuffle table. |
| 2754 | unsigned PFTableIndex = |
| 2755 | PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; |
| 2756 | |
| 2757 | unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; |
| 2758 | unsigned Cost = (PFEntry >> 30); |
| 2759 | |
| 2760 | // Determining when to avoid vperm is tricky. Many things affect the cost |
| 2761 | // of vperm, particularly how many times the perm mask needs to be computed. |
| 2762 | // For example, if the perm mask can be hoisted out of a loop or is already |
| 2763 | // used (perhaps because there are multiple permutes with the same shuffle |
| 2764 | // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of |
| 2765 | // the loop requires an extra register. |
| 2766 | // |
| 2767 | // As a compromise, we only emit discrete instructions if the shuffle can be |
| 2768 | // generated in 3 or fewer operations. When we have loop information |
| 2769 | // available, if this block is within a loop, we should avoid using vperm |
| 2770 | // for 3-operation perms and use a constant pool load instead. |
| 2771 | if (Cost < 3) |
| 2772 | return GeneratePerfectShuffle(PFEntry, V1, V2, DAG); |
| 2773 | } |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 2774 | |
| 2775 | // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant |
| 2776 | // vector that will get spilled to the constant pool. |
| 2777 | if (V2.getOpcode() == ISD::UNDEF) V2 = V1; |
| 2778 | |
| 2779 | // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except |
| 2780 | // that it is in input element units, not in bytes. Convert now. |
Dan Gohman | 51eaa86 | 2007-06-14 22:58:02 +0000 | [diff] [blame] | 2781 | MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType()); |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 2782 | unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; |
| 2783 | |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 2784 | SmallVector<SDOperand, 16> ResultMask; |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 2785 | for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { |
Chris Lattner | 730b456 | 2006-04-15 23:48:05 +0000 | [diff] [blame] | 2786 | unsigned SrcElt; |
| 2787 | if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) |
| 2788 | SrcElt = 0; |
| 2789 | else |
| 2790 | SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue(); |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 2791 | |
| 2792 | for (unsigned j = 0; j != BytesPerElement; ++j) |
| 2793 | ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, |
| 2794 | MVT::i8)); |
| 2795 | } |
| 2796 | |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 2797 | SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, |
| 2798 | &ResultMask[0], ResultMask.size()); |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 2799 | return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); |
| 2800 | } |
| 2801 | |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 2802 | /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an |
| 2803 | /// altivec comparison. If it is, return true and fill in Opc/isDot with |
| 2804 | /// information about the intrinsic. |
| 2805 | static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc, |
| 2806 | bool &isDot) { |
| 2807 | unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue(); |
| 2808 | CompareOpc = -1; |
| 2809 | isDot = false; |
| 2810 | switch (IntrinsicID) { |
| 2811 | default: return false; |
| 2812 | // Comparison predicates. |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2813 | case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; |
| 2814 | case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; |
| 2815 | case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; |
| 2816 | case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; |
| 2817 | case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; |
| 2818 | case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; |
| 2819 | case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; |
| 2820 | case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; |
| 2821 | case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; |
| 2822 | case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; |
| 2823 | case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; |
| 2824 | case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; |
| 2825 | case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; |
| 2826 | |
| 2827 | // Normal Comparisons. |
| 2828 | case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; |
| 2829 | case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; |
| 2830 | case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; |
| 2831 | case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; |
| 2832 | case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; |
| 2833 | case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; |
| 2834 | case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; |
| 2835 | case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; |
| 2836 | case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; |
| 2837 | case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; |
| 2838 | case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; |
| 2839 | case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; |
| 2840 | case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; |
| 2841 | } |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 2842 | return true; |
| 2843 | } |
| 2844 | |
| 2845 | /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom |
| 2846 | /// lower, do it, otherwise return null. |
| 2847 | static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { |
| 2848 | // If this is a lowered altivec predicate compare, CompareOpc is set to the |
| 2849 | // opcode number of the comparison. |
| 2850 | int CompareOpc; |
| 2851 | bool isDot; |
| 2852 | if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) |
| 2853 | return SDOperand(); // Don't custom lower most intrinsics. |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2854 | |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 2855 | // If this is a non-dot comparison, make the VCMP node and we are done. |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2856 | if (!isDot) { |
| 2857 | SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), |
| 2858 | Op.getOperand(1), Op.getOperand(2), |
| 2859 | DAG.getConstant(CompareOpc, MVT::i32)); |
| 2860 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); |
| 2861 | } |
| 2862 | |
| 2863 | // Create the PPCISD altivec 'dot' comparison node. |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 2864 | SDOperand Ops[] = { |
| 2865 | Op.getOperand(2), // LHS |
| 2866 | Op.getOperand(3), // RHS |
| 2867 | DAG.getConstant(CompareOpc, MVT::i32) |
| 2868 | }; |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2869 | std::vector<MVT::ValueType> VTs; |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2870 | VTs.push_back(Op.getOperand(2).getValueType()); |
| 2871 | VTs.push_back(MVT::Flag); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 2872 | SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2873 | |
| 2874 | // Now that we have the comparison, emit a copy from the CR to a GPR. |
| 2875 | // This is flagged to the above dot comparison. |
| 2876 | SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, |
| 2877 | DAG.getRegister(PPC::CR6, MVT::i32), |
| 2878 | CompNode.getValue(1)); |
| 2879 | |
| 2880 | // Unpack the result based on how the target uses it. |
| 2881 | unsigned BitNo; // Bit # of CR6. |
| 2882 | bool InvertBit; // Invert result? |
| 2883 | switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { |
| 2884 | default: // Can't happen, don't crash on invalid number though. |
| 2885 | case 0: // Return the value of the EQ bit of CR6. |
| 2886 | BitNo = 0; InvertBit = false; |
| 2887 | break; |
| 2888 | case 1: // Return the inverted value of the EQ bit of CR6. |
| 2889 | BitNo = 0; InvertBit = true; |
| 2890 | break; |
| 2891 | case 2: // Return the value of the LT bit of CR6. |
| 2892 | BitNo = 2; InvertBit = false; |
| 2893 | break; |
| 2894 | case 3: // Return the inverted value of the LT bit of CR6. |
| 2895 | BitNo = 2; InvertBit = true; |
| 2896 | break; |
| 2897 | } |
| 2898 | |
| 2899 | // Shift the bit into the low position. |
| 2900 | Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, |
| 2901 | DAG.getConstant(8-(3-BitNo), MVT::i32)); |
| 2902 | // Isolate the bit. |
| 2903 | Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, |
| 2904 | DAG.getConstant(1, MVT::i32)); |
| 2905 | |
| 2906 | // If we are supposed to, toggle the bit. |
| 2907 | if (InvertBit) |
| 2908 | Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, |
| 2909 | DAG.getConstant(1, MVT::i32)); |
| 2910 | return Flags; |
| 2911 | } |
| 2912 | |
| 2913 | static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { |
| 2914 | // Create a stack slot that is 16-byte aligned. |
| 2915 | MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); |
| 2916 | int FrameIdx = FrameInfo->CreateStackObject(16, 16); |
Chris Lattner | 0d72a20 | 2006-07-28 16:45:47 +0000 | [diff] [blame] | 2917 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 2918 | SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2919 | |
| 2920 | // Store the input value into Value#0 of the stack slot. |
Evan Cheng | 786225a | 2006-10-05 23:01:46 +0000 | [diff] [blame] | 2921 | SDOperand Store = DAG.getStore(DAG.getEntryNode(), |
Evan Cheng | 8b2794a | 2006-10-13 21:14:26 +0000 | [diff] [blame] | 2922 | Op.getOperand(0), FIdx, NULL, 0); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2923 | // Load it out. |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 2924 | return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2925 | } |
| 2926 | |
Chris Lattner | e7c768e | 2006-04-18 03:24:30 +0000 | [diff] [blame] | 2927 | static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { |
Chris Lattner | 72dd9bd | 2006-04-18 03:43:48 +0000 | [diff] [blame] | 2928 | if (Op.getValueType() == MVT::v4i32) { |
| 2929 | SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); |
| 2930 | |
| 2931 | SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); |
| 2932 | SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. |
| 2933 | |
| 2934 | SDOperand RHSSwap = // = vrlw RHS, 16 |
| 2935 | BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); |
| 2936 | |
| 2937 | // Shrinkify inputs to v8i16. |
| 2938 | LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS); |
| 2939 | RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS); |
| 2940 | RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap); |
| 2941 | |
| 2942 | // Low parts multiplied together, generating 32-bit results (we ignore the |
| 2943 | // top parts). |
| 2944 | SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, |
| 2945 | LHS, RHS, DAG, MVT::v4i32); |
| 2946 | |
| 2947 | SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, |
| 2948 | LHS, RHSSwap, Zero, DAG, MVT::v4i32); |
| 2949 | // Shift the high parts up 16 bits. |
| 2950 | HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); |
| 2951 | return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); |
| 2952 | } else if (Op.getValueType() == MVT::v8i16) { |
| 2953 | SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); |
| 2954 | |
Chris Lattner | cea2aa7 | 2006-04-18 04:28:57 +0000 | [diff] [blame] | 2955 | SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); |
Chris Lattner | 72dd9bd | 2006-04-18 03:43:48 +0000 | [diff] [blame] | 2956 | |
Chris Lattner | cea2aa7 | 2006-04-18 04:28:57 +0000 | [diff] [blame] | 2957 | return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, |
| 2958 | LHS, RHS, Zero, DAG); |
Chris Lattner | 19a8152 | 2006-04-18 03:57:35 +0000 | [diff] [blame] | 2959 | } else if (Op.getValueType() == MVT::v16i8) { |
| 2960 | SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); |
| 2961 | |
| 2962 | // Multiply the even 8-bit parts, producing 16-bit sums. |
| 2963 | SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, |
| 2964 | LHS, RHS, DAG, MVT::v8i16); |
| 2965 | EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); |
| 2966 | |
| 2967 | // Multiply the odd 8-bit parts, producing 16-bit sums. |
| 2968 | SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, |
| 2969 | LHS, RHS, DAG, MVT::v8i16); |
| 2970 | OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); |
| 2971 | |
| 2972 | // Merge the results together. |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 2973 | SDOperand Ops[16]; |
Chris Lattner | 19a8152 | 2006-04-18 03:57:35 +0000 | [diff] [blame] | 2974 | for (unsigned i = 0; i != 8; ++i) { |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 2975 | Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); |
| 2976 | Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); |
Chris Lattner | 19a8152 | 2006-04-18 03:57:35 +0000 | [diff] [blame] | 2977 | } |
Chris Lattner | 19a8152 | 2006-04-18 03:57:35 +0000 | [diff] [blame] | 2978 | return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 2979 | DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); |
Chris Lattner | 72dd9bd | 2006-04-18 03:43:48 +0000 | [diff] [blame] | 2980 | } else { |
| 2981 | assert(0 && "Unknown mul to lower!"); |
| 2982 | abort(); |
| 2983 | } |
Chris Lattner | e7c768e | 2006-04-18 03:24:30 +0000 | [diff] [blame] | 2984 | } |
| 2985 | |
Chris Lattner | e4bc9ea | 2005-08-26 00:52:45 +0000 | [diff] [blame] | 2986 | /// LowerOperation - Provide custom lowering hooks for some operations. |
| 2987 | /// |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 2988 | SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { |
Chris Lattner | e4bc9ea | 2005-08-26 00:52:45 +0000 | [diff] [blame] | 2989 | switch (Op.getOpcode()) { |
| 2990 | default: assert(0 && "Wasn't expecting to be able to lower this!"); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2991 | case ISD::ConstantPool: return LowerConstantPool(Op, DAG); |
| 2992 | case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); |
Lauro Ramos Venancio | 75ce010 | 2007-07-11 17:19:51 +0000 | [diff] [blame] | 2993 | case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 2994 | case ISD::JumpTable: return LowerJumpTable(Op, DAG); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2995 | case ISD::SETCC: return LowerSETCC(Op, DAG); |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 2996 | case ISD::VASTART: |
| 2997 | return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, |
| 2998 | VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); |
| 2999 | |
| 3000 | case ISD::VAARG: |
| 3001 | return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, |
| 3002 | VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); |
| 3003 | |
Chris Lattner | ef95710 | 2006-06-21 00:34:03 +0000 | [diff] [blame] | 3004 | case ISD::FORMAL_ARGUMENTS: |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 3005 | return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex, |
| 3006 | VarArgsStackOffset, VarArgsNumGPR, |
| 3007 | VarArgsNumFPR, PPCSubTarget); |
| 3008 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 3009 | case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget); |
Chris Lattner | b9a7bea | 2007-03-06 00:59:59 +0000 | [diff] [blame] | 3010 | case ISD::RET: return LowerRET(Op, DAG, getTargetMachine()); |
Jim Laskey | efc7e52 | 2006-12-04 22:04:42 +0000 | [diff] [blame] | 3011 | case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 3012 | case ISD::DYNAMIC_STACKALLOC: |
| 3013 | return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); |
Chris Lattner | 7c0d664 | 2005-10-02 06:37:13 +0000 | [diff] [blame] | 3014 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3015 | case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); |
| 3016 | case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); |
| 3017 | case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); |
Dale Johannesen | 6eaeff2 | 2007-10-10 01:01:31 +0000 | [diff] [blame] | 3018 | case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG); |
Chris Lattner | ecfe55e | 2006-03-22 05:30:33 +0000 | [diff] [blame] | 3019 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3020 | // Lower 64-bit shifts. |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 3021 | case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); |
| 3022 | case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); |
| 3023 | case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); |
Chris Lattner | ecfe55e | 2006-03-22 05:30:33 +0000 | [diff] [blame] | 3024 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3025 | // Vector-related lowering. |
| 3026 | case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); |
| 3027 | case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); |
| 3028 | case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); |
| 3029 | case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); |
Chris Lattner | e7c768e | 2006-04-18 03:24:30 +0000 | [diff] [blame] | 3030 | case ISD::MUL: return LowerMUL(Op, DAG); |
Nate Begeman | bcc5f36 | 2007-01-29 22:58:52 +0000 | [diff] [blame] | 3031 | |
| 3032 | // Frame & Return address. Currently unimplemented |
| 3033 | case ISD::RETURNADDR: break; |
Nicolas Geoffray | 43c6e7c | 2007-03-01 13:11:38 +0000 | [diff] [blame] | 3034 | case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); |
Chris Lattner | bc11c34 | 2005-08-31 20:23:54 +0000 | [diff] [blame] | 3035 | } |
Chris Lattner | e4bc9ea | 2005-08-26 00:52:45 +0000 | [diff] [blame] | 3036 | return SDOperand(); |
| 3037 | } |
| 3038 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3039 | //===----------------------------------------------------------------------===// |
| 3040 | // Other Lowering Code |
| 3041 | //===----------------------------------------------------------------------===// |
| 3042 | |
Chris Lattner | 8a2d3ca | 2005-08-26 21:23:58 +0000 | [diff] [blame] | 3043 | MachineBasicBlock * |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 3044 | PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, |
| 3045 | MachineBasicBlock *BB) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 3046 | const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); |
Chris Lattner | c08f902 | 2006-06-27 00:04:13 +0000 | [diff] [blame] | 3047 | assert((MI->getOpcode() == PPC::SELECT_CC_I4 || |
| 3048 | MI->getOpcode() == PPC::SELECT_CC_I8 || |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 3049 | MI->getOpcode() == PPC::SELECT_CC_F4 || |
Chris Lattner | 710ff32 | 2006-04-08 22:45:08 +0000 | [diff] [blame] | 3050 | MI->getOpcode() == PPC::SELECT_CC_F8 || |
| 3051 | MI->getOpcode() == PPC::SELECT_CC_VRRC) && |
Chris Lattner | 8a2d3ca | 2005-08-26 21:23:58 +0000 | [diff] [blame] | 3052 | "Unexpected instr type to insert"); |
| 3053 | |
| 3054 | // To "insert" a SELECT_CC instruction, we actually have to insert the diamond |
| 3055 | // control-flow pattern. The incoming instruction knows the destination vreg |
| 3056 | // to set, the condition code register to branch on, the true/false values to |
| 3057 | // select between, and a branch opcode to use. |
| 3058 | const BasicBlock *LLVM_BB = BB->getBasicBlock(); |
| 3059 | ilist<MachineBasicBlock>::iterator It = BB; |
| 3060 | ++It; |
| 3061 | |
| 3062 | // thisMBB: |
| 3063 | // ... |
| 3064 | // TrueVal = ... |
| 3065 | // cmpTY ccX, r1, r2 |
| 3066 | // bCC copy1MBB |
| 3067 | // fallthrough --> copy0MBB |
| 3068 | MachineBasicBlock *thisMBB = BB; |
| 3069 | MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); |
| 3070 | MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); |
Chris Lattner | df4ed63 | 2006-11-17 22:10:59 +0000 | [diff] [blame] | 3071 | unsigned SelectPred = MI->getOperand(4).getImm(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 3072 | BuildMI(BB, TII->get(PPC::BCC)) |
Chris Lattner | 18258c6 | 2006-11-17 22:37:34 +0000 | [diff] [blame] | 3073 | .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); |
Chris Lattner | 8a2d3ca | 2005-08-26 21:23:58 +0000 | [diff] [blame] | 3074 | MachineFunction *F = BB->getParent(); |
| 3075 | F->getBasicBlockList().insert(It, copy0MBB); |
| 3076 | F->getBasicBlockList().insert(It, sinkMBB); |
Nate Begeman | f15485a | 2006-03-27 01:32:24 +0000 | [diff] [blame] | 3077 | // Update machine-CFG edges by first adding all successors of the current |
| 3078 | // block to the new block which will contain the Phi node for the select. |
| 3079 | for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), |
| 3080 | e = BB->succ_end(); i != e; ++i) |
| 3081 | sinkMBB->addSuccessor(*i); |
| 3082 | // Next, remove all successors of the current block, and add the true |
| 3083 | // and fallthrough blocks as its successors. |
| 3084 | while(!BB->succ_empty()) |
| 3085 | BB->removeSuccessor(BB->succ_begin()); |
Chris Lattner | 8a2d3ca | 2005-08-26 21:23:58 +0000 | [diff] [blame] | 3086 | BB->addSuccessor(copy0MBB); |
| 3087 | BB->addSuccessor(sinkMBB); |
| 3088 | |
| 3089 | // copy0MBB: |
| 3090 | // %FalseValue = ... |
| 3091 | // # fallthrough to sinkMBB |
| 3092 | BB = copy0MBB; |
| 3093 | |
| 3094 | // Update machine-CFG edges |
| 3095 | BB->addSuccessor(sinkMBB); |
| 3096 | |
| 3097 | // sinkMBB: |
| 3098 | // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] |
| 3099 | // ... |
| 3100 | BB = sinkMBB; |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 3101 | BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg()) |
Chris Lattner | 8a2d3ca | 2005-08-26 21:23:58 +0000 | [diff] [blame] | 3102 | .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) |
| 3103 | .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); |
| 3104 | |
| 3105 | delete MI; // The pseudo instruction is gone now. |
| 3106 | return BB; |
| 3107 | } |
| 3108 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3109 | //===----------------------------------------------------------------------===// |
| 3110 | // Target Optimization Hooks |
| 3111 | //===----------------------------------------------------------------------===// |
| 3112 | |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 3113 | SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, |
| 3114 | DAGCombinerInfo &DCI) const { |
| 3115 | TargetMachine &TM = getTargetMachine(); |
| 3116 | SelectionDAG &DAG = DCI.DAG; |
| 3117 | switch (N->getOpcode()) { |
| 3118 | default: break; |
Chris Lattner | cf9d0ac | 2006-09-19 05:22:59 +0000 | [diff] [blame] | 3119 | case PPCISD::SHL: |
| 3120 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { |
| 3121 | if (C->getValue() == 0) // 0 << V -> 0. |
| 3122 | return N->getOperand(0); |
| 3123 | } |
| 3124 | break; |
| 3125 | case PPCISD::SRL: |
| 3126 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { |
| 3127 | if (C->getValue() == 0) // 0 >>u V -> 0. |
| 3128 | return N->getOperand(0); |
| 3129 | } |
| 3130 | break; |
| 3131 | case PPCISD::SRA: |
| 3132 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { |
| 3133 | if (C->getValue() == 0 || // 0 >>s V -> 0. |
| 3134 | C->isAllOnesValue()) // -1 >>s V -> -1. |
| 3135 | return N->getOperand(0); |
| 3136 | } |
| 3137 | break; |
| 3138 | |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 3139 | case ISD::SINT_TO_FP: |
Chris Lattner | a7a5854 | 2006-06-16 17:34:12 +0000 | [diff] [blame] | 3140 | if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { |
Chris Lattner | ecfe55e | 2006-03-22 05:30:33 +0000 | [diff] [blame] | 3141 | if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { |
| 3142 | // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. |
| 3143 | // We allow the src/dst to be either f32/f64, but the intermediate |
| 3144 | // type must be i64. |
| 3145 | if (N->getOperand(0).getValueType() == MVT::i64) { |
| 3146 | SDOperand Val = N->getOperand(0).getOperand(0); |
| 3147 | if (Val.getValueType() == MVT::f32) { |
| 3148 | Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); |
| 3149 | DCI.AddToWorklist(Val.Val); |
| 3150 | } |
| 3151 | |
| 3152 | Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 3153 | DCI.AddToWorklist(Val.Val); |
Chris Lattner | ecfe55e | 2006-03-22 05:30:33 +0000 | [diff] [blame] | 3154 | Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 3155 | DCI.AddToWorklist(Val.Val); |
Chris Lattner | ecfe55e | 2006-03-22 05:30:33 +0000 | [diff] [blame] | 3156 | if (N->getValueType(0) == MVT::f32) { |
| 3157 | Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val); |
| 3158 | DCI.AddToWorklist(Val.Val); |
| 3159 | } |
| 3160 | return Val; |
| 3161 | } else if (N->getOperand(0).getValueType() == MVT::i32) { |
| 3162 | // If the intermediate type is i32, we can avoid the load/store here |
| 3163 | // too. |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 3164 | } |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 3165 | } |
| 3166 | } |
| 3167 | break; |
Chris Lattner | 5126984 | 2006-03-01 05:50:56 +0000 | [diff] [blame] | 3168 | case ISD::STORE: |
| 3169 | // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). |
| 3170 | if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && |
| 3171 | N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && |
| 3172 | N->getOperand(1).getValueType() == MVT::i32) { |
| 3173 | SDOperand Val = N->getOperand(1).getOperand(0); |
| 3174 | if (Val.getValueType() == MVT::f32) { |
| 3175 | Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); |
| 3176 | DCI.AddToWorklist(Val.Val); |
| 3177 | } |
| 3178 | Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); |
| 3179 | DCI.AddToWorklist(Val.Val); |
| 3180 | |
| 3181 | Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, |
| 3182 | N->getOperand(2), N->getOperand(3)); |
| 3183 | DCI.AddToWorklist(Val.Val); |
| 3184 | return Val; |
| 3185 | } |
Chris Lattner | d998938 | 2006-07-10 20:56:58 +0000 | [diff] [blame] | 3186 | |
| 3187 | // Turn STORE (BSWAP) -> sthbrx/stwbrx. |
| 3188 | if (N->getOperand(1).getOpcode() == ISD::BSWAP && |
| 3189 | N->getOperand(1).Val->hasOneUse() && |
| 3190 | (N->getOperand(1).getValueType() == MVT::i32 || |
| 3191 | N->getOperand(1).getValueType() == MVT::i16)) { |
| 3192 | SDOperand BSwapOp = N->getOperand(1).getOperand(0); |
| 3193 | // Do an any-extend to 32-bits if this is a half-word input. |
| 3194 | if (BSwapOp.getValueType() == MVT::i16) |
| 3195 | BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); |
| 3196 | |
| 3197 | return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp, |
| 3198 | N->getOperand(2), N->getOperand(3), |
| 3199 | DAG.getValueType(N->getOperand(1).getValueType())); |
| 3200 | } |
| 3201 | break; |
| 3202 | case ISD::BSWAP: |
| 3203 | // Turn BSWAP (LOAD) -> lhbrx/lwbrx. |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 3204 | if (ISD::isNON_EXTLoad(N->getOperand(0).Val) && |
Chris Lattner | d998938 | 2006-07-10 20:56:58 +0000 | [diff] [blame] | 3205 | N->getOperand(0).hasOneUse() && |
| 3206 | (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { |
| 3207 | SDOperand Load = N->getOperand(0); |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 3208 | LoadSDNode *LD = cast<LoadSDNode>(Load); |
Chris Lattner | d998938 | 2006-07-10 20:56:58 +0000 | [diff] [blame] | 3209 | // Create the byte-swapping load. |
| 3210 | std::vector<MVT::ValueType> VTs; |
| 3211 | VTs.push_back(MVT::i32); |
| 3212 | VTs.push_back(MVT::Other); |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 3213 | SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset()); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 3214 | SDOperand Ops[] = { |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 3215 | LD->getChain(), // Chain |
| 3216 | LD->getBasePtr(), // Ptr |
| 3217 | SV, // SrcValue |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 3218 | DAG.getValueType(N->getValueType(0)) // VT |
| 3219 | }; |
| 3220 | SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); |
Chris Lattner | d998938 | 2006-07-10 20:56:58 +0000 | [diff] [blame] | 3221 | |
| 3222 | // If this is an i16 load, insert the truncate. |
| 3223 | SDOperand ResVal = BSLoad; |
| 3224 | if (N->getValueType(0) == MVT::i16) |
| 3225 | ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); |
| 3226 | |
| 3227 | // First, combine the bswap away. This makes the value produced by the |
| 3228 | // load dead. |
| 3229 | DCI.CombineTo(N, ResVal); |
| 3230 | |
| 3231 | // Next, combine the load away, we give it a bogus result value but a real |
| 3232 | // chain result. The result value is dead because the bswap is dead. |
| 3233 | DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1)); |
| 3234 | |
| 3235 | // Return N so it doesn't get rechecked! |
| 3236 | return SDOperand(N, 0); |
| 3237 | } |
| 3238 | |
Chris Lattner | 5126984 | 2006-03-01 05:50:56 +0000 | [diff] [blame] | 3239 | break; |
Chris Lattner | 4468c22 | 2006-03-31 06:02:07 +0000 | [diff] [blame] | 3240 | case PPCISD::VCMP: { |
| 3241 | // If a VCMPo node already exists with exactly the same operands as this |
| 3242 | // node, use its result instead of this node (VCMPo computes both a CR6 and |
| 3243 | // a normal output). |
| 3244 | // |
| 3245 | if (!N->getOperand(0).hasOneUse() && |
| 3246 | !N->getOperand(1).hasOneUse() && |
| 3247 | !N->getOperand(2).hasOneUse()) { |
| 3248 | |
| 3249 | // Scan all of the users of the LHS, looking for VCMPo's that match. |
| 3250 | SDNode *VCMPoNode = 0; |
| 3251 | |
| 3252 | SDNode *LHSN = N->getOperand(0).Val; |
| 3253 | for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); |
| 3254 | UI != E; ++UI) |
| 3255 | if ((*UI)->getOpcode() == PPCISD::VCMPo && |
| 3256 | (*UI)->getOperand(1) == N->getOperand(1) && |
| 3257 | (*UI)->getOperand(2) == N->getOperand(2) && |
| 3258 | (*UI)->getOperand(0) == N->getOperand(0)) { |
| 3259 | VCMPoNode = *UI; |
| 3260 | break; |
| 3261 | } |
| 3262 | |
Chris Lattner | 0090120 | 2006-04-18 18:28:22 +0000 | [diff] [blame] | 3263 | // If there is no VCMPo node, or if the flag value has a single use, don't |
| 3264 | // transform this. |
| 3265 | if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) |
| 3266 | break; |
| 3267 | |
| 3268 | // Look at the (necessarily single) use of the flag value. If it has a |
| 3269 | // chain, this transformation is more complex. Note that multiple things |
| 3270 | // could use the value result, which we should ignore. |
| 3271 | SDNode *FlagUser = 0; |
| 3272 | for (SDNode::use_iterator UI = VCMPoNode->use_begin(); |
| 3273 | FlagUser == 0; ++UI) { |
| 3274 | assert(UI != VCMPoNode->use_end() && "Didn't find user!"); |
| 3275 | SDNode *User = *UI; |
| 3276 | for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { |
| 3277 | if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) { |
| 3278 | FlagUser = User; |
| 3279 | break; |
| 3280 | } |
| 3281 | } |
| 3282 | } |
| 3283 | |
| 3284 | // If the user is a MFCR instruction, we know this is safe. Otherwise we |
| 3285 | // give up for right now. |
| 3286 | if (FlagUser->getOpcode() == PPCISD::MFCR) |
Chris Lattner | 4468c22 | 2006-03-31 06:02:07 +0000 | [diff] [blame] | 3287 | return SDOperand(VCMPoNode, 0); |
| 3288 | } |
| 3289 | break; |
| 3290 | } |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3291 | case ISD::BR_CC: { |
| 3292 | // If this is a branch on an altivec predicate comparison, lower this so |
| 3293 | // that we don't have to do a MFCR: instead, branch directly on CR6. This |
| 3294 | // lowering is done pre-legalize, because the legalizer lowers the predicate |
| 3295 | // compare down to code that is difficult to reassemble. |
| 3296 | ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); |
| 3297 | SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3); |
| 3298 | int CompareOpc; |
| 3299 | bool isDot; |
| 3300 | |
| 3301 | if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && |
| 3302 | isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && |
| 3303 | getAltivecCompareInfo(LHS, CompareOpc, isDot)) { |
| 3304 | assert(isDot && "Can't compare against a vector result!"); |
| 3305 | |
| 3306 | // If this is a comparison against something other than 0/1, then we know |
| 3307 | // that the condition is never/always true. |
| 3308 | unsigned Val = cast<ConstantSDNode>(RHS)->getValue(); |
| 3309 | if (Val != 0 && Val != 1) { |
| 3310 | if (CC == ISD::SETEQ) // Cond never true, remove branch. |
| 3311 | return N->getOperand(0); |
| 3312 | // Always !=, turn it into an unconditional branch. |
| 3313 | return DAG.getNode(ISD::BR, MVT::Other, |
| 3314 | N->getOperand(0), N->getOperand(4)); |
| 3315 | } |
| 3316 | |
| 3317 | bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); |
| 3318 | |
| 3319 | // Create the PPCISD altivec 'dot' comparison node. |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3320 | std::vector<MVT::ValueType> VTs; |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 3321 | SDOperand Ops[] = { |
| 3322 | LHS.getOperand(2), // LHS of compare |
| 3323 | LHS.getOperand(3), // RHS of compare |
| 3324 | DAG.getConstant(CompareOpc, MVT::i32) |
| 3325 | }; |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3326 | VTs.push_back(LHS.getOperand(2).getValueType()); |
| 3327 | VTs.push_back(MVT::Flag); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 3328 | SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3329 | |
| 3330 | // Unpack the result based on how the target uses it. |
Chris Lattner | df4ed63 | 2006-11-17 22:10:59 +0000 | [diff] [blame] | 3331 | PPC::Predicate CompOpc; |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3332 | switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) { |
| 3333 | default: // Can't happen, don't crash on invalid number though. |
| 3334 | case 0: // Branch on the value of the EQ bit of CR6. |
Chris Lattner | df4ed63 | 2006-11-17 22:10:59 +0000 | [diff] [blame] | 3335 | CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3336 | break; |
| 3337 | case 1: // Branch on the inverted value of the EQ bit of CR6. |
Chris Lattner | df4ed63 | 2006-11-17 22:10:59 +0000 | [diff] [blame] | 3338 | CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3339 | break; |
| 3340 | case 2: // Branch on the value of the LT bit of CR6. |
Chris Lattner | df4ed63 | 2006-11-17 22:10:59 +0000 | [diff] [blame] | 3341 | CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3342 | break; |
| 3343 | case 3: // Branch on the inverted value of the LT bit of CR6. |
Chris Lattner | df4ed63 | 2006-11-17 22:10:59 +0000 | [diff] [blame] | 3344 | CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3345 | break; |
| 3346 | } |
| 3347 | |
| 3348 | return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3349 | DAG.getConstant(CompOpc, MVT::i32), |
Chris Lattner | 18258c6 | 2006-11-17 22:37:34 +0000 | [diff] [blame] | 3350 | DAG.getRegister(PPC::CR6, MVT::i32), |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3351 | N->getOperand(4), CompNode.getValue(1)); |
| 3352 | } |
| 3353 | break; |
| 3354 | } |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 3355 | } |
| 3356 | |
| 3357 | return SDOperand(); |
| 3358 | } |
| 3359 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3360 | //===----------------------------------------------------------------------===// |
| 3361 | // Inline Assembly Support |
| 3362 | //===----------------------------------------------------------------------===// |
| 3363 | |
Chris Lattner | bbe77de | 2006-04-02 06:26:07 +0000 | [diff] [blame] | 3364 | void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, |
| 3365 | uint64_t Mask, |
| 3366 | uint64_t &KnownZero, |
| 3367 | uint64_t &KnownOne, |
Dan Gohman | ea859be | 2007-06-22 14:59:07 +0000 | [diff] [blame] | 3368 | const SelectionDAG &DAG, |
Chris Lattner | bbe77de | 2006-04-02 06:26:07 +0000 | [diff] [blame] | 3369 | unsigned Depth) const { |
| 3370 | KnownZero = 0; |
| 3371 | KnownOne = 0; |
| 3372 | switch (Op.getOpcode()) { |
| 3373 | default: break; |
Chris Lattner | d998938 | 2006-07-10 20:56:58 +0000 | [diff] [blame] | 3374 | case PPCISD::LBRX: { |
| 3375 | // lhbrx is known to have the top bits cleared out. |
| 3376 | if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16) |
| 3377 | KnownZero = 0xFFFF0000; |
| 3378 | break; |
| 3379 | } |
Chris Lattner | bbe77de | 2006-04-02 06:26:07 +0000 | [diff] [blame] | 3380 | case ISD::INTRINSIC_WO_CHAIN: { |
| 3381 | switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) { |
| 3382 | default: break; |
| 3383 | case Intrinsic::ppc_altivec_vcmpbfp_p: |
| 3384 | case Intrinsic::ppc_altivec_vcmpeqfp_p: |
| 3385 | case Intrinsic::ppc_altivec_vcmpequb_p: |
| 3386 | case Intrinsic::ppc_altivec_vcmpequh_p: |
| 3387 | case Intrinsic::ppc_altivec_vcmpequw_p: |
| 3388 | case Intrinsic::ppc_altivec_vcmpgefp_p: |
| 3389 | case Intrinsic::ppc_altivec_vcmpgtfp_p: |
| 3390 | case Intrinsic::ppc_altivec_vcmpgtsb_p: |
| 3391 | case Intrinsic::ppc_altivec_vcmpgtsh_p: |
| 3392 | case Intrinsic::ppc_altivec_vcmpgtsw_p: |
| 3393 | case Intrinsic::ppc_altivec_vcmpgtub_p: |
| 3394 | case Intrinsic::ppc_altivec_vcmpgtuh_p: |
| 3395 | case Intrinsic::ppc_altivec_vcmpgtuw_p: |
| 3396 | KnownZero = ~1U; // All bits but the low one are known to be zero. |
| 3397 | break; |
| 3398 | } |
| 3399 | } |
| 3400 | } |
| 3401 | } |
| 3402 | |
| 3403 | |
Chris Lattner | 4234f57 | 2007-03-25 02:14:49 +0000 | [diff] [blame] | 3404 | /// getConstraintType - Given a constraint, return the type of |
Chris Lattner | ad3bc8d | 2006-02-07 20:16:30 +0000 | [diff] [blame] | 3405 | /// constraint it is for this target. |
| 3406 | PPCTargetLowering::ConstraintType |
Chris Lattner | 4234f57 | 2007-03-25 02:14:49 +0000 | [diff] [blame] | 3407 | PPCTargetLowering::getConstraintType(const std::string &Constraint) const { |
| 3408 | if (Constraint.size() == 1) { |
| 3409 | switch (Constraint[0]) { |
| 3410 | default: break; |
| 3411 | case 'b': |
| 3412 | case 'r': |
| 3413 | case 'f': |
| 3414 | case 'v': |
| 3415 | case 'y': |
| 3416 | return C_RegisterClass; |
| 3417 | } |
| 3418 | } |
| 3419 | return TargetLowering::getConstraintType(Constraint); |
Chris Lattner | ad3bc8d | 2006-02-07 20:16:30 +0000 | [diff] [blame] | 3420 | } |
| 3421 | |
Chris Lattner | 331d1bc | 2006-11-02 01:44:04 +0000 | [diff] [blame] | 3422 | std::pair<unsigned, const TargetRegisterClass*> |
| 3423 | PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, |
| 3424 | MVT::ValueType VT) const { |
Chris Lattner | ddc787d | 2006-01-31 19:20:21 +0000 | [diff] [blame] | 3425 | if (Constraint.size() == 1) { |
Chris Lattner | 331d1bc | 2006-11-02 01:44:04 +0000 | [diff] [blame] | 3426 | // GCC RS6000 Constraint Letters |
| 3427 | switch (Constraint[0]) { |
| 3428 | case 'b': // R1-R31 |
| 3429 | case 'r': // R0-R31 |
| 3430 | if (VT == MVT::i64 && PPCSubTarget.isPPC64()) |
| 3431 | return std::make_pair(0U, PPC::G8RCRegisterClass); |
| 3432 | return std::make_pair(0U, PPC::GPRCRegisterClass); |
| 3433 | case 'f': |
| 3434 | if (VT == MVT::f32) |
| 3435 | return std::make_pair(0U, PPC::F4RCRegisterClass); |
| 3436 | else if (VT == MVT::f64) |
| 3437 | return std::make_pair(0U, PPC::F8RCRegisterClass); |
| 3438 | break; |
Chris Lattner | ddc787d | 2006-01-31 19:20:21 +0000 | [diff] [blame] | 3439 | case 'v': |
Chris Lattner | 331d1bc | 2006-11-02 01:44:04 +0000 | [diff] [blame] | 3440 | return std::make_pair(0U, PPC::VRRCRegisterClass); |
| 3441 | case 'y': // crrc |
| 3442 | return std::make_pair(0U, PPC::CRRCRegisterClass); |
Chris Lattner | ddc787d | 2006-01-31 19:20:21 +0000 | [diff] [blame] | 3443 | } |
| 3444 | } |
| 3445 | |
Chris Lattner | 331d1bc | 2006-11-02 01:44:04 +0000 | [diff] [blame] | 3446 | return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); |
Chris Lattner | ddc787d | 2006-01-31 19:20:21 +0000 | [diff] [blame] | 3447 | } |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 3448 | |
Chris Lattner | 331d1bc | 2006-11-02 01:44:04 +0000 | [diff] [blame] | 3449 | |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 3450 | /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops |
| 3451 | /// vector. If it is invalid, don't add anything to Ops. |
| 3452 | void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter, |
| 3453 | std::vector<SDOperand>&Ops, |
| 3454 | SelectionDAG &DAG) { |
| 3455 | SDOperand Result(0,0); |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 3456 | switch (Letter) { |
| 3457 | default: break; |
| 3458 | case 'I': |
| 3459 | case 'J': |
| 3460 | case 'K': |
| 3461 | case 'L': |
| 3462 | case 'M': |
| 3463 | case 'N': |
| 3464 | case 'O': |
| 3465 | case 'P': { |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 3466 | ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 3467 | if (!CST) return; // Must be an immediate to match. |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 3468 | unsigned Value = CST->getValue(); |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 3469 | switch (Letter) { |
| 3470 | default: assert(0 && "Unknown constraint letter!"); |
| 3471 | case 'I': // "I" is a signed 16-bit constant. |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 3472 | if ((short)Value == (int)Value) |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 3473 | Result = DAG.getTargetConstant(Value, Op.getValueType()); |
Chris Lattner | dba1aee | 2006-10-31 19:40:43 +0000 | [diff] [blame] | 3474 | break; |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 3475 | case 'J': // "J" is a constant with only the high-order 16 bits nonzero. |
| 3476 | case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 3477 | if ((short)Value == 0) |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 3478 | Result = DAG.getTargetConstant(Value, Op.getValueType()); |
Chris Lattner | dba1aee | 2006-10-31 19:40:43 +0000 | [diff] [blame] | 3479 | break; |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 3480 | case 'K': // "K" is a constant with only the low-order 16 bits nonzero. |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 3481 | if ((Value >> 16) == 0) |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 3482 | Result = DAG.getTargetConstant(Value, Op.getValueType()); |
Chris Lattner | dba1aee | 2006-10-31 19:40:43 +0000 | [diff] [blame] | 3483 | break; |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 3484 | case 'M': // "M" is a constant that is greater than 31. |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 3485 | if (Value > 31) |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 3486 | Result = DAG.getTargetConstant(Value, Op.getValueType()); |
Chris Lattner | dba1aee | 2006-10-31 19:40:43 +0000 | [diff] [blame] | 3487 | break; |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 3488 | case 'N': // "N" is a positive constant that is an exact power of two. |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 3489 | if ((int)Value > 0 && isPowerOf2_32(Value)) |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 3490 | Result = DAG.getTargetConstant(Value, Op.getValueType()); |
Chris Lattner | dba1aee | 2006-10-31 19:40:43 +0000 | [diff] [blame] | 3491 | break; |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 3492 | case 'O': // "O" is the constant zero. |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 3493 | if (Value == 0) |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 3494 | Result = DAG.getTargetConstant(Value, Op.getValueType()); |
Chris Lattner | dba1aee | 2006-10-31 19:40:43 +0000 | [diff] [blame] | 3495 | break; |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 3496 | case 'P': // "P" is a constant whose negation is a signed 16-bit constant. |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 3497 | if ((short)-Value == (int)-Value) |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 3498 | Result = DAG.getTargetConstant(Value, Op.getValueType()); |
Chris Lattner | dba1aee | 2006-10-31 19:40:43 +0000 | [diff] [blame] | 3499 | break; |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 3500 | } |
| 3501 | break; |
| 3502 | } |
| 3503 | } |
| 3504 | |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 3505 | if (Result.Val) { |
| 3506 | Ops.push_back(Result); |
| 3507 | return; |
| 3508 | } |
| 3509 | |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 3510 | // Handle standard constraint letters. |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 3511 | TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG); |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 3512 | } |
Evan Cheng | c4c6257 | 2006-03-13 23:20:37 +0000 | [diff] [blame] | 3513 | |
Chris Lattner | c9addb7 | 2007-03-30 23:15:24 +0000 | [diff] [blame] | 3514 | // isLegalAddressingMode - Return true if the addressing mode represented |
| 3515 | // by AM is legal for this target, for a load/store of the specified type. |
| 3516 | bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, |
| 3517 | const Type *Ty) const { |
| 3518 | // FIXME: PPC does not allow r+i addressing modes for vectors! |
| 3519 | |
| 3520 | // PPC allows a sign-extended 16-bit immediate field. |
| 3521 | if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) |
| 3522 | return false; |
| 3523 | |
| 3524 | // No global is ever allowed as a base. |
| 3525 | if (AM.BaseGV) |
| 3526 | return false; |
| 3527 | |
| 3528 | // PPC only support r+r, |
| 3529 | switch (AM.Scale) { |
| 3530 | case 0: // "r+i" or just "i", depending on HasBaseReg. |
| 3531 | break; |
| 3532 | case 1: |
| 3533 | if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. |
| 3534 | return false; |
| 3535 | // Otherwise we have r+r or r+i. |
| 3536 | break; |
| 3537 | case 2: |
| 3538 | if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. |
| 3539 | return false; |
| 3540 | // Allow 2*r as r+r. |
| 3541 | break; |
Chris Lattner | 7c7ba9d | 2007-04-09 22:10:05 +0000 | [diff] [blame] | 3542 | default: |
| 3543 | // No other scales are supported. |
| 3544 | return false; |
Chris Lattner | c9addb7 | 2007-03-30 23:15:24 +0000 | [diff] [blame] | 3545 | } |
| 3546 | |
| 3547 | return true; |
| 3548 | } |
| 3549 | |
Evan Cheng | c4c6257 | 2006-03-13 23:20:37 +0000 | [diff] [blame] | 3550 | /// isLegalAddressImmediate - Return true if the integer value can be used |
Evan Cheng | 8619391 | 2007-03-12 23:29:01 +0000 | [diff] [blame] | 3551 | /// as the offset of the target addressing mode for load / store of the |
| 3552 | /// given type. |
| 3553 | bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ |
Evan Cheng | c4c6257 | 2006-03-13 23:20:37 +0000 | [diff] [blame] | 3554 | // PPC allows a sign-extended 16-bit immediate field. |
| 3555 | return (V > -(1 << 16) && V < (1 << 16)-1); |
| 3556 | } |
Reid Spencer | 3a9ec24 | 2006-08-28 01:02:49 +0000 | [diff] [blame] | 3557 | |
| 3558 | bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { |
Chris Lattner | c9addb7 | 2007-03-30 23:15:24 +0000 | [diff] [blame] | 3559 | return false; |
Reid Spencer | 3a9ec24 | 2006-08-28 01:02:49 +0000 | [diff] [blame] | 3560 | } |
Nicolas Geoffray | 43c6e7c | 2007-03-01 13:11:38 +0000 | [diff] [blame] | 3561 | |
| 3562 | SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) |
| 3563 | { |
| 3564 | // Depths > 0 not supported yet! |
| 3565 | if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) |
| 3566 | return SDOperand(); |
| 3567 | |
| 3568 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 3569 | bool isPPC64 = PtrVT == MVT::i64; |
| 3570 | |
| 3571 | MachineFunction &MF = DAG.getMachineFunction(); |
| 3572 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 3573 | bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects()) |
| 3574 | && MFI->getStackSize(); |
| 3575 | |
| 3576 | if (isPPC64) |
| 3577 | return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1, |
Bill Wendling | b8a80f0 | 2007-08-30 00:59:19 +0000 | [diff] [blame] | 3578 | MVT::i64); |
Nicolas Geoffray | 43c6e7c | 2007-03-01 13:11:38 +0000 | [diff] [blame] | 3579 | else |
| 3580 | return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1, |
| 3581 | MVT::i32); |
| 3582 | } |