| David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 1 | //===- Thumb1InstrInfo.h - Thumb-1 Instruction Information ----------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the Thumb-1 implementation of the TargetInstrInfo class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #ifndef THUMB1INSTRUCTIONINFO_H |
| 15 | #define THUMB1INSTRUCTIONINFO_H |
| 16 | |
| 17 | #include "llvm/Target/TargetInstrInfo.h" |
| 18 | #include "ARM.h" |
| 19 | #include "ARMInstrInfo.h" |
| 20 | #include "Thumb1RegisterInfo.h" |
| 21 | |
| 22 | namespace llvm { |
| 23 | class ARMSubtarget; |
| 24 | |
| 25 | class Thumb1InstrInfo : public ARMBaseInstrInfo { |
| 26 | Thumb1RegisterInfo RI; |
| 27 | public: |
| 28 | explicit Thumb1InstrInfo(const ARMSubtarget &STI); |
| 29 | |
| David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame^] | 30 | // Return the non-pre/post incrementing version of 'Opc'. Return 0 |
| 31 | // if there is not such an opcode. |
| 32 | unsigned getUnindexedOpcode(unsigned Opc) const; |
| 33 | |
| 34 | // Return the opcode that implements 'Op', or 0 if no opcode |
| 35 | unsigned getOpcode(ARMII::Op Op) const; |
| 36 | |
| 37 | // Return true if the block does not fall through. |
| 38 | bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const; |
| 39 | |
| David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 40 | /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As |
| 41 | /// such, whenever a client has an instance of instruction info, it should |
| 42 | /// always be able to get register info as well (through this method). |
| 43 | /// |
| 44 | const Thumb1RegisterInfo &getRegisterInfo() const { return RI; } |
| 45 | |
| 46 | bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 47 | MachineBasicBlock::iterator MI, |
| 48 | const std::vector<CalleeSavedInfo> &CSI) const; |
| 49 | bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 50 | MachineBasicBlock::iterator MI, |
| 51 | const std::vector<CalleeSavedInfo> &CSI) const; |
| 52 | |
| 53 | bool isMoveInstr(const MachineInstr &MI, |
| 54 | unsigned &SrcReg, unsigned &DstReg, |
| 55 | unsigned &SrcSubIdx, unsigned &DstSubIdx) const; |
| 56 | unsigned isLoadFromStackSlot(const MachineInstr *MI, |
| 57 | int &FrameIndex) const; |
| 58 | unsigned isStoreToStackSlot(const MachineInstr *MI, |
| 59 | int &FrameIndex) const; |
| 60 | |
| 61 | bool copyRegToReg(MachineBasicBlock &MBB, |
| 62 | MachineBasicBlock::iterator I, |
| 63 | unsigned DestReg, unsigned SrcReg, |
| 64 | const TargetRegisterClass *DestRC, |
| 65 | const TargetRegisterClass *SrcRC) const; |
| 66 | void storeRegToStackSlot(MachineBasicBlock &MBB, |
| 67 | MachineBasicBlock::iterator MBBI, |
| 68 | unsigned SrcReg, bool isKill, int FrameIndex, |
| 69 | const TargetRegisterClass *RC) const; |
| 70 | |
| 71 | void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, |
| 72 | SmallVectorImpl<MachineOperand> &Addr, |
| 73 | const TargetRegisterClass *RC, |
| 74 | SmallVectorImpl<MachineInstr*> &NewMIs) const; |
| 75 | |
| 76 | void loadRegFromStackSlot(MachineBasicBlock &MBB, |
| 77 | MachineBasicBlock::iterator MBBI, |
| 78 | unsigned DestReg, int FrameIndex, |
| 79 | const TargetRegisterClass *RC) const; |
| 80 | |
| 81 | void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, |
| 82 | SmallVectorImpl<MachineOperand> &Addr, |
| 83 | const TargetRegisterClass *RC, |
| 84 | SmallVectorImpl<MachineInstr*> &NewMIs) const; |
| 85 | |
| 86 | bool canFoldMemoryOperand(const MachineInstr *MI, |
| 87 | const SmallVectorImpl<unsigned> &Ops) const; |
| 88 | |
| 89 | MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, |
| 90 | MachineInstr* MI, |
| 91 | const SmallVectorImpl<unsigned> &Ops, |
| 92 | int FrameIndex) const; |
| 93 | |
| 94 | MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, |
| 95 | MachineInstr* MI, |
| 96 | const SmallVectorImpl<unsigned> &Ops, |
| 97 | MachineInstr* LoadMI) const { |
| 98 | return 0; |
| 99 | } |
| 100 | }; |
| 101 | } |
| 102 | |
| 103 | #endif // THUMB1INSTRUCTIONINFO_H |