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Dan Gohmanf17a25c2007-07-18 16:29:46 +00001//===-- MachineInstr.cpp --------------------------------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/CodeGen/MachineFunction.h"
16#include "llvm/Target/TargetMachine.h"
17#include "llvm/Target/TargetInstrInfo.h"
18#include "llvm/Target/MRegisterInfo.h"
19#include "llvm/Support/LeakDetector.h"
20#include "llvm/Support/Streams.h"
21#include <ostream>
22using namespace llvm;
23
24/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
25/// TID NULL and no operands.
26MachineInstr::MachineInstr()
27 : TID(0), NumImplicitOps(0), parent(0) {
28 // Make sure that we get added to a machine basicblock
29 LeakDetector::addGarbageObject(this);
30}
31
32void MachineInstr::addImplicitDefUseOperands() {
33 if (TID->ImplicitDefs)
34 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) {
35 MachineOperand Op;
36 Op.opType = MachineOperand::MO_Register;
37 Op.IsDef = true;
38 Op.IsImp = true;
39 Op.IsKill = false;
40 Op.IsDead = false;
41 Op.contents.RegNo = *ImpDefs;
Evan Cheng4d0fbf32007-11-14 07:59:08 +000042 Op.auxInfo.subReg = 0;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000043 Operands.push_back(Op);
44 }
45 if (TID->ImplicitUses)
46 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) {
47 MachineOperand Op;
48 Op.opType = MachineOperand::MO_Register;
49 Op.IsDef = false;
50 Op.IsImp = true;
51 Op.IsKill = false;
52 Op.IsDead = false;
53 Op.contents.RegNo = *ImpUses;
Evan Cheng4d0fbf32007-11-14 07:59:08 +000054 Op.auxInfo.subReg = 0;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000055 Operands.push_back(Op);
56 }
57}
58
59/// MachineInstr ctor - This constructor create a MachineInstr and add the
60/// implicit operands. It reserves space for number of operands specified by
61/// TargetInstrDescriptor or the numOperands if it is not zero. (for
62/// instructions with variable number of operands).
Evan Chengbdf72b42007-10-13 02:23:01 +000063MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
Dan Gohmanf17a25c2007-07-18 16:29:46 +000064 : TID(&tid), NumImplicitOps(0), parent(0) {
Evan Chengbdf72b42007-10-13 02:23:01 +000065 if (!NoImp && TID->ImplicitDefs)
Dan Gohmanf17a25c2007-07-18 16:29:46 +000066 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
67 NumImplicitOps++;
Evan Chengbdf72b42007-10-13 02:23:01 +000068 if (!NoImp && TID->ImplicitUses)
Dan Gohmanf17a25c2007-07-18 16:29:46 +000069 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
70 NumImplicitOps++;
71 Operands.reserve(NumImplicitOps + TID->numOperands);
Evan Chengbdf72b42007-10-13 02:23:01 +000072 if (!NoImp)
73 addImplicitDefUseOperands();
Dan Gohmanf17a25c2007-07-18 16:29:46 +000074 // Make sure that we get added to a machine basicblock
75 LeakDetector::addGarbageObject(this);
76}
77
78/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
79/// MachineInstr is created and added to the end of the specified basic block.
80///
81MachineInstr::MachineInstr(MachineBasicBlock *MBB,
82 const TargetInstrDescriptor &tid)
83 : TID(&tid), NumImplicitOps(0), parent(0) {
84 assert(MBB && "Cannot use inserting ctor with null basic block!");
85 if (TID->ImplicitDefs)
86 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
87 NumImplicitOps++;
88 if (TID->ImplicitUses)
89 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
90 NumImplicitOps++;
91 Operands.reserve(NumImplicitOps + TID->numOperands);
92 addImplicitDefUseOperands();
93 // Make sure that we get added to a machine basicblock
94 LeakDetector::addGarbageObject(this);
95 MBB->push_back(this); // Add instruction to end of basic block!
96}
97
98/// MachineInstr ctor - Copies MachineInstr arg exactly
99///
100MachineInstr::MachineInstr(const MachineInstr &MI) {
101 TID = MI.getInstrDescriptor();
102 NumImplicitOps = MI.NumImplicitOps;
103 Operands.reserve(MI.getNumOperands());
104
105 // Add operands
106 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
107 Operands.push_back(MI.getOperand(i));
108
109 // Set parent, next, and prev to null
110 parent = 0;
111 prev = 0;
112 next = 0;
113}
114
115
116MachineInstr::~MachineInstr() {
117 LeakDetector::removeGarbageObject(this);
118}
119
120/// getOpcode - Returns the opcode of this MachineInstr.
121///
Dan Gohman5f222be2007-09-14 20:08:19 +0000122int MachineInstr::getOpcode() const {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000123 return TID->Opcode;
124}
125
126/// removeFromParent - This method unlinks 'this' from the containing basic
127/// block, and returns it, but does not delete it.
128MachineInstr *MachineInstr::removeFromParent() {
129 assert(getParent() && "Not embedded in a basic block!");
130 getParent()->remove(this);
131 return this;
132}
133
134
135/// OperandComplete - Return true if it's illegal to add a new operand
136///
137bool MachineInstr::OperandsComplete() const {
138 unsigned short NumOperands = TID->numOperands;
139 if ((TID->Flags & M_VARIABLE_OPS) == 0 &&
140 getNumOperands()-NumImplicitOps >= NumOperands)
141 return true; // Broken: we have all the operands of this instruction!
142 return false;
143}
144
145/// getNumExplicitOperands - Returns the number of non-implicit operands.
146///
147unsigned MachineInstr::getNumExplicitOperands() const {
148 unsigned NumOperands = TID->numOperands;
149 if ((TID->Flags & M_VARIABLE_OPS) == 0)
150 return NumOperands;
151
152 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
153 const MachineOperand &MO = getOperand(NumOperands);
154 if (!MO.isRegister() || !MO.isImplicit())
155 NumOperands++;
156 }
157 return NumOperands;
158}
159
160/// isIdenticalTo - Return true if this operand is identical to the specified
161/// operand.
162bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
163 if (getType() != Other.getType()) return false;
164
165 switch (getType()) {
166 default: assert(0 && "Unrecognized operand type");
167 case MachineOperand::MO_Register:
168 return getReg() == Other.getReg() && isDef() == Other.isDef();
169 case MachineOperand::MO_Immediate:
170 return getImm() == Other.getImm();
171 case MachineOperand::MO_MachineBasicBlock:
172 return getMBB() == Other.getMBB();
173 case MachineOperand::MO_FrameIndex:
174 return getFrameIndex() == Other.getFrameIndex();
175 case MachineOperand::MO_ConstantPoolIndex:
176 return getConstantPoolIndex() == Other.getConstantPoolIndex() &&
177 getOffset() == Other.getOffset();
178 case MachineOperand::MO_JumpTableIndex:
179 return getJumpTableIndex() == Other.getJumpTableIndex();
180 case MachineOperand::MO_GlobalAddress:
181 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
182 case MachineOperand::MO_ExternalSymbol:
183 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
184 getOffset() == Other.getOffset();
185 }
186}
187
188/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
189/// the specific register or -1 if it is not found. It further tightening
190/// the search criteria to a use that kills the register if isKill is true.
191int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
192 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
193 const MachineOperand &MO = getOperand(i);
Dan Gohman38a9a9f2007-09-14 20:33:02 +0000194 if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000195 if (!isKill || MO.isKill())
196 return i;
197 }
198 return -1;
199}
200
201/// findRegisterDefOperand() - Returns the MachineOperand that is a def of
202/// the specific register or NULL if it is not found.
203MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
204 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
205 MachineOperand &MO = getOperand(i);
Dan Gohman38a9a9f2007-09-14 20:33:02 +0000206 if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000207 return &MO;
208 }
209 return NULL;
210}
211
212/// findFirstPredOperandIdx() - Find the index of the first operand in the
213/// operand list that is used to represent the predicate. It returns -1 if
214/// none is found.
215int MachineInstr::findFirstPredOperandIdx() const {
216 const TargetInstrDescriptor *TID = getInstrDescriptor();
217 if (TID->Flags & M_PREDICABLE) {
218 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
219 if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
220 return i;
221 }
222
223 return -1;
224}
225
Evan Cheng687d1082007-10-12 08:50:34 +0000226/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
227/// to two addr elimination.
228bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
229 const TargetInstrDescriptor *TID = getInstrDescriptor();
230 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
231 const MachineOperand &MO1 = getOperand(i);
232 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
233 for (unsigned j = i+1; j < e; ++j) {
234 const MachineOperand &MO2 = getOperand(j);
235 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
236 TID->getOperandConstraint(j, TOI::TIED_TO) == (int)i)
237 return true;
238 }
239 }
240 }
241 return false;
242}
243
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000244/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
245///
246void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
247 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
248 const MachineOperand &MO = MI->getOperand(i);
Dan Gohman38a9a9f2007-09-14 20:33:02 +0000249 if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000250 continue;
251 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
252 MachineOperand &MOp = getOperand(j);
253 if (!MOp.isIdenticalTo(MO))
254 continue;
255 if (MO.isKill())
256 MOp.setIsKill();
257 else
258 MOp.setIsDead();
259 break;
260 }
261 }
262}
263
264/// copyPredicates - Copies predicate operand(s) from MI.
265void MachineInstr::copyPredicates(const MachineInstr *MI) {
266 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
267 if (TID->Flags & M_PREDICABLE) {
268 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
269 if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
270 const MachineOperand &MO = MI->getOperand(i);
271 // Predicated operands must be last operands.
Dan Gohman38a9a9f2007-09-14 20:33:02 +0000272 if (MO.isRegister())
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000273 addRegOperand(MO.getReg(), false);
274 else {
275 addImmOperand(MO.getImm());
276 }
277 }
278 }
279 }
280}
281
282void MachineInstr::dump() const {
283 cerr << " " << *this;
284}
285
286static inline void OutputReg(std::ostream &os, unsigned RegNo,
287 const MRegisterInfo *MRI = 0) {
288 if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
289 if (MRI)
290 os << "%" << MRI->get(RegNo).Name;
291 else
292 os << "%mreg(" << RegNo << ")";
293 } else
294 os << "%reg" << RegNo;
295}
296
297static void print(const MachineOperand &MO, std::ostream &OS,
298 const TargetMachine *TM) {
299 const MRegisterInfo *MRI = 0;
300
301 if (TM) MRI = TM->getRegisterInfo();
302
303 switch (MO.getType()) {
304 case MachineOperand::MO_Register:
305 OutputReg(OS, MO.getReg(), MRI);
306 break;
307 case MachineOperand::MO_Immediate:
308 OS << MO.getImmedValue();
309 break;
310 case MachineOperand::MO_MachineBasicBlock:
311 OS << "mbb<"
312 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
313 << "," << (void*)MO.getMachineBasicBlock() << ">";
314 break;
315 case MachineOperand::MO_FrameIndex:
316 OS << "<fi#" << MO.getFrameIndex() << ">";
317 break;
318 case MachineOperand::MO_ConstantPoolIndex:
319 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
320 break;
321 case MachineOperand::MO_JumpTableIndex:
322 OS << "<jt#" << MO.getJumpTableIndex() << ">";
323 break;
324 case MachineOperand::MO_GlobalAddress:
325 OS << "<ga:" << ((Value*)MO.getGlobal())->getName();
326 if (MO.getOffset()) OS << "+" << MO.getOffset();
327 OS << ">";
328 break;
329 case MachineOperand::MO_ExternalSymbol:
330 OS << "<es:" << MO.getSymbolName();
331 if (MO.getOffset()) OS << "+" << MO.getOffset();
332 OS << ">";
333 break;
334 default:
335 assert(0 && "Unrecognized operand type");
336 }
337}
338
339void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
340 unsigned StartOp = 0;
341
342 // Specialize printing if op#0 is definition
Dan Gohman38a9a9f2007-09-14 20:33:02 +0000343 if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000344 ::print(getOperand(0), OS, TM);
345 if (getOperand(0).isDead())
346 OS << "<dead>";
347 OS << " = ";
348 ++StartOp; // Don't print this operand again!
349 }
350
351 if (TID)
352 OS << TID->Name;
353
354 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
355 const MachineOperand& mop = getOperand(i);
356 if (i != StartOp)
357 OS << ",";
358 OS << " ";
359 ::print(mop, OS, TM);
360
Dan Gohman38a9a9f2007-09-14 20:33:02 +0000361 if (mop.isRegister()) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000362 if (mop.isDef() || mop.isKill() || mop.isDead() || mop.isImplicit()) {
363 OS << "<";
364 bool NeedComma = false;
365 if (mop.isImplicit()) {
366 OS << (mop.isDef() ? "imp-def" : "imp-use");
367 NeedComma = true;
368 } else if (mop.isDef()) {
369 OS << "def";
370 NeedComma = true;
371 }
372 if (mop.isKill() || mop.isDead()) {
373 if (NeedComma)
374 OS << ",";
375 if (mop.isKill())
376 OS << "kill";
377 if (mop.isDead())
378 OS << "dead";
379 }
380 OS << ">";
381 }
382 }
383 }
384
385 OS << "\n";
386}
387
388void MachineInstr::print(std::ostream &os) const {
389 // If the instruction is embedded into a basic block, we can find the target
390 // info for the instruction.
391 if (const MachineBasicBlock *MBB = getParent()) {
392 const MachineFunction *MF = MBB->getParent();
393 if (MF)
394 print(os, &MF->getTarget());
395 else
396 print(os, 0);
397 }
398
399 // Otherwise, print it out in the "raw" format without symbolic register names
400 // and such.
401 os << getInstrDescriptor()->Name;
402
403 for (unsigned i = 0, N = getNumOperands(); i < N; i++) {
404 os << "\t" << getOperand(i);
Dan Gohman38a9a9f2007-09-14 20:33:02 +0000405 if (getOperand(i).isRegister() && getOperand(i).isDef())
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000406 os << "<d>";
407 }
408
409 os << "\n";
410}
411
412void MachineOperand::print(std::ostream &OS) const {
413 switch (getType()) {
414 case MO_Register:
415 OutputReg(OS, getReg());
416 break;
417 case MO_Immediate:
418 OS << (long)getImmedValue();
419 break;
420 case MO_MachineBasicBlock:
421 OS << "<mbb:"
422 << ((Value*)getMachineBasicBlock()->getBasicBlock())->getName()
423 << "@" << (void*)getMachineBasicBlock() << ">";
424 break;
425 case MO_FrameIndex:
426 OS << "<fi#" << getFrameIndex() << ">";
427 break;
428 case MO_ConstantPoolIndex:
429 OS << "<cp#" << getConstantPoolIndex() << ">";
430 break;
431 case MO_JumpTableIndex:
432 OS << "<jt#" << getJumpTableIndex() << ">";
433 break;
434 case MO_GlobalAddress:
435 OS << "<ga:" << ((Value*)getGlobal())->getName() << ">";
436 break;
437 case MO_ExternalSymbol:
438 OS << "<es:" << getSymbolName() << ">";
439 break;
440 default:
441 assert(0 && "Unrecognized operand type");
442 break;
443 }
444}
445