Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1 | //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===// |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 9 | // |
| 10 | // This file describes the X86 instruction set, defining the instructions, and |
| 11 | // properties of the instructions which are needed for code generation, machine |
| 12 | // code emission, and analysis. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 16 | //===----------------------------------------------------------------------===// |
| 17 | // X86 specific DAG Nodes. |
| 18 | // |
| 19 | |
| 20 | def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, |
| 21 | SDTCisSameAs<1, 2>]>; |
| 22 | |
| 23 | def SDTX86Cmov : SDTypeProfile<1, 4, |
| 24 | [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, |
| 25 | SDTCisVT<3, OtherVT>, SDTCisVT<4, FlagVT>]>; |
| 26 | |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 27 | def SDTX86BrCond : SDTypeProfile<0, 3, |
| 28 | [SDTCisVT<0, OtherVT>, |
| 29 | SDTCisVT<1, OtherVT>, SDTCisVT<2, FlagVT>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 30 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 31 | def SDTX86SetCC : SDTypeProfile<1, 2, |
| 32 | [SDTCisVT<0, i8>, SDTCisVT<1, OtherVT>, |
| 33 | SDTCisVT<2, FlagVT>]>; |
| 34 | |
| 35 | def SDTX86RetFlag : SDTypeProfile<0, 2, [SDTCisVT<0, i16>, |
| 36 | SDTCisVT<1, FlagVT>]>; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 37 | |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 38 | def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 39 | SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>; |
| 40 | |
Evan Cheng | 5bc4da4 | 2005-12-22 02:26:21 +0000 | [diff] [blame] | 41 | def SDTX86FpSet : SDTypeProfile<1, 1, [SDTCisVT<0, FlagVT>, SDTCisFP<1>]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 42 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 43 | def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest, []>; |
| 44 | def X86test : SDNode<"X86ISD::TEST", SDTX86CmpTest, []>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 45 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 46 | def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov, []>; |
| 47 | def X86Brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, [SDNPHasChain]>; |
| 48 | def X86SetCC : SDNode<"X86ISD::SETCC", SDTX86SetCC, []>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 49 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 50 | def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86RetFlag, [SDNPHasChain]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 51 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 52 | def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, [SDNPHasChain]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 53 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 54 | def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", |
| 55 | SDTX86FpSet, [SDNPHasChain]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 56 | |
| 57 | //===----------------------------------------------------------------------===// |
| 58 | // X86 Operand Definitions. |
| 59 | // |
| 60 | |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 61 | // *mem - Operand definitions for the funky X86 addressing mode operands. |
| 62 | // |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 63 | class X86MemOperand<string printMethod> : Operand<i32> { |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 64 | let PrintMethod = printMethod; |
Chris Lattner | 6adaf79 | 2005-11-19 07:01:30 +0000 | [diff] [blame] | 65 | let NumMIOperands = 4; |
| 66 | let MIOperandInfo = (ops R32, i8imm, R32, i32imm); |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 67 | } |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 68 | |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 69 | def i8mem : X86MemOperand<"printi8mem">; |
| 70 | def i16mem : X86MemOperand<"printi16mem">; |
| 71 | def i32mem : X86MemOperand<"printi32mem">; |
| 72 | def i64mem : X86MemOperand<"printi64mem">; |
| 73 | def f32mem : X86MemOperand<"printf32mem">; |
| 74 | def f64mem : X86MemOperand<"printf64mem">; |
| 75 | def f80mem : X86MemOperand<"printf80mem">; |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 76 | |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 77 | def SSECC : Operand<i8> { |
| 78 | let PrintMethod = "printSSECC"; |
| 79 | } |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 80 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 81 | // A couple of more descriptive operand definitions. |
| 82 | // 16-bits but only 8 bits are significant. |
| 83 | def i16i8imm : Operand<i16>; |
| 84 | // 32-bits but only 8 bits are significant. |
| 85 | def i32i8imm : Operand<i32>; |
| 86 | |
Chris Lattner | e4ead0c | 2004-08-11 06:59:12 +0000 | [diff] [blame] | 87 | // PCRelative calls need special operand formatting. |
| 88 | let PrintMethod = "printCallOperand" in |
| 89 | def calltarget : Operand<i32>; |
| 90 | |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 91 | // Branch targets have OtherVT type. |
| 92 | def brtarget : Operand<OtherVT>; |
| 93 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 94 | //===----------------------------------------------------------------------===// |
| 95 | // X86 Complex Pattern Definitions. |
| 96 | // |
| 97 | |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 98 | // Define X86 specific addressing mode. |
Evan Cheng | 670fd8f | 2005-12-08 02:15:07 +0000 | [diff] [blame] | 99 | def addr : ComplexPattern<i32, 4, "SelectAddr", []>; |
Evan Cheng | 502c5bb | 2005-12-15 08:31:04 +0000 | [diff] [blame] | 100 | def leaaddr : ComplexPattern<i32, 4, "SelectLEAAddr", |
Evan Cheng | 3a03ebb | 2005-12-21 23:05:39 +0000 | [diff] [blame] | 101 | [add, frameindex, constpool, |
| 102 | globaladdr, tglobaladdr, externalsym]>; |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 103 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 104 | //===----------------------------------------------------------------------===// |
| 105 | // X86 Instruction Format Definitions. |
| 106 | // |
| 107 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 108 | // Format specifies the encoding used by the instruction. This is part of the |
| 109 | // ad-hoc solution used to emit machine instruction encodings by our machine |
| 110 | // code emitter. |
| 111 | class Format<bits<5> val> { |
| 112 | bits<5> Value = val; |
| 113 | } |
| 114 | |
| 115 | def Pseudo : Format<0>; def RawFrm : Format<1>; |
| 116 | def AddRegFrm : Format<2>; def MRMDestReg : Format<3>; |
| 117 | def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>; |
| 118 | def MRMSrcMem : Format<6>; |
Alkis Evlogimenos | 169584e | 2004-02-27 18:55:12 +0000 | [diff] [blame] | 119 | def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>; |
| 120 | def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>; |
| 121 | def MRM6r : Format<22>; def MRM7r : Format<23>; |
| 122 | def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>; |
| 123 | def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>; |
| 124 | def MRM6m : Format<30>; def MRM7m : Format<31>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 125 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 126 | //===----------------------------------------------------------------------===// |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 127 | // X86 Instruction Predicate Definitions. |
| 128 | def HasSSE1 : Predicate<"X86Vector >= SSE">; |
| 129 | def HasSSE2 : Predicate<"X86Vector >= SSE2">; |
| 130 | def HasSSE3 : Predicate<"X86Vector >= SSE3">; |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 131 | def FPStack : Predicate<"X86Vector < SSE2">; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 132 | |
| 133 | //===----------------------------------------------------------------------===// |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 134 | // X86 specific pattern fragments. |
| 135 | // |
| 136 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 137 | // ImmType - This specifies the immediate type used by an instruction. This is |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 138 | // part of the ad-hoc solution used to emit machine instruction encodings by our |
| 139 | // machine code emitter. |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 140 | class ImmType<bits<2> val> { |
| 141 | bits<2> Value = val; |
| 142 | } |
| 143 | def NoImm : ImmType<0>; |
| 144 | def Imm8 : ImmType<1>; |
| 145 | def Imm16 : ImmType<2>; |
| 146 | def Imm32 : ImmType<3>; |
| 147 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 148 | // FPFormat - This specifies what form this FP instruction has. This is used by |
| 149 | // the Floating-Point stackifier pass. |
| 150 | class FPFormat<bits<3> val> { |
| 151 | bits<3> Value = val; |
| 152 | } |
| 153 | def NotFP : FPFormat<0>; |
| 154 | def ZeroArgFP : FPFormat<1>; |
| 155 | def OneArgFP : FPFormat<2>; |
| 156 | def OneArgFPRW : FPFormat<3>; |
| 157 | def TwoArgFP : FPFormat<4>; |
Chris Lattner | ab8decc | 2004-06-11 04:41:24 +0000 | [diff] [blame] | 158 | def CompareFP : FPFormat<5>; |
| 159 | def CondMovFP : FPFormat<6>; |
| 160 | def SpecialFP : FPFormat<7>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 161 | |
| 162 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 163 | class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> |
| 164 | : Instruction { |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 165 | let Namespace = "X86"; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 166 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 167 | bits<8> Opcode = opcod; |
| 168 | Format Form = f; |
| 169 | bits<5> FormBits = Form.Value; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 170 | ImmType ImmT = i; |
| 171 | bits<2> ImmTypeBits = ImmT.Value; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 172 | |
Chris Lattner | c96bb81 | 2004-08-11 07:12:04 +0000 | [diff] [blame] | 173 | dag OperandList = ops; |
| 174 | string AsmString = AsmStr; |
| 175 | |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 176 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 177 | // Attributes specific to X86 instructions... |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 178 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 179 | bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 180 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 181 | bits<4> Prefix = 0; // Which prefix byte does this inst have? |
| 182 | FPFormat FPForm; // What flavor of FP instruction is this? |
| 183 | bits<3> FPFormBits = 0; |
| 184 | } |
| 185 | |
| 186 | class Imp<list<Register> uses, list<Register> defs> { |
| 187 | list<Register> Uses = uses; |
| 188 | list<Register> Defs = defs; |
| 189 | } |
| 190 | |
| 191 | |
| 192 | // Prefix byte classes which are used to indicate to the ad-hoc machine code |
| 193 | // emitter that various prefix bytes are required. |
| 194 | class OpSize { bit hasOpSizePrefix = 1; } |
| 195 | class TB { bits<4> Prefix = 1; } |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 196 | class REP { bits<4> Prefix = 2; } |
| 197 | class D8 { bits<4> Prefix = 3; } |
| 198 | class D9 { bits<4> Prefix = 4; } |
| 199 | class DA { bits<4> Prefix = 5; } |
| 200 | class DB { bits<4> Prefix = 6; } |
| 201 | class DC { bits<4> Prefix = 7; } |
| 202 | class DD { bits<4> Prefix = 8; } |
| 203 | class DE { bits<4> Prefix = 9; } |
| 204 | class DF { bits<4> Prefix = 10; } |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 205 | class XD { bits<4> Prefix = 11; } |
| 206 | class XS { bits<4> Prefix = 12; } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 207 | |
| 208 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 209 | //===----------------------------------------------------------------------===// |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 210 | // Pattern fragments... |
| 211 | // |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 212 | def i16immSExt8 : PatLeaf<(i16 imm), [{ |
| 213 | // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 214 | // sign extended field. |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 215 | return (int)N->getValue() == (signed char)N->getValue(); |
| 216 | }]>; |
| 217 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 218 | def i32immSExt8 : PatLeaf<(i32 imm), [{ |
| 219 | // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 220 | // sign extended field. |
| 221 | return (int)N->getValue() == (signed char)N->getValue(); |
| 222 | }]>; |
| 223 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 224 | def i16immZExt8 : PatLeaf<(i16 imm), [{ |
| 225 | // i16immZExt8 predicate - True if the 16-bit immediate fits in a 8-bit zero |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 226 | // extended field. |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 227 | return (unsigned)N->getValue() == (unsigned char)N->getValue(); |
| 228 | }]>; |
| 229 | |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 230 | // Helper fragments for loads. |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 231 | def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; |
| 232 | def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>; |
| 233 | def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 234 | def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; |
| 235 | def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 236 | |
| 237 | def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i1))>; |
| 238 | def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i1))>; |
| 239 | def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i8))>; |
| 240 | def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i8))>; |
| 241 | def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i16))>; |
| 242 | |
| 243 | def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i1))>; |
| 244 | def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i1))>; |
| 245 | def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i8))>; |
| 246 | def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i8))>; |
| 247 | def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i16))>; |
| 248 | |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 249 | def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extload node:$ptr, i1))>; |
| 250 | def extloadf64f32 : PatFrag<(ops node:$ptr), (f64 (extload node:$ptr, f32))>; |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 251 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 252 | //===----------------------------------------------------------------------===// |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 253 | // Instruction templates... |
| 254 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 255 | class I<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 256 | : X86Inst<o, f, NoImm, ops, asm> { |
| 257 | let Pattern = pattern; |
| 258 | } |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 259 | class Ii8 <bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 260 | : X86Inst<o, f, Imm8 , ops, asm> { |
| 261 | let Pattern = pattern; |
| 262 | } |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 263 | class Ii16<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 264 | : X86Inst<o, f, Imm16, ops, asm> { |
| 265 | let Pattern = pattern; |
| 266 | } |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 267 | class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 268 | : X86Inst<o, f, Imm32, ops, asm> { |
| 269 | let Pattern = pattern; |
| 270 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 271 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 272 | //===----------------------------------------------------------------------===// |
| 273 | // Instruction list... |
| 274 | // |
| 275 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 276 | def PHI : I<0, Pseudo, (ops variable_ops), "PHINODE", []>; // PHI node. |
| 277 | def NOOP : I<0x90, RawFrm, (ops), "nop", []>; // nop |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 278 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 279 | def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN", []>; |
Chris Lattner | 43ef131 | 2005-09-14 21:10:24 +0000 | [diff] [blame] | 280 | def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 281 | "#ADJCALLSTACKUP", []>; |
| 282 | def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>; |
| 283 | def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>; |
Alkis Evlogimenos | e0bb3e7 | 2003-12-20 16:22:59 +0000 | [diff] [blame] | 284 | let isTerminator = 1 in |
| 285 | let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 286 | def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>; |
Chris Lattner | 62cce39 | 2004-07-31 02:10:53 +0000 | [diff] [blame] | 287 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 288 | //===----------------------------------------------------------------------===// |
| 289 | // Control Flow Instructions... |
| 290 | // |
| 291 | |
Chris Lattner | 1be4811 | 2005-05-13 17:56:48 +0000 | [diff] [blame] | 292 | // Return instructions. |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 293 | let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in |
Evan Cheng | 793ca4c | 2005-12-21 22:22:16 +0000 | [diff] [blame] | 294 | def RET : I<0xC3, RawFrm, (ops), "ret", [(ret)]>; |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 295 | let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 296 | def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 297 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 298 | def : Pat<(X86retflag 0, FLAG), (RET)>; |
| 299 | def : Pat<(X86retflag imm:$amt, FLAG), (RETI imm:$amt)>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 300 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 301 | // All branches are RawFrm, Void, Branch, and Terminators |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 302 | let isBranch = 1, isTerminator = 1 in |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 303 | class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> : |
| 304 | I<opcode, RawFrm, ops, asm, pattern>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 305 | |
Chris Lattner | 62cce39 | 2004-07-31 02:10:53 +0000 | [diff] [blame] | 306 | let isBarrier = 1 in |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 307 | def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 308 | |
| 309 | def JE : IBr<0x84, (ops brtarget:$dst), "je $dst", |
| 310 | [(X86Brcond bb:$dst, SETEQ, STATUS)]>, Imp<[STATUS],[]>, TB; |
| 311 | def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst", |
| 312 | [(X86Brcond bb:$dst, SETNE, STATUS)]>, Imp<[STATUS],[]>, TB; |
| 313 | def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst", |
| 314 | [(X86Brcond bb:$dst, SETLT, STATUS)]>, Imp<[STATUS],[]>, TB; |
| 315 | def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst", |
| 316 | [(X86Brcond bb:$dst, SETLE, STATUS)]>, Imp<[STATUS],[]>, TB; |
| 317 | def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst", |
| 318 | [(X86Brcond bb:$dst, SETGT, STATUS)]>, Imp<[STATUS],[]>, TB; |
| 319 | def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst", |
| 320 | [(X86Brcond bb:$dst, SETGE, STATUS)]>, Imp<[STATUS],[]>, TB; |
| 321 | |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 322 | def JB : IBr<0x82, (ops brtarget:$dst), "jb $dst", |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 323 | [(X86Brcond bb:$dst, SETULT, STATUS)]>, Imp<[STATUS],[]>, TB; |
| 324 | def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst", |
| 325 | [(X86Brcond bb:$dst, SETULE, STATUS)]>, Imp<[STATUS],[]>, TB; |
| 326 | def JA : IBr<0x87, (ops brtarget:$dst), "ja $dst", |
| 327 | [(X86Brcond bb:$dst, SETUGT, STATUS)]>, Imp<[STATUS],[]>, TB; |
| 328 | def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst", |
| 329 | [(X86Brcond bb:$dst, SETUGE, STATUS)]>, Imp<[STATUS],[]>, TB; |
| 330 | |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 331 | def JS : IBr<0x88, (ops brtarget:$dst), "js $dst", []>, TB; |
| 332 | def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst", []>, TB; |
| 333 | def JP : IBr<0x8A, (ops brtarget:$dst), "jp $dst", []>, TB; |
| 334 | def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst", []>, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 335 | |
| 336 | //===----------------------------------------------------------------------===// |
| 337 | // Call Instructions... |
| 338 | // |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 339 | let isCall = 1 in |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 340 | // All calls clobber the non-callee saved registers... |
Nate Begeman | f63be7d | 2005-07-06 18:59:04 +0000 | [diff] [blame] | 341 | let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 342 | XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in { |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 343 | def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst", []>; |
| 344 | def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst", []>; |
| 345 | def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst", []>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 346 | } |
| 347 | |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 348 | // Tail call stuff. |
Chris Lattner | 2b3d56e | 2005-05-14 23:35:21 +0000 | [diff] [blame] | 349 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 350 | def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst # TAIL CALL", []>; |
Chris Lattner | 2b3d56e | 2005-05-14 23:35:21 +0000 | [diff] [blame] | 351 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 352 | def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst # TAIL CALL", []>; |
Chris Lattner | 2b3d56e | 2005-05-14 23:35:21 +0000 | [diff] [blame] | 353 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 354 | def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst), |
| 355 | "jmp {*}$dst # TAIL CALL", []>; |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 356 | |
| 357 | // ADJSTACKPTRri - This is a standard ADD32ri instruction, identical in every |
| 358 | // way, except that it is marked as being a terminator. This causes the epilog |
| 359 | // inserter to insert reloads of callee saved registers BEFORE this. We need |
| 360 | // this until we have a more accurate way of tracking where the stack pointer is |
| 361 | // within a function. |
| 362 | let isTerminator = 1, isTwoAddress = 1 in |
| 363 | def ADJSTACKPTRri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 364 | "add{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 365 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 366 | //===----------------------------------------------------------------------===// |
| 367 | // Miscellaneous Instructions... |
| 368 | // |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 369 | def LEAVE : I<0xC9, RawFrm, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 370 | (ops), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 371 | def POP32r : I<0x58, AddRegFrm, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 372 | (ops R32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 373 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 374 | let isTwoAddress = 1 in // R32 = bswap R32 |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 375 | def BSWAP32r : I<0xC8, AddRegFrm, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 376 | (ops R32:$dst, R32:$src), "bswap{l} $dst", []>, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 377 | |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 378 | def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 379 | (ops R8:$src1, R8:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 380 | "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 381 | def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 382 | (ops R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 383 | "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 384 | def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 385 | (ops R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 386 | "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 387 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 388 | def XCHG8mr : I<0x86, MRMDestMem, |
| 389 | (ops i8mem:$src1, R8:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 390 | "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 391 | def XCHG16mr : I<0x87, MRMDestMem, |
| 392 | (ops i16mem:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 393 | "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 394 | def XCHG32mr : I<0x87, MRMDestMem, |
| 395 | (ops i32mem:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 396 | "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 397 | def XCHG8rm : I<0x86, MRMSrcMem, |
| 398 | (ops R8:$src1, i8mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 399 | "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 400 | def XCHG16rm : I<0x87, MRMSrcMem, |
| 401 | (ops R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 402 | "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 403 | def XCHG32rm : I<0x87, MRMSrcMem, |
| 404 | (ops R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 405 | "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 406 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 407 | def LEA16r : I<0x8D, MRMSrcMem, |
| 408 | (ops R16:$dst, i32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 409 | "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 410 | def LEA32r : I<0x8D, MRMSrcMem, |
| 411 | (ops R32:$dst, i32mem:$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 412 | "lea{l} {$src|$dst}, {$dst|$src}", |
| 413 | [(set R32:$dst, leaaddr:$src)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 414 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 415 | def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 416 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 417 | def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 418 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize; |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 419 | def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 420 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 421 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 422 | def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 423 | Imp<[AL,ECX,EDI], [ECX,EDI]>, REP; |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 424 | def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 425 | Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize; |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 426 | def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 427 | Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP; |
| 428 | |
Chris Lattner | b89abef | 2004-02-14 04:45:37 +0000 | [diff] [blame] | 429 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 430 | //===----------------------------------------------------------------------===// |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 431 | // Input/Output Instructions... |
| 432 | // |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 433 | def IN8rr : I<0xEC, RawFrm, (ops), |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 434 | "in{b} {%dx, %al|%AL, %DX}", |
| 435 | [(set AL, (readport DX))]>, Imp<[DX], [AL]>; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 436 | def IN16rr : I<0xED, RawFrm, (ops), |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 437 | "in{w} {%dx, %ax|%AX, %DX}", |
| 438 | [(set AX, (readport DX))]>, Imp<[DX], [AX]>, OpSize; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 439 | def IN32rr : I<0xED, RawFrm, (ops), |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 440 | "in{l} {%dx, %eax|%EAX, %DX}", |
| 441 | [(set EAX, (readport DX))]>, Imp<[DX],[EAX]>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 442 | |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 443 | def IN8ri : Ii8<0xE4, RawFrm, (ops i16i8imm:$port), |
| 444 | "in{b} {$port, %al|%AL, $port}", |
| 445 | [(set AL, (readport i16immZExt8:$port))]>, |
| 446 | Imp<[], [AL]>; |
| 447 | def IN16ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port), |
| 448 | "in{w} {$port, %ax|%AX, $port}", |
| 449 | [(set AX, (readport i16immZExt8:$port))]>, |
| 450 | Imp<[], [AX]>, OpSize; |
| 451 | def IN32ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port), |
| 452 | "in{l} {$port, %eax|%EAX, $port}", |
| 453 | [(set EAX, (readport i16immZExt8:$port))]>, |
| 454 | Imp<[],[EAX]>; |
Chris Lattner | 440bbc2 | 2004-04-13 17:19:31 +0000 | [diff] [blame] | 455 | |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 456 | def OUT8rr : I<0xEE, RawFrm, (ops), |
| 457 | "out{b} {%al, %dx|%DX, %AL}", |
| 458 | [(writeport AL, DX)]>, Imp<[DX, AL], []>; |
| 459 | def OUT16rr : I<0xEF, RawFrm, (ops), |
| 460 | "out{w} {%ax, %dx|%DX, %AX}", |
| 461 | [(writeport AX, DX)]>, Imp<[DX, AX], []>, OpSize; |
| 462 | def OUT32rr : I<0xEF, RawFrm, (ops), |
| 463 | "out{l} {%eax, %dx|%DX, %EAX}", |
| 464 | [(writeport EAX, DX)]>, Imp<[DX, EAX], []>; |
Chris Lattner | ffff708 | 2004-08-01 07:44:35 +0000 | [diff] [blame] | 465 | |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 466 | def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port), |
| 467 | "out{b} {%al, $port|$port, %AL}", |
Evan Cheng | 5a38e02 | 2005-12-13 00:25:07 +0000 | [diff] [blame] | 468 | [(writeport AL, i16immZExt8:$port)]>, |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 469 | Imp<[AL], []>; |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 470 | def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port), |
| 471 | "out{w} {%ax, $port|$port, %AX}", |
Evan Cheng | 5a38e02 | 2005-12-13 00:25:07 +0000 | [diff] [blame] | 472 | [(writeport AX, i16immZExt8:$port)]>, |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 473 | Imp<[AX], []>, OpSize; |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 474 | def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port), |
| 475 | "out{l} {%eax, $port|$port, %EAX}", |
Evan Cheng | 5a38e02 | 2005-12-13 00:25:07 +0000 | [diff] [blame] | 476 | [(writeport EAX, i16immZExt8:$port)]>, |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 477 | Imp<[EAX], []>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 478 | |
| 479 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 480 | // Move Instructions... |
| 481 | // |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 482 | def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 483 | "mov{b} {$src, $dst|$dst, $src}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 484 | def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 485 | "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 486 | def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 487 | "mov{l} {$src, $dst|$dst, $src}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 488 | def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 489 | "mov{b} {$src, $dst|$dst, $src}", |
| 490 | [(set R8:$dst, imm:$src)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 491 | def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 492 | "mov{w} {$src, $dst|$dst, $src}", |
| 493 | [(set R16:$dst, imm:$src)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 494 | def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 495 | "mov{l} {$src, $dst|$dst, $src}", |
| 496 | [(set R32:$dst, imm:$src)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 497 | def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 498 | "mov{b} {$src, $dst|$dst, $src}", |
| 499 | [(store (i8 imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 500 | def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 501 | "mov{w} {$src, $dst|$dst, $src}", |
| 502 | [(store (i16 imm:$src), addr:$dst)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 503 | def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 504 | "mov{l} {$src, $dst|$dst, $src}", |
| 505 | [(store (i32 imm:$src), addr:$dst)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 506 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 507 | def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 508 | "mov{b} {$src, $dst|$dst, $src}", |
| 509 | [(set R8:$dst, (load addr:$src))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 510 | def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 511 | "mov{w} {$src, $dst|$dst, $src}", |
| 512 | [(set R16:$dst, (load addr:$src))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 513 | def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 514 | "mov{l} {$src, $dst|$dst, $src}", |
| 515 | [(set R32:$dst, (load addr:$src))]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 516 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 517 | def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 518 | "mov{b} {$src, $dst|$dst, $src}", |
| 519 | [(store R8:$src, addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 520 | def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 521 | "mov{w} {$src, $dst|$dst, $src}", |
| 522 | [(store R16:$src, addr:$dst)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 523 | def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 524 | "mov{l} {$src, $dst|$dst, $src}", |
| 525 | [(store R32:$src, addr:$dst)]>; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 526 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 527 | //===----------------------------------------------------------------------===// |
| 528 | // Fixed-Register Multiplication and Division Instructions... |
| 529 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 530 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 531 | // Extra precision multiplication |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 532 | def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 533 | Imp<[AL],[AX]>; // AL,AH = AL*R8 |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 534 | def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 535 | Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 536 | def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 537 | Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 538 | def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 539 | "mul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 540 | def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 541 | "mul{w} $src", []>, Imp<[AX],[AX,DX]>, |
| 542 | OpSize; // AX,DX = AX*[mem16] |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 543 | def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 544 | "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32] |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 545 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 546 | def IMUL8r : I<0xF6, MRM5r, (ops R8:$src), "imul{b} $src", []>, |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 547 | Imp<[AL],[AX]>; // AL,AH = AL*R8 |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 548 | def IMUL16r : I<0xF7, MRM5r, (ops R16:$src), "imul{w} $src", []>, |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 549 | Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 550 | def IMUL32r : I<0xF7, MRM5r, (ops R32:$src), "imul{l} $src", []>, |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 551 | Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 |
| 552 | def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 553 | "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 554 | def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 555 | "imul{w} $src", []>, Imp<[AX],[AX,DX]>, |
| 556 | OpSize; // AX,DX = AX*[mem16] |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 557 | def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 558 | "imul{l} $src", []>, |
| 559 | Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 560 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 561 | // unsigned division/remainder |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 562 | def DIV8r : I<0xF6, MRM6r, (ops R8:$src), // AX/r8 = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 563 | "div{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 564 | def DIV16r : I<0xF7, MRM6r, (ops R16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 565 | "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 566 | def DIV32r : I<0xF7, MRM6r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 567 | "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 568 | def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 569 | "div{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 570 | def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 571 | "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 572 | def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 573 | "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 574 | |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 575 | // Signed division/remainder. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 576 | def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), // AX/r8 = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 577 | "idiv{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 578 | def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 579 | "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 580 | def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 581 | "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 582 | def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 583 | "idiv{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 584 | def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 585 | "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 586 | def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 587 | "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 588 | |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 589 | // Sign-extenders for division. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 590 | def CBW : I<0x98, RawFrm, (ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 591 | "{cbtw|cbw}", []>, Imp<[AL],[AH]>; // AX = signext(AL) |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 592 | def CWD : I<0x99, RawFrm, (ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 593 | "{cwtd|cwd}", []>, Imp<[AX],[DX]>; // DX:AX = signext(AX) |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 594 | def CDQ : I<0x99, RawFrm, (ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 595 | "{cltd|cdq}", []>, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX) |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 596 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 597 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 598 | //===----------------------------------------------------------------------===// |
| 599 | // Two address Instructions... |
| 600 | // |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 601 | let isTwoAddress = 1 in { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 602 | |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 603 | // Conditional moves |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 604 | def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, R16 = R16 |
| 605 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 606 | "cmovb {$src2, $dst|$dst, $src2}", |
| 607 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
| 608 | SETULT, STATUS))]>, |
| 609 | Imp<[STATUS],[]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 610 | def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, R16 = [mem16] |
| 611 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 612 | "cmovb {$src2, $dst|$dst, $src2}", |
| 613 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
| 614 | SETULT, STATUS))]>, |
| 615 | Imp<[STATUS],[]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 616 | def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, R32 = R32 |
| 617 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 618 | "cmovb {$src2, $dst|$dst, $src2}", |
| 619 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
| 620 | SETULT, STATUS))]>, |
| 621 | Imp<[STATUS],[]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 622 | def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, R32 = [mem32] |
| 623 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 624 | "cmovb {$src2, $dst|$dst, $src2}", |
| 625 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
| 626 | SETULT, STATUS))]>, |
| 627 | Imp<[STATUS],[]>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 628 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 629 | def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, R16 = R16 |
| 630 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 631 | "cmovae {$src2, $dst|$dst, $src2}", |
| 632 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
| 633 | SETUGE, STATUS))]>, |
| 634 | Imp<[STATUS],[]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 635 | def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, R16 = [mem16] |
| 636 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 637 | "cmovae {$src2, $dst|$dst, $src2}", |
| 638 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
| 639 | SETUGE, STATUS))]>, |
| 640 | Imp<[STATUS],[]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 641 | def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, R32 = R32 |
| 642 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 643 | "cmovae {$src2, $dst|$dst, $src2}", |
| 644 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
| 645 | SETUGE, STATUS))]>, |
| 646 | Imp<[STATUS],[]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 647 | def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, R32 = [mem32] |
| 648 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 649 | "cmovae {$src2, $dst|$dst, $src2}", |
| 650 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
| 651 | SETUGE, STATUS))]>, |
| 652 | Imp<[STATUS],[]>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 653 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 654 | def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, R16 = R16 |
| 655 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 656 | "cmove {$src2, $dst|$dst, $src2}", |
| 657 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
| 658 | SETEQ, STATUS))]>, |
| 659 | Imp<[STATUS],[]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 660 | def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, R16 = [mem16] |
| 661 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 662 | "cmove {$src2, $dst|$dst, $src2}", |
| 663 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
| 664 | SETEQ, STATUS))]>, |
| 665 | Imp<[STATUS],[]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 666 | def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, R32 = R32 |
| 667 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 668 | "cmove {$src2, $dst|$dst, $src2}", |
| 669 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
| 670 | SETEQ, STATUS))]>, |
| 671 | Imp<[STATUS],[]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 672 | def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, R32 = [mem32] |
| 673 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 674 | "cmove {$src2, $dst|$dst, $src2}", |
| 675 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
| 676 | SETEQ, STATUS))]>, |
| 677 | Imp<[STATUS],[]>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 678 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 679 | def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, R16 = R16 |
| 680 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 681 | "cmovne {$src2, $dst|$dst, $src2}", |
| 682 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
| 683 | SETNE, STATUS))]>, |
| 684 | Imp<[STATUS],[]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 685 | def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, R16 = [mem16] |
| 686 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 687 | "cmovne {$src2, $dst|$dst, $src2}", |
| 688 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
| 689 | SETNE, STATUS))]>, |
| 690 | Imp<[STATUS],[]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 691 | def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, R32 = R32 |
| 692 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 693 | "cmovne {$src2, $dst|$dst, $src2}", |
| 694 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
| 695 | SETNE, STATUS))]>, |
| 696 | Imp<[STATUS],[]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 697 | def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, R32 = [mem32] |
| 698 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 699 | "cmovne {$src2, $dst|$dst, $src2}", |
| 700 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
| 701 | SETNE, STATUS))]>, |
| 702 | Imp<[STATUS],[]>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 703 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 704 | def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, R16 = R16 |
| 705 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 706 | "cmovbe {$src2, $dst|$dst, $src2}", |
| 707 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
| 708 | SETULE, STATUS))]>, |
| 709 | Imp<[STATUS],[]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 710 | def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, R16 = [mem16] |
| 711 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 712 | "cmovbe {$src2, $dst|$dst, $src2}", |
| 713 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
| 714 | SETULE, STATUS))]>, |
| 715 | Imp<[STATUS],[]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 716 | def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, R32 = R32 |
| 717 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 718 | "cmovbe {$src2, $dst|$dst, $src2}", |
| 719 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
| 720 | SETULE, STATUS))]>, |
| 721 | Imp<[STATUS],[]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 722 | def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, R32 = [mem32] |
| 723 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 724 | "cmovbe {$src2, $dst|$dst, $src2}", |
| 725 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
| 726 | SETULE, STATUS))]>, |
| 727 | Imp<[STATUS],[]>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 728 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 729 | def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, R16 = R16 |
| 730 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 731 | "cmova {$src2, $dst|$dst, $src2}", |
| 732 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
| 733 | SETUGT, STATUS))]>, |
| 734 | Imp<[STATUS],[]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 735 | def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, R16 = [mem16] |
| 736 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 737 | "cmova {$src2, $dst|$dst, $src2}", |
| 738 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
| 739 | SETUGT, STATUS))]>, |
| 740 | Imp<[STATUS],[]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 741 | def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, R32 = R32 |
| 742 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 743 | "cmova {$src2, $dst|$dst, $src2}", |
| 744 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
| 745 | SETUGT, STATUS))]>, |
| 746 | Imp<[STATUS],[]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 747 | def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, R32 = [mem32] |
| 748 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 749 | "cmova {$src2, $dst|$dst, $src2}", |
| 750 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
| 751 | SETUGT, STATUS))]>, |
| 752 | Imp<[STATUS],[]>, TB; |
| 753 | |
| 754 | def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, R16 = R16 |
| 755 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 756 | "cmovl {$src2, $dst|$dst, $src2}", |
| 757 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
| 758 | SETLT, STATUS))]>, |
| 759 | Imp<[STATUS],[]>, TB, OpSize; |
| 760 | def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, R16 = [mem16] |
| 761 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 762 | "cmovl {$src2, $dst|$dst, $src2}", |
| 763 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
| 764 | SETLT, STATUS))]>, |
| 765 | Imp<[STATUS],[]>, TB, OpSize; |
| 766 | def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, R32 = R32 |
| 767 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 768 | "cmovl {$src2, $dst|$dst, $src2}", |
| 769 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
| 770 | SETLT, STATUS))]>, |
| 771 | Imp<[STATUS],[]>, TB; |
| 772 | def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, R32 = [mem32] |
| 773 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 774 | "cmovl {$src2, $dst|$dst, $src2}", |
| 775 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
| 776 | SETLT, STATUS))]>, |
| 777 | Imp<[STATUS],[]>, TB; |
| 778 | |
| 779 | def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, R16 = R16 |
| 780 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 781 | "cmovge {$src2, $dst|$dst, $src2}", |
| 782 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
| 783 | SETGE, STATUS))]>, |
| 784 | Imp<[STATUS],[]>, TB, OpSize; |
| 785 | def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, R16 = [mem16] |
| 786 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 787 | "cmovge {$src2, $dst|$dst, $src2}", |
| 788 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
| 789 | SETGE, STATUS))]>, |
| 790 | Imp<[STATUS],[]>, TB, OpSize; |
| 791 | def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, R32 = R32 |
| 792 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 793 | "cmovge {$src2, $dst|$dst, $src2}", |
| 794 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
| 795 | SETGE, STATUS))]>, |
| 796 | Imp<[STATUS],[]>, TB; |
| 797 | def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, R32 = [mem32] |
| 798 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 799 | "cmovge {$src2, $dst|$dst, $src2}", |
| 800 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
| 801 | SETGE, STATUS))]>, |
| 802 | Imp<[STATUS],[]>, TB; |
| 803 | |
| 804 | def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, R16 = R16 |
| 805 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 806 | "cmovle {$src2, $dst|$dst, $src2}", |
| 807 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
| 808 | SETLE, STATUS))]>, |
| 809 | Imp<[STATUS],[]>, TB, OpSize; |
| 810 | def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, R16 = [mem16] |
| 811 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 812 | "cmovle {$src2, $dst|$dst, $src2}", |
| 813 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
| 814 | SETLE, STATUS))]>, |
| 815 | Imp<[STATUS],[]>, TB, OpSize; |
| 816 | def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, R32 = R32 |
| 817 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 818 | "cmovle {$src2, $dst|$dst, $src2}", |
| 819 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
| 820 | SETLE, STATUS))]>, |
| 821 | Imp<[STATUS],[]>, TB; |
| 822 | def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, R32 = [mem32] |
| 823 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 824 | "cmovle {$src2, $dst|$dst, $src2}", |
| 825 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
| 826 | SETLE, STATUS))]>, |
| 827 | Imp<[STATUS],[]>, TB; |
| 828 | |
| 829 | def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, R16 = R16 |
| 830 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 831 | "cmovg {$src2, $dst|$dst, $src2}", |
| 832 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
| 833 | SETGT, STATUS))]>, |
| 834 | Imp<[STATUS],[]>, TB, OpSize; |
| 835 | def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, R16 = [mem16] |
| 836 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 837 | "cmovg {$src2, $dst|$dst, $src2}", |
| 838 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
| 839 | SETGT, STATUS))]>, |
| 840 | Imp<[STATUS],[]>, TB, OpSize; |
| 841 | def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, R32 = R32 |
| 842 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 843 | "cmovg {$src2, $dst|$dst, $src2}", |
| 844 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
| 845 | SETGT, STATUS))]>, |
| 846 | Imp<[STATUS],[]>, TB; |
| 847 | def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, R32 = [mem32] |
| 848 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 849 | "cmovg {$src2, $dst|$dst, $src2}", |
| 850 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
| 851 | SETGT, STATUS))]>, |
| 852 | Imp<[STATUS],[]>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 853 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 854 | def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, R16 = R16 |
| 855 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 856 | "cmovs {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 857 | def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, R16 = [mem16] |
| 858 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 859 | "cmovs {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 860 | def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, R32 = R32 |
| 861 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 862 | "cmovs {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 863 | def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, R32 = [mem32] |
| 864 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 865 | "cmovs {$src2, $dst|$dst, $src2}", []>, TB; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 866 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 867 | def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, R16 = R16 |
| 868 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 869 | "cmovns {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 870 | def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, R16 = [mem16] |
| 871 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 872 | "cmovns {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 873 | def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, R32 = R32 |
| 874 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 875 | "cmovns {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 876 | def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, R32 = [mem32] |
| 877 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 878 | "cmovns {$src2, $dst|$dst, $src2}", []>, TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 879 | |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 880 | def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, R16 = R16 |
| 881 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 882 | "cmovp {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 883 | def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, R16 = [mem16] |
| 884 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 885 | "cmovp {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 886 | def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, R32 = R32 |
| 887 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 888 | "cmovp {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 889 | def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, R32 = [mem32] |
| 890 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 891 | "cmovp {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 892 | |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 893 | def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, R16 = R16 |
| 894 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 895 | "cmovnp {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 896 | def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, R16 = [mem16] |
| 897 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 898 | "cmovnp {$src2, $dst|$dst, $src2}", []>, TB, OpSize; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 899 | def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, R32 = R32 |
| 900 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 901 | "cmovnp {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 902 | def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, R32 = [mem32] |
| 903 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 904 | "cmovnp {$src2, $dst|$dst, $src2}", []>, TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 905 | |
| 906 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 907 | // unary instructions |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 908 | def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst", |
| 909 | [(set R8:$dst, (ineg R8:$src))]>; |
| 910 | def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst", |
| 911 | [(set R16:$dst, (ineg R16:$src))]>, OpSize; |
| 912 | def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst", |
| 913 | [(set R32:$dst, (ineg R32:$src))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 914 | let isTwoAddress = 0 in { |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 915 | def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 916 | [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 917 | def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 918 | [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 919 | def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 920 | [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>; |
| 921 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 922 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 923 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 924 | def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst", |
| 925 | [(set R8:$dst, (not R8:$src))]>; |
| 926 | def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst", |
| 927 | [(set R16:$dst, (not R16:$src))]>, OpSize; |
| 928 | def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst", |
| 929 | [(set R32:$dst, (not R32:$src))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 930 | let isTwoAddress = 0 in { |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 931 | def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 932 | [(store (not (loadi8 addr:$dst)), addr:$dst)]>; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 933 | def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 934 | [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 935 | def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 936 | [(store (not (loadi32 addr:$dst)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 937 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 938 | |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 939 | // TODO: inc/dec is slow for P4, but fast for Pentium-M. |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 940 | def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst", |
| 941 | [(set R8:$dst, (add R8:$src, 1))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 942 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 943 | def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst", |
| 944 | [(set R16:$dst, (add R16:$src, 1))]>, OpSize; |
| 945 | def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst", |
| 946 | [(set R32:$dst, (add R32:$src, 1))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 947 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 948 | let isTwoAddress = 0 in { |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 949 | def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 950 | [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 951 | def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 952 | [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, OpSize; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 953 | def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 954 | [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 955 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 956 | |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 957 | def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst", |
| 958 | [(set R8:$dst, (add R8:$src, -1))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 959 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 960 | def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst", |
| 961 | [(set R16:$dst, (add R16:$src, -1))]>, OpSize; |
| 962 | def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst", |
| 963 | [(set R32:$dst, (add R32:$src, -1))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 964 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 965 | |
| 966 | let isTwoAddress = 0 in { |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 967 | def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 968 | [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 969 | def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 970 | [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, OpSize; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 971 | def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 972 | [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 973 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 974 | |
| 975 | // Logical operators... |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 976 | let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 977 | def AND8rr : I<0x20, MRMDestReg, |
| 978 | (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 979 | "and{b} {$src2, $dst|$dst, $src2}", |
| 980 | [(set R8:$dst, (and R8:$src1, R8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 981 | def AND16rr : I<0x21, MRMDestReg, |
| 982 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 983 | "and{w} {$src2, $dst|$dst, $src2}", |
| 984 | [(set R16:$dst, (and R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 985 | def AND32rr : I<0x21, MRMDestReg, |
| 986 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 987 | "and{l} {$src2, $dst|$dst, $src2}", |
| 988 | [(set R32:$dst, (and R32:$src1, R32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 989 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 990 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 991 | def AND8rm : I<0x22, MRMSrcMem, |
| 992 | (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 993 | "and{b} {$src2, $dst|$dst, $src2}", |
| 994 | [(set R8:$dst, (and R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 995 | def AND16rm : I<0x23, MRMSrcMem, |
| 996 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 997 | "and{w} {$src2, $dst|$dst, $src2}", |
| 998 | [(set R16:$dst, (and R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 999 | def AND32rm : I<0x23, MRMSrcMem, |
| 1000 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1001 | "and{l} {$src2, $dst|$dst, $src2}", |
| 1002 | [(set R32:$dst, (and R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1003 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1004 | def AND8ri : Ii8<0x80, MRM4r, |
| 1005 | (ops R8 :$dst, R8 :$src1, i8imm :$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1006 | "and{b} {$src2, $dst|$dst, $src2}", |
| 1007 | [(set R8:$dst, (and R8:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1008 | def AND16ri : Ii16<0x81, MRM4r, |
| 1009 | (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1010 | "and{w} {$src2, $dst|$dst, $src2}", |
| 1011 | [(set R16:$dst, (and R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1012 | def AND32ri : Ii32<0x81, MRM4r, |
| 1013 | (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1014 | "and{l} {$src2, $dst|$dst, $src2}", |
| 1015 | [(set R32:$dst, (and R32:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1016 | def AND16ri8 : Ii8<0x83, MRM4r, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1017 | (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1018 | "and{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1019 | [(set R16:$dst, (and R16:$src1, i16immSExt8:$src2))]>, |
| 1020 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1021 | def AND32ri8 : Ii8<0x83, MRM4r, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1022 | (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1023 | "and{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1024 | [(set R32:$dst, (and R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1025 | |
| 1026 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1027 | def AND8mr : I<0x20, MRMDestMem, |
| 1028 | (ops i8mem :$dst, R8 :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1029 | "and{b} {$src, $dst|$dst, $src}", |
| 1030 | [(store (and (load addr:$dst), R8:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1031 | def AND16mr : I<0x21, MRMDestMem, |
| 1032 | (ops i16mem:$dst, R16:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1033 | "and{w} {$src, $dst|$dst, $src}", |
| 1034 | [(store (and (load addr:$dst), R16:$src), addr:$dst)]>, |
| 1035 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1036 | def AND32mr : I<0x21, MRMDestMem, |
| 1037 | (ops i32mem:$dst, R32:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1038 | "and{l} {$src, $dst|$dst, $src}", |
| 1039 | [(store (and (load addr:$dst), R32:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1040 | def AND8mi : Ii8<0x80, MRM4m, |
| 1041 | (ops i8mem :$dst, i8imm :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1042 | "and{b} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1043 | [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1044 | def AND16mi : Ii16<0x81, MRM4m, |
| 1045 | (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1046 | "and{w} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1047 | [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1048 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1049 | def AND32mi : Ii32<0x81, MRM4m, |
| 1050 | (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1051 | "and{l} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1052 | [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1053 | def AND16mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1054 | (ops i16mem:$dst, i16i8imm :$src), |
| 1055 | "and{w} {$src, $dst|$dst, $src}", |
| 1056 | [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 1057 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1058 | def AND32mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1059 | (ops i32mem:$dst, i32i8imm :$src), |
| 1060 | "and{l} {$src, $dst|$dst, $src}", |
| 1061 | [(store (add (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1062 | } |
| 1063 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1064 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1065 | let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1066 | def OR8rr : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1067 | "or{b} {$src2, $dst|$dst, $src2}", |
| 1068 | [(set R8:$dst, (or R8:$src1, R8:$src2))]>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1069 | def OR16rr : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1070 | "or{w} {$src2, $dst|$dst, $src2}", |
| 1071 | [(set R16:$dst, (or R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1072 | def OR32rr : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1073 | "or{l} {$src2, $dst|$dst, $src2}", |
| 1074 | [(set R32:$dst, (or R32:$src1, R32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1075 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1076 | def OR8rm : I<0x0A, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1077 | "or{b} {$src2, $dst|$dst, $src2}", |
| 1078 | [(set R8:$dst, (or R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1079 | def OR16rm : I<0x0B, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1080 | "or{w} {$src2, $dst|$dst, $src2}", |
| 1081 | [(set R16:$dst, (or R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1082 | def OR32rm : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1083 | "or{l} {$src2, $dst|$dst, $src2}", |
| 1084 | [(set R32:$dst, (or R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1085 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1086 | def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1087 | "or{b} {$src2, $dst|$dst, $src2}", |
| 1088 | [(set R8:$dst, (or R8:$src1, imm:$src2))]>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1089 | def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1090 | "or{w} {$src2, $dst|$dst, $src2}", |
| 1091 | [(set R16:$dst, (or R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1092 | def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1093 | "or{l} {$src2, $dst|$dst, $src2}", |
| 1094 | [(set R32:$dst, (or R32:$src1, imm:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1095 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1096 | def OR16ri8 : Ii8<0x83, MRM1r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1097 | "or{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1098 | [(set R16:$dst, (or R16:$src1, i16immSExt8:$src2))]>, OpSize; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1099 | def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1100 | "or{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1101 | [(set R32:$dst, (or R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1102 | let isTwoAddress = 0 in { |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1103 | def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1104 | "or{b} {$src, $dst|$dst, $src}", |
| 1105 | [(store (or (load addr:$dst), R8:$src), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1106 | def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, R16:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1107 | "or{w} {$src, $dst|$dst, $src}", |
| 1108 | [(store (or (load addr:$dst), R16:$src), addr:$dst)]>, OpSize; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1109 | def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, R32:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1110 | "or{l} {$src, $dst|$dst, $src}", |
| 1111 | [(store (or (load addr:$dst), R32:$src), addr:$dst)]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1112 | def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1113 | "or{b} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1114 | [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1115 | def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1116 | "or{w} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1117 | [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1118 | OpSize; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1119 | def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1120 | "or{l} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1121 | [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1122 | def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i16i8imm:$src), |
| 1123 | "or{w} {$src, $dst|$dst, $src}", |
| 1124 | [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 1125 | OpSize; |
| 1126 | def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i32i8imm:$src), |
| 1127 | "or{l} {$src, $dst|$dst, $src}", |
| 1128 | [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1129 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1130 | |
| 1131 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1132 | let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1133 | def XOR8rr : I<0x30, MRMDestReg, |
| 1134 | (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1135 | "xor{b} {$src2, $dst|$dst, $src2}", |
| 1136 | [(set R8:$dst, (xor R8:$src1, R8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1137 | def XOR16rr : I<0x31, MRMDestReg, |
| 1138 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1139 | "xor{w} {$src2, $dst|$dst, $src2}", |
| 1140 | [(set R16:$dst, (xor R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1141 | def XOR32rr : I<0x31, MRMDestReg, |
| 1142 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1143 | "xor{l} {$src2, $dst|$dst, $src2}", |
| 1144 | [(set R32:$dst, (xor R32:$src1, R32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1145 | } |
| 1146 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1147 | def XOR8rm : I<0x32, MRMSrcMem , |
| 1148 | (ops R8 :$dst, R8:$src1, i8mem :$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1149 | "xor{b} {$src2, $dst|$dst, $src2}", |
| 1150 | [(set R8:$dst, (xor R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1151 | def XOR16rm : I<0x33, MRMSrcMem , |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1152 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 1153 | "xor{w} {$src2, $dst|$dst, $src2}", |
| 1154 | [(set R16:$dst, (xor R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1155 | def XOR32rm : I<0x33, MRMSrcMem , |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1156 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 1157 | "xor{l} {$src2, $dst|$dst, $src2}", |
| 1158 | [(set R32:$dst, (xor R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1159 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1160 | def XOR8ri : Ii8<0x80, MRM6r, |
| 1161 | (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1162 | "xor{b} {$src2, $dst|$dst, $src2}", |
| 1163 | [(set R8:$dst, (xor R8:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1164 | def XOR16ri : Ii16<0x81, MRM6r, |
| 1165 | (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1166 | "xor{w} {$src2, $dst|$dst, $src2}", |
| 1167 | [(set R16:$dst, (xor R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1168 | def XOR32ri : Ii32<0x81, MRM6r, |
| 1169 | (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1170 | "xor{l} {$src2, $dst|$dst, $src2}", |
| 1171 | [(set R32:$dst, (xor R32:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1172 | def XOR16ri8 : Ii8<0x83, MRM6r, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1173 | (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1174 | "xor{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1175 | [(set R16:$dst, (xor R16:$src1, i16immSExt8:$src2))]>, |
| 1176 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1177 | def XOR32ri8 : Ii8<0x83, MRM6r, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1178 | (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1179 | "xor{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1180 | [(set R32:$dst, (xor R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1181 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1182 | def XOR8mr : I<0x30, MRMDestMem, |
| 1183 | (ops i8mem :$dst, R8 :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1184 | "xor{b} {$src, $dst|$dst, $src}", |
| 1185 | [(store (xor (load addr:$dst), R8:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1186 | def XOR16mr : I<0x31, MRMDestMem, |
| 1187 | (ops i16mem:$dst, R16:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1188 | "xor{w} {$src, $dst|$dst, $src}", |
| 1189 | [(store (xor (load addr:$dst), R16:$src), addr:$dst)]>, |
| 1190 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1191 | def XOR32mr : I<0x31, MRMDestMem, |
| 1192 | (ops i32mem:$dst, R32:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1193 | "xor{l} {$src, $dst|$dst, $src}", |
| 1194 | [(store (xor (load addr:$dst), R32:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1195 | def XOR8mi : Ii8<0x80, MRM6m, |
| 1196 | (ops i8mem :$dst, i8imm :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1197 | "xor{b} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1198 | [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1199 | def XOR16mi : Ii16<0x81, MRM6m, |
| 1200 | (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1201 | "xor{w} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1202 | [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1203 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1204 | def XOR32mi : Ii32<0x81, MRM6m, |
| 1205 | (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1206 | "xor{l} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1207 | [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1208 | def XOR16mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1209 | (ops i16mem:$dst, i16i8imm :$src), |
| 1210 | "xor{w} {$src, $dst|$dst, $src}", |
| 1211 | [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 1212 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1213 | def XOR32mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1214 | (ops i32mem:$dst, i32i8imm :$src), |
| 1215 | "xor{l} {$src, $dst|$dst, $src}", |
| 1216 | [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1217 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1218 | |
| 1219 | // Shift instructions |
Alkis Evlogimenos | 13d362f | 2004-03-07 03:19:11 +0000 | [diff] [blame] | 1220 | // FIXME: provide shorter instructions when imm8 == 1 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1221 | def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1222 | "shl{b} {%cl, $dst|$dst, %CL}", |
| 1223 | [(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1224 | def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1225 | "shl{w} {%cl, $dst|$dst, %CL}", |
| 1226 | [(set R16:$dst, (shl R16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1227 | def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1228 | "shl{l} {%cl, $dst|$dst, %CL}", |
| 1229 | [(set R32:$dst, (shl R32:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1230 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1231 | def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1232 | "shl{b} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1233 | [(set R8:$dst, (shl R8:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1234 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1235 | def SHL16ri : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1236 | "shl{w} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1237 | [(set R16:$dst, (shl R16:$src1, (i8 imm:$src2)))]>, OpSize; |
| 1238 | def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1239 | "shl{l} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1240 | [(set R32:$dst, (shl R32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1241 | } |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1242 | |
| 1243 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1244 | def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1245 | "shl{b} {%cl, $dst|$dst, %CL}", |
| 1246 | [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1247 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1248 | def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1249 | "shl{w} {%cl, $dst|$dst, %CL}", |
| 1250 | [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1251 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1252 | def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1253 | "shl{l} {%cl, $dst|$dst, %CL}", |
| 1254 | [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1255 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1256 | def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1257 | "shl{b} {$src, $dst|$dst, $src}", |
| 1258 | [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1259 | def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1260 | "shl{w} {$src, $dst|$dst, $src}", |
| 1261 | [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1262 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1263 | def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1264 | "shl{l} {$src, $dst|$dst, $src}", |
| 1265 | [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1266 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1267 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1268 | def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1269 | "shr{b} {%cl, $dst|$dst, %CL}", |
| 1270 | [(set R8:$dst, (srl R8:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1271 | def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1272 | "shr{w} {%cl, $dst|$dst, %CL}", |
| 1273 | [(set R16:$dst, (srl R16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1274 | def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1275 | "shr{l} {%cl, $dst|$dst, %CL}", |
| 1276 | [(set R32:$dst, (srl R32:$src, CL))]>, Imp<[CL],[]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1277 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1278 | def SHR8ri : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1279 | "shr{b} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1280 | [(set R8:$dst, (srl R8:$src1, (i8 imm:$src2)))]>; |
| 1281 | def SHR16ri : Ii8<0xC1, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1282 | "shr{w} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1283 | [(set R16:$dst, (srl R16:$src1, (i8 imm:$src2)))]>, OpSize; |
| 1284 | def SHR32ri : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1285 | "shr{l} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1286 | [(set R32:$dst, (srl R32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1287 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1288 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1289 | def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1290 | "shr{b} {%cl, $dst|$dst, %CL}", |
| 1291 | [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1292 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1293 | def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1294 | "shr{w} {%cl, $dst|$dst, %CL}", |
| 1295 | [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1296 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1297 | def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1298 | "shr{l} {%cl, $dst|$dst, %CL}", |
| 1299 | [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1300 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1301 | def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1302 | "shr{b} {$src, $dst|$dst, $src}", |
| 1303 | [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1304 | def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1305 | "shr{w} {$src, $dst|$dst, $src}", |
| 1306 | [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1307 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1308 | def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1309 | "shr{l} {$src, $dst|$dst, $src}", |
| 1310 | [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1311 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1312 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1313 | def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1314 | "sar{b} {%cl, $dst|$dst, %CL}", |
| 1315 | [(set R8:$dst, (sra R8:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1316 | def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1317 | "sar{w} {%cl, $dst|$dst, %CL}", |
| 1318 | [(set R16:$dst, (sra R16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1319 | def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1320 | "sar{l} {%cl, $dst|$dst, %CL}", |
| 1321 | [(set R32:$dst, (sra R32:$src, CL))]>, Imp<[CL],[]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1322 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1323 | def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1324 | "sar{b} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1325 | [(set R8:$dst, (sra R8:$src1, (i8 imm:$src2)))]>; |
| 1326 | def SAR16ri : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1327 | "sar{w} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1328 | [(set R16:$dst, (sra R16:$src1, (i8 imm:$src2)))]>, |
| 1329 | OpSize; |
| 1330 | def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1331 | "sar{l} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1332 | [(set R32:$dst, (sra R32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1333 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1334 | def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1335 | "sar{b} {%cl, $dst|$dst, %CL}", |
| 1336 | [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1337 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1338 | def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1339 | "sar{w} {%cl, $dst|$dst, %CL}", |
| 1340 | [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1341 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1342 | def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1343 | "sar{l} {%cl, $dst|$dst, %CL}", |
| 1344 | [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1345 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1346 | def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1347 | "sar{b} {$src, $dst|$dst, $src}", |
| 1348 | [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1349 | def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1350 | "sar{w} {$src, $dst|$dst, $src}", |
| 1351 | [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1352 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1353 | def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1354 | "sar{l} {$src, $dst|$dst, $src}", |
| 1355 | [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1356 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1357 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1358 | // Rotate instructions |
| 1359 | // FIXME: provide shorter instructions when imm8 == 1 |
| 1360 | def ROL8rCL : I<0xD2, MRM0r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1361 | "rol{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1362 | def ROL16rCL : I<0xD3, MRM0r, (ops R16:$dst, R16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1363 | "rol{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1364 | def ROL32rCL : I<0xD3, MRM0r, (ops R32:$dst, R32:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1365 | "rol{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1366 | |
| 1367 | def ROL8ri : Ii8<0xC0, MRM0r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1368 | "rol{b} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1369 | def ROL16ri : Ii8<0xC1, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1370 | "rol{w} {$src2, $dst|$dst, $src2}", []>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1371 | def ROL32ri : Ii8<0xC1, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1372 | "rol{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1373 | |
| 1374 | let isTwoAddress = 0 in { |
| 1375 | def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1376 | "rol{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1377 | def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1378 | "rol{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1379 | def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1380 | "rol{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1381 | def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1382 | "rol{b} {$src, $dst|$dst, $src}", []>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1383 | def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1384 | "rol{w} {$src, $dst|$dst, $src}", []>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1385 | def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1386 | "rol{l} {$src, $dst|$dst, $src}", []>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1387 | } |
| 1388 | |
| 1389 | def ROR8rCL : I<0xD2, MRM1r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1390 | "ror{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1391 | def ROR16rCL : I<0xD3, MRM1r, (ops R16:$dst, R16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1392 | "ror{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1393 | def ROR32rCL : I<0xD3, MRM1r, (ops R32:$dst, R32:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1394 | "ror{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1395 | |
| 1396 | def ROR8ri : Ii8<0xC0, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1397 | "ror{b} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1398 | def ROR16ri : Ii8<0xC1, MRM1r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1399 | "ror{w} {$src2, $dst|$dst, $src2}", []>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1400 | def ROR32ri : Ii8<0xC1, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1401 | "ror{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1402 | let isTwoAddress = 0 in { |
| 1403 | def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1404 | "ror{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1405 | def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1406 | "ror{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1407 | def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1408 | "ror{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1409 | def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1410 | "ror{b} {$src, $dst|$dst, $src}", []>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1411 | def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1412 | "ror{w} {$src, $dst|$dst, $src}", []>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1413 | def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1414 | "ror{l} {$src, $dst|$dst, $src}", []>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1415 | } |
| 1416 | |
| 1417 | |
| 1418 | |
| 1419 | // Double shift instructions (generalizations of rotate) |
| 1420 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1421 | def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1422 | "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1423 | Imp<[CL],[]>, TB; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1424 | def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1425 | "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1426 | Imp<[CL],[]>, TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1427 | def SHLD16rrCL : I<0xA5, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1428 | "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1429 | Imp<[CL],[]>, TB, OpSize; |
| 1430 | def SHRD16rrCL : I<0xAD, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1431 | "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1432 | Imp<[CL],[]>, TB, OpSize; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1433 | |
| 1434 | let isCommutable = 1 in { // These instructions commute to each other. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1435 | def SHLD32rri8 : Ii8<0xA4, MRMDestReg, |
| 1436 | (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1437 | "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1438 | def SHRD32rri8 : Ii8<0xAC, MRMDestReg, |
| 1439 | (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1440 | "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1441 | def SHLD16rri8 : Ii8<0xA4, MRMDestReg, |
| 1442 | (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1443 | "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1444 | TB, OpSize; |
| 1445 | def SHRD16rri8 : Ii8<0xAC, MRMDestReg, |
| 1446 | (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1447 | "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1448 | TB, OpSize; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1449 | } |
Chris Lattner | 0e967d4 | 2004-08-01 08:13:11 +0000 | [diff] [blame] | 1450 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1451 | let isTwoAddress = 0 in { |
| 1452 | def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1453 | "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1454 | Imp<[CL],[]>, TB; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1455 | def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1456 | "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1457 | Imp<[CL],[]>, TB; |
| 1458 | def SHLD32mri8 : Ii8<0xA4, MRMDestMem, |
| 1459 | (ops i32mem:$dst, R32:$src2, i8imm:$src3), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1460 | "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, |
| 1461 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1462 | def SHRD32mri8 : Ii8<0xAC, MRMDestMem, |
| 1463 | (ops i32mem:$dst, R32:$src2, i8imm:$src3), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1464 | "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, |
| 1465 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1466 | |
| 1467 | def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1468 | "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1469 | Imp<[CL],[]>, TB, OpSize; |
| 1470 | def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1471 | "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1472 | Imp<[CL],[]>, TB, OpSize; |
| 1473 | def SHLD16mri8 : Ii8<0xA4, MRMDestMem, |
| 1474 | (ops i16mem:$dst, R16:$src2, i8imm:$src3), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1475 | "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1476 | TB, OpSize; |
| 1477 | def SHRD16mri8 : Ii8<0xAC, MRMDestMem, |
| 1478 | (ops i16mem:$dst, R16:$src2, i8imm:$src3), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1479 | "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1480 | TB, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1481 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1482 | |
| 1483 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1484 | // Arithmetic. |
| 1485 | let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1486 | def ADD8rr : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1487 | "add{b} {$src2, $dst|$dst, $src2}", |
| 1488 | [(set R8:$dst, (add R8:$src1, R8:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1489 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1490 | def ADD16rr : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1491 | "add{w} {$src2, $dst|$dst, $src2}", |
| 1492 | [(set R16:$dst, (add R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1493 | def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1494 | "add{l} {$src2, $dst|$dst, $src2}", |
| 1495 | [(set R32:$dst, (add R32:$src1, R32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1496 | } // end isConvertibleToThreeAddress |
| 1497 | } // end isCommutable |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1498 | def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
Evan Cheng | ab24ed2 | 2005-12-09 22:48:48 +0000 | [diff] [blame] | 1499 | "add{b} {$src2, $dst|$dst, $src2}", |
| 1500 | [(set R8:$dst, (add R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1501 | def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | ab24ed2 | 2005-12-09 22:48:48 +0000 | [diff] [blame] | 1502 | "add{w} {$src2, $dst|$dst, $src2}", |
| 1503 | [(set R16:$dst, (add R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1504 | def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | ab24ed2 | 2005-12-09 22:48:48 +0000 | [diff] [blame] | 1505 | "add{l} {$src2, $dst|$dst, $src2}", |
| 1506 | [(set R32:$dst, (add R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1507 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1508 | def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1509 | "add{b} {$src2, $dst|$dst, $src2}", |
| 1510 | [(set R8:$dst, (add R8:$src1, imm:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1511 | |
| 1512 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1513 | def ADD16ri : Ii16<0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1514 | "add{w} {$src2, $dst|$dst, $src2}", |
| 1515 | [(set R16:$dst, (add R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1516 | def ADD32ri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1517 | "add{l} {$src2, $dst|$dst, $src2}", |
| 1518 | [(set R32:$dst, (add R32:$src1, imm:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1519 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1520 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1521 | // FIXME: move ADD16ri8 above ADD16ri to optimize for space. |
| 1522 | def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1523 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1524 | [(set R16:$dst, (add R16:$src1, i16immSExt8:$src2))]>, |
| 1525 | OpSize; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1526 | def ADD32ri8 : Ii8<0x83, MRM0r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1527 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1528 | [(set R32:$dst, (add R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1529 | |
| 1530 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1531 | def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1532 | "add{b} {$src2, $dst|$dst, $src2}", |
| 1533 | [(store (add (load addr:$dst), R8:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1534 | def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1535 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1536 | [(store (add (load addr:$dst), R16:$src2), addr:$dst)]>, |
| 1537 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1538 | def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1539 | "add{l} {$src2, $dst|$dst, $src2}", |
| 1540 | [(store (add (load addr:$dst), R32:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1541 | def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1542 | "add{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1543 | [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1544 | def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1545 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1546 | [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1547 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1548 | def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1549 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1550 | [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1551 | def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i16i8imm :$src2), |
| 1552 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1553 | [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
| 1554 | OpSize; |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1555 | def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i32i8imm :$src2), |
| 1556 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1557 | [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1558 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1559 | |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1560 | let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1561 | def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1562 | "adc{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1563 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1564 | def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1565 | "adc{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1566 | def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1567 | "adc{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1568 | def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1569 | "adc{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1570 | |
| 1571 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1572 | def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1573 | "adc{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1574 | def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1575 | "adc{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1576 | def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i8imm :$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1577 | "adc{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1578 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1579 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1580 | def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1581 | "sub{b} {$src2, $dst|$dst, $src2}", |
| 1582 | [(set R8:$dst, (sub R8:$src1, R8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1583 | def SUB16rr : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1584 | "sub{w} {$src2, $dst|$dst, $src2}", |
| 1585 | [(set R16:$dst, (sub R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1586 | def SUB32rr : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1587 | "sub{l} {$src2, $dst|$dst, $src2}", |
| 1588 | [(set R32:$dst, (sub R32:$src1, R32:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1589 | def SUB8rm : I<0x2A, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1590 | "sub{b} {$src2, $dst|$dst, $src2}", |
| 1591 | [(set R8:$dst, (sub R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1592 | def SUB16rm : I<0x2B, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1593 | "sub{w} {$src2, $dst|$dst, $src2}", |
| 1594 | [(set R16:$dst, (sub R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1595 | def SUB32rm : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1596 | "sub{l} {$src2, $dst|$dst, $src2}", |
| 1597 | [(set R32:$dst, (sub R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1598 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1599 | def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1600 | "sub{b} {$src2, $dst|$dst, $src2}", |
| 1601 | [(set R8:$dst, (sub R8:$src1, imm:$src2))]>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1602 | def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1603 | "sub{w} {$src2, $dst|$dst, $src2}", |
| 1604 | [(set R16:$dst, (sub R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1605 | def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1606 | "sub{l} {$src2, $dst|$dst, $src2}", |
| 1607 | [(set R32:$dst, (sub R32:$src1, imm:$src2))]>; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1608 | def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1609 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1610 | [(set R16:$dst, (sub R16:$src1, i16immSExt8:$src2))]>, |
| 1611 | OpSize; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1612 | def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1613 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1614 | [(set R32:$dst, (sub R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1615 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1616 | def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1617 | "sub{b} {$src2, $dst|$dst, $src2}", |
| 1618 | [(store (sub (load addr:$dst), R8:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1619 | def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1620 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1621 | [(store (sub (load addr:$dst), R16:$src2), addr:$dst)]>, |
| 1622 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1623 | def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1624 | "sub{l} {$src2, $dst|$dst, $src2}", |
| 1625 | [(store (sub (load addr:$dst), R32:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1626 | def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1627 | "sub{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1628 | [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1629 | def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1630 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1631 | [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1632 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1633 | def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1634 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1635 | [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1636 | def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i16i8imm :$src2), |
| 1637 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1638 | [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
| 1639 | OpSize; |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1640 | def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i32i8imm :$src2), |
| 1641 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1642 | [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1643 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1644 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1645 | def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1646 | "sbb{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1647 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1648 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1649 | def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1650 | "sbb{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1651 | def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1652 | "sbb{b} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1653 | def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1654 | "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1655 | def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1656 | "sbb{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1657 | def SBB16mi8 : Ii8<0x83, MRM3m, (ops i16mem:$dst, i8imm :$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1658 | "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1659 | def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i8imm :$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1660 | "sbb{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1661 | } |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1662 | def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1663 | "sbb{b} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1664 | def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1665 | "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1666 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1667 | def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1668 | "sbb{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1669 | def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1670 | "sbb{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1671 | |
Chris Lattner | 09c750f | 2004-10-06 14:31:50 +0000 | [diff] [blame] | 1672 | def SBB16ri8 : Ii8<0x83, MRM3r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1673 | "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1674 | def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1675 | "sbb{l} {$src2, $dst|$dst, $src2}", []>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1676 | |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1677 | let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1678 | def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1679 | "imul{w} {$src2, $dst|$dst, $src2}", |
| 1680 | [(set R16:$dst, (mul R16:$src1, R16:$src2))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1681 | def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1682 | "imul{l} {$src2, $dst|$dst, $src2}", |
| 1683 | [(set R32:$dst, (mul R32:$src1, R32:$src2))]>, TB; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1684 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1685 | def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 1686 | "imul{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1687 | [(set R16:$dst, (mul R16:$src1, (load addr:$src2)))]>, |
| 1688 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1689 | def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 1690 | "imul{l} {$src2, $dst|$dst, $src2}", |
| 1691 | [(set R32:$dst, (mul R32:$src1, (load addr:$src2)))]>, TB; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1692 | |
| 1693 | } // end Two Address instructions |
| 1694 | |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1695 | // Suprisingly enough, these are not two address instructions! |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1696 | def IMUL16rri : Ii16<0x69, MRMSrcReg, // R16 = R16*I16 |
| 1697 | (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1698 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 1699 | [(set R16:$dst, (mul R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1700 | def IMUL32rri : Ii32<0x69, MRMSrcReg, // R32 = R32*I32 |
| 1701 | (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1702 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
| 1703 | [(set R32:$dst, (mul R32:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1704 | def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // R16 = R16*I8 |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1705 | (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1706 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1707 | [(set R16:$dst, (mul R16:$src1, i16immSExt8:$src2))]>, |
| 1708 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1709 | def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8 |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1710 | (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1711 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1712 | [(set R32:$dst, (mul R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1713 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1714 | def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16 |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 1715 | (ops R16:$dst, i16mem:$src1, i16imm:$src2), |
| 1716 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
| 1717 | [(set R16:$dst, (mul (load addr:$src1), imm:$src2))]>, |
| 1718 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1719 | def IMUL32rmi : Ii32<0x69, MRMSrcMem, // R32 = [mem32]*I32 |
| 1720 | (ops R32:$dst, i32mem:$src1, i32imm:$src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 1721 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
| 1722 | [(set R32:$dst, (mul (load addr:$src1), imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1723 | def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // R16 = [mem16]*I8 |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 1724 | (ops R16:$dst, i16mem:$src1, i16i8imm :$src2), |
| 1725 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1726 | [(set R16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>, |
| 1727 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1728 | def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // R32 = [mem32]*I8 |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 1729 | (ops R32:$dst, i32mem:$src1, i32i8imm: $src2), |
| 1730 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1731 | [(set R32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1732 | |
| 1733 | //===----------------------------------------------------------------------===// |
| 1734 | // Test instructions are just like AND, except they don't generate a result. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1735 | // |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1736 | let isCommutable = 1 in { // TEST X, Y --> TEST Y, X |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1737 | def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1738 | "test{b} {$src2, $src1|$src1, $src2}", |
| 1739 | [(set STATUS, (X86test R8:$src1, R8:$src2))]>, |
| 1740 | Imp<[],[STATUS]>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1741 | def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1742 | "test{w} {$src2, $src1|$src1, $src2}", |
| 1743 | [(set STATUS, (X86test R16:$src1, R16:$src2))]>, |
| 1744 | Imp<[],[STATUS]>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1745 | def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1746 | "test{l} {$src2, $src1|$src1, $src2}", |
| 1747 | [(set STATUS, (X86test R32:$src1, R32:$src2))]>, |
| 1748 | Imp<[],[STATUS]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1749 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1750 | def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, R8 :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1751 | "test{b} {$src2, $src1|$src1, $src2}", |
| 1752 | [(set STATUS, (X86test (loadi8 addr:$src1), R8:$src2))]>, |
| 1753 | Imp<[],[STATUS]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1754 | def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1755 | "test{w} {$src2, $src1|$src1, $src2}", |
| 1756 | [(set STATUS, (X86test (loadi16 addr:$src1), R16:$src2))]>, |
| 1757 | Imp<[],[STATUS]>, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1758 | def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1759 | "test{l} {$src2, $src1|$src1, $src2}", |
| 1760 | [(set STATUS, (X86test (loadi32 addr:$src1), R32:$src2))]>, |
| 1761 | Imp<[],[STATUS]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1762 | def TEST8rm : I<0x84, MRMSrcMem, (ops R8 :$src1, i8mem :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1763 | "test{b} {$src2, $src1|$src1, $src2}", |
| 1764 | [(set STATUS, (X86test R8:$src1, (loadi8 addr:$src2)))]>, |
| 1765 | Imp<[],[STATUS]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1766 | def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1767 | "test{w} {$src2, $src1|$src1, $src2}", |
| 1768 | [(set STATUS, (X86test R16:$src1, (loadi16 addr:$src2)))]>, |
| 1769 | Imp<[],[STATUS]>, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1770 | def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1771 | "test{l} {$src2, $src1|$src1, $src2}", |
| 1772 | [(set STATUS, (X86test R32:$src1, (loadi32 addr:$src2)))]>, |
| 1773 | Imp<[],[STATUS]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1774 | |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 1775 | def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8 |
| 1776 | (ops R8:$src1, i8imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1777 | "test{b} {$src2, $src1|$src1, $src2}", |
| 1778 | [(set STATUS, (X86test R8:$src1, imm:$src2))]>, |
| 1779 | Imp<[],[STATUS]>; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 1780 | def TEST16ri : Ii16<0xF7, MRM0r, // flags = R16 & imm16 |
| 1781 | (ops R16:$src1, i16imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1782 | "test{w} {$src2, $src1|$src1, $src2}", |
| 1783 | [(set STATUS, (X86test R16:$src1, imm:$src2))]>, |
| 1784 | Imp<[],[STATUS]>, OpSize; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 1785 | def TEST32ri : Ii32<0xF7, MRM0r, // flags = R32 & imm32 |
| 1786 | (ops R32:$src1, i32imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1787 | "test{l} {$src2, $src1|$src1, $src2}", |
| 1788 | [(set STATUS, (X86test R32:$src1, imm:$src2))]>, |
| 1789 | Imp<[],[STATUS]>; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 1790 | def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8 |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1791 | (ops i8mem:$src1, i8imm:$src2), |
| 1792 | "test{b} {$src2, $src1|$src1, $src2}", |
| 1793 | [(set STATUS, (X86test (loadi8 addr:$src1), imm:$src2))]>, |
| 1794 | Imp<[],[STATUS]>; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 1795 | def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16 |
| 1796 | (ops i16mem:$src1, i16imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1797 | "test{w} {$src2, $src1|$src1, $src2}", |
| 1798 | [(set STATUS, (X86test (loadi16 addr:$src1), imm:$src2))]>, |
| 1799 | Imp<[],[STATUS]>, OpSize; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 1800 | def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32 |
| 1801 | (ops i32mem:$src1, i32imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1802 | "test{l} {$src2, $src1|$src1, $src2}", |
| 1803 | [(set STATUS, (X86test (loadi32 addr:$src1), imm:$src2))]>, |
| 1804 | Imp<[],[STATUS]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1805 | |
| 1806 | |
| 1807 | // Condition code ops, incl. set if equal/not equal/... |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1808 | def SAHF : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>; // flags = AH |
| 1809 | def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1810 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1811 | def SETEr : I<0x94, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 1812 | (ops R8 :$dst), |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 1813 | "sete $dst", [(set R8:$dst, (X86SetCC SETEQ, STATUS))]>, |
| 1814 | TB; // R8 = == |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1815 | def SETEm : I<0x94, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 1816 | (ops i8mem:$dst), |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 1817 | "sete $dst", [(store (X86SetCC SETEQ, STATUS), addr:$dst)]>, |
| 1818 | TB; // [mem8] = == |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1819 | def SETNEr : I<0x95, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 1820 | (ops R8 :$dst), |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 1821 | "setne $dst", [(set R8:$dst, (X86SetCC SETNE, STATUS))]>, |
| 1822 | TB; // R8 = != |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1823 | def SETNEm : I<0x95, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 1824 | (ops i8mem:$dst), |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 1825 | "setne $dst", [(store (X86SetCC SETNE, STATUS), addr:$dst)]>, |
| 1826 | TB; // [mem8] = != |
| 1827 | def SETLr : I<0x9C, MRM0r, |
| 1828 | (ops R8 :$dst), |
| 1829 | "setl $dst", [(set R8:$dst, (X86SetCC SETLT, STATUS))]>, |
| 1830 | TB; // R8 = < signed |
| 1831 | def SETLm : I<0x9C, MRM0m, |
| 1832 | (ops i8mem:$dst), |
| 1833 | "setl $dst", [(store (X86SetCC SETLT, STATUS), addr:$dst)]>, |
| 1834 | TB; // [mem8] = < signed |
| 1835 | def SETGEr : I<0x9D, MRM0r, |
| 1836 | (ops R8 :$dst), |
| 1837 | "setge $dst", [(set R8:$dst, (X86SetCC SETGE, STATUS))]>, |
| 1838 | TB; // R8 = >= signed |
| 1839 | def SETGEm : I<0x9D, MRM0m, |
| 1840 | (ops i8mem:$dst), |
| 1841 | "setge $dst", [(store (X86SetCC SETGE, STATUS), addr:$dst)]>, |
| 1842 | TB; // [mem8] = >= signed |
| 1843 | def SETLEr : I<0x9E, MRM0r, |
| 1844 | (ops R8 :$dst), |
| 1845 | "setle $dst", [(set R8:$dst, (X86SetCC SETLE, STATUS))]>, |
| 1846 | TB; // R8 = <= signed |
| 1847 | def SETLEm : I<0x9E, MRM0m, |
| 1848 | (ops i8mem:$dst), |
| 1849 | "setle $dst", [(store (X86SetCC SETLE, STATUS), addr:$dst)]>, |
| 1850 | TB; // [mem8] = <= signed |
| 1851 | def SETGr : I<0x9F, MRM0r, |
| 1852 | (ops R8 :$dst), |
| 1853 | "setg $dst", [(set R8:$dst, (X86SetCC SETGT, STATUS))]>, |
| 1854 | TB; // R8 = > signed |
| 1855 | def SETGm : I<0x9F, MRM0m, |
| 1856 | (ops i8mem:$dst), |
| 1857 | "setg $dst", [(store (X86SetCC SETGT, STATUS), addr:$dst)]>, |
| 1858 | TB; // [mem8] = > signed |
| 1859 | |
| 1860 | def SETBr : I<0x92, MRM0r, |
| 1861 | (ops R8 :$dst), |
| 1862 | "setb $dst", [(set R8:$dst, (X86SetCC SETULT, STATUS))]>, |
| 1863 | TB; // R8 = < unsign |
| 1864 | def SETBm : I<0x92, MRM0m, |
| 1865 | (ops i8mem:$dst), |
| 1866 | "setb $dst", [(store (X86SetCC SETULT, STATUS), addr:$dst)]>, |
| 1867 | TB; // [mem8] = < unsign |
| 1868 | def SETAEr : I<0x93, MRM0r, |
| 1869 | (ops R8 :$dst), |
| 1870 | "setae $dst", [(set R8:$dst, (X86SetCC SETUGE, STATUS))]>, |
| 1871 | TB; // R8 = >= unsign |
| 1872 | def SETAEm : I<0x93, MRM0m, |
| 1873 | (ops i8mem:$dst), |
| 1874 | "setae $dst", [(store (X86SetCC SETUGE, STATUS), addr:$dst)]>, |
| 1875 | TB; // [mem8] = >= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1876 | def SETBEr : I<0x96, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 1877 | (ops R8 :$dst), |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 1878 | "setbe $dst", [(set R8:$dst, (X86SetCC SETULE, STATUS))]>, |
| 1879 | TB; // R8 = <= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1880 | def SETBEm : I<0x96, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 1881 | (ops i8mem:$dst), |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 1882 | "setbe $dst", [(store (X86SetCC SETULE, STATUS), addr:$dst)]>, |
| 1883 | TB; // [mem8] = <= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1884 | def SETAr : I<0x97, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 1885 | (ops R8 :$dst), |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 1886 | "seta $dst", [(set R8:$dst, (X86SetCC SETUGT, STATUS))]>, |
| 1887 | TB; // R8 = > signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1888 | def SETAm : I<0x97, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 1889 | (ops i8mem:$dst), |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 1890 | "seta $dst", [(store (X86SetCC SETUGT, STATUS), addr:$dst)]>, |
| 1891 | TB; // [mem8] = > signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1892 | def SETSr : I<0x98, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 1893 | (ops R8 :$dst), |
| 1894 | "sets $dst", []>, TB; // R8 = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1895 | def SETSm : I<0x98, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 1896 | (ops i8mem:$dst), |
| 1897 | "sets $dst", []>, TB; // [mem8] = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1898 | def SETNSr : I<0x99, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 1899 | (ops R8 :$dst), |
| 1900 | "setns $dst", []>, TB; // R8 = !<sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1901 | def SETNSm : I<0x99, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 1902 | (ops i8mem:$dst), |
| 1903 | "setns $dst", []>, TB; // [mem8] = !<sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1904 | def SETPr : I<0x9A, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 1905 | (ops R8 :$dst), |
| 1906 | "setp $dst", []>, TB; // R8 = parity |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1907 | def SETPm : I<0x9A, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 1908 | (ops i8mem:$dst), |
| 1909 | "setp $dst", []>, TB; // [mem8] = parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1910 | def SETNPr : I<0x9B, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 1911 | (ops R8 :$dst), |
| 1912 | "setnp $dst", []>, TB; // R8 = not parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1913 | def SETNPm : I<0x9B, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 1914 | (ops i8mem:$dst), |
| 1915 | "setnp $dst", []>, TB; // [mem8] = not parity |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1916 | |
| 1917 | // Integer comparisons |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1918 | def CMP8rr : I<0x38, MRMDestReg, |
| 1919 | (ops R8 :$src1, R8 :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1920 | "cmp{b} {$src2, $src1|$src1, $src2}", |
| 1921 | [(set STATUS, (X86cmp R8:$src1, R8:$src2))]>, |
| 1922 | Imp<[],[STATUS]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1923 | def CMP16rr : I<0x39, MRMDestReg, |
| 1924 | (ops R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1925 | "cmp{w} {$src2, $src1|$src1, $src2}", |
| 1926 | [(set STATUS, (X86cmp R16:$src1, R16:$src2))]>, |
| 1927 | Imp<[],[STATUS]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1928 | def CMP32rr : I<0x39, MRMDestReg, |
| 1929 | (ops R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1930 | "cmp{l} {$src2, $src1|$src1, $src2}", |
| 1931 | [(set STATUS, (X86cmp R32:$src1, R32:$src2))]>, |
| 1932 | Imp<[],[STATUS]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1933 | def CMP8mr : I<0x38, MRMDestMem, |
| 1934 | (ops i8mem :$src1, R8 :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1935 | "cmp{b} {$src2, $src1|$src1, $src2}", |
| 1936 | [(set STATUS, (X86cmp (loadi8 addr:$src1), R8:$src2))]>, |
| 1937 | Imp<[],[STATUS]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1938 | def CMP16mr : I<0x39, MRMDestMem, |
| 1939 | (ops i16mem:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1940 | "cmp{w} {$src2, $src1|$src1, $src2}", |
| 1941 | [(set STATUS, (X86cmp (loadi16 addr:$src1), R16:$src2))]>, |
| 1942 | Imp<[],[STATUS]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1943 | def CMP32mr : I<0x39, MRMDestMem, |
| 1944 | (ops i32mem:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1945 | "cmp{l} {$src2, $src1|$src1, $src2}", |
| 1946 | [(set STATUS, (X86cmp (loadi32 addr:$src1), R32:$src2))]>, |
| 1947 | Imp<[],[STATUS]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1948 | def CMP8rm : I<0x3A, MRMSrcMem, |
| 1949 | (ops R8 :$src1, i8mem :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1950 | "cmp{b} {$src2, $src1|$src1, $src2}", |
| 1951 | [(set STATUS, (X86cmp R8:$src1, (loadi8 addr:$src2)))]>, |
| 1952 | Imp<[],[STATUS]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1953 | def CMP16rm : I<0x3B, MRMSrcMem, |
| 1954 | (ops R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1955 | "cmp{w} {$src2, $src1|$src1, $src2}", |
| 1956 | [(set STATUS, (X86cmp R16:$src1, (loadi16 addr:$src2)))]>, |
| 1957 | Imp<[],[STATUS]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1958 | def CMP32rm : I<0x3B, MRMSrcMem, |
| 1959 | (ops R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1960 | "cmp{l} {$src2, $src1|$src1, $src2}", |
| 1961 | [(set STATUS, (X86cmp R32:$src1, (loadi32 addr:$src2)))]>, |
| 1962 | Imp<[],[STATUS]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1963 | def CMP8ri : Ii8<0x80, MRM7r, |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1964 | (ops R8:$src1, i8imm:$src2), |
| 1965 | "cmp{b} {$src2, $src1|$src1, $src2}", |
| 1966 | [(set STATUS, (X86cmp R8:$src1, imm:$src2))]>, |
| 1967 | Imp<[],[STATUS]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1968 | def CMP16ri : Ii16<0x81, MRM7r, |
| 1969 | (ops R16:$src1, i16imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1970 | "cmp{w} {$src2, $src1|$src1, $src2}", |
| 1971 | [(set STATUS, (X86cmp R16:$src1, imm:$src2))]>, |
| 1972 | Imp<[],[STATUS]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1973 | def CMP32ri : Ii32<0x81, MRM7r, |
| 1974 | (ops R32:$src1, i32imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1975 | "cmp{l} {$src2, $src1|$src1, $src2}", |
| 1976 | [(set STATUS, (X86cmp R32:$src1, imm:$src2))]>, |
| 1977 | Imp<[],[STATUS]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1978 | def CMP8mi : Ii8 <0x80, MRM7m, |
| 1979 | (ops i8mem :$src1, i8imm :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1980 | "cmp{b} {$src2, $src1|$src1, $src2}", |
| 1981 | [(set STATUS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>, |
| 1982 | Imp<[],[STATUS]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1983 | def CMP16mi : Ii16<0x81, MRM7m, |
| 1984 | (ops i16mem:$src1, i16imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1985 | "cmp{w} {$src2, $src1|$src1, $src2}", |
| 1986 | [(set STATUS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>, |
| 1987 | Imp<[],[STATUS]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1988 | def CMP32mi : Ii32<0x81, MRM7m, |
| 1989 | (ops i32mem:$src1, i32imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1990 | "cmp{l} {$src2, $src1|$src1, $src2}", |
| 1991 | [(set STATUS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>, |
| 1992 | Imp<[],[STATUS]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1993 | |
| 1994 | // Sign/Zero extenders |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1995 | def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1996 | "movs{bw|x} {$src, $dst|$dst, $src}", |
| 1997 | [(set R16:$dst, (sext R8:$src))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1998 | def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops R16:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 1999 | "movs{bw|x} {$src, $dst|$dst, $src}", |
| 2000 | [(set R16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2001 | def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2002 | "movs{bl|x} {$src, $dst|$dst, $src}", |
| 2003 | [(set R32:$dst, (sext R8:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2004 | def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops R32:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2005 | "movs{bl|x} {$src, $dst|$dst, $src}", |
| 2006 | [(set R32:$dst, (sextloadi32i8 addr:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2007 | def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2008 | "movs{wl|x} {$src, $dst|$dst, $src}", |
| 2009 | [(set R32:$dst, (sext R16:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2010 | def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops R32:$dst, i16mem:$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2011 | "movs{wl|x} {$src, $dst|$dst, $src}", |
| 2012 | [(set R32:$dst, (sextloadi32i16 addr:$src))]>, TB; |
Alkis Evlogimenos | a7be982 | 2004-02-17 09:14:23 +0000 | [diff] [blame] | 2013 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2014 | def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2015 | "movz{bw|x} {$src, $dst|$dst, $src}", |
| 2016 | [(set R16:$dst, (zext R8:$src))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2017 | def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops R16:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2018 | "movz{bw|x} {$src, $dst|$dst, $src}", |
| 2019 | [(set R16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2020 | def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2021 | "movz{bl|x} {$src, $dst|$dst, $src}", |
| 2022 | [(set R32:$dst, (zext R8:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2023 | def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops R32:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2024 | "movz{bl|x} {$src, $dst|$dst, $src}", |
| 2025 | [(set R32:$dst, (zextloadi32i8 addr:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2026 | def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2027 | "movz{wl|x} {$src, $dst|$dst, $src}", |
| 2028 | [(set R32:$dst, (zext R16:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2029 | def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2030 | "movz{wl|x} {$src, $dst|$dst, $src}", |
| 2031 | [(set R32:$dst, (zextloadi32i16 addr:$src))]>, TB; |
| 2032 | |
| 2033 | // Handling 1 bit zextload and sextload |
| 2034 | def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>; |
| 2035 | def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>; |
| 2036 | def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; |
| 2037 | def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2038 | |
Evan Cheng | cb17bac | 2005-12-15 19:49:23 +0000 | [diff] [blame] | 2039 | // Handling 1 bit extload |
| 2040 | def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; |
| 2041 | |
Evan Cheng | 1aabc4e | 2005-12-17 01:47:57 +0000 | [diff] [blame] | 2042 | // Modeling anyext as zext |
| 2043 | def : Pat<(i16 (anyext R8 :$src)), (MOVZX16rr8 R8 :$src)>; |
| 2044 | def : Pat<(i32 (anyext R8 :$src)), (MOVZX32rr8 R8 :$src)>; |
| 2045 | def : Pat<(i32 (anyext R16:$src)), (MOVZX32rr16 R16:$src)>; |
| 2046 | |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2047 | //===----------------------------------------------------------------------===// |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2048 | // XMM Floating point support (requires SSE / SSE2) |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2049 | //===----------------------------------------------------------------------===// |
| 2050 | |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2051 | def MOVSSrr : I<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2052 | "movss {$src, $dst|$dst, $src}", []>, |
| 2053 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2054 | def MOVSDrr : I<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2055 | "movsd {$src, $dst|$dst, $src}", []>, |
| 2056 | Requires<[HasSSE2]>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2057 | |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2058 | def MOVSSrm : I<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src), |
| 2059 | "movss {$src, $dst|$dst, $src}", |
| 2060 | [(set FR32:$dst, (loadf32 addr:$src))]>, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2061 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2062 | def MOVSSmr : I<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src), |
| 2063 | "movss {$src, $dst|$dst, $src}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2064 | [(store FR32:$src, addr:$dst)]>, |
| 2065 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2066 | def MOVSDrm : I<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src), |
| 2067 | "movsd {$src, $dst|$dst, $src}", |
| 2068 | [(set FR64:$dst, (loadf64 addr:$src))]>, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2069 | Requires<[HasSSE2]>, XD; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2070 | def MOVSDmr : I<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src), |
| 2071 | "movsd {$src, $dst|$dst, $src}", |
| 2072 | [(store FR64:$src, addr:$dst)]>, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2073 | Requires<[HasSSE2]>, XD; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2074 | |
| 2075 | def CVTTSD2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2076 | "cvttsd2si {$src, $dst|$dst, $src}", |
| 2077 | [(set R32:$dst, (fp_to_sint FR64:$src))]>, |
| 2078 | Requires<[HasSSE2]>, XD; |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 2079 | def CVTTSD2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2080 | "cvttsd2si {$src, $dst|$dst, $src}", |
| 2081 | [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>, |
| 2082 | Requires<[HasSSE2]>, XD; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2083 | def CVTTSS2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2084 | "cvttss2si {$src, $dst|$dst, $src}", |
| 2085 | [(set R32:$dst, (fp_to_sint FR32:$src))]>, |
| 2086 | Requires<[HasSSE1]>, XS; |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 2087 | def CVTTSS2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2088 | "cvttss2si {$src, $dst|$dst, $src}", |
| 2089 | [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>, |
| 2090 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2091 | def CVTSD2SSrr: I<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2092 | "cvtsd2ss {$src, $dst|$dst, $src}", |
| 2093 | [(set FR32:$dst, (fround FR64:$src))]>, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2094 | Requires<[HasSSE2]>, XS; |
| 2095 | def CVTSD2SSrm: I<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2096 | "cvtsd2ss {$src, $dst|$dst, $src}", |
| 2097 | [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2098 | Requires<[HasSSE2]>, XS; |
| 2099 | def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2100 | "cvtss2sd {$src, $dst|$dst, $src}", |
| 2101 | [(set FR64:$dst, (fextend FR32:$src))]>, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2102 | Requires<[HasSSE2]>, XD; |
| 2103 | def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2104 | "cvtss2sd {$src, $dst|$dst, $src}", |
| 2105 | [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2106 | Requires<[HasSSE2]>, XD; |
| 2107 | def CVTSI2SSrr: I<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2108 | "cvtsi2ss {$src, $dst|$dst, $src}", |
| 2109 | [(set FR32:$dst, (sint_to_fp R32:$src))]>, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2110 | Requires<[HasSSE2]>, XS; |
| 2111 | def CVTSI2SSrm: I<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2112 | "cvtsi2ss {$src, $dst|$dst, $src}", |
| 2113 | [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2114 | Requires<[HasSSE2]>, XS; |
| 2115 | def CVTSI2SDrr: I<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2116 | "cvtsi2sd {$src, $dst|$dst, $src}", |
| 2117 | [(set FR64:$dst, (sint_to_fp R32:$src))]>, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2118 | Requires<[HasSSE2]>, XD; |
| 2119 | def CVTSI2SDrm: I<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2120 | "cvtsi2sd {$src, $dst|$dst, $src}", |
| 2121 | [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2122 | Requires<[HasSSE2]>, XD; |
Nate Begeman | f63be7d | 2005-07-06 18:59:04 +0000 | [diff] [blame] | 2123 | |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2124 | def SQRTSSrm : I<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2125 | "sqrtss {$src, $dst|$dst, $src}", |
| 2126 | [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>, |
| 2127 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2128 | def SQRTSSrr : I<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2129 | "sqrtss {$src, $dst|$dst, $src}", |
| 2130 | [(set FR32:$dst, (fsqrt FR32:$src))]>, |
| 2131 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2132 | def SQRTSDrm : I<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2133 | "sqrtsd {$src, $dst|$dst, $src}", |
| 2134 | [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>, |
| 2135 | Requires<[HasSSE2]>, XD; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2136 | def SQRTSDrr : I<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2137 | "sqrtsd {$src, $dst|$dst, $src}", |
| 2138 | [(set FR64:$dst, (fsqrt FR64:$src))]>, |
| 2139 | Requires<[HasSSE2]>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2140 | |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2141 | def UCOMISDrr: I<0x2E, MRMSrcReg, (ops FR64:$dst, FR64:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2142 | "ucomisd {$src, $dst|$dst, $src}", []>, |
| 2143 | Requires<[HasSSE2]>, TB, OpSize; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2144 | def UCOMISDrm: I<0x2E, MRMSrcMem, (ops FR64:$dst, f64mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2145 | "ucomisd {$src, $dst|$dst, $src}", []>, |
| 2146 | Requires<[HasSSE2]>, TB, OpSize; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2147 | def UCOMISSrr: I<0x2E, MRMSrcReg, (ops FR32:$dst, FR32:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2148 | "ucomiss {$src, $dst|$dst, $src}", []>, |
| 2149 | Requires<[HasSSE1]>, TB; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2150 | def UCOMISSrm: I<0x2E, MRMSrcMem, (ops FR32:$dst, f32mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2151 | "ucomiss {$src, $dst|$dst, $src}", []>, |
| 2152 | Requires<[HasSSE1]>, TB; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2153 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2154 | // Pseudo-instructions that map fld0 to xorps/xorpd for sse. |
Nate Begeman | 1c73c7b | 2005-08-03 23:26:28 +0000 | [diff] [blame] | 2155 | // FIXME: remove when we can teach regalloc that xor reg, reg is ok. |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2156 | def FLD0SS : I<0x57, MRMSrcReg, (ops FR32:$dst), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2157 | "xorps $dst, $dst", []>, Requires<[HasSSE1]>, TB; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2158 | def FLD0SD : I<0x57, MRMSrcReg, (ops FR64:$dst), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2159 | "xorpd $dst, $dst", []>, Requires<[HasSSE2]>, TB, OpSize; |
Nate Begeman | 1c73c7b | 2005-08-03 23:26:28 +0000 | [diff] [blame] | 2160 | |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2161 | let isTwoAddress = 1 in { |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2162 | // SSE Scalar Arithmetic |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2163 | let isCommutable = 1 in { |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2164 | def ADDSSrr : I<0x58, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2165 | "addss {$src2, $dst|$dst, $src2}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2166 | [(set FR32:$dst, (fadd FR32:$src1, FR32:$src2))]>, |
| 2167 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2168 | def ADDSDrr : I<0x58, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2169 | "addsd {$src2, $dst|$dst, $src2}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2170 | [(set FR64:$dst, (fadd FR64:$src1, FR64:$src2))]>, |
| 2171 | Requires<[HasSSE2]>, XD; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2172 | def MULSSrr : I<0x59, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2173 | "mulss {$src2, $dst|$dst, $src2}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2174 | [(set FR32:$dst, (fmul FR32:$src1, FR32:$src2))]>, |
| 2175 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2176 | def MULSDrr : I<0x59, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2177 | "mulsd {$src2, $dst|$dst, $src2}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2178 | [(set FR64:$dst, (fmul FR64:$src1, FR64:$src2))]>, |
| 2179 | Requires<[HasSSE2]>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2180 | } |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2181 | |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2182 | def ADDSSrm : I<0x58, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2), |
| 2183 | "addss {$src2, $dst|$dst, $src2}", |
| 2184 | [(set FR32:$dst, (fadd FR32:$src1, (loadf32 addr:$src2)))]>, |
| 2185 | Requires<[HasSSE1]>, XS; |
| 2186 | def ADDSDrm : I<0x58, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2), |
| 2187 | "addsd {$src2, $dst|$dst, $src2}", |
| 2188 | [(set FR64:$dst, (fadd FR64:$src1, (loadf64 addr:$src2)))]>, |
| 2189 | Requires<[HasSSE2]>, XD; |
| 2190 | def MULSSrm : I<0x59, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2), |
| 2191 | "mulss {$src2, $dst|$dst, $src2}", |
| 2192 | [(set FR32:$dst, (fmul FR32:$src1, (loadf32 addr:$src2)))]>, |
| 2193 | Requires<[HasSSE1]>, XS; |
| 2194 | def MULSDrm : I<0x59, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2), |
| 2195 | "mulsd {$src2, $dst|$dst, $src2}", |
| 2196 | [(set FR64:$dst, (fmul FR64:$src1, (loadf64 addr:$src2)))]>, |
| 2197 | Requires<[HasSSE2]>, XD; |
| 2198 | |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2199 | def DIVSSrr : I<0x5E, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2200 | "divss {$src2, $dst|$dst, $src2}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2201 | [(set FR32:$dst, (fdiv FR32:$src1, FR32:$src2))]>, |
| 2202 | Requires<[HasSSE1]>, XS; |
| 2203 | def DIVSSrm : I<0x5E, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2), |
| 2204 | "divss {$src2, $dst|$dst, $src2}", |
| 2205 | [(set FR32:$dst, (fdiv FR32:$src1, (loadf32 addr:$src2)))]>, |
| 2206 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2207 | def DIVSDrr : I<0x5E, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2208 | "divsd {$src2, $dst|$dst, $src2}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2209 | [(set FR64:$dst, (fdiv FR64:$src1, FR64:$src2))]>, |
| 2210 | Requires<[HasSSE2]>, XD; |
| 2211 | def DIVSDrm : I<0x5E, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2), |
| 2212 | "divsd {$src2, $dst|$dst, $src2}", |
| 2213 | [(set FR64:$dst, (fdiv FR64:$src1, (loadf64 addr:$src2)))]>, |
| 2214 | Requires<[HasSSE2]>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2215 | |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2216 | def SUBSSrr : I<0x5C, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2217 | "subss {$src2, $dst|$dst, $src2}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2218 | [(set FR32:$dst, (fsub FR32:$src1, FR32:$src2))]>, |
| 2219 | Requires<[HasSSE1]>, XS; |
| 2220 | def SUBSSrm : I<0x5C, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2), |
| 2221 | "subss {$src2, $dst|$dst, $src2}", |
| 2222 | [(set FR32:$dst, (fsub FR32:$src1, (loadf32 addr:$src2)))]>, |
| 2223 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2224 | def SUBSDrr : I<0x5C, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2225 | "subsd {$src2, $dst|$dst, $src2}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2226 | [(set FR64:$dst, (fsub FR64:$src1, FR64:$src2))]>, |
| 2227 | Requires<[HasSSE2]>, XD; |
| 2228 | def SUBSDrm : I<0x5C, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2), |
| 2229 | "subsd {$src2, $dst|$dst, $src2}", |
| 2230 | [(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))]>, |
| 2231 | Requires<[HasSSE2]>, XD; |
| 2232 | |
| 2233 | // SSE Logical |
| 2234 | let isCommutable = 1 in { |
| 2235 | def ANDPSrr : I<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), |
| 2236 | "andps {$src2, $dst|$dst, $src2}", []>, |
| 2237 | Requires<[HasSSE1]>, TB; |
| 2238 | def ANDPDrr : I<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), |
| 2239 | "andpd {$src2, $dst|$dst, $src2}", []>, |
| 2240 | Requires<[HasSSE2]>, TB, OpSize; |
| 2241 | def ORPSrr : I<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), |
| 2242 | "orps {$src2, $dst|$dst, $src2}", []>, |
| 2243 | Requires<[HasSSE1]>, TB; |
| 2244 | def ORPDrr : I<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), |
| 2245 | "orpd {$src2, $dst|$dst, $src2}", []>, |
| 2246 | Requires<[HasSSE2]>, TB, OpSize; |
| 2247 | def XORPSrr : I<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), |
| 2248 | "xorps {$src2, $dst|$dst, $src2}", []>, |
| 2249 | Requires<[HasSSE1]>, TB; |
| 2250 | def XORPDrr : I<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), |
| 2251 | "xorpd {$src2, $dst|$dst, $src2}", []>, |
| 2252 | Requires<[HasSSE2]>, TB, OpSize; |
| 2253 | } |
| 2254 | def ANDNPSrr : I<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), |
| 2255 | "andnps {$src2, $dst|$dst, $src2}", []>, |
| 2256 | Requires<[HasSSE1]>, TB; |
| 2257 | def ANDNPDrr : I<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), |
| 2258 | "andnpd {$src2, $dst|$dst, $src2}", []>, |
| 2259 | Requires<[HasSSE2]>, TB, OpSize; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2260 | |
| 2261 | def CMPSSrr : I<0xC2, MRMSrcReg, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2262 | (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2263 | "cmp${cc}ss {$src, $dst|$dst, $src}", []>, |
| 2264 | Requires<[HasSSE1]>, XS; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2265 | def CMPSSrm : I<0xC2, MRMSrcMem, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2266 | (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2267 | "cmp${cc}ss {$src, $dst|$dst, $src}", []>, |
| 2268 | Requires<[HasSSE1]>, XS; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2269 | def CMPSDrr : I<0xC2, MRMSrcReg, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2270 | (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2271 | "cmp${cc}sd {$src, $dst|$dst, $src}", []>, |
| 2272 | Requires<[HasSSE1]>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2273 | def CMPSDrm : I<0xC2, MRMSrcMem, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2274 | (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2275 | "cmp${cc}sd {$src, $dst|$dst, $src}", []>, |
| 2276 | Requires<[HasSSE2]>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2277 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2278 | |
| 2279 | //===----------------------------------------------------------------------===// |
Chris Lattner | c515ad1 | 2005-12-21 07:50:26 +0000 | [diff] [blame] | 2280 | // Floating Point Stack Support |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2281 | //===----------------------------------------------------------------------===// |
| 2282 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2283 | // Floating point support. All FP Stack operations are represented with two |
| 2284 | // instructions here. The first instruction, generated by the instruction |
| 2285 | // selector, uses "RFP" registers: a traditional register file to reference |
| 2286 | // floating point values. These instructions are all psuedo instructions and |
| 2287 | // use the "Fp" prefix. The second instruction is defined with FPI, which is |
| 2288 | // the actual instruction emitted by the assembler. The FP stackifier pass |
| 2289 | // converts one to the other after register allocation occurs. |
| 2290 | // |
| 2291 | // Note that the FpI instruction should have instruction selection info (e.g. |
| 2292 | // a pattern) and the FPI instruction should have emission info (e.g. opcode |
| 2293 | // encoding and asm printing info). |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2294 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2295 | // FPI - Floating Point Instruction template. |
| 2296 | class FPI<bits<8> o, Format F, dag ops, string asm> : I<o, F, ops, asm, []> {} |
| 2297 | |
| 2298 | // FpI - Floating Point Psuedo Instruction template. |
| 2299 | class FpI<dag ops, FPFormat fp, list<dag> pattern> |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2300 | : X86Inst<0, Pseudo, NoImm, ops, "">, Requires<[FPStack]> { |
| 2301 | let FPForm = fp; let FPFormBits = FPForm.Value; |
| 2302 | let Pattern = pattern; |
| 2303 | } |
| 2304 | |
| 2305 | // FpI - Floating Point Psuedo Instruction template. |
| 2306 | // TEMPORARY: for FpGETRESULT and FpSETRESULT only. Since |
| 2307 | // they must match regardless of X86Vector. |
| 2308 | class FpPseudoI<dag ops, FPFormat fp, list<dag> pattern> |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2309 | : X86Inst<0, Pseudo, NoImm, ops, ""> { |
Chris Lattner | 9795b3a | 2004-08-11 06:50:10 +0000 | [diff] [blame] | 2310 | let FPForm = fp; let FPFormBits = FPForm.Value; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2311 | let Pattern = pattern; |
Chris Lattner | 9795b3a | 2004-08-11 06:50:10 +0000 | [diff] [blame] | 2312 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2313 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2314 | // Random Pseudo Instructions. |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2315 | def FpGETRESULT : FpPseudoI<(ops RFP:$dst), SpecialFP, // FPR = ST(0) |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2316 | []>; |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2317 | def FpSETRESULT : FpPseudoI<(ops RFP:$src), SpecialFP, |
Evan Cheng | 5bc4da4 | 2005-12-22 02:26:21 +0000 | [diff] [blame] | 2318 | [(set FLAG, (X86fpset RFP:$src))]>, |
| 2319 | Imp<[], [ST0]>; // ST(0) = FPR |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2320 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2321 | def FpMOV : FpI<(ops RFP:$dst, RFP:$src), SpecialFP, |
| 2322 | []>; // f1 = fmov f2 |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2323 | |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2324 | // Arithmetic |
| 2325 | |
| 2326 | // Add, Sub, Mul, Div. |
| 2327 | def FpADD : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP, |
| 2328 | [(set RFP:$dst, (fadd RFP:$src1, RFP:$src2))]>; |
| 2329 | def FpSUB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP, |
| 2330 | [(set RFP:$dst, (fsub RFP:$src1, RFP:$src2))]>; |
| 2331 | def FpMUL : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP, |
| 2332 | [(set RFP:$dst, (fmul RFP:$src1, RFP:$src2))]>; |
| 2333 | def FpDIV : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP, |
| 2334 | [(set RFP:$dst, (fdiv RFP:$src1, RFP:$src2))]>; |
| 2335 | |
| 2336 | class FPST0rInst<bits<8> o, string asm> |
| 2337 | : FPI<o, AddRegFrm, (ops RST:$op), asm>, D8; |
| 2338 | class FPrST0Inst<bits<8> o, string asm> |
| 2339 | : FPI<o, AddRegFrm, (ops RST:$op), asm>, DC; |
| 2340 | class FPrST0PInst<bits<8> o, string asm> |
| 2341 | : FPI<o, AddRegFrm, (ops RST:$op), asm>, DE; |
| 2342 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2343 | // Binary Ops with a memory source. |
| 2344 | def FpADD32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2345 | [(set RFP:$dst, (fadd RFP:$src1, |
| 2346 | (extloadf64f32 addr:$src2)))]>; |
| 2347 | // ST(0) = ST(0) + [mem32] |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2348 | def FpADD64m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2349 | [(set RFP:$dst, (fadd RFP:$src1, (loadf64 addr:$src2)))]>; |
| 2350 | // ST(0) = ST(0) + [mem64] |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2351 | def FpMUL32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2352 | [(set RFP:$dst, (fmul RFP:$src1, |
| 2353 | (extloadf64f32 addr:$src2)))]>; |
| 2354 | // ST(0) = ST(0) * [mem32] |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2355 | def FpMUL64m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2356 | [(set RFP:$dst, (fmul RFP:$src1, (loadf64 addr:$src2)))]>; |
| 2357 | // ST(0) = ST(0) * [mem64] |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2358 | def FpSUB32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2359 | [(set RFP:$dst, (fsub RFP:$src1, |
| 2360 | (extloadf64f32 addr:$src2)))]>; |
| 2361 | // ST(0) = ST(0) - [mem32] |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2362 | def FpSUB64m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2363 | [(set RFP:$dst, (fsub RFP:$src1, (loadf64 addr:$src2)))]>; |
| 2364 | // ST(0) = ST(0) - [mem64] |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2365 | def FpSUBR32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2366 | [(set RFP:$dst, (fadd (extloadf64f32 addr:$src2), |
| 2367 | RFP:$src1))]>; |
| 2368 | // ST(0) = [mem32] - ST(0) |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2369 | def FpSUBR64m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2370 | [(set RFP:$dst, (fsub (loadf64 addr:$src2), RFP:$src1))]>; |
| 2371 | // ST(0) = [mem64] - ST(0) |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2372 | def FpDIV32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2373 | [(set RFP:$dst, (fdiv RFP:$src1, |
| 2374 | (extloadf64f32 addr:$src2)))]>; |
| 2375 | // ST(0) = ST(0) / [mem32] |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2376 | def FpDIV64m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2377 | [(set RFP:$dst, (fdiv RFP:$src1, (loadf64 addr:$src2)))]>; |
| 2378 | // ST(0) = ST(0) / [mem64] |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2379 | def FpDIVR32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2380 | [(set RFP:$dst, (fdiv (extloadf64f32 addr:$src2), |
| 2381 | RFP:$src1))]>; |
| 2382 | // ST(0) = [mem32] / ST(0) |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2383 | def FpDIVR64m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2384 | [(set RFP:$dst, (fdiv (loadf64 addr:$src2), RFP:$src1))]>; |
| 2385 | // ST(0) = [mem64] / ST(0) |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2386 | |
| 2387 | |
| 2388 | def FADD32m : FPI<0xD8, MRM0m, (ops f32mem:$src), "fadd{s} $src">; |
| 2389 | def FADD64m : FPI<0xDC, MRM0m, (ops f64mem:$src), "fadd{l} $src">; |
| 2390 | def FMUL32m : FPI<0xD8, MRM1m, (ops f32mem:$src), "fmul{s} $src">; |
| 2391 | def FMUL64m : FPI<0xDC, MRM1m, (ops f64mem:$src), "fmul{l} $src">; |
| 2392 | def FSUB32m : FPI<0xD8, MRM4m, (ops f32mem:$src), "fsub{s} $src">; |
| 2393 | def FSUB64m : FPI<0xDC, MRM4m, (ops f64mem:$src), "fsub{l} $src">; |
| 2394 | def FSUBR32m : FPI<0xD8, MRM5m, (ops f32mem:$src), "fsubr{s} $src">; |
| 2395 | def FSUBR64m : FPI<0xDC, MRM5m, (ops f64mem:$src), "fsubr{l} $src">; |
| 2396 | def FDIV32m : FPI<0xD8, MRM6m, (ops f32mem:$src), "fdiv{s} $src">; |
| 2397 | def FDIV64m : FPI<0xDC, MRM6m, (ops f64mem:$src), "fdiv{l} $src">; |
| 2398 | def FDIVR32m : FPI<0xD8, MRM7m, (ops f32mem:$src), "fdivr{s} $src">; |
| 2399 | def FDIVR64m : FPI<0xDC, MRM7m, (ops f64mem:$src), "fdivr{l} $src">; |
| 2400 | |
| 2401 | // FIXME: Implement these when we have a dag-dag isel! |
| 2402 | //def FIADD16m : FPI<0xDE, MRM0m>; // ST(0) = ST(0) + [mem16int] |
| 2403 | //def FIADD32m : FPI<0xDA, MRM0m>; // ST(0) = ST(0) + [mem32int] |
| 2404 | //def FIMUL16m : FPI<0xDE, MRM1m>; // ST(0) = ST(0) * [mem16] |
| 2405 | //def FIMUL32m : FPI<0xDA, MRM1m>; // ST(0) = ST(0) * [mem32] |
| 2406 | //def FISUB16m : FPI<0xDE, MRM4m>; // ST(0) = ST(0) - [mem16int] |
| 2407 | //def FISUB32m : FPI<0xDA, MRM4m>; // ST(0) = ST(0) - [mem32int] |
| 2408 | //def FISUBR16m : FPI<0xDE, MRM5m>; // ST(0) = [mem16int] - ST(0) |
| 2409 | //def FISUBR32m : FPI<0xDA, MRM5m>; // ST(0) = [mem32int] - ST(0) |
| 2410 | //def FIDIV16m : FPI<0xDE, MRM6m>; // ST(0) = ST(0) / [mem16int] |
| 2411 | //def FIDIV32m : FPI<0xDA, MRM6m>; // ST(0) = ST(0) / [mem32int] |
| 2412 | //def FIDIVR16m : FPI<0xDE, MRM7m>; // ST(0) = [mem16int] / ST(0) |
| 2413 | //def FIDIVR32m : FPI<0xDA, MRM7m>; // ST(0) = [mem32int] / ST(0) |
| 2414 | |
| 2415 | |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2416 | // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion |
| 2417 | // of some of the 'reverse' forms of the fsub and fdiv instructions. As such, |
| 2418 | // we have to put some 'r's in and take them out of weird places. |
| 2419 | def FADDST0r : FPST0rInst <0xC0, "fadd $op">; |
| 2420 | def FADDrST0 : FPrST0Inst <0xC0, "fadd {%ST(0), $op|$op, %ST(0)}">; |
| 2421 | def FADDPrST0 : FPrST0PInst<0xC0, "faddp $op">; |
| 2422 | def FSUBRST0r : FPST0rInst <0xE8, "fsubr $op">; |
| 2423 | def FSUBrST0 : FPrST0Inst <0xE8, "fsub{r} {%ST(0), $op|$op, %ST(0)}">; |
| 2424 | def FSUBPrST0 : FPrST0PInst<0xE8, "fsub{r}p $op">; |
| 2425 | def FSUBST0r : FPST0rInst <0xE0, "fsub $op">; |
| 2426 | def FSUBRrST0 : FPrST0Inst <0xE0, "fsub{|r} {%ST(0), $op|$op, %ST(0)}">; |
| 2427 | def FSUBRPrST0 : FPrST0PInst<0xE0, "fsub{|r}p $op">; |
| 2428 | def FMULST0r : FPST0rInst <0xC8, "fmul $op">; |
| 2429 | def FMULrST0 : FPrST0Inst <0xC8, "fmul {%ST(0), $op|$op, %ST(0)}">; |
| 2430 | def FMULPrST0 : FPrST0PInst<0xC8, "fmulp $op">; |
| 2431 | def FDIVRST0r : FPST0rInst <0xF8, "fdivr $op">; |
| 2432 | def FDIVrST0 : FPrST0Inst <0xF8, "fdiv{r} {%ST(0), $op|$op, %ST(0)}">; |
| 2433 | def FDIVPrST0 : FPrST0PInst<0xF8, "fdiv{r}p $op">; |
| 2434 | def FDIVST0r : FPST0rInst <0xF0, "fdiv $op">; |
| 2435 | def FDIVRrST0 : FPrST0Inst <0xF0, "fdiv{|r} {%ST(0), $op|$op, %ST(0)}">; |
| 2436 | def FDIVRPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p $op">; |
| 2437 | |
| 2438 | |
| 2439 | // Unary operations. |
| 2440 | def FpCHS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW, |
| 2441 | [(set RFP:$dst, (fneg RFP:$src))]>; |
| 2442 | def FpABS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW, |
| 2443 | [(set RFP:$dst, (fabs RFP:$src))]>; |
| 2444 | def FpSQRT : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW, |
| 2445 | [(set RFP:$dst, (fsqrt RFP:$src))]>; |
| 2446 | def FpSIN : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW, |
| 2447 | [(set RFP:$dst, (fsin RFP:$src))]>; |
| 2448 | def FpCOS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW, |
| 2449 | [(set RFP:$dst, (fcos RFP:$src))]>; |
| 2450 | def FpTST : FpI<(ops RFP:$src), OneArgFP, |
| 2451 | []>; |
| 2452 | |
| 2453 | def FCHS : FPI<0xE0, RawFrm, (ops), "fchs">, D9; |
| 2454 | def FABS : FPI<0xE1, RawFrm, (ops), "fabs">, D9; |
| 2455 | def FSQRT : FPI<0xFA, RawFrm, (ops), "fsqrt">, D9; |
| 2456 | def FSIN : FPI<0xFE, RawFrm, (ops), "fsin">, D9; |
| 2457 | def FCOS : FPI<0xFF, RawFrm, (ops), "fcos">, D9; |
| 2458 | def FTST : FPI<0xE4, RawFrm, (ops), "ftst">, D9; |
| 2459 | |
| 2460 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2461 | // Floating point cmovs. |
| 2462 | let isTwoAddress = 1 in { |
| 2463 | def FpCMOVB : FpI<(ops RST:$dst, RFP:$src1, RFP:$src2), CondMovFP, []>; |
| 2464 | def FpCMOVBE : FpI<(ops RST:$dst, RFP:$src1, RFP:$src2), CondMovFP, []>; |
| 2465 | def FpCMOVE : FpI<(ops RST:$dst, RFP:$src1, RFP:$src2), CondMovFP, []>; |
| 2466 | def FpCMOVP : FpI<(ops RST:$dst, RFP:$src1, RFP:$src2), CondMovFP, []>; |
| 2467 | def FpCMOVAE : FpI<(ops RST:$dst, RFP:$src1, RFP:$src2), CondMovFP, []>; |
| 2468 | def FpCMOVA : FpI<(ops RST:$dst, RFP:$src1, RFP:$src2), CondMovFP, []>; |
| 2469 | def FpCMOVNE : FpI<(ops RST:$dst, RFP:$src1, RFP:$src2), CondMovFP, []>; |
| 2470 | def FpCMOVNP : FpI<(ops RST:$dst, RFP:$src1, RFP:$src2), CondMovFP, []>; |
| 2471 | } |
| 2472 | |
| 2473 | def FCMOVB : FPI<0xC0, AddRegFrm, (ops RST:$op), |
| 2474 | "fcmovb {$op, %ST(0)|%ST(0), $op}">, DA; |
| 2475 | def FCMOVBE : FPI<0xD0, AddRegFrm, (ops RST:$op), |
| 2476 | "fcmovbe {$op, %ST(0)|%ST(0), $op}">, DA; |
| 2477 | def FCMOVE : FPI<0xC8, AddRegFrm, (ops RST:$op), |
| 2478 | "fcmove {$op, %ST(0)|%ST(0), $op}">, DA; |
| 2479 | def FCMOVP : FPI<0xD8, AddRegFrm, (ops RST:$op), |
| 2480 | "fcmovu {$op, %ST(0)|%ST(0), $op}">, DA; |
| 2481 | def FCMOVAE : FPI<0xC0, AddRegFrm, (ops RST:$op), |
| 2482 | "fcmovae {$op, %ST(0)|%ST(0), $op}">, DB; |
| 2483 | def FCMOVA : FPI<0xD0, AddRegFrm, (ops RST:$op), |
| 2484 | "fcmova {$op, %ST(0)|%ST(0), $op}">, DB; |
| 2485 | def FCMOVNE : FPI<0xC8, AddRegFrm, (ops RST:$op), |
| 2486 | "fcmovne {$op, %ST(0)|%ST(0), $op}">, DB; |
| 2487 | def FCMOVNP : FPI<0xD8, AddRegFrm, (ops RST:$op), |
| 2488 | "fcmovnu {$op, %ST(0)|%ST(0), $op}">, DB; |
| 2489 | |
| 2490 | // Floating point loads & stores. |
| 2491 | def FpLD32m : FpI<(ops RFP:$dst, f32mem:$src), ZeroArgFP, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2492 | [(set RFP:$dst, (extloadf64f32 addr:$src))]>; |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2493 | def FpLD64m : FpI<(ops RFP:$dst, f64mem:$src), ZeroArgFP, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2494 | [(set RFP:$dst, (loadf64 addr:$src))]>; |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2495 | def FpILD16m : FpI<(ops RFP:$dst, i16mem:$src), ZeroArgFP, |
| 2496 | []>; |
| 2497 | def FpILD32m : FpI<(ops RFP:$dst, i32mem:$src), ZeroArgFP, |
| 2498 | []>; |
| 2499 | def FpILD64m : FpI<(ops RFP:$dst, i64mem:$src), ZeroArgFP, |
| 2500 | []>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 2501 | |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2502 | // Required for RET of f32 / f64 values. |
| 2503 | def : Pat<(X86fld addr:$src, f32), (FpLD32m addr:$src)>; |
| 2504 | def : Pat<(X86fld addr:$src, f64), (FpLD64m addr:$src)>; |
| 2505 | |
| 2506 | def FpST32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP, |
| 2507 | [(truncstore RFP:$src, addr:$op, f32)]>; |
| 2508 | def FpST64m : FpI<(ops f64mem:$op, RFP:$src), OneArgFP, |
| 2509 | [(store RFP:$src, addr:$op)]>; |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2510 | def FpSTP32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP, []>; |
| 2511 | def FpSTP64m : FpI<(ops f64mem:$op, RFP:$src), OneArgFP, []>; |
| 2512 | def FpIST16m : FpI<(ops i16mem:$op, RFP:$src), OneArgFP, []>; |
| 2513 | def FpIST32m : FpI<(ops i32mem:$op, RFP:$src), OneArgFP, []>; |
| 2514 | def FpIST64m : FpI<(ops i64mem:$op, RFP:$src), OneArgFP, []>; |
Alkis Evlogimenos | 978f629 | 2004-09-08 16:54:54 +0000 | [diff] [blame] | 2515 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2516 | def FLD32m : FPI<0xD9, MRM0m, (ops f32mem:$src), "fld{s} $src">; |
| 2517 | def FLD64m : FPI<0xDD, MRM0m, (ops f64mem:$src), "fld{l} $src">; |
| 2518 | def FILD16m : FPI<0xDF, MRM0m, (ops i16mem:$src), "fild{s} $src">; |
| 2519 | def FILD32m : FPI<0xDB, MRM0m, (ops i32mem:$src), "fild{l} $src">; |
| 2520 | def FILD64m : FPI<0xDF, MRM5m, (ops i64mem:$src), "fild{ll} $src">; |
| 2521 | def FST32m : FPI<0xD9, MRM2m, (ops f32mem:$dst), "fst{s} $dst">; |
| 2522 | def FST64m : FPI<0xDD, MRM2m, (ops f64mem:$dst), "fst{l} $dst">; |
| 2523 | def FSTP32m : FPI<0xD9, MRM3m, (ops f32mem:$dst), "fstp{s} $dst">; |
| 2524 | def FSTP64m : FPI<0xDD, MRM3m, (ops f64mem:$dst), "fstp{l} $dst">; |
| 2525 | def FIST16m : FPI<0xDF, MRM2m, (ops i16mem:$dst), "fist{s} $dst">; |
| 2526 | def FIST32m : FPI<0xDB, MRM2m, (ops i32mem:$dst), "fist{l} $dst">; |
| 2527 | def FISTP16m : FPI<0xDF, MRM3m, (ops i16mem:$dst), "fistp{s} $dst">; |
| 2528 | def FISTP32m : FPI<0xDB, MRM3m, (ops i32mem:$dst), "fistp{l} $dst">; |
| 2529 | def FISTP64m : FPI<0xDF, MRM7m, (ops i64mem:$dst), "fistp{ll} $dst">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2530 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2531 | // FP Stack manipulation instructions. |
| 2532 | def FLDrr : FPI<0xC0, AddRegFrm, (ops RST:$op), "fld $op">, D9; |
| 2533 | def FSTrr : FPI<0xD0, AddRegFrm, (ops RST:$op), "fst $op">, DD; |
| 2534 | def FSTPrr : FPI<0xD8, AddRegFrm, (ops RST:$op), "fstp $op">, DD; |
| 2535 | def FXCH : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9; |
Chris Lattner | 490e86f | 2004-04-11 20:24:15 +0000 | [diff] [blame] | 2536 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2537 | // Floating point constant loads. |
| 2538 | def FpLD0 : FpI<(ops RFP:$dst), ZeroArgFP, []>; |
| 2539 | def FpLD1 : FpI<(ops RFP:$dst), ZeroArgFP, []>; |
Chris Lattner | 490e86f | 2004-04-11 20:24:15 +0000 | [diff] [blame] | 2540 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2541 | def FLD0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9; |
| 2542 | def FLD1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9; |
Chris Lattner | 490e86f | 2004-04-11 20:24:15 +0000 | [diff] [blame] | 2543 | |
Chris Lattner | 1c54a85 | 2004-03-31 22:02:13 +0000 | [diff] [blame] | 2544 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2545 | // Floating point compares. |
| 2546 | def FpUCOMr : FpI<(ops RST:$lhs, RST:$rhs), CompareFP, |
| 2547 | []>; // FPSW = cmp ST(0) with ST(i) |
| 2548 | def FpUCOMIr : FpI<(ops RST:$lhs, RST:$rhs), CompareFP, |
| 2549 | []>; // CC = cmp ST(0) with ST(i) |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2550 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2551 | def FUCOMr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i) |
| 2552 | (ops RST:$reg), |
| 2553 | "fucom $reg">, DD, Imp<[ST0],[]>; |
| 2554 | def FUCOMPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop |
| 2555 | (ops RST:$reg), |
| 2556 | "fucomp $reg">, DD, Imp<[ST0],[]>; |
| 2557 | def FUCOMPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop |
| 2558 | (ops), |
| 2559 | "fucompp">, DA, Imp<[ST0],[]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2560 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2561 | def FUCOMIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i) |
| 2562 | (ops RST:$reg), |
| 2563 | "fucomi {$reg, %ST(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>; |
| 2564 | def FUCOMIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop |
| 2565 | (ops RST:$reg), |
| 2566 | "fucomip {$reg, %ST(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>; |
Chris Lattner | 0e967d4 | 2004-08-01 08:13:11 +0000 | [diff] [blame] | 2567 | |
Chris Lattner | a1b5e16 | 2004-04-12 01:38:55 +0000 | [diff] [blame] | 2568 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2569 | // Floating point flag ops. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2570 | def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2571 | (ops), "fnstsw", []>, DF, Imp<[],[AX]>; |
Chris Lattner | 96563df | 2004-08-01 06:01:00 +0000 | [diff] [blame] | 2572 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2573 | def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2574 | (ops i16mem:$dst), "fnstcw $dst", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2575 | def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2576 | (ops i16mem:$dst), "fldcw $dst", []>; |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame^] | 2577 | |
| 2578 | |
| 2579 | //===----------------------------------------------------------------------===// |
| 2580 | // Miscellaneous Instructions |
| 2581 | //===----------------------------------------------------------------------===// |
| 2582 | |
| 2583 | def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", []>, TB, Imp<[],[EAX,EDX]>; |