Blame - lib/Target/Hexagon/HexagonVLIWPacketizer.cpp - fp2-dev/platform/external/llvm

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Sirish Pande	26f61a1	2012-05-03 21:52:53 +0000	[diff] [blame]	1	//===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
				2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
				9	//
				10	// This implements a simple VLIW packetizer using DFA. The packetizer works on
				11	// machine basic blocks. For each instruction I in BB, the packetizer consults
				12	// the DFA to see if machine resources are available to execute I. If so, the
				13	// packetizer checks if I depends on any instruction J in the current packet.
				14	// If no dependency is found, I is added to current packet and machine resource
				15	// is marked as taken. If any dependency is found, a target API call is made to
				16	// prune the dependence.
				17	//
				18	//===----------------------------------------------------------------------===//
				19	#define DEBUG_TYPE "packets"
Sirish Pande	26f61a1	2012-05-03 21:52:53 +0000	[diff] [blame]	20	#include "Hexagon.h"
Chandler Carruth	d04a8d4	2012-12-03 16:50:05 +0000	[diff] [blame]	21	#include "HexagonMachineFunctionInfo.h"
Sirish Pande	26f61a1	2012-05-03 21:52:53 +0000	[diff] [blame]	22	#include "HexagonRegisterInfo.h"
				23	#include "HexagonSubtarget.h"
Chandler Carruth	d04a8d4	2012-12-03 16:50:05 +0000	[diff] [blame]	24	#include "HexagonTargetMachine.h"
				25	#include "llvm/ADT/DenseMap.h"
				26	#include "llvm/ADT/Statistic.h"
				27	#include "llvm/CodeGen/DFAPacketizer.h"
				28	#include "llvm/CodeGen/LatencyPriorityQueue.h"
				29	#include "llvm/CodeGen/MachineDominators.h"
				30	#include "llvm/CodeGen/MachineFrameInfo.h"
				31	#include "llvm/CodeGen/MachineFunctionAnalysis.h"
				32	#include "llvm/CodeGen/MachineFunctionPass.h"
				33	#include "llvm/CodeGen/MachineInstrBuilder.h"
				34	#include "llvm/CodeGen/MachineLoopInfo.h"
				35	#include "llvm/CodeGen/MachineRegisterInfo.h"
				36	#include "llvm/CodeGen/Passes.h"
				37	#include "llvm/CodeGen/ScheduleDAG.h"
				38	#include "llvm/CodeGen/ScheduleDAGInstrs.h"
				39	#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
				40	#include "llvm/CodeGen/SchedulerRegistry.h"
				41	#include "llvm/MC/MCInstrItineraries.h"
				42	#include "llvm/Support/CommandLine.h"
				43	#include "llvm/Support/Compiler.h"
				44	#include "llvm/Support/Debug.h"
				45	#include "llvm/Support/MathExtras.h"
				46	#include "llvm/Target/TargetInstrInfo.h"
				47	#include "llvm/Target/TargetMachine.h"
				48	#include "llvm/Target/TargetRegisterInfo.h"
Sirish Pande	26f61a1	2012-05-03 21:52:53 +0000	[diff] [blame]	49	#include <map>
				50
				51	using namespace llvm;
				52
				53	namespace {
				54	class HexagonPacketizer : public MachineFunctionPass {
				55
				56	public:
				57	static char ID;
				58	HexagonPacketizer() : MachineFunctionPass(ID) {}
				59
				60	void getAnalysisUsage(AnalysisUsage &AU) const {
				61	AU.setPreservesCFG();
				62	AU.addRequired<MachineDominatorTree>();
				63	AU.addPreserved<MachineDominatorTree>();
				64	AU.addRequired<MachineLoopInfo>();
				65	AU.addPreserved<MachineLoopInfo>();
				66	MachineFunctionPass::getAnalysisUsage(AU);
				67	}
				68
				69	const char *getPassName() const {
				70	return "Hexagon Packetizer";
				71	}
				72
				73	bool runOnMachineFunction(MachineFunction &Fn);
				74	};
				75	char HexagonPacketizer::ID = 0;
				76
				77	class HexagonPacketizerList : public VLIWPacketizerList {
				78
				79	private:
				80
				81	// Has the instruction been promoted to a dot-new instruction.
				82	bool PromotedToDotNew;
				83
				84	// Has the instruction been glued to allocframe.
				85	bool GlueAllocframeStore;
				86
				87	// Has the feeder instruction been glued to new value jump.
				88	bool GlueToNewValueJump;
				89
				90	// Check if there is a dependence between some instruction already in this
				91	// packet and this instruction.
				92	bool Dependence;
				93
				94	// Only check for dependence if there are resources available to
				95	// schedule this instruction.
				96	bool FoundSequentialDependence;
				97
				98	public:
				99	// Ctor.
				100	HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
				101	MachineDominatorTree &MDT);
				102
				103	// initPacketizerState - initialize some internal flags.
				104	void initPacketizerState();
				105
				106	// ignorePseudoInstruction - Ignore bundling of pseudo instructions.
				107	bool ignorePseudoInstruction(MachineInstr MI, MachineBasicBlock MBB);
				108
				109	// isSoloInstruction - return true if instruction MI can not be packetized
				110	// with any other instruction, which means that MI itself is a packet.
				111	bool isSoloInstruction(MachineInstr *MI);
				112
				113	// isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
				114	// together.
				115	bool isLegalToPacketizeTogether(SUnit SUI, SUnit SUJ);
				116
				117	// isLegalToPruneDependencies - Is it legal to prune dependece between SUI
				118	// and SUJ.
				119	bool isLegalToPruneDependencies(SUnit SUI, SUnit SUJ);
				120
				121	MachineBasicBlock::iterator addToPacket(MachineInstr *MI);
				122	private:
				123	bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
				124	bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
				125	MachineBasicBlock::iterator &MII,
				126	const TargetRegisterClass* RC);
				127	bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,
				128	unsigned DepReg,
				129	std::map <MachineInstr, SUnit> MIToSUnit,
				130	MachineBasicBlock::iterator &MII,
				131	const TargetRegisterClass* RC);
				132	bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,
				133	unsigned DepReg,
				134	std::map <MachineInstr, SUnit> MIToSUnit,
				135	MachineBasicBlock::iterator &MII);
				136	bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,
				137	unsigned DepReg,
				138	std::map <MachineInstr, SUnit> MIToSUnit);
				139	bool DemoteToDotOld(MachineInstr* MI);
				140	bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,
				141	std::map <MachineInstr, SUnit> MIToSUnit);
				142	bool RestrictingDepExistInPacket(MachineInstr*,
				143	unsigned, std::map <MachineInstr, SUnit>);
				144	bool isNewifiable(MachineInstr* MI);
				145	bool isCondInst(MachineInstr* MI);
				146	bool IsNewifyStore (MachineInstr* MI);
				147	bool tryAllocateResourcesForConstExt(MachineInstr* MI);
				148	bool canReserveResourcesForConstExt(MachineInstr *MI);
				149	void reserveResourcesForConstExt(MachineInstr* MI);
				150	bool isNewValueInst(MachineInstr* MI);
				151	bool isDotNewInst(MachineInstr* MI);
				152	};
				153	}
				154
				155	// HexagonPacketizerList Ctor.
				156	HexagonPacketizerList::HexagonPacketizerList(
				157	MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT)
				158	: VLIWPacketizerList(MF, MLI, MDT, true){
				159	}
				160
				161	bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
				162	const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
				163	MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
				164	MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
				165
				166	// Instantiate the packetizer.
				167	HexagonPacketizerList Packetizer(Fn, MLI, MDT);
				168
				169	// DFA state table should not be empty.
				170	assert(Packetizer.getResourceTracker() && "Empty DFA table!");
				171
				172	//
				173	// Loop over all basic blocks and remove KILL pseudo-instructions
				174	// These instructions confuse the dependence analysis. Consider:
				175	// D0 = ... (Insn 0)
				176	// R0 = KILL R0, D0 (Insn 1)
				177	// R0 = ... (Insn 2)
				178	// Here, Insn 1 will result in the dependence graph not emitting an output
				179	// dependence between Insn 0 and Insn 2. This can lead to incorrect
				180	// packetization
				181	//
				182	for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
				183	MBB != MBBe; ++MBB) {
				184	MachineBasicBlock::iterator End = MBB->end();
				185	MachineBasicBlock::iterator MI = MBB->begin();
				186	while (MI != End) {
				187	if (MI->isKill()) {
				188	MachineBasicBlock::iterator DeleteMI = MI;
				189	++MI;
				190	MBB->erase(DeleteMI);
				191	End = MBB->end();
				192	continue;
				193	}
				194	++MI;
				195	}
				196	}
				197
				198	// Loop over all of the basic blocks.
				199	for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
				200	MBB != MBBe; ++MBB) {
				201	// Find scheduling regions and schedule / packetize each region.
				202	unsigned RemainingCount = MBB->size();
				203	for(MachineBasicBlock::iterator RegionEnd = MBB->end();
				204	RegionEnd != MBB->begin();) {
				205	// The next region starts above the previous region. Look backward in the
				206	// instruction stream until we find the nearest boundary.
				207	MachineBasicBlock::iterator I = RegionEnd;
				208	for(;I != MBB->begin(); --I, --RemainingCount) {
				209	if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
				210	break;
				211	}
				212	I = MBB->begin();
				213
				214	// Skip empty scheduling regions.
				215	if (I == RegionEnd) {
				216	RegionEnd = llvm::prior(RegionEnd);
				217	--RemainingCount;
				218	continue;
				219	}
				220	// Skip regions with one instruction.
				221	if (I == llvm::prior(RegionEnd)) {
				222	RegionEnd = llvm::prior(RegionEnd);
				223	continue;
				224	}
				225
				226	Packetizer.PacketizeMIs(MBB, I, RegionEnd);
				227	RegionEnd = I;
				228	}
				229	}
				230
				231	return true;
				232	}
				233
				234
				235	static bool IsIndirectCall(MachineInstr* MI) {
				236	return ((MI->getOpcode() == Hexagon::CALLR) \|\|
				237	(MI->getOpcode() == Hexagon::CALLRv3));
				238	}
				239
				240	// Reserve resources for constant extender. Trigure an assertion if
				241	// reservation fail.
				242	void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
				243	const HexagonInstrInfo QII = (const HexagonInstrInfo ) TII;
Jyotsna Verma	39498d1	2012-12-20 06:45:39 +0000	[diff] [blame^]	244	MachineFunction *MF = MI->getParent()->getParent();
				245	MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
				246	MI->getDebugLoc());
Sirish Pande	26f61a1	2012-05-03 21:52:53 +0000	[diff] [blame]	247
				248	if (ResourceTracker->canReserveResources(PseudoMI)) {
				249	ResourceTracker->reserveResources(PseudoMI);
				250	MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
				251	} else {
				252	MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
				253	llvm_unreachable("can not reserve resources for constant extender.");
				254	}
				255	return;
				256	}
				257
				258	bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
				259	const HexagonInstrInfo QII = (const HexagonInstrInfo ) TII;
Brendon Cahoon	5262abb	2012-05-14 19:35:42 +0000	[diff] [blame]	260	assert(QII->isExtended(MI) &&
Sirish Pande	26f61a1	2012-05-03 21:52:53 +0000	[diff] [blame]	261	"Should only be called for constant extended instructions");
				262	MachineFunction *MF = MI->getParent()->getParent();
Jyotsna Verma	39498d1	2012-12-20 06:45:39 +0000	[diff] [blame^]	263	MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
Sirish Pande	26f61a1	2012-05-03 21:52:53 +0000	[diff] [blame]	264	MI->getDebugLoc());
				265	bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
				266	MF->DeleteMachineInstr(PseudoMI);
				267	return CanReserve;
				268	}
				269
				270	// Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return
				271	// true, otherwise, return false.
				272	bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
				273	const HexagonInstrInfo QII = (const HexagonInstrInfo ) TII;
Jyotsna Verma	39498d1	2012-12-20 06:45:39 +0000	[diff] [blame^]	274	MachineFunction *MF = MI->getParent()->getParent();
				275	MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
				276	MI->getDebugLoc());
Sirish Pande	26f61a1	2012-05-03 21:52:53 +0000	[diff] [blame]	277
				278	if (ResourceTracker->canReserveResources(PseudoMI)) {
				279	ResourceTracker->reserveResources(PseudoMI);
				280	MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
				281	return true;
				282	} else {
				283	MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
				284	return false;
				285	}
				286	}
				287
				288
				289	bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
				290	SDep::Kind DepType,
				291	unsigned DepReg) {
				292
				293	const HexagonInstrInfo QII = (const HexagonInstrInfo ) TII;
				294	const HexagonRegisterInfo* QRI =
				295	(const HexagonRegisterInfo *) TM.getRegisterInfo();
				296
				297	// Check for lr dependence
				298	if (DepReg == QRI->getRARegister()) {
				299	return true;
				300	}
				301
				302	if (QII->isDeallocRet(MI)) {
				303	if (DepReg == QRI->getFrameRegister() \|\|
				304	DepReg == QRI->getStackRegister())
				305	return true;
				306	}
				307
				308	// Check if this is a predicate dependence
				309	const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
				310	if (RC == &Hexagon::PredRegsRegClass) {
				311	return true;
				312	}
				313
				314	//
				315	// Lastly check for an operand used in an indirect call
				316	// If we had an attribute for checking if an instruction is an indirect call,
				317	// then we could have avoided this relatively brittle implementation of
				318	// IsIndirectCall()
				319	//
				320	// Assumes that the first operand of the CALLr is the function address
				321	//
				322	if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
				323	MachineOperand MO = MI->getOperand(0);
				324	if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
				325	return true;
				326	}
				327	}
				328
				329	return false;
				330	}
				331
				332	static bool IsRegDependence(const SDep::Kind DepType) {
				333	return (DepType == SDep::Data \|\| DepType == SDep::Anti \|\|
				334	DepType == SDep::Output);
				335	}
				336
				337	static bool IsDirectJump(MachineInstr* MI) {
				338	return (MI->getOpcode() == Hexagon::JMP);
				339	}
				340
				341	static bool IsSchedBarrier(MachineInstr* MI) {
				342	switch (MI->getOpcode()) {
				343	case Hexagon::BARRIER:
				344	return true;
				345	}
				346	return false;
				347	}
				348
				349	static bool IsControlFlow(MachineInstr* MI) {
				350	return (MI->getDesc().isTerminator() \|\| MI->getDesc().isCall());
				351	}
				352
				353	bool HexagonPacketizerList::isNewValueInst(MachineInstr* MI) {
				354	const HexagonInstrInfo QII = (const HexagonInstrInfo ) TII;
				355	if (QII->isNewValueJump(MI))
				356	return true;
				357
				358	if (QII->isNewValueStore(MI))
				359	return true;
				360
				361	return false;
				362	}
				363
				364	// Function returns true if an instruction can be promoted to the new-value
				365	// store. It will always return false for v2 and v3.
				366	// It lists all the conditional and unconditional stores that can be promoted
				367	// to the new-value stores.
				368
				369	bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
				370	const HexagonRegisterInfo* QRI =
				371	(const HexagonRegisterInfo *) TM.getRegisterInfo();
				372	switch (MI->getOpcode())
				373	{
				374	// store byte
				375	case Hexagon::STrib:
				376	case Hexagon::STrib_indexed:
				377	case Hexagon::STrib_indexed_shl_V4:
				378	case Hexagon::STrib_shl_V4:
				379	case Hexagon::STrib_GP_V4:
				380	case Hexagon::STb_GP_V4:
				381	case Hexagon::POST_STbri:
				382	case Hexagon::STrib_cPt:
				383	case Hexagon::STrib_cdnPt_V4:
				384	case Hexagon::STrib_cNotPt:
				385	case Hexagon::STrib_cdnNotPt_V4:
				386	case Hexagon::STrib_indexed_cPt:
				387	case Hexagon::STrib_indexed_cdnPt_V4:
				388	case Hexagon::STrib_indexed_cNotPt:
				389	case Hexagon::STrib_indexed_cdnNotPt_V4:
				390	case Hexagon::STrib_indexed_shl_cPt_V4:
				391	case Hexagon::STrib_indexed_shl_cdnPt_V4:
				392	case Hexagon::STrib_indexed_shl_cNotPt_V4:
				393	case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
				394	case Hexagon::POST_STbri_cPt:
				395	case Hexagon::POST_STbri_cdnPt_V4:
				396	case Hexagon::POST_STbri_cNotPt:
				397	case Hexagon::POST_STbri_cdnNotPt_V4:
				398	case Hexagon::STb_GP_cPt_V4:
				399	case Hexagon::STb_GP_cNotPt_V4:
				400	case Hexagon::STb_GP_cdnPt_V4:
				401	case Hexagon::STb_GP_cdnNotPt_V4:
				402	case Hexagon::STrib_GP_cPt_V4:
				403	case Hexagon::STrib_GP_cNotPt_V4:
				404	case Hexagon::STrib_GP_cdnPt_V4:
				405	case Hexagon::STrib_GP_cdnNotPt_V4:
				406
				407	// store halfword
				408	case Hexagon::STrih:
				409	case Hexagon::STrih_indexed:
				410	case Hexagon::STrih_indexed_shl_V4:
				411	case Hexagon::STrih_shl_V4:
				412	case Hexagon::STrih_GP_V4:
				413	case Hexagon::STh_GP_V4:
				414	case Hexagon::POST_SThri:
				415	case Hexagon::STrih_cPt:
				416	case Hexagon::STrih_cdnPt_V4:
				417	case Hexagon::STrih_cNotPt:
				418	case Hexagon::STrih_cdnNotPt_V4:
				419	case Hexagon::STrih_indexed_cPt:
				420	case Hexagon::STrih_indexed_cdnPt_V4:
				421	case Hexagon::STrih_indexed_cNotPt:
				422	case Hexagon::STrih_indexed_cdnNotPt_V4:
				423	case Hexagon::STrih_indexed_shl_cPt_V4:
				424	case Hexagon::STrih_indexed_shl_cdnPt_V4:
				425	case Hexagon::STrih_indexed_shl_cNotPt_V4:
				426	case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
				427	case Hexagon::POST_SThri_cPt:
				428	case Hexagon::POST_SThri_cdnPt_V4:
				429	case Hexagon::POST_SThri_cNotPt:
				430	case Hexagon::POST_SThri_cdnNotPt_V4:
				431	case Hexagon::STh_GP_cPt_V4:
				432	case Hexagon::STh_GP_cNotPt_V4:
				433	case Hexagon::STh_GP_cdnPt_V4:
				434	case Hexagon::STh_GP_cdnNotPt_V4:
				435	case Hexagon::STrih_GP_cPt_V4:
				436	case Hexagon::STrih_GP_cNotPt_V4:
				437	case Hexagon::STrih_GP_cdnPt_V4:
				438	case Hexagon::STrih_GP_cdnNotPt_V4:
				439
				440	// store word
				441	case Hexagon::STriw:
				442	case Hexagon::STriw_indexed:
				443	case Hexagon::STriw_indexed_shl_V4:
				444	case Hexagon::STriw_shl_V4:
				445	case Hexagon::STriw_GP_V4:
				446	case Hexagon::STw_GP_V4:
				447	case Hexagon::POST_STwri:
				448	case Hexagon::STriw_cPt:
				449	case Hexagon::STriw_cdnPt_V4:
				450	case Hexagon::STriw_cNotPt:
				451	case Hexagon::STriw_cdnNotPt_V4:
				452	case Hexagon::STriw_indexed_cPt:
				453	case Hexagon::STriw_indexed_cdnPt_V4:
				454	case Hexagon::STriw_indexed_cNotPt:
				455	case Hexagon::STriw_indexed_cdnNotPt_V4:
				456	case Hexagon::STriw_indexed_shl_cPt_V4:
				457	case Hexagon::STriw_indexed_shl_cdnPt_V4:
				458	case Hexagon::STriw_indexed_shl_cNotPt_V4:
				459	case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
				460	case Hexagon::POST_STwri_cPt:
				461	case Hexagon::POST_STwri_cdnPt_V4:
				462	case Hexagon::POST_STwri_cNotPt:
				463	case Hexagon::POST_STwri_cdnNotPt_V4:
				464	case Hexagon::STw_GP_cPt_V4:
				465	case Hexagon::STw_GP_cNotPt_V4:
				466	case Hexagon::STw_GP_cdnPt_V4:
				467	case Hexagon::STw_GP_cdnNotPt_V4:
				468	case Hexagon::STriw_GP_cPt_V4:
				469	case Hexagon::STriw_GP_cNotPt_V4:
				470	case Hexagon::STriw_GP_cdnPt_V4:
				471	case Hexagon::STriw_GP_cdnNotPt_V4:
				472	return QRI->Subtarget.hasV4TOps();
				473	}
				474	return false;
				475	}
				476
				477	static bool IsLoopN(MachineInstr *MI) {
				478	return (MI->getOpcode() == Hexagon::LOOP0_i \|\|
				479	MI->getOpcode() == Hexagon::LOOP0_r);
				480	}
				481
				482	/// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a
				483	/// callee-saved register.
				484	static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
				485	const TargetRegisterInfo *TRI) {
				486	for (const uint16_t CSR = TRI->getCalleeSavedRegs(); CSR; ++CSR) {
				487	unsigned CalleeSavedReg = *CSR;
				488	if (MI->modifiesRegister(CalleeSavedReg, TRI))
				489	return true;
				490	}
				491	return false;
				492	}
				493
				494	// Return the new value instruction for a given store.
				495	static int GetDotNewOp(const int opc) {
				496	switch (opc) {
				497	default: llvm_unreachable("Unknown .new type");
				498	// store new value byte
				499	case Hexagon::STrib:
				500	return Hexagon::STrib_nv_V4;
				501
				502	case Hexagon::STrib_indexed:
				503	return Hexagon::STrib_indexed_nv_V4;
				504
				505	case Hexagon::STrib_indexed_shl_V4:
				506	return Hexagon::STrib_indexed_shl_nv_V4;
				507
				508	case Hexagon::STrib_shl_V4:
				509	return Hexagon::STrib_shl_nv_V4;
				510
				511	case Hexagon::STrib_GP_V4:
				512	return Hexagon::STrib_GP_nv_V4;
				513
				514	case Hexagon::STb_GP_V4:
				515	return Hexagon::STb_GP_nv_V4;
				516
				517	case Hexagon::POST_STbri:
				518	return Hexagon::POST_STbri_nv_V4;
				519
				520	case Hexagon::STrib_cPt:
				521	return Hexagon::STrib_cPt_nv_V4;
				522
				523	case Hexagon::STrib_cdnPt_V4:
				524	return Hexagon::STrib_cdnPt_nv_V4;
				525
				526	case Hexagon::STrib_cNotPt:
				527	return Hexagon::STrib_cNotPt_nv_V4;
				528
				529	case Hexagon::STrib_cdnNotPt_V4:
				530	return Hexagon::STrib_cdnNotPt_nv_V4;
				531
				532	case Hexagon::STrib_indexed_cPt:
				533	return Hexagon::STrib_indexed_cPt_nv_V4;
				534
				535	case Hexagon::STrib_indexed_cdnPt_V4:
				536	return Hexagon::STrib_indexed_cdnPt_nv_V4;
				537
				538	case Hexagon::STrib_indexed_cNotPt:
				539	return Hexagon::STrib_indexed_cNotPt_nv_V4;
				540
				541	case Hexagon::STrib_indexed_cdnNotPt_V4:
				542	return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
				543
				544	case Hexagon::STrib_indexed_shl_cPt_V4:
				545	return Hexagon::STrib_indexed_shl_cPt_nv_V4;
				546
				547	case Hexagon::STrib_indexed_shl_cdnPt_V4:
				548	return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
				549
				550	case Hexagon::STrib_indexed_shl_cNotPt_V4:
				551	return Hexagon::STrib_indexed_shl_cNotPt_nv_V4;
				552
				553	case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
				554	return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
				555
				556	case Hexagon::POST_STbri_cPt:
				557	return Hexagon::POST_STbri_cPt_nv_V4;
				558
				559	case Hexagon::POST_STbri_cdnPt_V4:
				560	return Hexagon::POST_STbri_cdnPt_nv_V4;
				561
				562	case Hexagon::POST_STbri_cNotPt:
				563	return Hexagon::POST_STbri_cNotPt_nv_V4;
				564
				565	case Hexagon::POST_STbri_cdnNotPt_V4:
				566	return Hexagon::POST_STbri_cdnNotPt_nv_V4;
				567
				568	case Hexagon::STb_GP_cPt_V4:
				569	return Hexagon::STb_GP_cPt_nv_V4;
				570
				571	case Hexagon::STb_GP_cNotPt_V4:
				572	return Hexagon::STb_GP_cNotPt_nv_V4;
				573
				574	case Hexagon::STb_GP_cdnPt_V4:
				575	return Hexagon::STb_GP_cdnPt_nv_V4;
				576
				577	case Hexagon::STb_GP_cdnNotPt_V4:
				578	return Hexagon::STb_GP_cdnNotPt_nv_V4;
				579
				580	case Hexagon::STrib_GP_cPt_V4:
				581	return Hexagon::STrib_GP_cPt_nv_V4;
				582
				583	case Hexagon::STrib_GP_cNotPt_V4:
				584	return Hexagon::STrib_GP_cNotPt_nv_V4;
				585
				586	case Hexagon::STrib_GP_cdnPt_V4:
				587	return Hexagon::STrib_GP_cdnPt_nv_V4;
				588
				589	case Hexagon::STrib_GP_cdnNotPt_V4:
				590	return Hexagon::STrib_GP_cdnNotPt_nv_V4;
				591
				592	// store new value halfword
				593	case Hexagon::STrih:
				594	return Hexagon::STrih_nv_V4;
				595
				596	case Hexagon::STrih_indexed:
				597	return Hexagon::STrih_indexed_nv_V4;
				598
				599	case Hexagon::STrih_indexed_shl_V4:
				600	return Hexagon::STrih_indexed_shl_nv_V4;
				601
				602	case Hexagon::STrih_shl_V4:
				603	return Hexagon::STrih_shl_nv_V4;
				604
				605	case Hexagon::STrih_GP_V4:
				606	return Hexagon::STrih_GP_nv_V4;
				607
				608	case Hexagon::STh_GP_V4:
				609	return Hexagon::STh_GP_nv_V4;
				610
				611	case Hexagon::POST_SThri:
				612	return Hexagon::POST_SThri_nv_V4;
				613
				614	case Hexagon::STrih_cPt:
				615	return Hexagon::STrih_cPt_nv_V4;
				616
				617	case Hexagon::STrih_cdnPt_V4:
				618	return Hexagon::STrih_cdnPt_nv_V4;
				619
				620	case Hexagon::STrih_cNotPt:
				621	return Hexagon::STrih_cNotPt_nv_V4;
				622
				623	case Hexagon::STrih_cdnNotPt_V4:
				624	return Hexagon::STrih_cdnNotPt_nv_V4;
				625
				626	case Hexagon::STrih_indexed_cPt:
				627	return Hexagon::STrih_indexed_cPt_nv_V4;
				628
				629	case Hexagon::STrih_indexed_cdnPt_V4:
				630	return Hexagon::STrih_indexed_cdnPt_nv_V4;
				631
				632	case Hexagon::STrih_indexed_cNotPt:
				633	return Hexagon::STrih_indexed_cNotPt_nv_V4;
				634
				635	case Hexagon::STrih_indexed_cdnNotPt_V4:
				636	return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
				637
				638	case Hexagon::STrih_indexed_shl_cPt_V4:
				639	return Hexagon::STrih_indexed_shl_cPt_nv_V4;
				640
				641	case Hexagon::STrih_indexed_shl_cdnPt_V4:
				642	return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
				643
				644	case Hexagon::STrih_indexed_shl_cNotPt_V4:
				645	return Hexagon::STrih_indexed_shl_cNotPt_nv_V4;
				646
				647	case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
				648	return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
				649
				650	case Hexagon::POST_SThri_cPt:
				651	return Hexagon::POST_SThri_cPt_nv_V4;
				652
				653	case Hexagon::POST_SThri_cdnPt_V4:
				654	return Hexagon::POST_SThri_cdnPt_nv_V4;
				655
				656	case Hexagon::POST_SThri_cNotPt:
				657	return Hexagon::POST_SThri_cNotPt_nv_V4;
				658
				659	case Hexagon::POST_SThri_cdnNotPt_V4:
				660	return Hexagon::POST_SThri_cdnNotPt_nv_V4;
				661
				662	case Hexagon::STh_GP_cPt_V4:
				663	return Hexagon::STh_GP_cPt_nv_V4;
				664
				665	case Hexagon::STh_GP_cNotPt_V4:
				666	return Hexagon::STh_GP_cNotPt_nv_V4;
				667
				668	case Hexagon::STh_GP_cdnPt_V4:
				669	return Hexagon::STh_GP_cdnPt_nv_V4;
				670
				671	case Hexagon::STh_GP_cdnNotPt_V4:
				672	return Hexagon::STh_GP_cdnNotPt_nv_V4;
				673
				674	case Hexagon::STrih_GP_cPt_V4:
				675	return Hexagon::STrih_GP_cPt_nv_V4;
				676
				677	case Hexagon::STrih_GP_cNotPt_V4:
				678	return Hexagon::STrih_GP_cNotPt_nv_V4;
				679
				680	case Hexagon::STrih_GP_cdnPt_V4:
				681	return Hexagon::STrih_GP_cdnPt_nv_V4;
				682
				683	case Hexagon::STrih_GP_cdnNotPt_V4:
				684	return Hexagon::STrih_GP_cdnNotPt_nv_V4;
				685
				686	// store new value word
				687	case Hexagon::STriw:
				688	return Hexagon::STriw_nv_V4;
				689
				690	case Hexagon::STriw_indexed:
				691	return Hexagon::STriw_indexed_nv_V4;
				692
				693	case Hexagon::STriw_indexed_shl_V4:
				694	return Hexagon::STriw_indexed_shl_nv_V4;
				695
				696	case Hexagon::STriw_shl_V4:
				697	return Hexagon::STriw_shl_nv_V4;
				698
				699	case Hexagon::STriw_GP_V4:
				700	return Hexagon::STriw_GP_nv_V4;
				701
				702	case Hexagon::STw_GP_V4:
				703	return Hexagon::STw_GP_nv_V4;
				704
				705	case Hexagon::POST_STwri:
				706	return Hexagon::POST_STwri_nv_V4;
				707
				708	case Hexagon::STriw_cPt:
				709	return Hexagon::STriw_cPt_nv_V4;
				710
				711	case Hexagon::STriw_cdnPt_V4:
				712	return Hexagon::STriw_cdnPt_nv_V4;
				713
				714	case Hexagon::STriw_cNotPt:
				715	return Hexagon::STriw_cNotPt_nv_V4;
				716
				717	case Hexagon::STriw_cdnNotPt_V4:
				718	return Hexagon::STriw_cdnNotPt_nv_V4;
				719
				720	case Hexagon::STriw_indexed_cPt:
				721	return Hexagon::STriw_indexed_cPt_nv_V4;
				722
				723	case Hexagon::STriw_indexed_cdnPt_V4:
				724	return Hexagon::STriw_indexed_cdnPt_nv_V4;
				725
				726	case Hexagon::STriw_indexed_cNotPt:
				727	return Hexagon::STriw_indexed_cNotPt_nv_V4;
				728
				729	case Hexagon::STriw_indexed_cdnNotPt_V4:
				730	return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
				731
				732	case Hexagon::STriw_indexed_shl_cPt_V4:
				733	return Hexagon::STriw_indexed_shl_cPt_nv_V4;
				734
				735	case Hexagon::STriw_indexed_shl_cdnPt_V4:
				736	return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
				737
				738	case Hexagon::STriw_indexed_shl_cNotPt_V4:
				739	return Hexagon::STriw_indexed_shl_cNotPt_nv_V4;
				740
				741	case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
				742	return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
				743
				744	case Hexagon::POST_STwri_cPt:
				745	return Hexagon::POST_STwri_cPt_nv_V4;
				746
				747	case Hexagon::POST_STwri_cdnPt_V4:
				748	return Hexagon::POST_STwri_cdnPt_nv_V4;
				749
				750	case Hexagon::POST_STwri_cNotPt:
				751	return Hexagon::POST_STwri_cNotPt_nv_V4;
				752
				753	case Hexagon::POST_STwri_cdnNotPt_V4:
				754	return Hexagon::POST_STwri_cdnNotPt_nv_V4;
				755
				756	case Hexagon::STw_GP_cPt_V4:
				757	return Hexagon::STw_GP_cPt_nv_V4;
				758
				759	case Hexagon::STw_GP_cNotPt_V4:
				760	return Hexagon::STw_GP_cNotPt_nv_V4;
				761
				762	case Hexagon::STw_GP_cdnPt_V4:
				763	return Hexagon::STw_GP_cdnPt_nv_V4;
				764
				765	case Hexagon::STw_GP_cdnNotPt_V4:
				766	return Hexagon::STw_GP_cdnNotPt_nv_V4;
				767
				768	case Hexagon::STriw_GP_cPt_V4:
				769	return Hexagon::STriw_GP_cPt_nv_V4;
				770
				771	case Hexagon::STriw_GP_cNotPt_V4:
				772	return Hexagon::STriw_GP_cNotPt_nv_V4;
				773
				774	case Hexagon::STriw_GP_cdnPt_V4:
				775	return Hexagon::STriw_GP_cdnPt_nv_V4;
				776
				777	case Hexagon::STriw_GP_cdnNotPt_V4:
				778	return Hexagon::STriw_GP_cdnNotPt_nv_V4;
				779	}
				780	}
				781
				782	// Return .new predicate version for an instruction
				783	static int GetDotNewPredOp(const int opc) {
				784	switch (opc) {
				785	default: llvm_unreachable("Unknown .new type");
				786	// Conditional stores
				787	// Store byte conditionally
				788	case Hexagon::STrib_cPt :
				789	return Hexagon::STrib_cdnPt_V4;
				790
				791	case Hexagon::STrib_cNotPt :
				792	return Hexagon::STrib_cdnNotPt_V4;
				793
				794	case Hexagon::STrib_indexed_cPt :
				795	return Hexagon::STrib_indexed_cdnPt_V4;
				796
				797	case Hexagon::STrib_indexed_cNotPt :
				798	return Hexagon::STrib_indexed_cdnNotPt_V4;
				799
				800	case Hexagon::STrib_imm_cPt_V4 :
				801	return Hexagon::STrib_imm_cdnPt_V4;
				802
				803	case Hexagon::STrib_imm_cNotPt_V4 :
				804	return Hexagon::STrib_imm_cdnNotPt_V4;
				805
				806	case Hexagon::POST_STbri_cPt :
				807	return Hexagon::POST_STbri_cdnPt_V4;
				808
				809	case Hexagon::POST_STbri_cNotPt :
				810	return Hexagon::POST_STbri_cdnNotPt_V4;
				811
				812	case Hexagon::STrib_indexed_shl_cPt_V4 :
				813	return Hexagon::STrib_indexed_shl_cdnPt_V4;
				814
				815	case Hexagon::STrib_indexed_shl_cNotPt_V4 :
				816	return Hexagon::STrib_indexed_shl_cdnNotPt_V4;
				817
				818	case Hexagon::STb_GP_cPt_V4 :
				819	return Hexagon::STb_GP_cdnPt_V4;
				820
				821	case Hexagon::STb_GP_cNotPt_V4 :
				822	return Hexagon::STb_GP_cdnNotPt_V4;
				823
				824	case Hexagon::STrib_GP_cPt_V4 :
				825	return Hexagon::STrib_GP_cdnPt_V4;
				826
				827	case Hexagon::STrib_GP_cNotPt_V4 :
				828	return Hexagon::STrib_GP_cdnNotPt_V4;
				829
				830	// Store doubleword conditionally
				831	case Hexagon::STrid_cPt :
				832	return Hexagon::STrid_cdnPt_V4;
				833
				834	case Hexagon::STrid_cNotPt :
				835	return Hexagon::STrid_cdnNotPt_V4;
				836
				837	case Hexagon::STrid_indexed_cPt :
				838	return Hexagon::STrid_indexed_cdnPt_V4;
				839
				840	case Hexagon::STrid_indexed_cNotPt :
				841	return Hexagon::STrid_indexed_cdnNotPt_V4;
				842
				843	case Hexagon::STrid_indexed_shl_cPt_V4 :
				844	return Hexagon::STrid_indexed_shl_cdnPt_V4;
				845
				846	case Hexagon::STrid_indexed_shl_cNotPt_V4 :
				847	return Hexagon::STrid_indexed_shl_cdnNotPt_V4;
				848
				849	case Hexagon::POST_STdri_cPt :
				850	return Hexagon::POST_STdri_cdnPt_V4;
				851
				852	case Hexagon::POST_STdri_cNotPt :
				853	return Hexagon::POST_STdri_cdnNotPt_V4;
				854
				855	case Hexagon::STd_GP_cPt_V4 :
				856	return Hexagon::STd_GP_cdnPt_V4;
				857
				858	case Hexagon::STd_GP_cNotPt_V4 :
				859	return Hexagon::STd_GP_cdnNotPt_V4;
				860
				861	case Hexagon::STrid_GP_cPt_V4 :
				862	return Hexagon::STrid_GP_cdnPt_V4;
				863
				864	case Hexagon::STrid_GP_cNotPt_V4 :
				865	return Hexagon::STrid_GP_cdnNotPt_V4;
				866
				867	// Store halfword conditionally
				868	case Hexagon::STrih_cPt :
				869	return Hexagon::STrih_cdnPt_V4;
				870
				871	case Hexagon::STrih_cNotPt :
				872	return Hexagon::STrih_cdnNotPt_V4;
				873
				874	case Hexagon::STrih_indexed_cPt :
				875	return Hexagon::STrih_indexed_cdnPt_V4;
				876
				877	case Hexagon::STrih_indexed_cNotPt :
				878	return Hexagon::STrih_indexed_cdnNotPt_V4;
				879
				880	case Hexagon::STrih_imm_cPt_V4 :
				881	return Hexagon::STrih_imm_cdnPt_V4;
				882
				883	case Hexagon::STrih_imm_cNotPt_V4 :
				884	return Hexagon::STrih_imm_cdnNotPt_V4;
				885
				886	case Hexagon::STrih_indexed_shl_cPt_V4 :
				887	return Hexagon::STrih_indexed_shl_cdnPt_V4;
				888
				889	case Hexagon::STrih_indexed_shl_cNotPt_V4 :
				890	return Hexagon::STrih_indexed_shl_cdnNotPt_V4;
				891
				892	case Hexagon::POST_SThri_cPt :
				893	return Hexagon::POST_SThri_cdnPt_V4;
				894
				895	case Hexagon::POST_SThri_cNotPt :
				896	return Hexagon::POST_SThri_cdnNotPt_V4;
				897
				898	case Hexagon::STh_GP_cPt_V4 :
				899	return Hexagon::STh_GP_cdnPt_V4;
				900
				901	case Hexagon::STh_GP_cNotPt_V4 :
				902	return Hexagon::STh_GP_cdnNotPt_V4;
				903
				904	case Hexagon::STrih_GP_cPt_V4 :
				905	return Hexagon::STrih_GP_cdnPt_V4;
				906
				907	case Hexagon::STrih_GP_cNotPt_V4 :
				908	return Hexagon::STrih_GP_cdnNotPt_V4;
				909
				910	// Store word conditionally
				911	case Hexagon::STriw_cPt :
				912	return Hexagon::STriw_cdnPt_V4;
				913
				914	case Hexagon::STriw_cNotPt :
				915	return Hexagon::STriw_cdnNotPt_V4;
				916
				917	case Hexagon::STriw_indexed_cPt :
				918	return Hexagon::STriw_indexed_cdnPt_V4;
				919
				920	case Hexagon::STriw_indexed_cNotPt :
				921	return Hexagon::STriw_indexed_cdnNotPt_V4;
				922
				923	case Hexagon::STriw_imm_cPt_V4 :
				924	return Hexagon::STriw_imm_cdnPt_V4;
				925
				926	case Hexagon::STriw_imm_cNotPt_V4 :
				927	return Hexagon::STriw_imm_cdnNotPt_V4;
				928
				929	case Hexagon::STriw_indexed_shl_cPt_V4 :
				930	return Hexagon::STriw_indexed_shl_cdnPt_V4;
				931
				932	case Hexagon::STriw_indexed_shl_cNotPt_V4 :
				933	return Hexagon::STriw_indexed_shl_cdnNotPt_V4;
				934
				935	case Hexagon::POST_STwri_cPt :
				936	return Hexagon::POST_STwri_cdnPt_V4;
				937
				938	case Hexagon::POST_STwri_cNotPt :
				939	return Hexagon::POST_STwri_cdnNotPt_V4;
				940
				941	case Hexagon::STw_GP_cPt_V4 :
				942	return Hexagon::STw_GP_cdnPt_V4;
				943
				944	case Hexagon::STw_GP_cNotPt_V4 :
				945	return Hexagon::STw_GP_cdnNotPt_V4;
				946
				947	case Hexagon::STriw_GP_cPt_V4 :
				948	return Hexagon::STriw_GP_cdnPt_V4;
				949
				950	case Hexagon::STriw_GP_cNotPt_V4 :
				951	return Hexagon::STriw_GP_cdnNotPt_V4;
				952
				953	// Condtional Jumps
				954	case Hexagon::JMP_c:
				955	return Hexagon::JMP_cdnPt;
				956
				957	case Hexagon::JMP_cNot:
				958	return Hexagon::JMP_cdnNotPt;
				959
				960	case Hexagon::JMPR_cPt:
				961	return Hexagon::JMPR_cdnPt_V3;
				962
				963	case Hexagon::JMPR_cNotPt:
				964	return Hexagon::JMPR_cdnNotPt_V3;
				965
				966	// Conditional Transfers
				967	case Hexagon::TFR_cPt:
				968	return Hexagon::TFR_cdnPt;
				969
				970	case Hexagon::TFR_cNotPt:
				971	return Hexagon::TFR_cdnNotPt;
				972
				973	case Hexagon::TFRI_cPt:
				974	return Hexagon::TFRI_cdnPt;
				975
				976	case Hexagon::TFRI_cNotPt:
				977	return Hexagon::TFRI_cdnNotPt;
				978
				979	// Load double word
				980	case Hexagon::LDrid_cPt :
				981	return Hexagon::LDrid_cdnPt;
				982
				983	case Hexagon::LDrid_cNotPt :
				984	return Hexagon::LDrid_cdnNotPt;
				985
				986	case Hexagon::LDrid_indexed_cPt :
				987	return Hexagon::LDrid_indexed_cdnPt;
				988
				989	case Hexagon::LDrid_indexed_cNotPt :
				990	return Hexagon::LDrid_indexed_cdnNotPt;
				991
				992	case Hexagon::POST_LDrid_cPt :
				993	return Hexagon::POST_LDrid_cdnPt_V4;
				994
				995	case Hexagon::POST_LDrid_cNotPt :
				996	return Hexagon::POST_LDrid_cdnNotPt_V4;
				997
				998	// Load word
				999	case Hexagon::LDriw_cPt :
				1000	return Hexagon::LDriw_cdnPt;
				1001
				1002	case Hexagon::LDriw_cNotPt :
				1003	return Hexagon::LDriw_cdnNotPt;
				1004
				1005	case Hexagon::LDriw_indexed_cPt :
				1006	return Hexagon::LDriw_indexed_cdnPt;
				1007
				1008	case Hexagon::LDriw_indexed_cNotPt :
				1009	return Hexagon::LDriw_indexed_cdnNotPt;
				1010
				1011	case Hexagon::POST_LDriw_cPt :
				1012	return Hexagon::POST_LDriw_cdnPt_V4;
				1013
				1014	case Hexagon::POST_LDriw_cNotPt :
				1015	return Hexagon::POST_LDriw_cdnNotPt_V4;
				1016
				1017	// Load halfword
				1018	case Hexagon::LDrih_cPt :
				1019	return Hexagon::LDrih_cdnPt;
				1020
				1021	case Hexagon::LDrih_cNotPt :
				1022	return Hexagon::LDrih_cdnNotPt;
				1023
				1024	case Hexagon::LDrih_indexed_cPt :
				1025	return Hexagon::LDrih_indexed_cdnPt;
				1026
				1027	case Hexagon::LDrih_indexed_cNotPt :
				1028	return Hexagon::LDrih_indexed_cdnNotPt;
				1029
				1030	case Hexagon::POST_LDrih_cPt :
				1031	return Hexagon::POST_LDrih_cdnPt_V4;
				1032
				1033	case Hexagon::POST_LDrih_cNotPt :
				1034	return Hexagon::POST_LDrih_cdnNotPt_V4;
				1035
				1036	// Load byte
				1037	case Hexagon::LDrib_cPt :
				1038	return Hexagon::LDrib_cdnPt;
				1039
				1040	case Hexagon::LDrib_cNotPt :
				1041	return Hexagon::LDrib_cdnNotPt;
				1042
				1043	case Hexagon::LDrib_indexed_cPt :
				1044	return Hexagon::LDrib_indexed_cdnPt;
				1045
				1046	case Hexagon::LDrib_indexed_cNotPt :
				1047	return Hexagon::LDrib_indexed_cdnNotPt;
				1048
				1049	case Hexagon::POST_LDrib_cPt :
				1050	return Hexagon::POST_LDrib_cdnPt_V4;
				1051
				1052	case Hexagon::POST_LDrib_cNotPt :
				1053	return Hexagon::POST_LDrib_cdnNotPt_V4;
				1054
				1055	// Load unsigned halfword
				1056	case Hexagon::LDriuh_cPt :
				1057	return Hexagon::LDriuh_cdnPt;
				1058
				1059	case Hexagon::LDriuh_cNotPt :
				1060	return Hexagon::LDriuh_cdnNotPt;
				1061
				1062	case Hexagon::LDriuh_indexed_cPt :
				1063	return Hexagon::LDriuh_indexed_cdnPt;
				1064
				1065	case Hexagon::LDriuh_indexed_cNotPt :
				1066	return Hexagon::LDriuh_indexed_cdnNotPt;
				1067
				1068	case Hexagon::POST_LDriuh_cPt :
				1069	return Hexagon::POST_LDriuh_cdnPt_V4;
				1070
				1071	case Hexagon::POST_LDriuh_cNotPt :
				1072	return Hexagon::POST_LDriuh_cdnNotPt_V4;
				1073
				1074	// Load unsigned byte
				1075	case Hexagon::LDriub_cPt :
				1076	return Hexagon::LDriub_cdnPt;
				1077
				1078	case Hexagon::LDriub_cNotPt :
				1079	return Hexagon::LDriub_cdnNotPt;
				1080
				1081	case Hexagon::LDriub_indexed_cPt :
				1082	return Hexagon::LDriub_indexed_cdnPt;
				1083
				1084	case Hexagon::LDriub_indexed_cNotPt :
				1085	return Hexagon::LDriub_indexed_cdnNotPt;
				1086
				1087	case Hexagon::POST_LDriub_cPt :
				1088	return Hexagon::POST_LDriub_cdnPt_V4;
				1089
				1090	case Hexagon::POST_LDriub_cNotPt :
				1091	return Hexagon::POST_LDriub_cdnNotPt_V4;
				1092
				1093	// V4 indexed+scaled load
				1094
				1095	case Hexagon::LDrid_indexed_cPt_V4 :
				1096	return Hexagon::LDrid_indexed_cdnPt_V4;
				1097
				1098	case Hexagon::LDrid_indexed_cNotPt_V4 :
				1099	return Hexagon::LDrid_indexed_cdnNotPt_V4;
				1100
				1101	case Hexagon::LDrid_indexed_shl_cPt_V4 :
				1102	return Hexagon::LDrid_indexed_shl_cdnPt_V4;
				1103
				1104	case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
				1105	return Hexagon::LDrid_indexed_shl_cdnNotPt_V4;
				1106
				1107	case Hexagon::LDrib_indexed_cPt_V4 :
				1108	return Hexagon::LDrib_indexed_cdnPt_V4;
				1109
				1110	case Hexagon::LDrib_indexed_cNotPt_V4 :
				1111	return Hexagon::LDrib_indexed_cdnNotPt_V4;
				1112
				1113	case Hexagon::LDrib_indexed_shl_cPt_V4 :
				1114	return Hexagon::LDrib_indexed_shl_cdnPt_V4;
				1115
				1116	case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
				1117	return Hexagon::LDrib_indexed_shl_cdnNotPt_V4;
				1118
				1119	case Hexagon::LDriub_indexed_cPt_V4 :
				1120	return Hexagon::LDriub_indexed_cdnPt_V4;
				1121
				1122	case Hexagon::LDriub_indexed_cNotPt_V4 :
				1123	return Hexagon::LDriub_indexed_cdnNotPt_V4;
				1124
				1125	case Hexagon::LDriub_indexed_shl_cPt_V4 :
				1126	return Hexagon::LDriub_indexed_shl_cdnPt_V4;
				1127
				1128	case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
				1129	return Hexagon::LDriub_indexed_shl_cdnNotPt_V4;
				1130
				1131	case Hexagon::LDrih_indexed_cPt_V4 :
				1132	return Hexagon::LDrih_indexed_cdnPt_V4;
				1133
				1134	case Hexagon::LDrih_indexed_cNotPt_V4 :
				1135	return Hexagon::LDrih_indexed_cdnNotPt_V4;
				1136
				1137	case Hexagon::LDrih_indexed_shl_cPt_V4 :
				1138	return Hexagon::LDrih_indexed_shl_cdnPt_V4;
				1139
				1140	case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
				1141	return Hexagon::LDrih_indexed_shl_cdnNotPt_V4;
				1142
				1143	case Hexagon::LDriuh_indexed_cPt_V4 :
				1144	return Hexagon::LDriuh_indexed_cdnPt_V4;
				1145
				1146	case Hexagon::LDriuh_indexed_cNotPt_V4 :
				1147	return Hexagon::LDriuh_indexed_cdnNotPt_V4;
				1148
				1149	case Hexagon::LDriuh_indexed_shl_cPt_V4 :
				1150	return Hexagon::LDriuh_indexed_shl_cdnPt_V4;
				1151
				1152	case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
				1153	return Hexagon::LDriuh_indexed_shl_cdnNotPt_V4;
				1154
				1155	case Hexagon::LDriw_indexed_cPt_V4 :
				1156	return Hexagon::LDriw_indexed_cdnPt_V4;
				1157
				1158	case Hexagon::LDriw_indexed_cNotPt_V4 :
				1159	return Hexagon::LDriw_indexed_cdnNotPt_V4;
				1160
				1161	case Hexagon::LDriw_indexed_shl_cPt_V4 :
				1162	return Hexagon::LDriw_indexed_shl_cdnPt_V4;
				1163
				1164	case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
				1165	return Hexagon::LDriw_indexed_shl_cdnNotPt_V4;
				1166
				1167	// V4 global address load
				1168
				1169	case Hexagon::LDd_GP_cPt_V4:
				1170	return Hexagon::LDd_GP_cdnPt_V4;
				1171
				1172	case Hexagon::LDd_GP_cNotPt_V4:
				1173	return Hexagon::LDd_GP_cdnNotPt_V4;
				1174
				1175	case Hexagon::LDb_GP_cPt_V4:
				1176	return Hexagon::LDb_GP_cdnPt_V4;
				1177
				1178	case Hexagon::LDb_GP_cNotPt_V4:
				1179	return Hexagon::LDb_GP_cdnNotPt_V4;
				1180
				1181	case Hexagon::LDub_GP_cPt_V4:
				1182	return Hexagon::LDub_GP_cdnPt_V4;
				1183
				1184	case Hexagon::LDub_GP_cNotPt_V4:
				1185	return Hexagon::LDub_GP_cdnNotPt_V4;
				1186
				1187	case Hexagon::LDh_GP_cPt_V4:
				1188	return Hexagon::LDh_GP_cdnPt_V4;
				1189
				1190	case Hexagon::LDh_GP_cNotPt_V4:
				1191	return Hexagon::LDh_GP_cdnNotPt_V4;
				1192
				1193	case Hexagon::LDuh_GP_cPt_V4:
				1194	return Hexagon::LDuh_GP_cdnPt_V4;
				1195
				1196	case Hexagon::LDuh_GP_cNotPt_V4:
				1197	return Hexagon::LDuh_GP_cdnNotPt_V4;
				1198
				1199	case Hexagon::LDw_GP_cPt_V4:
				1200	return Hexagon::LDw_GP_cdnPt_V4;
				1201
				1202	case Hexagon::LDw_GP_cNotPt_V4:
				1203	return Hexagon::LDw_GP_cdnNotPt_V4;
				1204
				1205	case Hexagon::LDrid_GP_cPt_V4:
				1206	return Hexagon::LDrid_GP_cdnPt_V4;
				1207
				1208	case Hexagon::LDrid_GP_cNotPt_V4:
				1209	return Hexagon::LDrid_GP_cdnNotPt_V4;
				1210
				1211	case Hexagon::LDrib_GP_cPt_V4:
				1212	return Hexagon::LDrib_GP_cdnPt_V4;
				1213
				1214	case Hexagon::LDrib_GP_cNotPt_V4:
				1215	return Hexagon::LDrib_GP_cdnNotPt_V4;
				1216
				1217	case Hexagon::LDriub_GP_cPt_V4:
				1218	return Hexagon::LDriub_GP_cdnPt_V4;
				1219
				1220	case Hexagon::LDriub_GP_cNotPt_V4:
				1221	return Hexagon::LDriub_GP_cdnNotPt_V4;
				1222
				1223	case Hexagon::LDrih_GP_cPt_V4:
				1224	return Hexagon::LDrih_GP_cdnPt_V4;
				1225
				1226	case Hexagon::LDrih_GP_cNotPt_V4:
				1227	return Hexagon::LDrih_GP_cdnNotPt_V4;
				1228
				1229	case Hexagon::LDriuh_GP_cPt_V4:
				1230	return Hexagon::LDriuh_GP_cdnPt_V4;
				1231
				1232	case Hexagon::LDriuh_GP_cNotPt_V4:
				1233	return Hexagon::LDriuh_GP_cdnNotPt_V4;
				1234
				1235	case Hexagon::LDriw_GP_cPt_V4:
				1236	return Hexagon::LDriw_GP_cdnPt_V4;
				1237
				1238	case Hexagon::LDriw_GP_cNotPt_V4:
				1239	return Hexagon::LDriw_GP_cdnNotPt_V4;
				1240
				1241	// Conditional store new-value byte
				1242	case Hexagon::STrib_cPt_nv_V4 :
				1243	return Hexagon::STrib_cdnPt_nv_V4;
				1244	case Hexagon::STrib_cNotPt_nv_V4 :
				1245	return Hexagon::STrib_cdnNotPt_nv_V4;
				1246
				1247	case Hexagon::STrib_indexed_cPt_nv_V4 :
				1248	return Hexagon::STrib_indexed_cdnPt_nv_V4;
				1249	case Hexagon::STrib_indexed_cNotPt_nv_V4 :
				1250	return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
				1251
				1252	case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
				1253	return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
				1254	case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
				1255	return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
				1256
				1257	case Hexagon::POST_STbri_cPt_nv_V4 :
				1258	return Hexagon::POST_STbri_cdnPt_nv_V4;
				1259	case Hexagon::POST_STbri_cNotPt_nv_V4 :
				1260	return Hexagon::POST_STbri_cdnNotPt_nv_V4;
				1261
				1262	case Hexagon::STb_GP_cPt_nv_V4 :
				1263	return Hexagon::STb_GP_cdnPt_nv_V4;
				1264
				1265	case Hexagon::STb_GP_cNotPt_nv_V4 :
				1266	return Hexagon::STb_GP_cdnNotPt_nv_V4;
				1267
				1268	case Hexagon::STrib_GP_cPt_nv_V4 :
				1269	return Hexagon::STrib_GP_cdnPt_nv_V4;
				1270
				1271	case Hexagon::STrib_GP_cNotPt_nv_V4 :
				1272	return Hexagon::STrib_GP_cdnNotPt_nv_V4;
				1273
				1274	// Conditional store new-value halfword
				1275	case Hexagon::STrih_cPt_nv_V4 :
				1276	return Hexagon::STrih_cdnPt_nv_V4;
				1277	case Hexagon::STrih_cNotPt_nv_V4 :
				1278	return Hexagon::STrih_cdnNotPt_nv_V4;
				1279
				1280	case Hexagon::STrih_indexed_cPt_nv_V4 :
				1281	return Hexagon::STrih_indexed_cdnPt_nv_V4;
				1282	case Hexagon::STrih_indexed_cNotPt_nv_V4 :
				1283	return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
				1284
				1285	case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
				1286	return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
				1287	case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
				1288	return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
				1289
				1290	case Hexagon::POST_SThri_cPt_nv_V4 :
				1291	return Hexagon::POST_SThri_cdnPt_nv_V4;
				1292	case Hexagon::POST_SThri_cNotPt_nv_V4 :
				1293	return Hexagon::POST_SThri_cdnNotPt_nv_V4;
				1294
				1295	case Hexagon::STh_GP_cPt_nv_V4 :
				1296	return Hexagon::STh_GP_cdnPt_nv_V4;
				1297
				1298	case Hexagon::STh_GP_cNotPt_nv_V4 :
				1299	return Hexagon::STh_GP_cdnNotPt_nv_V4;
				1300
				1301	case Hexagon::STrih_GP_cPt_nv_V4 :
				1302	return Hexagon::STrih_GP_cdnPt_nv_V4;
				1303
				1304	case Hexagon::STrih_GP_cNotPt_nv_V4 :
				1305	return Hexagon::STrih_GP_cdnNotPt_nv_V4;
				1306
				1307	// Conditional store new-value word
				1308	case Hexagon::STriw_cPt_nv_V4 :
				1309	return Hexagon::STriw_cdnPt_nv_V4;
				1310	case Hexagon::STriw_cNotPt_nv_V4 :
				1311	return Hexagon::STriw_cdnNotPt_nv_V4;
				1312
				1313	case Hexagon::STriw_indexed_cPt_nv_V4 :
				1314	return Hexagon::STriw_indexed_cdnPt_nv_V4;
				1315	case Hexagon::STriw_indexed_cNotPt_nv_V4 :
				1316	return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
				1317
				1318	case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
				1319	return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
				1320	case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
				1321	return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
				1322
				1323	case Hexagon::POST_STwri_cPt_nv_V4 :
				1324	return Hexagon::POST_STwri_cdnPt_nv_V4;
				1325	case Hexagon::POST_STwri_cNotPt_nv_V4:
				1326	return Hexagon::POST_STwri_cdnNotPt_nv_V4;
				1327
				1328	case Hexagon::STw_GP_cPt_nv_V4 :
				1329	return Hexagon::STw_GP_cdnPt_nv_V4;
				1330
				1331	case Hexagon::STw_GP_cNotPt_nv_V4 :
				1332	return Hexagon::STw_GP_cdnNotPt_nv_V4;
				1333
				1334	case Hexagon::STriw_GP_cPt_nv_V4 :
				1335	return Hexagon::STriw_GP_cdnPt_nv_V4;
				1336
				1337	case Hexagon::STriw_GP_cNotPt_nv_V4 :
				1338	return Hexagon::STriw_GP_cdnNotPt_nv_V4;
				1339
				1340	// Conditional add
				1341	case Hexagon::ADD_ri_cPt :
				1342	return Hexagon::ADD_ri_cdnPt;
				1343	case Hexagon::ADD_ri_cNotPt :
				1344	return Hexagon::ADD_ri_cdnNotPt;
				1345
				1346	case Hexagon::ADD_rr_cPt :
				1347	return Hexagon::ADD_rr_cdnPt;
				1348	case Hexagon::ADD_rr_cNotPt :
				1349	return Hexagon::ADD_rr_cdnNotPt;
				1350
				1351	// Conditional logical Operations
				1352	case Hexagon::XOR_rr_cPt :
				1353	return Hexagon::XOR_rr_cdnPt;
				1354	case Hexagon::XOR_rr_cNotPt :
				1355	return Hexagon::XOR_rr_cdnNotPt;
				1356
				1357	case Hexagon::AND_rr_cPt :
				1358	return Hexagon::AND_rr_cdnPt;
				1359	case Hexagon::AND_rr_cNotPt :
				1360	return Hexagon::AND_rr_cdnNotPt;
				1361
				1362	case Hexagon::OR_rr_cPt :
				1363	return Hexagon::OR_rr_cdnPt;
				1364	case Hexagon::OR_rr_cNotPt :
				1365	return Hexagon::OR_rr_cdnNotPt;
				1366
				1367	// Conditional Subtract
				1368	case Hexagon::SUB_rr_cPt :
				1369	return Hexagon::SUB_rr_cdnPt;
				1370	case Hexagon::SUB_rr_cNotPt :
				1371	return Hexagon::SUB_rr_cdnNotPt;
				1372
				1373	// Conditional combine
				1374	case Hexagon::COMBINE_rr_cPt :
				1375	return Hexagon::COMBINE_rr_cdnPt;
				1376	case Hexagon::COMBINE_rr_cNotPt :
				1377	return Hexagon::COMBINE_rr_cdnNotPt;
				1378
				1379	case Hexagon::ASLH_cPt_V4 :
				1380	return Hexagon::ASLH_cdnPt_V4;
				1381	case Hexagon::ASLH_cNotPt_V4 :
				1382	return Hexagon::ASLH_cdnNotPt_V4;
				1383
				1384	case Hexagon::ASRH_cPt_V4 :
				1385	return Hexagon::ASRH_cdnPt_V4;
				1386	case Hexagon::ASRH_cNotPt_V4 :
				1387	return Hexagon::ASRH_cdnNotPt_V4;
				1388
				1389	case Hexagon::SXTB_cPt_V4 :
				1390	return Hexagon::SXTB_cdnPt_V4;
				1391	case Hexagon::SXTB_cNotPt_V4 :
				1392	return Hexagon::SXTB_cdnNotPt_V4;
				1393
				1394	case Hexagon::SXTH_cPt_V4 :
				1395	return Hexagon::SXTH_cdnPt_V4;
				1396	case Hexagon::SXTH_cNotPt_V4 :
				1397	return Hexagon::SXTH_cdnNotPt_V4;
				1398
				1399	case Hexagon::ZXTB_cPt_V4 :
				1400	return Hexagon::ZXTB_cdnPt_V4;
				1401	case Hexagon::ZXTB_cNotPt_V4 :
				1402	return Hexagon::ZXTB_cdnNotPt_V4;
				1403
				1404	case Hexagon::ZXTH_cPt_V4 :
				1405	return Hexagon::ZXTH_cdnPt_V4;
				1406	case Hexagon::ZXTH_cNotPt_V4 :
				1407	return Hexagon::ZXTH_cdnNotPt_V4;
				1408	}
				1409	}
				1410
				1411	// Returns true if an instruction can be promoted to .new predicate
				1412	// or new-value store.
				1413	bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
				1414	if ( isCondInst(MI) \|\| IsNewifyStore(MI))
				1415	return true;
				1416	else
				1417	return false;
				1418	}
				1419
				1420	bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
				1421	const HexagonInstrInfo QII = (const HexagonInstrInfo ) TII;
				1422	const MCInstrDesc& TID = MI->getDesc();
				1423	// bug 5670: until that is fixed,
				1424	// this portion is disabled.
				1425	if ( TID.isConditionalBranch() // && !IsRegisterJump(MI)) \|\|
				1426	\|\| QII->isConditionalTransfer(MI)
				1427	\|\| QII->isConditionalALU32(MI)
				1428	\|\| QII->isConditionalLoad(MI)
				1429	\|\| QII->isConditionalStore(MI)) {
				1430	return true;
				1431	}
				1432	return false;
				1433	}
				1434
Brendon Cahoon	5262abb	2012-05-14 19:35:42 +0000	[diff] [blame]	1435
Sirish Pande	26f61a1	2012-05-03 21:52:53 +0000	[diff] [blame]	1436	// Promote an instructiont to its .new form.
				1437	// At this time, we have already made a call to CanPromoteToDotNew
				1438	// and made sure that it can indeed be promoted.
				1439	bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
				1440	SDep::Kind DepType, MachineBasicBlock::iterator &MII,
				1441	const TargetRegisterClass* RC) {
				1442
				1443	assert (DepType == SDep::Data);
				1444	const HexagonInstrInfo QII = (const HexagonInstrInfo ) TII;
				1445
				1446	int NewOpcode;
				1447	if (RC == &Hexagon::PredRegsRegClass)
				1448	NewOpcode = GetDotNewPredOp(MI->getOpcode());
				1449	else
				1450	NewOpcode = GetDotNewOp(MI->getOpcode());
				1451	MI->setDesc(QII->get(NewOpcode));
				1452
				1453	return true;
				1454	}
				1455
				1456	// Returns the most basic instruction for the .new predicated instructions and
				1457	// new-value stores.
				1458	// For example, all of the following instructions will be converted back to the
				1459	// same instruction:
				1460	// 1) if (p0.new) memw(R0+#0) = R1.new --->
				1461	// 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
				1462	// 3) if (p0.new) memw(R0+#0) = R1 --->
				1463	//
				1464	// To understand the translation of instruction 1 to its original form, consider
				1465	// a packet with 3 instructions.
				1466	// { p0 = cmp.eq(R0,R1)
				1467	// if (p0.new) R2 = add(R3, R4)
				1468	// R5 = add (R3, R1)
				1469	// }
				1470	// if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
				1471	//
				1472	// This instruction can be part of the previous packet only if both p0 and R2
				1473	// are promoted to .new values. This promotion happens in steps, first
				1474	// predicate register is promoted to .new and in the next iteration R2 is
				1475	// promoted. Therefore, in case of dependence check failure (due to R5) during
				1476	// next iteration, it should be converted back to its most basic form.
				1477
				1478	static int GetDotOldOp(const int opc) {
				1479	switch (opc) {
				1480	default: llvm_unreachable("Unknown .old type");
				1481	case Hexagon::TFR_cdnPt:
				1482	return Hexagon::TFR_cPt;
				1483
				1484	case Hexagon::TFR_cdnNotPt:
				1485	return Hexagon::TFR_cNotPt;
				1486
				1487	case Hexagon::TFRI_cdnPt:
				1488	return Hexagon::TFRI_cPt;
				1489
				1490	case Hexagon::TFRI_cdnNotPt:
				1491	return Hexagon::TFRI_cNotPt;
				1492
				1493	case Hexagon::JMP_cdnPt:
				1494	return Hexagon::JMP_c;
				1495
				1496	case Hexagon::JMP_cdnNotPt:
				1497	return Hexagon::JMP_cNot;
				1498
				1499	case Hexagon::JMPR_cdnPt_V3:
				1500	return Hexagon::JMPR_cPt;
				1501
				1502	case Hexagon::JMPR_cdnNotPt_V3:
				1503	return Hexagon::JMPR_cNotPt;
				1504
				1505	// Load double word
				1506
				1507	case Hexagon::LDrid_cdnPt :
				1508	return Hexagon::LDrid_cPt;
				1509
				1510	case Hexagon::LDrid_cdnNotPt :
				1511	return Hexagon::LDrid_cNotPt;
				1512
				1513	case Hexagon::LDrid_indexed_cdnPt :
				1514	return Hexagon::LDrid_indexed_cPt;
				1515
				1516	case Hexagon::LDrid_indexed_cdnNotPt :
				1517	return Hexagon::LDrid_indexed_cNotPt;
				1518
				1519	case Hexagon::POST_LDrid_cdnPt_V4 :
				1520	return Hexagon::POST_LDrid_cPt;
				1521
				1522	case Hexagon::POST_LDrid_cdnNotPt_V4 :
				1523	return Hexagon::POST_LDrid_cNotPt;
				1524
				1525	// Load word
				1526
				1527	case Hexagon::LDriw_cdnPt :
				1528	return Hexagon::LDriw_cPt;
				1529
				1530	case Hexagon::LDriw_cdnNotPt :
				1531	return Hexagon::LDriw_cNotPt;
				1532
				1533	case Hexagon::LDriw_indexed_cdnPt :
				1534	return Hexagon::LDriw_indexed_cPt;
				1535
				1536	case Hexagon::LDriw_indexed_cdnNotPt :
				1537	return Hexagon::LDriw_indexed_cNotPt;
				1538
				1539	case Hexagon::POST_LDriw_cdnPt_V4 :
				1540	return Hexagon::POST_LDriw_cPt;
				1541
				1542	case Hexagon::POST_LDriw_cdnNotPt_V4 :
				1543	return Hexagon::POST_LDriw_cNotPt;
				1544
				1545	// Load half
				1546
				1547	case Hexagon::LDrih_cdnPt :
				1548	return Hexagon::LDrih_cPt;
				1549
				1550	case Hexagon::LDrih_cdnNotPt :
				1551	return Hexagon::LDrih_cNotPt;
				1552
				1553	case Hexagon::LDrih_indexed_cdnPt :
				1554	return Hexagon::LDrih_indexed_cPt;
				1555
				1556	case Hexagon::LDrih_indexed_cdnNotPt :
				1557	return Hexagon::LDrih_indexed_cNotPt;
				1558
				1559	case Hexagon::POST_LDrih_cdnPt_V4 :
				1560	return Hexagon::POST_LDrih_cPt;
				1561
				1562	case Hexagon::POST_LDrih_cdnNotPt_V4 :
				1563	return Hexagon::POST_LDrih_cNotPt;
				1564
				1565	// Load byte
				1566
				1567	case Hexagon::LDrib_cdnPt :
				1568	return Hexagon::LDrib_cPt;
				1569
				1570	case Hexagon::LDrib_cdnNotPt :
				1571	return Hexagon::LDrib_cNotPt;
				1572
				1573	case Hexagon::LDrib_indexed_cdnPt :
				1574	return Hexagon::LDrib_indexed_cPt;
				1575
				1576	case Hexagon::LDrib_indexed_cdnNotPt :
				1577	return Hexagon::LDrib_indexed_cNotPt;
				1578
				1579	case Hexagon::POST_LDrib_cdnPt_V4 :
				1580	return Hexagon::POST_LDrib_cPt;
				1581
				1582	case Hexagon::POST_LDrib_cdnNotPt_V4 :
				1583	return Hexagon::POST_LDrib_cNotPt;
				1584
				1585	// Load unsigned half
				1586
				1587	case Hexagon::LDriuh_cdnPt :
				1588	return Hexagon::LDriuh_cPt;
				1589
				1590	case Hexagon::LDriuh_cdnNotPt :
				1591	return Hexagon::LDriuh_cNotPt;
				1592
				1593	case Hexagon::LDriuh_indexed_cdnPt :
				1594	return Hexagon::LDriuh_indexed_cPt;
				1595
				1596	case Hexagon::LDriuh_indexed_cdnNotPt :
				1597	return Hexagon::LDriuh_indexed_cNotPt;
				1598
				1599	case Hexagon::POST_LDriuh_cdnPt_V4 :
				1600	return Hexagon::POST_LDriuh_cPt;
				1601
				1602	case Hexagon::POST_LDriuh_cdnNotPt_V4 :
				1603	return Hexagon::POST_LDriuh_cNotPt;
				1604
				1605	// Load unsigned byte
				1606	case Hexagon::LDriub_cdnPt :
				1607	return Hexagon::LDriub_cPt;
				1608
				1609	case Hexagon::LDriub_cdnNotPt :
				1610	return Hexagon::LDriub_cNotPt;
				1611
				1612	case Hexagon::LDriub_indexed_cdnPt :
				1613	return Hexagon::LDriub_indexed_cPt;
				1614
				1615	case Hexagon::LDriub_indexed_cdnNotPt :
				1616	return Hexagon::LDriub_indexed_cNotPt;
				1617
				1618	case Hexagon::POST_LDriub_cdnPt_V4 :
				1619	return Hexagon::POST_LDriub_cPt;
				1620
				1621	case Hexagon::POST_LDriub_cdnNotPt_V4 :
				1622	return Hexagon::POST_LDriub_cNotPt;
				1623
				1624	// V4 indexed+scaled Load
				1625
				1626	case Hexagon::LDrid_indexed_cdnPt_V4 :
				1627	return Hexagon::LDrid_indexed_cPt_V4;
				1628
				1629	case Hexagon::LDrid_indexed_cdnNotPt_V4 :
				1630	return Hexagon::LDrid_indexed_cNotPt_V4;
				1631
				1632	case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
				1633	return Hexagon::LDrid_indexed_shl_cPt_V4;
				1634
				1635	case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
				1636	return Hexagon::LDrid_indexed_shl_cNotPt_V4;
				1637
				1638	case Hexagon::LDrib_indexed_cdnPt_V4 :
				1639	return Hexagon::LDrib_indexed_cPt_V4;
				1640
				1641	case Hexagon::LDrib_indexed_cdnNotPt_V4 :
				1642	return Hexagon::LDrib_indexed_cNotPt_V4;
				1643
				1644	case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
				1645	return Hexagon::LDrib_indexed_shl_cPt_V4;
				1646
				1647	case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
				1648	return Hexagon::LDrib_indexed_shl_cNotPt_V4;
				1649
				1650	case Hexagon::LDriub_indexed_cdnPt_V4 :
				1651	return Hexagon::LDriub_indexed_cPt_V4;
				1652
				1653	case Hexagon::LDriub_indexed_cdnNotPt_V4 :
				1654	return Hexagon::LDriub_indexed_cNotPt_V4;
				1655
				1656	case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
				1657	return Hexagon::LDriub_indexed_shl_cPt_V4;
				1658
				1659	case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
				1660	return Hexagon::LDriub_indexed_shl_cNotPt_V4;
				1661
				1662	case Hexagon::LDrih_indexed_cdnPt_V4 :
				1663	return Hexagon::LDrih_indexed_cPt_V4;
				1664
				1665	case Hexagon::LDrih_indexed_cdnNotPt_V4 :
				1666	return Hexagon::LDrih_indexed_cNotPt_V4;
				1667
				1668	case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
				1669	return Hexagon::LDrih_indexed_shl_cPt_V4;
				1670
				1671	case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
				1672	return Hexagon::LDrih_indexed_shl_cNotPt_V4;
				1673
				1674	case Hexagon::LDriuh_indexed_cdnPt_V4 :
				1675	return Hexagon::LDriuh_indexed_cPt_V4;
				1676
				1677	case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
				1678	return Hexagon::LDriuh_indexed_cNotPt_V4;
				1679
				1680	case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
				1681	return Hexagon::LDriuh_indexed_shl_cPt_V4;
				1682
				1683	case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
				1684	return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
				1685
				1686	case Hexagon::LDriw_indexed_cdnPt_V4 :
				1687	return Hexagon::LDriw_indexed_cPt_V4;
				1688
				1689	case Hexagon::LDriw_indexed_cdnNotPt_V4 :
				1690	return Hexagon::LDriw_indexed_cNotPt_V4;
				1691
				1692	case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
				1693	return Hexagon::LDriw_indexed_shl_cPt_V4;
				1694
				1695	case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
				1696	return Hexagon::LDriw_indexed_shl_cNotPt_V4;
				1697
				1698	// V4 global address load
				1699
				1700	case Hexagon::LDd_GP_cdnPt_V4:
				1701	return Hexagon::LDd_GP_cPt_V4;
				1702
				1703	case Hexagon::LDd_GP_cdnNotPt_V4:
				1704	return Hexagon::LDd_GP_cNotPt_V4;
				1705
				1706	case Hexagon::LDb_GP_cdnPt_V4:
				1707	return Hexagon::LDb_GP_cPt_V4;
				1708
				1709	case Hexagon::LDb_GP_cdnNotPt_V4:
				1710	return Hexagon::LDb_GP_cNotPt_V4;
				1711
				1712	case Hexagon::LDub_GP_cdnPt_V4:
				1713	return Hexagon::LDub_GP_cPt_V4;
				1714
				1715	case Hexagon::LDub_GP_cdnNotPt_V4:
				1716	return Hexagon::LDub_GP_cNotPt_V4;
				1717
				1718	case Hexagon::LDh_GP_cdnPt_V4:
				1719	return Hexagon::LDh_GP_cPt_V4;
				1720
				1721	case Hexagon::LDh_GP_cdnNotPt_V4:
				1722	return Hexagon::LDh_GP_cNotPt_V4;
				1723
				1724	case Hexagon::LDuh_GP_cdnPt_V4:
				1725	return Hexagon::LDuh_GP_cPt_V4;
				1726
				1727	case Hexagon::LDuh_GP_cdnNotPt_V4:
				1728	return Hexagon::LDuh_GP_cNotPt_V4;
				1729
				1730	case Hexagon::LDw_GP_cdnPt_V4:
				1731	return Hexagon::LDw_GP_cPt_V4;
				1732
				1733	case Hexagon::LDw_GP_cdnNotPt_V4:
				1734	return Hexagon::LDw_GP_cNotPt_V4;
				1735
				1736	case Hexagon::LDrid_GP_cdnPt_V4:
				1737	return Hexagon::LDrid_GP_cPt_V4;
				1738
				1739	case Hexagon::LDrid_GP_cdnNotPt_V4:
				1740	return Hexagon::LDrid_GP_cNotPt_V4;
				1741
				1742	case Hexagon::LDrib_GP_cdnPt_V4:
				1743	return Hexagon::LDrib_GP_cPt_V4;
				1744
				1745	case Hexagon::LDrib_GP_cdnNotPt_V4:
				1746	return Hexagon::LDrib_GP_cNotPt_V4;
				1747
				1748	case Hexagon::LDriub_GP_cdnPt_V4:
				1749	return Hexagon::LDriub_GP_cPt_V4;
				1750
				1751	case Hexagon::LDriub_GP_cdnNotPt_V4:
				1752	return Hexagon::LDriub_GP_cNotPt_V4;
				1753
				1754	case Hexagon::LDrih_GP_cdnPt_V4:
				1755	return Hexagon::LDrih_GP_cPt_V4;
				1756
				1757	case Hexagon::LDrih_GP_cdnNotPt_V4:
				1758	return Hexagon::LDrih_GP_cNotPt_V4;
				1759
				1760	case Hexagon::LDriuh_GP_cdnPt_V4:
				1761	return Hexagon::LDriuh_GP_cPt_V4;
				1762
				1763	case Hexagon::LDriuh_GP_cdnNotPt_V4:
				1764	return Hexagon::LDriuh_GP_cNotPt_V4;
				1765
				1766	case Hexagon::LDriw_GP_cdnPt_V4:
				1767	return Hexagon::LDriw_GP_cPt_V4;
				1768
				1769	case Hexagon::LDriw_GP_cdnNotPt_V4:
				1770	return Hexagon::LDriw_GP_cNotPt_V4;
				1771
				1772	// Conditional add
				1773
				1774	case Hexagon::ADD_ri_cdnPt :
				1775	return Hexagon::ADD_ri_cPt;
				1776	case Hexagon::ADD_ri_cdnNotPt :
				1777	return Hexagon::ADD_ri_cNotPt;
				1778
				1779	case Hexagon::ADD_rr_cdnPt :
				1780	return Hexagon::ADD_rr_cPt;
				1781	case Hexagon::ADD_rr_cdnNotPt:
				1782	return Hexagon::ADD_rr_cNotPt;
				1783
				1784	// Conditional logical Operations
				1785
				1786	case Hexagon::XOR_rr_cdnPt :
				1787	return Hexagon::XOR_rr_cPt;
				1788	case Hexagon::XOR_rr_cdnNotPt :
				1789	return Hexagon::XOR_rr_cNotPt;
				1790
				1791	case Hexagon::AND_rr_cdnPt :
				1792	return Hexagon::AND_rr_cPt;
				1793	case Hexagon::AND_rr_cdnNotPt :
				1794	return Hexagon::AND_rr_cNotPt;
				1795
				1796	case Hexagon::OR_rr_cdnPt :
				1797	return Hexagon::OR_rr_cPt;
				1798	case Hexagon::OR_rr_cdnNotPt :
				1799	return Hexagon::OR_rr_cNotPt;
				1800
				1801	// Conditional Subtract
				1802
				1803	case Hexagon::SUB_rr_cdnPt :
				1804	return Hexagon::SUB_rr_cPt;
				1805	case Hexagon::SUB_rr_cdnNotPt :
				1806	return Hexagon::SUB_rr_cNotPt;
				1807
				1808	// Conditional combine
				1809
				1810	case Hexagon::COMBINE_rr_cdnPt :
				1811	return Hexagon::COMBINE_rr_cPt;
				1812	case Hexagon::COMBINE_rr_cdnNotPt :
				1813	return Hexagon::COMBINE_rr_cNotPt;
				1814
				1815	// Conditional shift operations
				1816
				1817	case Hexagon::ASLH_cdnPt_V4 :
				1818	return Hexagon::ASLH_cPt_V4;
				1819	case Hexagon::ASLH_cdnNotPt_V4 :
				1820	return Hexagon::ASLH_cNotPt_V4;
				1821
				1822	case Hexagon::ASRH_cdnPt_V4 :
				1823	return Hexagon::ASRH_cPt_V4;
				1824	case Hexagon::ASRH_cdnNotPt_V4 :
				1825	return Hexagon::ASRH_cNotPt_V4;
				1826
				1827	case Hexagon::SXTB_cdnPt_V4 :
				1828	return Hexagon::SXTB_cPt_V4;
				1829	case Hexagon::SXTB_cdnNotPt_V4 :
				1830	return Hexagon::SXTB_cNotPt_V4;
				1831
				1832	case Hexagon::SXTH_cdnPt_V4 :
				1833	return Hexagon::SXTH_cPt_V4;
				1834	case Hexagon::SXTH_cdnNotPt_V4 :
				1835	return Hexagon::SXTH_cNotPt_V4;
				1836
				1837	case Hexagon::ZXTB_cdnPt_V4 :
				1838	return Hexagon::ZXTB_cPt_V4;
				1839	case Hexagon::ZXTB_cdnNotPt_V4 :
				1840	return Hexagon::ZXTB_cNotPt_V4;
				1841
				1842	case Hexagon::ZXTH_cdnPt_V4 :
				1843	return Hexagon::ZXTH_cPt_V4;
				1844	case Hexagon::ZXTH_cdnNotPt_V4 :
				1845	return Hexagon::ZXTH_cNotPt_V4;
				1846
				1847	// Store byte
				1848
				1849	case Hexagon::STrib_imm_cdnPt_V4 :
				1850	return Hexagon::STrib_imm_cPt_V4;
				1851
				1852	case Hexagon::STrib_imm_cdnNotPt_V4 :
				1853	return Hexagon::STrib_imm_cNotPt_V4;
				1854
				1855	case Hexagon::STrib_cdnPt_nv_V4 :
				1856	case Hexagon::STrib_cPt_nv_V4 :
				1857	case Hexagon::STrib_cdnPt_V4 :
				1858	return Hexagon::STrib_cPt;
				1859
				1860	case Hexagon::STrib_cdnNotPt_nv_V4 :
				1861	case Hexagon::STrib_cNotPt_nv_V4 :
				1862	case Hexagon::STrib_cdnNotPt_V4 :
				1863	return Hexagon::STrib_cNotPt;
				1864
				1865	case Hexagon::STrib_indexed_cdnPt_V4 :
				1866	case Hexagon::STrib_indexed_cPt_nv_V4 :
				1867	case Hexagon::STrib_indexed_cdnPt_nv_V4 :
				1868	return Hexagon::STrib_indexed_cPt;
				1869
				1870	case Hexagon::STrib_indexed_cdnNotPt_V4 :
				1871	case Hexagon::STrib_indexed_cNotPt_nv_V4 :
				1872	case Hexagon::STrib_indexed_cdnNotPt_nv_V4 :
				1873	return Hexagon::STrib_indexed_cNotPt;
				1874
				1875	case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
				1876	case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
				1877	case Hexagon::STrib_indexed_shl_cdnPt_V4 :
				1878	return Hexagon::STrib_indexed_shl_cPt_V4;
				1879
				1880	case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
				1881	case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
				1882	case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
				1883	return Hexagon::STrib_indexed_shl_cNotPt_V4;
				1884
				1885	case Hexagon::POST_STbri_cdnPt_nv_V4 :
				1886	case Hexagon::POST_STbri_cPt_nv_V4 :
				1887	case Hexagon::POST_STbri_cdnPt_V4 :
				1888	return Hexagon::POST_STbri_cPt;
				1889
				1890	case Hexagon::POST_STbri_cdnNotPt_nv_V4 :
				1891	case Hexagon::POST_STbri_cNotPt_nv_V4:
				1892	case Hexagon::POST_STbri_cdnNotPt_V4 :
				1893	return Hexagon::POST_STbri_cNotPt;
				1894
				1895	case Hexagon::STb_GP_cdnPt_nv_V4:
				1896	case Hexagon::STb_GP_cdnPt_V4:
				1897	case Hexagon::STb_GP_cPt_nv_V4:
				1898	return Hexagon::STb_GP_cPt_V4;
				1899
				1900	case Hexagon::STb_GP_cdnNotPt_nv_V4:
				1901	case Hexagon::STb_GP_cdnNotPt_V4:
				1902	case Hexagon::STb_GP_cNotPt_nv_V4:
				1903	return Hexagon::STb_GP_cNotPt_V4;
				1904
				1905	case Hexagon::STrib_GP_cdnPt_nv_V4:
				1906	case Hexagon::STrib_GP_cdnPt_V4:
				1907	case Hexagon::STrib_GP_cPt_nv_V4:
				1908	return Hexagon::STrib_GP_cPt_V4;
				1909
				1910	case Hexagon::STrib_GP_cdnNotPt_nv_V4:
				1911	case Hexagon::STrib_GP_cdnNotPt_V4:
				1912	case Hexagon::STrib_GP_cNotPt_nv_V4:
				1913	return Hexagon::STrib_GP_cNotPt_V4;
				1914
				1915	// Store new-value byte - unconditional
				1916	case Hexagon::STrib_nv_V4:
				1917	return Hexagon::STrib;
				1918
				1919	case Hexagon::STrib_indexed_nv_V4:
				1920	return Hexagon::STrib_indexed;
				1921
				1922	case Hexagon::STrib_indexed_shl_nv_V4:
				1923	return Hexagon::STrib_indexed_shl_V4;
				1924
				1925	case Hexagon::STrib_shl_nv_V4:
				1926	return Hexagon::STrib_shl_V4;
				1927
				1928	case Hexagon::STrib_GP_nv_V4:
				1929	return Hexagon::STrib_GP_V4;
				1930
				1931	case Hexagon::STb_GP_nv_V4:
				1932	return Hexagon::STb_GP_V4;
				1933
				1934	case Hexagon::POST_STbri_nv_V4:
				1935	return Hexagon::POST_STbri;
				1936
				1937	// Store halfword
				1938	case Hexagon::STrih_imm_cdnPt_V4 :
				1939	return Hexagon::STrih_imm_cPt_V4;
				1940
				1941	case Hexagon::STrih_imm_cdnNotPt_V4 :
				1942	return Hexagon::STrih_imm_cNotPt_V4;
				1943
				1944	case Hexagon::STrih_cdnPt_nv_V4 :
				1945	case Hexagon::STrih_cPt_nv_V4 :
				1946	case Hexagon::STrih_cdnPt_V4 :
				1947	return Hexagon::STrih_cPt;
				1948
				1949	case Hexagon::STrih_cdnNotPt_nv_V4 :
				1950	case Hexagon::STrih_cNotPt_nv_V4 :
				1951	case Hexagon::STrih_cdnNotPt_V4 :
				1952	return Hexagon::STrih_cNotPt;
				1953
				1954	case Hexagon::STrih_indexed_cdnPt_nv_V4:
				1955	case Hexagon::STrih_indexed_cPt_nv_V4 :
				1956	case Hexagon::STrih_indexed_cdnPt_V4 :
				1957	return Hexagon::STrih_indexed_cPt;
				1958
				1959	case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
				1960	case Hexagon::STrih_indexed_cNotPt_nv_V4 :
				1961	case Hexagon::STrih_indexed_cdnNotPt_V4 :
				1962	return Hexagon::STrih_indexed_cNotPt;
				1963
				1964	case Hexagon::STrih_indexed_shl_cdnPt_nv_V4 :
				1965	case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
				1966	case Hexagon::STrih_indexed_shl_cdnPt_V4 :
				1967	return Hexagon::STrih_indexed_shl_cPt_V4;
				1968
				1969	case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4 :
				1970	case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
				1971	case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
				1972	return Hexagon::STrih_indexed_shl_cNotPt_V4;
				1973
				1974	case Hexagon::POST_SThri_cdnPt_nv_V4 :
				1975	case Hexagon::POST_SThri_cPt_nv_V4 :
				1976	case Hexagon::POST_SThri_cdnPt_V4 :
				1977	return Hexagon::POST_SThri_cPt;
				1978
				1979	case Hexagon::POST_SThri_cdnNotPt_nv_V4 :
				1980	case Hexagon::POST_SThri_cNotPt_nv_V4 :
				1981	case Hexagon::POST_SThri_cdnNotPt_V4 :
				1982	return Hexagon::POST_SThri_cNotPt;
				1983
				1984	case Hexagon::STh_GP_cdnPt_nv_V4:
				1985	case Hexagon::STh_GP_cdnPt_V4:
				1986	case Hexagon::STh_GP_cPt_nv_V4:
				1987	return Hexagon::STh_GP_cPt_V4;
				1988
				1989	case Hexagon::STh_GP_cdnNotPt_nv_V4:
				1990	case Hexagon::STh_GP_cdnNotPt_V4:
				1991	case Hexagon::STh_GP_cNotPt_nv_V4:
				1992	return Hexagon::STh_GP_cNotPt_V4;
				1993
				1994	case Hexagon::STrih_GP_cdnPt_nv_V4:
				1995	case Hexagon::STrih_GP_cdnPt_V4:
				1996	case Hexagon::STrih_GP_cPt_nv_V4:
				1997	return Hexagon::STrih_GP_cPt_V4;
				1998
				1999	case Hexagon::STrih_GP_cdnNotPt_nv_V4:
				2000	case Hexagon::STrih_GP_cdnNotPt_V4:
				2001	case Hexagon::STrih_GP_cNotPt_nv_V4:
				2002	return Hexagon::STrih_GP_cNotPt_V4;
				2003
				2004	// Store new-value halfword - unconditional
				2005
				2006	case Hexagon::STrih_nv_V4:
				2007	return Hexagon::STrih;
				2008
				2009	case Hexagon::STrih_indexed_nv_V4:
				2010	return Hexagon::STrih_indexed;
				2011
				2012	case Hexagon::STrih_indexed_shl_nv_V4:
				2013	return Hexagon::STrih_indexed_shl_V4;
				2014
				2015	case Hexagon::STrih_shl_nv_V4:
				2016	return Hexagon::STrih_shl_V4;
				2017
				2018	case Hexagon::STrih_GP_nv_V4:
				2019	return Hexagon::STrih_GP_V4;
				2020
				2021	case Hexagon::STh_GP_nv_V4:
				2022	return Hexagon::STh_GP_V4;
				2023
				2024	case Hexagon::POST_SThri_nv_V4:
				2025	return Hexagon::POST_SThri;
				2026
				2027	// Store word
				2028
				2029	case Hexagon::STriw_imm_cdnPt_V4 :
				2030	return Hexagon::STriw_imm_cPt_V4;
				2031
				2032	case Hexagon::STriw_imm_cdnNotPt_V4 :
				2033	return Hexagon::STriw_imm_cNotPt_V4;
				2034
				2035	case Hexagon::STriw_cdnPt_nv_V4 :
				2036	case Hexagon::STriw_cPt_nv_V4 :
				2037	case Hexagon::STriw_cdnPt_V4 :
				2038	return Hexagon::STriw_cPt;
				2039
				2040	case Hexagon::STriw_cdnNotPt_nv_V4 :
				2041	case Hexagon::STriw_cNotPt_nv_V4 :
				2042	case Hexagon::STriw_cdnNotPt_V4 :
				2043	return Hexagon::STriw_cNotPt;
				2044
				2045	case Hexagon::STriw_indexed_cdnPt_nv_V4 :
				2046	case Hexagon::STriw_indexed_cPt_nv_V4 :
				2047	case Hexagon::STriw_indexed_cdnPt_V4 :
				2048	return Hexagon::STriw_indexed_cPt;
				2049
				2050	case Hexagon::STriw_indexed_cdnNotPt_nv_V4 :
				2051	case Hexagon::STriw_indexed_cNotPt_nv_V4 :
				2052	case Hexagon::STriw_indexed_cdnNotPt_V4 :
				2053	return Hexagon::STriw_indexed_cNotPt;
				2054
				2055	case Hexagon::STriw_indexed_shl_cdnPt_nv_V4 :
				2056	case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
				2057	case Hexagon::STriw_indexed_shl_cdnPt_V4 :
				2058	return Hexagon::STriw_indexed_shl_cPt_V4;
				2059
				2060	case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4 :
				2061	case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
				2062	case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
				2063	return Hexagon::STriw_indexed_shl_cNotPt_V4;
				2064
				2065	case Hexagon::POST_STwri_cdnPt_nv_V4 :
				2066	case Hexagon::POST_STwri_cPt_nv_V4 :
				2067	case Hexagon::POST_STwri_cdnPt_V4 :
				2068	return Hexagon::POST_STwri_cPt;
				2069
				2070	case Hexagon::POST_STwri_cdnNotPt_nv_V4 :
				2071	case Hexagon::POST_STwri_cNotPt_nv_V4 :
				2072	case Hexagon::POST_STwri_cdnNotPt_V4 :
				2073	return Hexagon::POST_STwri_cNotPt;
				2074
				2075	case Hexagon::STw_GP_cdnPt_nv_V4:
				2076	case Hexagon::STw_GP_cdnPt_V4:
				2077	case Hexagon::STw_GP_cPt_nv_V4:
				2078	return Hexagon::STw_GP_cPt_V4;
				2079
				2080	case Hexagon::STw_GP_cdnNotPt_nv_V4:
				2081	case Hexagon::STw_GP_cdnNotPt_V4:
				2082	case Hexagon::STw_GP_cNotPt_nv_V4:
				2083	return Hexagon::STw_GP_cNotPt_V4;
				2084
				2085	case Hexagon::STriw_GP_cdnPt_nv_V4:
				2086	case Hexagon::STriw_GP_cdnPt_V4:
				2087	case Hexagon::STriw_GP_cPt_nv_V4:
				2088	return Hexagon::STriw_GP_cPt_V4;
				2089
				2090	case Hexagon::STriw_GP_cdnNotPt_nv_V4:
				2091	case Hexagon::STriw_GP_cdnNotPt_V4:
				2092	case Hexagon::STriw_GP_cNotPt_nv_V4:
				2093	return Hexagon::STriw_GP_cNotPt_V4;
				2094
				2095	// Store new-value word - unconditional
				2096
				2097	case Hexagon::STriw_nv_V4:
				2098	return Hexagon::STriw;
				2099
				2100	case Hexagon::STriw_indexed_nv_V4:
				2101	return Hexagon::STriw_indexed;
				2102
				2103	case Hexagon::STriw_indexed_shl_nv_V4:
				2104	return Hexagon::STriw_indexed_shl_V4;
				2105
				2106	case Hexagon::STriw_shl_nv_V4:
				2107	return Hexagon::STriw_shl_V4;
				2108
				2109	case Hexagon::STriw_GP_nv_V4:
				2110	return Hexagon::STriw_GP_V4;
				2111
				2112	case Hexagon::STw_GP_nv_V4:
				2113	return Hexagon::STw_GP_V4;
				2114
				2115	case Hexagon::POST_STwri_nv_V4:
				2116	return Hexagon::POST_STwri;
				2117
				2118	// Store doubleword
				2119
				2120	case Hexagon::STrid_cdnPt_V4 :
				2121	return Hexagon::STrid_cPt;
				2122
				2123	case Hexagon::STrid_cdnNotPt_V4 :
				2124	return Hexagon::STrid_cNotPt;
				2125
				2126	case Hexagon::STrid_indexed_cdnPt_V4 :
				2127	return Hexagon::STrid_indexed_cPt;
				2128
				2129	case Hexagon::STrid_indexed_cdnNotPt_V4 :
				2130	return Hexagon::STrid_indexed_cNotPt;
				2131
				2132	case Hexagon::STrid_indexed_shl_cdnPt_V4 :
				2133	return Hexagon::STrid_indexed_shl_cPt_V4;
				2134
				2135	case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
				2136	return Hexagon::STrid_indexed_shl_cNotPt_V4;
				2137
				2138	case Hexagon::POST_STdri_cdnPt_V4 :
				2139	return Hexagon::POST_STdri_cPt;
				2140
				2141	case Hexagon::POST_STdri_cdnNotPt_V4 :
				2142	return Hexagon::POST_STdri_cNotPt;
				2143
				2144	case Hexagon::STd_GP_cdnPt_V4 :
				2145	return Hexagon::STd_GP_cPt_V4;
				2146
				2147	case Hexagon::STd_GP_cdnNotPt_V4 :
				2148	return Hexagon::STd_GP_cNotPt_V4;
				2149
				2150	case Hexagon::STrid_GP_cdnPt_V4 :
				2151	return Hexagon::STrid_GP_cPt_V4;
				2152
				2153	case Hexagon::STrid_GP_cdnNotPt_V4 :
				2154	return Hexagon::STrid_GP_cNotPt_V4;
				2155	}
				2156	}
				2157
				2158	bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
				2159	const HexagonInstrInfo QII = (const HexagonInstrInfo ) TII;
				2160	int NewOpcode = GetDotOldOp(MI->getOpcode());
				2161	MI->setDesc(QII->get(NewOpcode));
				2162	return true;
				2163	}
				2164
				2165	// Returns true if an instruction is predicated on p0 and false if it's
				2166	// predicated on !p0.
				2167
				2168	static bool GetPredicateSense(MachineInstr* MI,
				2169	const HexagonInstrInfo *QII) {
				2170
				2171	switch (MI->getOpcode()) {
				2172	default: llvm_unreachable("Unknown predicate sense of the instruction");
				2173	case Hexagon::TFR_cPt:
				2174	case Hexagon::TFR_cdnPt:
				2175	case Hexagon::TFRI_cPt:
				2176	case Hexagon::TFRI_cdnPt:
				2177	case Hexagon::STrib_cPt :
				2178	case Hexagon::STrib_cdnPt_V4 :
				2179	case Hexagon::STrib_indexed_cPt :
				2180	case Hexagon::STrib_indexed_cdnPt_V4 :
				2181	case Hexagon::STrib_indexed_shl_cPt_V4 :
				2182	case Hexagon::STrib_indexed_shl_cdnPt_V4 :
				2183	case Hexagon::POST_STbri_cPt :
				2184	case Hexagon::POST_STbri_cdnPt_V4 :
				2185	case Hexagon::STrih_cPt :
				2186	case Hexagon::STrih_cdnPt_V4 :
				2187	case Hexagon::STrih_indexed_cPt :
				2188	case Hexagon::STrih_indexed_cdnPt_V4 :
				2189	case Hexagon::STrih_indexed_shl_cPt_V4 :
				2190	case Hexagon::STrih_indexed_shl_cdnPt_V4 :
				2191	case Hexagon::POST_SThri_cPt :
				2192	case Hexagon::POST_SThri_cdnPt_V4 :
				2193	case Hexagon::STriw_cPt :
				2194	case Hexagon::STriw_cdnPt_V4 :
				2195	case Hexagon::STriw_indexed_cPt :
				2196	case Hexagon::STriw_indexed_cdnPt_V4 :
				2197	case Hexagon::STriw_indexed_shl_cPt_V4 :
				2198	case Hexagon::STriw_indexed_shl_cdnPt_V4 :
				2199	case Hexagon::POST_STwri_cPt :
				2200	case Hexagon::POST_STwri_cdnPt_V4 :
				2201	case Hexagon::STrib_imm_cPt_V4 :
				2202	case Hexagon::STrib_imm_cdnPt_V4 :
				2203	case Hexagon::STrid_cPt :
				2204	case Hexagon::STrid_cdnPt_V4 :
				2205	case Hexagon::STrid_indexed_cPt :
				2206	case Hexagon::STrid_indexed_cdnPt_V4 :
				2207	case Hexagon::STrid_indexed_shl_cPt_V4 :
				2208	case Hexagon::STrid_indexed_shl_cdnPt_V4 :
				2209	case Hexagon::POST_STdri_cPt :
				2210	case Hexagon::POST_STdri_cdnPt_V4 :
				2211	case Hexagon::STrih_imm_cPt_V4 :
				2212	case Hexagon::STrih_imm_cdnPt_V4 :
				2213	case Hexagon::STriw_imm_cPt_V4 :
				2214	case Hexagon::STriw_imm_cdnPt_V4 :
				2215	case Hexagon::JMP_cdnPt :
				2216	case Hexagon::LDrid_cPt :
				2217	case Hexagon::LDrid_cdnPt :
				2218	case Hexagon::LDrid_indexed_cPt :
				2219	case Hexagon::LDrid_indexed_cdnPt :
				2220	case Hexagon::POST_LDrid_cPt :
				2221	case Hexagon::POST_LDrid_cdnPt_V4 :
				2222	case Hexagon::LDriw_cPt :
				2223	case Hexagon::LDriw_cdnPt :
				2224	case Hexagon::LDriw_indexed_cPt :
				2225	case Hexagon::LDriw_indexed_cdnPt :
				2226	case Hexagon::POST_LDriw_cPt :
				2227	case Hexagon::POST_LDriw_cdnPt_V4 :
				2228	case Hexagon::LDrih_cPt :
				2229	case Hexagon::LDrih_cdnPt :
				2230	case Hexagon::LDrih_indexed_cPt :
				2231	case Hexagon::LDrih_indexed_cdnPt :
				2232	case Hexagon::POST_LDrih_cPt :
				2233	case Hexagon::POST_LDrih_cdnPt_V4 :
				2234	case Hexagon::LDrib_cPt :
				2235	case Hexagon::LDrib_cdnPt :
				2236	case Hexagon::LDrib_indexed_cPt :
				2237	case Hexagon::LDrib_indexed_cdnPt :
				2238	case Hexagon::POST_LDrib_cPt :
				2239	case Hexagon::POST_LDrib_cdnPt_V4 :
				2240	case Hexagon::LDriuh_cPt :
				2241	case Hexagon::LDriuh_cdnPt :
				2242	case Hexagon::LDriuh_indexed_cPt :
				2243	case Hexagon::LDriuh_indexed_cdnPt :
				2244	case Hexagon::POST_LDriuh_cPt :
				2245	case Hexagon::POST_LDriuh_cdnPt_V4 :
				2246	case Hexagon::LDriub_cPt :
				2247	case Hexagon::LDriub_cdnPt :
				2248	case Hexagon::LDriub_indexed_cPt :
				2249	case Hexagon::LDriub_indexed_cdnPt :
				2250	case Hexagon::POST_LDriub_cPt :
				2251	case Hexagon::POST_LDriub_cdnPt_V4 :
				2252	case Hexagon::LDrid_indexed_cPt_V4 :
				2253	case Hexagon::LDrid_indexed_cdnPt_V4 :
				2254	case Hexagon::LDrid_indexed_shl_cPt_V4 :
				2255	case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
				2256	case Hexagon::LDrib_indexed_cPt_V4 :
				2257	case Hexagon::LDrib_indexed_cdnPt_V4 :
				2258	case Hexagon::LDrib_indexed_shl_cPt_V4 :
				2259	case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
				2260	case Hexagon::LDriub_indexed_cPt_V4 :
				2261	case Hexagon::LDriub_indexed_cdnPt_V4 :
				2262	case Hexagon::LDriub_indexed_shl_cPt_V4 :
				2263	case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
				2264	case Hexagon::LDrih_indexed_cPt_V4 :
				2265	case Hexagon::LDrih_indexed_cdnPt_V4 :
				2266	case Hexagon::LDrih_indexed_shl_cPt_V4 :
				2267	case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
				2268	case Hexagon::LDriuh_indexed_cPt_V4 :
				2269	case Hexagon::LDriuh_indexed_cdnPt_V4 :
				2270	case Hexagon::LDriuh_indexed_shl_cPt_V4 :
				2271	case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
				2272	case Hexagon::LDriw_indexed_cPt_V4 :
				2273	case Hexagon::LDriw_indexed_cdnPt_V4 :
				2274	case Hexagon::LDriw_indexed_shl_cPt_V4 :
				2275	case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
				2276	case Hexagon::ADD_ri_cPt :
				2277	case Hexagon::ADD_ri_cdnPt :
				2278	case Hexagon::ADD_rr_cPt :
				2279	case Hexagon::ADD_rr_cdnPt :
				2280	case Hexagon::XOR_rr_cPt :
				2281	case Hexagon::XOR_rr_cdnPt :
				2282	case Hexagon::AND_rr_cPt :
				2283	case Hexagon::AND_rr_cdnPt :
				2284	case Hexagon::OR_rr_cPt :
				2285	case Hexagon::OR_rr_cdnPt :
				2286	case Hexagon::SUB_rr_cPt :
				2287	case Hexagon::SUB_rr_cdnPt :
				2288	case Hexagon::COMBINE_rr_cPt :
				2289	case Hexagon::COMBINE_rr_cdnPt :
				2290	case Hexagon::ASLH_cPt_V4 :
				2291	case Hexagon::ASLH_cdnPt_V4 :
				2292	case Hexagon::ASRH_cPt_V4 :
				2293	case Hexagon::ASRH_cdnPt_V4 :
				2294	case Hexagon::SXTB_cPt_V4 :
				2295	case Hexagon::SXTB_cdnPt_V4 :
				2296	case Hexagon::SXTH_cPt_V4 :
				2297	case Hexagon::SXTH_cdnPt_V4 :
				2298	case Hexagon::ZXTB_cPt_V4 :
				2299	case Hexagon::ZXTB_cdnPt_V4 :
				2300	case Hexagon::ZXTH_cPt_V4 :
				2301	case Hexagon::ZXTH_cdnPt_V4 :
				2302	case Hexagon::LDrid_GP_cPt_V4 :
				2303	case Hexagon::LDrib_GP_cPt_V4 :
				2304	case Hexagon::LDriub_GP_cPt_V4 :
				2305	case Hexagon::LDrih_GP_cPt_V4 :
				2306	case Hexagon::LDriuh_GP_cPt_V4 :
				2307	case Hexagon::LDriw_GP_cPt_V4 :
				2308	case Hexagon::LDd_GP_cPt_V4 :
				2309	case Hexagon::LDb_GP_cPt_V4 :
				2310	case Hexagon::LDub_GP_cPt_V4 :
				2311	case Hexagon::LDh_GP_cPt_V4 :
				2312	case Hexagon::LDuh_GP_cPt_V4 :
				2313	case Hexagon::LDw_GP_cPt_V4 :
				2314	case Hexagon::STrid_GP_cPt_V4 :
				2315	case Hexagon::STrib_GP_cPt_V4 :
				2316	case Hexagon::STrih_GP_cPt_V4 :
				2317	case Hexagon::STriw_GP_cPt_V4 :
				2318	case Hexagon::STd_GP_cPt_V4 :
				2319	case Hexagon::STb_GP_cPt_V4 :
				2320	case Hexagon::STh_GP_cPt_V4 :
				2321	case Hexagon::STw_GP_cPt_V4 :
				2322	case Hexagon::LDrid_GP_cdnPt_V4 :
				2323	case Hexagon::LDrib_GP_cdnPt_V4 :
				2324	case Hexagon::LDriub_GP_cdnPt_V4 :
				2325	case Hexagon::LDrih_GP_cdnPt_V4 :
				2326	case Hexagon::LDriuh_GP_cdnPt_V4 :
				2327	case Hexagon::LDriw_GP_cdnPt_V4 :
				2328	case Hexagon::LDd_GP_cdnPt_V4 :
				2329	case Hexagon::LDb_GP_cdnPt_V4 :
				2330	case Hexagon::LDub_GP_cdnPt_V4 :
				2331	case Hexagon::LDh_GP_cdnPt_V4 :
				2332	case Hexagon::LDuh_GP_cdnPt_V4 :
				2333	case Hexagon::LDw_GP_cdnPt_V4 :
				2334	case Hexagon::STrid_GP_cdnPt_V4 :
				2335	case Hexagon::STrib_GP_cdnPt_V4 :
				2336	case Hexagon::STrih_GP_cdnPt_V4 :
				2337	case Hexagon::STriw_GP_cdnPt_V4 :
				2338	case Hexagon::STd_GP_cdnPt_V4 :
				2339	case Hexagon::STb_GP_cdnPt_V4 :
				2340	case Hexagon::STh_GP_cdnPt_V4 :
				2341	case Hexagon::STw_GP_cdnPt_V4 :
				2342	return true;
				2343
				2344	case Hexagon::TFR_cNotPt:
				2345	case Hexagon::TFR_cdnNotPt:
				2346	case Hexagon::TFRI_cNotPt:
				2347	case Hexagon::TFRI_cdnNotPt:
				2348	case Hexagon::STrib_cNotPt :
				2349	case Hexagon::STrib_cdnNotPt_V4 :
				2350	case Hexagon::STrib_indexed_cNotPt :
				2351	case Hexagon::STrib_indexed_cdnNotPt_V4 :
				2352	case Hexagon::STrib_indexed_shl_cNotPt_V4 :
				2353	case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
				2354	case Hexagon::POST_STbri_cNotPt :
				2355	case Hexagon::POST_STbri_cdnNotPt_V4 :
				2356	case Hexagon::STrih_cNotPt :
				2357	case Hexagon::STrih_cdnNotPt_V4 :
				2358	case Hexagon::STrih_indexed_cNotPt :
				2359	case Hexagon::STrih_indexed_cdnNotPt_V4 :
				2360	case Hexagon::STrih_indexed_shl_cNotPt_V4 :
				2361	case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
				2362	case Hexagon::POST_SThri_cNotPt :
				2363	case Hexagon::POST_SThri_cdnNotPt_V4 :
				2364	case Hexagon::STriw_cNotPt :
				2365	case Hexagon::STriw_cdnNotPt_V4 :
				2366	case Hexagon::STriw_indexed_cNotPt :
				2367	case Hexagon::STriw_indexed_cdnNotPt_V4 :
				2368	case Hexagon::STriw_indexed_shl_cNotPt_V4 :
				2369	case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
				2370	case Hexagon::POST_STwri_cNotPt :
				2371	case Hexagon::POST_STwri_cdnNotPt_V4 :
				2372	case Hexagon::STrib_imm_cNotPt_V4 :
				2373	case Hexagon::STrib_imm_cdnNotPt_V4 :
				2374	case Hexagon::STrid_cNotPt :
				2375	case Hexagon::STrid_cdnNotPt_V4 :
				2376	case Hexagon::STrid_indexed_cdnNotPt_V4 :
				2377	case Hexagon::STrid_indexed_cNotPt :
				2378	case Hexagon::STrid_indexed_shl_cNotPt_V4 :
				2379	case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
				2380	case Hexagon::POST_STdri_cNotPt :
				2381	case Hexagon::POST_STdri_cdnNotPt_V4 :
				2382	case Hexagon::STrih_imm_cNotPt_V4 :
				2383	case Hexagon::STrih_imm_cdnNotPt_V4 :
				2384	case Hexagon::STriw_imm_cNotPt_V4 :
				2385	case Hexagon::STriw_imm_cdnNotPt_V4 :
				2386	case Hexagon::JMP_cdnNotPt :
				2387	case Hexagon::LDrid_cNotPt :
				2388	case Hexagon::LDrid_cdnNotPt :
				2389	case Hexagon::LDrid_indexed_cNotPt :
				2390	case Hexagon::LDrid_indexed_cdnNotPt :
				2391	case Hexagon::POST_LDrid_cNotPt :
				2392	case Hexagon::POST_LDrid_cdnNotPt_V4 :
				2393	case Hexagon::LDriw_cNotPt :
				2394	case Hexagon::LDriw_cdnNotPt :
				2395	case Hexagon::LDriw_indexed_cNotPt :
				2396	case Hexagon::LDriw_indexed_cdnNotPt :
				2397	case Hexagon::POST_LDriw_cNotPt :
				2398	case Hexagon::POST_LDriw_cdnNotPt_V4 :
				2399	case Hexagon::LDrih_cNotPt :
				2400	case Hexagon::LDrih_cdnNotPt :
				2401	case Hexagon::LDrih_indexed_cNotPt :
				2402	case Hexagon::LDrih_indexed_cdnNotPt :
				2403	case Hexagon::POST_LDrih_cNotPt :
				2404	case Hexagon::POST_LDrih_cdnNotPt_V4 :
				2405	case Hexagon::LDrib_cNotPt :
				2406	case Hexagon::LDrib_cdnNotPt :
				2407	case Hexagon::LDrib_indexed_cNotPt :
				2408	case Hexagon::LDrib_indexed_cdnNotPt :
				2409	case Hexagon::POST_LDrib_cNotPt :
				2410	case Hexagon::POST_LDrib_cdnNotPt_V4 :
				2411	case Hexagon::LDriuh_cNotPt :
				2412	case Hexagon::LDriuh_cdnNotPt :
				2413	case Hexagon::LDriuh_indexed_cNotPt :
				2414	case Hexagon::LDriuh_indexed_cdnNotPt :
				2415	case Hexagon::POST_LDriuh_cNotPt :
				2416	case Hexagon::POST_LDriuh_cdnNotPt_V4 :
				2417	case Hexagon::LDriub_cNotPt :
				2418	case Hexagon::LDriub_cdnNotPt :
				2419	case Hexagon::LDriub_indexed_cNotPt :
				2420	case Hexagon::LDriub_indexed_cdnNotPt :
				2421	case Hexagon::POST_LDriub_cNotPt :
				2422	case Hexagon::POST_LDriub_cdnNotPt_V4 :
				2423	case Hexagon::LDrid_indexed_cNotPt_V4 :
				2424	case Hexagon::LDrid_indexed_cdnNotPt_V4 :
				2425	case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
				2426	case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
				2427	case Hexagon::LDrib_indexed_cNotPt_V4 :
				2428	case Hexagon::LDrib_indexed_cdnNotPt_V4 :
				2429	case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
				2430	case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
				2431	case Hexagon::LDriub_indexed_cNotPt_V4 :
				2432	case Hexagon::LDriub_indexed_cdnNotPt_V4 :
				2433	case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
				2434	case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
				2435	case Hexagon::LDrih_indexed_cNotPt_V4 :
				2436	case Hexagon::LDrih_indexed_cdnNotPt_V4 :
				2437	case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
				2438	case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
				2439	case Hexagon::LDriuh_indexed_cNotPt_V4 :
				2440	case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
				2441	case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
				2442	case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
				2443	case Hexagon::LDriw_indexed_cNotPt_V4 :
				2444	case Hexagon::LDriw_indexed_cdnNotPt_V4 :
				2445	case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
				2446	case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
				2447	case Hexagon::ADD_ri_cNotPt :
				2448	case Hexagon::ADD_ri_cdnNotPt :
				2449	case Hexagon::ADD_rr_cNotPt :
				2450	case Hexagon::ADD_rr_cdnNotPt :
				2451	case Hexagon::XOR_rr_cNotPt :
				2452	case Hexagon::XOR_rr_cdnNotPt :
				2453	case Hexagon::AND_rr_cNotPt :
				2454	case Hexagon::AND_rr_cdnNotPt :
				2455	case Hexagon::OR_rr_cNotPt :
				2456	case Hexagon::OR_rr_cdnNotPt :
				2457	case Hexagon::SUB_rr_cNotPt :
				2458	case Hexagon::SUB_rr_cdnNotPt :
				2459	case Hexagon::COMBINE_rr_cNotPt :
				2460	case Hexagon::COMBINE_rr_cdnNotPt :
				2461	case Hexagon::ASLH_cNotPt_V4 :
				2462	case Hexagon::ASLH_cdnNotPt_V4 :
				2463	case Hexagon::ASRH_cNotPt_V4 :
				2464	case Hexagon::ASRH_cdnNotPt_V4 :
				2465	case Hexagon::SXTB_cNotPt_V4 :
				2466	case Hexagon::SXTB_cdnNotPt_V4 :
				2467	case Hexagon::SXTH_cNotPt_V4 :
				2468	case Hexagon::SXTH_cdnNotPt_V4 :
				2469	case Hexagon::ZXTB_cNotPt_V4 :
				2470	case Hexagon::ZXTB_cdnNotPt_V4 :
				2471	case Hexagon::ZXTH_cNotPt_V4 :
				2472	case Hexagon::ZXTH_cdnNotPt_V4 :
				2473
				2474	case Hexagon::LDrid_GP_cNotPt_V4 :
				2475	case Hexagon::LDrib_GP_cNotPt_V4 :
				2476	case Hexagon::LDriub_GP_cNotPt_V4 :
				2477	case Hexagon::LDrih_GP_cNotPt_V4 :
				2478	case Hexagon::LDriuh_GP_cNotPt_V4 :
				2479	case Hexagon::LDriw_GP_cNotPt_V4 :
				2480	case Hexagon::LDd_GP_cNotPt_V4 :
				2481	case Hexagon::LDb_GP_cNotPt_V4 :
				2482	case Hexagon::LDub_GP_cNotPt_V4 :
				2483	case Hexagon::LDh_GP_cNotPt_V4 :
				2484	case Hexagon::LDuh_GP_cNotPt_V4 :
				2485	case Hexagon::LDw_GP_cNotPt_V4 :
				2486	case Hexagon::STrid_GP_cNotPt_V4 :
				2487	case Hexagon::STrib_GP_cNotPt_V4 :
				2488	case Hexagon::STrih_GP_cNotPt_V4 :
				2489	case Hexagon::STriw_GP_cNotPt_V4 :
				2490	case Hexagon::STd_GP_cNotPt_V4 :
				2491	case Hexagon::STb_GP_cNotPt_V4 :
				2492	case Hexagon::STh_GP_cNotPt_V4 :
				2493	case Hexagon::STw_GP_cNotPt_V4 :
				2494	case Hexagon::LDrid_GP_cdnNotPt_V4 :
				2495	case Hexagon::LDrib_GP_cdnNotPt_V4 :
				2496	case Hexagon::LDriub_GP_cdnNotPt_V4 :
				2497	case Hexagon::LDrih_GP_cdnNotPt_V4 :
				2498	case Hexagon::LDriuh_GP_cdnNotPt_V4 :
				2499	case Hexagon::LDriw_GP_cdnNotPt_V4 :
				2500	case Hexagon::LDd_GP_cdnNotPt_V4 :
				2501	case Hexagon::LDb_GP_cdnNotPt_V4 :
				2502	case Hexagon::LDub_GP_cdnNotPt_V4 :
				2503	case Hexagon::LDh_GP_cdnNotPt_V4 :
				2504	case Hexagon::LDuh_GP_cdnNotPt_V4 :
				2505	case Hexagon::LDw_GP_cdnNotPt_V4 :
				2506	case Hexagon::STrid_GP_cdnNotPt_V4 :
				2507	case Hexagon::STrib_GP_cdnNotPt_V4 :
				2508	case Hexagon::STrih_GP_cdnNotPt_V4 :
				2509	case Hexagon::STriw_GP_cdnNotPt_V4 :
				2510	case Hexagon::STd_GP_cdnNotPt_V4 :
				2511	case Hexagon::STb_GP_cdnNotPt_V4 :
				2512	case Hexagon::STh_GP_cdnNotPt_V4 :
				2513	case Hexagon::STw_GP_cdnNotPt_V4 :
				2514	return false;
				2515	}
				2516	// return some value to avoid compiler warning
				2517	return false;
				2518	}
				2519
				2520	bool HexagonPacketizerList::isDotNewInst(MachineInstr* MI) {
				2521	if (isNewValueInst(MI))
				2522	return true;
				2523
				2524	switch (MI->getOpcode()) {
				2525	case Hexagon::TFR_cdnNotPt:
				2526	case Hexagon::TFR_cdnPt:
				2527	case Hexagon::TFRI_cdnNotPt:
				2528	case Hexagon::TFRI_cdnPt:
				2529	case Hexagon::LDrid_cdnPt :
				2530	case Hexagon::LDrid_cdnNotPt :
				2531	case Hexagon::LDrid_indexed_cdnPt :
				2532	case Hexagon::LDrid_indexed_cdnNotPt :
				2533	case Hexagon::POST_LDrid_cdnPt_V4 :
				2534	case Hexagon::POST_LDrid_cdnNotPt_V4 :
				2535	case Hexagon::LDriw_cdnPt :
				2536	case Hexagon::LDriw_cdnNotPt :
				2537	case Hexagon::LDriw_indexed_cdnPt :
				2538	case Hexagon::LDriw_indexed_cdnNotPt :
				2539	case Hexagon::POST_LDriw_cdnPt_V4 :
				2540	case Hexagon::POST_LDriw_cdnNotPt_V4 :
				2541	case Hexagon::LDrih_cdnPt :
				2542	case Hexagon::LDrih_cdnNotPt :
				2543	case Hexagon::LDrih_indexed_cdnPt :
				2544	case Hexagon::LDrih_indexed_cdnNotPt :
				2545	case Hexagon::POST_LDrih_cdnPt_V4 :
				2546	case Hexagon::POST_LDrih_cdnNotPt_V4 :
				2547	case Hexagon::LDrib_cdnPt :
				2548	case Hexagon::LDrib_cdnNotPt :
				2549	case Hexagon::LDrib_indexed_cdnPt :
				2550	case Hexagon::LDrib_indexed_cdnNotPt :
				2551	case Hexagon::POST_LDrib_cdnPt_V4 :
				2552	case Hexagon::POST_LDrib_cdnNotPt_V4 :
				2553	case Hexagon::LDriuh_cdnPt :
				2554	case Hexagon::LDriuh_cdnNotPt :
				2555	case Hexagon::LDriuh_indexed_cdnPt :
				2556	case Hexagon::LDriuh_indexed_cdnNotPt :
				2557	case Hexagon::POST_LDriuh_cdnPt_V4 :
				2558	case Hexagon::POST_LDriuh_cdnNotPt_V4 :
				2559	case Hexagon::LDriub_cdnPt :
				2560	case Hexagon::LDriub_cdnNotPt :
				2561	case Hexagon::LDriub_indexed_cdnPt :
				2562	case Hexagon::LDriub_indexed_cdnNotPt :
				2563	case Hexagon::POST_LDriub_cdnPt_V4 :
				2564	case Hexagon::POST_LDriub_cdnNotPt_V4 :
				2565
				2566	case Hexagon::LDrid_indexed_cdnPt_V4 :
				2567	case Hexagon::LDrid_indexed_cdnNotPt_V4 :
				2568	case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
				2569	case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
				2570	case Hexagon::LDrib_indexed_cdnPt_V4 :
				2571	case Hexagon::LDrib_indexed_cdnNotPt_V4 :
				2572	case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
				2573	case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
				2574	case Hexagon::LDriub_indexed_cdnPt_V4 :
				2575	case Hexagon::LDriub_indexed_cdnNotPt_V4 :
				2576	case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
				2577	case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
				2578	case Hexagon::LDrih_indexed_cdnPt_V4 :
				2579	case Hexagon::LDrih_indexed_cdnNotPt_V4 :
				2580	case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
				2581	case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
				2582	case Hexagon::LDriuh_indexed_cdnPt_V4 :
				2583	case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
				2584	case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
				2585	case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
				2586	case Hexagon::LDriw_indexed_cdnPt_V4 :
				2587	case Hexagon::LDriw_indexed_cdnNotPt_V4 :
				2588	case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
				2589	case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
				2590
				2591	// Coditional add
				2592	case Hexagon::ADD_ri_cdnPt:
				2593	case Hexagon::ADD_ri_cdnNotPt:
				2594	case Hexagon::ADD_rr_cdnPt:
				2595	case Hexagon::ADD_rr_cdnNotPt:
				2596
				2597	// Conditional logical operations
				2598	case Hexagon::XOR_rr_cdnPt :
				2599	case Hexagon::XOR_rr_cdnNotPt :
				2600	case Hexagon::AND_rr_cdnPt :
				2601	case Hexagon::AND_rr_cdnNotPt :
				2602	case Hexagon::OR_rr_cdnPt :
				2603	case Hexagon::OR_rr_cdnNotPt :
				2604
				2605	// Conditonal subtract
				2606	case Hexagon::SUB_rr_cdnPt :
				2607	case Hexagon::SUB_rr_cdnNotPt :
				2608
				2609	// Conditional combine
				2610	case Hexagon::COMBINE_rr_cdnPt :
				2611	case Hexagon::COMBINE_rr_cdnNotPt :
				2612
				2613	// Conditional shift operations
				2614	case Hexagon::ASLH_cdnPt_V4:
				2615	case Hexagon::ASLH_cdnNotPt_V4:
				2616	case Hexagon::ASRH_cdnPt_V4:
				2617	case Hexagon::ASRH_cdnNotPt_V4:
				2618	case Hexagon::SXTB_cdnPt_V4:
				2619	case Hexagon::SXTB_cdnNotPt_V4:
				2620	case Hexagon::SXTH_cdnPt_V4:
				2621	case Hexagon::SXTH_cdnNotPt_V4:
				2622	case Hexagon::ZXTB_cdnPt_V4:
				2623	case Hexagon::ZXTB_cdnNotPt_V4:
				2624	case Hexagon::ZXTH_cdnPt_V4:
				2625	case Hexagon::ZXTH_cdnNotPt_V4:
				2626
				2627	// Conditional stores
				2628	case Hexagon::STrib_imm_cdnPt_V4 :
				2629	case Hexagon::STrib_imm_cdnNotPt_V4 :
				2630	case Hexagon::STrib_cdnPt_V4 :
				2631	case Hexagon::STrib_cdnNotPt_V4 :
				2632	case Hexagon::STrib_indexed_cdnPt_V4 :
				2633	case Hexagon::STrib_indexed_cdnNotPt_V4 :
				2634	case Hexagon::POST_STbri_cdnPt_V4 :
				2635	case Hexagon::POST_STbri_cdnNotPt_V4 :
				2636	case Hexagon::STrib_indexed_shl_cdnPt_V4 :
				2637	case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
				2638
				2639	// Store doubleword conditionally
				2640	case Hexagon::STrid_indexed_cdnPt_V4 :
				2641	case Hexagon::STrid_indexed_cdnNotPt_V4 :
				2642	case Hexagon::STrid_indexed_shl_cdnPt_V4 :
				2643	case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
				2644	case Hexagon::POST_STdri_cdnPt_V4 :
				2645	case Hexagon::POST_STdri_cdnNotPt_V4 :
				2646
				2647	// Store halfword conditionally
				2648	case Hexagon::STrih_cdnPt_V4 :
				2649	case Hexagon::STrih_cdnNotPt_V4 :
				2650	case Hexagon::STrih_indexed_cdnPt_V4 :
				2651	case Hexagon::STrih_indexed_cdnNotPt_V4 :
				2652	case Hexagon::STrih_imm_cdnPt_V4 :
				2653	case Hexagon::STrih_imm_cdnNotPt_V4 :
				2654	case Hexagon::STrih_indexed_shl_cdnPt_V4 :
				2655	case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
				2656	case Hexagon::POST_SThri_cdnPt_V4 :
				2657	case Hexagon::POST_SThri_cdnNotPt_V4 :
				2658
				2659	// Store word conditionally
				2660	case Hexagon::STriw_cdnPt_V4 :
				2661	case Hexagon::STriw_cdnNotPt_V4 :
				2662	case Hexagon::STriw_indexed_cdnPt_V4 :
				2663	case Hexagon::STriw_indexed_cdnNotPt_V4 :
				2664	case Hexagon::STriw_imm_cdnPt_V4 :
				2665	case Hexagon::STriw_imm_cdnNotPt_V4 :
				2666	case Hexagon::STriw_indexed_shl_cdnPt_V4 :
				2667	case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
				2668	case Hexagon::POST_STwri_cdnPt_V4 :
				2669	case Hexagon::POST_STwri_cdnNotPt_V4 :
				2670
				2671	case Hexagon::LDd_GP_cdnPt_V4:
				2672	case Hexagon::LDd_GP_cdnNotPt_V4:
				2673	case Hexagon::LDb_GP_cdnPt_V4:
				2674	case Hexagon::LDb_GP_cdnNotPt_V4:
				2675	case Hexagon::LDub_GP_cdnPt_V4:
				2676	case Hexagon::LDub_GP_cdnNotPt_V4:
				2677	case Hexagon::LDh_GP_cdnPt_V4:
				2678	case Hexagon::LDh_GP_cdnNotPt_V4:
				2679	case Hexagon::LDuh_GP_cdnPt_V4:
				2680	case Hexagon::LDuh_GP_cdnNotPt_V4:
				2681	case Hexagon::LDw_GP_cdnPt_V4:
				2682	case Hexagon::LDw_GP_cdnNotPt_V4:
				2683	case Hexagon::LDrid_GP_cdnPt_V4:
				2684	case Hexagon::LDrid_GP_cdnNotPt_V4:
				2685	case Hexagon::LDrib_GP_cdnPt_V4:
				2686	case Hexagon::LDrib_GP_cdnNotPt_V4:
				2687	case Hexagon::LDriub_GP_cdnPt_V4:
				2688	case Hexagon::LDriub_GP_cdnNotPt_V4:
				2689	case Hexagon::LDrih_GP_cdnPt_V4:
				2690	case Hexagon::LDrih_GP_cdnNotPt_V4:
				2691	case Hexagon::LDriuh_GP_cdnPt_V4:
				2692	case Hexagon::LDriuh_GP_cdnNotPt_V4:
				2693	case Hexagon::LDriw_GP_cdnPt_V4:
				2694	case Hexagon::LDriw_GP_cdnNotPt_V4:
				2695
				2696	case Hexagon::STrid_GP_cdnPt_V4:
				2697	case Hexagon::STrid_GP_cdnNotPt_V4:
				2698	case Hexagon::STrib_GP_cdnPt_V4:
				2699	case Hexagon::STrib_GP_cdnNotPt_V4:
				2700	case Hexagon::STrih_GP_cdnPt_V4:
				2701	case Hexagon::STrih_GP_cdnNotPt_V4:
				2702	case Hexagon::STriw_GP_cdnPt_V4:
				2703	case Hexagon::STriw_GP_cdnNotPt_V4:
				2704	case Hexagon::STd_GP_cdnPt_V4:
				2705	case Hexagon::STd_GP_cdnNotPt_V4:
				2706	case Hexagon::STb_GP_cdnPt_V4:
				2707	case Hexagon::STb_GP_cdnNotPt_V4:
				2708	case Hexagon::STh_GP_cdnPt_V4:
				2709	case Hexagon::STh_GP_cdnNotPt_V4:
				2710	case Hexagon::STw_GP_cdnPt_V4:
				2711	case Hexagon::STw_GP_cdnNotPt_V4:
				2712	return true;
				2713	}
				2714	return false;
				2715	}
				2716
				2717	static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
				2718	const HexagonInstrInfo *QII) {
				2719	assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
				2720	#ifndef NDEBUG
				2721	// Post Increment means duplicates. Use dense map to find duplicates in the
				2722	// list. Caution: Densemap initializes with the minimum of 64 buckets,
				2723	// whereas there are at most 5 operands in the post increment.
				2724	DenseMap<unsigned, unsigned> DefRegsSet;
				2725	for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
				2726	if (MI->getOperand(opNum).isReg() &&
				2727	MI->getOperand(opNum).isDef()) {
				2728	DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
				2729	}
				2730
				2731	for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
				2732	if (MI->getOperand(opNum).isReg() &&
				2733	MI->getOperand(opNum).isUse()) {
				2734	if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
				2735	return MI->getOperand(opNum);
				2736	}
				2737	}
				2738	#else
				2739	if (MI->getDesc().mayLoad()) {
				2740	// The 2nd operand is always the post increment operand in load.
				2741	assert(MI->getOperand(1).isReg() &&
				2742	"Post increment operand has be to a register.");
				2743	return (MI->getOperand(1));
				2744	}
				2745	if (MI->getDesc().mayStore()) {
				2746	// The 1st operand is always the post increment operand in store.
				2747	assert(MI->getOperand(0).isReg() &&
				2748	"Post increment operand has be to a register.");
				2749	return (MI->getOperand(0));
				2750	}
				2751	#endif
				2752	// we should never come here.
				2753	llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
				2754	}
				2755
				2756	// get the value being stored
				2757	static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
				2758	// value being stored is always the last operand.
				2759	return (MI->getOperand(MI->getNumOperands()-1));
				2760	}
				2761
				2762	// can be new value store?
				2763	// Following restrictions are to be respected in convert a store into
				2764	// a new value store.
				2765	// 1. If an instruction uses auto-increment, its address register cannot
				2766	// be a new-value register. Arch Spec 5.4.2.1
				2767	// 2. If an instruction uses absolute-set addressing mode,
				2768	// its address register cannot be a new-value register.
				2769	// Arch Spec 5.4.2.1.TODO: This is not enabled as
				2770	// as absolute-set address mode patters are not implemented.
				2771	// 3. If an instruction produces a 64-bit result, its registers cannot be used
				2772	// as new-value registers. Arch Spec 5.4.2.2.
				2773	// 4. If the instruction that sets a new-value register is conditional, then
				2774	// the instruction that uses the new-value register must also be conditional,
				2775	// and both must always have their predicates evaluate identically.
				2776	// Arch Spec 5.4.2.3.
				2777	// 5. There is an implied restriction of a packet can not have another store,
				2778	// if there is a new value store in the packet. Corollary, if there is
				2779	// already a store in a packet, there can not be a new value store.
				2780	// Arch Spec: 3.4.4.2
				2781	bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
				2782	MachineInstr *PacketMI, unsigned DepReg,
				2783	std::map <MachineInstr, SUnit> MIToSUnit)
				2784	{
				2785	// Make sure we are looking at the store
				2786	if (!IsNewifyStore(MI))
				2787	return false;
				2788
				2789	// Make sure there is dependency and can be new value'ed
				2790	if (GetStoreValueOperand(MI).isReg() &&
				2791	GetStoreValueOperand(MI).getReg() != DepReg)
				2792	return false;
				2793
				2794	const HexagonRegisterInfo* QRI =
				2795	(const HexagonRegisterInfo *) TM.getRegisterInfo();
				2796	const MCInstrDesc& MCID = PacketMI->getDesc();
				2797	// first operand is always the result
				2798
				2799	const HexagonInstrInfo QII = (const HexagonInstrInfo ) TII;
Jakob Stoklund Olesen	397fc48	2012-05-07 22:10:26 +0000	[diff] [blame]	2800	const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
Sirish Pande	26f61a1	2012-05-03 21:52:53 +0000	[diff] [blame]	2801
				2802	// if there is already an store in the packet, no can do new value store
				2803	// Arch Spec 3.4.4.2.
				2804	for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
				2805	VE = CurrentPacketMIs.end();
				2806	(VI != VE); ++VI) {
				2807	SUnit* PacketSU = MIToSUnit[*VI];
				2808	if (PacketSU->getInstr()->getDesc().mayStore() \|\|
				2809	// if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
				2810	// then we don't need this
				2811	PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME \|\|
				2812	PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
				2813	return false;
				2814	}
				2815
				2816	if (PacketRC == &Hexagon::DoubleRegsRegClass) {
				2817	// new value store constraint: double regs can not feed into new value store
				2818	// arch spec section: 5.4.2.2
				2819	return false;
				2820	}
				2821
				2822	// Make sure it's NOT the post increment register that we are going to
				2823	// new value.
				2824	if (QII->isPostIncrement(MI) &&
				2825	MI->getDesc().mayStore() &&
				2826	GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
				2827	return false;
				2828	}
				2829
				2830	if (QII->isPostIncrement(PacketMI) &&
				2831	PacketMI->getDesc().mayLoad() &&
				2832	GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
				2833	// if source is post_inc, or absolute-set addressing,
				2834	// it can not feed into new value store
				2835	// r3 = memw(r2++#4)
				2836	// memw(r30 + #-1404) = r2.new -> can not be new value store
				2837	// arch spec section: 5.4.2.1
				2838	return false;
				2839	}
				2840
				2841	// If the source that feeds the store is predicated, new value store must
				2842	// also be also predicated.
				2843	if (QII->isPredicated(PacketMI)) {
				2844	if (!QII->isPredicated(MI))
				2845	return false;
				2846
				2847	// Check to make sure that they both will have their predicates
				2848	// evaluate identically
Sirish Pande	12a5252	2012-05-11 20:00:34 +0000	[diff] [blame]	2849	unsigned predRegNumSrc = 0;
				2850	unsigned predRegNumDst = 0;
				2851	const TargetRegisterClass* predRegClass = NULL;
Sirish Pande	26f61a1	2012-05-03 21:52:53 +0000	[diff] [blame]	2852
				2853	// Get predicate register used in the source instruction
				2854	for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
				2855	if ( PacketMI->getOperand(opNum).isReg())
				2856	predRegNumSrc = PacketMI->getOperand(opNum).getReg();
				2857	predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
				2858	if (predRegClass == &Hexagon::PredRegsRegClass) {
				2859	break;
				2860	}
				2861	}
				2862	assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
				2863	("predicate register not found in a predicated PacketMI instruction"));
				2864
				2865	// Get predicate register used in new-value store instruction
				2866	for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
				2867	if ( MI->getOperand(opNum).isReg())
				2868	predRegNumDst = MI->getOperand(opNum).getReg();
				2869	predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
				2870	if (predRegClass == &Hexagon::PredRegsRegClass) {
				2871	break;
				2872	}
				2873	}
				2874	assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
				2875	("predicate register not found in a predicated MI instruction"));
				2876
				2877	// New-value register producer and user (store) need to satisfy these
				2878	// constraints:
				2879	// 1) Both instructions should be predicated on the same register.
				2880	// 2) If producer of the new-value register is .new predicated then store
				2881	// should also be .new predicated and if producer is not .new predicated
				2882	// then store should not be .new predicated.
				2883	// 3) Both new-value register producer and user should have same predicate
				2884	// sense, i.e, either both should be negated or both should be none negated.
				2885
				2886	if (( predRegNumDst != predRegNumSrc) \|\|
				2887	isDotNewInst(PacketMI) != isDotNewInst(MI) \|\|
				2888	GetPredicateSense(MI, QII) != GetPredicateSense(PacketMI, QII)) {
				2889	return false;
				2890	}
				2891	}
				2892
				2893	// Make sure that other than the new-value register no other store instruction
				2894	// register has been modified in the same packet. Predicate registers can be
				2895	// modified by they should not be modified between the producer and the store
				2896	// instruction as it will make them both conditional on different values.
				2897	// We already know this to be true for all the instructions before and
				2898	// including PacketMI. Howerver, we need to perform the check for the
				2899	// remaining instructions in the packet.
				2900
				2901	std::vector<MachineInstr*>::iterator VI;
				2902	std::vector<MachineInstr*>::iterator VE;
				2903	unsigned StartCheck = 0;
				2904
				2905	for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
				2906	(VI != VE); ++VI) {
				2907	SUnit* TempSU = MIToSUnit[*VI];
				2908	MachineInstr* TempMI = TempSU->getInstr();
				2909
				2910	// Following condition is true for all the instructions until PacketMI is
				2911	// reached (StartCheck is set to 0 before the for loop).
				2912	// StartCheck flag is 1 for all the instructions after PacketMI.
				2913	if (TempMI != PacketMI && !StartCheck) // start processing only after
				2914	continue; // encountering PacketMI
				2915
				2916	StartCheck = 1;
				2917	if (TempMI == PacketMI) // We don't want to check PacketMI for dependence
				2918	continue;
				2919
				2920	for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
				2921	if (MI->getOperand(opNum).isReg() &&
				2922	TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
				2923	QRI))
				2924	return false;
				2925	}
				2926	}
				2927
				2928	// Make sure that for non POST_INC stores:
				2929	// 1. The only use of reg is DepReg and no other registers.
				2930	// This handles V4 base+index registers.
				2931	// The following store can not be dot new.
				2932	// Eg. r0 = add(r0, #3)a
				2933	// memw(r1+r0<<#2) = r0
				2934	if (!QII->isPostIncrement(MI) &&
				2935	GetStoreValueOperand(MI).isReg() &&
				2936	GetStoreValueOperand(MI).getReg() == DepReg) {
				2937	for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
				2938	if (MI->getOperand(opNum).isReg() &&
				2939	MI->getOperand(opNum).getReg() == DepReg) {
				2940	return false;
				2941	}
				2942	}
				2943	// 2. If data definition is because of implicit definition of the register,
				2944	// do not newify the store. Eg.
				2945	// %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
				2946	// STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
				2947	for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
				2948	if (PacketMI->getOperand(opNum).isReg() &&
				2949	PacketMI->getOperand(opNum).getReg() == DepReg &&
				2950	PacketMI->getOperand(opNum).isDef() &&
				2951	PacketMI->getOperand(opNum).isImplicit()) {
				2952	return false;
				2953	}
				2954	}
				2955	}
				2956
				2957	// Can be dot new store.
				2958	return true;
				2959	}
				2960
				2961	// can this MI to promoted to either
				2962	// new value store or new value jump
				2963	bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,
				2964	SUnit *PacketSU, unsigned DepReg,
				2965	std::map <MachineInstr, SUnit> MIToSUnit,
				2966	MachineBasicBlock::iterator &MII)
				2967	{
				2968
				2969	const HexagonRegisterInfo* QRI =
				2970	(const HexagonRegisterInfo *) TM.getRegisterInfo();
				2971	if (!QRI->Subtarget.hasV4TOps() \|\|
				2972	!IsNewifyStore(MI))
				2973	return false;
				2974
				2975	MachineInstr *PacketMI = PacketSU->getInstr();
				2976
				2977	// Check to see the store can be new value'ed.
				2978	if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
				2979	return true;
				2980
				2981	// Check to see the compare/jump can be new value'ed.
				2982	// This is done as a pass on its own. Don't need to check it here.
				2983	return false;
				2984	}
				2985
				2986	// Check to see if an instruction can be dot new
				2987	// There are three kinds.
				2988	// 1. dot new on predicate - V2/V3/V4
				2989	// 2. dot new on stores NV/ST - V4
				2990	// 3. dot new on jump NV/J - V4 -- This is generated in a pass.
				2991	bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
				2992	SUnit *PacketSU, unsigned DepReg,
				2993	std::map <MachineInstr, SUnit> MIToSUnit,
				2994	MachineBasicBlock::iterator &MII,
				2995	const TargetRegisterClass* RC )
				2996	{
				2997	// already a dot new instruction
				2998	if (isDotNewInst(MI) && !IsNewifyStore(MI))
				2999	return false;
				3000
				3001	if (!isNewifiable(MI))
				3002	return false;
				3003
				3004	// predicate .new
				3005	if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
				3006	return true;
				3007	else if (RC != &Hexagon::PredRegsRegClass &&
				3008	!IsNewifyStore(MI)) // MI is not a new-value store
				3009	return false;
				3010	else {
				3011	// Create a dot new machine instruction to see if resources can be
				3012	// allocated. If not, bail out now.
				3013	const HexagonInstrInfo QII = (const HexagonInstrInfo ) TII;
				3014	int NewOpcode = GetDotNewOp(MI->getOpcode());
				3015	const MCInstrDesc &desc = QII->get(NewOpcode);
				3016	DebugLoc dl;
				3017	MachineInstr *NewMI =
				3018	MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
				3019	bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
				3020	MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
				3021
				3022	if (!ResourcesAvailable)
				3023	return false;
				3024
				3025	// new value store only
				3026	// new new value jump generated as a passes
				3027	if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
				3028	return false;
				3029	}
				3030	}
				3031	return true;
				3032	}
				3033
				3034	// Go through the packet instructions and search for anti dependency
				3035	// between them and DepReg from MI
				3036	// Consider this case:
				3037	// Trying to add
				3038	// a) %R1<def> = TFRI_cdNotPt %P3, 2
				3039	// to this packet:
				3040	// {
				3041	// b) %P0<def> = OR_pp %P3<kill>, %P0<kill>
				3042	// c) %P3<def> = TFR_PdRs %R23
				3043	// d) %R1<def> = TFRI_cdnPt %P3, 4
				3044	// }
				3045	// The P3 from a) and d) will be complements after
				3046	// a)'s P3 is converted to .new form
				3047	// Anti Dep between c) and b) is irrelevant for this case
				3048	bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,
				3049	unsigned DepReg,
				3050	std::map <MachineInstr, SUnit> MIToSUnit) {
				3051
				3052	const HexagonInstrInfo QII = (const HexagonInstrInfo ) TII;
				3053	SUnit* PacketSUDep = MIToSUnit[MI];
				3054
				3055	for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
				3056	VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
				3057
				3058	// We only care for dependencies to predicated instructions
				3059	if(!QII->isPredicated(*VIN)) continue;
				3060
				3061	// Scheduling Unit for current insn in the packet
				3062	SUnit* PacketSU = MIToSUnit[*VIN];
				3063
				3064	// Look at dependencies between current members of the packet
				3065	// and predicate defining instruction MI.
				3066	// Make sure that dependency is on the exact register
				3067	// we care about.
				3068	if (PacketSU->isSucc(PacketSUDep)) {
				3069	for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
				3070	if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
				3071	(PacketSU->Succs[i].getKind() == SDep::Anti) &&
				3072	(PacketSU->Succs[i].getReg() == DepReg)) {
				3073	return true;
				3074	}
				3075	}
				3076	}
				3077	}
				3078
				3079	return false;
				3080	}
				3081
				3082
				3083	// Given two predicated instructions, this function detects whether
				3084	// the predicates are complements
				3085	bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
				3086	MachineInstr* MI2, std::map <MachineInstr, SUnit> MIToSUnit) {
				3087
				3088	const HexagonInstrInfo QII = (const HexagonInstrInfo ) TII;
				3089	// Currently can only reason about conditional transfers
				3090	if (!QII->isConditionalTransfer(MI1) \|\| !QII->isConditionalTransfer(MI2)) {
				3091	return false;
				3092	}
				3093
				3094	// Scheduling unit for candidate
				3095	SUnit* SU = MIToSUnit[MI1];
				3096
				3097	// One corner case deals with the following scenario:
				3098	// Trying to add
				3099	// a) %R24<def> = TFR_cPt %P0, %R25
				3100	// to this packet:
				3101	//
				3102	// {
				3103	// b) %R25<def> = TFR_cNotPt %P0, %R24
				3104	// c) %P0<def> = CMPEQri %R26, 1
				3105	// }
				3106	//
				3107	// On general check a) and b) are complements, but
				3108	// presence of c) will convert a) to .new form, and
				3109	// then it is not a complement
				3110	// We attempt to detect it by analyzing existing
				3111	// dependencies in the packet
				3112
				3113	// Analyze relationships between all existing members of the packet.
				3114	// Look for Anti dependecy on the same predicate reg
				3115	// as used in the candidate
				3116	for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
				3117	VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
				3118
				3119	// Scheduling Unit for current insn in the packet
				3120	SUnit* PacketSU = MIToSUnit[*VIN];
				3121
				3122	// If this instruction in the packet is succeeded by the candidate...
				3123	if (PacketSU->isSucc(SU)) {
				3124	for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
				3125	// The corner case exist when there is true data
				3126	// dependency between candidate and one of current
				3127	// packet members, this dep is on predicate reg, and
				3128	// there already exist anti dep on the same pred in
				3129	// the packet.
				3130	if (PacketSU->Succs[i].getSUnit() == SU &&
				3131	Hexagon::PredRegsRegClass.contains(
				3132	PacketSU->Succs[i].getReg()) &&
				3133	PacketSU->Succs[i].getKind() == SDep::Data &&
				3134	// Here I know that *VIN is predicate setting instruction
				3135	// with true data dep to candidate on the register
				3136	// we care about - c) in the above example.
				3137	// Now I need to see if there is an anti dependency
				3138	// from c) to any other instruction in the
				3139	// same packet on the pred reg of interest
				3140	RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
				3141	MIToSUnit)) {
				3142	return false;
				3143	}
				3144	}
				3145	}
				3146	}
				3147
				3148	// If the above case does not apply, check regular
				3149	// complement condition.
				3150	// Check that the predicate register is the same and
				3151	// that the predicate sense is different
				3152	// We also need to differentiate .old vs. .new:
				3153	// !p0 is not complimentary to p0.new
				3154	return ((MI1->getOperand(1).getReg() == MI2->getOperand(1).getReg()) &&
				3155	(GetPredicateSense(MI1, QII) != GetPredicateSense(MI2, QII)) &&
				3156	(isDotNewInst(MI1) == isDotNewInst(MI2)));
				3157	}
				3158
				3159	// initPacketizerState - Initialize packetizer flags
				3160	void HexagonPacketizerList::initPacketizerState() {
				3161
				3162	Dependence = false;
				3163	PromotedToDotNew = false;
				3164	GlueToNewValueJump = false;
				3165	GlueAllocframeStore = false;
				3166	FoundSequentialDependence = false;
				3167
				3168	return;
				3169	}
				3170
				3171	// ignorePseudoInstruction - Ignore bundling of pseudo instructions.
				3172	bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
				3173	MachineBasicBlock *MBB) {
				3174	if (MI->isDebugValue())
				3175	return true;
				3176
				3177	// We must print out inline assembly
				3178	if (MI->isInlineAsm())
				3179	return false;
				3180
				3181	// We check if MI has any functional units mapped to it.
				3182	// If it doesn't, we ignore the instruction.
				3183	const MCInstrDesc& TID = MI->getDesc();
				3184	unsigned SchedClass = TID.getSchedClass();
				3185	const InstrStage* IS =
				3186	ResourceTracker->getInstrItins()->beginStage(SchedClass);
Hal Finkel	b460a33	2012-06-22 20:27:13 +0000	[diff] [blame]	3187	unsigned FuncUnits = IS->getUnits();
Sirish Pande	26f61a1	2012-05-03 21:52:53 +0000	[diff] [blame]	3188	return !FuncUnits;
				3189	}
				3190
				3191	// isSoloInstruction: - Returns true for instructions that must be
				3192	// scheduled in their own packet.
				3193	bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
				3194
				3195	if (MI->isInlineAsm())
				3196	return true;
				3197
				3198	if (MI->isEHLabel())
				3199	return true;
				3200
				3201	// From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
				3202	// trap, pause, barrier, icinva, isync, and syncht are solo instructions.
				3203	// They must not be grouped with other instructions in a packet.
				3204	if (IsSchedBarrier(MI))
				3205	return true;
				3206
				3207	return false;
				3208	}
				3209
				3210	// isLegalToPacketizeTogether:
				3211	// SUI is the current instruction that is out side of the current packet.
				3212	// SUJ is the current instruction inside the current packet against which that
				3213	// SUI will be packetized.
				3214	bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit SUI, SUnit SUJ) {
				3215	MachineInstr *I = SUI->getInstr();
				3216	MachineInstr *J = SUJ->getInstr();
				3217	assert(I && J && "Unable to packetize null instruction!");
				3218
				3219	const MCInstrDesc &MCIDI = I->getDesc();
				3220	const MCInstrDesc &MCIDJ = J->getDesc();
				3221
				3222	MachineBasicBlock::iterator II = I;
				3223
				3224	const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
				3225	const HexagonRegisterInfo* QRI =
				3226	(const HexagonRegisterInfo *) TM.getRegisterInfo();
				3227	const HexagonInstrInfo QII = (const HexagonInstrInfo ) TII;
				3228
				3229	// Inline asm cannot go in the packet.
				3230	if (I->getOpcode() == Hexagon::INLINEASM)
				3231	llvm_unreachable("Should not meet inline asm here!");
				3232
				3233	if (isSoloInstruction(I))
				3234	llvm_unreachable("Should not meet solo instr here!");
				3235
				3236	// A save callee-save register function call can only be in a packet
				3237	// with instructions that don't write to the callee-save registers.
				3238	if ((QII->isSaveCalleeSavedRegsCall(I) &&
				3239	DoesModifyCalleeSavedReg(J, QRI)) \|\|
				3240	(QII->isSaveCalleeSavedRegsCall(J) &&
				3241	DoesModifyCalleeSavedReg(I, QRI))) {
				3242	Dependence = true;
				3243	return false;
				3244	}
				3245
				3246	// Two control flow instructions cannot go in the same packet.
				3247	if (IsControlFlow(I) && IsControlFlow(J)) {
				3248	Dependence = true;
				3249	return false;
				3250	}
				3251
				3252	// A LoopN instruction cannot appear in the same packet as a jump or call.
				3253	if (IsLoopN(I) && ( IsDirectJump(J)
				3254	\|\| MCIDJ.isCall()
				3255	\|\| QII->isDeallocRet(J))) {
				3256	Dependence = true;
				3257	return false;
				3258	}
				3259	if (IsLoopN(J) && ( IsDirectJump(I)
				3260	\|\| MCIDI.isCall()
				3261	\|\| QII->isDeallocRet(I))) {
				3262	Dependence = true;
				3263	return false;
				3264	}
				3265
				3266	// dealloc_return cannot appear in the same packet as a conditional or
				3267	// unconditional jump.
				3268	if (QII->isDeallocRet(I) && ( MCIDJ.isBranch()
				3269	\|\| MCIDJ.isCall()
				3270	\|\| MCIDJ.isBarrier())) {
				3271	Dependence = true;
				3272	return false;
				3273	}
				3274
				3275
				3276	// V4 allows dual store. But does not allow second store, if the
				3277	// first store is not in SLOT0. New value store, new value jump,
				3278	// dealloc_return and memop always take SLOT0.
				3279	// Arch spec 3.4.4.2
				3280	if (QRI->Subtarget.hasV4TOps()) {
				3281
				3282	if (MCIDI.mayStore() && MCIDJ.mayStore() && isNewValueInst(J)) {
				3283	Dependence = true;
				3284	return false;
				3285	}
				3286
				3287	if ( (QII->isMemOp(J) && MCIDI.mayStore())
				3288	\|\| (MCIDJ.mayStore() && QII->isMemOp(I))
				3289	\|\| (QII->isMemOp(J) && QII->isMemOp(I))) {
				3290	Dependence = true;
				3291	return false;
				3292	}
				3293
				3294	//if dealloc_return
				3295	if (MCIDJ.mayStore() && QII->isDeallocRet(I)){
				3296	Dependence = true;
				3297	return false;
				3298	}
				3299
				3300	// If an instruction feeds new value jump, glue it.
				3301	MachineBasicBlock::iterator NextMII = I;
				3302	++NextMII;
				3303	MachineInstr *NextMI = NextMII;
				3304
				3305	if (QII->isNewValueJump(NextMI)) {
				3306
				3307	bool secondRegMatch = false;
				3308	bool maintainNewValueJump = false;
				3309
				3310	if (NextMI->getOperand(1).isReg() &&
				3311	I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
				3312	secondRegMatch = true;
				3313	maintainNewValueJump = true;
				3314	}
				3315
				3316	if (!secondRegMatch &&
				3317	I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
				3318	maintainNewValueJump = true;
				3319	}
				3320
				3321	for (std::vector<MachineInstr*>::iterator
				3322	VI = CurrentPacketMIs.begin(),
				3323	VE = CurrentPacketMIs.end();
				3324	(VI != VE && maintainNewValueJump); ++VI) {
				3325	SUnit* PacketSU = MIToSUnit[*VI];
				3326
				3327	// NVJ can not be part of the dual jump - Arch Spec: section 7.8
				3328	if (PacketSU->getInstr()->getDesc().isCall()) {
				3329	Dependence = true;
				3330	break;
				3331	}
				3332	// Validate
				3333	// 1. Packet does not have a store in it.
				3334	// 2. If the first operand of the nvj is newified, and the second
				3335	// operand is also a reg, it (second reg) is not defined in
				3336	// the same packet.
				3337	// 3. If the second operand of the nvj is newified, (which means
				3338	// first operand is also a reg), first reg is not defined in
				3339	// the same packet.
				3340	if (PacketSU->getInstr()->getDesc().mayStore() \|\|
				3341	PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME \|\|
				3342	// Check #2.
				3343	(!secondRegMatch && NextMI->getOperand(1).isReg() &&
				3344	PacketSU->getInstr()->modifiesRegister(
				3345	NextMI->getOperand(1).getReg(), QRI)) \|\|
				3346	// Check #3.
				3347	(secondRegMatch &&
				3348	PacketSU->getInstr()->modifiesRegister(
				3349	NextMI->getOperand(0).getReg(), QRI))) {
				3350	Dependence = true;
				3351	break;
				3352	}
				3353	}
				3354	if (!Dependence)
				3355	GlueToNewValueJump = true;
				3356	else
				3357	return false;
				3358	}
				3359	}
				3360
				3361	if (SUJ->isSucc(SUI)) {
				3362	for (unsigned i = 0;
				3363	(i < SUJ->Succs.size()) && !FoundSequentialDependence;
				3364	++i) {
				3365
				3366	if (SUJ->Succs[i].getSUnit() != SUI) {
				3367	continue;
				3368	}
				3369
				3370	SDep::Kind DepType = SUJ->Succs[i].getKind();
				3371
				3372	// For direct calls:
				3373	// Ignore register dependences for call instructions for
				3374	// packetization purposes except for those due to r31 and
				3375	// predicate registers.
				3376	//
				3377	// For indirect calls:
				3378	// Same as direct calls + check for true dependences to the register
				3379	// used in the indirect call.
				3380	//
				3381	// We completely ignore Order dependences for call instructions
				3382	//
				3383	// For returns:
				3384	// Ignore register dependences for return instructions like jumpr,
				3385	// dealloc return unless we have dependencies on the explicit uses
				3386	// of the registers used by jumpr (like r31) or dealloc return
				3387	// (like r29 or r30).
				3388	//
				3389	// TODO: Currently, jumpr is handling only return of r31. So, the
				3390	// following logic (specificaly IsCallDependent) is working fine.
				3391	// We need to enable jumpr for register other than r31 and then,
				3392	// we need to rework the last part, where it handles indirect call
				3393	// of that (IsCallDependent) function. Bug 6216 is opened for this.
				3394	//
				3395	unsigned DepReg = 0;
				3396	const TargetRegisterClass* RC = NULL;
				3397	if (DepType == SDep::Data) {
				3398	DepReg = SUJ->Succs[i].getReg();
				3399	RC = QRI->getMinimalPhysRegClass(DepReg);
				3400	}
				3401	if ((MCIDI.isCall() \|\| MCIDI.isReturn()) &&
				3402	(!IsRegDependence(DepType) \|\|
				3403	!IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
				3404	/* do nothing */
				3405	}
				3406
				3407	// For instructions that can be promoted to dot-new, try to promote.
				3408	else if ((DepType == SDep::Data) &&
				3409	CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
				3410	PromoteToDotNew(I, DepType, II, RC)) {
				3411	PromotedToDotNew = true;
				3412	/* do nothing */
				3413	}
				3414
				3415	else if ((DepType == SDep::Data) &&
				3416	(QII->isNewValueJump(I))) {
				3417	/* do nothing */
				3418	}
				3419
				3420	// For predicated instructions, if the predicates are complements
				3421	// then there can be no dependence.
				3422	else if (QII->isPredicated(I) &&
				3423	QII->isPredicated(J) &&
				3424	ArePredicatesComplements(I, J, MIToSUnit)) {
				3425	/* do nothing */
				3426
				3427	}
				3428	else if (IsDirectJump(I) &&
				3429	!MCIDJ.isBranch() &&
				3430	!MCIDJ.isCall() &&
				3431	(DepType == SDep::Order)) {
				3432	// Ignore Order dependences between unconditional direct branches
				3433	// and non-control-flow instructions
				3434	/* do nothing */
				3435	}
				3436	else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
				3437	(DepType != SDep::Output)) {
				3438	// Ignore all dependences for jumps except for true and output
				3439	// dependences
				3440	/* do nothing */
				3441	}
				3442
				3443	// Ignore output dependences due to superregs. We can
				3444	// write to two different subregisters of R1:0 for instance
				3445	// in the same cycle
				3446	//
				3447
				3448	//
				3449	// Let the
				3450	// If neither I nor J defines DepReg, then this is a
				3451	// superfluous output dependence. The dependence must be of the
				3452	// form:
				3453	// R0 = ...
				3454	// R1 = ...
				3455	// and there is an output dependence between the two instructions
				3456	// with
				3457	// DepReg = D0
				3458	// We want to ignore these dependences.
				3459	// Ideally, the dependence constructor should annotate such
				3460	// dependences. We can then avoid this relatively expensive check.
				3461	//
				3462	else if (DepType == SDep::Output) {
				3463	// DepReg is the register that's responsible for the dependence.
				3464	unsigned DepReg = SUJ->Succs[i].getReg();
				3465
				3466	// Check if I and J really defines DepReg.
				3467	if (I->definesRegister(DepReg) \|\|
				3468	J->definesRegister(DepReg)) {
				3469	FoundSequentialDependence = true;
				3470	break;
				3471	}
				3472	}
				3473
				3474	// We ignore Order dependences for
				3475	// 1. Two loads unless they are volatile.
				3476	// 2. Two stores in V4 unless they are volatile.
				3477	else if ((DepType == SDep::Order) &&
Jakob Stoklund Olesen	f036f7a	2012-08-29 21:19:21 +0000	[diff] [blame]	3478	!I->hasOrderedMemoryRef() &&
				3479	!J->hasOrderedMemoryRef()) {
Sirish Pande	26f61a1	2012-05-03 21:52:53 +0000	[diff] [blame]	3480	if (QRI->Subtarget.hasV4TOps() &&
				3481	// hexagonv4 allows dual store.
				3482	MCIDI.mayStore() && MCIDJ.mayStore()) {
				3483	/* do nothing */
				3484	}
				3485	// store followed by store-- not OK on V2
				3486	// store followed by load -- not OK on all (OK if addresses
				3487	// are not aliased)
				3488	// load followed by store -- OK on all
				3489	// load followed by load -- OK on all
				3490	else if ( !MCIDJ.mayStore()) {
				3491	/* do nothing */
				3492	}
				3493	else {
				3494	FoundSequentialDependence = true;
				3495	break;
				3496	}
				3497	}
				3498
				3499	// For V4, special case ALLOCFRAME. Even though there is dependency
				3500	// between ALLOCAFRAME and subsequent store, allow it to be
				3501	// packetized in a same packet. This implies that the store is using
				3502	// caller's SP. Hense, offset needs to be updated accordingly.
				3503	else if (DepType == SDep::Data
				3504	&& QRI->Subtarget.hasV4TOps()
				3505	&& J->getOpcode() == Hexagon::ALLOCFRAME
				3506	&& (I->getOpcode() == Hexagon::STrid
				3507	\|\| I->getOpcode() == Hexagon::STriw
				3508	\|\| I->getOpcode() == Hexagon::STrib)
				3509	&& I->getOperand(0).getReg() == QRI->getStackRegister()
				3510	&& QII->isValidOffset(I->getOpcode(),
				3511	I->getOperand(1).getImm() -
				3512	(FrameSize + HEXAGON_LRFP_SIZE)))
				3513	{
				3514	GlueAllocframeStore = true;
				3515	// Since this store is to be glued with allocframe in the same
				3516	// packet, it will use SP of the previous stack frame, i.e
				3517	// caller's SP. Therefore, we need to recalculate offset according
				3518	// to this change.
				3519	I->getOperand(1).setImm(I->getOperand(1).getImm() -
				3520	(FrameSize + HEXAGON_LRFP_SIZE));
				3521	}
				3522
				3523	//
				3524	// Skip over anti-dependences. Two instructions that are
				3525	// anti-dependent can share a packet
				3526	//
				3527	else if (DepType != SDep::Anti) {
				3528	FoundSequentialDependence = true;
				3529	break;
				3530	}
				3531	}
				3532
				3533	if (FoundSequentialDependence) {
				3534	Dependence = true;
				3535	return false;
				3536	}
				3537	}
				3538
				3539	return true;
				3540	}
				3541
				3542	// isLegalToPruneDependencies
				3543	bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit SUI, SUnit SUJ) {
				3544	MachineInstr *I = SUI->getInstr();
				3545	assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
				3546
				3547	const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
				3548
				3549	if (Dependence) {
				3550
				3551	// Check if the instruction was promoted to a dot-new. If so, demote it
				3552	// back into a dot-old.
				3553	if (PromotedToDotNew) {
				3554	DemoteToDotOld(I);
				3555	}
				3556
				3557	// Check if the instruction (must be a store) was glued with an Allocframe
				3558	// instruction. If so, restore its offset to its original value, i.e. use
				3559	// curent SP instead of caller's SP.
				3560	if (GlueAllocframeStore) {
				3561	I->getOperand(1).setImm(I->getOperand(1).getImm() +
				3562	FrameSize + HEXAGON_LRFP_SIZE);
				3563	}
				3564
				3565	return false;
				3566	}
				3567	return true;
				3568	}
				3569
				3570	MachineBasicBlock::iterator
				3571	HexagonPacketizerList::addToPacket(MachineInstr *MI) {
				3572
				3573	MachineBasicBlock::iterator MII = MI;
				3574	MachineBasicBlock *MBB = MI->getParent();
				3575
				3576	const HexagonInstrInfo QII = (const HexagonInstrInfo ) TII;
				3577
				3578	if (GlueToNewValueJump) {
				3579
				3580	++MII;
				3581	MachineInstr *nvjMI = MII;
				3582	assert(ResourceTracker->canReserveResources(MI));
				3583	ResourceTracker->reserveResources(MI);
Brendon Cahoon	5262abb	2012-05-14 19:35:42 +0000	[diff] [blame]	3584	if (QII->isExtended(MI) &&
Sirish Pande	26f61a1	2012-05-03 21:52:53 +0000	[diff] [blame]	3585	!tryAllocateResourcesForConstExt(MI)) {
				3586	endPacket(MBB, MI);
				3587	ResourceTracker->reserveResources(MI);
				3588	assert(canReserveResourcesForConstExt(MI) &&
				3589	"Ensure that there is a slot");
				3590	reserveResourcesForConstExt(MI);
				3591	// Reserve resources for new value jump constant extender.
				3592	assert(canReserveResourcesForConstExt(MI) &&
				3593	"Ensure that there is a slot");
				3594	reserveResourcesForConstExt(nvjMI);
				3595	assert(ResourceTracker->canReserveResources(nvjMI) &&
				3596	"Ensure that there is a slot");
				3597
				3598	} else if ( // Extended instruction takes two slots in the packet.
				3599	// Try reserve and allocate 4-byte in the current packet first.
				3600	(QII->isExtended(nvjMI)
				3601	&& (!tryAllocateResourcesForConstExt(nvjMI)
				3602	\|\| !ResourceTracker->canReserveResources(nvjMI)))
				3603	\|\| // For non-extended instruction, no need to allocate extra 4 bytes.
				3604	(!QII->isExtended(nvjMI) &&
				3605	!ResourceTracker->canReserveResources(nvjMI)))
				3606	{
				3607	endPacket(MBB, MI);
				3608	// A new and empty packet starts.
				3609	// We are sure that the resources requirements can be satisfied.
				3610	// Therefore, do not need to call "canReserveResources" anymore.
				3611	ResourceTracker->reserveResources(MI);
				3612	if (QII->isExtended(nvjMI))
				3613	reserveResourcesForConstExt(nvjMI);
				3614	}
				3615	// Here, we are sure that "reserveResources" would succeed.
				3616	ResourceTracker->reserveResources(nvjMI);
				3617	CurrentPacketMIs.push_back(MI);
				3618	CurrentPacketMIs.push_back(nvjMI);
				3619	} else {
Brendon Cahoon	5262abb	2012-05-14 19:35:42 +0000	[diff] [blame]	3620	if ( QII->isExtended(MI)
Sirish Pande	26f61a1	2012-05-03 21:52:53 +0000	[diff] [blame]	3621	&& ( !tryAllocateResourcesForConstExt(MI)
				3622	\|\| !ResourceTracker->canReserveResources(MI)))
				3623	{
				3624	endPacket(MBB, MI);
				3625	// Check if the instruction was promoted to a dot-new. If so, demote it
				3626	// back into a dot-old
				3627	if (PromotedToDotNew) {
				3628	DemoteToDotOld(MI);
				3629	}
				3630	reserveResourcesForConstExt(MI);
				3631	}
				3632	// In case that "MI" is not an extended insn,
				3633	// the resource availability has already been checked.
				3634	ResourceTracker->reserveResources(MI);
				3635	CurrentPacketMIs.push_back(MI);
				3636	}
				3637	return MII;
				3638	}
				3639
				3640	//===----------------------------------------------------------------------===//
				3641	// Public Constructor Functions
				3642	//===----------------------------------------------------------------------===//
				3643
				3644	FunctionPass *llvm::createHexagonPacketizer() {
				3645	return new HexagonPacketizer();
				3646	}
				3647