Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 1 | //===-- RegAllocLocal.cpp - A BasicBlock generic register allocator -------===// |
John Criswell | b576c94 | 2003-10-20 19:43:21 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 9 | // |
| 10 | // This register allocator allocates registers to a basic block at a time, |
| 11 | // attempting to keep values in registers and reusing registers as appropriate. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
Chris Lattner | 4cc662b | 2003-08-03 21:47:31 +0000 | [diff] [blame] | 15 | #define DEBUG_TYPE "regalloc" |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 16 | #include "llvm/CodeGen/Passes.h" |
Chris Lattner | 580f9be | 2002-12-28 20:40:43 +0000 | [diff] [blame] | 17 | #include "llvm/CodeGen/MachineFunctionPass.h" |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 18 | #include "llvm/CodeGen/MachineInstr.h" |
Chris Lattner | ff863ba | 2002-12-25 05:05:46 +0000 | [diff] [blame] | 19 | #include "llvm/CodeGen/SSARegMap.h" |
Chris Lattner | eb24db9 | 2002-12-28 21:08:26 +0000 | [diff] [blame] | 20 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 21 | #include "llvm/CodeGen/LiveVariables.h" |
Chris Lattner | 3501fea | 2003-01-14 22:00:31 +0000 | [diff] [blame] | 22 | #include "llvm/Target/TargetInstrInfo.h" |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 23 | #include "llvm/Target/TargetMachine.h" |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 24 | #include "Support/CommandLine.h" |
Chris Lattner | a11136b | 2003-08-01 22:21:34 +0000 | [diff] [blame] | 25 | #include "Support/Debug.h" |
| 26 | #include "Support/Statistic.h" |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 27 | #include <iostream> |
Chris Lattner | ef09c63 | 2004-01-31 21:27:19 +0000 | [diff] [blame] | 28 | using namespace llvm; |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 29 | |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 30 | namespace { |
| 31 | Statistic<> NumSpilled ("ra-local", "Number of registers spilled"); |
| 32 | Statistic<> NumReloaded("ra-local", "Number of registers reloaded"); |
Chris Lattner | 3e43026 | 2003-10-24 20:05:58 +0000 | [diff] [blame] | 33 | cl::opt<bool> DisableKill("disable-kill", cl::Hidden, |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 34 | cl::desc("Disable register kill in local-ra")); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 35 | |
Chris Lattner | 580f9be | 2002-12-28 20:40:43 +0000 | [diff] [blame] | 36 | class RA : public MachineFunctionPass { |
| 37 | const TargetMachine *TM; |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 38 | MachineFunction *MF; |
Chris Lattner | 580f9be | 2002-12-28 20:40:43 +0000 | [diff] [blame] | 39 | const MRegisterInfo *RegInfo; |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 40 | LiveVariables *LV; |
Chris Lattner | ff863ba | 2002-12-25 05:05:46 +0000 | [diff] [blame] | 41 | |
Chris Lattner | b8822ad | 2003-08-04 23:36:39 +0000 | [diff] [blame] | 42 | // StackSlotForVirtReg - Maps virtual regs to the frame index where these |
| 43 | // values are spilled. |
Chris Lattner | 580f9be | 2002-12-28 20:40:43 +0000 | [diff] [blame] | 44 | std::map<unsigned, int> StackSlotForVirtReg; |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 45 | |
| 46 | // Virt2PhysRegMap - This map contains entries for each virtual register |
Chris Lattner | ecea563 | 2004-02-09 02:12:04 +0000 | [diff] [blame] | 47 | // that is currently available in a physical register. This is "logically" |
| 48 | // a map from virtual register numbers to physical register numbers. |
| 49 | // Instead of using a map, however, which is slow, we use a vector. The |
| 50 | // index is the VREG number - FirstVirtualRegister. If the entry is zero, |
| 51 | // then it is logically "not in the map". |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 52 | // |
Chris Lattner | ecea563 | 2004-02-09 02:12:04 +0000 | [diff] [blame] | 53 | std::vector<unsigned> Virt2PhysRegMap; |
| 54 | |
| 55 | unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) { |
| 56 | assert(VirtReg >= MRegisterInfo::FirstVirtualRegister &&"Illegal VREG #"); |
| 57 | assert(VirtReg-MRegisterInfo::FirstVirtualRegister <Virt2PhysRegMap.size() |
| 58 | && "VirtReg not in map!"); |
| 59 | return Virt2PhysRegMap[VirtReg-MRegisterInfo::FirstVirtualRegister]; |
| 60 | } |
| 61 | unsigned &getOrInsertVirt2PhysRegMapSlot(unsigned VirtReg) { |
| 62 | assert(VirtReg >= MRegisterInfo::FirstVirtualRegister &&"Illegal VREG #"); |
| 63 | if (VirtReg-MRegisterInfo::FirstVirtualRegister >= Virt2PhysRegMap.size()) |
| 64 | Virt2PhysRegMap.resize(VirtReg-MRegisterInfo::FirstVirtualRegister+1); |
| 65 | return Virt2PhysRegMap[VirtReg-MRegisterInfo::FirstVirtualRegister]; |
| 66 | } |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 67 | |
Chris Lattner | 64667b6 | 2004-02-09 01:26:13 +0000 | [diff] [blame] | 68 | // PhysRegsUsed - This array is effectively a map, containing entries for |
| 69 | // each physical register that currently has a value (ie, it is in |
| 70 | // Virt2PhysRegMap). The value mapped to is the virtual register |
| 71 | // corresponding to the physical register (the inverse of the |
| 72 | // Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned |
| 73 | // because it is used by a future instruction. If the entry for a physical |
| 74 | // register is -1, then the physical register is "not in the map". |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 75 | // |
Chris Lattner | 64667b6 | 2004-02-09 01:26:13 +0000 | [diff] [blame] | 76 | int PhysRegsUsed[MRegisterInfo::FirstVirtualRegister]; |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 77 | |
| 78 | // PhysRegsUseOrder - This contains a list of the physical registers that |
| 79 | // currently have a virtual register value in them. This list provides an |
| 80 | // ordering of registers, imposing a reallocation order. This list is only |
| 81 | // used if all registers are allocated and we have to spill one, in which |
| 82 | // case we spill the least recently used register. Entries at the front of |
| 83 | // the list are the least recently used registers, entries at the back are |
| 84 | // the most recently used. |
| 85 | // |
| 86 | std::vector<unsigned> PhysRegsUseOrder; |
| 87 | |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 88 | // VirtRegModified - This bitset contains information about which virtual |
| 89 | // registers need to be spilled back to memory when their registers are |
| 90 | // scavenged. If a virtual register has simply been rematerialized, there |
| 91 | // is no reason to spill it to memory when we need the register back. |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 92 | // |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 93 | std::vector<bool> VirtRegModified; |
| 94 | |
| 95 | void markVirtRegModified(unsigned Reg, bool Val = true) { |
Chris Lattner | ef09c63 | 2004-01-31 21:27:19 +0000 | [diff] [blame] | 96 | assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 97 | Reg -= MRegisterInfo::FirstVirtualRegister; |
| 98 | if (VirtRegModified.size() <= Reg) VirtRegModified.resize(Reg+1); |
| 99 | VirtRegModified[Reg] = Val; |
| 100 | } |
| 101 | |
| 102 | bool isVirtRegModified(unsigned Reg) const { |
Chris Lattner | ef09c63 | 2004-01-31 21:27:19 +0000 | [diff] [blame] | 103 | assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 104 | assert(Reg - MRegisterInfo::FirstVirtualRegister < VirtRegModified.size() |
| 105 | && "Illegal virtual register!"); |
| 106 | return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister]; |
| 107 | } |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 108 | |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 109 | void MarkPhysRegRecentlyUsed(unsigned Reg) { |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 110 | assert(!PhysRegsUseOrder.empty() && "No registers used!"); |
Chris Lattner | 0eb172c | 2002-12-24 00:04:55 +0000 | [diff] [blame] | 111 | if (PhysRegsUseOrder.back() == Reg) return; // Already most recently used |
| 112 | |
| 113 | for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i) |
| 114 | if (areRegsEqual(Reg, PhysRegsUseOrder[i-1])) { |
| 115 | unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from middle |
| 116 | PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1); |
| 117 | // Add it to the end of the list |
| 118 | PhysRegsUseOrder.push_back(RegMatch); |
| 119 | if (RegMatch == Reg) |
| 120 | return; // Found an exact match, exit early |
| 121 | } |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | public: |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 125 | virtual const char *getPassName() const { |
| 126 | return "Local Register Allocator"; |
| 127 | } |
| 128 | |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 129 | virtual void getAnalysisUsage(AnalysisUsage &AU) const { |
| 130 | if (!DisableKill) |
| 131 | AU.addRequired<LiveVariables>(); |
| 132 | AU.addRequiredID(PHIEliminationID); |
Alkis Evlogimenos | 4c08086 | 2003-12-18 22:40:24 +0000 | [diff] [blame] | 133 | AU.addRequiredID(TwoAddressInstructionPassID); |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 134 | MachineFunctionPass::getAnalysisUsage(AU); |
| 135 | } |
| 136 | |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 137 | private: |
| 138 | /// runOnMachineFunction - Register allocate the whole function |
| 139 | bool runOnMachineFunction(MachineFunction &Fn); |
| 140 | |
| 141 | /// AllocateBasicBlock - Register allocate the specified basic block. |
| 142 | void AllocateBasicBlock(MachineBasicBlock &MBB); |
| 143 | |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 144 | |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 145 | /// areRegsEqual - This method returns true if the specified registers are |
| 146 | /// related to each other. To do this, it checks to see if they are equal |
| 147 | /// or if the first register is in the alias set of the second register. |
| 148 | /// |
| 149 | bool areRegsEqual(unsigned R1, unsigned R2) const { |
| 150 | if (R1 == R2) return true; |
Alkis Evlogimenos | 73ff512 | 2003-10-08 05:20:08 +0000 | [diff] [blame] | 151 | for (const unsigned *AliasSet = RegInfo->getAliasSet(R2); |
| 152 | *AliasSet; ++AliasSet) { |
| 153 | if (*AliasSet == R1) return true; |
| 154 | } |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 155 | return false; |
| 156 | } |
| 157 | |
Chris Lattner | 580f9be | 2002-12-28 20:40:43 +0000 | [diff] [blame] | 158 | /// getStackSpaceFor - This returns the frame index of the specified virtual |
Chris Lattner | b8822ad | 2003-08-04 23:36:39 +0000 | [diff] [blame] | 159 | /// register on the stack, allocating space if necessary. |
Chris Lattner | 580f9be | 2002-12-28 20:40:43 +0000 | [diff] [blame] | 160 | int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 161 | |
Chris Lattner | b8822ad | 2003-08-04 23:36:39 +0000 | [diff] [blame] | 162 | /// removePhysReg - This method marks the specified physical register as no |
| 163 | /// longer being in use. |
| 164 | /// |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 165 | void removePhysReg(unsigned PhysReg); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 166 | |
| 167 | /// spillVirtReg - This method spills the value specified by PhysReg into |
| 168 | /// the virtual register slot specified by VirtReg. It then updates the RA |
| 169 | /// data structures to indicate the fact that PhysReg is now available. |
| 170 | /// |
| 171 | void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, |
| 172 | unsigned VirtReg, unsigned PhysReg); |
| 173 | |
Chris Lattner | c21be92 | 2002-12-16 17:44:42 +0000 | [diff] [blame] | 174 | /// spillPhysReg - This method spills the specified physical register into |
Chris Lattner | 128c2aa | 2003-08-17 18:01:15 +0000 | [diff] [blame] | 175 | /// the virtual register slot associated with it. If OnlyVirtRegs is set to |
| 176 | /// true, then the request is ignored if the physical register does not |
| 177 | /// contain a virtual register. |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 178 | /// |
Chris Lattner | c21be92 | 2002-12-16 17:44:42 +0000 | [diff] [blame] | 179 | void spillPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, |
Chris Lattner | 128c2aa | 2003-08-17 18:01:15 +0000 | [diff] [blame] | 180 | unsigned PhysReg, bool OnlyVirtRegs = false); |
Chris Lattner | c21be92 | 2002-12-16 17:44:42 +0000 | [diff] [blame] | 181 | |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 182 | /// assignVirtToPhysReg - This method updates local state so that we know |
| 183 | /// that PhysReg is the proper container for VirtReg now. The physical |
| 184 | /// register must not be used for anything else when this is called. |
| 185 | /// |
| 186 | void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg); |
| 187 | |
| 188 | /// liberatePhysReg - Make sure the specified physical register is available |
| 189 | /// for use. If there is currently a value in it, it is either moved out of |
| 190 | /// the way or spilled to memory. |
| 191 | /// |
| 192 | void liberatePhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, |
| 193 | unsigned PhysReg); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 194 | |
Chris Lattner | ae64043 | 2002-12-17 02:50:10 +0000 | [diff] [blame] | 195 | /// isPhysRegAvailable - Return true if the specified physical register is |
| 196 | /// free and available for use. This also includes checking to see if |
| 197 | /// aliased registers are all free... |
| 198 | /// |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 199 | bool isPhysRegAvailable(unsigned PhysReg) const; |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 200 | |
| 201 | /// getFreeReg - Look to see if there is a free register available in the |
| 202 | /// specified register class. If not, return 0. |
| 203 | /// |
| 204 | unsigned getFreeReg(const TargetRegisterClass *RC); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 205 | |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 206 | /// getReg - Find a physical register to hold the specified virtual |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 207 | /// register. If all compatible physical registers are used, this method |
| 208 | /// spills the last used virtual register to the stack, and uses that |
| 209 | /// register. |
| 210 | /// |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 211 | unsigned getReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, |
| 212 | unsigned VirtReg); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 213 | |
| 214 | /// reloadVirtReg - This method loads the specified virtual register into a |
| 215 | /// physical register, returning the physical register chosen. This updates |
| 216 | /// the regalloc data structures to reflect the fact that the virtual reg is |
| 217 | /// now alive in a physical register, and the previous one isn't. |
| 218 | /// |
| 219 | unsigned reloadVirtReg(MachineBasicBlock &MBB, |
| 220 | MachineBasicBlock::iterator &I, unsigned VirtReg); |
Chris Lattner | b8822ad | 2003-08-04 23:36:39 +0000 | [diff] [blame] | 221 | |
| 222 | void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, |
| 223 | unsigned PhysReg); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 224 | }; |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 225 | } |
| 226 | |
Chris Lattner | b8822ad | 2003-08-04 23:36:39 +0000 | [diff] [blame] | 227 | /// getStackSpaceFor - This allocates space for the specified virtual register |
| 228 | /// to be held on the stack. |
| 229 | int RA::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { |
| 230 | // Find the location Reg would belong... |
| 231 | std::map<unsigned, int>::iterator I =StackSlotForVirtReg.lower_bound(VirtReg); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 232 | |
Chris Lattner | 580f9be | 2002-12-28 20:40:43 +0000 | [diff] [blame] | 233 | if (I != StackSlotForVirtReg.end() && I->first == VirtReg) |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 234 | return I->second; // Already has space allocated? |
| 235 | |
Chris Lattner | 580f9be | 2002-12-28 20:40:43 +0000 | [diff] [blame] | 236 | // Allocate a new stack object for this spill location... |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 237 | int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 238 | |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 239 | // Assign the slot... |
Chris Lattner | 580f9be | 2002-12-28 20:40:43 +0000 | [diff] [blame] | 240 | StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx)); |
| 241 | return FrameIdx; |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 242 | } |
| 243 | |
Chris Lattner | ae64043 | 2002-12-17 02:50:10 +0000 | [diff] [blame] | 244 | |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 245 | /// removePhysReg - This method marks the specified physical register as no |
| 246 | /// longer being in use. |
| 247 | /// |
| 248 | void RA::removePhysReg(unsigned PhysReg) { |
Chris Lattner | 64667b6 | 2004-02-09 01:26:13 +0000 | [diff] [blame] | 249 | PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 250 | |
| 251 | std::vector<unsigned>::iterator It = |
| 252 | std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), PhysReg); |
Alkis Evlogimenos | 19b6486 | 2004-01-13 06:24:30 +0000 | [diff] [blame] | 253 | if (It != PhysRegsUseOrder.end()) |
| 254 | PhysRegsUseOrder.erase(It); |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 255 | } |
| 256 | |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 257 | |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 258 | /// spillVirtReg - This method spills the value specified by PhysReg into the |
| 259 | /// virtual register slot specified by VirtReg. It then updates the RA data |
| 260 | /// structures to indicate the fact that PhysReg is now available. |
| 261 | /// |
| 262 | void RA::spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, |
| 263 | unsigned VirtReg, unsigned PhysReg) { |
Chris Lattner | 8c81945 | 2003-08-05 04:13:58 +0000 | [diff] [blame] | 264 | if (!VirtReg && DisableKill) return; |
| 265 | assert(VirtReg && "Spilling a physical register is illegal!" |
Chris Lattner | d9ac6a7 | 2003-08-05 00:49:09 +0000 | [diff] [blame] | 266 | " Must not have appropriate kill for the register or use exists beyond" |
| 267 | " the intended one."); |
| 268 | DEBUG(std::cerr << " Spilling register " << RegInfo->getName(PhysReg); |
| 269 | std::cerr << " containing %reg" << VirtReg; |
| 270 | if (!isVirtRegModified(VirtReg)) |
| 271 | std::cerr << " which has not been modified, so no store necessary!"); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 272 | |
Chris Lattner | d9ac6a7 | 2003-08-05 00:49:09 +0000 | [diff] [blame] | 273 | // Otherwise, there is a virtual register corresponding to this physical |
| 274 | // register. We only need to spill it into its stack slot if it has been |
| 275 | // modified. |
| 276 | if (isVirtRegModified(VirtReg)) { |
| 277 | const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); |
| 278 | int FrameIndex = getStackSpaceFor(VirtReg, RC); |
| 279 | DEBUG(std::cerr << " to stack slot #" << FrameIndex); |
| 280 | RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC); |
| 281 | ++NumSpilled; // Update statistics |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 282 | } |
Chris Lattner | ecea563 | 2004-02-09 02:12:04 +0000 | [diff] [blame] | 283 | |
| 284 | getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 285 | |
Chris Lattner | b8822ad | 2003-08-04 23:36:39 +0000 | [diff] [blame] | 286 | DEBUG(std::cerr << "\n"); |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 287 | removePhysReg(PhysReg); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 288 | } |
| 289 | |
Chris Lattner | ae64043 | 2002-12-17 02:50:10 +0000 | [diff] [blame] | 290 | |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 291 | /// spillPhysReg - This method spills the specified physical register into the |
Chris Lattner | 128c2aa | 2003-08-17 18:01:15 +0000 | [diff] [blame] | 292 | /// virtual register slot associated with it. If OnlyVirtRegs is set to true, |
| 293 | /// then the request is ignored if the physical register does not contain a |
| 294 | /// virtual register. |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 295 | /// |
| 296 | void RA::spillPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, |
Chris Lattner | 128c2aa | 2003-08-17 18:01:15 +0000 | [diff] [blame] | 297 | unsigned PhysReg, bool OnlyVirtRegs) { |
Chris Lattner | 64667b6 | 2004-02-09 01:26:13 +0000 | [diff] [blame] | 298 | if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used! |
| 299 | if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs) |
| 300 | spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg); |
Alkis Evlogimenos | 73ff512 | 2003-10-08 05:20:08 +0000 | [diff] [blame] | 301 | } else { |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 302 | // If the selected register aliases any other registers, we must make |
| 303 | // sure that one of the aliases isn't alive... |
Alkis Evlogimenos | 73ff512 | 2003-10-08 05:20:08 +0000 | [diff] [blame] | 304 | for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); |
Chris Lattner | 64667b6 | 2004-02-09 01:26:13 +0000 | [diff] [blame] | 305 | *AliasSet; ++AliasSet) |
| 306 | if (PhysRegsUsed[*AliasSet] != -1) // Spill aliased register... |
| 307 | if (PhysRegsUsed[*AliasSet] || !OnlyVirtRegs) |
| 308 | spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet); |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 309 | } |
| 310 | } |
| 311 | |
| 312 | |
| 313 | /// assignVirtToPhysReg - This method updates local state so that we know |
| 314 | /// that PhysReg is the proper container for VirtReg now. The physical |
| 315 | /// register must not be used for anything else when this is called. |
| 316 | /// |
| 317 | void RA::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) { |
Chris Lattner | 64667b6 | 2004-02-09 01:26:13 +0000 | [diff] [blame] | 318 | assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!"); |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 319 | // Update information to note the fact that this register was just used, and |
| 320 | // it holds VirtReg. |
| 321 | PhysRegsUsed[PhysReg] = VirtReg; |
Chris Lattner | ecea563 | 2004-02-09 02:12:04 +0000 | [diff] [blame] | 322 | getOrInsertVirt2PhysRegMapSlot(VirtReg) = PhysReg; |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 323 | PhysRegsUseOrder.push_back(PhysReg); // New use of PhysReg |
| 324 | } |
| 325 | |
| 326 | |
Chris Lattner | ae64043 | 2002-12-17 02:50:10 +0000 | [diff] [blame] | 327 | /// isPhysRegAvailable - Return true if the specified physical register is free |
| 328 | /// and available for use. This also includes checking to see if aliased |
| 329 | /// registers are all free... |
| 330 | /// |
| 331 | bool RA::isPhysRegAvailable(unsigned PhysReg) const { |
Chris Lattner | 64667b6 | 2004-02-09 01:26:13 +0000 | [diff] [blame] | 332 | if (PhysRegsUsed[PhysReg] != -1) return false; |
Chris Lattner | ae64043 | 2002-12-17 02:50:10 +0000 | [diff] [blame] | 333 | |
| 334 | // If the selected register aliases any other allocated registers, it is |
| 335 | // not free! |
Alkis Evlogimenos | 73ff512 | 2003-10-08 05:20:08 +0000 | [diff] [blame] | 336 | for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); |
| 337 | *AliasSet; ++AliasSet) |
Chris Lattner | 64667b6 | 2004-02-09 01:26:13 +0000 | [diff] [blame] | 338 | if (PhysRegsUsed[*AliasSet] != -1) // Aliased register in use? |
Alkis Evlogimenos | 73ff512 | 2003-10-08 05:20:08 +0000 | [diff] [blame] | 339 | return false; // Can't use this reg then. |
Chris Lattner | ae64043 | 2002-12-17 02:50:10 +0000 | [diff] [blame] | 340 | return true; |
| 341 | } |
| 342 | |
| 343 | |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 344 | /// getFreeReg - Look to see if there is a free register available in the |
| 345 | /// specified register class. If not, return 0. |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 346 | /// |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 347 | unsigned RA::getFreeReg(const TargetRegisterClass *RC) { |
Chris Lattner | 580f9be | 2002-12-28 20:40:43 +0000 | [diff] [blame] | 348 | // Get iterators defining the range of registers that are valid to allocate in |
| 349 | // this class, which also specifies the preferred allocation order. |
| 350 | TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF); |
| 351 | TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF); |
Chris Lattner | ae64043 | 2002-12-17 02:50:10 +0000 | [diff] [blame] | 352 | |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 353 | for (; RI != RE; ++RI) |
| 354 | if (isPhysRegAvailable(*RI)) { // Is reg unused? |
| 355 | assert(*RI != 0 && "Cannot use register!"); |
| 356 | return *RI; // Found an unused register! |
| 357 | } |
| 358 | return 0; |
| 359 | } |
| 360 | |
| 361 | |
| 362 | /// liberatePhysReg - Make sure the specified physical register is available for |
| 363 | /// use. If there is currently a value in it, it is either moved out of the way |
| 364 | /// or spilled to memory. |
| 365 | /// |
| 366 | void RA::liberatePhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, |
| 367 | unsigned PhysReg) { |
| 368 | // FIXME: This code checks to see if a register is available, but it really |
| 369 | // wants to know if a reg is available BEFORE the instruction executes. If |
| 370 | // called after killed operands are freed, it runs the risk of reallocating a |
| 371 | // used operand... |
| 372 | #if 0 |
| 373 | if (isPhysRegAvailable(PhysReg)) return; // Already available... |
| 374 | |
| 375 | // Check to see if the register is directly used, not indirectly used through |
| 376 | // aliases. If aliased registers are the ones actually used, we cannot be |
| 377 | // sure that we will be able to save the whole thing if we do a reg-reg copy. |
Chris Lattner | 64667b6 | 2004-02-09 01:26:13 +0000 | [diff] [blame] | 378 | if (PhysRegsUsed[PhysReg] != -1) { |
| 379 | // The virtual register held... |
| 380 | unsigned VirtReg = PhysRegsUsed[PhysReg]->second; |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 381 | |
| 382 | // Check to see if there is a compatible register available. If so, we can |
| 383 | // move the value into the new register... |
| 384 | // |
| 385 | const TargetRegisterClass *RC = RegInfo->getRegClass(PhysReg); |
| 386 | if (unsigned NewReg = getFreeReg(RC)) { |
| 387 | // Emit the code to copy the value... |
| 388 | RegInfo->copyRegToReg(MBB, I, NewReg, PhysReg, RC); |
| 389 | |
| 390 | // Update our internal state to indicate that PhysReg is available and Reg |
| 391 | // isn't. |
Chris Lattner | ecea563 | 2004-02-09 02:12:04 +0000 | [diff] [blame] | 392 | getVirt2PhysRegMapSlot[VirtReg] = 0; |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 393 | removePhysReg(PhysReg); // Free the physreg |
| 394 | |
| 395 | // Move reference over to new register... |
| 396 | assignVirtToPhysReg(VirtReg, NewReg); |
| 397 | return; |
Chris Lattner | ae64043 | 2002-12-17 02:50:10 +0000 | [diff] [blame] | 398 | } |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 399 | } |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 400 | #endif |
| 401 | spillPhysReg(MBB, I, PhysReg); |
| 402 | } |
| 403 | |
| 404 | |
| 405 | /// getReg - Find a physical register to hold the specified virtual |
| 406 | /// register. If all compatible physical registers are used, this method spills |
| 407 | /// the last used virtual register to the stack, and uses that register. |
| 408 | /// |
| 409 | unsigned RA::getReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, |
| 410 | unsigned VirtReg) { |
| 411 | const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); |
| 412 | |
| 413 | // First check to see if we have a free register of the requested type... |
| 414 | unsigned PhysReg = getFreeReg(RC); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 415 | |
Chris Lattner | ae64043 | 2002-12-17 02:50:10 +0000 | [diff] [blame] | 416 | // If we didn't find an unused register, scavenge one now! |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 417 | if (PhysReg == 0) { |
Chris Lattner | c21be92 | 2002-12-16 17:44:42 +0000 | [diff] [blame] | 418 | assert(!PhysRegsUseOrder.empty() && "No allocated registers??"); |
Chris Lattner | ae64043 | 2002-12-17 02:50:10 +0000 | [diff] [blame] | 419 | |
| 420 | // Loop over all of the preallocated registers from the least recently used |
| 421 | // to the most recently used. When we find one that is capable of holding |
| 422 | // our register, use it. |
| 423 | for (unsigned i = 0; PhysReg == 0; ++i) { |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 424 | assert(i != PhysRegsUseOrder.size() && |
| 425 | "Couldn't find a register of the appropriate class!"); |
Chris Lattner | ae64043 | 2002-12-17 02:50:10 +0000 | [diff] [blame] | 426 | |
| 427 | unsigned R = PhysRegsUseOrder[i]; |
Chris Lattner | 41822c7 | 2003-08-23 23:49:42 +0000 | [diff] [blame] | 428 | |
| 429 | // We can only use this register if it holds a virtual register (ie, it |
| 430 | // can be spilled). Do not use it if it is an explicitly allocated |
| 431 | // physical register! |
Chris Lattner | 64667b6 | 2004-02-09 01:26:13 +0000 | [diff] [blame] | 432 | assert(PhysRegsUsed[R] != -1 && |
Chris Lattner | 41822c7 | 2003-08-23 23:49:42 +0000 | [diff] [blame] | 433 | "PhysReg in PhysRegsUseOrder, but is not allocated?"); |
| 434 | if (PhysRegsUsed[R]) { |
| 435 | // If the current register is compatible, use it. |
| 436 | if (RegInfo->getRegClass(R) == RC) { |
| 437 | PhysReg = R; |
| 438 | break; |
| 439 | } else { |
| 440 | // If one of the registers aliased to the current register is |
| 441 | // compatible, use it. |
Alkis Evlogimenos | 73ff512 | 2003-10-08 05:20:08 +0000 | [diff] [blame] | 442 | for (const unsigned *AliasSet = RegInfo->getAliasSet(R); |
| 443 | *AliasSet; ++AliasSet) { |
| 444 | if (RegInfo->getRegClass(*AliasSet) == RC) { |
| 445 | PhysReg = *AliasSet; // Take an aliased register |
| 446 | break; |
| 447 | } |
| 448 | } |
Chris Lattner | 41822c7 | 2003-08-23 23:49:42 +0000 | [diff] [blame] | 449 | } |
Chris Lattner | ae64043 | 2002-12-17 02:50:10 +0000 | [diff] [blame] | 450 | } |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 451 | } |
| 452 | |
Chris Lattner | ae64043 | 2002-12-17 02:50:10 +0000 | [diff] [blame] | 453 | assert(PhysReg && "Physical register not assigned!?!?"); |
| 454 | |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 455 | // At this point PhysRegsUseOrder[i] is the least recently used register of |
| 456 | // compatible register class. Spill it to memory and reap its remains. |
Chris Lattner | c21be92 | 2002-12-16 17:44:42 +0000 | [diff] [blame] | 457 | spillPhysReg(MBB, I, PhysReg); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 458 | } |
| 459 | |
| 460 | // Now that we know which register we need to assign this to, do it now! |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 461 | assignVirtToPhysReg(VirtReg, PhysReg); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 462 | return PhysReg; |
| 463 | } |
| 464 | |
Chris Lattner | ae64043 | 2002-12-17 02:50:10 +0000 | [diff] [blame] | 465 | |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 466 | /// reloadVirtReg - This method loads the specified virtual register into a |
| 467 | /// physical register, returning the physical register chosen. This updates the |
| 468 | /// regalloc data structures to reflect the fact that the virtual reg is now |
| 469 | /// alive in a physical register, and the previous one isn't. |
| 470 | /// |
| 471 | unsigned RA::reloadVirtReg(MachineBasicBlock &MBB, |
| 472 | MachineBasicBlock::iterator &I, |
| 473 | unsigned VirtReg) { |
Chris Lattner | ecea563 | 2004-02-09 02:12:04 +0000 | [diff] [blame] | 474 | if (unsigned PR = getOrInsertVirt2PhysRegMapSlot(VirtReg)) { |
| 475 | MarkPhysRegRecentlyUsed(PR); |
| 476 | return PR; // Already have this value available! |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 477 | } |
| 478 | |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 479 | unsigned PhysReg = getReg(MBB, I, VirtReg); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 480 | |
Chris Lattner | ff863ba | 2002-12-25 05:05:46 +0000 | [diff] [blame] | 481 | const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); |
Chris Lattner | 580f9be | 2002-12-28 20:40:43 +0000 | [diff] [blame] | 482 | int FrameIndex = getStackSpaceFor(VirtReg, RC); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 483 | |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 484 | markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded |
| 485 | |
Chris Lattner | b8822ad | 2003-08-04 23:36:39 +0000 | [diff] [blame] | 486 | DEBUG(std::cerr << " Reloading %reg" << VirtReg << " into " |
| 487 | << RegInfo->getName(PhysReg) << "\n"); |
| 488 | |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 489 | // Add move instruction(s) |
Chris Lattner | 580f9be | 2002-12-28 20:40:43 +0000 | [diff] [blame] | 490 | RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIndex, RC); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 491 | ++NumReloaded; // Update statistics |
| 492 | return PhysReg; |
| 493 | } |
| 494 | |
Chris Lattner | b8822ad | 2003-08-04 23:36:39 +0000 | [diff] [blame] | 495 | |
| 496 | |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 497 | void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { |
| 498 | // loop over each instruction |
| 499 | MachineBasicBlock::iterator I = MBB.begin(); |
| 500 | for (; I != MBB.end(); ++I) { |
| 501 | MachineInstr *MI = *I; |
Chris Lattner | 3501fea | 2003-01-14 22:00:31 +0000 | [diff] [blame] | 502 | const TargetInstrDescriptor &TID = TM->getInstrInfo().get(MI->getOpcode()); |
Chris Lattner | b8822ad | 2003-08-04 23:36:39 +0000 | [diff] [blame] | 503 | DEBUG(std::cerr << "\nStarting RegAlloc of: " << *MI; |
| 504 | std::cerr << " Regs have values: "; |
Chris Lattner | 64667b6 | 2004-02-09 01:26:13 +0000 | [diff] [blame] | 505 | for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i) |
| 506 | if (PhysRegsUsed[i] != -1) |
| 507 | std::cerr << "[" << RegInfo->getName(i) |
| 508 | << ",%reg" << PhysRegsUsed[i] << "] "; |
Chris Lattner | b8822ad | 2003-08-04 23:36:39 +0000 | [diff] [blame] | 509 | std::cerr << "\n"); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 510 | |
Chris Lattner | ae64043 | 2002-12-17 02:50:10 +0000 | [diff] [blame] | 511 | // Loop over the implicit uses, making sure that they are at the head of the |
| 512 | // use order list, so they don't get reallocated. |
Alkis Evlogimenos | 73ff512 | 2003-10-08 05:20:08 +0000 | [diff] [blame] | 513 | for (const unsigned *ImplicitUses = TID.ImplicitUses; |
| 514 | *ImplicitUses; ++ImplicitUses) |
Chris Lattner | ecea563 | 2004-02-09 02:12:04 +0000 | [diff] [blame] | 515 | MarkPhysRegRecentlyUsed(*ImplicitUses); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 516 | |
Brian Gaeke | 53b99a0 | 2003-08-15 21:19:25 +0000 | [diff] [blame] | 517 | // Get the used operands into registers. This has the potential to spill |
Chris Lattner | b8822ad | 2003-08-04 23:36:39 +0000 | [diff] [blame] | 518 | // incoming values if we are out of registers. Note that we completely |
| 519 | // ignore physical register uses here. We assume that if an explicit |
| 520 | // physical register is referenced by the instruction, that it is guaranteed |
| 521 | // to be live-in, or the input is badly hosed. |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 522 | // |
| 523 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) |
Alkis Evlogimenos | 4d7af65 | 2003-12-14 13:24:17 +0000 | [diff] [blame] | 524 | if (MI->getOperand(i).isUse() && |
| 525 | !MI->getOperand(i).isDef() && |
| 526 | MI->getOperand(i).isVirtualRegister()){ |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 527 | unsigned VirtSrcReg = MI->getOperand(i).getAllocatedRegNum(); |
| 528 | unsigned PhysSrcReg = reloadVirtReg(MBB, I, VirtSrcReg); |
| 529 | MI->SetMachineOperandReg(i, PhysSrcReg); // Assign the input register |
| 530 | } |
| 531 | |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 532 | if (!DisableKill) { |
| 533 | // If this instruction is the last user of anything in registers, kill the |
| 534 | // value, freeing the register being used, so it doesn't need to be |
| 535 | // spilled to memory. |
| 536 | // |
| 537 | for (LiveVariables::killed_iterator KI = LV->killed_begin(MI), |
Chris Lattner | d572563 | 2003-05-12 03:54:14 +0000 | [diff] [blame] | 538 | KE = LV->killed_end(MI); KI != KE; ++KI) { |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 539 | unsigned VirtReg = KI->second; |
Chris Lattner | d572563 | 2003-05-12 03:54:14 +0000 | [diff] [blame] | 540 | unsigned PhysReg = VirtReg; |
Chris Lattner | ef09c63 | 2004-01-31 21:27:19 +0000 | [diff] [blame] | 541 | if (MRegisterInfo::isVirtualRegister(VirtReg)) { |
Chris Lattner | ecea563 | 2004-02-09 02:12:04 +0000 | [diff] [blame] | 542 | unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); |
| 543 | PhysReg = PhysRegSlot; |
| 544 | assert(PhysReg != 0); |
| 545 | PhysRegSlot = 0; |
Chris Lattner | d572563 | 2003-05-12 03:54:14 +0000 | [diff] [blame] | 546 | } |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 547 | |
Chris Lattner | d572563 | 2003-05-12 03:54:14 +0000 | [diff] [blame] | 548 | if (PhysReg) { |
Chris Lattner | b8822ad | 2003-08-04 23:36:39 +0000 | [diff] [blame] | 549 | DEBUG(std::cerr << " Last use of " << RegInfo->getName(PhysReg) |
| 550 | << "[%reg" << VirtReg <<"], removing it from live set\n"); |
Chris Lattner | d9ac6a7 | 2003-08-05 00:49:09 +0000 | [diff] [blame] | 551 | removePhysReg(PhysReg); |
Chris Lattner | d572563 | 2003-05-12 03:54:14 +0000 | [diff] [blame] | 552 | } |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 553 | } |
| 554 | } |
| 555 | |
| 556 | // Loop over all of the operands of the instruction, spilling registers that |
| 557 | // are defined, and marking explicit destinations in the PhysRegsUsed map. |
| 558 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) |
Alkis Evlogimenos | 4d7af65 | 2003-12-14 13:24:17 +0000 | [diff] [blame] | 559 | if (MI->getOperand(i).isDef() && |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 560 | MI->getOperand(i).isPhysicalRegister()) { |
| 561 | unsigned Reg = MI->getOperand(i).getAllocatedRegNum(); |
Chris Lattner | 128c2aa | 2003-08-17 18:01:15 +0000 | [diff] [blame] | 562 | spillPhysReg(MBB, I, Reg, true); // Spill any existing value in the reg |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 563 | PhysRegsUsed[Reg] = 0; // It is free and reserved now |
| 564 | PhysRegsUseOrder.push_back(Reg); |
Alkis Evlogimenos | 19b6486 | 2004-01-13 06:24:30 +0000 | [diff] [blame] | 565 | for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); |
| 566 | *AliasSet; ++AliasSet) { |
Chris Lattner | ecea563 | 2004-02-09 02:12:04 +0000 | [diff] [blame] | 567 | PhysRegsUseOrder.push_back(*AliasSet); |
| 568 | PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now |
Alkis Evlogimenos | 19b6486 | 2004-01-13 06:24:30 +0000 | [diff] [blame] | 569 | } |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 570 | } |
| 571 | |
| 572 | // Loop over the implicit defs, spilling them as well. |
Alkis Evlogimenos | efe995a | 2003-12-13 01:20:58 +0000 | [diff] [blame] | 573 | for (const unsigned *ImplicitDefs = TID.ImplicitDefs; |
| 574 | *ImplicitDefs; ++ImplicitDefs) { |
| 575 | unsigned Reg = *ImplicitDefs; |
| 576 | spillPhysReg(MBB, I, Reg); |
| 577 | PhysRegsUseOrder.push_back(Reg); |
| 578 | PhysRegsUsed[Reg] = 0; // It is free and reserved now |
Alkis Evlogimenos | 19b6486 | 2004-01-13 06:24:30 +0000 | [diff] [blame] | 579 | for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); |
| 580 | *AliasSet; ++AliasSet) { |
Chris Lattner | ecea563 | 2004-02-09 02:12:04 +0000 | [diff] [blame] | 581 | PhysRegsUseOrder.push_back(*AliasSet); |
| 582 | PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now |
Alkis Evlogimenos | 19b6486 | 2004-01-13 06:24:30 +0000 | [diff] [blame] | 583 | } |
Alkis Evlogimenos | efe995a | 2003-12-13 01:20:58 +0000 | [diff] [blame] | 584 | } |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 585 | |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 586 | // Okay, we have allocated all of the source operands and spilled any values |
| 587 | // that would be destroyed by defs of this instruction. Loop over the |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 588 | // implicit defs and assign them to a register, spilling incoming values if |
| 589 | // we need to scavenge a register. |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 590 | // |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 591 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) |
Alkis Evlogimenos | 4d7af65 | 2003-12-14 13:24:17 +0000 | [diff] [blame] | 592 | if (MI->getOperand(i).isDef() && |
| 593 | MI->getOperand(i).isVirtualRegister()) { |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 594 | unsigned DestVirtReg = MI->getOperand(i).getAllocatedRegNum(); |
| 595 | unsigned DestPhysReg; |
| 596 | |
Alkis Evlogimenos | 9af9dbd | 2003-12-18 13:08:52 +0000 | [diff] [blame] | 597 | // If DestVirtReg already has a value, use it. |
Chris Lattner | ecea563 | 2004-02-09 02:12:04 +0000 | [diff] [blame] | 598 | if (!(DestPhysReg = getOrInsertVirt2PhysRegMapSlot(DestVirtReg))) |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 599 | DestPhysReg = getReg(MBB, I, DestVirtReg); |
Chris Lattner | d572563 | 2003-05-12 03:54:14 +0000 | [diff] [blame] | 600 | markVirtRegModified(DestVirtReg); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 601 | MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register |
| 602 | } |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 603 | |
| 604 | if (!DisableKill) { |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 605 | // If this instruction defines any registers that are immediately dead, |
| 606 | // kill them now. |
| 607 | // |
| 608 | for (LiveVariables::killed_iterator KI = LV->dead_begin(MI), |
Chris Lattner | d572563 | 2003-05-12 03:54:14 +0000 | [diff] [blame] | 609 | KE = LV->dead_end(MI); KI != KE; ++KI) { |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 610 | unsigned VirtReg = KI->second; |
Chris Lattner | d572563 | 2003-05-12 03:54:14 +0000 | [diff] [blame] | 611 | unsigned PhysReg = VirtReg; |
Chris Lattner | ef09c63 | 2004-01-31 21:27:19 +0000 | [diff] [blame] | 612 | if (MRegisterInfo::isVirtualRegister(VirtReg)) { |
Chris Lattner | ecea563 | 2004-02-09 02:12:04 +0000 | [diff] [blame] | 613 | unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); |
| 614 | PhysReg = PhysRegSlot; |
| 615 | assert(PhysReg != 0); |
| 616 | PhysRegSlot = 0; |
Chris Lattner | d572563 | 2003-05-12 03:54:14 +0000 | [diff] [blame] | 617 | } |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 618 | |
Chris Lattner | d572563 | 2003-05-12 03:54:14 +0000 | [diff] [blame] | 619 | if (PhysReg) { |
Chris Lattner | b8822ad | 2003-08-04 23:36:39 +0000 | [diff] [blame] | 620 | DEBUG(std::cerr << " Register " << RegInfo->getName(PhysReg) |
| 621 | << " [%reg" << VirtReg |
| 622 | << "] is never used, removing it frame live list\n"); |
Chris Lattner | d572563 | 2003-05-12 03:54:14 +0000 | [diff] [blame] | 623 | removePhysReg(PhysReg); |
| 624 | } |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 625 | } |
| 626 | } |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 627 | } |
| 628 | |
| 629 | // Rewind the iterator to point to the first flow control instruction... |
Chris Lattner | 3501fea | 2003-01-14 22:00:31 +0000 | [diff] [blame] | 630 | const TargetInstrInfo &TII = TM->getInstrInfo(); |
Chris Lattner | 0416d2a | 2003-01-16 18:06:43 +0000 | [diff] [blame] | 631 | I = MBB.end(); |
Chris Lattner | 3501fea | 2003-01-14 22:00:31 +0000 | [diff] [blame] | 632 | while (I != MBB.begin() && TII.isTerminatorInstr((*(I-1))->getOpcode())) |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 633 | --I; |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 634 | |
| 635 | // Spill all physical registers holding virtual registers now. |
Chris Lattner | 64667b6 | 2004-02-09 01:26:13 +0000 | [diff] [blame] | 636 | for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i) |
| 637 | if (PhysRegsUsed[i] != -1) |
| 638 | if (unsigned VirtReg = PhysRegsUsed[i]) |
| 639 | spillVirtReg(MBB, I, VirtReg, i); |
| 640 | else |
| 641 | removePhysReg(i); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 642 | |
Chris Lattner | ecea563 | 2004-02-09 02:12:04 +0000 | [diff] [blame] | 643 | #ifndef NDEBUG |
| 644 | bool AllOk = true; |
| 645 | for (unsigned i = 0, e = Virt2PhysRegMap.size(); i != e; ++i) |
| 646 | if (unsigned PR = Virt2PhysRegMap[i]) { |
| 647 | std::cerr << "Register still mapped: " << i << " -> " << PR << "\n"; |
| 648 | AllOk = false; |
| 649 | } |
| 650 | assert(AllOk && "Virtual registers still in phys regs?"); |
| 651 | #endif |
Chris Lattner | 128c2aa | 2003-08-17 18:01:15 +0000 | [diff] [blame] | 652 | |
| 653 | // Clear any physical register which appear live at the end of the basic |
| 654 | // block, but which do not hold any virtual registers. e.g., the stack |
| 655 | // pointer. |
| 656 | PhysRegsUseOrder.clear(); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 657 | } |
| 658 | |
Chris Lattner | 86c69a6 | 2002-12-17 03:16:10 +0000 | [diff] [blame] | 659 | |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 660 | /// runOnMachineFunction - Register allocate the whole function |
| 661 | /// |
| 662 | bool RA::runOnMachineFunction(MachineFunction &Fn) { |
| 663 | DEBUG(std::cerr << "Machine Function " << "\n"); |
| 664 | MF = &Fn; |
Chris Lattner | 580f9be | 2002-12-28 20:40:43 +0000 | [diff] [blame] | 665 | TM = &Fn.getTarget(); |
| 666 | RegInfo = TM->getRegisterInfo(); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 667 | |
Chris Lattner | 64667b6 | 2004-02-09 01:26:13 +0000 | [diff] [blame] | 668 | memset(PhysRegsUsed, -1, RegInfo->getNumRegs()*sizeof(unsigned)); |
| 669 | |
Chris Lattner | ecea563 | 2004-02-09 02:12:04 +0000 | [diff] [blame] | 670 | // Reserve some space for a moderate number of registers. If we know what the |
| 671 | // max virtual register number was we could use that instead and save some |
| 672 | // runtime overhead... |
| 673 | Virt2PhysRegMap.resize(1024); |
| 674 | |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 675 | if (!DisableKill) |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 676 | LV = &getAnalysis<LiveVariables>(); |
Chris Lattner | 82bee0f | 2002-12-18 08:14:26 +0000 | [diff] [blame] | 677 | |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 678 | // Loop over all of the basic blocks, eliminating virtual register references |
| 679 | for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); |
| 680 | MBB != MBBe; ++MBB) |
| 681 | AllocateBasicBlock(*MBB); |
| 682 | |
Chris Lattner | 580f9be | 2002-12-28 20:40:43 +0000 | [diff] [blame] | 683 | StackSlotForVirtReg.clear(); |
Chris Lattner | 91a452b | 2003-01-13 00:25:40 +0000 | [diff] [blame] | 684 | VirtRegModified.clear(); |
Chris Lattner | ecea563 | 2004-02-09 02:12:04 +0000 | [diff] [blame] | 685 | Virt2PhysRegMap.clear(); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 686 | return true; |
| 687 | } |
| 688 | |
Chris Lattner | ef09c63 | 2004-01-31 21:27:19 +0000 | [diff] [blame] | 689 | FunctionPass *llvm::createLocalRegisterAllocator() { |
Chris Lattner | 580f9be | 2002-12-28 20:40:43 +0000 | [diff] [blame] | 690 | return new RA(); |
Chris Lattner | b74e83c | 2002-12-16 16:15:28 +0000 | [diff] [blame] | 691 | } |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 692 | |