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Chris Lattner97f06932009-10-19 20:20:46 +00001//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2//
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00006// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a printer that converts from our internal representation
11// of machine-dependent LLVM code to GAS-format ARM assembly language.
12//
13//===----------------------------------------------------------------------===//
14
Chris Lattner95b2c7d2006-12-19 22:59:26 +000015#define DEBUG_TYPE "asm-printer"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000016#include "ARM.h"
Jim Grosbachbaf120f2010-12-01 03:45:07 +000017#include "ARMAsmPrinter.h"
Evan Chengb72d2a92011-01-11 21:46:47 +000018#include "ARMAddressingModes.h"
19#include "ARMBuildAttrs.h"
20#include "ARMBaseRegisterInfo.h"
21#include "ARMConstantPoolValue.h"
Chris Lattner97f06932009-10-19 20:20:46 +000022#include "ARMMachineFunctionInfo.h"
Evan Cheng5de5d4b2011-01-17 08:03:18 +000023#include "ARMMCExpr.h"
Chris Lattner97f06932009-10-19 20:20:46 +000024#include "ARMTargetMachine.h"
Jason W Kim17b443d2010-10-11 23:01:44 +000025#include "ARMTargetObjectFile.h"
Evan Chengb72d2a92011-01-11 21:46:47 +000026#include "InstPrinter/ARMInstPrinter.h"
Dale Johannesen3f282aa2010-04-26 20:07:31 +000027#include "llvm/Analysis/DebugInfo.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000028#include "llvm/Constants.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000029#include "llvm/Module.h"
Benjamin Kramere55b15f2009-12-28 12:27:56 +000030#include "llvm/Type.h"
Dan Gohmancf20ac42009-08-13 01:36:44 +000031#include "llvm/Assembly/Writer.h"
Chris Lattnerb0f294c2009-10-19 18:38:33 +000032#include "llvm/CodeGen/MachineModuleInfoImpls.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000033#include "llvm/CodeGen/MachineFunctionPass.h"
Evan Chenga8e29892007-01-19 07:51:42 +000034#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattnerb0f294c2009-10-19 18:38:33 +000035#include "llvm/MC/MCAsmInfo.h"
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000036#include "llvm/MC/MCAssembler.h"
Chris Lattnerb0f294c2009-10-19 18:38:33 +000037#include "llvm/MC/MCContext.h"
Bill Wendlingbecd83e2010-03-09 00:40:17 +000038#include "llvm/MC/MCExpr.h"
Chris Lattner97f06932009-10-19 20:20:46 +000039#include "llvm/MC/MCInst.h"
Chris Lattnerf9bdedd2009-08-10 18:15:01 +000040#include "llvm/MC/MCSectionMachO.h"
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000041#include "llvm/MC/MCObjectStreamer.h"
Chris Lattner6c2f9e12009-08-19 05:49:37 +000042#include "llvm/MC/MCStreamer.h"
Chris Lattner325d3dc2009-09-13 17:14:04 +000043#include "llvm/MC/MCSymbol.h"
Chris Lattnerd62f1b42010-03-12 21:19:23 +000044#include "llvm/Target/Mangler.h"
Rafael Espindolab01c4bb2006-07-27 11:38:51 +000045#include "llvm/Target/TargetData.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000046#include "llvm/Target/TargetMachine.h"
Evan Cheng5be54b02007-01-19 19:25:36 +000047#include "llvm/Target/TargetOptions.h"
Daniel Dunbar51b198a2009-07-15 20:24:03 +000048#include "llvm/Target/TargetRegistry.h"
Evan Chengc324ecb2009-07-24 18:19:46 +000049#include "llvm/ADT/SmallPtrSet.h"
Jim Grosbachc40d9f92009-09-01 18:49:12 +000050#include "llvm/ADT/SmallString.h"
Bob Wilson54c78ef2009-11-06 23:33:28 +000051#include "llvm/ADT/StringExtras.h"
Chris Lattner97f06932009-10-19 20:20:46 +000052#include "llvm/Support/CommandLine.h"
Devang Patel59135f42010-08-04 22:39:39 +000053#include "llvm/Support/Debug.h"
Torok Edwin30464702009-07-08 20:55:50 +000054#include "llvm/Support/ErrorHandling.h"
Chris Lattnerb23569a2010-04-04 08:18:47 +000055#include "llvm/Support/raw_ostream.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000056#include <cctype>
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000057using namespace llvm;
58
Chris Lattner95b2c7d2006-12-19 22:59:26 +000059namespace {
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000060
61 // Per section and per symbol attributes are not supported.
62 // To implement them we would need the ability to delay this emission
63 // until the assembly file is fully parsed/generated as only then do we
64 // know the symbol and section numbers.
65 class AttributeEmitter {
66 public:
67 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
68 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
Jason W Kimf009a962011-02-07 00:49:53 +000069 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000070 virtual void Finish() = 0;
Rafael Espindola4921e232010-10-25 18:38:32 +000071 virtual ~AttributeEmitter() {}
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000072 };
73
74 class AsmAttributeEmitter : public AttributeEmitter {
75 MCStreamer &Streamer;
76
77 public:
78 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
79 void MaybeSwitchVendor(StringRef Vendor) { }
80
81 void EmitAttribute(unsigned Attribute, unsigned Value) {
82 Streamer.EmitRawText("\t.eabi_attribute " +
83 Twine(Attribute) + ", " + Twine(Value));
84 }
85
Jason W Kimf009a962011-02-07 00:49:53 +000086 void EmitTextAttribute(unsigned Attribute, StringRef String) {
87 switch (Attribute) {
88 case ARMBuildAttrs::CPU_name:
Jason W Kimc046d642011-02-07 19:07:11 +000089 Streamer.EmitRawText(StringRef("\t.cpu ") + LowercaseString(String));
Jason W Kimf009a962011-02-07 00:49:53 +000090 break;
Renato Golin728ff0d2011-02-28 22:04:27 +000091 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + LowercaseString(String));
95 break;
Jason W Kimf009a962011-02-07 00:49:53 +000096 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
97 }
98 }
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000099 void Finish() { }
100 };
101
102 class ObjectAttributeEmitter : public AttributeEmitter {
103 MCObjectStreamer &Streamer;
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000104 StringRef CurrentVendor;
105 SmallString<64> Contents;
106
107 public:
108 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
109 Streamer(Streamer_), CurrentVendor("") { }
110
111 void MaybeSwitchVendor(StringRef Vendor) {
112 assert(!Vendor.empty() && "Vendor cannot be empty.");
113
114 if (CurrentVendor.empty())
115 CurrentVendor = Vendor;
116 else if (CurrentVendor == Vendor)
117 return;
118 else
119 Finish();
120
121 CurrentVendor = Vendor;
122
Rafael Espindola33363842010-10-25 22:26:55 +0000123 assert(Contents.size() == 0);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000124 }
125
126 void EmitAttribute(unsigned Attribute, unsigned Value) {
127 // FIXME: should be ULEB
128 Contents += Attribute;
129 Contents += Value;
130 }
131
Jason W Kimf009a962011-02-07 00:49:53 +0000132 void EmitTextAttribute(unsigned Attribute, StringRef String) {
133 Contents += Attribute;
Jason W Kimc046d642011-02-07 19:07:11 +0000134 Contents += UppercaseString(String);
Jason W Kimf009a962011-02-07 00:49:53 +0000135 Contents += 0;
136 }
137
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000138 void Finish() {
Rafael Espindola33363842010-10-25 22:26:55 +0000139 const size_t ContentsSize = Contents.size();
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000140
Rafael Espindola33363842010-10-25 22:26:55 +0000141 // Vendor size + Vendor name + '\0'
142 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000143
Rafael Espindola33363842010-10-25 22:26:55 +0000144 // Tag + Tag Size
145 const size_t TagHeaderSize = 1 + 4;
146
147 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
148 Streamer.EmitBytes(CurrentVendor, 0);
149 Streamer.EmitIntValue(0, 1); // '\0'
150
151 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
152 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000153
154 Streamer.EmitBytes(Contents, 0);
Rafael Espindola33363842010-10-25 22:26:55 +0000155
156 Contents.clear();
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000157 }
158 };
159
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000160} // end of anonymous namespace
161
Jim Grosbachbaf120f2010-12-01 03:45:07 +0000162MachineLocation ARMAsmPrinter::
163getDebugValueLocation(const MachineInstr *MI) const {
164 MachineLocation Location;
165 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
166 // Frame address. Currently handles register +- offset only.
167 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
168 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
169 else {
170 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
171 }
172 return Location;
173}
174
Chris Lattner953ebb72010-01-27 23:58:11 +0000175void ARMAsmPrinter::EmitFunctionEntryLabel() {
176 if (AFI->isThumbFunction()) {
Jim Grosbachce792992010-11-05 22:08:08 +0000177 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
178 OutStreamer.EmitThumbFunc(Subtarget->isTargetDarwin()? CurrentFnSym : 0);
Chris Lattner953ebb72010-01-27 23:58:11 +0000179 }
Jim Grosbachb0739b72010-09-02 01:02:06 +0000180
Chris Lattner953ebb72010-01-27 23:58:11 +0000181 OutStreamer.EmitLabel(CurrentFnSym);
182}
183
Jim Grosbach2317e402010-09-30 01:57:53 +0000184/// runOnMachineFunction - This uses the EmitInstruction()
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000185/// method to print assembly for each instruction.
186///
187bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
Evan Chenga8e29892007-01-19 07:51:42 +0000188 AFI = MF.getInfo<ARMFunctionInfo>();
Evan Cheng6d63a722008-09-18 07:27:23 +0000189 MCP = MF.getConstantPool();
Rafael Espindola4b442b52006-05-23 02:48:20 +0000190
Chris Lattnerd49fe1b2010-01-28 01:28:58 +0000191 return AsmPrinter::runOnMachineFunction(MF);
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000192}
193
Evan Cheng055b0312009-06-29 07:51:04 +0000194void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
Chris Lattner35c33bd2010-04-04 04:47:45 +0000195 raw_ostream &O, const char *Modifier) {
Evan Cheng055b0312009-06-29 07:51:04 +0000196 const MachineOperand &MO = MI->getOperand(OpNum);
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000197 unsigned TF = MO.getTargetFlags();
198
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000199 switch (MO.getType()) {
Chris Lattner8bc86cb2009-10-19 20:59:55 +0000200 default:
201 assert(0 && "<unknown operand type>");
Bob Wilson5bafff32009-06-22 23:27:02 +0000202 case MachineOperand::MO_Register: {
203 unsigned Reg = MO.getReg();
Chris Lattner8bc86cb2009-10-19 20:59:55 +0000204 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
Jim Grosbach35636282010-10-06 21:22:32 +0000205 assert(!MO.getSubReg() && "Subregs should be eliminated!");
206 O << ARMInstPrinter::getRegisterName(Reg);
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000207 break;
Bob Wilson5bafff32009-06-22 23:27:02 +0000208 }
Evan Chenga8e29892007-01-19 07:51:42 +0000209 case MachineOperand::MO_Immediate: {
Evan Cheng5adb66a2009-09-28 09:14:39 +0000210 int64_t Imm = MO.getImm();
Anton Korobeynikov632606c2009-10-08 20:43:22 +0000211 O << '#';
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000212 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
Jason W Kim650b7d72011-01-12 23:21:49 +0000213 (TF == ARMII::MO_LO16))
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000214 O << ":lower16:";
215 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
Jason W Kim650b7d72011-01-12 23:21:49 +0000216 (TF == ARMII::MO_HI16))
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000217 O << ":upper16:";
Anton Korobeynikov632606c2009-10-08 20:43:22 +0000218 O << Imm;
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000219 break;
Evan Chenga8e29892007-01-19 07:51:42 +0000220 }
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000221 case MachineOperand::MO_MachineBasicBlock:
Chris Lattner1b2eb0e2010-03-13 21:04:28 +0000222 O << *MO.getMBB()->getSymbol();
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000223 return;
Rafael Espindola84b19be2006-07-16 01:02:57 +0000224 case MachineOperand::MO_GlobalAddress: {
Dan Gohman46510a72010-04-15 01:51:59 +0000225 const GlobalValue *GV = MO.getGlobal();
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000226 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
227 (TF & ARMII::MO_LO16))
228 O << ":lower16:";
229 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
230 (TF & ARMII::MO_HI16))
231 O << ":upper16:";
Chris Lattnerd62f1b42010-03-12 21:19:23 +0000232 O << *Mang->getSymbol(GV);
Anton Korobeynikov7751ad92008-11-22 16:15:34 +0000233
Chris Lattner0c08d092010-04-03 22:28:33 +0000234 printOffset(MO.getOffset(), O);
Jim Grosbach1d6111c2010-10-06 21:36:43 +0000235 if (TF == ARMII::MO_PLT)
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +0000236 O << "(PLT)";
Evan Chenga8e29892007-01-19 07:51:42 +0000237 break;
Rafael Espindola84b19be2006-07-16 01:02:57 +0000238 }
Evan Chenga8e29892007-01-19 07:51:42 +0000239 case MachineOperand::MO_ExternalSymbol: {
Chris Lattner10b318b2010-01-17 21:43:43 +0000240 O << *GetExternalSymbolSymbol(MO.getSymbolName());
Jim Grosbach1d6111c2010-10-06 21:36:43 +0000241 if (TF == ARMII::MO_PLT)
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +0000242 O << "(PLT)";
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000243 break;
Evan Chenga8e29892007-01-19 07:51:42 +0000244 }
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000245 case MachineOperand::MO_ConstantPoolIndex:
Chris Lattner1b46f432010-01-23 07:00:21 +0000246 O << *GetCPISymbol(MO.getIndex());
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000247 break;
Evan Chenga8e29892007-01-19 07:51:42 +0000248 case MachineOperand::MO_JumpTableIndex:
Chris Lattner1b46f432010-01-23 07:00:21 +0000249 O << *GetJTISymbol(MO.getIndex());
Evan Chenga8e29892007-01-19 07:51:42 +0000250 break;
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000251 }
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000252}
253
Evan Cheng055b0312009-06-29 07:51:04 +0000254//===--------------------------------------------------------------------===//
255
Chris Lattner0890cf12010-01-25 19:51:38 +0000256MCSymbol *ARMAsmPrinter::
257GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
258 const MachineBasicBlock *MBB) const {
259 SmallString<60> Name;
260 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
Chris Lattnerbfcb0962010-01-25 19:39:52 +0000261 << getFunctionNumber() << '_' << uid << '_' << uid2
Chris Lattner0890cf12010-01-25 19:51:38 +0000262 << "_set_" << MBB->getNumber();
Chris Lattner9b97a732010-03-30 18:10:53 +0000263 return OutContext.GetOrCreateSymbol(Name.str());
Chris Lattner0890cf12010-01-25 19:51:38 +0000264}
265
266MCSymbol *ARMAsmPrinter::
267GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
268 SmallString<60> Name;
269 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
Chris Lattner281e7762010-01-25 23:28:03 +0000270 << getFunctionNumber() << '_' << uid << '_' << uid2;
Chris Lattner9b97a732010-03-30 18:10:53 +0000271 return OutContext.GetOrCreateSymbol(Name.str());
Chris Lattnerbfcb0962010-01-25 19:39:52 +0000272}
273
Jim Grosbach433a5782010-09-24 20:47:58 +0000274
275MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
276 SmallString<60> Name;
277 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
278 << getFunctionNumber();
279 return OutContext.GetOrCreateSymbol(Name.str());
280}
281
Evan Cheng055b0312009-06-29 07:51:04 +0000282bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
Chris Lattnerc75c0282010-04-04 05:29:35 +0000283 unsigned AsmVariant, const char *ExtraCode,
284 raw_ostream &O) {
Evan Chenga8e29892007-01-19 07:51:42 +0000285 // Does this asm operand have a single letter operand modifier?
286 if (ExtraCode && ExtraCode[0]) {
287 if (ExtraCode[1] != 0) return true; // Unknown modifier.
Anton Korobeynikov8e9ece72009-08-08 23:10:41 +0000288
Evan Chenga8e29892007-01-19 07:51:42 +0000289 switch (ExtraCode[0]) {
290 default: return true; // Unknown modifier.
Bob Wilson9b4b00a2009-07-09 23:54:51 +0000291 case 'a': // Print as a memory address.
292 if (MI->getOperand(OpNum).isReg()) {
Jim Grosbach2f24c4e2010-09-30 15:25:22 +0000293 O << "["
294 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
295 << "]";
Bob Wilson9b4b00a2009-07-09 23:54:51 +0000296 return false;
297 }
298 // Fallthrough
299 case 'c': // Don't print "#" before an immediate operand.
Bob Wilson4f38b382009-08-21 21:58:55 +0000300 if (!MI->getOperand(OpNum).isImm())
301 return true;
Jim Grosbach2317e402010-09-30 01:57:53 +0000302 O << MI->getOperand(OpNum).getImm();
Bob Wilson8f343462009-04-06 21:46:51 +0000303 return false;
Evan Chenge21e3962007-04-04 00:13:29 +0000304 case 'P': // Print a VFP double precision register.
Evan Chengd831cda2009-12-08 23:06:22 +0000305 case 'q': // Print a NEON quad precision register.
Chris Lattner35c33bd2010-04-04 04:47:45 +0000306 printOperand(MI, OpNum, O);
Evan Cheng23a95702007-03-08 22:42:46 +0000307 return false;
Evan Chenga8e29892007-01-19 07:51:42 +0000308 case 'Q':
Bob Wilsond984eb62010-05-27 20:23:42 +0000309 case 'R':
Bob Wilsond984eb62010-05-27 20:23:42 +0000310 case 'H':
Bob Wilson9bb43e12010-12-17 23:06:42 +0000311 // These modifiers are not yet supported.
Bob Wilsond984eb62010-05-27 20:23:42 +0000312 return true;
Evan Cheng84f60b72010-05-27 22:08:38 +0000313 }
Evan Chenga8e29892007-01-19 07:51:42 +0000314 }
Jim Grosbache9952212009-09-04 01:38:51 +0000315
Chris Lattner35c33bd2010-04-04 04:47:45 +0000316 printOperand(MI, OpNum, O);
Evan Chenga8e29892007-01-19 07:51:42 +0000317 return false;
318}
319
Bob Wilson224c2442009-05-19 05:53:42 +0000320bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
Evan Cheng055b0312009-06-29 07:51:04 +0000321 unsigned OpNum, unsigned AsmVariant,
Chris Lattnerc75c0282010-04-04 05:29:35 +0000322 const char *ExtraCode,
323 raw_ostream &O) {
Bob Wilson224c2442009-05-19 05:53:42 +0000324 if (ExtraCode && ExtraCode[0])
325 return true; // Unknown modifier.
Bob Wilson765cc0b2009-10-13 20:50:28 +0000326
327 const MachineOperand &MO = MI->getOperand(OpNum);
328 assert(MO.isReg() && "unexpected inline asm memory operand");
Jim Grosbach2317e402010-09-30 01:57:53 +0000329 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
Bob Wilson224c2442009-05-19 05:53:42 +0000330 return false;
331}
332
Bob Wilson812209a2009-09-30 22:06:26 +0000333void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
Bob Wilson0fb34682009-09-30 00:23:42 +0000334 if (Subtarget->isTargetDarwin()) {
335 Reloc::Model RelocM = TM.getRelocationModel();
336 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
337 // Declare all the text sections up front (before the DWARF sections
338 // emitted by AsmPrinter::doInitialization) so the assembler will keep
339 // them together at the beginning of the object file. This helps
340 // avoid out-of-range branches that are due a fundamental limitation of
341 // the way symbol offsets are encoded with the current Darwin ARM
342 // relocations.
Jim Grosbachb0739b72010-09-02 01:02:06 +0000343 const TargetLoweringObjectFileMachO &TLOFMacho =
Dan Gohman0d805c32010-04-17 16:44:48 +0000344 static_cast<const TargetLoweringObjectFileMachO &>(
345 getObjFileLowering());
Bob Wilson29e06692009-09-30 22:25:37 +0000346 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
347 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
348 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
349 if (RelocM == Reloc::DynamicNoPIC) {
350 const MCSection *sect =
Chris Lattner22772212010-04-08 20:40:11 +0000351 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
352 MCSectionMachO::S_SYMBOL_STUBS,
353 12, SectionKind::getText());
Bob Wilson29e06692009-09-30 22:25:37 +0000354 OutStreamer.SwitchSection(sect);
355 } else {
356 const MCSection *sect =
Chris Lattner22772212010-04-08 20:40:11 +0000357 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
358 MCSectionMachO::S_SYMBOL_STUBS,
359 16, SectionKind::getText());
Bob Wilson29e06692009-09-30 22:25:37 +0000360 OutStreamer.SwitchSection(sect);
361 }
Bob Wilson63db5942010-07-30 19:55:47 +0000362 const MCSection *StaticInitSect =
363 OutContext.getMachOSection("__TEXT", "__StaticInit",
364 MCSectionMachO::S_REGULAR |
365 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
366 SectionKind::getText());
367 OutStreamer.SwitchSection(StaticInitSect);
Bob Wilson0fb34682009-09-30 00:23:42 +0000368 }
369 }
370
Jim Grosbache5165492009-11-09 00:11:35 +0000371 // Use unified assembler syntax.
Jason W Kimafd1cc22010-09-30 02:45:56 +0000372 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
Anton Korobeynikovd61eca52009-06-17 23:43:18 +0000373
Anton Korobeynikov88ce6672009-05-23 19:51:20 +0000374 // Emit ARM Build Attributes
375 if (Subtarget->isTargetELF()) {
Anton Korobeynikov88ce6672009-05-23 19:51:20 +0000376
Jason W Kimdef9ac42010-10-06 22:36:46 +0000377 emitAttributes();
Anton Korobeynikov88ce6672009-05-23 19:51:20 +0000378 }
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000379}
380
Anton Korobeynikov0f3cc652008-08-07 09:54:23 +0000381
Chris Lattner4a071d62009-10-19 17:59:19 +0000382void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
Evan Cheng5be54b02007-01-19 19:25:36 +0000383 if (Subtarget->isTargetDarwin()) {
Chris Lattnerf61159b2009-08-03 22:18:15 +0000384 // All darwin targets use mach-o.
Dan Gohman0d805c32010-04-17 16:44:48 +0000385 const TargetLoweringObjectFileMachO &TLOFMacho =
386 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000387 MachineModuleInfoMachO &MMIMacho =
388 MMI->getObjFileInfo<MachineModuleInfoMachO>();
Jim Grosbache9952212009-09-04 01:38:51 +0000389
Evan Chenga8e29892007-01-19 07:51:42 +0000390 // Output non-lazy-pointers for external and common global variables.
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000391 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
Bill Wendlingcebae362010-03-10 22:34:10 +0000392
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000393 if (!Stubs.empty()) {
Chris Lattnerff4bc462009-08-10 01:39:42 +0000394 // Switch with ".non_lazy_symbol_pointer" directive.
Chris Lattner6c2f9e12009-08-19 05:49:37 +0000395 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
Chris Lattnerc076a972009-08-10 18:01:34 +0000396 EmitAlignment(2);
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000397 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000398 // L_foo$stub:
399 OutStreamer.EmitLabel(Stubs[i].first);
400 // .indirect_symbol _foo
Bill Wendling52a50e52010-03-11 01:18:13 +0000401 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
402 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000403
Bill Wendling52a50e52010-03-11 01:18:13 +0000404 if (MCSym.getInt())
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000405 // External to current translation unit.
406 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
407 else
408 // Internal to current translation unit.
Bill Wendling5e1b55d2010-03-31 18:47:10 +0000409 //
Jim Grosbach1b935a32010-09-22 16:45:13 +0000410 // When we place the LSDA into the TEXT section, the type info
411 // pointers need to be indirect and pc-rel. We accomplish this by
412 // using NLPs; however, sometimes the types are local to the file.
413 // We need to fill in the value for the NLP in those cases.
Bill Wendling52a50e52010-03-11 01:18:13 +0000414 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
415 OutContext),
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000416 4/*size*/, 0/*addrspace*/);
Evan Chengae94e592008-12-05 01:06:39 +0000417 }
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000418
419 Stubs.clear();
420 OutStreamer.AddBlankLine();
Evan Chenga8e29892007-01-19 07:51:42 +0000421 }
422
Chris Lattnere4d9ea82009-10-19 18:44:38 +0000423 Stubs = MMIMacho.GetHiddenGVStubList();
424 if (!Stubs.empty()) {
Chris Lattner6c2f9e12009-08-19 05:49:37 +0000425 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
Chris Lattnerf3231de2009-08-10 18:02:16 +0000426 EmitAlignment(2);
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000427 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
428 // L_foo$stub:
429 OutStreamer.EmitLabel(Stubs[i].first);
430 // .long _foo
Bill Wendlingcebae362010-03-10 22:34:10 +0000431 OutStreamer.EmitValue(MCSymbolRefExpr::
432 Create(Stubs[i].second.getPointer(),
433 OutContext),
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000434 4/*size*/, 0/*addrspace*/);
435 }
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000436
437 Stubs.clear();
438 OutStreamer.AddBlankLine();
Evan Chengae94e592008-12-05 01:06:39 +0000439 }
440
Evan Chenga8e29892007-01-19 07:51:42 +0000441 // Funny Darwin hack: This flag tells the linker that no global symbols
442 // contain code that falls through to other global symbols (e.g. the obvious
443 // implementation of multiple entry points). If this doesn't occur, the
444 // linker can safely perform dead code stripping. Since LLVM never
445 // generates code that does this, it is always safe to set.
Chris Lattnera5ad93a2010-01-23 06:39:22 +0000446 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
Rafael Espindolab01c4bb2006-07-27 11:38:51 +0000447 }
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000448}
Anton Korobeynikov0bd89712008-08-17 13:55:10 +0000449
Chris Lattner97f06932009-10-19 20:20:46 +0000450//===----------------------------------------------------------------------===//
Jason W Kimdef9ac42010-10-06 22:36:46 +0000451// Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
452// FIXME:
453// The following seem like one-off assembler flags, but they actually need
Jim Grosbachfa7fb642010-10-06 22:46:47 +0000454// to appear in the .ARM.attributes section in ELF.
Jason W Kimdef9ac42010-10-06 22:36:46 +0000455// Instead of subclassing the MCELFStreamer, we do the work here.
456
457void ARMAsmPrinter::emitAttributes() {
Jim Grosbachfa7fb642010-10-06 22:46:47 +0000458
Jason W Kim17b443d2010-10-11 23:01:44 +0000459 emitARMAttributeSection();
460
Renato Golin728ff0d2011-02-28 22:04:27 +0000461 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
462 bool emitFPU = false;
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000463 AttributeEmitter *AttrEmitter;
Renato Golin728ff0d2011-02-28 22:04:27 +0000464 if (OutStreamer.hasRawTextSupport()) {
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000465 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
Renato Golin728ff0d2011-02-28 22:04:27 +0000466 emitFPU = true;
467 } else {
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000468 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
469 AttrEmitter = new ObjectAttributeEmitter(O);
470 }
471
472 AttrEmitter->MaybeSwitchVendor("aeabi");
473
Jason W Kimdef9ac42010-10-06 22:36:46 +0000474 std::string CPUString = Subtarget->getCPUString();
Jason W Kimf009a962011-02-07 00:49:53 +0000475
476 if (CPUString == "cortex-a8" ||
477 Subtarget->isCortexA8()) {
Jason W Kimc046d642011-02-07 19:07:11 +0000478 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
Jason W Kimf009a962011-02-07 00:49:53 +0000479 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
480 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
481 ARMBuildAttrs::ApplicationProfile);
482 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
483 ARMBuildAttrs::Allowed);
484 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
485 ARMBuildAttrs::AllowThumb32);
486 // Fixme: figure out when this is emitted.
487 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
488 // ARMBuildAttrs::AllowWMMXv1);
489 //
490
491 /// ADD additional Else-cases here!
492 } else if (CPUString == "generic") {
Dale Johannesen7179d1e2010-11-08 19:17:22 +0000493 // FIXME: Why these defaults?
494 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
Jason W Kimf009a962011-02-07 00:49:53 +0000495 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
496 ARMBuildAttrs::Allowed);
497 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
498 ARMBuildAttrs::Allowed);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000499 }
Jason W Kimdef9ac42010-10-06 22:36:46 +0000500
Renato Goline89a0532011-03-02 21:20:09 +0000501 if (Subtarget->hasNEON() && emitFPU) {
Renato Golin728ff0d2011-02-28 22:04:27 +0000502 /* NEON is not exactly a VFP architecture, but GAS emit one of
503 * neon/vfpv3/vfpv2 for .fpu parameters */
504 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
505 /* If emitted for NEON, omit from VFP below, since you can have both
506 * NEON and VFP in build attributes but only one .fpu */
507 emitFPU = false;
508 }
509
510 /* VFPv3 + .fpu */
511 if (Subtarget->hasVFP3()) {
512 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
513 ARMBuildAttrs::AllowFPv3A);
514 if (emitFPU)
515 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
516
517 /* VFPv2 + .fpu */
518 } else if (Subtarget->hasVFP2()) {
Jason W Kimf009a962011-02-07 00:49:53 +0000519 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
520 ARMBuildAttrs::AllowFPv2);
Renato Golin728ff0d2011-02-28 22:04:27 +0000521 if (emitFPU)
522 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
523 }
524
525 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
526 * since NEON can have 1 (allowed) or 2 (fused MAC operations) */
527 if (Subtarget->hasNEON()) {
528 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
529 ARMBuildAttrs::Allowed);
530 }
Jason W Kimdef9ac42010-10-06 22:36:46 +0000531
532 // Signal various FP modes.
533 if (!UnsafeFPMath) {
Jason W Kimf009a962011-02-07 00:49:53 +0000534 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
535 ARMBuildAttrs::Allowed);
536 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
537 ARMBuildAttrs::Allowed);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000538 }
539
540 if (NoInfsFPMath && NoNaNsFPMath)
Jason W Kimf009a962011-02-07 00:49:53 +0000541 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
542 ARMBuildAttrs::Allowed);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000543 else
Jason W Kimf009a962011-02-07 00:49:53 +0000544 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
545 ARMBuildAttrs::AllowIEE754);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000546
Jason W Kimf009a962011-02-07 00:49:53 +0000547 // FIXME: add more flags to ARMBuildAttrs.h
Jason W Kimdef9ac42010-10-06 22:36:46 +0000548 // 8-bytes alignment stuff.
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000549 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
550 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000551
552 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
553 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000554 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
555 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000556 }
557 // FIXME: Should we signal R9 usage?
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000558
Jason W Kimf009a962011-02-07 00:49:53 +0000559 if (Subtarget->hasDivide())
560 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000561
562 AttrEmitter->Finish();
563 delete AttrEmitter;
Jason W Kimdef9ac42010-10-06 22:36:46 +0000564}
565
Jason W Kim17b443d2010-10-11 23:01:44 +0000566void ARMAsmPrinter::emitARMAttributeSection() {
567 // <format-version>
568 // [ <section-length> "vendor-name"
569 // [ <file-tag> <size> <attribute>*
570 // | <section-tag> <size> <section-number>* 0 <attribute>*
571 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
572 // ]+
573 // ]*
574
575 if (OutStreamer.hasRawTextSupport())
576 return;
577
578 const ARMElfTargetObjectFile &TLOFELF =
579 static_cast<const ARMElfTargetObjectFile &>
580 (getObjFileLowering());
581
582 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
Jason W Kim17b443d2010-10-11 23:01:44 +0000583
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000584 // Format version
585 OutStreamer.EmitIntValue(0x41, 1);
Jason W Kim17b443d2010-10-11 23:01:44 +0000586}
587
Jason W Kimdef9ac42010-10-06 22:36:46 +0000588//===----------------------------------------------------------------------===//
Chris Lattner97f06932009-10-19 20:20:46 +0000589
Jim Grosbach988ce092010-09-18 00:05:05 +0000590static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
591 unsigned LabelId, MCContext &Ctx) {
592
593 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
594 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
595 return Label;
596}
597
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000598static MCSymbolRefExpr::VariantKind
599getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
600 switch (Modifier) {
601 default: llvm_unreachable("Unknown modifier!");
602 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
603 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
604 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
605 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
606 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
607 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
608 }
609 return MCSymbolRefExpr::VK_None;
610}
611
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000612MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
613 bool isIndirect = Subtarget->isTargetDarwin() &&
614 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
615 if (!isIndirect)
616 return Mang->getSymbol(GV);
617
618 // FIXME: Remove this when Darwin transition to @GOT like syntax.
619 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
620 MachineModuleInfoMachO &MMIMachO =
621 MMI->getObjFileInfo<MachineModuleInfoMachO>();
622 MachineModuleInfoImpl::StubValueTy &StubSym =
623 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
624 MMIMachO.getGVStubEntry(MCSym);
625 if (StubSym.getPointer() == 0)
626 StubSym = MachineModuleInfoImpl::
627 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
628 return MCSym;
629}
630
Jim Grosbach5df08d82010-11-09 18:45:04 +0000631void ARMAsmPrinter::
632EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
633 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
634
635 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000636
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000637 MCSymbol *MCSym;
Jim Grosbach5df08d82010-11-09 18:45:04 +0000638 if (ACPV->isLSDA()) {
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000639 SmallString<128> Str;
640 raw_svector_ostream OS(Str);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000641 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000642 MCSym = OutContext.GetOrCreateSymbol(OS.str());
Jim Grosbach5df08d82010-11-09 18:45:04 +0000643 } else if (ACPV->isBlockAddress()) {
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000644 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
Jim Grosbach5df08d82010-11-09 18:45:04 +0000645 } else if (ACPV->isGlobalValue()) {
646 const GlobalValue *GV = ACPV->getGV();
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000647 MCSym = GetARMGVSymbol(GV);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000648 } else {
649 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000650 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
Jim Grosbach5df08d82010-11-09 18:45:04 +0000651 }
652
653 // Create an MCSymbol for the reference.
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000654 const MCExpr *Expr =
655 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
656 OutContext);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000657
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000658 if (ACPV->getPCAdjustment()) {
659 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
660 getFunctionNumber(),
661 ACPV->getLabelId(),
662 OutContext);
663 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
664 PCRelExpr =
665 MCBinaryExpr::CreateAdd(PCRelExpr,
666 MCConstantExpr::Create(ACPV->getPCAdjustment(),
667 OutContext),
668 OutContext);
669 if (ACPV->mustAddCurrentAddress()) {
670 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
671 // label, so just emit a local label end reference that instead.
672 MCSymbol *DotSym = OutContext.CreateTempSymbol();
673 OutStreamer.EmitLabel(DotSym);
674 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
675 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000676 }
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000677 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000678 }
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000679 OutStreamer.EmitValue(Expr, Size);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000680}
681
Jim Grosbacha2244cb2010-09-22 17:39:48 +0000682void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
683 unsigned Opcode = MI->getOpcode();
684 int OpNum = 1;
685 if (Opcode == ARM::BR_JTadd)
686 OpNum = 2;
687 else if (Opcode == ARM::BR_JTm)
688 OpNum = 3;
689
690 const MachineOperand &MO1 = MI->getOperand(OpNum);
691 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
692 unsigned JTI = MO1.getIndex();
693
694 // Emit a label for the jump table.
695 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
696 OutStreamer.EmitLabel(JTISymbol);
697
698 // Emit each entry of the table.
699 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
700 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
701 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
702
703 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
704 MachineBasicBlock *MBB = JTBBs[i];
705 // Construct an MCExpr for the entry. We want a value of the form:
706 // (BasicBlockAddr - TableBeginAddr)
707 //
708 // For example, a table with entries jumping to basic blocks BB0 and BB1
709 // would look like:
710 // LJTI_0_0:
711 // .word (LBB0 - LJTI_0_0)
712 // .word (LBB1 - LJTI_0_0)
713 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
714
715 if (TM.getRelocationModel() == Reloc::PIC_)
716 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
717 OutContext),
718 OutContext);
719 OutStreamer.EmitValue(Expr, 4);
720 }
721}
722
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000723void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
724 unsigned Opcode = MI->getOpcode();
725 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
726 const MachineOperand &MO1 = MI->getOperand(OpNum);
727 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
728 unsigned JTI = MO1.getIndex();
729
730 // Emit a label for the jump table.
731 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
732 OutStreamer.EmitLabel(JTISymbol);
733
734 // Emit each entry of the table.
735 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
736 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
737 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000738 unsigned OffsetWidth = 4;
Jim Grosbachd092a872010-11-29 21:28:32 +0000739 if (MI->getOpcode() == ARM::t2TBB_JT)
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000740 OffsetWidth = 1;
Jim Grosbachd092a872010-11-29 21:28:32 +0000741 else if (MI->getOpcode() == ARM::t2TBH_JT)
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000742 OffsetWidth = 2;
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000743
744 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
745 MachineBasicBlock *MBB = JTBBs[i];
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000746 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
747 OutContext);
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000748 // If this isn't a TBB or TBH, the entries are direct branch instructions.
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000749 if (OffsetWidth == 4) {
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000750 MCInst BrInst;
751 BrInst.setOpcode(ARM::t2B);
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000752 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000753 OutStreamer.EmitInstruction(BrInst);
754 continue;
755 }
756 // Otherwise it's an offset from the dispatch instruction. Construct an
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000757 // MCExpr for the entry. We want a value of the form:
758 // (BasicBlockAddr - TableBeginAddr) / 2
759 //
760 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
761 // would look like:
762 // LJTI_0_0:
763 // .byte (LBB0 - LJTI_0_0) / 2
764 // .byte (LBB1 - LJTI_0_0) / 2
765 const MCExpr *Expr =
766 MCBinaryExpr::CreateSub(MBBSymbolExpr,
767 MCSymbolRefExpr::Create(JTISymbol, OutContext),
768 OutContext);
769 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
770 OutContext);
771 OutStreamer.EmitValue(Expr, OffsetWidth);
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000772 }
773}
774
Jim Grosbach2d0f53b2010-09-28 17:05:56 +0000775void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
776 raw_ostream &OS) {
777 unsigned NOps = MI->getNumOperands();
778 assert(NOps==4);
779 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
780 // cast away const; DIetc do not take const operands for some reason.
781 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
782 OS << V.getName();
783 OS << " <- ";
784 // Frame address. Currently handles register +- offset only.
785 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
786 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
787 OS << ']';
788 OS << "+";
789 printOperand(MI, NOps-2, OS);
790}
791
Jim Grosbach40edf732010-12-14 21:10:47 +0000792static void populateADROperands(MCInst &Inst, unsigned Dest,
793 const MCSymbol *Label,
794 unsigned pred, unsigned ccreg,
795 MCContext &Ctx) {
796 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
797 Inst.addOperand(MCOperand::CreateReg(Dest));
798 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
799 // Add predicate operands.
800 Inst.addOperand(MCOperand::CreateImm(pred));
801 Inst.addOperand(MCOperand::CreateReg(ccreg));
802}
803
Anton Korobeynikov4d728602011-01-01 20:38:38 +0000804void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
805 unsigned Opcode) {
806 MCInst TmpInst;
807
808 // Emit the instruction as usual, just patch the opcode.
809 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
810 TmpInst.setOpcode(Opcode);
811 OutStreamer.EmitInstruction(TmpInst);
812}
813
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000814void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
815 assert(MI->getFlag(MachineInstr::FrameSetup) &&
816 "Only instruction which are involved into frame setup code are allowed");
817
818 const MachineFunction &MF = *MI->getParent()->getParent();
819 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
820
821 unsigned FramePtr = RegInfo->getFrameRegister(MF);
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000822 unsigned Opc = MI->getOpcode();
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000823 unsigned SrcReg, DstReg;
824
Anton Korobeynikov3daccd82011-03-05 18:43:50 +0000825 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
826 // Two special cases:
827 // 1) tPUSH does not have src/dst regs.
828 // 2) for Thumb1 code we sometimes materialize the constant via constpool
829 // load. Yes, this is pretty fragile, but for now I don't see better
830 // way... :(
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000831 SrcReg = DstReg = ARM::SP;
832 } else {
Anton Korobeynikov3daccd82011-03-05 18:43:50 +0000833 SrcReg = MI->getOperand(1).getReg();
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000834 DstReg = MI->getOperand(0).getReg();
835 }
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000836
837 // Try to figure out the unwinding opcode out of src / dst regs.
838 if (MI->getDesc().mayStore()) {
839 // Register saves.
840 assert(DstReg == ARM::SP &&
841 "Only stack pointer as a destination reg is supported");
842
843 SmallVector<unsigned, 4> RegList;
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000844 // Skip src & dst reg, and pred ops.
845 unsigned StartOp = 2 + 2;
846 // Use all the operands.
847 unsigned NumOffset = 0;
848
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000849 switch (Opc) {
850 default:
851 MI->dump();
852 assert(0 && "Unsupported opcode for unwinding information");
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000853 case ARM::tPUSH:
854 // Special case here: no src & dst reg, but two extra imp ops.
855 StartOp = 2; NumOffset = 2;
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000856 case ARM::STMDB_UPD:
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000857 case ARM::t2STMDB_UPD:
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000858 case ARM::VSTMDDB_UPD:
859 assert(SrcReg == ARM::SP &&
860 "Only stack pointer as a source reg is supported");
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000861 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
862 i != NumOps; ++i)
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000863 RegList.push_back(MI->getOperand(i).getReg());
864 break;
865 case ARM::STR_PRE:
866 assert(MI->getOperand(2).getReg() == ARM::SP &&
867 "Only stack pointer as a source reg is supported");
868 RegList.push_back(SrcReg);
869 break;
870 }
871 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
872 } else {
873 // Changes of stack / frame pointer.
874 if (SrcReg == ARM::SP) {
875 int64_t Offset = 0;
876 switch (Opc) {
877 default:
878 MI->dump();
879 assert(0 && "Unsupported opcode for unwinding information");
880 case ARM::MOVr:
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000881 case ARM::tMOVgpr2gpr:
Anton Korobeynikov3daccd82011-03-05 18:43:50 +0000882 case ARM::tMOVgpr2tgpr:
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000883 Offset = 0;
884 break;
885 case ARM::ADDri:
886 Offset = -MI->getOperand(2).getImm();
887 break;
888 case ARM::SUBri:
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000889 case ARM::t2SUBrSPi:
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000890 Offset = MI->getOperand(2).getImm();
891 break;
Anton Korobeynikov7a764162011-03-05 18:43:43 +0000892 case ARM::tSUBspi:
893 Offset = MI->getOperand(2).getImm()*4;
894 break;
895 case ARM::tADDspi:
896 case ARM::tADDrSPi:
897 Offset = -MI->getOperand(2).getImm()*4;
898 break;
Anton Korobeynikov3daccd82011-03-05 18:43:50 +0000899 case ARM::tLDRpci:
900 assert(0 && "Not implemented yet!");
901 break;
Anton Korobeynikov57caad72011-03-05 18:43:32 +0000902 }
903
904 if (DstReg == FramePtr && FramePtr != ARM::SP)
905 // Set-up of the frame pointer.
906 OutStreamer.EmitSetFP(FramePtr, ARM::SP, Offset);
907 else if (DstReg == ARM::SP) {
908 // Change of SP by an offset. Positive values corresponds to "sub"
909 // instruction.
910 OutStreamer.EmitPad(Offset);
911 } else {
912 MI->dump();
913 assert(0 && "Unsupported opcode for unwinding information");
914 }
915 } else if (DstReg == ARM::SP) {
916 // FIXME: .movsp goes here
917 MI->dump();
918 assert(0 && "Unsupported opcode for unwinding information");
919 }
920 else {
921 MI->dump();
922 assert(0 && "Unsupported opcode for unwinding information");
923 }
924 }
925}
926
927extern cl::opt<bool> EnableARMEHABI;
928
Jim Grosbachb454cda2010-09-29 15:23:40 +0000929void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000930 unsigned Opc = MI->getOpcode();
931 switch (Opc) {
Chris Lattner4d152222009-10-19 22:23:04 +0000932 default: break;
Jim Grosbach9702e602010-12-09 01:22:19 +0000933 case ARM::t2ADDrSPi:
934 case ARM::t2ADDrSPi12:
935 case ARM::t2SUBrSPi:
936 case ARM::t2SUBrSPi12:
Jim Grosbach766a63d2010-12-09 01:23:51 +0000937 assert ((MI->getOperand(1).getReg() == ARM::SP) &&
938 "Unexpected source register!");
Jim Grosbach9702e602010-12-09 01:22:19 +0000939 break;
940
Chris Lattner112f2392010-11-14 20:31:06 +0000941 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
Jim Grosbach2d0f53b2010-09-28 17:05:56 +0000942 case ARM::DBG_VALUE: {
943 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
944 SmallString<128> TmpStr;
945 raw_svector_ostream OS(TmpStr);
946 PrintDebugValueComment(MI, OS);
947 OutStreamer.EmitRawText(StringRef(OS.str()));
948 }
949 return;
950 }
Jim Grosbach3efad8f2010-12-16 19:11:16 +0000951 case ARM::tBfar: {
952 MCInst TmpInst;
953 TmpInst.setOpcode(ARM::tBL);
954 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
955 MI->getOperand(0).getMBB()->getSymbol(), OutContext)));
956 OutStreamer.EmitInstruction(TmpInst);
957 return;
958 }
Jim Grosbach40edf732010-12-14 21:10:47 +0000959 case ARM::LEApcrel:
Jim Grosbachd40963c2010-12-14 22:28:03 +0000960 case ARM::tLEApcrel:
Jim Grosbach40edf732010-12-14 21:10:47 +0000961 case ARM::t2LEApcrel: {
Jim Grosbachdff84b02010-12-02 00:28:45 +0000962 // FIXME: Need to also handle globals and externals
Jim Grosbachdff84b02010-12-02 00:28:45 +0000963 MCInst TmpInst;
Jim Grosbachd40963c2010-12-14 22:28:03 +0000964 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
965 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
966 : ARM::ADR));
Jim Grosbach40edf732010-12-14 21:10:47 +0000967 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
968 GetCPISymbol(MI->getOperand(1).getIndex()),
969 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
970 OutContext);
Jim Grosbachdff84b02010-12-02 00:28:45 +0000971 OutStreamer.EmitInstruction(TmpInst);
972 return;
973 }
Jim Grosbachd40963c2010-12-14 22:28:03 +0000974 case ARM::LEApcrelJT:
975 case ARM::tLEApcrelJT:
976 case ARM::t2LEApcrelJT: {
Jim Grosbach5d14f9b2010-12-01 19:47:31 +0000977 MCInst TmpInst;
Jim Grosbachd40963c2010-12-14 22:28:03 +0000978 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
979 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
980 : ARM::ADR));
Jim Grosbach40edf732010-12-14 21:10:47 +0000981 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
982 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
983 MI->getOperand(2).getImm()),
984 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
985 OutContext);
Jim Grosbach5d14f9b2010-12-01 19:47:31 +0000986 OutStreamer.EmitInstruction(TmpInst);
987 return;
988 }
Jim Grosbach2e812e12010-11-30 18:56:36 +0000989 case ARM::MOVPCRX: {
990 MCInst TmpInst;
991 TmpInst.setOpcode(ARM::MOVr);
992 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
993 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
994 // Add predicate operands.
995 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
996 TmpInst.addOperand(MCOperand::CreateReg(0));
997 // Add 's' bit operand (always reg0 for this)
998 TmpInst.addOperand(MCOperand::CreateReg(0));
999 OutStreamer.EmitInstruction(TmpInst);
1000 return;
1001 }
Jim Grosbacha0d2c8a2010-11-30 18:30:19 +00001002 case ARM::BXr9_CALL:
1003 case ARM::BX_CALL: {
1004 {
1005 MCInst TmpInst;
1006 TmpInst.setOpcode(ARM::MOVr);
1007 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1008 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1009 // Add predicate operands.
1010 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1011 TmpInst.addOperand(MCOperand::CreateReg(0));
1012 // Add 's' bit operand (always reg0 for this)
1013 TmpInst.addOperand(MCOperand::CreateReg(0));
1014 OutStreamer.EmitInstruction(TmpInst);
1015 }
1016 {
1017 MCInst TmpInst;
1018 TmpInst.setOpcode(ARM::BX);
1019 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1020 OutStreamer.EmitInstruction(TmpInst);
1021 }
1022 return;
1023 }
1024 case ARM::BMOVPCRXr9_CALL:
1025 case ARM::BMOVPCRX_CALL: {
1026 {
1027 MCInst TmpInst;
1028 TmpInst.setOpcode(ARM::MOVr);
1029 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1030 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1031 // Add predicate operands.
1032 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1033 TmpInst.addOperand(MCOperand::CreateReg(0));
1034 // Add 's' bit operand (always reg0 for this)
1035 TmpInst.addOperand(MCOperand::CreateReg(0));
1036 OutStreamer.EmitInstruction(TmpInst);
1037 }
1038 {
1039 MCInst TmpInst;
1040 TmpInst.setOpcode(ARM::MOVr);
1041 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1042 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1043 // Add predicate operands.
1044 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1045 TmpInst.addOperand(MCOperand::CreateReg(0));
1046 // Add 's' bit operand (always reg0 for this)
1047 TmpInst.addOperand(MCOperand::CreateReg(0));
1048 OutStreamer.EmitInstruction(TmpInst);
1049 }
1050 return;
1051 }
Evan Cheng53519f02011-01-21 18:55:51 +00001052 case ARM::MOVi16_ga_pcrel:
1053 case ARM::t2MOVi16_ga_pcrel: {
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001054 MCInst TmpInst;
Evan Cheng53519f02011-01-21 18:55:51 +00001055 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001056 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1057
Evan Cheng53519f02011-01-21 18:55:51 +00001058 unsigned TF = MI->getOperand(1).getTargetFlags();
1059 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001060 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1061 MCSymbol *GVSym = GetARMGVSymbol(GV);
1062 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
Evan Cheng53519f02011-01-21 18:55:51 +00001063 if (isPIC) {
1064 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1065 getFunctionNumber(),
1066 MI->getOperand(2).getImm(), OutContext);
1067 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1068 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1069 const MCExpr *PCRelExpr =
1070 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1071 MCBinaryExpr::CreateAdd(LabelSymExpr,
1072 MCConstantExpr::Create(PCAdj, OutContext),
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001073 OutContext), OutContext), OutContext);
Evan Cheng53519f02011-01-21 18:55:51 +00001074 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1075 } else {
1076 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1077 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1078 }
1079
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001080 // Add predicate operands.
1081 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1082 TmpInst.addOperand(MCOperand::CreateReg(0));
1083 // Add 's' bit operand (always reg0 for this)
1084 TmpInst.addOperand(MCOperand::CreateReg(0));
1085 OutStreamer.EmitInstruction(TmpInst);
1086 return;
1087 }
Evan Cheng53519f02011-01-21 18:55:51 +00001088 case ARM::MOVTi16_ga_pcrel:
1089 case ARM::t2MOVTi16_ga_pcrel: {
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001090 MCInst TmpInst;
Evan Cheng53519f02011-01-21 18:55:51 +00001091 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1092 ? ARM::MOVTi16 : ARM::t2MOVTi16);
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001093 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1094 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1095
Evan Cheng53519f02011-01-21 18:55:51 +00001096 unsigned TF = MI->getOperand(2).getTargetFlags();
1097 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001098 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1099 MCSymbol *GVSym = GetARMGVSymbol(GV);
1100 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
Evan Cheng53519f02011-01-21 18:55:51 +00001101 if (isPIC) {
1102 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1103 getFunctionNumber(),
1104 MI->getOperand(3).getImm(), OutContext);
1105 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1106 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1107 const MCExpr *PCRelExpr =
1108 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1109 MCBinaryExpr::CreateAdd(LabelSymExpr,
1110 MCConstantExpr::Create(PCAdj, OutContext),
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001111 OutContext), OutContext), OutContext);
Evan Cheng53519f02011-01-21 18:55:51 +00001112 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1113 } else {
1114 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1115 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1116 }
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001117 // Add predicate operands.
1118 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1119 TmpInst.addOperand(MCOperand::CreateReg(0));
1120 // Add 's' bit operand (always reg0 for this)
1121 TmpInst.addOperand(MCOperand::CreateReg(0));
1122 OutStreamer.EmitInstruction(TmpInst);
1123 return;
1124 }
Jim Grosbachfbd18732010-09-17 23:41:53 +00001125 case ARM::tPICADD: {
1126 // This is a pseudo op for a label + instruction sequence, which looks like:
1127 // LPC0:
1128 // add r0, pc
1129 // This adds the address of LPC0 to r0.
1130
1131 // Emit the label.
Jim Grosbach988ce092010-09-18 00:05:05 +00001132 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1133 getFunctionNumber(), MI->getOperand(2).getImm(),
1134 OutContext));
Jim Grosbachfbd18732010-09-17 23:41:53 +00001135
1136 // Form and emit the add.
1137 MCInst AddInst;
1138 AddInst.setOpcode(ARM::tADDhirr);
1139 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1140 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1141 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1142 // Add predicate operands.
1143 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1144 AddInst.addOperand(MCOperand::CreateReg(0));
1145 OutStreamer.EmitInstruction(AddInst);
1146 return;
1147 }
Jim Grosbacha3fbadf2010-09-30 19:53:58 +00001148 case ARM::PICADD: {
Chris Lattner4d152222009-10-19 22:23:04 +00001149 // This is a pseudo op for a label + instruction sequence, which looks like:
1150 // LPC0:
1151 // add r0, pc, r0
1152 // This adds the address of LPC0 to r0.
Jim Grosbachb0739b72010-09-02 01:02:06 +00001153
Chris Lattner4d152222009-10-19 22:23:04 +00001154 // Emit the label.
Jim Grosbach988ce092010-09-18 00:05:05 +00001155 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1156 getFunctionNumber(), MI->getOperand(2).getImm(),
1157 OutContext));
Jim Grosbachb0739b72010-09-02 01:02:06 +00001158
Jim Grosbachf3f09522010-09-14 21:05:34 +00001159 // Form and emit the add.
Chris Lattner4d152222009-10-19 22:23:04 +00001160 MCInst AddInst;
1161 AddInst.setOpcode(ARM::ADDrr);
1162 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1163 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1164 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
Jim Grosbach5b46d622010-09-14 21:28:17 +00001165 // Add predicate operands.
1166 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1167 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1168 // Add 's' bit operand (always reg0 for this)
1169 AddInst.addOperand(MCOperand::CreateReg(0));
Chris Lattner850d2e22010-02-03 01:16:28 +00001170 OutStreamer.EmitInstruction(AddInst);
Chris Lattner4d152222009-10-19 22:23:04 +00001171 return;
1172 }
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001173 case ARM::PICSTR:
1174 case ARM::PICSTRB:
1175 case ARM::PICSTRH:
1176 case ARM::PICLDR:
1177 case ARM::PICLDRB:
1178 case ARM::PICLDRH:
1179 case ARM::PICLDRSB:
1180 case ARM::PICLDRSH: {
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001181 // This is a pseudo op for a label + instruction sequence, which looks like:
1182 // LPC0:
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001183 // OP r0, [pc, r0]
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001184 // The LCP0 label is referenced by a constant pool entry in order to get
1185 // a PC-relative address at the ldr instruction.
1186
1187 // Emit the label.
Jim Grosbach988ce092010-09-18 00:05:05 +00001188 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1189 getFunctionNumber(), MI->getOperand(2).getImm(),
1190 OutContext));
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001191
1192 // Form and emit the load
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001193 unsigned Opcode;
1194 switch (MI->getOpcode()) {
1195 default:
1196 llvm_unreachable("Unexpected opcode!");
Jim Grosbach7e3383c2010-10-27 23:12:14 +00001197 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1198 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001199 case ARM::PICSTRH: Opcode = ARM::STRH; break;
Jim Grosbach3e556122010-10-26 22:37:02 +00001200 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
Jim Grosbachc1d30212010-10-27 00:19:44 +00001201 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001202 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1203 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1204 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1205 }
1206 MCInst LdStInst;
1207 LdStInst.setOpcode(Opcode);
1208 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1209 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1210 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1211 LdStInst.addOperand(MCOperand::CreateImm(0));
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001212 // Add predicate operands.
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001213 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1214 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1215 OutStreamer.EmitInstruction(LdStInst);
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001216
1217 return;
1218 }
Jim Grosbacha3fbadf2010-09-30 19:53:58 +00001219 case ARM::CONSTPOOL_ENTRY: {
Chris Lattnera70e6442009-10-19 22:33:05 +00001220 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1221 /// in the function. The first operand is the ID# for this instruction, the
1222 /// second is the index into the MachineConstantPool that this is, the third
1223 /// is the size in bytes of this constant pool entry.
1224 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1225 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1226
1227 EmitAlignment(2);
Chris Lattner1b46f432010-01-23 07:00:21 +00001228 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
Chris Lattnera70e6442009-10-19 22:33:05 +00001229
1230 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1231 if (MCPE.isMachineConstantPoolEntry())
1232 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1233 else
1234 EmitGlobalConstant(MCPE.Val.ConstVal);
Jim Grosbachb0739b72010-09-02 01:02:06 +00001235
Chris Lattnera70e6442009-10-19 22:33:05 +00001236 return;
1237 }
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001238 case ARM::t2BR_JT: {
1239 // Lower and emit the instruction itself, then the jump table following it.
1240 MCInst TmpInst;
Jim Grosbach5ca66692010-11-29 22:37:40 +00001241 TmpInst.setOpcode(ARM::tMOVgpr2gpr);
1242 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1243 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1244 // Add predicate operands.
1245 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1246 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001247 OutStreamer.EmitInstruction(TmpInst);
Jim Grosbach5ca66692010-11-29 22:37:40 +00001248 // Output the data for the jump table itself
1249 EmitJump2Table(MI);
1250 return;
1251 }
1252 case ARM::t2TBB_JT: {
1253 // Lower and emit the instruction itself, then the jump table following it.
1254 MCInst TmpInst;
1255
1256 TmpInst.setOpcode(ARM::t2TBB);
1257 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1258 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1259 // Add predicate operands.
1260 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1261 TmpInst.addOperand(MCOperand::CreateReg(0));
1262 OutStreamer.EmitInstruction(TmpInst);
1263 // Output the data for the jump table itself
1264 EmitJump2Table(MI);
1265 // Make sure the next instruction is 2-byte aligned.
1266 EmitAlignment(1);
1267 return;
1268 }
1269 case ARM::t2TBH_JT: {
1270 // Lower and emit the instruction itself, then the jump table following it.
1271 MCInst TmpInst;
1272
1273 TmpInst.setOpcode(ARM::t2TBH);
1274 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1275 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1276 // Add predicate operands.
1277 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1278 TmpInst.addOperand(MCOperand::CreateReg(0));
1279 OutStreamer.EmitInstruction(TmpInst);
1280 // Output the data for the jump table itself
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001281 EmitJump2Table(MI);
1282 return;
1283 }
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001284 case ARM::tBR_JTr:
Jim Grosbach2dc77682010-11-29 18:37:44 +00001285 case ARM::BR_JTr: {
1286 // Lower and emit the instruction itself, then the jump table following it.
1287 // mov pc, target
1288 MCInst TmpInst;
Jim Grosbach5ca66692010-11-29 22:37:40 +00001289 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1290 ARM::MOVr : ARM::tMOVgpr2gpr;
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001291 TmpInst.setOpcode(Opc);
Jim Grosbach2dc77682010-11-29 18:37:44 +00001292 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1293 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1294 // Add predicate operands.
1295 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1296 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbacha0d2c8a2010-11-30 18:30:19 +00001297 // Add 's' bit operand (always reg0 for this)
1298 if (Opc == ARM::MOVr)
1299 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbach2dc77682010-11-29 18:37:44 +00001300 OutStreamer.EmitInstruction(TmpInst);
1301
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001302 // Make sure the Thumb jump table is 4-byte aligned.
Bill Wendlinga68a4fd2010-12-18 02:13:59 +00001303 if (Opc == ARM::tMOVgpr2gpr)
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001304 EmitAlignment(2);
1305
Jim Grosbach2dc77682010-11-29 18:37:44 +00001306 // Output the data for the jump table itself
1307 EmitJumpTable(MI);
1308 return;
1309 }
1310 case ARM::BR_JTm: {
1311 // Lower and emit the instruction itself, then the jump table following it.
1312 // ldr pc, target
1313 MCInst TmpInst;
1314 if (MI->getOperand(1).getReg() == 0) {
1315 // literal offset
1316 TmpInst.setOpcode(ARM::LDRi12);
1317 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1318 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1319 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1320 } else {
1321 TmpInst.setOpcode(ARM::LDRrs);
1322 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1323 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1324 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1325 TmpInst.addOperand(MCOperand::CreateImm(0));
1326 }
1327 // Add predicate operands.
1328 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1329 TmpInst.addOperand(MCOperand::CreateReg(0));
1330 OutStreamer.EmitInstruction(TmpInst);
1331
1332 // Output the data for the jump table itself
Jim Grosbacha2244cb2010-09-22 17:39:48 +00001333 EmitJumpTable(MI);
1334 return;
1335 }
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001336 case ARM::BR_JTadd: {
1337 // Lower and emit the instruction itself, then the jump table following it.
1338 // add pc, target, idx
Jim Grosbach2dc77682010-11-29 18:37:44 +00001339 MCInst TmpInst;
1340 TmpInst.setOpcode(ARM::ADDrr);
1341 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1342 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1343 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001344 // Add predicate operands.
Jim Grosbach2dc77682010-11-29 18:37:44 +00001345 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1346 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001347 // Add 's' bit operand (always reg0 for this)
Jim Grosbach2dc77682010-11-29 18:37:44 +00001348 TmpInst.addOperand(MCOperand::CreateReg(0));
1349 OutStreamer.EmitInstruction(TmpInst);
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001350
1351 // Output the data for the jump table itself
1352 EmitJumpTable(MI);
1353 return;
1354 }
Jim Grosbach2e6ae132010-09-23 18:05:37 +00001355 case ARM::TRAP: {
1356 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1357 // FIXME: Remove this special case when they do.
1358 if (!Subtarget->isTargetDarwin()) {
Jim Grosbach78890f42010-10-01 23:21:38 +00001359 //.long 0xe7ffdefe @ trap
Jim Grosbachb2dda4b2010-09-23 19:42:17 +00001360 uint32_t Val = 0xe7ffdefeUL;
Jim Grosbach2e6ae132010-09-23 18:05:37 +00001361 OutStreamer.AddComment("trap");
1362 OutStreamer.EmitIntValue(Val, 4);
1363 return;
1364 }
1365 break;
1366 }
1367 case ARM::tTRAP: {
1368 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1369 // FIXME: Remove this special case when they do.
1370 if (!Subtarget->isTargetDarwin()) {
Jim Grosbach78890f42010-10-01 23:21:38 +00001371 //.short 57086 @ trap
Benjamin Kramerc8ab9eb2010-09-23 18:57:26 +00001372 uint16_t Val = 0xdefe;
Jim Grosbach2e6ae132010-09-23 18:05:37 +00001373 OutStreamer.AddComment("trap");
1374 OutStreamer.EmitIntValue(Val, 2);
1375 return;
1376 }
1377 break;
1378 }
Jim Grosbach433a5782010-09-24 20:47:58 +00001379 case ARM::t2Int_eh_sjlj_setjmp:
1380 case ARM::t2Int_eh_sjlj_setjmp_nofp:
Jim Grosbacha3fbadf2010-09-30 19:53:58 +00001381 case ARM::tInt_eh_sjlj_setjmp: {
Jim Grosbach433a5782010-09-24 20:47:58 +00001382 // Two incoming args: GPR:$src, GPR:$val
1383 // mov $val, pc
1384 // adds $val, #7
1385 // str $val, [$src, #4]
1386 // movs r0, #0
1387 // b 1f
1388 // movs r0, #1
1389 // 1:
1390 unsigned SrcReg = MI->getOperand(0).getReg();
1391 unsigned ValReg = MI->getOperand(1).getReg();
1392 MCSymbol *Label = GetARMSJLJEHLabel();
1393 {
1394 MCInst TmpInst;
1395 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1396 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1397 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1398 // 's' bit operand
1399 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1400 OutStreamer.AddComment("eh_setjmp begin");
1401 OutStreamer.EmitInstruction(TmpInst);
1402 }
1403 {
1404 MCInst TmpInst;
1405 TmpInst.setOpcode(ARM::tADDi3);
1406 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1407 // 's' bit operand
1408 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1409 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1410 TmpInst.addOperand(MCOperand::CreateImm(7));
1411 // Predicate.
1412 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1413 TmpInst.addOperand(MCOperand::CreateReg(0));
1414 OutStreamer.EmitInstruction(TmpInst);
1415 }
1416 {
1417 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001418 TmpInst.setOpcode(ARM::tSTRi);
Jim Grosbach433a5782010-09-24 20:47:58 +00001419 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1420 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1421 // The offset immediate is #4. The operand value is scaled by 4 for the
1422 // tSTR instruction.
1423 TmpInst.addOperand(MCOperand::CreateImm(1));
Jim Grosbach433a5782010-09-24 20:47:58 +00001424 // Predicate.
1425 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1426 TmpInst.addOperand(MCOperand::CreateReg(0));
1427 OutStreamer.EmitInstruction(TmpInst);
1428 }
1429 {
1430 MCInst TmpInst;
1431 TmpInst.setOpcode(ARM::tMOVi8);
1432 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1433 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1434 TmpInst.addOperand(MCOperand::CreateImm(0));
1435 // Predicate.
1436 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1437 TmpInst.addOperand(MCOperand::CreateReg(0));
1438 OutStreamer.EmitInstruction(TmpInst);
1439 }
1440 {
1441 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1442 MCInst TmpInst;
1443 TmpInst.setOpcode(ARM::tB);
1444 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1445 OutStreamer.EmitInstruction(TmpInst);
1446 }
1447 {
1448 MCInst TmpInst;
1449 TmpInst.setOpcode(ARM::tMOVi8);
1450 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1451 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1452 TmpInst.addOperand(MCOperand::CreateImm(1));
1453 // Predicate.
1454 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1455 TmpInst.addOperand(MCOperand::CreateReg(0));
1456 OutStreamer.AddComment("eh_setjmp end");
1457 OutStreamer.EmitInstruction(TmpInst);
1458 }
1459 OutStreamer.EmitLabel(Label);
1460 return;
1461 }
1462
Jim Grosbach45390082010-09-23 23:33:56 +00001463 case ARM::Int_eh_sjlj_setjmp_nofp:
Jim Grosbacha3fbadf2010-09-30 19:53:58 +00001464 case ARM::Int_eh_sjlj_setjmp: {
Jim Grosbach45390082010-09-23 23:33:56 +00001465 // Two incoming args: GPR:$src, GPR:$val
1466 // add $val, pc, #8
1467 // str $val, [$src, #+4]
1468 // mov r0, #0
1469 // add pc, pc, #0
1470 // mov r0, #1
1471 unsigned SrcReg = MI->getOperand(0).getReg();
1472 unsigned ValReg = MI->getOperand(1).getReg();
1473
1474 {
1475 MCInst TmpInst;
1476 TmpInst.setOpcode(ARM::ADDri);
1477 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1478 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1479 TmpInst.addOperand(MCOperand::CreateImm(8));
1480 // Predicate.
1481 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1482 TmpInst.addOperand(MCOperand::CreateReg(0));
1483 // 's' bit operand (always reg0 for this).
1484 TmpInst.addOperand(MCOperand::CreateReg(0));
1485 OutStreamer.AddComment("eh_setjmp begin");
1486 OutStreamer.EmitInstruction(TmpInst);
1487 }
1488 {
1489 MCInst TmpInst;
Jim Grosbach7e3383c2010-10-27 23:12:14 +00001490 TmpInst.setOpcode(ARM::STRi12);
Jim Grosbach45390082010-09-23 23:33:56 +00001491 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1492 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach45390082010-09-23 23:33:56 +00001493 TmpInst.addOperand(MCOperand::CreateImm(4));
1494 // Predicate.
1495 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1496 TmpInst.addOperand(MCOperand::CreateReg(0));
1497 OutStreamer.EmitInstruction(TmpInst);
1498 }
1499 {
1500 MCInst TmpInst;
1501 TmpInst.setOpcode(ARM::MOVi);
1502 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1503 TmpInst.addOperand(MCOperand::CreateImm(0));
1504 // Predicate.
1505 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1506 TmpInst.addOperand(MCOperand::CreateReg(0));
1507 // 's' bit operand (always reg0 for this).
1508 TmpInst.addOperand(MCOperand::CreateReg(0));
1509 OutStreamer.EmitInstruction(TmpInst);
1510 }
1511 {
1512 MCInst TmpInst;
1513 TmpInst.setOpcode(ARM::ADDri);
1514 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1515 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1516 TmpInst.addOperand(MCOperand::CreateImm(0));
1517 // Predicate.
1518 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1519 TmpInst.addOperand(MCOperand::CreateReg(0));
1520 // 's' bit operand (always reg0 for this).
1521 TmpInst.addOperand(MCOperand::CreateReg(0));
1522 OutStreamer.EmitInstruction(TmpInst);
1523 }
1524 {
1525 MCInst TmpInst;
1526 TmpInst.setOpcode(ARM::MOVi);
1527 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1528 TmpInst.addOperand(MCOperand::CreateImm(1));
1529 // Predicate.
1530 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1531 TmpInst.addOperand(MCOperand::CreateReg(0));
1532 // 's' bit operand (always reg0 for this).
1533 TmpInst.addOperand(MCOperand::CreateReg(0));
1534 OutStreamer.AddComment("eh_setjmp end");
1535 OutStreamer.EmitInstruction(TmpInst);
1536 }
1537 return;
1538 }
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001539 case ARM::Int_eh_sjlj_longjmp: {
1540 // ldr sp, [$src, #8]
1541 // ldr $scratch, [$src, #4]
1542 // ldr r7, [$src]
1543 // bx $scratch
1544 unsigned SrcReg = MI->getOperand(0).getReg();
1545 unsigned ScratchReg = MI->getOperand(1).getReg();
1546 {
1547 MCInst TmpInst;
Jim Grosbach3e556122010-10-26 22:37:02 +00001548 TmpInst.setOpcode(ARM::LDRi12);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001549 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1550 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001551 TmpInst.addOperand(MCOperand::CreateImm(8));
1552 // Predicate.
1553 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1554 TmpInst.addOperand(MCOperand::CreateReg(0));
1555 OutStreamer.EmitInstruction(TmpInst);
1556 }
1557 {
1558 MCInst TmpInst;
Jim Grosbach3e556122010-10-26 22:37:02 +00001559 TmpInst.setOpcode(ARM::LDRi12);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001560 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1561 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001562 TmpInst.addOperand(MCOperand::CreateImm(4));
1563 // Predicate.
1564 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1565 TmpInst.addOperand(MCOperand::CreateReg(0));
1566 OutStreamer.EmitInstruction(TmpInst);
1567 }
1568 {
1569 MCInst TmpInst;
Jim Grosbach3e556122010-10-26 22:37:02 +00001570 TmpInst.setOpcode(ARM::LDRi12);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001571 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1572 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001573 TmpInst.addOperand(MCOperand::CreateImm(0));
1574 // Predicate.
1575 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1576 TmpInst.addOperand(MCOperand::CreateReg(0));
1577 OutStreamer.EmitInstruction(TmpInst);
1578 }
1579 {
1580 MCInst TmpInst;
Bill Wendling6e46d842010-11-30 00:48:15 +00001581 TmpInst.setOpcode(ARM::BX);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001582 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1583 // Predicate.
1584 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1585 TmpInst.addOperand(MCOperand::CreateReg(0));
1586 OutStreamer.EmitInstruction(TmpInst);
1587 }
1588 return;
1589 }
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001590 case ARM::tInt_eh_sjlj_longjmp: {
1591 // ldr $scratch, [$src, #8]
1592 // mov sp, $scratch
1593 // ldr $scratch, [$src, #4]
1594 // ldr r7, [$src]
1595 // bx $scratch
1596 unsigned SrcReg = MI->getOperand(0).getReg();
1597 unsigned ScratchReg = MI->getOperand(1).getReg();
1598 {
1599 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001600 TmpInst.setOpcode(ARM::tLDRi);
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001601 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1602 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1603 // The offset immediate is #8. The operand value is scaled by 4 for the
Bill Wendlingf4caf692010-12-14 03:36:38 +00001604 // tLDR instruction.
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001605 TmpInst.addOperand(MCOperand::CreateImm(2));
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001606 // Predicate.
1607 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1608 TmpInst.addOperand(MCOperand::CreateReg(0));
1609 OutStreamer.EmitInstruction(TmpInst);
1610 }
1611 {
1612 MCInst TmpInst;
1613 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1614 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1615 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1616 // Predicate.
1617 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1618 TmpInst.addOperand(MCOperand::CreateReg(0));
1619 OutStreamer.EmitInstruction(TmpInst);
1620 }
1621 {
1622 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001623 TmpInst.setOpcode(ARM::tLDRi);
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001624 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1625 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1626 TmpInst.addOperand(MCOperand::CreateImm(1));
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001627 // Predicate.
1628 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1629 TmpInst.addOperand(MCOperand::CreateReg(0));
1630 OutStreamer.EmitInstruction(TmpInst);
1631 }
1632 {
1633 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001634 TmpInst.setOpcode(ARM::tLDRr);
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001635 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1636 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001637 TmpInst.addOperand(MCOperand::CreateReg(0));
1638 // Predicate.
1639 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1640 TmpInst.addOperand(MCOperand::CreateReg(0));
1641 OutStreamer.EmitInstruction(TmpInst);
1642 }
1643 {
1644 MCInst TmpInst;
1645 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1646 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1647 // Predicate.
1648 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1649 TmpInst.addOperand(MCOperand::CreateReg(0));
1650 OutStreamer.EmitInstruction(TmpInst);
1651 }
1652 return;
1653 }
Anton Korobeynikov4d728602011-01-01 20:38:38 +00001654 // These are the pseudos created to comply with stricter operand restrictions
1655 // on ARMv5. Lower them now to "normal" instructions, since all the
1656 // restrictions are already satisfied.
1657 case ARM::MULv5:
1658 EmitPatchedInstruction(MI, ARM::MUL);
1659 return;
1660 case ARM::MLAv5:
1661 EmitPatchedInstruction(MI, ARM::MLA);
1662 return;
1663 case ARM::SMULLv5:
1664 EmitPatchedInstruction(MI, ARM::SMULL);
1665 return;
1666 case ARM::UMULLv5:
1667 EmitPatchedInstruction(MI, ARM::UMULL);
1668 return;
1669 case ARM::SMLALv5:
1670 EmitPatchedInstruction(MI, ARM::SMLAL);
1671 return;
1672 case ARM::UMLALv5:
1673 EmitPatchedInstruction(MI, ARM::UMLAL);
1674 return;
1675 case ARM::UMAALv5:
1676 EmitPatchedInstruction(MI, ARM::UMAAL);
1677 return;
Chris Lattner97f06932009-10-19 20:20:46 +00001678 }
Jim Grosbachb0739b72010-09-02 01:02:06 +00001679
Chris Lattner97f06932009-10-19 20:20:46 +00001680 MCInst TmpInst;
Chris Lattner30e2cc22010-11-14 21:00:02 +00001681 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001682
1683 // Emit unwinding stuff for frame-related instructions
1684 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1685 EmitUnwindingInstruction(MI);
1686
Chris Lattner850d2e22010-02-03 01:16:28 +00001687 OutStreamer.EmitInstruction(TmpInst);
Chris Lattner97f06932009-10-19 20:20:46 +00001688}
Daniel Dunbar2685a292009-10-20 05:15:36 +00001689
1690//===----------------------------------------------------------------------===//
1691// Target Registry Stuff
1692//===----------------------------------------------------------------------===//
1693
1694static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1695 unsigned SyntaxVariant,
Chris Lattnerd3740872010-04-04 05:04:31 +00001696 const MCAsmInfo &MAI) {
Daniel Dunbar2685a292009-10-20 05:15:36 +00001697 if (SyntaxVariant == 0)
Jim Grosbach74d7e6c2010-09-17 21:33:25 +00001698 return new ARMInstPrinter(MAI);
Daniel Dunbar2685a292009-10-20 05:15:36 +00001699 return 0;
1700}
1701
1702// Force static initialization.
1703extern "C" void LLVMInitializeARMAsmPrinter() {
1704 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1705 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1706
1707 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1708 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
1709}
1710