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Arnold Schwaighofer92226dd2007-10-12 21:53:12 +00001//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that X86 uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86.h"
Evan Cheng0cc39452006-01-16 21:21:29 +000016#include "X86InstrBuilder.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000017#include "X86ISelLowering.h"
18#include "X86TargetMachine.h"
19#include "llvm/CallingConv.h"
Evan Cheng223547a2006-01-31 22:28:30 +000020#include "llvm/Constants.h"
Evan Cheng347d5f72006-04-28 21:29:37 +000021#include "llvm/DerivedTypes.h"
Chris Lattnerb903bed2009-06-26 21:20:29 +000022#include "llvm/GlobalAlias.h"
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +000023#include "llvm/GlobalVariable.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000024#include "llvm/Function.h"
Evan Cheng6be2c582006-04-05 23:38:46 +000025#include "llvm/Intrinsics.h"
Evan Cheng14b32e12007-12-11 01:46:18 +000026#include "llvm/ADT/BitVector.h"
Evan Cheng30b37b52006-03-13 23:18:16 +000027#include "llvm/ADT/VectorExtras.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000028#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Cheng4a460802006-01-11 00:33:36 +000029#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
Evan Chenga844bde2008-02-02 04:07:54 +000031#include "llvm/CodeGen/MachineModuleInfo.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000032#include "llvm/CodeGen/MachineRegisterInfo.h"
Dan Gohman69de1932008-02-06 22:27:42 +000033#include "llvm/CodeGen/PseudoSourceValue.h"
Evan Chengef6ffb12006-01-31 03:14:29 +000034#include "llvm/Support/MathExtras.h"
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +000035#include "llvm/Support/Debug.h"
Torok Edwinab7c09b2009-07-08 18:01:40 +000036#include "llvm/Support/ErrorHandling.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000037#include "llvm/Target/TargetOptions.h"
Evan Cheng14b32e12007-12-11 01:46:18 +000038#include "llvm/ADT/SmallSet.h"
Chris Lattner1a60aa72006-10-31 19:42:44 +000039#include "llvm/ADT/StringExtras.h"
Mon P Wang3c81d352008-11-23 04:37:22 +000040#include "llvm/Support/CommandLine.h"
Torok Edwindac237e2009-07-08 20:53:28 +000041#include "llvm/Support/raw_ostream.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000042using namespace llvm;
43
Mon P Wang3c81d352008-11-23 04:37:22 +000044static cl::opt<bool>
Mon P Wang9f22a4a2008-11-24 02:10:43 +000045DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
Mon P Wang3c81d352008-11-23 04:37:22 +000046
Evan Cheng10e86422008-04-25 19:11:04 +000047// Forward declarations.
Nate Begeman9008ca62009-04-27 18:41:29 +000048static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
49 SDValue V2);
Evan Cheng10e86422008-04-25 19:11:04 +000050
Dan Gohmanc9f5f3f2008-05-14 01:58:56 +000051X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000052 : TargetLowering(TM) {
Evan Cheng559806f2006-01-27 08:10:46 +000053 Subtarget = &TM.getSubtarget<X86Subtarget>();
Dale Johannesenf1fc3a82007-09-23 14:52:20 +000054 X86ScalarSSEf64 = Subtarget->hasSSE2();
55 X86ScalarSSEf32 = Subtarget->hasSSE1();
Evan Cheng25ab6902006-09-08 06:48:29 +000056 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
Anton Korobeynikovbff66b02008-09-09 18:22:57 +000057
Anton Korobeynikov2365f512007-07-14 14:06:15 +000058 RegInfo = TM.getRegisterInfo();
Anton Korobeynikovbff66b02008-09-09 18:22:57 +000059 TD = getTargetData();
Anton Korobeynikov2365f512007-07-14 14:06:15 +000060
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000061 // Set up the TargetLowering object.
62
63 // X86 is weird, it always uses i8 for shift amounts and setcc results.
64 setShiftAmountType(MVT::i8);
Duncan Sands03228082008-11-23 15:47:28 +000065 setBooleanContents(ZeroOrOneBooleanContent);
Evan Cheng0b2afbd2006-01-25 09:15:17 +000066 setSchedulingPreference(SchedulingForRegPressure);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000067 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
Evan Cheng25ab6902006-09-08 06:48:29 +000068 setStackPointerRegisterToSaveRestore(X86StackPtr);
Evan Cheng714554d2006-03-16 21:47:42 +000069
Anton Korobeynikovd27a2582006-12-10 23:12:42 +000070 if (Subtarget->isTargetDarwin()) {
Evan Chengdf57fa02006-03-17 20:31:41 +000071 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
Anton Korobeynikovd27a2582006-12-10 23:12:42 +000072 setUseUnderscoreSetJmp(false);
73 setUseUnderscoreLongJmp(false);
Anton Korobeynikov317848f2007-01-03 11:43:14 +000074 } else if (Subtarget->isTargetMingw()) {
Anton Korobeynikovd27a2582006-12-10 23:12:42 +000075 // MS runtime is weird: it exports _setjmp, but longjmp!
76 setUseUnderscoreSetJmp(true);
77 setUseUnderscoreLongJmp(false);
78 } else {
79 setUseUnderscoreSetJmp(true);
80 setUseUnderscoreLongJmp(true);
81 }
Scott Michelfdc40a02009-02-17 22:15:04 +000082
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000083 // Set up the register classes.
Evan Cheng069287d2006-05-16 07:21:53 +000084 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
85 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
86 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
Evan Cheng25ab6902006-09-08 06:48:29 +000087 if (Subtarget->is64Bit())
88 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000089
Evan Cheng03294662008-10-14 21:26:46 +000090 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
Evan Chengc5484282006-10-04 00:56:09 +000091
Scott Michelfdc40a02009-02-17 22:15:04 +000092 // We don't accept any truncstore of integer registers.
Chris Lattnerddf89562008-01-17 19:59:44 +000093 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
94 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
95 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
96 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
97 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
Evan Cheng7f042682008-10-15 02:05:31 +000098 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
99
100 // SETOEQ and SETUNE require checking two conditions.
101 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
102 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
103 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
104 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
105 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
106 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
Chris Lattnerddf89562008-01-17 19:59:44 +0000107
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000108 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
109 // operation.
110 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
111 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
112 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
Evan Cheng6892f282006-01-17 02:32:49 +0000113
Evan Cheng25ab6902006-09-08 06:48:29 +0000114 if (Subtarget->is64Bit()) {
Evan Cheng6892f282006-01-17 02:32:49 +0000115 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
Bill Wendling105be5a2009-03-13 08:41:47 +0000116 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
Eli Friedman948e95a2009-05-23 09:59:16 +0000117 } else if (!UseSoftFloat) {
118 if (X86ScalarSSEf64) {
Dale Johannesen1c15bf52008-10-21 20:50:01 +0000119 // We have an impenetrably clever algorithm for ui64->double only.
120 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
Bill Wendling105be5a2009-03-13 08:41:47 +0000121 }
Eli Friedman948e95a2009-05-23 09:59:16 +0000122 // We have an algorithm for SSE2, and we turn this into a 64-bit
123 // FILD for other targets.
124 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000125 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000126
127 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
128 // this operation.
129 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
130 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
Bill Wendling105be5a2009-03-13 08:41:47 +0000131
Devang Patel6a784892009-06-05 18:48:29 +0000132 if (!UseSoftFloat) {
Bill Wendling105be5a2009-03-13 08:41:47 +0000133 // SSE has no i16 to fp conversion, only i32
134 if (X86ScalarSSEf32) {
135 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
136 // f32 and f64 cases are Legal, f80 case is not
137 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
138 } else {
139 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
140 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
141 }
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000142 } else {
Bill Wendling105be5a2009-03-13 08:41:47 +0000143 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
144 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
Evan Cheng5298bcc2006-02-17 07:01:52 +0000145 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000146
Dale Johannesen73328d12007-09-19 23:55:34 +0000147 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
148 // are Legal, f80 is custom lowered.
149 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
150 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
Evan Cheng6dab0532006-01-30 08:02:57 +0000151
Evan Cheng02568ff2006-01-30 22:13:22 +0000152 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
153 // this operation.
154 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
155 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
156
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000157 if (X86ScalarSSEf32) {
Evan Cheng02568ff2006-01-30 22:13:22 +0000158 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000159 // f32 and f64 cases are Legal, f80 case is not
160 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
Evan Cheng02568ff2006-01-30 22:13:22 +0000161 } else {
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000162 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
Evan Cheng02568ff2006-01-30 22:13:22 +0000163 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000164 }
165
166 // Handle FP_TO_UINT by promoting the destination to a larger signed
167 // conversion.
168 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
169 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
170 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
171
Evan Cheng25ab6902006-09-08 06:48:29 +0000172 if (Subtarget->is64Bit()) {
173 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000174 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
Eli Friedman948e95a2009-05-23 09:59:16 +0000175 } else if (!UseSoftFloat) {
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000176 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
Evan Cheng25ab6902006-09-08 06:48:29 +0000177 // Expand FP_TO_UINT into a select.
178 // FIXME: We would like to use a Custom expander here eventually to do
179 // the optimal thing for SSE vs. the default expansion in the legalizer.
180 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
181 else
Eli Friedman948e95a2009-05-23 09:59:16 +0000182 // With SSE3 we can use fisttpll to convert to a signed i64; without
183 // SSE, we're stuck with a fistpll.
184 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000185 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000186
Chris Lattner399610a2006-12-05 18:22:22 +0000187 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000188 if (!X86ScalarSSEf64) {
Chris Lattnerf3597a12006-12-05 18:45:06 +0000189 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
190 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
191 }
Chris Lattner21f66852005-12-23 05:15:23 +0000192
Dan Gohmanb00ee212008-02-18 19:34:53 +0000193 // Scalar integer divide and remainder are lowered to use operations that
194 // produce two results, to match the available instructions. This exposes
195 // the two-result form to trivial CSE, which is able to combine x/y and x%y
196 // into a single instruction.
197 //
198 // Scalar integer multiply-high is also lowered to use two-result
199 // operations, to match the available instructions. However, plain multiply
200 // (low) operations are left as Legal, as there are single-result
201 // instructions for this in x86. Using the two-result multiply instructions
202 // when both high and low results are needed must be arranged by dagcombine.
Dan Gohman525178c2007-10-08 18:33:35 +0000203 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
204 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
205 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
206 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
207 setOperationAction(ISD::SREM , MVT::i8 , Expand);
208 setOperationAction(ISD::UREM , MVT::i8 , Expand);
Dan Gohman525178c2007-10-08 18:33:35 +0000209 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
210 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
211 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
212 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
213 setOperationAction(ISD::SREM , MVT::i16 , Expand);
214 setOperationAction(ISD::UREM , MVT::i16 , Expand);
Dan Gohman525178c2007-10-08 18:33:35 +0000215 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
216 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
217 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
218 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
219 setOperationAction(ISD::SREM , MVT::i32 , Expand);
220 setOperationAction(ISD::UREM , MVT::i32 , Expand);
Dan Gohman525178c2007-10-08 18:33:35 +0000221 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
222 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
223 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
224 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
225 setOperationAction(ISD::SREM , MVT::i64 , Expand);
226 setOperationAction(ISD::UREM , MVT::i64 , Expand);
Dan Gohmana37c9f72007-09-25 18:23:27 +0000227
Evan Chengc35497f2006-10-30 08:02:39 +0000228 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
Evan Cheng5298bcc2006-02-17 07:01:52 +0000229 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
Nate Begeman750ac1b2006-02-01 07:19:44 +0000230 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
231 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
Evan Cheng25ab6902006-09-08 06:48:29 +0000232 if (Subtarget->is64Bit())
Christopher Lambc59e5212007-08-10 21:48:46 +0000233 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
234 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
235 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000236 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
237 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
Chris Lattnerd1108222008-03-07 06:36:32 +0000238 setOperationAction(ISD::FREM , MVT::f32 , Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000239 setOperationAction(ISD::FREM , MVT::f64 , Expand);
Chris Lattnerd1108222008-03-07 06:36:32 +0000240 setOperationAction(ISD::FREM , MVT::f80 , Expand);
Dan Gohman1a024862008-01-31 00:41:03 +0000241 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
Scott Michelfdc40a02009-02-17 22:15:04 +0000242
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000243 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
Evan Cheng18efe262007-12-14 02:13:44 +0000244 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
245 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000246 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
Evan Cheng18efe262007-12-14 02:13:44 +0000247 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
248 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000249 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
Evan Cheng18efe262007-12-14 02:13:44 +0000250 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
251 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000252 if (Subtarget->is64Bit()) {
253 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
Evan Cheng18efe262007-12-14 02:13:44 +0000254 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
255 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000256 }
257
Andrew Lenharthb873ff32005-11-20 21:41:10 +0000258 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
Nate Begemand88fc032006-01-14 03:14:10 +0000259 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
Nate Begeman35ef9132006-01-11 21:21:00 +0000260
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000261 // These should be promoted to a larger select which is supported.
262 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
263 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000264 // X86 wants to expand cmov itself.
Evan Cheng5298bcc2006-02-17 07:01:52 +0000265 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
266 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
267 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
268 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000269 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
Evan Cheng5298bcc2006-02-17 07:01:52 +0000270 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
271 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
272 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
273 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
274 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000275 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000276 if (Subtarget->is64Bit()) {
277 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
278 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
279 }
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000280 // X86 ret instruction may pop stack.
Evan Cheng5298bcc2006-02-17 07:01:52 +0000281 setOperationAction(ISD::RET , MVT::Other, Custom);
Anton Korobeynikov260a6b82008-09-08 21:12:11 +0000282 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
Anton Korobeynikov2365f512007-07-14 14:06:15 +0000283
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000284 // Darwin ABI issue.
Evan Cheng7ccced62006-02-18 00:15:05 +0000285 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
Nate Begeman37efe672006-04-22 18:53:45 +0000286 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
Evan Cheng5298bcc2006-02-17 07:01:52 +0000287 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +0000288 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
Anton Korobeynikov6625eff2008-05-04 21:36:32 +0000289 if (Subtarget->is64Bit())
290 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
Bill Wendling056292f2008-09-16 21:48:12 +0000291 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000292 if (Subtarget->is64Bit()) {
293 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
294 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
295 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
Bill Wendling056292f2008-09-16 21:48:12 +0000296 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000297 }
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000298 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
Evan Cheng5298bcc2006-02-17 07:01:52 +0000299 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
300 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
301 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
Dan Gohman4c1fa612008-03-03 22:22:09 +0000302 if (Subtarget->is64Bit()) {
303 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
304 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
305 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
306 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000307
Evan Chengd2cde682008-03-10 19:38:10 +0000308 if (Subtarget->hasSSE1())
309 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
Evan Cheng27b7db52008-03-08 00:58:38 +0000310
Andrew Lenharthd497d9f2008-02-16 14:46:26 +0000311 if (!Subtarget->hasSSE2())
312 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
313
Mon P Wang63307c32008-05-05 19:05:59 +0000314 // Expand certain atomics
Dan Gohman0b1d4a72008-12-23 21:37:04 +0000315 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
316 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
317 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
318 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
Bill Wendling5bf1b4e2008-08-20 00:28:16 +0000319
Dan Gohman0b1d4a72008-12-23 21:37:04 +0000320 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
321 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
322 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
323 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
Andrew Lenharthd497d9f2008-02-16 14:46:26 +0000324
Dale Johannesen48c1bc22008-10-02 18:53:47 +0000325 if (!Subtarget->is64Bit()) {
Dan Gohman0b1d4a72008-12-23 21:37:04 +0000326 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
327 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
328 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
329 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
330 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
331 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
332 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
Dale Johannesen48c1bc22008-10-02 18:53:47 +0000333 }
334
Dan Gohman7f460202008-06-30 20:59:49 +0000335 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
336 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
Evan Cheng3c992d22006-03-07 02:02:57 +0000337 // FIXME - use subtarget debug flags
Anton Korobeynikovab4022f2006-10-31 08:31:24 +0000338 if (!Subtarget->isTargetDarwin() &&
339 !Subtarget->isTargetELF() &&
Dan Gohman44066042008-07-01 00:05:16 +0000340 !Subtarget->isTargetCygMing()) {
341 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
342 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
343 }
Chris Lattnerf73bae12005-11-29 06:16:21 +0000344
Anton Korobeynikovce3b4652007-05-02 19:53:33 +0000345 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
346 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
347 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
348 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
349 if (Subtarget->is64Bit()) {
Anton Korobeynikovce3b4652007-05-02 19:53:33 +0000350 setExceptionPointerRegister(X86::RAX);
351 setExceptionSelectorRegister(X86::RDX);
352 } else {
353 setExceptionPointerRegister(X86::EAX);
354 setExceptionSelectorRegister(X86::EDX);
355 }
Anton Korobeynikov38252622007-09-03 00:36:06 +0000356 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
Anton Korobeynikov260a6b82008-09-08 21:12:11 +0000357 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
358
Duncan Sandsf7331b32007-09-11 14:10:23 +0000359 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
Duncan Sandsb116fac2007-07-27 20:02:49 +0000360
Chris Lattnerda68d302008-01-15 21:58:22 +0000361 setOperationAction(ISD::TRAP, MVT::Other, Legal);
Anton Korobeynikov66fac792008-01-15 07:02:33 +0000362
Nate Begemanacc398c2006-01-25 18:21:52 +0000363 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
364 setOperationAction(ISD::VASTART , MVT::Other, Custom);
Nate Begemanacc398c2006-01-25 18:21:52 +0000365 setOperationAction(ISD::VAEND , MVT::Other, Expand);
Dan Gohman9018e832008-05-10 01:26:14 +0000366 if (Subtarget->is64Bit()) {
367 setOperationAction(ISD::VAARG , MVT::Other, Custom);
Evan Chengae642192007-03-02 23:16:35 +0000368 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
Dan Gohman9018e832008-05-10 01:26:14 +0000369 } else {
370 setOperationAction(ISD::VAARG , MVT::Other, Expand);
Evan Chengae642192007-03-02 23:16:35 +0000371 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
Dan Gohman9018e832008-05-10 01:26:14 +0000372 }
Evan Chengae642192007-03-02 23:16:35 +0000373
Anton Korobeynikov12c49af2006-11-21 00:01:06 +0000374 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
Chris Lattnere1125522006-01-15 09:00:21 +0000375 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
Evan Cheng25ab6902006-09-08 06:48:29 +0000376 if (Subtarget->is64Bit())
377 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +0000378 if (Subtarget->isTargetCygMing())
379 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
380 else
381 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
Chris Lattnerb99329e2006-01-13 02:42:53 +0000382
Evan Chengc7ce29b2009-02-13 22:36:38 +0000383 if (!UseSoftFloat && X86ScalarSSEf64) {
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000384 // f32 and f64 use SSE.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000385 // Set up the FP register classes.
Evan Cheng5ee4ccc2006-01-12 08:27:59 +0000386 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
387 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000388
Evan Cheng223547a2006-01-31 22:28:30 +0000389 // Use ANDPD to simulate FABS.
390 setOperationAction(ISD::FABS , MVT::f64, Custom);
391 setOperationAction(ISD::FABS , MVT::f32, Custom);
392
393 // Use XORP to simulate FNEG.
394 setOperationAction(ISD::FNEG , MVT::f64, Custom);
395 setOperationAction(ISD::FNEG , MVT::f32, Custom);
396
Evan Cheng68c47cb2007-01-05 07:55:56 +0000397 // Use ANDPD and ORPD to simulate FCOPYSIGN.
398 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
399 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
400
Evan Chengd25e9e82006-02-02 00:28:23 +0000401 // We don't support sin/cos/fmod
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000402 setOperationAction(ISD::FSIN , MVT::f64, Expand);
403 setOperationAction(ISD::FCOS , MVT::f64, Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000404 setOperationAction(ISD::FSIN , MVT::f32, Expand);
405 setOperationAction(ISD::FCOS , MVT::f32, Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000406
Chris Lattnera54aa942006-01-29 06:26:08 +0000407 // Expand FP immediates into loads from the stack, except for the special
408 // cases we handle.
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000409 addLegalFPImmediate(APFloat(+0.0)); // xorpd
410 addLegalFPImmediate(APFloat(+0.0f)); // xorps
Evan Chengc7ce29b2009-02-13 22:36:38 +0000411 } else if (!UseSoftFloat && X86ScalarSSEf32) {
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000412 // Use SSE for f32, x87 for f64.
413 // Set up the FP register classes.
414 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
415 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
416
417 // Use ANDPS to simulate FABS.
418 setOperationAction(ISD::FABS , MVT::f32, Custom);
419
420 // Use XORP to simulate FNEG.
421 setOperationAction(ISD::FNEG , MVT::f32, Custom);
422
423 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
424
425 // Use ANDPS and ORPS to simulate FCOPYSIGN.
426 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
427 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
428
429 // We don't support sin/cos/fmod
430 setOperationAction(ISD::FSIN , MVT::f32, Expand);
431 setOperationAction(ISD::FCOS , MVT::f32, Expand);
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000432
Nate Begemane1795842008-02-14 08:57:00 +0000433 // Special cases we handle for FP constants.
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000434 addLegalFPImmediate(APFloat(+0.0f)); // xorps
435 addLegalFPImmediate(APFloat(+0.0)); // FLD0
436 addLegalFPImmediate(APFloat(+1.0)); // FLD1
437 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
438 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
439
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000440 if (!UnsafeFPMath) {
441 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
442 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
443 }
Evan Chengc7ce29b2009-02-13 22:36:38 +0000444 } else if (!UseSoftFloat) {
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000445 // f32 and f64 in x87.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000446 // Set up the FP register classes.
Dale Johannesen849f2142007-07-03 00:53:03 +0000447 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
448 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +0000449
Evan Cheng68c47cb2007-01-05 07:55:56 +0000450 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
Dale Johannesen849f2142007-07-03 00:53:03 +0000451 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
Evan Cheng68c47cb2007-01-05 07:55:56 +0000452 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
453 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
Dale Johannesen5411a392007-08-09 01:04:01 +0000454
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000455 if (!UnsafeFPMath) {
456 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
457 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
458 }
Dale Johannesenf04afdb2007-08-30 00:23:21 +0000459 addLegalFPImmediate(APFloat(+0.0)); // FLD0
460 addLegalFPImmediate(APFloat(+1.0)); // FLD1
461 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
462 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000463 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
464 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
465 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
466 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000467 }
Evan Cheng470a6ad2006-02-22 02:26:30 +0000468
Dale Johannesen59a58732007-08-05 18:49:15 +0000469 // Long double always uses X87.
Evan Cheng92722532009-03-26 23:06:32 +0000470 if (!UseSoftFloat) {
Evan Chengc7ce29b2009-02-13 22:36:38 +0000471 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
472 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
473 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
474 {
475 bool ignored;
476 APFloat TmpFlt(+0.0);
477 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
478 &ignored);
479 addLegalFPImmediate(TmpFlt); // FLD0
480 TmpFlt.changeSign();
481 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
482 APFloat TmpFlt2(+1.0);
483 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
484 &ignored);
485 addLegalFPImmediate(TmpFlt2); // FLD1
486 TmpFlt2.changeSign();
487 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
488 }
Scott Michelfdc40a02009-02-17 22:15:04 +0000489
Evan Chengc7ce29b2009-02-13 22:36:38 +0000490 if (!UnsafeFPMath) {
491 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
492 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
493 }
Dale Johannesen2f429012007-09-26 21:10:55 +0000494 }
Dale Johannesen59a58732007-08-05 18:49:15 +0000495
Dan Gohmanf96e4de2007-10-11 23:21:31 +0000496 // Always use a library call for pow.
497 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
498 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
499 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
500
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000501 setOperationAction(ISD::FLOG, MVT::f80, Expand);
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000502 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000503 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000504 setOperationAction(ISD::FEXP, MVT::f80, Expand);
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000505 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
506
Mon P Wangf007a8b2008-11-06 05:31:54 +0000507 // First set operation action for all vector types to either promote
Mon P Wang0c397192008-10-30 08:01:45 +0000508 // (for widening) or expand (for scalarization). Then we will selectively
509 // turn on ones that can be effectively codegen'd.
Dan Gohmanfa0f77d2007-05-18 18:44:07 +0000510 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
511 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000512 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
513 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
514 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
515 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
516 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
517 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
518 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
519 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
520 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
521 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
522 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
523 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
524 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
Gabor Greif327ef032008-08-28 23:19:51 +0000525 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
526 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
Eli Friedman108b5192009-05-23 22:44:52 +0000527 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
Gabor Greif327ef032008-08-28 23:19:51 +0000528 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
Duncan Sands83ec4b62008-06-06 12:08:01 +0000529 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
530 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
531 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
532 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
533 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
534 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
535 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
538 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
540 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
542 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
543 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
Dale Johannesenfb0e1322008-09-10 17:31:40 +0000551 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
Eli Friedman23ef1052009-06-06 03:57:58 +0000556 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
Evan Chengd30bf012006-03-01 01:11:20 +0000560 }
561
Evan Chengc7ce29b2009-02-13 22:36:38 +0000562 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
563 // with -msoft-float, disable use of MMX as well.
Evan Cheng92722532009-03-26 23:06:32 +0000564 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
Evan Cheng470a6ad2006-02-22 02:26:30 +0000565 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
566 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
567 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
Dale Johannesena68f9012008-06-24 22:01:44 +0000568 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
Bill Wendlingeebc8a12007-03-26 07:53:08 +0000569 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
Evan Cheng470a6ad2006-02-22 02:26:30 +0000570
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000571 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
572 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
573 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
Chris Lattner6c284d72007-04-12 04:14:49 +0000574 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000575
Bill Wendlingc1fb0472007-03-10 09:57:05 +0000576 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
577 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
578 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
Dale Johannesen8d26e592007-10-30 01:18:38 +0000579 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
Bill Wendlingc1fb0472007-03-10 09:57:05 +0000580
Bill Wendling74027e92007-03-15 21:24:36 +0000581 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
582 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
583
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000584 setOperationAction(ISD::AND, MVT::v8i8, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000585 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000586 setOperationAction(ISD::AND, MVT::v4i16, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000587 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
588 setOperationAction(ISD::AND, MVT::v2i32, Promote);
589 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
590 setOperationAction(ISD::AND, MVT::v1i64, Legal);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000591
592 setOperationAction(ISD::OR, MVT::v8i8, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000593 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000594 setOperationAction(ISD::OR, MVT::v4i16, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000595 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
596 setOperationAction(ISD::OR, MVT::v2i32, Promote);
597 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
598 setOperationAction(ISD::OR, MVT::v1i64, Legal);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000599
600 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000601 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000602 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000603 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
604 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
605 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
606 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000607
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000608 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
Bill Wendlingeebc8a12007-03-26 07:53:08 +0000609 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000610 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
Bill Wendlingeebc8a12007-03-26 07:53:08 +0000611 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
612 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
613 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
Dale Johannesena68f9012008-06-24 22:01:44 +0000614 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
615 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
Bill Wendlingeebc8a12007-03-26 07:53:08 +0000616 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000617
Bill Wendlingccc44ad2007-03-27 20:22:40 +0000618 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
619 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
620 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
Dale Johannesena68f9012008-06-24 22:01:44 +0000621 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
Bill Wendlingccc44ad2007-03-27 20:22:40 +0000622 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
Bill Wendlinga348c562007-03-22 18:42:45 +0000623
624 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
625 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
626 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
Bill Wendlingccc44ad2007-03-27 20:22:40 +0000627 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
Bill Wendling826f36f2007-03-28 00:57:11 +0000628
Evan Cheng52672b82008-07-22 18:39:19 +0000629 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
Bill Wendling826f36f2007-03-28 00:57:11 +0000630 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
631 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
Bill Wendling2f9bb1a2007-04-24 21:16:55 +0000632 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
Bill Wendling3180e202008-07-20 02:32:23 +0000633
634 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
Mon P Wang9e5ecb82008-12-12 01:25:51 +0000635
Bill Wendlingf9abd7e2009-03-11 22:30:01 +0000636 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
Mon P Wang9e5ecb82008-12-12 01:25:51 +0000637 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
638 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
639 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
640 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
641 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
Evan Cheng470a6ad2006-02-22 02:26:30 +0000642 }
643
Evan Cheng92722532009-03-26 23:06:32 +0000644 if (!UseSoftFloat && Subtarget->hasSSE1()) {
Evan Cheng470a6ad2006-02-22 02:26:30 +0000645 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
646
Evan Cheng6bdb3f62006-10-27 18:49:08 +0000647 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
648 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
649 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
650 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
Dan Gohman20382522007-07-10 00:05:58 +0000651 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
652 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
Evan Chengf7c378e2006-04-10 07:23:14 +0000653 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
654 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
655 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
Evan Cheng11e15b32006-04-03 20:53:28 +0000656 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
Evan Chengf7c378e2006-04-10 07:23:14 +0000657 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
Nate Begeman30a0de92008-07-17 16:51:19 +0000658 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
Evan Cheng470a6ad2006-02-22 02:26:30 +0000659 }
660
Evan Cheng92722532009-03-26 23:06:32 +0000661 if (!UseSoftFloat && Subtarget->hasSSE2()) {
Evan Cheng470a6ad2006-02-22 02:26:30 +0000662 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
Evan Chengc7ce29b2009-02-13 22:36:38 +0000663
Bill Wendlingf9abd7e2009-03-11 22:30:01 +0000664 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
665 // registers cannot be used even for integer operations.
Evan Cheng470a6ad2006-02-22 02:26:30 +0000666 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
667 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
668 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
669 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
670
Evan Chengf7c378e2006-04-10 07:23:14 +0000671 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
672 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
673 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
Evan Cheng37e88562007-03-12 22:58:52 +0000674 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
Mon P Wangaf9b9522008-12-18 21:42:19 +0000675 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
Evan Chengf7c378e2006-04-10 07:23:14 +0000676 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
677 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
678 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
Evan Cheng37e88562007-03-12 22:58:52 +0000679 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
Evan Chengf9989842006-04-13 05:10:25 +0000680 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
Evan Cheng6bdb3f62006-10-27 18:49:08 +0000681 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
682 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
683 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
684 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
Dan Gohman20382522007-07-10 00:05:58 +0000685 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
686 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
Evan Cheng2c3ae372006-04-12 21:21:57 +0000687
Nate Begeman30a0de92008-07-17 16:51:19 +0000688 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
689 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
690 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
691 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
Nate Begemanc2616e42008-05-12 20:34:32 +0000692
Evan Chengf7c378e2006-04-10 07:23:14 +0000693 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
694 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
Evan Chengb067a1e2006-03-31 19:22:53 +0000695 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
Evan Cheng5edb8d22006-04-17 22:04:06 +0000696 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
Evan Cheng5edb8d22006-04-17 22:04:06 +0000697 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
Evan Chengf7c378e2006-04-10 07:23:14 +0000698
Evan Cheng2c3ae372006-04-12 21:21:57 +0000699 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000700 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
701 MVT VT = (MVT::SimpleValueType)i;
Nate Begeman844e0f92007-12-11 01:41:33 +0000702 // Do not attempt to custom lower non-power-of-2 vectors
Duncan Sands83ec4b62008-06-06 12:08:01 +0000703 if (!isPowerOf2_32(VT.getVectorNumElements()))
Nate Begeman844e0f92007-12-11 01:41:33 +0000704 continue;
David Greene9b9838d2009-06-29 16:47:10 +0000705 // Do not attempt to custom lower non-128-bit vectors
706 if (!VT.is128BitVector())
707 continue;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000708 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
709 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
710 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
Evan Cheng2c3ae372006-04-12 21:21:57 +0000711 }
Bill Wendlingf9abd7e2009-03-11 22:30:01 +0000712
Evan Cheng2c3ae372006-04-12 21:21:57 +0000713 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
714 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
715 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
716 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
Nate Begemancdd1eec2008-02-12 22:51:28 +0000717 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
Evan Cheng2c3ae372006-04-12 21:21:57 +0000718 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
Bill Wendlingf9abd7e2009-03-11 22:30:01 +0000719
Nate Begemancdd1eec2008-02-12 22:51:28 +0000720 if (Subtarget->is64Bit()) {
721 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
Dale Johannesen25f1d082007-10-31 00:32:36 +0000722 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
Nate Begemancdd1eec2008-02-12 22:51:28 +0000723 }
Evan Cheng2c3ae372006-04-12 21:21:57 +0000724
Anton Korobeynikov12c49af2006-11-21 00:01:06 +0000725 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
David Greene9b9838d2009-06-29 16:47:10 +0000726 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
727 MVT VT = (MVT::SimpleValueType)i;
728
729 // Do not attempt to promote non-128-bit vectors
730 if (!VT.is128BitVector()) {
731 continue;
732 }
733 setOperationAction(ISD::AND, VT, Promote);
734 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
735 setOperationAction(ISD::OR, VT, Promote);
736 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
737 setOperationAction(ISD::XOR, VT, Promote);
738 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
739 setOperationAction(ISD::LOAD, VT, Promote);
740 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
741 setOperationAction(ISD::SELECT, VT, Promote);
742 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
Evan Chengf7c378e2006-04-10 07:23:14 +0000743 }
Evan Cheng2c3ae372006-04-12 21:21:57 +0000744
Chris Lattnerddf89562008-01-17 19:59:44 +0000745 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
Chris Lattnerd43d00c2008-01-24 08:07:48 +0000746
Evan Cheng2c3ae372006-04-12 21:21:57 +0000747 // Custom lower v2i64 and v2f64 selects.
748 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
Evan Cheng91b740d2006-04-12 17:12:36 +0000749 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
Evan Chengf7c378e2006-04-10 07:23:14 +0000750 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
Evan Cheng2c3ae372006-04-12 21:21:57 +0000751 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
Scott Michelfdc40a02009-02-17 22:15:04 +0000752
Eli Friedman23ef1052009-06-06 03:57:58 +0000753 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
754 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
755 if (!DisableMMX && Subtarget->hasMMX()) {
756 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
757 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
758 }
Evan Cheng470a6ad2006-02-22 02:26:30 +0000759 }
Evan Chengc7ce29b2009-02-13 22:36:38 +0000760
Nate Begeman14d12ca2008-02-11 04:19:36 +0000761 if (Subtarget->hasSSE41()) {
762 // FIXME: Do we need to handle scalar-to-vector here?
763 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
764
765 // i8 and i16 vectors are custom , because the source register and source
766 // source memory operand types are not the same width. f32 vectors are
767 // custom since the immediate controlling the insert encodes additional
768 // information.
769 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
770 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
Mon P Wangf0fcdd82009-01-15 21:10:20 +0000771 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
Nate Begeman14d12ca2008-02-11 04:19:36 +0000772 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
773
774 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
775 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
Mon P Wangf0fcdd82009-01-15 21:10:20 +0000776 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
Evan Cheng62a3f152008-03-24 21:52:23 +0000777 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
Nate Begeman14d12ca2008-02-11 04:19:36 +0000778
779 if (Subtarget->is64Bit()) {
Nate Begemancdd1eec2008-02-12 22:51:28 +0000780 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
781 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
Nate Begeman14d12ca2008-02-11 04:19:36 +0000782 }
783 }
Evan Cheng470a6ad2006-02-22 02:26:30 +0000784
Nate Begeman30a0de92008-07-17 16:51:19 +0000785 if (Subtarget->hasSSE42()) {
786 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
787 }
Scott Michelfdc40a02009-02-17 22:15:04 +0000788
David Greene9b9838d2009-06-29 16:47:10 +0000789 if (!UseSoftFloat && Subtarget->hasAVX()) {
David Greened94c1012009-06-29 22:50:51 +0000790 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
791 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
792 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
793 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
794
David Greene9b9838d2009-06-29 16:47:10 +0000795 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
796 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
797 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
798 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
799 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
800 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
801 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
802 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
803 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
804 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
805 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
806 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
807 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
808 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
809 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
810
811 // Operations to consider commented out -v16i16 v32i8
812 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
813 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
814 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
815 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
816 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
817 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
818 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
819 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
820 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
821 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
822 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
823 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
824 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
825 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
826
827 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
828 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
829 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
830 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
831
832 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
833 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
834 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
835 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
837
838 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
839 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
840 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
841 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
843 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
844
845#if 0
846 // Not sure we want to do this since there are no 256-bit integer
847 // operations in AVX
848
849 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
850 // This includes 256-bit vectors
851 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
852 MVT VT = (MVT::SimpleValueType)i;
853
854 // Do not attempt to custom lower non-power-of-2 vectors
855 if (!isPowerOf2_32(VT.getVectorNumElements()))
856 continue;
857
858 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
859 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
860 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
861 }
862
863 if (Subtarget->is64Bit()) {
864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
865 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
866 }
867#endif
868
869#if 0
870 // Not sure we want to do this since there are no 256-bit integer
871 // operations in AVX
872
873 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
874 // Including 256-bit vectors
875 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
876 MVT VT = (MVT::SimpleValueType)i;
877
878 if (!VT.is256BitVector()) {
879 continue;
880 }
881 setOperationAction(ISD::AND, VT, Promote);
882 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
883 setOperationAction(ISD::OR, VT, Promote);
884 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
885 setOperationAction(ISD::XOR, VT, Promote);
886 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
887 setOperationAction(ISD::LOAD, VT, Promote);
888 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
889 setOperationAction(ISD::SELECT, VT, Promote);
890 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
891 }
892
893 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
894#endif
895 }
896
Evan Cheng6be2c582006-04-05 23:38:46 +0000897 // We want to custom lower some of our intrinsics.
898 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
899
Bill Wendling74c37652008-12-09 22:08:41 +0000900 // Add/Sub/Mul with overflow operations are custom lowered.
Bill Wendling41ea7e72008-11-24 19:21:46 +0000901 setOperationAction(ISD::SADDO, MVT::i32, Custom);
902 setOperationAction(ISD::SADDO, MVT::i64, Custom);
903 setOperationAction(ISD::UADDO, MVT::i32, Custom);
904 setOperationAction(ISD::UADDO, MVT::i64, Custom);
Bill Wendling74c37652008-12-09 22:08:41 +0000905 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
906 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
907 setOperationAction(ISD::USUBO, MVT::i32, Custom);
908 setOperationAction(ISD::USUBO, MVT::i64, Custom);
909 setOperationAction(ISD::SMULO, MVT::i32, Custom);
910 setOperationAction(ISD::SMULO, MVT::i64, Custom);
Bill Wendling41ea7e72008-11-24 19:21:46 +0000911
Evan Chengd54f2d52009-03-31 19:38:51 +0000912 if (!Subtarget->is64Bit()) {
913 // These libcalls are not available in 32-bit.
914 setLibcallName(RTLIB::SHL_I128, 0);
915 setLibcallName(RTLIB::SRL_I128, 0);
916 setLibcallName(RTLIB::SRA_I128, 0);
917 }
918
Evan Cheng206ee9d2006-07-07 08:33:52 +0000919 // We have target-specific dag combine patterns for the following nodes:
920 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
Evan Chengd880b972008-05-09 21:53:03 +0000921 setTargetDAGCombine(ISD::BUILD_VECTOR);
Chris Lattner83e6c992006-10-04 06:57:07 +0000922 setTargetDAGCombine(ISD::SELECT);
Nate Begeman740ab032009-01-26 00:52:55 +0000923 setTargetDAGCombine(ISD::SHL);
924 setTargetDAGCombine(ISD::SRA);
925 setTargetDAGCombine(ISD::SRL);
Chris Lattner149a4e52008-02-22 02:09:43 +0000926 setTargetDAGCombine(ISD::STORE);
Owen Anderson99177002009-06-29 18:04:45 +0000927 setTargetDAGCombine(ISD::MEMBARRIER);
Evan Cheng0b0cd912009-03-28 05:57:29 +0000928 if (Subtarget->is64Bit())
929 setTargetDAGCombine(ISD::MUL);
Evan Cheng206ee9d2006-07-07 08:33:52 +0000930
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000931 computeRegisterProperties();
932
Evan Cheng87ed7162006-02-14 08:25:08 +0000933 // FIXME: These should be based on subtarget info. Plus, the values should
934 // be smaller when we are in optimizing for size mode.
Dan Gohman87060f52008-06-30 21:00:56 +0000935 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
936 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
937 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000938 allowUnalignedMemoryAccesses = true; // x86 supports it!
Evan Chengfb8075d2008-02-28 00:43:03 +0000939 setPrefLoopAlignment(16);
Evan Cheng6ebf7bc2009-05-13 21:42:09 +0000940 benefitFromCodePlacementOpt = true;
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000941}
942
Scott Michel5b8f82e2008-03-10 15:42:14 +0000943
Duncan Sands5480c042009-01-01 15:52:00 +0000944MVT X86TargetLowering::getSetCCResultType(MVT VT) const {
Scott Michel5b8f82e2008-03-10 15:42:14 +0000945 return MVT::i8;
946}
947
948
Evan Cheng29286502008-01-23 23:17:41 +0000949/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
950/// the desired ByVal argument alignment.
951static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
952 if (MaxAlign == 16)
953 return;
954 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
955 if (VTy->getBitWidth() == 128)
956 MaxAlign = 16;
Evan Cheng29286502008-01-23 23:17:41 +0000957 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
958 unsigned EltAlign = 0;
959 getMaxByValAlign(ATy->getElementType(), EltAlign);
960 if (EltAlign > MaxAlign)
961 MaxAlign = EltAlign;
962 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
963 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
964 unsigned EltAlign = 0;
965 getMaxByValAlign(STy->getElementType(i), EltAlign);
966 if (EltAlign > MaxAlign)
967 MaxAlign = EltAlign;
968 if (MaxAlign == 16)
969 break;
970 }
971 }
972 return;
973}
974
975/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
976/// function arguments in the caller parameter area. For X86, aggregates
Dale Johannesen0c191872008-02-08 19:48:20 +0000977/// that contain SSE vectors are placed at 16-byte boundaries while the rest
978/// are at 4-byte boundaries.
Evan Cheng29286502008-01-23 23:17:41 +0000979unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
Evan Cheng1887c1c2008-08-21 21:00:15 +0000980 if (Subtarget->is64Bit()) {
981 // Max of 8 and alignment of type.
Anton Korobeynikovbff66b02008-09-09 18:22:57 +0000982 unsigned TyAlign = TD->getABITypeAlignment(Ty);
Evan Cheng1887c1c2008-08-21 21:00:15 +0000983 if (TyAlign > 8)
984 return TyAlign;
985 return 8;
986 }
987
Evan Cheng29286502008-01-23 23:17:41 +0000988 unsigned Align = 4;
Dale Johannesen0c191872008-02-08 19:48:20 +0000989 if (Subtarget->hasSSE1())
990 getMaxByValAlign(Ty, Align);
Evan Cheng29286502008-01-23 23:17:41 +0000991 return Align;
992}
Chris Lattner2b02a442007-02-25 08:29:00 +0000993
Evan Chengf0df0312008-05-15 08:39:06 +0000994/// getOptimalMemOpType - Returns the target specific optimal type for load
Evan Cheng0ef8de32008-05-15 22:13:02 +0000995/// and store operations as a result of memset, memcpy, and memmove
996/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
Evan Chengf0df0312008-05-15 08:39:06 +0000997/// determining it.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000998MVT
Evan Chengf0df0312008-05-15 08:39:06 +0000999X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
Devang Patel578efa92009-06-05 21:57:13 +00001000 bool isSrcConst, bool isSrcStr,
1001 SelectionDAG &DAG) const {
Chris Lattner4002a1b2008-10-28 05:49:35 +00001002 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1003 // linux. This is because the stack realignment code can't handle certain
1004 // cases like PR2962. This should be removed when PR2962 is fixed.
Devang Patel578efa92009-06-05 21:57:13 +00001005 const Function *F = DAG.getMachineFunction().getFunction();
1006 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1007 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
Chris Lattner4002a1b2008-10-28 05:49:35 +00001008 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1009 return MVT::v4i32;
1010 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1011 return MVT::v4f32;
1012 }
Evan Chengf0df0312008-05-15 08:39:06 +00001013 if (Subtarget->is64Bit() && Size >= 8)
1014 return MVT::i64;
1015 return MVT::i32;
1016}
1017
Evan Chengcc415862007-11-09 01:32:10 +00001018/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1019/// jumptable.
Dan Gohman475871a2008-07-27 21:46:04 +00001020SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
Evan Chengcc415862007-11-09 01:32:10 +00001021 SelectionDAG &DAG) const {
1022 if (usesGlobalOffsetTable())
Dale Johannesenb300d2a2009-02-07 00:55:49 +00001023 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
Chris Lattnere4df7562009-07-09 03:15:51 +00001024 if (!Subtarget->is64Bit())
Dale Johannesenb300d2a2009-02-07 00:55:49 +00001025 // This doesn't have DebugLoc associated with it, but is not really the
1026 // same as a Register.
1027 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1028 getPointerTy());
Evan Chengcc415862007-11-09 01:32:10 +00001029 return Table;
1030}
1031
Bill Wendlingb4202b82009-07-01 18:50:55 +00001032/// getFunctionAlignment - Return the Log2 alignment of this function.
Bill Wendling20c568f2009-06-30 22:38:32 +00001033unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1034 return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 4;
1035}
1036
Chris Lattner2b02a442007-02-25 08:29:00 +00001037//===----------------------------------------------------------------------===//
1038// Return Value Calling Convention Implementation
1039//===----------------------------------------------------------------------===//
1040
Chris Lattner59ed56b2007-02-28 04:55:35 +00001041#include "X86GenCallingConv.inc"
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001042
Chris Lattner2a9bdd72007-02-25 09:12:39 +00001043/// LowerRET - Lower an ISD::RET node.
Dan Gohman475871a2008-07-27 21:46:04 +00001044SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
Dale Johannesen6f38cb62009-02-07 19:59:05 +00001045 DebugLoc dl = Op.getDebugLoc();
Chris Lattner2a9bdd72007-02-25 09:12:39 +00001046 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
Scott Michelfdc40a02009-02-17 22:15:04 +00001047
Chris Lattner9774c912007-02-27 05:28:59 +00001048 SmallVector<CCValAssign, 16> RVLocs;
1049 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
Chris Lattner52387be2007-06-19 00:13:10 +00001050 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1051 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
Gabor Greifba36cb52008-08-28 21:40:38 +00001052 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
Scott Michelfdc40a02009-02-17 22:15:04 +00001053
Chris Lattner2a9bdd72007-02-25 09:12:39 +00001054 // If this is the first return lowered for this function, add the regs to the
1055 // liveout set for the function.
Chris Lattner84bc5422007-12-31 04:13:23 +00001056 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
Chris Lattner9774c912007-02-27 05:28:59 +00001057 for (unsigned i = 0; i != RVLocs.size(); ++i)
1058 if (RVLocs[i].isRegLoc())
Chris Lattner84bc5422007-12-31 04:13:23 +00001059 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
Chris Lattner2a9bdd72007-02-25 09:12:39 +00001060 }
Dan Gohman475871a2008-07-27 21:46:04 +00001061 SDValue Chain = Op.getOperand(0);
Scott Michelfdc40a02009-02-17 22:15:04 +00001062
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001063 // Handle tail call return.
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00001064 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001065 if (Chain.getOpcode() == X86ISD::TAILCALL) {
Dan Gohman475871a2008-07-27 21:46:04 +00001066 SDValue TailCall = Chain;
1067 SDValue TargetAddress = TailCall.getOperand(1);
1068 SDValue StackAdjustment = TailCall.getOperand(2);
Chris Lattnerb4a6eaa2008-01-16 05:52:18 +00001069 assert(((TargetAddress.getOpcode() == ISD::Register &&
Arnold Schwaighofer290ae032008-09-22 14:50:07 +00001070 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX ||
Arnold Schwaighoferbbd8c332009-06-12 16:26:57 +00001071 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R11)) ||
Bill Wendling056292f2008-09-16 21:48:12 +00001072 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
Scott Michelfdc40a02009-02-17 22:15:04 +00001073 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001074 "Expecting an global address, external symbol, or register");
Chris Lattnerb4a6eaa2008-01-16 05:52:18 +00001075 assert(StackAdjustment.getOpcode() == ISD::Constant &&
1076 "Expecting a const value");
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001077
Dan Gohman475871a2008-07-27 21:46:04 +00001078 SmallVector<SDValue,8> Operands;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001079 Operands.push_back(Chain.getOperand(0));
1080 Operands.push_back(TargetAddress);
1081 Operands.push_back(StackAdjustment);
1082 // Copy registers used by the call. Last operand is a flag so it is not
1083 // copied.
Arnold Schwaighofer448175f2007-10-16 09:05:00 +00001084 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001085 Operands.push_back(Chain.getOperand(i));
1086 }
Scott Michelfdc40a02009-02-17 22:15:04 +00001087 return DAG.getNode(X86ISD::TC_RETURN, dl, MVT::Other, &Operands[0],
Arnold Schwaighofer448175f2007-10-16 09:05:00 +00001088 Operands.size());
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001089 }
Scott Michelfdc40a02009-02-17 22:15:04 +00001090
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001091 // Regular return.
Dan Gohman475871a2008-07-27 21:46:04 +00001092 SDValue Flag;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001093
Dan Gohman475871a2008-07-27 21:46:04 +00001094 SmallVector<SDValue, 6> RetOps;
Chris Lattner447ff682008-03-11 03:23:40 +00001095 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1096 // Operand #1 = Bytes To Pop
1097 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
Scott Michelfdc40a02009-02-17 22:15:04 +00001098
Chris Lattner2a9bdd72007-02-25 09:12:39 +00001099 // Copy the result values into the output registers.
Chris Lattner8e6da152008-03-10 21:08:41 +00001100 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1101 CCValAssign &VA = RVLocs[i];
1102 assert(VA.isRegLoc() && "Can only return in registers!");
Dan Gohman475871a2008-07-27 21:46:04 +00001103 SDValue ValToCopy = Op.getOperand(i*2+1);
Scott Michelfdc40a02009-02-17 22:15:04 +00001104
Chris Lattner447ff682008-03-11 03:23:40 +00001105 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1106 // the RET instruction and handled by the FP Stackifier.
Dan Gohman37eed792009-02-04 17:28:58 +00001107 if (VA.getLocReg() == X86::ST0 ||
1108 VA.getLocReg() == X86::ST1) {
Chris Lattner447ff682008-03-11 03:23:40 +00001109 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1110 // change the value to the FP stack register class.
Dan Gohman37eed792009-02-04 17:28:58 +00001111 if (isScalarFPTypeInSSEReg(VA.getValVT()))
Dale Johannesenace16102009-02-03 19:33:06 +00001112 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
Chris Lattner447ff682008-03-11 03:23:40 +00001113 RetOps.push_back(ValToCopy);
1114 // Don't emit a copytoreg.
1115 continue;
1116 }
Dale Johannesena68f9012008-06-24 22:01:44 +00001117
Evan Cheng242b38b2009-02-23 09:03:22 +00001118 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1119 // which is returned in RAX / RDX.
Evan Cheng6140a8b2009-02-22 08:05:12 +00001120 if (Subtarget->is64Bit()) {
1121 MVT ValVT = ValToCopy.getValueType();
Evan Cheng242b38b2009-02-23 09:03:22 +00001122 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
Evan Cheng6140a8b2009-02-22 08:05:12 +00001123 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
Evan Cheng242b38b2009-02-23 09:03:22 +00001124 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1125 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1126 }
Evan Cheng6140a8b2009-02-22 08:05:12 +00001127 }
1128
Dale Johannesendd64c412009-02-04 00:33:20 +00001129 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
Chris Lattner2a9bdd72007-02-25 09:12:39 +00001130 Flag = Chain.getValue(1);
1131 }
Dan Gohman61a92132008-04-21 23:59:07 +00001132
1133 // The x86-64 ABI for returning structs by value requires that we copy
1134 // the sret argument into %rax for the return. We saved the argument into
1135 // a virtual register in the entry block, so now we copy the value out
1136 // and into %rax.
1137 if (Subtarget->is64Bit() &&
1138 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1139 MachineFunction &MF = DAG.getMachineFunction();
1140 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1141 unsigned Reg = FuncInfo->getSRetReturnReg();
1142 if (!Reg) {
1143 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1144 FuncInfo->setSRetReturnReg(Reg);
1145 }
Dale Johannesendd64c412009-02-04 00:33:20 +00001146 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
Dan Gohman61a92132008-04-21 23:59:07 +00001147
Dale Johannesendd64c412009-02-04 00:33:20 +00001148 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
Dan Gohman61a92132008-04-21 23:59:07 +00001149 Flag = Chain.getValue(1);
1150 }
Scott Michelfdc40a02009-02-17 22:15:04 +00001151
Chris Lattner447ff682008-03-11 03:23:40 +00001152 RetOps[0] = Chain; // Update chain.
1153
1154 // Add the flag if we have it.
Gabor Greifba36cb52008-08-28 21:40:38 +00001155 if (Flag.getNode())
Chris Lattner447ff682008-03-11 03:23:40 +00001156 RetOps.push_back(Flag);
Scott Michelfdc40a02009-02-17 22:15:04 +00001157
1158 return DAG.getNode(X86ISD::RET_FLAG, dl,
Dale Johannesenace16102009-02-03 19:33:06 +00001159 MVT::Other, &RetOps[0], RetOps.size());
Chris Lattner2a9bdd72007-02-25 09:12:39 +00001160}
1161
1162
Chris Lattner3085e152007-02-25 08:59:22 +00001163/// LowerCallResult - Lower the result values of an ISD::CALL into the
1164/// appropriate copies out of appropriate physical registers. This assumes that
1165/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
1166/// being lowered. The returns a SDNode with the same number of values as the
1167/// ISD::CALL.
1168SDNode *X86TargetLowering::
Scott Michelfdc40a02009-02-17 22:15:04 +00001169LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
Chris Lattner3085e152007-02-25 08:59:22 +00001170 unsigned CallingConv, SelectionDAG &DAG) {
Dale Johannesenace16102009-02-03 19:33:06 +00001171
Scott Michelfdc40a02009-02-17 22:15:04 +00001172 DebugLoc dl = TheCall->getDebugLoc();
Chris Lattnere32bbf62007-02-28 07:09:55 +00001173 // Assign locations to each value returned by this call.
Chris Lattner9774c912007-02-27 05:28:59 +00001174 SmallVector<CCValAssign, 16> RVLocs;
Dan Gohman095cc292008-09-13 01:54:27 +00001175 bool isVarArg = TheCall->isVarArg();
Torok Edwin3f142c32009-02-01 18:15:56 +00001176 bool Is64Bit = Subtarget->is64Bit();
Chris Lattner52387be2007-06-19 00:13:10 +00001177 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
Chris Lattnere32bbf62007-02-28 07:09:55 +00001178 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
1179
Dan Gohman475871a2008-07-27 21:46:04 +00001180 SmallVector<SDValue, 8> ResultVals;
Scott Michelfdc40a02009-02-17 22:15:04 +00001181
Chris Lattner3085e152007-02-25 08:59:22 +00001182 // Copy all of the result registers out of their specified physreg.
Chris Lattner8e6da152008-03-10 21:08:41 +00001183 for (unsigned i = 0; i != RVLocs.size(); ++i) {
Dan Gohman37eed792009-02-04 17:28:58 +00001184 CCValAssign &VA = RVLocs[i];
1185 MVT CopyVT = VA.getValVT();
Scott Michelfdc40a02009-02-17 22:15:04 +00001186
Torok Edwin3f142c32009-02-01 18:15:56 +00001187 // If this is x86-64, and we disabled SSE, we can't return FP values
Scott Michelfdc40a02009-02-17 22:15:04 +00001188 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
Torok Edwin3f142c32009-02-01 18:15:56 +00001189 ((Is64Bit || TheCall->isInreg()) && !Subtarget->hasSSE1())) {
Torok Edwin804e0fe2009-07-08 19:04:27 +00001190 llvm_report_error("SSE register return with SSE disabled");
Torok Edwin3f142c32009-02-01 18:15:56 +00001191 }
1192
Chris Lattner8e6da152008-03-10 21:08:41 +00001193 // If this is a call to a function that returns an fp value on the floating
1194 // point stack, but where we prefer to use the value in xmm registers, copy
1195 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
Dan Gohman37eed792009-02-04 17:28:58 +00001196 if ((VA.getLocReg() == X86::ST0 ||
1197 VA.getLocReg() == X86::ST1) &&
1198 isScalarFPTypeInSSEReg(VA.getValVT())) {
Chris Lattner8e6da152008-03-10 21:08:41 +00001199 CopyVT = MVT::f80;
Chris Lattner3085e152007-02-25 08:59:22 +00001200 }
Scott Michelfdc40a02009-02-17 22:15:04 +00001201
Evan Cheng79fb3b42009-02-20 20:43:02 +00001202 SDValue Val;
1203 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
Evan Cheng242b38b2009-02-23 09:03:22 +00001204 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1205 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1206 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1207 MVT::v2i64, InFlag).getValue(1);
1208 Val = Chain.getValue(0);
1209 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1210 Val, DAG.getConstant(0, MVT::i64));
1211 } else {
1212 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1213 MVT::i64, InFlag).getValue(1);
1214 Val = Chain.getValue(0);
1215 }
Evan Cheng79fb3b42009-02-20 20:43:02 +00001216 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1217 } else {
1218 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1219 CopyVT, InFlag).getValue(1);
1220 Val = Chain.getValue(0);
1221 }
Chris Lattner8e6da152008-03-10 21:08:41 +00001222 InFlag = Chain.getValue(2);
Chris Lattner112dedc2007-12-29 06:41:28 +00001223
Dan Gohman37eed792009-02-04 17:28:58 +00001224 if (CopyVT != VA.getValVT()) {
Chris Lattner8e6da152008-03-10 21:08:41 +00001225 // Round the F80 the right size, which also moves to the appropriate xmm
1226 // register.
Dan Gohman37eed792009-02-04 17:28:58 +00001227 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
Chris Lattner8e6da152008-03-10 21:08:41 +00001228 // This truncation won't change the value.
1229 DAG.getIntPtrConstant(1));
1230 }
Scott Michelfdc40a02009-02-17 22:15:04 +00001231
Chris Lattner8e6da152008-03-10 21:08:41 +00001232 ResultVals.push_back(Val);
Chris Lattner3085e152007-02-25 08:59:22 +00001233 }
Duncan Sands4bdcb612008-07-02 17:40:58 +00001234
Chris Lattner3085e152007-02-25 08:59:22 +00001235 // Merge everything together with a MERGE_VALUES node.
1236 ResultVals.push_back(Chain);
Dale Johannesenace16102009-02-03 19:33:06 +00001237 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
1238 &ResultVals[0], ResultVals.size()).getNode();
Chris Lattner2b02a442007-02-25 08:29:00 +00001239}
1240
1241
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001242//===----------------------------------------------------------------------===//
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001243// C & StdCall & Fast Calling Convention implementation
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001244//===----------------------------------------------------------------------===//
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001245// StdCall calling convention seems to be standard for many Windows' API
1246// routines and around. It differs from C calling convention just a little:
1247// callee should clean up the stack, not caller. Symbols should be also
1248// decorated in some fancy way :) It doesn't support any vector arguments.
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001249// For info on fast calling convention see Fast Calling Convention (tail call)
1250// implementation LowerX86_32FastCCCallTo.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001251
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001252/// CallIsStructReturn - Determines whether a CALL node uses struct return
1253/// semantics.
Dan Gohman095cc292008-09-13 01:54:27 +00001254static bool CallIsStructReturn(CallSDNode *TheCall) {
1255 unsigned NumOps = TheCall->getNumArgs();
Gordon Henriksen86737662008-01-05 16:56:59 +00001256 if (!NumOps)
1257 return false;
Duncan Sands276dcbd2008-03-21 09:14:45 +00001258
Dan Gohman095cc292008-09-13 01:54:27 +00001259 return TheCall->getArgFlags(0).isSRet();
Gordon Henriksen86737662008-01-05 16:56:59 +00001260}
1261
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001262/// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1263/// return semantics.
Dan Gohman475871a2008-07-27 21:46:04 +00001264static bool ArgsAreStructReturn(SDValue Op) {
Gabor Greifba36cb52008-08-28 21:40:38 +00001265 unsigned NumArgs = Op.getNode()->getNumValues() - 1;
Gordon Henriksen86737662008-01-05 16:56:59 +00001266 if (!NumArgs)
1267 return false;
Duncan Sands276dcbd2008-03-21 09:14:45 +00001268
1269 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
Gordon Henriksen86737662008-01-05 16:56:59 +00001270}
1271
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001272/// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1273/// the callee to pop its own arguments. Callee pop is necessary to support tail
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001274/// calls.
Dan Gohman095cc292008-09-13 01:54:27 +00001275bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001276 if (IsVarArg)
1277 return false;
1278
Dan Gohman095cc292008-09-13 01:54:27 +00001279 switch (CallingConv) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001280 default:
1281 return false;
1282 case CallingConv::X86_StdCall:
1283 return !Subtarget->is64Bit();
1284 case CallingConv::X86_FastCall:
1285 return !Subtarget->is64Bit();
1286 case CallingConv::Fast:
1287 return PerformTailCallOpt;
1288 }
1289}
1290
Dan Gohman095cc292008-09-13 01:54:27 +00001291/// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1292/// given CallingConvention value.
1293CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
Anton Korobeynikov7c1c2612008-02-20 11:22:39 +00001294 if (Subtarget->is64Bit()) {
Anton Korobeynikov1a979d92008-03-22 20:57:27 +00001295 if (Subtarget->isTargetWin64())
Anton Korobeynikov8f88cb02008-03-22 20:37:30 +00001296 return CC_X86_Win64_C;
Evan Chenge9ac9e62008-09-07 09:07:23 +00001297 else
1298 return CC_X86_64_C;
Anton Korobeynikov7c1c2612008-02-20 11:22:39 +00001299 }
1300
Gordon Henriksen86737662008-01-05 16:56:59 +00001301 if (CC == CallingConv::X86_FastCall)
1302 return CC_X86_32_FastCall;
Evan Chengb188dd92008-09-10 18:25:29 +00001303 else if (CC == CallingConv::Fast)
1304 return CC_X86_32_FastCC;
Gordon Henriksen86737662008-01-05 16:56:59 +00001305 else
1306 return CC_X86_32_C;
1307}
1308
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001309/// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1310/// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
Gordon Henriksen86737662008-01-05 16:56:59 +00001311NameDecorationStyle
Dan Gohman475871a2008-07-27 21:46:04 +00001312X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001313 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
Gordon Henriksen86737662008-01-05 16:56:59 +00001314 if (CC == CallingConv::X86_FastCall)
1315 return FastCall;
1316 else if (CC == CallingConv::X86_StdCall)
1317 return StdCall;
1318 return None;
1319}
1320
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001321
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001322/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1323/// by "Src" to address "Dst" with size and alignment information specified by
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001324/// the specific parameter attribute. The copy will be passed as a byval
1325/// function parameter.
Scott Michelfdc40a02009-02-17 22:15:04 +00001326static SDValue
Dan Gohman475871a2008-07-27 21:46:04 +00001327CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
Dale Johannesendd64c412009-02-04 00:33:20 +00001328 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1329 DebugLoc dl) {
Dan Gohman475871a2008-07-27 21:46:04 +00001330 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
Dale Johannesendd64c412009-02-04 00:33:20 +00001331 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00001332 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001333}
1334
Dan Gohman475871a2008-07-27 21:46:04 +00001335SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
Rafael Espindola7effac52007-09-14 15:48:13 +00001336 const CCValAssign &VA,
1337 MachineFrameInfo *MFI,
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001338 unsigned CC,
Dan Gohman475871a2008-07-27 21:46:04 +00001339 SDValue Root, unsigned i) {
Rafael Espindola7effac52007-09-14 15:48:13 +00001340 // Create the nodes corresponding to a load from this parameter slot.
Duncan Sands276dcbd2008-03-21 09:14:45 +00001341 ISD::ArgFlagsTy Flags =
1342 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001343 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
Duncan Sands276dcbd2008-03-21 09:14:45 +00001344 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
Evan Chenge70bb592008-01-10 02:24:25 +00001345
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001346 // FIXME: For now, all byval parameter objects are marked mutable. This can be
Scott Michelfdc40a02009-02-17 22:15:04 +00001347 // changed with more analysis.
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001348 // In case of tail call optimization mark all arguments mutable. Since they
1349 // could be overwritten by lowering of arguments in case of a tail call.
Duncan Sands83ec4b62008-06-06 12:08:01 +00001350 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001351 VA.getLocMemOffset(), isImmutable);
Dan Gohman475871a2008-07-27 21:46:04 +00001352 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
Duncan Sands276dcbd2008-03-21 09:14:45 +00001353 if (Flags.isByVal())
Rafael Espindola7effac52007-09-14 15:48:13 +00001354 return FIN;
Dale Johannesen6f38cb62009-02-07 19:59:05 +00001355 return DAG.getLoad(VA.getValVT(), Op.getDebugLoc(), Root, FIN,
Dan Gohmana54cf172008-07-11 22:44:52 +00001356 PseudoSourceValue::getFixedStack(FI), 0);
Rafael Espindola7effac52007-09-14 15:48:13 +00001357}
1358
Dan Gohman475871a2008-07-27 21:46:04 +00001359SDValue
1360X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
Evan Cheng1bc78042006-04-26 01:20:17 +00001361 MachineFunction &MF = DAG.getMachineFunction();
Gordon Henriksen86737662008-01-05 16:56:59 +00001362 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
Dale Johannesen6f38cb62009-02-07 19:59:05 +00001363 DebugLoc dl = Op.getDebugLoc();
Scott Michelfdc40a02009-02-17 22:15:04 +00001364
Gordon Henriksen86737662008-01-05 16:56:59 +00001365 const Function* Fn = MF.getFunction();
1366 if (Fn->hasExternalLinkage() &&
1367 Subtarget->isTargetCygMing() &&
1368 Fn->getName() == "main")
1369 FuncInfo->setForceFramePointer(true);
1370
1371 // Decorate the function name.
1372 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
Scott Michelfdc40a02009-02-17 22:15:04 +00001373
Evan Cheng1bc78042006-04-26 01:20:17 +00001374 MachineFrameInfo *MFI = MF.getFrameInfo();
Dan Gohman475871a2008-07-27 21:46:04 +00001375 SDValue Root = Op.getOperand(0);
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001376 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001377 unsigned CC = MF.getFunction()->getCallingConv();
Gordon Henriksen86737662008-01-05 16:56:59 +00001378 bool Is64Bit = Subtarget->is64Bit();
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001379 bool IsWin64 = Subtarget->isTargetWin64();
Gordon Henriksenae636f82008-01-03 16:47:34 +00001380
1381 assert(!(isVarArg && CC == CallingConv::Fast) &&
1382 "Var args not supported with calling convention fastcc");
1383
Chris Lattner638402b2007-02-28 07:00:42 +00001384 // Assign locations to all of the incoming arguments.
Chris Lattnerf39f7712007-02-28 05:46:49 +00001385 SmallVector<CCValAssign, 16> ArgLocs;
Gordon Henriksenae636f82008-01-03 16:47:34 +00001386 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
Dan Gohman095cc292008-09-13 01:54:27 +00001387 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC));
Scott Michelfdc40a02009-02-17 22:15:04 +00001388
Dan Gohman475871a2008-07-27 21:46:04 +00001389 SmallVector<SDValue, 8> ArgValues;
Chris Lattnerf39f7712007-02-28 05:46:49 +00001390 unsigned LastVal = ~0U;
1391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1392 CCValAssign &VA = ArgLocs[i];
1393 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1394 // places.
1395 assert(VA.getValNo() != LastVal &&
1396 "Don't support value assigned to multiple locs yet");
1397 LastVal = VA.getValNo();
Scott Michelfdc40a02009-02-17 22:15:04 +00001398
Chris Lattnerf39f7712007-02-28 05:46:49 +00001399 if (VA.isRegLoc()) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00001400 MVT RegVT = VA.getLocVT();
Devang Patel8a84e442009-01-05 17:31:22 +00001401 TargetRegisterClass *RC = NULL;
Chris Lattnerf39f7712007-02-28 05:46:49 +00001402 if (RegVT == MVT::i32)
1403 RC = X86::GR32RegisterClass;
Gordon Henriksen86737662008-01-05 16:56:59 +00001404 else if (Is64Bit && RegVT == MVT::i64)
1405 RC = X86::GR64RegisterClass;
Dale Johannesene672af12008-02-05 20:46:33 +00001406 else if (RegVT == MVT::f32)
Gordon Henriksen86737662008-01-05 16:56:59 +00001407 RC = X86::FR32RegisterClass;
Dale Johannesene672af12008-02-05 20:46:33 +00001408 else if (RegVT == MVT::f64)
Gordon Henriksen86737662008-01-05 16:56:59 +00001409 RC = X86::FR64RegisterClass;
Duncan Sands83ec4b62008-06-06 12:08:01 +00001410 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
Evan Chengee472b12008-04-25 07:56:45 +00001411 RC = X86::VR128RegisterClass;
Duncan Sands83ec4b62008-06-06 12:08:01 +00001412 else if (RegVT.isVector()) {
1413 assert(RegVT.getSizeInBits() == 64);
Evan Chengee472b12008-04-25 07:56:45 +00001414 if (!Is64Bit)
1415 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1416 else {
1417 // Darwin calling convention passes MMX values in either GPRs or
1418 // XMMs in x86-64. Other targets pass them in memory.
1419 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1420 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1421 RegVT = MVT::v2i64;
1422 } else {
1423 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1424 RegVT = MVT::i64;
1425 }
1426 }
1427 } else {
1428 assert(0 && "Unknown argument type!");
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001429 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001430
Bob Wilson998e1252009-04-20 18:36:57 +00001431 unsigned Reg = DAG.getMachineFunction().addLiveIn(VA.getLocReg(), RC);
Dale Johannesendd64c412009-02-04 00:33:20 +00001432 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
Scott Michelfdc40a02009-02-17 22:15:04 +00001433
Chris Lattnerf39f7712007-02-28 05:46:49 +00001434 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1435 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1436 // right size.
1437 if (VA.getLocInfo() == CCValAssign::SExt)
Dale Johannesenace16102009-02-03 19:33:06 +00001438 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
Chris Lattnerf39f7712007-02-28 05:46:49 +00001439 DAG.getValueType(VA.getValVT()));
1440 else if (VA.getLocInfo() == CCValAssign::ZExt)
Dale Johannesenace16102009-02-03 19:33:06 +00001441 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
Chris Lattnerf39f7712007-02-28 05:46:49 +00001442 DAG.getValueType(VA.getValVT()));
Scott Michelfdc40a02009-02-17 22:15:04 +00001443
Chris Lattnerf39f7712007-02-28 05:46:49 +00001444 if (VA.getLocInfo() != CCValAssign::Full)
Dale Johannesenace16102009-02-03 19:33:06 +00001445 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
Scott Michelfdc40a02009-02-17 22:15:04 +00001446
Gordon Henriksen86737662008-01-05 16:56:59 +00001447 // Handle MMX values passed in GPRs.
Evan Cheng44c0fd12008-04-25 20:13:28 +00001448 if (Is64Bit && RegVT != VA.getLocVT()) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00001449 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
Dale Johannesenace16102009-02-03 19:33:06 +00001450 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
Evan Cheng44c0fd12008-04-25 20:13:28 +00001451 else if (RC == X86::VR128RegisterClass) {
Dale Johannesenace16102009-02-03 19:33:06 +00001452 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1453 ArgValue, DAG.getConstant(0, MVT::i64));
1454 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
Evan Cheng44c0fd12008-04-25 20:13:28 +00001455 }
1456 }
Scott Michelfdc40a02009-02-17 22:15:04 +00001457
Chris Lattnerf39f7712007-02-28 05:46:49 +00001458 ArgValues.push_back(ArgValue);
1459 } else {
1460 assert(VA.isMemLoc());
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001461 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
Evan Cheng1bc78042006-04-26 01:20:17 +00001462 }
Evan Cheng1bc78042006-04-26 01:20:17 +00001463 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001464
Dan Gohman61a92132008-04-21 23:59:07 +00001465 // The x86-64 ABI for returning structs by value requires that we copy
1466 // the sret argument into %rax for the return. Save the argument into
1467 // a virtual register so that we can access it from the return points.
1468 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1469 MachineFunction &MF = DAG.getMachineFunction();
1470 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1471 unsigned Reg = FuncInfo->getSRetReturnReg();
1472 if (!Reg) {
1473 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1474 FuncInfo->setSRetReturnReg(Reg);
1475 }
Dale Johannesendd64c412009-02-04 00:33:20 +00001476 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
Dale Johannesenace16102009-02-03 19:33:06 +00001477 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
Dan Gohman61a92132008-04-21 23:59:07 +00001478 }
1479
Chris Lattnerf39f7712007-02-28 05:46:49 +00001480 unsigned StackSize = CCInfo.getNextStackOffset();
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001481 // align stack specially for tail calls
Evan Chenge9ac9e62008-09-07 09:07:23 +00001482 if (PerformTailCallOpt && CC == CallingConv::Fast)
Gordon Henriksenae636f82008-01-03 16:47:34 +00001483 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
Evan Cheng25caf632006-05-23 21:06:34 +00001484
Evan Cheng1bc78042006-04-26 01:20:17 +00001485 // If the function takes variable number of arguments, make a frame index for
1486 // the start of the first vararg value... for expansion of llvm.va_start.
Gordon Henriksenae636f82008-01-03 16:47:34 +00001487 if (isVarArg) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001488 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1489 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1490 }
1491 if (Is64Bit) {
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001492 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1493
1494 // FIXME: We should really autogenerate these arrays
1495 static const unsigned GPR64ArgRegsWin64[] = {
1496 X86::RCX, X86::RDX, X86::R8, X86::R9
Gordon Henriksen86737662008-01-05 16:56:59 +00001497 };
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001498 static const unsigned XMMArgRegsWin64[] = {
1499 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1500 };
1501 static const unsigned GPR64ArgRegs64Bit[] = {
1502 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1503 };
1504 static const unsigned XMMArgRegs64Bit[] = {
Gordon Henriksen86737662008-01-05 16:56:59 +00001505 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1506 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1507 };
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001508 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1509
1510 if (IsWin64) {
1511 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1512 GPR64ArgRegs = GPR64ArgRegsWin64;
1513 XMMArgRegs = XMMArgRegsWin64;
1514 } else {
1515 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1516 GPR64ArgRegs = GPR64ArgRegs64Bit;
1517 XMMArgRegs = XMMArgRegs64Bit;
1518 }
1519 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1520 TotalNumIntRegs);
1521 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1522 TotalNumXMMRegs);
1523
Devang Patel578efa92009-06-05 21:57:13 +00001524 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
Evan Chengc7ce29b2009-02-13 22:36:38 +00001525 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
Torok Edwin3f142c32009-02-01 18:15:56 +00001526 "SSE register cannot be used when SSE is disabled!");
Devang Patel578efa92009-06-05 21:57:13 +00001527 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
Evan Chengc7ce29b2009-02-13 22:36:38 +00001528 "SSE register cannot be used when SSE is disabled!");
Devang Patel578efa92009-06-05 21:57:13 +00001529 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
Torok Edwin3f142c32009-02-01 18:15:56 +00001530 // Kernel mode asks for SSE to be disabled, so don't push them
1531 // on the stack.
1532 TotalNumXMMRegs = 0;
Bill Wendlingf9abd7e2009-03-11 22:30:01 +00001533
Gordon Henriksen86737662008-01-05 16:56:59 +00001534 // For X86-64, if there are vararg parameters that are passed via
1535 // registers, then we must store them to their spots on the stack so they
1536 // may be loaded by deferencing the result of va_next.
1537 VarArgsGPOffset = NumIntRegs * 8;
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001538 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1539 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1540 TotalNumXMMRegs * 16, 16);
1541
Gordon Henriksen86737662008-01-05 16:56:59 +00001542 // Store the integer parameter registers.
Dan Gohman475871a2008-07-27 21:46:04 +00001543 SmallVector<SDValue, 8> MemOps;
1544 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
Dale Johannesenace16102009-02-03 19:33:06 +00001545 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
Chris Lattner0bd48932008-01-17 07:00:52 +00001546 DAG.getIntPtrConstant(VarArgsGPOffset));
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001547 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
Bob Wilson998e1252009-04-20 18:36:57 +00001548 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1549 X86::GR64RegisterClass);
Dale Johannesendd64c412009-02-04 00:33:20 +00001550 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
Dan Gohman475871a2008-07-27 21:46:04 +00001551 SDValue Store =
Dale Johannesenace16102009-02-03 19:33:06 +00001552 DAG.getStore(Val.getValue(1), dl, Val, FIN,
Dan Gohmana54cf172008-07-11 22:44:52 +00001553 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
Gordon Henriksen86737662008-01-05 16:56:59 +00001554 MemOps.push_back(Store);
Dale Johannesenace16102009-02-03 19:33:06 +00001555 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
Chris Lattner0bd48932008-01-17 07:00:52 +00001556 DAG.getIntPtrConstant(8));
Gordon Henriksen86737662008-01-05 16:56:59 +00001557 }
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001558
Gordon Henriksen86737662008-01-05 16:56:59 +00001559 // Now store the XMM (fp + vector) parameter registers.
Dale Johannesenace16102009-02-03 19:33:06 +00001560 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
Chris Lattner0bd48932008-01-17 07:00:52 +00001561 DAG.getIntPtrConstant(VarArgsFPOffset));
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001562 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
Bob Wilson998e1252009-04-20 18:36:57 +00001563 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1564 X86::VR128RegisterClass);
Dale Johannesendd64c412009-02-04 00:33:20 +00001565 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::v4f32);
Dan Gohman475871a2008-07-27 21:46:04 +00001566 SDValue Store =
Dale Johannesenace16102009-02-03 19:33:06 +00001567 DAG.getStore(Val.getValue(1), dl, Val, FIN,
Dan Gohmana54cf172008-07-11 22:44:52 +00001568 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
Gordon Henriksen86737662008-01-05 16:56:59 +00001569 MemOps.push_back(Store);
Dale Johannesenace16102009-02-03 19:33:06 +00001570 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
Chris Lattner0bd48932008-01-17 07:00:52 +00001571 DAG.getIntPtrConstant(16));
Gordon Henriksen86737662008-01-05 16:56:59 +00001572 }
1573 if (!MemOps.empty())
Dale Johannesenace16102009-02-03 19:33:06 +00001574 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Gordon Henriksen86737662008-01-05 16:56:59 +00001575 &MemOps[0], MemOps.size());
1576 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001577 }
Scott Michelfdc40a02009-02-17 22:15:04 +00001578
Gordon Henriksenae636f82008-01-03 16:47:34 +00001579 ArgValues.push_back(Root);
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001580
Gordon Henriksen86737662008-01-05 16:56:59 +00001581 // Some CCs need callee pop.
Dan Gohman095cc292008-09-13 01:54:27 +00001582 if (IsCalleePop(isVarArg, CC)) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001583 BytesToPopOnReturn = StackSize; // Callee pops everything.
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001584 BytesCallerReserves = 0;
1585 } else {
Anton Korobeynikov1d9bacc2007-03-06 08:12:33 +00001586 BytesToPopOnReturn = 0; // Callee pops nothing.
Chris Lattnerf39f7712007-02-28 05:46:49 +00001587 // If this is an sret function, the return should pop the hidden pointer.
Evan Chengb188dd92008-09-10 18:25:29 +00001588 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op))
Scott Michelfdc40a02009-02-17 22:15:04 +00001589 BytesToPopOnReturn = 4;
Chris Lattnerf39f7712007-02-28 05:46:49 +00001590 BytesCallerReserves = StackSize;
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001591 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001592
Gordon Henriksen86737662008-01-05 16:56:59 +00001593 if (!Is64Bit) {
1594 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1595 if (CC == CallingConv::X86_FastCall)
1596 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1597 }
Evan Cheng25caf632006-05-23 21:06:34 +00001598
Anton Korobeynikova2780e12007-08-15 17:12:32 +00001599 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
Evan Cheng1bc78042006-04-26 01:20:17 +00001600
Evan Cheng25caf632006-05-23 21:06:34 +00001601 // Return the new list of results.
Dale Johannesenace16102009-02-03 19:33:06 +00001602 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
Duncan Sandsaaffa052008-12-01 11:41:29 +00001603 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001604}
1605
Dan Gohman475871a2008-07-27 21:46:04 +00001606SDValue
Dan Gohman095cc292008-09-13 01:54:27 +00001607X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
Dan Gohman475871a2008-07-27 21:46:04 +00001608 const SDValue &StackPtr,
Evan Chengdffbd832008-01-10 00:09:10 +00001609 const CCValAssign &VA,
Dan Gohman475871a2008-07-27 21:46:04 +00001610 SDValue Chain,
Dan Gohman095cc292008-09-13 01:54:27 +00001611 SDValue Arg, ISD::ArgFlagsTy Flags) {
Dale Johannesenace16102009-02-03 19:33:06 +00001612 DebugLoc dl = TheCall->getDebugLoc();
Dan Gohman4fdad172008-02-07 16:28:05 +00001613 unsigned LocMemOffset = VA.getLocMemOffset();
Dan Gohman475871a2008-07-27 21:46:04 +00001614 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
Dale Johannesenace16102009-02-03 19:33:06 +00001615 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
Duncan Sands276dcbd2008-03-21 09:14:45 +00001616 if (Flags.isByVal()) {
Dale Johannesendd64c412009-02-04 00:33:20 +00001617 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
Evan Chengdffbd832008-01-10 00:09:10 +00001618 }
Dale Johannesenace16102009-02-03 19:33:06 +00001619 return DAG.getStore(Chain, dl, Arg, PtrOff,
Dan Gohman3069b872008-02-07 18:41:25 +00001620 PseudoSourceValue::getStack(), LocMemOffset);
Evan Chengdffbd832008-01-10 00:09:10 +00001621}
1622
Bill Wendling64e87322009-01-16 19:25:27 +00001623/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001624/// optimization is performed and it is required.
Scott Michelfdc40a02009-02-17 22:15:04 +00001625SDValue
1626X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
Dan Gohman475871a2008-07-27 21:46:04 +00001627 SDValue &OutRetAddr,
Scott Michelfdc40a02009-02-17 22:15:04 +00001628 SDValue Chain,
1629 bool IsTailCall,
1630 bool Is64Bit,
Dale Johannesenace16102009-02-03 19:33:06 +00001631 int FPDiff,
1632 DebugLoc dl) {
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001633 if (!IsTailCall || FPDiff==0) return Chain;
1634
1635 // Adjust the Return address stack slot.
Duncan Sands83ec4b62008-06-06 12:08:01 +00001636 MVT VT = getPointerTy();
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001637 OutRetAddr = getReturnAddressFrameIndex(DAG);
Bill Wendling64e87322009-01-16 19:25:27 +00001638
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001639 // Load the "old" Return address.
Dale Johannesenace16102009-02-03 19:33:06 +00001640 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
Gabor Greifba36cb52008-08-28 21:40:38 +00001641 return SDValue(OutRetAddr.getNode(), 1);
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001642}
1643
1644/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1645/// optimization is performed and it is required (FPDiff!=0).
Scott Michelfdc40a02009-02-17 22:15:04 +00001646static SDValue
1647EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
Dan Gohman475871a2008-07-27 21:46:04 +00001648 SDValue Chain, SDValue RetAddrFrIdx,
Dale Johannesenace16102009-02-03 19:33:06 +00001649 bool Is64Bit, int FPDiff, DebugLoc dl) {
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001650 // Store the return address to the appropriate stack slot.
1651 if (!FPDiff) return Chain;
1652 // Calculate the new stack slot for the return address.
1653 int SlotSize = Is64Bit ? 8 : 4;
Scott Michelfdc40a02009-02-17 22:15:04 +00001654 int NewReturnAddrFI =
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001655 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
Duncan Sands83ec4b62008-06-06 12:08:01 +00001656 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
Dan Gohman475871a2008-07-27 21:46:04 +00001657 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
Scott Michelfdc40a02009-02-17 22:15:04 +00001658 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
Dan Gohmana54cf172008-07-11 22:44:52 +00001659 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001660 return Chain;
1661}
1662
Dan Gohman475871a2008-07-27 21:46:04 +00001663SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001664 MachineFunction &MF = DAG.getMachineFunction();
Dan Gohman095cc292008-09-13 01:54:27 +00001665 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
1666 SDValue Chain = TheCall->getChain();
1667 unsigned CC = TheCall->getCallingConv();
1668 bool isVarArg = TheCall->isVarArg();
1669 bool IsTailCall = TheCall->isTailCall() &&
1670 CC == CallingConv::Fast && PerformTailCallOpt;
1671 SDValue Callee = TheCall->getCallee();
Gordon Henriksen86737662008-01-05 16:56:59 +00001672 bool Is64Bit = Subtarget->is64Bit();
Dan Gohman095cc292008-09-13 01:54:27 +00001673 bool IsStructRet = CallIsStructReturn(TheCall);
Dale Johannesenace16102009-02-03 19:33:06 +00001674 DebugLoc dl = TheCall->getDebugLoc();
Gordon Henriksenae636f82008-01-03 16:47:34 +00001675
1676 assert(!(isVarArg && CC == CallingConv::Fast) &&
1677 "Var args not supported with calling convention fastcc");
1678
Chris Lattner638402b2007-02-28 07:00:42 +00001679 // Analyze operands of the call, assigning locations to each operand.
Chris Lattner423c5f42007-02-28 05:31:48 +00001680 SmallVector<CCValAssign, 16> ArgLocs;
Chris Lattner52387be2007-06-19 00:13:10 +00001681 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
Dan Gohman095cc292008-09-13 01:54:27 +00001682 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC));
Scott Michelfdc40a02009-02-17 22:15:04 +00001683
Chris Lattner423c5f42007-02-28 05:31:48 +00001684 // Get a count of how many bytes are to be pushed on the stack.
1685 unsigned NumBytes = CCInfo.getNextStackOffset();
Arnold Schwaighofer1fdc40f2008-09-11 20:28:43 +00001686 if (PerformTailCallOpt && CC == CallingConv::Fast)
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001687 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001688
Gordon Henriksen86737662008-01-05 16:56:59 +00001689 int FPDiff = 0;
1690 if (IsTailCall) {
1691 // Lower arguments at fp - stackoffset + fpdiff.
Scott Michelfdc40a02009-02-17 22:15:04 +00001692 unsigned NumBytesCallerPushed =
Gordon Henriksen86737662008-01-05 16:56:59 +00001693 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1694 FPDiff = NumBytesCallerPushed - NumBytes;
1695
1696 // Set the delta of movement of the returnaddr stackslot.
1697 // But only set if delta is greater than previous delta.
1698 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1699 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1700 }
1701
Chris Lattnere563bbc2008-10-11 22:08:30 +00001702 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001703
Dan Gohman475871a2008-07-27 21:46:04 +00001704 SDValue RetAddrFrIdx;
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001705 // Load return adress for tail calls.
1706 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
Dale Johannesenace16102009-02-03 19:33:06 +00001707 FPDiff, dl);
Gordon Henriksen86737662008-01-05 16:56:59 +00001708
Dan Gohman475871a2008-07-27 21:46:04 +00001709 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1710 SmallVector<SDValue, 8> MemOpChains;
1711 SDValue StackPtr;
Chris Lattner423c5f42007-02-28 05:31:48 +00001712
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00001713 // Walk the register/memloc assignments, inserting copies/loads. In the case
1714 // of tail call optimization arguments are handle later.
Chris Lattner423c5f42007-02-28 05:31:48 +00001715 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1716 CCValAssign &VA = ArgLocs[i];
Dan Gohman095cc292008-09-13 01:54:27 +00001717 SDValue Arg = TheCall->getArg(i);
1718 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1719 bool isByVal = Flags.isByVal();
Scott Michelfdc40a02009-02-17 22:15:04 +00001720
Chris Lattner423c5f42007-02-28 05:31:48 +00001721 // Promote the value if needed.
1722 switch (VA.getLocInfo()) {
1723 default: assert(0 && "Unknown loc info!");
1724 case CCValAssign::Full: break;
1725 case CCValAssign::SExt:
Dale Johannesenace16102009-02-03 19:33:06 +00001726 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
Chris Lattner423c5f42007-02-28 05:31:48 +00001727 break;
1728 case CCValAssign::ZExt:
Dale Johannesenace16102009-02-03 19:33:06 +00001729 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
Chris Lattner423c5f42007-02-28 05:31:48 +00001730 break;
1731 case CCValAssign::AExt:
Dale Johannesenace16102009-02-03 19:33:06 +00001732 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
Chris Lattner423c5f42007-02-28 05:31:48 +00001733 break;
Evan Cheng6b5783d2006-05-25 18:56:34 +00001734 }
Scott Michelfdc40a02009-02-17 22:15:04 +00001735
Chris Lattner423c5f42007-02-28 05:31:48 +00001736 if (VA.isRegLoc()) {
Evan Cheng10e86422008-04-25 19:11:04 +00001737 if (Is64Bit) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00001738 MVT RegVT = VA.getLocVT();
1739 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
Evan Cheng10e86422008-04-25 19:11:04 +00001740 switch (VA.getLocReg()) {
1741 default:
1742 break;
1743 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1744 case X86::R8: {
1745 // Special case: passing MMX values in GPR registers.
Dale Johannesenace16102009-02-03 19:33:06 +00001746 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
Evan Cheng10e86422008-04-25 19:11:04 +00001747 break;
1748 }
1749 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1750 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1751 // Special case: passing MMX values in XMM registers.
Dale Johannesenace16102009-02-03 19:33:06 +00001752 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1753 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
Nate Begeman9008ca62009-04-27 18:41:29 +00001754 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
Evan Cheng10e86422008-04-25 19:11:04 +00001755 break;
1756 }
1757 }
1758 }
Chris Lattner423c5f42007-02-28 05:31:48 +00001759 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1760 } else {
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001761 if (!IsTailCall || (IsTailCall && isByVal)) {
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001762 assert(VA.isMemLoc());
Gabor Greifba36cb52008-08-28 21:40:38 +00001763 if (StackPtr.getNode() == 0)
Dale Johannesendd64c412009-02-04 00:33:20 +00001764 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
Scott Michelfdc40a02009-02-17 22:15:04 +00001765
Dan Gohman095cc292008-09-13 01:54:27 +00001766 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
1767 Chain, Arg, Flags));
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001768 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001769 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001770 }
Scott Michelfdc40a02009-02-17 22:15:04 +00001771
Evan Cheng32fe1032006-05-25 00:59:30 +00001772 if (!MemOpChains.empty())
Dale Johannesenace16102009-02-03 19:33:06 +00001773 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Chris Lattnerbd564bf2006-08-08 02:23:42 +00001774 &MemOpChains[0], MemOpChains.size());
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001775
Evan Cheng347d5f72006-04-28 21:29:37 +00001776 // Build a sequence of copy-to-reg nodes chained together with token chain
1777 // and flag operands which copy the outgoing args into registers.
Dan Gohman475871a2008-07-27 21:46:04 +00001778 SDValue InFlag;
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00001779 // Tail call byval lowering might overwrite argument registers so in case of
1780 // tail call optimization the copies to registers are lowered later.
1781 if (!IsTailCall)
1782 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
Scott Michelfdc40a02009-02-17 22:15:04 +00001783 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
Dale Johannesendd64c412009-02-04 00:33:20 +00001784 RegsToPass[i].second, InFlag);
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00001785 InFlag = Chain.getValue(1);
1786 }
Gordon Henriksen86737662008-01-05 16:56:59 +00001787
Chris Lattner951bf7d2009-07-09 02:44:11 +00001788
Chris Lattner88e1fd52009-07-09 04:24:46 +00001789 if (Subtarget->isPICStyleGOT()) {
Chris Lattnerb133a0a2009-07-09 02:55:47 +00001790 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1791 // GOT pointer.
1792 if (!IsTailCall) {
1793 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1794 DAG.getNode(X86ISD::GlobalBaseReg,
1795 DebugLoc::getUnknownLoc(),
1796 getPointerTy()),
1797 InFlag);
1798 InFlag = Chain.getValue(1);
1799 } else {
1800 // If we are tail calling and generating PIC/GOT style code load the
1801 // address of the callee into ECX. The value in ecx is used as target of
1802 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1803 // for tail calls on PIC/GOT architectures. Normally we would just put the
1804 // address of GOT into ebx and then call target@PLT. But for tail calls
1805 // ebx would be restored (since ebx is callee saved) before jumping to the
1806 // target@PLT.
1807
1808 // Note: The actual moving to ECX is done further down.
1809 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1810 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1811 !G->getGlobal()->hasProtectedVisibility())
1812 Callee = LowerGlobalAddress(Callee, DAG);
1813 else if (isa<ExternalSymbolSDNode>(Callee))
1814 Callee = LowerExternalSymbol(Callee,DAG);
1815 }
Anton Korobeynikov7f705592007-01-12 19:20:47 +00001816 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001817
Gordon Henriksen86737662008-01-05 16:56:59 +00001818 if (Is64Bit && isVarArg) {
1819 // From AMD64 ABI document:
1820 // For calls that may call functions that use varargs or stdargs
1821 // (prototype-less calls or calls to functions containing ellipsis (...) in
1822 // the declaration) %al is used as hidden argument to specify the number
1823 // of SSE registers used. The contents of %al do not need to match exactly
1824 // the number of registers, but must be an ubound on the number of SSE
1825 // registers used and is in the range 0 - 8 inclusive.
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001826
1827 // FIXME: Verify this on Win64
Gordon Henriksen86737662008-01-05 16:56:59 +00001828 // Count the number of XMM registers allocated.
1829 static const unsigned XMMArgRegs[] = {
1830 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1831 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1832 };
1833 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
Scott Michelfdc40a02009-02-17 22:15:04 +00001834 assert((Subtarget->hasSSE1() || !NumXMMRegs)
Torok Edwin3f142c32009-02-01 18:15:56 +00001835 && "SSE registers cannot be used when SSE is disabled");
Scott Michelfdc40a02009-02-17 22:15:04 +00001836
Dale Johannesendd64c412009-02-04 00:33:20 +00001837 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
Gordon Henriksen86737662008-01-05 16:56:59 +00001838 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1839 InFlag = Chain.getValue(1);
1840 }
1841
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001842
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001843 // For tail calls lower the arguments to the 'real' stack slot.
Gordon Henriksen86737662008-01-05 16:56:59 +00001844 if (IsTailCall) {
Dan Gohman475871a2008-07-27 21:46:04 +00001845 SmallVector<SDValue, 8> MemOpChains2;
1846 SDValue FIN;
Gordon Henriksen86737662008-01-05 16:56:59 +00001847 int FI = 0;
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001848 // Do not flag preceeding copytoreg stuff together with the following stuff.
Dan Gohman475871a2008-07-27 21:46:04 +00001849 InFlag = SDValue();
Gordon Henriksen86737662008-01-05 16:56:59 +00001850 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1851 CCValAssign &VA = ArgLocs[i];
1852 if (!VA.isRegLoc()) {
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001853 assert(VA.isMemLoc());
Dan Gohman095cc292008-09-13 01:54:27 +00001854 SDValue Arg = TheCall->getArg(i);
1855 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
Gordon Henriksen86737662008-01-05 16:56:59 +00001856 // Create frame index.
1857 int32_t Offset = VA.getLocMemOffset()+FPDiff;
Duncan Sands83ec4b62008-06-06 12:08:01 +00001858 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
Gordon Henriksen86737662008-01-05 16:56:59 +00001859 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001860 FIN = DAG.getFrameIndex(FI, getPointerTy());
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001861
Duncan Sands276dcbd2008-03-21 09:14:45 +00001862 if (Flags.isByVal()) {
Evan Cheng8e5712b2008-01-12 01:08:07 +00001863 // Copy relative to framepointer.
Dan Gohman475871a2008-07-27 21:46:04 +00001864 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
Gabor Greifba36cb52008-08-28 21:40:38 +00001865 if (StackPtr.getNode() == 0)
Scott Michelfdc40a02009-02-17 22:15:04 +00001866 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
Dale Johannesendd64c412009-02-04 00:33:20 +00001867 getPointerTy());
Dale Johannesenace16102009-02-03 19:33:06 +00001868 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001869
1870 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
Dale Johannesendd64c412009-02-04 00:33:20 +00001871 Flags, DAG, dl));
Gordon Henriksen86737662008-01-05 16:56:59 +00001872 } else {
Evan Cheng8e5712b2008-01-12 01:08:07 +00001873 // Store relative to framepointer.
Dan Gohman69de1932008-02-06 22:27:42 +00001874 MemOpChains2.push_back(
Dale Johannesenace16102009-02-03 19:33:06 +00001875 DAG.getStore(Chain, dl, Arg, FIN,
Dan Gohmana54cf172008-07-11 22:44:52 +00001876 PseudoSourceValue::getFixedStack(FI), 0));
Scott Michelfdc40a02009-02-17 22:15:04 +00001877 }
Gordon Henriksen86737662008-01-05 16:56:59 +00001878 }
1879 }
1880
1881 if (!MemOpChains2.empty())
Dale Johannesenace16102009-02-03 19:33:06 +00001882 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Arnold Schwaighofer719eb022008-01-11 14:34:56 +00001883 &MemOpChains2[0], MemOpChains2.size());
Gordon Henriksen86737662008-01-05 16:56:59 +00001884
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00001885 // Copy arguments to their registers.
1886 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
Scott Michelfdc40a02009-02-17 22:15:04 +00001887 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
Dale Johannesendd64c412009-02-04 00:33:20 +00001888 RegsToPass[i].second, InFlag);
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00001889 InFlag = Chain.getValue(1);
1890 }
Dan Gohman475871a2008-07-27 21:46:04 +00001891 InFlag =SDValue();
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001892
Gordon Henriksen86737662008-01-05 16:56:59 +00001893 // Store the return address to the appropriate stack slot.
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001894 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
Dale Johannesenace16102009-02-03 19:33:06 +00001895 FPDiff, dl);
Gordon Henriksen86737662008-01-05 16:56:59 +00001896 }
1897
Evan Cheng32fe1032006-05-25 00:59:30 +00001898 // If the callee is a GlobalAddress node (quite common, every direct call is)
1899 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
Anton Korobeynikova5986852006-11-20 10:46:14 +00001900 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
Anton Korobeynikov2b2bc682006-12-22 22:29:05 +00001901 // We should use extra load for direct calls to dllimported functions in
1902 // non-JIT mode.
Evan Cheng817a6a92008-07-16 01:34:02 +00001903 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1904 getTargetMachine(), true))
Dan Gohman6520e202008-10-18 02:06:02 +00001905 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy(),
1906 G->getOffset());
Bill Wendling056292f2008-09-16 21:48:12 +00001907 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1908 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
Gordon Henriksen86737662008-01-05 16:56:59 +00001909 } else if (IsTailCall) {
Arnold Schwaighoferbbd8c332009-06-12 16:26:57 +00001910 unsigned Opc = Is64Bit ? X86::R11 : X86::EAX;
Gordon Henriksen86737662008-01-05 16:56:59 +00001911
Dale Johannesendd64c412009-02-04 00:33:20 +00001912 Chain = DAG.getCopyToReg(Chain, dl,
Scott Michelfdc40a02009-02-17 22:15:04 +00001913 DAG.getRegister(Opc, getPointerTy()),
Gordon Henriksen86737662008-01-05 16:56:59 +00001914 Callee,InFlag);
1915 Callee = DAG.getRegister(Opc, getPointerTy());
1916 // Add register as live out.
1917 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
Gordon Henriksenae636f82008-01-03 16:47:34 +00001918 }
Scott Michelfdc40a02009-02-17 22:15:04 +00001919
Chris Lattnerd96d0722007-02-25 06:40:16 +00001920 // Returns a chain & a flag for retval copy to use.
1921 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00001922 SmallVector<SDValue, 8> Ops;
Gordon Henriksen86737662008-01-05 16:56:59 +00001923
1924 if (IsTailCall) {
Dale Johannesene8d72302009-02-06 23:05:02 +00001925 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1926 DAG.getIntPtrConstant(0, true), InFlag);
Gordon Henriksen86737662008-01-05 16:56:59 +00001927 InFlag = Chain.getValue(1);
Scott Michelfdc40a02009-02-17 22:15:04 +00001928
Gordon Henriksen86737662008-01-05 16:56:59 +00001929 // Returns a chain & a flag for retval copy to use.
1930 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1931 Ops.clear();
1932 }
Scott Michelfdc40a02009-02-17 22:15:04 +00001933
Nate Begeman4c5dcf52006-02-17 00:03:04 +00001934 Ops.push_back(Chain);
1935 Ops.push_back(Callee);
Evan Chengb69d1132006-06-14 18:17:40 +00001936
Gordon Henriksen86737662008-01-05 16:56:59 +00001937 if (IsTailCall)
1938 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
Evan Chengf4684712007-02-21 21:18:14 +00001939
Gordon Henriksen86737662008-01-05 16:56:59 +00001940 // Add argument registers to the end of the list so that they are known live
1941 // into the call.
Evan Cheng9b449442008-01-07 23:08:23 +00001942 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1943 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1944 RegsToPass[i].second.getValueType()));
Scott Michelfdc40a02009-02-17 22:15:04 +00001945
Evan Cheng586ccac2008-03-18 23:36:35 +00001946 // Add an implicit use GOT pointer in EBX.
Chris Lattner88e1fd52009-07-09 04:24:46 +00001947 if (!IsTailCall && Subtarget->isPICStyleGOT())
Evan Cheng586ccac2008-03-18 23:36:35 +00001948 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1949
1950 // Add an implicit use of AL for x86 vararg functions.
1951 if (Is64Bit && isVarArg)
1952 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1953
Gabor Greifba36cb52008-08-28 21:40:38 +00001954 if (InFlag.getNode())
Evan Cheng347d5f72006-04-28 21:29:37 +00001955 Ops.push_back(InFlag);
Gordon Henriksenae636f82008-01-03 16:47:34 +00001956
Gordon Henriksen86737662008-01-05 16:56:59 +00001957 if (IsTailCall) {
Scott Michelfdc40a02009-02-17 22:15:04 +00001958 assert(InFlag.getNode() &&
Gordon Henriksen86737662008-01-05 16:56:59 +00001959 "Flag must be set. Depend on flag being set in LowerRET");
Dale Johannesenace16102009-02-03 19:33:06 +00001960 Chain = DAG.getNode(X86ISD::TAILCALL, dl,
Dan Gohman095cc292008-09-13 01:54:27 +00001961 TheCall->getVTList(), &Ops[0], Ops.size());
Scott Michelfdc40a02009-02-17 22:15:04 +00001962
Gabor Greifba36cb52008-08-28 21:40:38 +00001963 return SDValue(Chain.getNode(), Op.getResNo());
Gordon Henriksen86737662008-01-05 16:56:59 +00001964 }
1965
Dale Johannesenace16102009-02-03 19:33:06 +00001966 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
Evan Cheng347d5f72006-04-28 21:29:37 +00001967 InFlag = Chain.getValue(1);
Evan Chengd90eb7f2006-01-05 00:27:02 +00001968
Chris Lattner2d297092006-05-23 18:50:38 +00001969 // Create the CALLSEQ_END node.
Gordon Henriksen86737662008-01-05 16:56:59 +00001970 unsigned NumBytesForCalleeToPush;
Dan Gohman095cc292008-09-13 01:54:27 +00001971 if (IsCalleePop(isVarArg, CC))
Gordon Henriksen86737662008-01-05 16:56:59 +00001972 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
Evan Chengb188dd92008-09-10 18:25:29 +00001973 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet)
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001974 // If this is is a call to a struct-return function, the callee
1975 // pops the hidden struct pointer, so we have to push it back.
1976 // This is common for Darwin/X86, Linux & Mingw32 targets.
Gordon Henriksenae636f82008-01-03 16:47:34 +00001977 NumBytesForCalleeToPush = 4;
Gordon Henriksen86737662008-01-05 16:56:59 +00001978 else
Gordon Henriksenae636f82008-01-03 16:47:34 +00001979 NumBytesForCalleeToPush = 0; // Callee pops nothing.
Scott Michelfdc40a02009-02-17 22:15:04 +00001980
Gordon Henriksenae636f82008-01-03 16:47:34 +00001981 // Returns a flag for retval copy to use.
Bill Wendling0f8d9c02007-11-13 00:44:25 +00001982 Chain = DAG.getCALLSEQ_END(Chain,
Chris Lattnere563bbc2008-10-11 22:08:30 +00001983 DAG.getIntPtrConstant(NumBytes, true),
1984 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
1985 true),
Bill Wendling0f8d9c02007-11-13 00:44:25 +00001986 InFlag);
Chris Lattner3085e152007-02-25 08:59:22 +00001987 InFlag = Chain.getValue(1);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00001988
Chris Lattner3085e152007-02-25 08:59:22 +00001989 // Handle result values, copying them out of physregs into vregs that we
1990 // return.
Dan Gohman095cc292008-09-13 01:54:27 +00001991 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
Gabor Greif327ef032008-08-28 23:19:51 +00001992 Op.getResNo());
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001993}
1994
Evan Cheng25ab6902006-09-08 06:48:29 +00001995
1996//===----------------------------------------------------------------------===//
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001997// Fast Calling Convention (tail call) implementation
1998//===----------------------------------------------------------------------===//
1999
2000// Like std call, callee cleans arguments, convention except that ECX is
2001// reserved for storing the tail called function address. Only 2 registers are
2002// free for argument passing (inreg). Tail call optimization is performed
2003// provided:
2004// * tailcallopt is enabled
2005// * caller/callee are fastcc
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00002006// On X86_64 architecture with GOT-style position independent code only local
2007// (within module) calls are supported at the moment.
Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +00002008// To keep the stack aligned according to platform abi the function
2009// GetAlignedArgumentStackSize ensures that argument delta is always multiples
2010// of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00002011// If a tail called function callee has more arguments than the caller the
2012// caller needs to make sure that there is room to move the RETADDR to. This is
Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +00002013// achieved by reserving an area the size of the argument delta right after the
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00002014// original REtADDR, but before the saved framepointer or the spilled registers
2015// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2016// stack layout:
2017// arg1
2018// arg2
2019// RETADDR
Scott Michelfdc40a02009-02-17 22:15:04 +00002020// [ new RETADDR
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00002021// move area ]
2022// (possible EBP)
2023// ESI
2024// EDI
2025// local1 ..
2026
2027/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2028/// for a 16 byte align requirement.
Scott Michelfdc40a02009-02-17 22:15:04 +00002029unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00002030 SelectionDAG& DAG) {
Evan Chenge9ac9e62008-09-07 09:07:23 +00002031 MachineFunction &MF = DAG.getMachineFunction();
2032 const TargetMachine &TM = MF.getTarget();
2033 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2034 unsigned StackAlignment = TFI.getStackAlignment();
Scott Michelfdc40a02009-02-17 22:15:04 +00002035 uint64_t AlignMask = StackAlignment - 1;
Evan Chenge9ac9e62008-09-07 09:07:23 +00002036 int64_t Offset = StackSize;
Anton Korobeynikovbff66b02008-09-09 18:22:57 +00002037 uint64_t SlotSize = TD->getPointerSize();
Evan Chenge9ac9e62008-09-07 09:07:23 +00002038 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2039 // Number smaller than 12 so just add the difference.
2040 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2041 } else {
2042 // Mask out lower bits, add stackalignment once plus the 12 bytes.
Scott Michelfdc40a02009-02-17 22:15:04 +00002043 Offset = ((~AlignMask) & Offset) + StackAlignment +
Evan Chenge9ac9e62008-09-07 09:07:23 +00002044 (StackAlignment-SlotSize);
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00002045 }
Evan Chenge9ac9e62008-09-07 09:07:23 +00002046 return Offset;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00002047}
2048
2049/// IsEligibleForTailCallElimination - Check to see whether the next instruction
Evan Cheng9df7dc52007-11-02 01:26:22 +00002050/// following the call is a return. A function is eligible if caller/callee
2051/// calling conventions match, currently only fastcc supports tail calls, and
2052/// the function CALL is immediatly followed by a RET.
Dan Gohman095cc292008-09-13 01:54:27 +00002053bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
Dan Gohman475871a2008-07-27 21:46:04 +00002054 SDValue Ret,
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00002055 SelectionDAG& DAG) const {
Evan Cheng9df7dc52007-11-02 01:26:22 +00002056 if (!PerformTailCallOpt)
2057 return false;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00002058
Dan Gohman095cc292008-09-13 01:54:27 +00002059 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00002060 MachineFunction &MF = DAG.getMachineFunction();
2061 unsigned CallerCC = MF.getFunction()->getCallingConv();
Dan Gohman095cc292008-09-13 01:54:27 +00002062 unsigned CalleeCC= TheCall->getCallingConv();
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00002063 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
Chris Lattnerb133a0a2009-07-09 02:55:47 +00002064 // On x86/32Bit PIC/GOT tail calls are supported.
Evan Cheng9df7dc52007-11-02 01:26:22 +00002065 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
Chris Lattnerb133a0a2009-07-09 02:55:47 +00002066 !Subtarget->isPICStyleGOT() || !Subtarget->is64Bit())
Evan Cheng9df7dc52007-11-02 01:26:22 +00002067 return true;
Chris Lattner88e1fd52009-07-09 04:24:46 +00002068
2069 SDValue Callee = TheCall->getCallee();
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00002070 // Can only do local tail calls (in same module, hidden or protected) on
2071 // x86_64 PIC/GOT at the moment.
Gordon Henriksen86737662008-01-05 16:56:59 +00002072 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2073 return G->getGlobal()->hasHiddenVisibility()
2074 || G->getGlobal()->hasProtectedVisibility();
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00002075 }
2076 }
Evan Cheng9df7dc52007-11-02 01:26:22 +00002077
2078 return false;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00002079}
2080
Dan Gohman3df24e62008-09-03 23:12:08 +00002081FastISel *
2082X86TargetLowering::createFastISel(MachineFunction &mf,
Dan Gohmand57dd5f2008-09-23 21:53:34 +00002083 MachineModuleInfo *mmo,
Devang Patel83489bb2009-01-13 00:35:13 +00002084 DwarfWriter *dw,
Dan Gohman3df24e62008-09-03 23:12:08 +00002085 DenseMap<const Value *, unsigned> &vm,
2086 DenseMap<const BasicBlock *,
Dan Gohman0586d912008-09-10 20:11:02 +00002087 MachineBasicBlock *> &bm,
Dan Gohmandd5b58a2008-10-14 23:54:11 +00002088 DenseMap<const AllocaInst *, int> &am
2089#ifndef NDEBUG
2090 , SmallSet<Instruction*, 8> &cil
2091#endif
2092 ) {
Devang Patel83489bb2009-01-13 00:35:13 +00002093 return X86::createFastISel(mf, mmo, dw, vm, bm, am
Dan Gohmandd5b58a2008-10-14 23:54:11 +00002094#ifndef NDEBUG
2095 , cil
2096#endif
2097 );
Dan Gohmand9f3c482008-08-19 21:32:53 +00002098}
2099
2100
Chris Lattnerfcf1a3d2007-02-28 06:10:12 +00002101//===----------------------------------------------------------------------===//
2102// Other Lowering Hooks
2103//===----------------------------------------------------------------------===//
2104
2105
Dan Gohman475871a2008-07-27 21:46:04 +00002106SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
Anton Korobeynikova2780e12007-08-15 17:12:32 +00002107 MachineFunction &MF = DAG.getMachineFunction();
2108 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2109 int ReturnAddrIndex = FuncInfo->getRAIndex();
2110
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00002111 if (ReturnAddrIndex == 0) {
2112 // Set up a frame object for the return address.
Bill Wendling64e87322009-01-16 19:25:27 +00002113 uint64_t SlotSize = TD->getPointerSize();
Anton Korobeynikovbff66b02008-09-09 18:22:57 +00002114 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
Anton Korobeynikova2780e12007-08-15 17:12:32 +00002115 FuncInfo->setRAIndex(ReturnAddrIndex);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00002116 }
2117
Evan Cheng25ab6902006-09-08 06:48:29 +00002118 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00002119}
2120
2121
Chris Lattner1c39d4c2008-12-24 23:53:05 +00002122/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2123/// specific condition code, returning the condition code and the LHS/RHS of the
2124/// comparison to make.
2125static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2126 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
Evan Chengd9558e02006-01-06 00:43:03 +00002127 if (!isFP) {
Chris Lattnerbfd68a72006-09-13 17:04:54 +00002128 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2129 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2130 // X > -1 -> X == 0, jump !sign.
2131 RHS = DAG.getConstant(0, RHS.getValueType());
Chris Lattner1c39d4c2008-12-24 23:53:05 +00002132 return X86::COND_NS;
Chris Lattnerbfd68a72006-09-13 17:04:54 +00002133 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2134 // X < 0 -> X == 0, jump on sign.
Chris Lattner1c39d4c2008-12-24 23:53:05 +00002135 return X86::COND_S;
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002136 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
Dan Gohman5f6913c2007-09-17 14:49:27 +00002137 // X < 1 -> X <= 0
2138 RHS = DAG.getConstant(0, RHS.getValueType());
Chris Lattner1c39d4c2008-12-24 23:53:05 +00002139 return X86::COND_LE;
Chris Lattnerbfd68a72006-09-13 17:04:54 +00002140 }
Chris Lattnerf9570512006-09-13 03:22:10 +00002141 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00002142
Evan Chengd9558e02006-01-06 00:43:03 +00002143 switch (SetCCOpcode) {
Chris Lattner4c78e022008-12-23 23:42:27 +00002144 default: assert(0 && "Invalid integer condition!");
Chris Lattner1c39d4c2008-12-24 23:53:05 +00002145 case ISD::SETEQ: return X86::COND_E;
2146 case ISD::SETGT: return X86::COND_G;
2147 case ISD::SETGE: return X86::COND_GE;
2148 case ISD::SETLT: return X86::COND_L;
2149 case ISD::SETLE: return X86::COND_LE;
2150 case ISD::SETNE: return X86::COND_NE;
2151 case ISD::SETULT: return X86::COND_B;
2152 case ISD::SETUGT: return X86::COND_A;
2153 case ISD::SETULE: return X86::COND_BE;
2154 case ISD::SETUGE: return X86::COND_AE;
Evan Chengd9558e02006-01-06 00:43:03 +00002155 }
Chris Lattner4c78e022008-12-23 23:42:27 +00002156 }
Scott Michelfdc40a02009-02-17 22:15:04 +00002157
Chris Lattner4c78e022008-12-23 23:42:27 +00002158 // First determine if it is required or is profitable to flip the operands.
Duncan Sands4047f4a2008-10-24 13:03:10 +00002159
Chris Lattner4c78e022008-12-23 23:42:27 +00002160 // If LHS is a foldable load, but RHS is not, flip the condition.
2161 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2162 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2163 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2164 std::swap(LHS, RHS);
Evan Cheng4d46d0a2008-08-28 23:48:31 +00002165 }
2166
Chris Lattner4c78e022008-12-23 23:42:27 +00002167 switch (SetCCOpcode) {
2168 default: break;
2169 case ISD::SETOLT:
2170 case ISD::SETOLE:
2171 case ISD::SETUGT:
2172 case ISD::SETUGE:
2173 std::swap(LHS, RHS);
2174 break;
2175 }
2176
2177 // On a floating point condition, the flags are set as follows:
2178 // ZF PF CF op
2179 // 0 | 0 | 0 | X > Y
2180 // 0 | 0 | 1 | X < Y
2181 // 1 | 0 | 0 | X == Y
2182 // 1 | 1 | 1 | unordered
2183 switch (SetCCOpcode) {
Chris Lattner1c39d4c2008-12-24 23:53:05 +00002184 default: assert(0 && "Condcode should be pre-legalized away");
Chris Lattner4c78e022008-12-23 23:42:27 +00002185 case ISD::SETUEQ:
Chris Lattner1c39d4c2008-12-24 23:53:05 +00002186 case ISD::SETEQ: return X86::COND_E;
Chris Lattner4c78e022008-12-23 23:42:27 +00002187 case ISD::SETOLT: // flipped
2188 case ISD::SETOGT:
Chris Lattner1c39d4c2008-12-24 23:53:05 +00002189 case ISD::SETGT: return X86::COND_A;
Chris Lattner4c78e022008-12-23 23:42:27 +00002190 case ISD::SETOLE: // flipped
2191 case ISD::SETOGE:
Chris Lattner1c39d4c2008-12-24 23:53:05 +00002192 case ISD::SETGE: return X86::COND_AE;
Chris Lattner4c78e022008-12-23 23:42:27 +00002193 case ISD::SETUGT: // flipped
2194 case ISD::SETULT:
Chris Lattner1c39d4c2008-12-24 23:53:05 +00002195 case ISD::SETLT: return X86::COND_B;
Chris Lattner4c78e022008-12-23 23:42:27 +00002196 case ISD::SETUGE: // flipped
2197 case ISD::SETULE:
Chris Lattner1c39d4c2008-12-24 23:53:05 +00002198 case ISD::SETLE: return X86::COND_BE;
Chris Lattner4c78e022008-12-23 23:42:27 +00002199 case ISD::SETONE:
Chris Lattner1c39d4c2008-12-24 23:53:05 +00002200 case ISD::SETNE: return X86::COND_NE;
2201 case ISD::SETUO: return X86::COND_P;
2202 case ISD::SETO: return X86::COND_NP;
Chris Lattner4c78e022008-12-23 23:42:27 +00002203 }
Evan Chengd9558e02006-01-06 00:43:03 +00002204}
2205
Evan Cheng4a460802006-01-11 00:33:36 +00002206/// hasFPCMov - is there a floating point cmov for the specific X86 condition
2207/// code. Current x86 isa includes the following FP cmov instructions:
Evan Chengaaca22c2006-01-10 20:26:56 +00002208/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
Evan Cheng4a460802006-01-11 00:33:36 +00002209static bool hasFPCMov(unsigned X86CC) {
Evan Chengaaca22c2006-01-10 20:26:56 +00002210 switch (X86CC) {
2211 default:
2212 return false;
Chris Lattner7fbe9722006-10-20 17:42:20 +00002213 case X86::COND_B:
2214 case X86::COND_BE:
2215 case X86::COND_E:
2216 case X86::COND_P:
2217 case X86::COND_A:
2218 case X86::COND_AE:
2219 case X86::COND_NE:
2220 case X86::COND_NP:
Evan Chengaaca22c2006-01-10 20:26:56 +00002221 return true;
2222 }
2223}
2224
Nate Begeman9008ca62009-04-27 18:41:29 +00002225/// isUndefOrInRange - Return true if Val is undef or if its value falls within
2226/// the specified range (L, H].
2227static bool isUndefOrInRange(int Val, int Low, int Hi) {
2228 return (Val < 0) || (Val >= Low && Val < Hi);
2229}
2230
2231/// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2232/// specified value.
2233static bool isUndefOrEqual(int Val, int CmpVal) {
2234 if (Val < 0 || Val == CmpVal)
Evan Cheng5ced1d82006-04-06 23:23:56 +00002235 return true;
Nate Begeman9008ca62009-04-27 18:41:29 +00002236 return false;
Evan Chengc5cdff22006-04-07 21:53:05 +00002237}
2238
Nate Begeman9008ca62009-04-27 18:41:29 +00002239/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2240/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2241/// the second operand.
Nate Begeman5a5ca152009-04-29 05:20:52 +00002242static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, MVT VT) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002243 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2244 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2245 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2246 return (Mask[0] < 2 && Mask[1] < 2);
2247 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002248}
2249
Nate Begeman9008ca62009-04-27 18:41:29 +00002250bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2251 SmallVector<int, 8> M;
2252 N->getMask(M);
2253 return ::isPSHUFDMask(M, N->getValueType(0));
2254}
Evan Cheng0188ecb2006-03-22 18:59:22 +00002255
Nate Begeman9008ca62009-04-27 18:41:29 +00002256/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2257/// is suitable for input to PSHUFHW.
Nate Begeman5a5ca152009-04-29 05:20:52 +00002258static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, MVT VT) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002259 if (VT != MVT::v8i16)
Evan Cheng0188ecb2006-03-22 18:59:22 +00002260 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002261
2262 // Lower quadword copied in order or undef.
2263 for (int i = 0; i != 4; ++i)
2264 if (Mask[i] >= 0 && Mask[i] != i)
Evan Cheng506d3df2006-03-29 23:07:14 +00002265 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002266
Evan Cheng506d3df2006-03-29 23:07:14 +00002267 // Upper quadword shuffled.
Nate Begeman9008ca62009-04-27 18:41:29 +00002268 for (int i = 4; i != 8; ++i)
2269 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
Evan Cheng506d3df2006-03-29 23:07:14 +00002270 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002271
Evan Cheng506d3df2006-03-29 23:07:14 +00002272 return true;
2273}
2274
Nate Begeman9008ca62009-04-27 18:41:29 +00002275bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2276 SmallVector<int, 8> M;
2277 N->getMask(M);
2278 return ::isPSHUFHWMask(M, N->getValueType(0));
2279}
Evan Cheng506d3df2006-03-29 23:07:14 +00002280
Nate Begeman9008ca62009-04-27 18:41:29 +00002281/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2282/// is suitable for input to PSHUFLW.
Nate Begeman5a5ca152009-04-29 05:20:52 +00002283static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, MVT VT) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002284 if (VT != MVT::v8i16)
Evan Cheng506d3df2006-03-29 23:07:14 +00002285 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002286
Rafael Espindola15684b22009-04-24 12:40:33 +00002287 // Upper quadword copied in order.
Nate Begeman9008ca62009-04-27 18:41:29 +00002288 for (int i = 4; i != 8; ++i)
2289 if (Mask[i] >= 0 && Mask[i] != i)
Rafael Espindola15684b22009-04-24 12:40:33 +00002290 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002291
Rafael Espindola15684b22009-04-24 12:40:33 +00002292 // Lower quadword shuffled.
Nate Begeman9008ca62009-04-27 18:41:29 +00002293 for (int i = 0; i != 4; ++i)
2294 if (Mask[i] >= 4)
Rafael Espindola15684b22009-04-24 12:40:33 +00002295 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002296
Rafael Espindola15684b22009-04-24 12:40:33 +00002297 return true;
Nate Begemanb706d292009-04-24 03:42:54 +00002298}
2299
Nate Begeman9008ca62009-04-27 18:41:29 +00002300bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2301 SmallVector<int, 8> M;
2302 N->getMask(M);
2303 return ::isPSHUFLWMask(M, N->getValueType(0));
2304}
2305
Evan Cheng14aed5e2006-03-24 01:18:28 +00002306/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2307/// specifies a shuffle of elements that is suitable for input to SHUFP*.
Nate Begeman5a5ca152009-04-29 05:20:52 +00002308static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002309 int NumElems = VT.getVectorNumElements();
2310 if (NumElems != 2 && NumElems != 4)
2311 return false;
2312
2313 int Half = NumElems / 2;
2314 for (int i = 0; i < Half; ++i)
2315 if (!isUndefOrInRange(Mask[i], 0, NumElems))
Evan Cheng39623da2006-04-20 08:58:49 +00002316 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002317 for (int i = Half; i < NumElems; ++i)
2318 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
Evan Cheng39623da2006-04-20 08:58:49 +00002319 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002320
Evan Cheng14aed5e2006-03-24 01:18:28 +00002321 return true;
2322}
2323
Nate Begeman9008ca62009-04-27 18:41:29 +00002324bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2325 SmallVector<int, 8> M;
2326 N->getMask(M);
2327 return ::isSHUFPMask(M, N->getValueType(0));
Evan Cheng39623da2006-04-20 08:58:49 +00002328}
2329
Evan Cheng213d2cf2007-05-17 18:45:50 +00002330/// isCommutedSHUFP - Returns true if the shuffle mask is exactly
Evan Cheng39623da2006-04-20 08:58:49 +00002331/// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2332/// half elements to come from vector 1 (which would equal the dest.) and
2333/// the upper half to come from vector 2.
Nate Begeman5a5ca152009-04-29 05:20:52 +00002334static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002335 int NumElems = VT.getVectorNumElements();
2336
2337 if (NumElems != 2 && NumElems != 4)
2338 return false;
2339
2340 int Half = NumElems / 2;
2341 for (int i = 0; i < Half; ++i)
2342 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
Evan Cheng39623da2006-04-20 08:58:49 +00002343 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002344 for (int i = Half; i < NumElems; ++i)
2345 if (!isUndefOrInRange(Mask[i], 0, NumElems))
Evan Cheng39623da2006-04-20 08:58:49 +00002346 return false;
2347 return true;
2348}
2349
Nate Begeman9008ca62009-04-27 18:41:29 +00002350static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2351 SmallVector<int, 8> M;
2352 N->getMask(M);
2353 return isCommutedSHUFPMask(M, N->getValueType(0));
Evan Cheng39623da2006-04-20 08:58:49 +00002354}
2355
Evan Cheng2c0dbd02006-03-24 02:58:06 +00002356/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2357/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
Nate Begeman9008ca62009-04-27 18:41:29 +00002358bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2359 if (N->getValueType(0).getVectorNumElements() != 4)
Evan Cheng2c0dbd02006-03-24 02:58:06 +00002360 return false;
2361
Evan Cheng2064a2b2006-03-28 06:50:32 +00002362 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
Nate Begeman9008ca62009-04-27 18:41:29 +00002363 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2364 isUndefOrEqual(N->getMaskElt(1), 7) &&
2365 isUndefOrEqual(N->getMaskElt(2), 2) &&
2366 isUndefOrEqual(N->getMaskElt(3), 3);
Evan Cheng6e56e2c2006-11-07 22:14:24 +00002367}
2368
Evan Cheng5ced1d82006-04-06 23:23:56 +00002369/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2370/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
Nate Begeman9008ca62009-04-27 18:41:29 +00002371bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2372 unsigned NumElems = N->getValueType(0).getVectorNumElements();
Evan Cheng5ced1d82006-04-06 23:23:56 +00002373
Evan Cheng5ced1d82006-04-06 23:23:56 +00002374 if (NumElems != 2 && NumElems != 4)
2375 return false;
2376
Evan Chengc5cdff22006-04-07 21:53:05 +00002377 for (unsigned i = 0; i < NumElems/2; ++i)
Nate Begeman9008ca62009-04-27 18:41:29 +00002378 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
Evan Chengc5cdff22006-04-07 21:53:05 +00002379 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002380
Evan Chengc5cdff22006-04-07 21:53:05 +00002381 for (unsigned i = NumElems/2; i < NumElems; ++i)
Nate Begeman9008ca62009-04-27 18:41:29 +00002382 if (!isUndefOrEqual(N->getMaskElt(i), i))
Evan Chengc5cdff22006-04-07 21:53:05 +00002383 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002384
2385 return true;
2386}
2387
2388/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
Evan Cheng533a0aa2006-04-19 20:35:22 +00002389/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2390/// and MOVLHPS.
Nate Begeman9008ca62009-04-27 18:41:29 +00002391bool X86::isMOVHPMask(ShuffleVectorSDNode *N) {
2392 unsigned NumElems = N->getValueType(0).getVectorNumElements();
Evan Cheng5ced1d82006-04-06 23:23:56 +00002393
Evan Cheng5ced1d82006-04-06 23:23:56 +00002394 if (NumElems != 2 && NumElems != 4)
2395 return false;
2396
Evan Chengc5cdff22006-04-07 21:53:05 +00002397 for (unsigned i = 0; i < NumElems/2; ++i)
Nate Begeman9008ca62009-04-27 18:41:29 +00002398 if (!isUndefOrEqual(N->getMaskElt(i), i))
Evan Chengc5cdff22006-04-07 21:53:05 +00002399 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002400
Nate Begeman9008ca62009-04-27 18:41:29 +00002401 for (unsigned i = 0; i < NumElems/2; ++i)
2402 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
Evan Chengc5cdff22006-04-07 21:53:05 +00002403 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002404
2405 return true;
2406}
2407
Nate Begeman9008ca62009-04-27 18:41:29 +00002408/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2409/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2410/// <2, 3, 2, 3>
2411bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2412 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2413
2414 if (NumElems != 4)
2415 return false;
2416
2417 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2418 isUndefOrEqual(N->getMaskElt(1), 3) &&
2419 isUndefOrEqual(N->getMaskElt(2), 2) &&
2420 isUndefOrEqual(N->getMaskElt(3), 3);
2421}
2422
Evan Cheng0038e592006-03-28 00:39:58 +00002423/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2424/// specifies a shuffle of elements that is suitable for input to UNPCKL.
Nate Begeman5a5ca152009-04-29 05:20:52 +00002425static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, MVT VT,
Rafael Espindola15684b22009-04-24 12:40:33 +00002426 bool V2IsSplat = false) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002427 int NumElts = VT.getVectorNumElements();
Chris Lattner5a88b832007-02-25 07:10:00 +00002428 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
Evan Cheng0038e592006-03-28 00:39:58 +00002429 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002430
2431 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2432 int BitI = Mask[i];
2433 int BitI1 = Mask[i+1];
Evan Chengc5cdff22006-04-07 21:53:05 +00002434 if (!isUndefOrEqual(BitI, j))
2435 return false;
Evan Cheng39623da2006-04-20 08:58:49 +00002436 if (V2IsSplat) {
Mon P Wang7bcaefa2009-02-04 01:16:59 +00002437 if (!isUndefOrEqual(BitI1, NumElts))
Evan Cheng39623da2006-04-20 08:58:49 +00002438 return false;
2439 } else {
Chris Lattner5a88b832007-02-25 07:10:00 +00002440 if (!isUndefOrEqual(BitI1, j + NumElts))
Evan Cheng39623da2006-04-20 08:58:49 +00002441 return false;
2442 }
Evan Cheng0038e592006-03-28 00:39:58 +00002443 }
Evan Cheng0038e592006-03-28 00:39:58 +00002444 return true;
2445}
2446
Nate Begeman9008ca62009-04-27 18:41:29 +00002447bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2448 SmallVector<int, 8> M;
2449 N->getMask(M);
2450 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
Evan Cheng39623da2006-04-20 08:58:49 +00002451}
2452
Evan Cheng4fcb9222006-03-28 02:43:26 +00002453/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2454/// specifies a shuffle of elements that is suitable for input to UNPCKH.
Nate Begeman5a5ca152009-04-29 05:20:52 +00002455static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, MVT VT,
Rafael Espindola15684b22009-04-24 12:40:33 +00002456 bool V2IsSplat = false) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002457 int NumElts = VT.getVectorNumElements();
Chris Lattner5a88b832007-02-25 07:10:00 +00002458 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
Evan Cheng4fcb9222006-03-28 02:43:26 +00002459 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002460
2461 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2462 int BitI = Mask[i];
2463 int BitI1 = Mask[i+1];
Chris Lattner5a88b832007-02-25 07:10:00 +00002464 if (!isUndefOrEqual(BitI, j + NumElts/2))
Evan Chengc5cdff22006-04-07 21:53:05 +00002465 return false;
Evan Cheng39623da2006-04-20 08:58:49 +00002466 if (V2IsSplat) {
Chris Lattner5a88b832007-02-25 07:10:00 +00002467 if (isUndefOrEqual(BitI1, NumElts))
Evan Cheng39623da2006-04-20 08:58:49 +00002468 return false;
2469 } else {
Chris Lattner5a88b832007-02-25 07:10:00 +00002470 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
Evan Cheng39623da2006-04-20 08:58:49 +00002471 return false;
2472 }
Evan Cheng4fcb9222006-03-28 02:43:26 +00002473 }
Evan Cheng4fcb9222006-03-28 02:43:26 +00002474 return true;
2475}
2476
Nate Begeman9008ca62009-04-27 18:41:29 +00002477bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2478 SmallVector<int, 8> M;
2479 N->getMask(M);
2480 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
Evan Cheng39623da2006-04-20 08:58:49 +00002481}
2482
Evan Cheng1d5a8cc2006-04-05 07:20:06 +00002483/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2484/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2485/// <0, 0, 1, 1>
Nate Begeman5a5ca152009-04-29 05:20:52 +00002486static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002487 int NumElems = VT.getVectorNumElements();
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00002488 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
Evan Cheng1d5a8cc2006-04-05 07:20:06 +00002489 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002490
2491 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2492 int BitI = Mask[i];
2493 int BitI1 = Mask[i+1];
Evan Chengc5cdff22006-04-07 21:53:05 +00002494 if (!isUndefOrEqual(BitI, j))
2495 return false;
2496 if (!isUndefOrEqual(BitI1, j))
2497 return false;
Evan Cheng1d5a8cc2006-04-05 07:20:06 +00002498 }
Rafael Espindola15684b22009-04-24 12:40:33 +00002499 return true;
Nate Begemanb706d292009-04-24 03:42:54 +00002500}
2501
Nate Begeman9008ca62009-04-27 18:41:29 +00002502bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2503 SmallVector<int, 8> M;
2504 N->getMask(M);
2505 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2506}
2507
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00002508/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2509/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2510/// <2, 2, 3, 3>
Nate Begeman5a5ca152009-04-29 05:20:52 +00002511static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002512 int NumElems = VT.getVectorNumElements();
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00002513 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2514 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002515
2516 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2517 int BitI = Mask[i];
2518 int BitI1 = Mask[i+1];
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00002519 if (!isUndefOrEqual(BitI, j))
2520 return false;
2521 if (!isUndefOrEqual(BitI1, j))
2522 return false;
2523 }
Rafael Espindola15684b22009-04-24 12:40:33 +00002524 return true;
Nate Begemanb706d292009-04-24 03:42:54 +00002525}
2526
Nate Begeman9008ca62009-04-27 18:41:29 +00002527bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2528 SmallVector<int, 8> M;
2529 N->getMask(M);
2530 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2531}
2532
Evan Cheng017dcc62006-04-21 01:05:10 +00002533/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2534/// specifies a shuffle of elements that is suitable for input to MOVSS,
2535/// MOVSD, and MOVD, i.e. setting the lowest element.
Nate Begeman5a5ca152009-04-29 05:20:52 +00002536static bool isMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT) {
Eli Friedman10415532009-06-06 06:05:10 +00002537 if (VT.getVectorElementType().getSizeInBits() < 32)
Evan Chengd6d1cbd2006-04-11 00:19:04 +00002538 return false;
Eli Friedman10415532009-06-06 06:05:10 +00002539
2540 int NumElts = VT.getVectorNumElements();
Nate Begeman9008ca62009-04-27 18:41:29 +00002541
2542 if (!isUndefOrEqual(Mask[0], NumElts))
Evan Chengd6d1cbd2006-04-11 00:19:04 +00002543 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002544
2545 for (int i = 1; i < NumElts; ++i)
2546 if (!isUndefOrEqual(Mask[i], i))
Evan Chengd6d1cbd2006-04-11 00:19:04 +00002547 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002548
Evan Chengd6d1cbd2006-04-11 00:19:04 +00002549 return true;
2550}
Evan Cheng1d5a8cc2006-04-05 07:20:06 +00002551
Nate Begeman9008ca62009-04-27 18:41:29 +00002552bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2553 SmallVector<int, 8> M;
2554 N->getMask(M);
2555 return ::isMOVLMask(M, N->getValueType(0));
Evan Cheng39623da2006-04-20 08:58:49 +00002556}
2557
Evan Cheng017dcc62006-04-21 01:05:10 +00002558/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2559/// of what x86 movss want. X86 movs requires the lowest element to be lowest
Evan Cheng39623da2006-04-20 08:58:49 +00002560/// element of vector 2 and the other elements to come from vector 1 in order.
Nate Begeman5a5ca152009-04-29 05:20:52 +00002561static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT,
Nate Begeman9008ca62009-04-27 18:41:29 +00002562 bool V2IsSplat = false, bool V2IsUndef = false) {
2563 int NumOps = VT.getVectorNumElements();
Chris Lattner5a88b832007-02-25 07:10:00 +00002564 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
Evan Cheng39623da2006-04-20 08:58:49 +00002565 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002566
2567 if (!isUndefOrEqual(Mask[0], 0))
Evan Cheng39623da2006-04-20 08:58:49 +00002568 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002569
2570 for (int i = 1; i < NumOps; ++i)
2571 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2572 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2573 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
Evan Cheng8cf723d2006-09-08 01:50:06 +00002574 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002575
Evan Cheng39623da2006-04-20 08:58:49 +00002576 return true;
2577}
2578
Nate Begeman9008ca62009-04-27 18:41:29 +00002579static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
Evan Cheng8cf723d2006-09-08 01:50:06 +00002580 bool V2IsUndef = false) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002581 SmallVector<int, 8> M;
2582 N->getMask(M);
2583 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
Evan Cheng39623da2006-04-20 08:58:49 +00002584}
2585
Evan Chengd9539472006-04-14 21:59:03 +00002586/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2587/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
Nate Begeman9008ca62009-04-27 18:41:29 +00002588bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2589 if (N->getValueType(0).getVectorNumElements() != 4)
Evan Chengd9539472006-04-14 21:59:03 +00002590 return false;
2591
2592 // Expect 1, 1, 3, 3
Rafael Espindola15684b22009-04-24 12:40:33 +00002593 for (unsigned i = 0; i < 2; ++i) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002594 int Elt = N->getMaskElt(i);
2595 if (Elt >= 0 && Elt != 1)
2596 return false;
Rafael Espindola15684b22009-04-24 12:40:33 +00002597 }
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002598
2599 bool HasHi = false;
Evan Chengd9539472006-04-14 21:59:03 +00002600 for (unsigned i = 2; i < 4; ++i) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002601 int Elt = N->getMaskElt(i);
2602 if (Elt >= 0 && Elt != 3)
2603 return false;
2604 if (Elt == 3)
2605 HasHi = true;
Evan Chengd9539472006-04-14 21:59:03 +00002606 }
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002607 // Don't use movshdup if it can be done with a shufps.
Nate Begeman9008ca62009-04-27 18:41:29 +00002608 // FIXME: verify that matching u, u, 3, 3 is what we want.
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002609 return HasHi;
Evan Chengd9539472006-04-14 21:59:03 +00002610}
2611
2612/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2613/// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
Nate Begeman9008ca62009-04-27 18:41:29 +00002614bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2615 if (N->getValueType(0).getVectorNumElements() != 4)
Evan Chengd9539472006-04-14 21:59:03 +00002616 return false;
2617
2618 // Expect 0, 0, 2, 2
Nate Begeman9008ca62009-04-27 18:41:29 +00002619 for (unsigned i = 0; i < 2; ++i)
2620 if (N->getMaskElt(i) > 0)
2621 return false;
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002622
2623 bool HasHi = false;
Evan Chengd9539472006-04-14 21:59:03 +00002624 for (unsigned i = 2; i < 4; ++i) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002625 int Elt = N->getMaskElt(i);
2626 if (Elt >= 0 && Elt != 2)
2627 return false;
2628 if (Elt == 2)
2629 HasHi = true;
Evan Chengd9539472006-04-14 21:59:03 +00002630 }
Nate Begeman9008ca62009-04-27 18:41:29 +00002631 // Don't use movsldup if it can be done with a shufps.
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002632 return HasHi;
Evan Chengd9539472006-04-14 21:59:03 +00002633}
2634
Evan Cheng0b457f02008-09-25 20:50:48 +00002635/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2636/// specifies a shuffle of elements that is suitable for input to MOVDDUP.
Nate Begeman9008ca62009-04-27 18:41:29 +00002637bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2638 int e = N->getValueType(0).getVectorNumElements() / 2;
2639
2640 for (int i = 0; i < e; ++i)
2641 if (!isUndefOrEqual(N->getMaskElt(i), i))
Evan Cheng0b457f02008-09-25 20:50:48 +00002642 return false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002643 for (int i = 0; i < e; ++i)
2644 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
Evan Cheng0b457f02008-09-25 20:50:48 +00002645 return false;
2646 return true;
2647}
2648
Evan Cheng63d33002006-03-22 08:01:21 +00002649/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2650/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2651/// instructions.
2652unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002653 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2654 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
2655
Evan Chengb9df0ca2006-03-22 02:53:00 +00002656 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2657 unsigned Mask = 0;
Nate Begeman9008ca62009-04-27 18:41:29 +00002658 for (int i = 0; i < NumOperands; ++i) {
2659 int Val = SVOp->getMaskElt(NumOperands-i-1);
2660 if (Val < 0) Val = 0;
Evan Cheng14aed5e2006-03-24 01:18:28 +00002661 if (Val >= NumOperands) Val -= NumOperands;
Evan Cheng63d33002006-03-22 08:01:21 +00002662 Mask |= Val;
Evan Cheng36b27f32006-03-28 23:41:33 +00002663 if (i != NumOperands - 1)
2664 Mask <<= Shift;
2665 }
Evan Cheng63d33002006-03-22 08:01:21 +00002666 return Mask;
2667}
2668
Evan Cheng506d3df2006-03-29 23:07:14 +00002669/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2670/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2671/// instructions.
2672unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002673 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
Evan Cheng506d3df2006-03-29 23:07:14 +00002674 unsigned Mask = 0;
2675 // 8 nodes, but we only care about the last 4.
2676 for (unsigned i = 7; i >= 4; --i) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002677 int Val = SVOp->getMaskElt(i);
2678 if (Val >= 0)
Mon P Wang7bcaefa2009-02-04 01:16:59 +00002679 Mask |= (Val - 4);
Evan Cheng506d3df2006-03-29 23:07:14 +00002680 if (i != 4)
2681 Mask <<= 2;
2682 }
Evan Cheng506d3df2006-03-29 23:07:14 +00002683 return Mask;
2684}
2685
2686/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2687/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2688/// instructions.
2689unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002690 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
Evan Cheng506d3df2006-03-29 23:07:14 +00002691 unsigned Mask = 0;
2692 // 8 nodes, but we only care about the first 4.
2693 for (int i = 3; i >= 0; --i) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002694 int Val = SVOp->getMaskElt(i);
2695 if (Val >= 0)
2696 Mask |= Val;
Evan Cheng506d3df2006-03-29 23:07:14 +00002697 if (i != 0)
2698 Mask <<= 2;
2699 }
Evan Cheng506d3df2006-03-29 23:07:14 +00002700 return Mask;
2701}
2702
Nate Begeman9008ca62009-04-27 18:41:29 +00002703/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
2704/// their permute mask.
2705static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
2706 SelectionDAG &DAG) {
2707 MVT VT = SVOp->getValueType(0);
Nate Begeman5a5ca152009-04-29 05:20:52 +00002708 unsigned NumElems = VT.getVectorNumElements();
Nate Begeman9008ca62009-04-27 18:41:29 +00002709 SmallVector<int, 8> MaskVec;
2710
Nate Begeman5a5ca152009-04-29 05:20:52 +00002711 for (unsigned i = 0; i != NumElems; ++i) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002712 int idx = SVOp->getMaskElt(i);
2713 if (idx < 0)
2714 MaskVec.push_back(idx);
Nate Begeman5a5ca152009-04-29 05:20:52 +00002715 else if (idx < (int)NumElems)
Nate Begeman9008ca62009-04-27 18:41:29 +00002716 MaskVec.push_back(idx + NumElems);
Evan Cheng5ced1d82006-04-06 23:23:56 +00002717 else
Nate Begeman9008ca62009-04-27 18:41:29 +00002718 MaskVec.push_back(idx - NumElems);
Evan Cheng5ced1d82006-04-06 23:23:56 +00002719 }
Nate Begeman9008ca62009-04-27 18:41:29 +00002720 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
2721 SVOp->getOperand(0), &MaskVec[0]);
Evan Cheng5ced1d82006-04-06 23:23:56 +00002722}
2723
Evan Cheng779ccea2007-12-07 21:30:01 +00002724/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2725/// the two vector operands have swapped position.
Nate Begeman9008ca62009-04-27 18:41:29 +00002726static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, MVT VT) {
Nate Begeman5a5ca152009-04-29 05:20:52 +00002727 unsigned NumElems = VT.getVectorNumElements();
2728 for (unsigned i = 0; i != NumElems; ++i) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002729 int idx = Mask[i];
2730 if (idx < 0)
Evan Cheng8a86c3f2007-12-07 08:07:39 +00002731 continue;
Nate Begeman5a5ca152009-04-29 05:20:52 +00002732 else if (idx < (int)NumElems)
Nate Begeman9008ca62009-04-27 18:41:29 +00002733 Mask[i] = idx + NumElems;
Evan Cheng8a86c3f2007-12-07 08:07:39 +00002734 else
Nate Begeman9008ca62009-04-27 18:41:29 +00002735 Mask[i] = idx - NumElems;
Evan Cheng8a86c3f2007-12-07 08:07:39 +00002736 }
Evan Cheng8a86c3f2007-12-07 08:07:39 +00002737}
2738
Evan Cheng533a0aa2006-04-19 20:35:22 +00002739/// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2740/// match movhlps. The lower half elements should come from upper half of
2741/// V1 (and in order), and the upper half elements should come from the upper
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00002742/// half of V2 (and in order).
Nate Begeman9008ca62009-04-27 18:41:29 +00002743static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
2744 if (Op->getValueType(0).getVectorNumElements() != 4)
Evan Cheng533a0aa2006-04-19 20:35:22 +00002745 return false;
2746 for (unsigned i = 0, e = 2; i != e; ++i)
Nate Begeman9008ca62009-04-27 18:41:29 +00002747 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
Evan Cheng533a0aa2006-04-19 20:35:22 +00002748 return false;
2749 for (unsigned i = 2; i != 4; ++i)
Nate Begeman9008ca62009-04-27 18:41:29 +00002750 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
Evan Cheng533a0aa2006-04-19 20:35:22 +00002751 return false;
2752 return true;
2753}
2754
Evan Cheng5ced1d82006-04-06 23:23:56 +00002755/// isScalarLoadToVector - Returns true if the node is a scalar load that
Evan Cheng7e2ff772008-05-08 00:57:18 +00002756/// is promoted to a vector. It also returns the LoadSDNode by reference if
2757/// required.
2758static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
Evan Cheng0b457f02008-09-25 20:50:48 +00002759 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2760 return false;
2761 N = N->getOperand(0).getNode();
2762 if (!ISD::isNON_EXTLoad(N))
2763 return false;
2764 if (LD)
2765 *LD = cast<LoadSDNode>(N);
2766 return true;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002767}
2768
Evan Cheng533a0aa2006-04-19 20:35:22 +00002769/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2770/// match movlp{s|d}. The lower half elements should come from lower half of
2771/// V1 (and in order), and the upper half elements should come from the upper
2772/// half of V2 (and in order). And since V1 will become the source of the
2773/// MOVLP, it must be either a vector load or a scalar load to vector.
Nate Begeman9008ca62009-04-27 18:41:29 +00002774static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
2775 ShuffleVectorSDNode *Op) {
Evan Cheng466685d2006-10-09 20:57:25 +00002776 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
Evan Cheng533a0aa2006-04-19 20:35:22 +00002777 return false;
Evan Cheng23425f52006-10-09 21:39:25 +00002778 // Is V2 is a vector load, don't do this transformation. We will try to use
2779 // load folding shufps op.
2780 if (ISD::isNON_EXTLoad(V2))
2781 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002782
Nate Begeman5a5ca152009-04-29 05:20:52 +00002783 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
Nate Begeman9008ca62009-04-27 18:41:29 +00002784
Evan Cheng533a0aa2006-04-19 20:35:22 +00002785 if (NumElems != 2 && NumElems != 4)
2786 return false;
Nate Begeman5a5ca152009-04-29 05:20:52 +00002787 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
Nate Begeman9008ca62009-04-27 18:41:29 +00002788 if (!isUndefOrEqual(Op->getMaskElt(i), i))
Evan Cheng533a0aa2006-04-19 20:35:22 +00002789 return false;
Nate Begeman5a5ca152009-04-29 05:20:52 +00002790 for (unsigned i = NumElems/2; i != NumElems; ++i)
Nate Begeman9008ca62009-04-27 18:41:29 +00002791 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
Evan Cheng533a0aa2006-04-19 20:35:22 +00002792 return false;
2793 return true;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002794}
2795
Evan Cheng39623da2006-04-20 08:58:49 +00002796/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2797/// all the same.
2798static bool isSplatVector(SDNode *N) {
2799 if (N->getOpcode() != ISD::BUILD_VECTOR)
2800 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002801
Dan Gohman475871a2008-07-27 21:46:04 +00002802 SDValue SplatValue = N->getOperand(0);
Evan Cheng39623da2006-04-20 08:58:49 +00002803 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2804 if (N->getOperand(i) != SplatValue)
Evan Cheng5ced1d82006-04-06 23:23:56 +00002805 return false;
2806 return true;
2807}
2808
Evan Cheng213d2cf2007-05-17 18:45:50 +00002809/// isZeroNode - Returns true if Elt is a constant zero or a floating point
2810/// constant +0.0.
Dan Gohman475871a2008-07-27 21:46:04 +00002811static inline bool isZeroNode(SDValue Elt) {
Evan Cheng213d2cf2007-05-17 18:45:50 +00002812 return ((isa<ConstantSDNode>(Elt) &&
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002813 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
Evan Cheng213d2cf2007-05-17 18:45:50 +00002814 (isa<ConstantFPSDNode>(Elt) &&
Dale Johanneseneaf08942007-08-31 04:03:46 +00002815 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
Evan Cheng213d2cf2007-05-17 18:45:50 +00002816}
2817
2818/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
Nate Begeman9008ca62009-04-27 18:41:29 +00002819/// to an zero vector.
Nate Begeman5a5ca152009-04-29 05:20:52 +00002820/// FIXME: move to dag combiner / method on ShuffleVectorSDNode
Nate Begeman9008ca62009-04-27 18:41:29 +00002821static bool isZeroShuffle(ShuffleVectorSDNode *N) {
Dan Gohman475871a2008-07-27 21:46:04 +00002822 SDValue V1 = N->getOperand(0);
2823 SDValue V2 = N->getOperand(1);
Nate Begeman5a5ca152009-04-29 05:20:52 +00002824 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2825 for (unsigned i = 0; i != NumElems; ++i) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002826 int Idx = N->getMaskElt(i);
Nate Begeman5a5ca152009-04-29 05:20:52 +00002827 if (Idx >= (int)NumElems) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002828 unsigned Opc = V2.getOpcode();
Rafael Espindola15684b22009-04-24 12:40:33 +00002829 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2830 continue;
Nate Begeman9008ca62009-04-27 18:41:29 +00002831 if (Opc != ISD::BUILD_VECTOR || !isZeroNode(V2.getOperand(Idx-NumElems)))
2832 return false;
2833 } else if (Idx >= 0) {
2834 unsigned Opc = V1.getOpcode();
2835 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2836 continue;
2837 if (Opc != ISD::BUILD_VECTOR || !isZeroNode(V1.getOperand(Idx)))
Chris Lattner8a594482007-11-25 00:24:49 +00002838 return false;
Evan Cheng213d2cf2007-05-17 18:45:50 +00002839 }
2840 }
2841 return true;
2842}
2843
2844/// getZeroVector - Returns a vector of specified type with all zero elements.
2845///
Dale Johannesenace16102009-02-03 19:33:06 +00002846static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG,
2847 DebugLoc dl) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00002848 assert(VT.isVector() && "Expected a vector type");
Scott Michelfdc40a02009-02-17 22:15:04 +00002849
Chris Lattner8a594482007-11-25 00:24:49 +00002850 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2851 // type. This ensures they get CSE'd.
Dan Gohman475871a2008-07-27 21:46:04 +00002852 SDValue Vec;
Duncan Sands83ec4b62008-06-06 12:08:01 +00002853 if (VT.getSizeInBits() == 64) { // MMX
Dan Gohman475871a2008-07-27 21:46:04 +00002854 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
Evan Chenga87008d2009-02-25 22:49:59 +00002855 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
Evan Chengf0df0312008-05-15 08:39:06 +00002856 } else if (HasSSE2) { // SSE2
Dan Gohman475871a2008-07-27 21:46:04 +00002857 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
Evan Chenga87008d2009-02-25 22:49:59 +00002858 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
Evan Chengf0df0312008-05-15 08:39:06 +00002859 } else { // SSE1
Dan Gohman475871a2008-07-27 21:46:04 +00002860 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
Evan Chenga87008d2009-02-25 22:49:59 +00002861 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
Evan Chengf0df0312008-05-15 08:39:06 +00002862 }
Dale Johannesenace16102009-02-03 19:33:06 +00002863 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
Evan Cheng213d2cf2007-05-17 18:45:50 +00002864}
2865
Chris Lattner8a594482007-11-25 00:24:49 +00002866/// getOnesVector - Returns a vector of specified type with all bits set.
2867///
Dale Johannesenace16102009-02-03 19:33:06 +00002868static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00002869 assert(VT.isVector() && "Expected a vector type");
Scott Michelfdc40a02009-02-17 22:15:04 +00002870
Chris Lattner8a594482007-11-25 00:24:49 +00002871 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2872 // type. This ensures they get CSE'd.
Dan Gohman475871a2008-07-27 21:46:04 +00002873 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2874 SDValue Vec;
Duncan Sands83ec4b62008-06-06 12:08:01 +00002875 if (VT.getSizeInBits() == 64) // MMX
Evan Chenga87008d2009-02-25 22:49:59 +00002876 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
Chris Lattner8a594482007-11-25 00:24:49 +00002877 else // SSE
Evan Chenga87008d2009-02-25 22:49:59 +00002878 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
Dale Johannesenace16102009-02-03 19:33:06 +00002879 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
Chris Lattner8a594482007-11-25 00:24:49 +00002880}
2881
2882
Evan Cheng39623da2006-04-20 08:58:49 +00002883/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2884/// that point to V2 points to its first element.
Nate Begeman9008ca62009-04-27 18:41:29 +00002885static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
2886 MVT VT = SVOp->getValueType(0);
Nate Begeman5a5ca152009-04-29 05:20:52 +00002887 unsigned NumElems = VT.getVectorNumElements();
Nate Begeman9008ca62009-04-27 18:41:29 +00002888
Evan Cheng39623da2006-04-20 08:58:49 +00002889 bool Changed = false;
Nate Begeman9008ca62009-04-27 18:41:29 +00002890 SmallVector<int, 8> MaskVec;
2891 SVOp->getMask(MaskVec);
2892
Nate Begeman5a5ca152009-04-29 05:20:52 +00002893 for (unsigned i = 0; i != NumElems; ++i) {
2894 if (MaskVec[i] > (int)NumElems) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002895 MaskVec[i] = NumElems;
2896 Changed = true;
Evan Cheng39623da2006-04-20 08:58:49 +00002897 }
Evan Cheng39623da2006-04-20 08:58:49 +00002898 }
Evan Cheng39623da2006-04-20 08:58:49 +00002899 if (Changed)
Nate Begeman9008ca62009-04-27 18:41:29 +00002900 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
2901 SVOp->getOperand(1), &MaskVec[0]);
2902 return SDValue(SVOp, 0);
Evan Cheng39623da2006-04-20 08:58:49 +00002903}
2904
Evan Cheng017dcc62006-04-21 01:05:10 +00002905/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2906/// operation of specified width.
Nate Begeman9008ca62009-04-27 18:41:29 +00002907static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
2908 SDValue V2) {
2909 unsigned NumElems = VT.getVectorNumElements();
2910 SmallVector<int, 8> Mask;
2911 Mask.push_back(NumElems);
Evan Cheng39623da2006-04-20 08:58:49 +00002912 for (unsigned i = 1; i != NumElems; ++i)
Nate Begeman9008ca62009-04-27 18:41:29 +00002913 Mask.push_back(i);
2914 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
Evan Cheng39623da2006-04-20 08:58:49 +00002915}
2916
Nate Begeman9008ca62009-04-27 18:41:29 +00002917/// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
2918static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
2919 SDValue V2) {
2920 unsigned NumElems = VT.getVectorNumElements();
2921 SmallVector<int, 8> Mask;
Evan Chengc575ca22006-04-17 20:43:08 +00002922 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002923 Mask.push_back(i);
2924 Mask.push_back(i + NumElems);
Evan Chengc575ca22006-04-17 20:43:08 +00002925 }
Nate Begeman9008ca62009-04-27 18:41:29 +00002926 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
Evan Chengc575ca22006-04-17 20:43:08 +00002927}
2928
Nate Begeman9008ca62009-04-27 18:41:29 +00002929/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
2930static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
2931 SDValue V2) {
2932 unsigned NumElems = VT.getVectorNumElements();
Evan Cheng39623da2006-04-20 08:58:49 +00002933 unsigned Half = NumElems/2;
Nate Begeman9008ca62009-04-27 18:41:29 +00002934 SmallVector<int, 8> Mask;
Evan Cheng39623da2006-04-20 08:58:49 +00002935 for (unsigned i = 0; i != Half; ++i) {
Nate Begeman9008ca62009-04-27 18:41:29 +00002936 Mask.push_back(i + Half);
2937 Mask.push_back(i + NumElems + Half);
Evan Cheng39623da2006-04-20 08:58:49 +00002938 }
Nate Begeman9008ca62009-04-27 18:41:29 +00002939 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
Chris Lattner62098042008-03-09 01:05:04 +00002940}
2941
Evan Cheng0c0f83f2008-04-05 00:30:36 +00002942/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
Nate Begeman9008ca62009-04-27 18:41:29 +00002943static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
2944 bool HasSSE2) {
2945 if (SV->getValueType(0).getVectorNumElements() <= 4)
2946 return SDValue(SV, 0);
2947
2948 MVT PVT = MVT::v4f32;
2949 MVT VT = SV->getValueType(0);
2950 DebugLoc dl = SV->getDebugLoc();
2951 SDValue V1 = SV->getOperand(0);
2952 int NumElems = VT.getVectorNumElements();
2953 int EltNo = SV->getSplatIndex();
Rafael Espindola15684b22009-04-24 12:40:33 +00002954
Nate Begeman9008ca62009-04-27 18:41:29 +00002955 // unpack elements to the correct location
2956 while (NumElems > 4) {
2957 if (EltNo < NumElems/2) {
2958 V1 = getUnpackl(DAG, dl, VT, V1, V1);
2959 } else {
2960 V1 = getUnpackh(DAG, dl, VT, V1, V1);
2961 EltNo -= NumElems/2;
2962 }
2963 NumElems >>= 1;
2964 }
2965
2966 // Perform the splat.
2967 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
Dale Johannesenace16102009-02-03 19:33:06 +00002968 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
Nate Begeman9008ca62009-04-27 18:41:29 +00002969 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
2970 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
Evan Chengc575ca22006-04-17 20:43:08 +00002971}
2972
Evan Chengba05f722006-04-21 23:03:30 +00002973/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
Chris Lattner8a594482007-11-25 00:24:49 +00002974/// vector of zero or undef vector. This produces a shuffle where the low
2975/// element of V2 is swizzled into the zero/undef vector, landing at element
2976/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
Dan Gohman475871a2008-07-27 21:46:04 +00002977static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
Evan Chengf0df0312008-05-15 08:39:06 +00002978 bool isZero, bool HasSSE2,
2979 SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00002980 MVT VT = V2.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +00002981 SDValue V1 = isZero
Nate Begeman9008ca62009-04-27 18:41:29 +00002982 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
2983 unsigned NumElems = VT.getVectorNumElements();
2984 SmallVector<int, 16> MaskVec;
Chris Lattner8a594482007-11-25 00:24:49 +00002985 for (unsigned i = 0; i != NumElems; ++i)
Nate Begeman9008ca62009-04-27 18:41:29 +00002986 // If this is the insertion idx, put the low elt of V2 here.
2987 MaskVec.push_back(i == Idx ? NumElems : i);
2988 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
Evan Cheng017dcc62006-04-21 01:05:10 +00002989}
2990
Evan Chengf26ffe92008-05-29 08:22:04 +00002991/// getNumOfConsecutiveZeros - Return the number of elements in a result of
2992/// a shuffle that is zero.
2993static
Nate Begeman9008ca62009-04-27 18:41:29 +00002994unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
2995 bool Low, SelectionDAG &DAG) {
Evan Chengf26ffe92008-05-29 08:22:04 +00002996 unsigned NumZeros = 0;
Nate Begeman9008ca62009-04-27 18:41:29 +00002997 for (int i = 0; i < NumElems; ++i) {
Evan Chengab262272008-06-25 20:52:59 +00002998 unsigned Index = Low ? i : NumElems-i-1;
Nate Begeman9008ca62009-04-27 18:41:29 +00002999 int Idx = SVOp->getMaskElt(Index);
3000 if (Idx < 0) {
Evan Chengf26ffe92008-05-29 08:22:04 +00003001 ++NumZeros;
3002 continue;
3003 }
Nate Begeman9008ca62009-04-27 18:41:29 +00003004 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
Gabor Greifba36cb52008-08-28 21:40:38 +00003005 if (Elt.getNode() && isZeroNode(Elt))
Evan Chengf26ffe92008-05-29 08:22:04 +00003006 ++NumZeros;
3007 else
3008 break;
3009 }
3010 return NumZeros;
3011}
3012
3013/// isVectorShift - Returns true if the shuffle can be implemented as a
3014/// logical left or right shift of a vector.
Nate Begeman9008ca62009-04-27 18:41:29 +00003015/// FIXME: split into pslldqi, psrldqi, palignr variants.
3016static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
Dan Gohman475871a2008-07-27 21:46:04 +00003017 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
Nate Begeman9008ca62009-04-27 18:41:29 +00003018 int NumElems = SVOp->getValueType(0).getVectorNumElements();
Evan Chengf26ffe92008-05-29 08:22:04 +00003019
3020 isLeft = true;
Nate Begeman9008ca62009-04-27 18:41:29 +00003021 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
Evan Chengf26ffe92008-05-29 08:22:04 +00003022 if (!NumZeros) {
3023 isLeft = false;
Nate Begeman9008ca62009-04-27 18:41:29 +00003024 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
Evan Chengf26ffe92008-05-29 08:22:04 +00003025 if (!NumZeros)
3026 return false;
3027 }
Evan Chengf26ffe92008-05-29 08:22:04 +00003028 bool SeenV1 = false;
3029 bool SeenV2 = false;
Nate Begeman9008ca62009-04-27 18:41:29 +00003030 for (int i = NumZeros; i < NumElems; ++i) {
3031 int Val = isLeft ? (i - NumZeros) : i;
3032 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3033 if (Idx < 0)
Evan Chengf26ffe92008-05-29 08:22:04 +00003034 continue;
Nate Begeman9008ca62009-04-27 18:41:29 +00003035 if (Idx < NumElems)
Evan Chengf26ffe92008-05-29 08:22:04 +00003036 SeenV1 = true;
3037 else {
Nate Begeman9008ca62009-04-27 18:41:29 +00003038 Idx -= NumElems;
Evan Chengf26ffe92008-05-29 08:22:04 +00003039 SeenV2 = true;
3040 }
Nate Begeman9008ca62009-04-27 18:41:29 +00003041 if (Idx != Val)
Evan Chengf26ffe92008-05-29 08:22:04 +00003042 return false;
3043 }
3044 if (SeenV1 && SeenV2)
3045 return false;
3046
Nate Begeman9008ca62009-04-27 18:41:29 +00003047 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
Evan Chengf26ffe92008-05-29 08:22:04 +00003048 ShAmt = NumZeros;
3049 return true;
3050}
3051
3052
Evan Chengc78d3b42006-04-24 18:01:45 +00003053/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3054///
Dan Gohman475871a2008-07-27 21:46:04 +00003055static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
Evan Chengc78d3b42006-04-24 18:01:45 +00003056 unsigned NumNonZero, unsigned NumZero,
Evan Cheng25ab6902006-09-08 06:48:29 +00003057 SelectionDAG &DAG, TargetLowering &TLI) {
Evan Chengc78d3b42006-04-24 18:01:45 +00003058 if (NumNonZero > 8)
Dan Gohman475871a2008-07-27 21:46:04 +00003059 return SDValue();
Evan Chengc78d3b42006-04-24 18:01:45 +00003060
Dale Johannesen6f38cb62009-02-07 19:59:05 +00003061 DebugLoc dl = Op.getDebugLoc();
Dan Gohman475871a2008-07-27 21:46:04 +00003062 SDValue V(0, 0);
Evan Chengc78d3b42006-04-24 18:01:45 +00003063 bool First = true;
3064 for (unsigned i = 0; i < 16; ++i) {
3065 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3066 if (ThisIsNonZero && First) {
3067 if (NumZero)
Dale Johannesenace16102009-02-03 19:33:06 +00003068 V = getZeroVector(MVT::v8i16, true, DAG, dl);
Evan Chengc78d3b42006-04-24 18:01:45 +00003069 else
Dale Johannesene8d72302009-02-06 23:05:02 +00003070 V = DAG.getUNDEF(MVT::v8i16);
Evan Chengc78d3b42006-04-24 18:01:45 +00003071 First = false;
3072 }
3073
3074 if ((i & 1) != 0) {
Dan Gohman475871a2008-07-27 21:46:04 +00003075 SDValue ThisElt(0, 0), LastElt(0, 0);
Evan Chengc78d3b42006-04-24 18:01:45 +00003076 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3077 if (LastIsNonZero) {
Scott Michelfdc40a02009-02-17 22:15:04 +00003078 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
Dale Johannesenace16102009-02-03 19:33:06 +00003079 MVT::i16, Op.getOperand(i-1));
Evan Chengc78d3b42006-04-24 18:01:45 +00003080 }
3081 if (ThisIsNonZero) {
Dale Johannesenace16102009-02-03 19:33:06 +00003082 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3083 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
Evan Chengc78d3b42006-04-24 18:01:45 +00003084 ThisElt, DAG.getConstant(8, MVT::i8));
3085 if (LastIsNonZero)
Dale Johannesenace16102009-02-03 19:33:06 +00003086 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
Evan Chengc78d3b42006-04-24 18:01:45 +00003087 } else
3088 ThisElt = LastElt;
3089
Gabor Greifba36cb52008-08-28 21:40:38 +00003090 if (ThisElt.getNode())
Dale Johannesenace16102009-02-03 19:33:06 +00003091 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
Chris Lattner0bd48932008-01-17 07:00:52 +00003092 DAG.getIntPtrConstant(i/2));
Evan Chengc78d3b42006-04-24 18:01:45 +00003093 }
3094 }
3095
Dale Johannesenace16102009-02-03 19:33:06 +00003096 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
Evan Chengc78d3b42006-04-24 18:01:45 +00003097}
3098
Bill Wendlinga348c562007-03-22 18:42:45 +00003099/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
Evan Chengc78d3b42006-04-24 18:01:45 +00003100///
Dan Gohman475871a2008-07-27 21:46:04 +00003101static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
Evan Chengc78d3b42006-04-24 18:01:45 +00003102 unsigned NumNonZero, unsigned NumZero,
Evan Cheng25ab6902006-09-08 06:48:29 +00003103 SelectionDAG &DAG, TargetLowering &TLI) {
Evan Chengc78d3b42006-04-24 18:01:45 +00003104 if (NumNonZero > 4)
Dan Gohman475871a2008-07-27 21:46:04 +00003105 return SDValue();
Evan Chengc78d3b42006-04-24 18:01:45 +00003106
Dale Johannesen6f38cb62009-02-07 19:59:05 +00003107 DebugLoc dl = Op.getDebugLoc();
Dan Gohman475871a2008-07-27 21:46:04 +00003108 SDValue V(0, 0);
Evan Chengc78d3b42006-04-24 18:01:45 +00003109 bool First = true;
3110 for (unsigned i = 0; i < 8; ++i) {
3111 bool isNonZero = (NonZeros & (1 << i)) != 0;
3112 if (isNonZero) {
3113 if (First) {
3114 if (NumZero)
Dale Johannesenace16102009-02-03 19:33:06 +00003115 V = getZeroVector(MVT::v8i16, true, DAG, dl);
Evan Chengc78d3b42006-04-24 18:01:45 +00003116 else
Dale Johannesene8d72302009-02-06 23:05:02 +00003117 V = DAG.getUNDEF(MVT::v8i16);
Evan Chengc78d3b42006-04-24 18:01:45 +00003118 First = false;
3119 }
Scott Michelfdc40a02009-02-17 22:15:04 +00003120 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
Dale Johannesenace16102009-02-03 19:33:06 +00003121 MVT::v8i16, V, Op.getOperand(i),
Chris Lattner0bd48932008-01-17 07:00:52 +00003122 DAG.getIntPtrConstant(i));
Evan Chengc78d3b42006-04-24 18:01:45 +00003123 }
3124 }
3125
3126 return V;
3127}
3128
Evan Chengf26ffe92008-05-29 08:22:04 +00003129/// getVShift - Return a vector logical shift node.
3130///
Dan Gohman475871a2008-07-27 21:46:04 +00003131static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
Nate Begeman9008ca62009-04-27 18:41:29 +00003132 unsigned NumBits, SelectionDAG &DAG,
3133 const TargetLowering &TLI, DebugLoc dl) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00003134 bool isMMX = VT.getSizeInBits() == 64;
3135 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
Evan Chengf26ffe92008-05-29 08:22:04 +00003136 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
Dale Johannesenace16102009-02-03 19:33:06 +00003137 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3138 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3139 DAG.getNode(Opc, dl, ShVT, SrcOp,
Gabor Greif327ef032008-08-28 23:19:51 +00003140 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
Evan Chengf26ffe92008-05-29 08:22:04 +00003141}
3142
Dan Gohman475871a2008-07-27 21:46:04 +00003143SDValue
3144X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
Dale Johannesen6f38cb62009-02-07 19:59:05 +00003145 DebugLoc dl = Op.getDebugLoc();
Chris Lattner8a594482007-11-25 00:24:49 +00003146 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
Gabor Greif327ef032008-08-28 23:19:51 +00003147 if (ISD::isBuildVectorAllZeros(Op.getNode())
3148 || ISD::isBuildVectorAllOnes(Op.getNode())) {
Chris Lattner8a594482007-11-25 00:24:49 +00003149 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3150 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3151 // eliminated on x86-32 hosts.
3152 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3153 return Op;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003154
Gabor Greifba36cb52008-08-28 21:40:38 +00003155 if (ISD::isBuildVectorAllOnes(Op.getNode()))
Dale Johannesenace16102009-02-03 19:33:06 +00003156 return getOnesVector(Op.getValueType(), DAG, dl);
3157 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
Chris Lattner8a594482007-11-25 00:24:49 +00003158 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00003159
Duncan Sands83ec4b62008-06-06 12:08:01 +00003160 MVT VT = Op.getValueType();
3161 MVT EVT = VT.getVectorElementType();
3162 unsigned EVTBits = EVT.getSizeInBits();
Evan Cheng0db9fe62006-04-25 20:13:52 +00003163
3164 unsigned NumElems = Op.getNumOperands();
3165 unsigned NumZero = 0;
3166 unsigned NumNonZero = 0;
3167 unsigned NonZeros = 0;
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003168 bool IsAllConstants = true;
Dan Gohman475871a2008-07-27 21:46:04 +00003169 SmallSet<SDValue, 8> Values;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003170 for (unsigned i = 0; i < NumElems; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00003171 SDValue Elt = Op.getOperand(i);
Evan Chengdb2d5242007-12-12 06:45:40 +00003172 if (Elt.getOpcode() == ISD::UNDEF)
3173 continue;
3174 Values.insert(Elt);
3175 if (Elt.getOpcode() != ISD::Constant &&
3176 Elt.getOpcode() != ISD::ConstantFP)
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003177 IsAllConstants = false;
Evan Chengdb2d5242007-12-12 06:45:40 +00003178 if (isZeroNode(Elt))
3179 NumZero++;
3180 else {
3181 NonZeros |= (1 << i);
3182 NumNonZero++;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003183 }
3184 }
3185
Dan Gohman7f321562007-06-25 16:23:39 +00003186 if (NumNonZero == 0) {
Chris Lattner8a594482007-11-25 00:24:49 +00003187 // All undef vector. Return an UNDEF. All zero vectors were handled above.
Dale Johannesene8d72302009-02-06 23:05:02 +00003188 return DAG.getUNDEF(VT);
Dan Gohman7f321562007-06-25 16:23:39 +00003189 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00003190
Chris Lattner67f453a2008-03-09 05:42:06 +00003191 // Special case for single non-zero, non-undef, element.
Eli Friedman10415532009-06-06 06:05:10 +00003192 if (NumNonZero == 1) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00003193 unsigned Idx = CountTrailingZeros_32(NonZeros);
Dan Gohman475871a2008-07-27 21:46:04 +00003194 SDValue Item = Op.getOperand(Idx);
Scott Michelfdc40a02009-02-17 22:15:04 +00003195
Chris Lattner62098042008-03-09 01:05:04 +00003196 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3197 // the value are obviously zero, truncate the value to i32 and do the
3198 // insertion that way. Only do this if the value is non-constant or if the
3199 // value is a constant being inserted into element 0. It is cheaper to do
3200 // a constant pool load than it is to do a movd + shuffle.
3201 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3202 (!IsAllConstants || Idx == 0)) {
3203 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3204 // Handle MMX and SSE both.
Duncan Sands83ec4b62008-06-06 12:08:01 +00003205 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3206 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
Scott Michelfdc40a02009-02-17 22:15:04 +00003207
Chris Lattner62098042008-03-09 01:05:04 +00003208 // Truncate the value (which may itself be a constant) to i32, and
3209 // convert it to a vector with movd (S2V+shuffle to zero extend).
Dale Johannesenace16102009-02-03 19:33:06 +00003210 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3211 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
Evan Chengf0df0312008-05-15 08:39:06 +00003212 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3213 Subtarget->hasSSE2(), DAG);
Scott Michelfdc40a02009-02-17 22:15:04 +00003214
Chris Lattner62098042008-03-09 01:05:04 +00003215 // Now we have our 32-bit value zero extended in the low element of
3216 // a vector. If Idx != 0, swizzle it into place.
3217 if (Idx != 0) {
Nate Begeman9008ca62009-04-27 18:41:29 +00003218 SmallVector<int, 4> Mask;
3219 Mask.push_back(Idx);
3220 for (unsigned i = 1; i != VecElts; ++i)
3221 Mask.push_back(i);
3222 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3223 DAG.getUNDEF(Item.getValueType()),
3224 &Mask[0]);
Chris Lattner62098042008-03-09 01:05:04 +00003225 }
Dale Johannesenace16102009-02-03 19:33:06 +00003226 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
Chris Lattner62098042008-03-09 01:05:04 +00003227 }
3228 }
Scott Michelfdc40a02009-02-17 22:15:04 +00003229
Chris Lattner19f79692008-03-08 22:59:52 +00003230 // If we have a constant or non-constant insertion into the low element of
3231 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3232 // the rest of the elements. This will be matched as movd/movq/movss/movsd
Eli Friedman10415532009-06-06 06:05:10 +00003233 // depending on what the source datatype is.
3234 if (Idx == 0) {
3235 if (NumZero == 0) {
3236 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3237 } else if (EVT == MVT::i32 || EVT == MVT::f32 || EVT == MVT::f64 ||
3238 (EVT == MVT::i64 && Subtarget->is64Bit())) {
3239 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3240 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3241 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3242 DAG);
3243 } else if (EVT == MVT::i16 || EVT == MVT::i8) {
3244 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3245 MVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3246 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3247 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3248 Subtarget->hasSSE2(), DAG);
3249 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3250 }
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003251 }
Evan Chengf26ffe92008-05-29 08:22:04 +00003252
3253 // Is it a vector logical left shift?
3254 if (NumElems == 2 && Idx == 1 &&
3255 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00003256 unsigned NumBits = VT.getSizeInBits();
Evan Chengf26ffe92008-05-29 08:22:04 +00003257 return getVShift(true, VT,
Scott Michelfdc40a02009-02-17 22:15:04 +00003258 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
Dale Johannesenb300d2a2009-02-07 00:55:49 +00003259 VT, Op.getOperand(1)),
Dale Johannesenace16102009-02-03 19:33:06 +00003260 NumBits/2, DAG, *this, dl);
Evan Chengf26ffe92008-05-29 08:22:04 +00003261 }
Scott Michelfdc40a02009-02-17 22:15:04 +00003262
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003263 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
Dan Gohman475871a2008-07-27 21:46:04 +00003264 return SDValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00003265
Chris Lattner19f79692008-03-08 22:59:52 +00003266 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3267 // is a non-constant being inserted into an element other than the low one,
3268 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3269 // movd/movss) to move this into the low element, then shuffle it into
3270 // place.
Evan Cheng0db9fe62006-04-25 20:13:52 +00003271 if (EVTBits == 32) {
Dale Johannesenace16102009-02-03 19:33:06 +00003272 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
Scott Michelfdc40a02009-02-17 22:15:04 +00003273
Evan Cheng0db9fe62006-04-25 20:13:52 +00003274 // Turn it into a shuffle of zero and zero-extended scalar to vector.
Evan Chengf0df0312008-05-15 08:39:06 +00003275 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3276 Subtarget->hasSSE2(), DAG);
Nate Begeman9008ca62009-04-27 18:41:29 +00003277 SmallVector<int, 8> MaskVec;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003278 for (unsigned i = 0; i < NumElems; i++)
Nate Begeman9008ca62009-04-27 18:41:29 +00003279 MaskVec.push_back(i == Idx ? 0 : 1);
3280 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003281 }
3282 }
3283
Chris Lattner67f453a2008-03-09 05:42:06 +00003284 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3285 if (Values.size() == 1)
Dan Gohman475871a2008-07-27 21:46:04 +00003286 return SDValue();
Scott Michelfdc40a02009-02-17 22:15:04 +00003287
Dan Gohmana3941172007-07-24 22:55:08 +00003288 // A vector full of immediates; various special cases are already
3289 // handled, so this is best done with a single constant-pool load.
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003290 if (IsAllConstants)
Dan Gohman475871a2008-07-27 21:46:04 +00003291 return SDValue();
Dan Gohmana3941172007-07-24 22:55:08 +00003292
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00003293 // Let legalizer expand 2-wide build_vectors.
Evan Cheng7e2ff772008-05-08 00:57:18 +00003294 if (EVTBits == 64) {
3295 if (NumNonZero == 1) {
3296 // One half is zero or undef.
3297 unsigned Idx = CountTrailingZeros_32(NonZeros);
Dale Johannesenace16102009-02-03 19:33:06 +00003298 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
Evan Cheng7e2ff772008-05-08 00:57:18 +00003299 Op.getOperand(Idx));
Evan Chengf0df0312008-05-15 08:39:06 +00003300 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3301 Subtarget->hasSSE2(), DAG);
Evan Cheng7e2ff772008-05-08 00:57:18 +00003302 }
Dan Gohman475871a2008-07-27 21:46:04 +00003303 return SDValue();
Evan Cheng7e2ff772008-05-08 00:57:18 +00003304 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00003305
3306 // If element VT is < 32 bits, convert it to inserts into a zero vector.
Bill Wendling826f36f2007-03-28 00:57:11 +00003307 if (EVTBits == 8 && NumElems == 16) {
Dan Gohman475871a2008-07-27 21:46:04 +00003308 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
Evan Cheng25ab6902006-09-08 06:48:29 +00003309 *this);
Gabor Greifba36cb52008-08-28 21:40:38 +00003310 if (V.getNode()) return V;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003311 }
3312
Bill Wendling826f36f2007-03-28 00:57:11 +00003313 if (EVTBits == 16 && NumElems == 8) {
Dan Gohman475871a2008-07-27 21:46:04 +00003314 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
Evan Cheng25ab6902006-09-08 06:48:29 +00003315 *this);
Gabor Greifba36cb52008-08-28 21:40:38 +00003316 if (V.getNode()) return V;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003317 }
3318
3319 // If element VT is == 32 bits, turn it into a number of shuffles.
Dan Gohman475871a2008-07-27 21:46:04 +00003320 SmallVector<SDValue, 8> V;
Chris Lattner5a88b832007-02-25 07:10:00 +00003321 V.resize(NumElems);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003322 if (NumElems == 4 && NumZero > 0) {
3323 for (unsigned i = 0; i < 4; ++i) {
3324 bool isZero = !(NonZeros & (1 << i));
3325 if (isZero)
Dale Johannesenace16102009-02-03 19:33:06 +00003326 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003327 else
Dale Johannesenace16102009-02-03 19:33:06 +00003328 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
Evan Cheng0db9fe62006-04-25 20:13:52 +00003329 }
3330
3331 for (unsigned i = 0; i < 2; ++i) {
3332 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3333 default: break;
3334 case 0:
3335 V[i] = V[i*2]; // Must be a zero vector.
3336 break;
3337 case 1:
Nate Begeman9008ca62009-04-27 18:41:29 +00003338 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003339 break;
3340 case 2:
Nate Begeman9008ca62009-04-27 18:41:29 +00003341 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003342 break;
3343 case 3:
Nate Begeman9008ca62009-04-27 18:41:29 +00003344 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003345 break;
3346 }
3347 }
3348
Nate Begeman9008ca62009-04-27 18:41:29 +00003349 SmallVector<int, 8> MaskVec;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003350 bool Reverse = (NonZeros & 0x3) == 2;
3351 for (unsigned i = 0; i < 2; ++i)
Nate Begeman9008ca62009-04-27 18:41:29 +00003352 MaskVec.push_back(Reverse ? 1-i : i);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003353 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3354 for (unsigned i = 0; i < 2; ++i)
Nate Begeman9008ca62009-04-27 18:41:29 +00003355 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3356 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003357 }
3358
3359 if (Values.size() > 2) {
Nate Begeman9008ca62009-04-27 18:41:29 +00003360 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3361 // values to be inserted is equal to the number of elements, in which case
3362 // use the unpack code below in the hopes of matching the consecutive elts
3363 // load merge pattern for shuffles.
3364 // FIXME: We could probably just check that here directly.
3365 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3366 getSubtarget()->hasSSE41()) {
3367 V[0] = DAG.getUNDEF(VT);
3368 for (unsigned i = 0; i < NumElems; ++i)
3369 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3370 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3371 Op.getOperand(i), DAG.getIntPtrConstant(i));
3372 return V[0];
3373 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00003374 // Expand into a number of unpckl*.
3375 // e.g. for v4f32
3376 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3377 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3378 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
Evan Cheng0db9fe62006-04-25 20:13:52 +00003379 for (unsigned i = 0; i < NumElems; ++i)
Dale Johannesenace16102009-02-03 19:33:06 +00003380 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
Evan Cheng0db9fe62006-04-25 20:13:52 +00003381 NumElems >>= 1;
3382 while (NumElems != 0) {
3383 for (unsigned i = 0; i < NumElems; ++i)
Nate Begeman9008ca62009-04-27 18:41:29 +00003384 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003385 NumElems >>= 1;
3386 }
3387 return V[0];
3388 }
3389
Dan Gohman475871a2008-07-27 21:46:04 +00003390 return SDValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00003391}
3392
Nate Begemanb9a47b82009-02-23 08:49:38 +00003393// v8i16 shuffles - Prefer shuffles in the following order:
3394// 1. [all] pshuflw, pshufhw, optional move
3395// 2. [ssse3] 1 x pshufb
3396// 3. [ssse3] 2 x pshufb + 1 x por
3397// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003398static
Nate Begeman9008ca62009-04-27 18:41:29 +00003399SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3400 SelectionDAG &DAG, X86TargetLowering &TLI) {
3401 SDValue V1 = SVOp->getOperand(0);
3402 SDValue V2 = SVOp->getOperand(1);
3403 DebugLoc dl = SVOp->getDebugLoc();
Nate Begemanb9a47b82009-02-23 08:49:38 +00003404 SmallVector<int, 8> MaskVals;
Evan Cheng14b32e12007-12-11 01:46:18 +00003405
Nate Begemanb9a47b82009-02-23 08:49:38 +00003406 // Determine if more than 1 of the words in each of the low and high quadwords
3407 // of the result come from the same quadword of one of the two inputs. Undef
3408 // mask values count as coming from any quadword, for better codegen.
3409 SmallVector<unsigned, 4> LoQuad(4);
3410 SmallVector<unsigned, 4> HiQuad(4);
3411 BitVector InputQuads(4);
3412 for (unsigned i = 0; i < 8; ++i) {
3413 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
Nate Begeman9008ca62009-04-27 18:41:29 +00003414 int EltIdx = SVOp->getMaskElt(i);
Nate Begemanb9a47b82009-02-23 08:49:38 +00003415 MaskVals.push_back(EltIdx);
3416 if (EltIdx < 0) {
3417 ++Quad[0];
3418 ++Quad[1];
3419 ++Quad[2];
3420 ++Quad[3];
Evan Cheng14b32e12007-12-11 01:46:18 +00003421 continue;
Nate Begemanb9a47b82009-02-23 08:49:38 +00003422 }
3423 ++Quad[EltIdx / 4];
3424 InputQuads.set(EltIdx / 4);
Evan Cheng14b32e12007-12-11 01:46:18 +00003425 }
Bill Wendlinge85dc492008-08-21 22:35:37 +00003426
Nate Begemanb9a47b82009-02-23 08:49:38 +00003427 int BestLoQuad = -1;
Evan Cheng14b32e12007-12-11 01:46:18 +00003428 unsigned MaxQuad = 1;
3429 for (unsigned i = 0; i < 4; ++i) {
Nate Begemanb9a47b82009-02-23 08:49:38 +00003430 if (LoQuad[i] > MaxQuad) {
3431 BestLoQuad = i;
3432 MaxQuad = LoQuad[i];
Evan Cheng14b32e12007-12-11 01:46:18 +00003433 }
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003434 }
3435
Nate Begemanb9a47b82009-02-23 08:49:38 +00003436 int BestHiQuad = -1;
Evan Cheng14b32e12007-12-11 01:46:18 +00003437 MaxQuad = 1;
3438 for (unsigned i = 0; i < 4; ++i) {
Nate Begemanb9a47b82009-02-23 08:49:38 +00003439 if (HiQuad[i] > MaxQuad) {
3440 BestHiQuad = i;
3441 MaxQuad = HiQuad[i];
Evan Cheng14b32e12007-12-11 01:46:18 +00003442 }
3443 }
3444
Nate Begemanb9a47b82009-02-23 08:49:38 +00003445 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3446 // of the two input vectors, shuffle them into one input vector so only a
3447 // single pshufb instruction is necessary. If There are more than 2 input
3448 // quads, disable the next transformation since it does not help SSSE3.
3449 bool V1Used = InputQuads[0] || InputQuads[1];
3450 bool V2Used = InputQuads[2] || InputQuads[3];
3451 if (TLI.getSubtarget()->hasSSSE3()) {
3452 if (InputQuads.count() == 2 && V1Used && V2Used) {
3453 BestLoQuad = InputQuads.find_first();
3454 BestHiQuad = InputQuads.find_next(BestLoQuad);
3455 }
3456 if (InputQuads.count() > 2) {
3457 BestLoQuad = -1;
3458 BestHiQuad = -1;
3459 }
3460 }
Bill Wendlinge85dc492008-08-21 22:35:37 +00003461
Nate Begemanb9a47b82009-02-23 08:49:38 +00003462 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3463 // the shuffle mask. If a quad is scored as -1, that means that it contains
3464 // words from all 4 input quadwords.
3465 SDValue NewV;
3466 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
Nate Begeman9008ca62009-04-27 18:41:29 +00003467 SmallVector<int, 8> MaskV;
3468 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3469 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3470 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3471 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3472 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
Dale Johannesenace16102009-02-03 19:33:06 +00003473 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
Evan Cheng14b32e12007-12-11 01:46:18 +00003474
Nate Begemanb9a47b82009-02-23 08:49:38 +00003475 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3476 // source words for the shuffle, to aid later transformations.
3477 bool AllWordsInNewV = true;
Mon P Wang37b9a192009-03-11 06:35:11 +00003478 bool InOrder[2] = { true, true };
Evan Cheng14b32e12007-12-11 01:46:18 +00003479 for (unsigned i = 0; i != 8; ++i) {
Nate Begemanb9a47b82009-02-23 08:49:38 +00003480 int idx = MaskVals[i];
Mon P Wang37b9a192009-03-11 06:35:11 +00003481 if (idx != (int)i)
3482 InOrder[i/4] = false;
Nate Begemanb9a47b82009-02-23 08:49:38 +00003483 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
Evan Cheng14b32e12007-12-11 01:46:18 +00003484 continue;
Nate Begemanb9a47b82009-02-23 08:49:38 +00003485 AllWordsInNewV = false;
3486 break;
Evan Cheng14b32e12007-12-11 01:46:18 +00003487 }
Bill Wendlinge85dc492008-08-21 22:35:37 +00003488
Nate Begemanb9a47b82009-02-23 08:49:38 +00003489 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3490 if (AllWordsInNewV) {
3491 for (int i = 0; i != 8; ++i) {
3492 int idx = MaskVals[i];
3493 if (idx < 0)
Evan Cheng14b32e12007-12-11 01:46:18 +00003494 continue;
Nate Begemanb9a47b82009-02-23 08:49:38 +00003495 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3496 if ((idx != i) && idx < 4)
3497 pshufhw = false;
3498 if ((idx != i) && idx > 3)
3499 pshuflw = false;
Evan Cheng14b32e12007-12-11 01:46:18 +00003500 }
Nate Begemanb9a47b82009-02-23 08:49:38 +00003501 V1 = NewV;
3502 V2Used = false;
3503 BestLoQuad = 0;
3504 BestHiQuad = 1;
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003505 }
Evan Cheng14b32e12007-12-11 01:46:18 +00003506
Nate Begemanb9a47b82009-02-23 08:49:38 +00003507 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3508 // pshufhw, that's as cheap as it gets. Return the new shuffle.
Mon P Wang37b9a192009-03-11 06:35:11 +00003509 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
Nate Begeman9008ca62009-04-27 18:41:29 +00003510 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3511 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
Evan Cheng14b32e12007-12-11 01:46:18 +00003512 }
Evan Cheng14b32e12007-12-11 01:46:18 +00003513 }
Nate Begemanb9a47b82009-02-23 08:49:38 +00003514
3515 // If we have SSSE3, and all words of the result are from 1 input vector,
3516 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
3517 // is present, fall back to case 4.
3518 if (TLI.getSubtarget()->hasSSSE3()) {
3519 SmallVector<SDValue,16> pshufbMask;
3520
3521 // If we have elements from both input vectors, set the high bit of the
3522 // shuffle mask element to zero out elements that come from V2 in the V1
3523 // mask, and elements that come from V1 in the V2 mask, so that the two
3524 // results can be OR'd together.
3525 bool TwoInputs = V1Used && V2Used;
3526 for (unsigned i = 0; i != 8; ++i) {
3527 int EltIdx = MaskVals[i] * 2;
3528 if (TwoInputs && (EltIdx >= 16)) {
3529 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3530 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3531 continue;
3532 }
3533 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3534 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
3535 }
3536 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
3537 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
Evan Chenga87008d2009-02-25 22:49:59 +00003538 DAG.getNode(ISD::BUILD_VECTOR, dl,
3539 MVT::v16i8, &pshufbMask[0], 16));
Nate Begemanb9a47b82009-02-23 08:49:38 +00003540 if (!TwoInputs)
3541 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3542
3543 // Calculate the shuffle mask for the second input, shuffle it, and
3544 // OR it with the first shuffled input.
3545 pshufbMask.clear();
3546 for (unsigned i = 0; i != 8; ++i) {
3547 int EltIdx = MaskVals[i] * 2;
3548 if (EltIdx < 16) {
3549 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3550 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3551 continue;
3552 }
3553 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3554 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
3555 }
3556 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
3557 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
Evan Chenga87008d2009-02-25 22:49:59 +00003558 DAG.getNode(ISD::BUILD_VECTOR, dl,
3559 MVT::v16i8, &pshufbMask[0], 16));
Nate Begemanb9a47b82009-02-23 08:49:38 +00003560 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3561 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3562 }
3563
3564 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
3565 // and update MaskVals with new element order.
3566 BitVector InOrder(8);
3567 if (BestLoQuad >= 0) {
Nate Begeman9008ca62009-04-27 18:41:29 +00003568 SmallVector<int, 8> MaskV;
Nate Begemanb9a47b82009-02-23 08:49:38 +00003569 for (int i = 0; i != 4; ++i) {
3570 int idx = MaskVals[i];
3571 if (idx < 0) {
Nate Begeman9008ca62009-04-27 18:41:29 +00003572 MaskV.push_back(-1);
Nate Begemanb9a47b82009-02-23 08:49:38 +00003573 InOrder.set(i);
3574 } else if ((idx / 4) == BestLoQuad) {
Nate Begeman9008ca62009-04-27 18:41:29 +00003575 MaskV.push_back(idx & 3);
Nate Begemanb9a47b82009-02-23 08:49:38 +00003576 InOrder.set(i);
3577 } else {
Nate Begeman9008ca62009-04-27 18:41:29 +00003578 MaskV.push_back(-1);
Nate Begemanb9a47b82009-02-23 08:49:38 +00003579 }
3580 }
3581 for (unsigned i = 4; i != 8; ++i)
Nate Begeman9008ca62009-04-27 18:41:29 +00003582 MaskV.push_back(i);
3583 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3584 &MaskV[0]);
Nate Begemanb9a47b82009-02-23 08:49:38 +00003585 }
3586
3587 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
3588 // and update MaskVals with the new element order.
3589 if (BestHiQuad >= 0) {
Nate Begeman9008ca62009-04-27 18:41:29 +00003590 SmallVector<int, 8> MaskV;
Nate Begemanb9a47b82009-02-23 08:49:38 +00003591 for (unsigned i = 0; i != 4; ++i)
Nate Begeman9008ca62009-04-27 18:41:29 +00003592 MaskV.push_back(i);
Nate Begemanb9a47b82009-02-23 08:49:38 +00003593 for (unsigned i = 4; i != 8; ++i) {
3594 int idx = MaskVals[i];
3595 if (idx < 0) {
Nate Begeman9008ca62009-04-27 18:41:29 +00003596 MaskV.push_back(-1);
Nate Begemanb9a47b82009-02-23 08:49:38 +00003597 InOrder.set(i);
3598 } else if ((idx / 4) == BestHiQuad) {
Nate Begeman9008ca62009-04-27 18:41:29 +00003599 MaskV.push_back((idx & 3) + 4);
Nate Begemanb9a47b82009-02-23 08:49:38 +00003600 InOrder.set(i);
3601 } else {
Nate Begeman9008ca62009-04-27 18:41:29 +00003602 MaskV.push_back(-1);
Nate Begemanb9a47b82009-02-23 08:49:38 +00003603 }
3604 }
Nate Begeman9008ca62009-04-27 18:41:29 +00003605 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3606 &MaskV[0]);
Nate Begemanb9a47b82009-02-23 08:49:38 +00003607 }
3608
3609 // In case BestHi & BestLo were both -1, which means each quadword has a word
3610 // from each of the four input quadwords, calculate the InOrder bitvector now
3611 // before falling through to the insert/extract cleanup.
3612 if (BestLoQuad == -1 && BestHiQuad == -1) {
3613 NewV = V1;
3614 for (int i = 0; i != 8; ++i)
3615 if (MaskVals[i] < 0 || MaskVals[i] == i)
3616 InOrder.set(i);
3617 }
3618
3619 // The other elements are put in the right place using pextrw and pinsrw.
3620 for (unsigned i = 0; i != 8; ++i) {
3621 if (InOrder[i])
3622 continue;
3623 int EltIdx = MaskVals[i];
3624 if (EltIdx < 0)
3625 continue;
3626 SDValue ExtOp = (EltIdx < 8)
3627 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3628 DAG.getIntPtrConstant(EltIdx))
3629 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3630 DAG.getIntPtrConstant(EltIdx - 8));
3631 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3632 DAG.getIntPtrConstant(i));
3633 }
3634 return NewV;
3635}
3636
3637// v16i8 shuffles - Prefer shuffles in the following order:
3638// 1. [ssse3] 1 x pshufb
3639// 2. [ssse3] 2 x pshufb + 1 x por
3640// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
3641static
Nate Begeman9008ca62009-04-27 18:41:29 +00003642SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
3643 SelectionDAG &DAG, X86TargetLowering &TLI) {
3644 SDValue V1 = SVOp->getOperand(0);
3645 SDValue V2 = SVOp->getOperand(1);
3646 DebugLoc dl = SVOp->getDebugLoc();
Nate Begemanb9a47b82009-02-23 08:49:38 +00003647 SmallVector<int, 16> MaskVals;
Nate Begeman9008ca62009-04-27 18:41:29 +00003648 SVOp->getMask(MaskVals);
Nate Begemanb9a47b82009-02-23 08:49:38 +00003649
3650 // If we have SSSE3, case 1 is generated when all result bytes come from
3651 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
3652 // present, fall back to case 3.
3653 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
3654 bool V1Only = true;
3655 bool V2Only = true;
3656 for (unsigned i = 0; i < 16; ++i) {
Nate Begeman9008ca62009-04-27 18:41:29 +00003657 int EltIdx = MaskVals[i];
Nate Begemanb9a47b82009-02-23 08:49:38 +00003658 if (EltIdx < 0)
3659 continue;
3660 if (EltIdx < 16)
3661 V2Only = false;
3662 else
3663 V1Only = false;
3664 }
3665
3666 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
3667 if (TLI.getSubtarget()->hasSSSE3()) {
3668 SmallVector<SDValue,16> pshufbMask;
3669
3670 // If all result elements are from one input vector, then only translate
3671 // undef mask values to 0x80 (zero out result) in the pshufb mask.
3672 //
3673 // Otherwise, we have elements from both input vectors, and must zero out
3674 // elements that come from V2 in the first mask, and V1 in the second mask
3675 // so that we can OR them together.
3676 bool TwoInputs = !(V1Only || V2Only);
3677 for (unsigned i = 0; i != 16; ++i) {
3678 int EltIdx = MaskVals[i];
3679 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
3680 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3681 continue;
3682 }
3683 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3684 }
3685 // If all the elements are from V2, assign it to V1 and return after
3686 // building the first pshufb.
3687 if (V2Only)
3688 V1 = V2;
3689 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
Evan Chenga87008d2009-02-25 22:49:59 +00003690 DAG.getNode(ISD::BUILD_VECTOR, dl,
3691 MVT::v16i8, &pshufbMask[0], 16));
Nate Begemanb9a47b82009-02-23 08:49:38 +00003692 if (!TwoInputs)
3693 return V1;
3694
3695 // Calculate the shuffle mask for the second input, shuffle it, and
3696 // OR it with the first shuffled input.
3697 pshufbMask.clear();
3698 for (unsigned i = 0; i != 16; ++i) {
3699 int EltIdx = MaskVals[i];
3700 if (EltIdx < 16) {
3701 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3702 continue;
3703 }
3704 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3705 }
3706 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
Evan Chenga87008d2009-02-25 22:49:59 +00003707 DAG.getNode(ISD::BUILD_VECTOR, dl,
3708 MVT::v16i8, &pshufbMask[0], 16));
Nate Begemanb9a47b82009-02-23 08:49:38 +00003709 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3710 }
3711
3712 // No SSSE3 - Calculate in place words and then fix all out of place words
3713 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
3714 // the 16 different words that comprise the two doublequadword input vectors.
3715 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3716 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
3717 SDValue NewV = V2Only ? V2 : V1;
3718 for (int i = 0; i != 8; ++i) {
3719 int Elt0 = MaskVals[i*2];
3720 int Elt1 = MaskVals[i*2+1];
3721
3722 // This word of the result is all undef, skip it.
3723 if (Elt0 < 0 && Elt1 < 0)
3724 continue;
3725
3726 // This word of the result is already in the correct place, skip it.
3727 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
3728 continue;
3729 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
3730 continue;
3731
3732 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
3733 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
3734 SDValue InsElt;
Mon P Wang6b3ef692009-03-11 18:47:57 +00003735
3736 // If Elt0 and Elt1 are defined, are consecutive, and can be load
3737 // using a single extract together, load it and store it.
3738 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
3739 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3740 DAG.getIntPtrConstant(Elt1 / 2));
3741 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3742 DAG.getIntPtrConstant(i));
3743 continue;
3744 }
3745
Nate Begemanb9a47b82009-02-23 08:49:38 +00003746 // If Elt1 is defined, extract it from the appropriate source. If the
Mon P Wang6b3ef692009-03-11 18:47:57 +00003747 // source byte is not also odd, shift the extracted word left 8 bits
3748 // otherwise clear the bottom 8 bits if we need to do an or.
Nate Begemanb9a47b82009-02-23 08:49:38 +00003749 if (Elt1 >= 0) {
3750 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3751 DAG.getIntPtrConstant(Elt1 / 2));
3752 if ((Elt1 & 1) == 0)
3753 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
3754 DAG.getConstant(8, TLI.getShiftAmountTy()));
Mon P Wang6b3ef692009-03-11 18:47:57 +00003755 else if (Elt0 >= 0)
3756 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
3757 DAG.getConstant(0xFF00, MVT::i16));
Nate Begemanb9a47b82009-02-23 08:49:38 +00003758 }
3759 // If Elt0 is defined, extract it from the appropriate source. If the
3760 // source byte is not also even, shift the extracted word right 8 bits. If
3761 // Elt1 was also defined, OR the extracted values together before
3762 // inserting them in the result.
3763 if (Elt0 >= 0) {
3764 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
3765 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
3766 if ((Elt0 & 1) != 0)
3767 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
3768 DAG.getConstant(8, TLI.getShiftAmountTy()));
Mon P Wang6b3ef692009-03-11 18:47:57 +00003769 else if (Elt1 >= 0)
3770 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
3771 DAG.getConstant(0x00FF, MVT::i16));
Nate Begemanb9a47b82009-02-23 08:49:38 +00003772 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
3773 : InsElt0;
3774 }
3775 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3776 DAG.getIntPtrConstant(i));
3777 }
3778 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
Evan Cheng14b32e12007-12-11 01:46:18 +00003779}
3780
Evan Cheng7a831ce2007-12-15 03:00:47 +00003781/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3782/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3783/// done when every pair / quad of shuffle mask elements point to elements in
3784/// the right sequence. e.g.
Evan Cheng14b32e12007-12-11 01:46:18 +00003785/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3786static
Nate Begeman9008ca62009-04-27 18:41:29 +00003787SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
3788 SelectionDAG &DAG,
3789 TargetLowering &TLI, DebugLoc dl) {
3790 MVT VT = SVOp->getValueType(0);
3791 SDValue V1 = SVOp->getOperand(0);
3792 SDValue V2 = SVOp->getOperand(1);
3793 unsigned NumElems = VT.getVectorNumElements();
Evan Cheng7a831ce2007-12-15 03:00:47 +00003794 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
Duncan Sands83ec4b62008-06-06 12:08:01 +00003795 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
Duncan Sandsd038e042008-07-21 10:20:31 +00003796 MVT MaskEltVT = MaskVT.getVectorElementType();
Duncan Sands83ec4b62008-06-06 12:08:01 +00003797 MVT NewVT = MaskVT;
3798 switch (VT.getSimpleVT()) {
3799 default: assert(false && "Unexpected!");
Evan Cheng7a831ce2007-12-15 03:00:47 +00003800 case MVT::v4f32: NewVT = MVT::v2f64; break;
3801 case MVT::v4i32: NewVT = MVT::v2i64; break;
3802 case MVT::v8i16: NewVT = MVT::v4i32; break;
3803 case MVT::v16i8: NewVT = MVT::v4i32; break;
Evan Cheng7a831ce2007-12-15 03:00:47 +00003804 }
3805
Anton Korobeynikov7c1c2612008-02-20 11:22:39 +00003806 if (NewWidth == 2) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00003807 if (VT.isInteger())
Evan Cheng7a831ce2007-12-15 03:00:47 +00003808 NewVT = MVT::v2i64;
3809 else
3810 NewVT = MVT::v2f64;
Anton Korobeynikov7c1c2612008-02-20 11:22:39 +00003811 }
Nate Begeman9008ca62009-04-27 18:41:29 +00003812 int Scale = NumElems / NewWidth;
3813 SmallVector<int, 8> MaskVec;
Evan Cheng14b32e12007-12-11 01:46:18 +00003814 for (unsigned i = 0; i < NumElems; i += Scale) {
Nate Begeman9008ca62009-04-27 18:41:29 +00003815 int StartIdx = -1;
3816 for (int j = 0; j < Scale; ++j) {
3817 int EltIdx = SVOp->getMaskElt(i+j);
3818 if (EltIdx < 0)
Evan Cheng14b32e12007-12-11 01:46:18 +00003819 continue;
Nate Begeman9008ca62009-04-27 18:41:29 +00003820 if (StartIdx == -1)
Evan Cheng14b32e12007-12-11 01:46:18 +00003821 StartIdx = EltIdx - (EltIdx % Scale);
3822 if (EltIdx != StartIdx + j)
Dan Gohman475871a2008-07-27 21:46:04 +00003823 return SDValue();
Evan Cheng14b32e12007-12-11 01:46:18 +00003824 }
Nate Begeman9008ca62009-04-27 18:41:29 +00003825 if (StartIdx == -1)
3826 MaskVec.push_back(-1);
Evan Cheng14b32e12007-12-11 01:46:18 +00003827 else
Nate Begeman9008ca62009-04-27 18:41:29 +00003828 MaskVec.push_back(StartIdx / Scale);
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003829 }
3830
Dale Johannesenace16102009-02-03 19:33:06 +00003831 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
3832 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
Nate Begeman9008ca62009-04-27 18:41:29 +00003833 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003834}
3835
Evan Chengd880b972008-05-09 21:53:03 +00003836/// getVZextMovL - Return a zero-extending vector move low node.
Evan Cheng7e2ff772008-05-08 00:57:18 +00003837///
Dan Gohman475871a2008-07-27 21:46:04 +00003838static SDValue getVZextMovL(MVT VT, MVT OpVT,
Nate Begeman9008ca62009-04-27 18:41:29 +00003839 SDValue SrcOp, SelectionDAG &DAG,
3840 const X86Subtarget *Subtarget, DebugLoc dl) {
Evan Cheng7e2ff772008-05-08 00:57:18 +00003841 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3842 LoadSDNode *LD = NULL;
Gabor Greifba36cb52008-08-28 21:40:38 +00003843 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
Evan Cheng7e2ff772008-05-08 00:57:18 +00003844 LD = dyn_cast<LoadSDNode>(SrcOp);
3845 if (!LD) {
3846 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3847 // instead.
Duncan Sands83ec4b62008-06-06 12:08:01 +00003848 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
Evan Cheng7e2ff772008-05-08 00:57:18 +00003849 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3850 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3851 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3852 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3853 // PR2108
3854 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
Dale Johannesenace16102009-02-03 19:33:06 +00003855 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3856 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
3857 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3858 OpVT,
Gabor Greif327ef032008-08-28 23:19:51 +00003859 SrcOp.getOperand(0)
3860 .getOperand(0))));
Evan Cheng7e2ff772008-05-08 00:57:18 +00003861 }
3862 }
3863 }
3864
Dale Johannesenace16102009-02-03 19:33:06 +00003865 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3866 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
Scott Michelfdc40a02009-02-17 22:15:04 +00003867 DAG.getNode(ISD::BIT_CONVERT, dl,
Dale Johannesenace16102009-02-03 19:33:06 +00003868 OpVT, SrcOp)));
Evan Cheng7e2ff772008-05-08 00:57:18 +00003869}
3870
Evan Chengace3c172008-07-22 21:13:36 +00003871/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3872/// shuffles.
Dan Gohman475871a2008-07-27 21:46:04 +00003873static SDValue
Nate Begeman9008ca62009-04-27 18:41:29 +00003874LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3875 SDValue V1 = SVOp->getOperand(0);
3876 SDValue V2 = SVOp->getOperand(1);
3877 DebugLoc dl = SVOp->getDebugLoc();
3878 MVT VT = SVOp->getValueType(0);
3879
Evan Chengace3c172008-07-22 21:13:36 +00003880 SmallVector<std::pair<int, int>, 8> Locs;
Rafael Espindola833a9902008-08-28 18:32:53 +00003881 Locs.resize(4);
Nate Begeman9008ca62009-04-27 18:41:29 +00003882 SmallVector<int, 8> Mask1(4U, -1);
3883 SmallVector<int, 8> PermMask;
3884 SVOp->getMask(PermMask);
3885
Evan Chengace3c172008-07-22 21:13:36 +00003886 unsigned NumHi = 0;
3887 unsigned NumLo = 0;
Evan Chengace3c172008-07-22 21:13:36 +00003888 for (unsigned i = 0; i != 4; ++i) {
Nate Begeman9008ca62009-04-27 18:41:29 +00003889 int Idx = PermMask[i];
3890 if (Idx < 0) {
Evan Chengace3c172008-07-22 21:13:36 +00003891 Locs[i] = std::make_pair(-1, -1);
3892 } else {
Nate Begeman9008ca62009-04-27 18:41:29 +00003893 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
3894 if (Idx < 4) {
Evan Chengace3c172008-07-22 21:13:36 +00003895 Locs[i] = std::make_pair(0, NumLo);
Nate Begeman9008ca62009-04-27 18:41:29 +00003896 Mask1[NumLo] = Idx;
Evan Chengace3c172008-07-22 21:13:36 +00003897 NumLo++;
3898 } else {
3899 Locs[i] = std::make_pair(1, NumHi);
3900 if (2+NumHi < 4)
Nate Begeman9008ca62009-04-27 18:41:29 +00003901 Mask1[2+NumHi] = Idx;
Evan Chengace3c172008-07-22 21:13:36 +00003902 NumHi++;
3903 }
3904 }
3905 }
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003906
Evan Chengace3c172008-07-22 21:13:36 +00003907 if (NumLo <= 2 && NumHi <= 2) {
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003908 // If no more than two elements come from either vector. This can be
3909 // implemented with two shuffles. First shuffle gather the elements.
3910 // The second shuffle, which takes the first shuffle as both of its
3911 // vector operands, put the elements into the right order.
Nate Begeman9008ca62009-04-27 18:41:29 +00003912 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003913
Nate Begeman9008ca62009-04-27 18:41:29 +00003914 SmallVector<int, 8> Mask2(4U, -1);
3915
Evan Chengace3c172008-07-22 21:13:36 +00003916 for (unsigned i = 0; i != 4; ++i) {
3917 if (Locs[i].first == -1)
3918 continue;
3919 else {
3920 unsigned Idx = (i < 2) ? 0 : 4;
3921 Idx += Locs[i].first * 2 + Locs[i].second;
Nate Begeman9008ca62009-04-27 18:41:29 +00003922 Mask2[i] = Idx;
Evan Chengace3c172008-07-22 21:13:36 +00003923 }
3924 }
3925
Nate Begeman9008ca62009-04-27 18:41:29 +00003926 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003927 } else if (NumLo == 3 || NumHi == 3) {
3928 // Otherwise, we must have three elements from one vector, call it X, and
3929 // one element from the other, call it Y. First, use a shufps to build an
3930 // intermediate vector with the one element from Y and the element from X
3931 // that will be in the same half in the final destination (the indexes don't
3932 // matter). Then, use a shufps to build the final vector, taking the half
3933 // containing the element from Y from the intermediate, and the other half
3934 // from X.
3935 if (NumHi == 3) {
3936 // Normalize it so the 3 elements come from V1.
Nate Begeman9008ca62009-04-27 18:41:29 +00003937 CommuteVectorShuffleMask(PermMask, VT);
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003938 std::swap(V1, V2);
3939 }
3940
3941 // Find the element from V2.
3942 unsigned HiIndex;
3943 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
Nate Begeman9008ca62009-04-27 18:41:29 +00003944 int Val = PermMask[HiIndex];
3945 if (Val < 0)
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003946 continue;
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003947 if (Val >= 4)
3948 break;
3949 }
3950
Nate Begeman9008ca62009-04-27 18:41:29 +00003951 Mask1[0] = PermMask[HiIndex];
3952 Mask1[1] = -1;
3953 Mask1[2] = PermMask[HiIndex^1];
3954 Mask1[3] = -1;
3955 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003956
3957 if (HiIndex >= 2) {
Nate Begeman9008ca62009-04-27 18:41:29 +00003958 Mask1[0] = PermMask[0];
3959 Mask1[1] = PermMask[1];
3960 Mask1[2] = HiIndex & 1 ? 6 : 4;
3961 Mask1[3] = HiIndex & 1 ? 4 : 6;
3962 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003963 } else {
Nate Begeman9008ca62009-04-27 18:41:29 +00003964 Mask1[0] = HiIndex & 1 ? 2 : 0;
3965 Mask1[1] = HiIndex & 1 ? 0 : 2;
3966 Mask1[2] = PermMask[2];
3967 Mask1[3] = PermMask[3];
3968 if (Mask1[2] >= 0)
3969 Mask1[2] += 4;
3970 if (Mask1[3] >= 0)
3971 Mask1[3] += 4;
3972 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003973 }
Evan Chengace3c172008-07-22 21:13:36 +00003974 }
3975
3976 // Break it into (shuffle shuffle_hi, shuffle_lo).
3977 Locs.clear();
Nate Begeman9008ca62009-04-27 18:41:29 +00003978 SmallVector<int,8> LoMask(4U, -1);
3979 SmallVector<int,8> HiMask(4U, -1);
3980
3981 SmallVector<int,8> *MaskPtr = &LoMask;
Evan Chengace3c172008-07-22 21:13:36 +00003982 unsigned MaskIdx = 0;
3983 unsigned LoIdx = 0;
3984 unsigned HiIdx = 2;
3985 for (unsigned i = 0; i != 4; ++i) {
3986 if (i == 2) {
3987 MaskPtr = &HiMask;
3988 MaskIdx = 1;
3989 LoIdx = 0;
3990 HiIdx = 2;
3991 }
Nate Begeman9008ca62009-04-27 18:41:29 +00003992 int Idx = PermMask[i];
3993 if (Idx < 0) {
Evan Chengace3c172008-07-22 21:13:36 +00003994 Locs[i] = std::make_pair(-1, -1);
Nate Begeman9008ca62009-04-27 18:41:29 +00003995 } else if (Idx < 4) {
Evan Chengace3c172008-07-22 21:13:36 +00003996 Locs[i] = std::make_pair(MaskIdx, LoIdx);
Nate Begeman9008ca62009-04-27 18:41:29 +00003997 (*MaskPtr)[LoIdx] = Idx;
Evan Chengace3c172008-07-22 21:13:36 +00003998 LoIdx++;
3999 } else {
4000 Locs[i] = std::make_pair(MaskIdx, HiIdx);
Nate Begeman9008ca62009-04-27 18:41:29 +00004001 (*MaskPtr)[HiIdx] = Idx;
Evan Chengace3c172008-07-22 21:13:36 +00004002 HiIdx++;
4003 }
4004 }
4005
Nate Begeman9008ca62009-04-27 18:41:29 +00004006 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4007 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4008 SmallVector<int, 8> MaskOps;
Evan Chengace3c172008-07-22 21:13:36 +00004009 for (unsigned i = 0; i != 4; ++i) {
4010 if (Locs[i].first == -1) {
Nate Begeman9008ca62009-04-27 18:41:29 +00004011 MaskOps.push_back(-1);
Evan Chengace3c172008-07-22 21:13:36 +00004012 } else {
4013 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
Nate Begeman9008ca62009-04-27 18:41:29 +00004014 MaskOps.push_back(Idx);
Evan Chengace3c172008-07-22 21:13:36 +00004015 }
4016 }
Nate Begeman9008ca62009-04-27 18:41:29 +00004017 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
Evan Chengace3c172008-07-22 21:13:36 +00004018}
4019
Dan Gohman475871a2008-07-27 21:46:04 +00004020SDValue
4021X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
Nate Begeman9008ca62009-04-27 18:41:29 +00004022 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
Dan Gohman475871a2008-07-27 21:46:04 +00004023 SDValue V1 = Op.getOperand(0);
4024 SDValue V2 = Op.getOperand(1);
Duncan Sands83ec4b62008-06-06 12:08:01 +00004025 MVT VT = Op.getValueType();
Dale Johannesen6f38cb62009-02-07 19:59:05 +00004026 DebugLoc dl = Op.getDebugLoc();
Nate Begeman9008ca62009-04-27 18:41:29 +00004027 unsigned NumElems = VT.getVectorNumElements();
Duncan Sands83ec4b62008-06-06 12:08:01 +00004028 bool isMMX = VT.getSizeInBits() == 64;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004029 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4030 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
Evan Chengd9b8e402006-10-16 06:36:00 +00004031 bool V1IsSplat = false;
4032 bool V2IsSplat = false;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004033
Nate Begeman9008ca62009-04-27 18:41:29 +00004034 if (isZeroShuffle(SVOp))
Dale Johannesenace16102009-02-03 19:33:06 +00004035 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
Evan Cheng213d2cf2007-05-17 18:45:50 +00004036
Nate Begeman9008ca62009-04-27 18:41:29 +00004037 // Promote splats to v4f32.
4038 if (SVOp->isSplat()) {
4039 if (isMMX || NumElems < 4)
4040 return Op;
4041 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
Evan Cheng0db9fe62006-04-25 20:13:52 +00004042 }
4043
Evan Cheng7a831ce2007-12-15 03:00:47 +00004044 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4045 // do it!
4046 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
Nate Begeman9008ca62009-04-27 18:41:29 +00004047 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
Gabor Greifba36cb52008-08-28 21:40:38 +00004048 if (NewOp.getNode())
Scott Michelfdc40a02009-02-17 22:15:04 +00004049 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
Dale Johannesenace16102009-02-03 19:33:06 +00004050 LowerVECTOR_SHUFFLE(NewOp, DAG));
Evan Cheng7a831ce2007-12-15 03:00:47 +00004051 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4052 // FIXME: Figure out a cleaner way to do this.
4053 // Try to make use of movq to zero out the top part.
Gabor Greifba36cb52008-08-28 21:40:38 +00004054 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
Nate Begeman9008ca62009-04-27 18:41:29 +00004055 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
Gabor Greifba36cb52008-08-28 21:40:38 +00004056 if (NewOp.getNode()) {
Nate Begeman9008ca62009-04-27 18:41:29 +00004057 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4058 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4059 DAG, Subtarget, dl);
Evan Cheng7a831ce2007-12-15 03:00:47 +00004060 }
Gabor Greifba36cb52008-08-28 21:40:38 +00004061 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
Nate Begeman9008ca62009-04-27 18:41:29 +00004062 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4063 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
Evan Chengd880b972008-05-09 21:53:03 +00004064 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
Nate Begeman9008ca62009-04-27 18:41:29 +00004065 DAG, Subtarget, dl);
Evan Cheng7a831ce2007-12-15 03:00:47 +00004066 }
4067 }
Nate Begeman9008ca62009-04-27 18:41:29 +00004068
4069 if (X86::isPSHUFDMask(SVOp))
4070 return Op;
4071
Evan Chengf26ffe92008-05-29 08:22:04 +00004072 // Check if this can be converted into a logical shift.
4073 bool isLeft = false;
4074 unsigned ShAmt = 0;
Dan Gohman475871a2008-07-27 21:46:04 +00004075 SDValue ShVal;
Nate Begeman9008ca62009-04-27 18:41:29 +00004076 bool isShift = getSubtarget()->hasSSE2() &&
4077 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
Evan Chengf26ffe92008-05-29 08:22:04 +00004078 if (isShift && ShVal.hasOneUse()) {
Scott Michelfdc40a02009-02-17 22:15:04 +00004079 // If the shifted value has multiple uses, it may be cheaper to use
Evan Chengf26ffe92008-05-29 08:22:04 +00004080 // v_set0 + movlhps or movhlps, etc.
Duncan Sands83ec4b62008-06-06 12:08:01 +00004081 MVT EVT = VT.getVectorElementType();
4082 ShAmt *= EVT.getSizeInBits();
Dale Johannesenace16102009-02-03 19:33:06 +00004083 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
Evan Chengf26ffe92008-05-29 08:22:04 +00004084 }
Nate Begeman9008ca62009-04-27 18:41:29 +00004085
4086 if (X86::isMOVLMask(SVOp)) {
Evan Cheng7e2ff772008-05-08 00:57:18 +00004087 if (V1IsUndef)
4088 return V2;
Gabor Greifba36cb52008-08-28 21:40:38 +00004089 if (ISD::isBuildVectorAllZeros(V1.getNode()))
Dale Johannesenace16102009-02-03 19:33:06 +00004090 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
Nate Begemanfb8ead02008-07-25 19:05:58 +00004091 if (!isMMX)
4092 return Op;
Evan Cheng7e2ff772008-05-08 00:57:18 +00004093 }
Nate Begeman9008ca62009-04-27 18:41:29 +00004094
4095 // FIXME: fold these into legal mask.
4096 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4097 X86::isMOVSLDUPMask(SVOp) ||
4098 X86::isMOVHLPSMask(SVOp) ||
4099 X86::isMOVHPMask(SVOp) ||
4100 X86::isMOVLPMask(SVOp)))
Evan Cheng9bbbb982006-10-25 20:48:19 +00004101 return Op;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004102
Nate Begeman9008ca62009-04-27 18:41:29 +00004103 if (ShouldXformToMOVHLPS(SVOp) ||
4104 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4105 return CommuteVectorShuffle(SVOp, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004106
Evan Chengf26ffe92008-05-29 08:22:04 +00004107 if (isShift) {
4108 // No better options. Use a vshl / vsrl.
Duncan Sands83ec4b62008-06-06 12:08:01 +00004109 MVT EVT = VT.getVectorElementType();
4110 ShAmt *= EVT.getSizeInBits();
Dale Johannesenace16102009-02-03 19:33:06 +00004111 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
Evan Chengf26ffe92008-05-29 08:22:04 +00004112 }
Nate Begeman9008ca62009-04-27 18:41:29 +00004113
Evan Cheng9eca5e82006-10-25 21:49:50 +00004114 bool Commuted = false;
Chris Lattner8a594482007-11-25 00:24:49 +00004115 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4116 // 1,1,1,1 -> v8i16 though.
Gabor Greifba36cb52008-08-28 21:40:38 +00004117 V1IsSplat = isSplatVector(V1.getNode());
4118 V2IsSplat = isSplatVector(V2.getNode());
Scott Michelfdc40a02009-02-17 22:15:04 +00004119
Chris Lattner8a594482007-11-25 00:24:49 +00004120 // Canonicalize the splat or undef, if present, to be on the RHS.
Evan Cheng9bbbb982006-10-25 20:48:19 +00004121 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
Nate Begeman9008ca62009-04-27 18:41:29 +00004122 Op = CommuteVectorShuffle(SVOp, DAG);
4123 SVOp = cast<ShuffleVectorSDNode>(Op);
4124 V1 = SVOp->getOperand(0);
4125 V2 = SVOp->getOperand(1);
Evan Cheng9bbbb982006-10-25 20:48:19 +00004126 std::swap(V1IsSplat, V2IsSplat);
4127 std::swap(V1IsUndef, V2IsUndef);
Evan Cheng9eca5e82006-10-25 21:49:50 +00004128 Commuted = true;
Evan Cheng9bbbb982006-10-25 20:48:19 +00004129 }
4130
Nate Begeman9008ca62009-04-27 18:41:29 +00004131 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4132 // Shuffling low element of v1 into undef, just return v1.
4133 if (V2IsUndef)
4134 return V1;
4135 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4136 // the instruction selector will not match, so get a canonical MOVL with
4137 // swapped operands to undo the commute.
4138 return getMOVL(DAG, dl, VT, V2, V1);
Evan Chengd9b8e402006-10-16 06:36:00 +00004139 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004140
Nate Begeman9008ca62009-04-27 18:41:29 +00004141 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4142 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4143 X86::isUNPCKLMask(SVOp) ||
4144 X86::isUNPCKHMask(SVOp))
Evan Chengd9b8e402006-10-16 06:36:00 +00004145 return Op;
Evan Chenge1113032006-10-04 18:33:38 +00004146
Evan Cheng9bbbb982006-10-25 20:48:19 +00004147 if (V2IsSplat) {
4148 // Normalize mask so all entries that point to V2 points to its first
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00004149 // element then try to match unpck{h|l} again. If match, return a
Evan Cheng9bbbb982006-10-25 20:48:19 +00004150 // new vector_shuffle with the corrected mask.
Nate Begeman9008ca62009-04-27 18:41:29 +00004151 SDValue NewMask = NormalizeMask(SVOp, DAG);
4152 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4153 if (NSVOp != SVOp) {
4154 if (X86::isUNPCKLMask(NSVOp, true)) {
4155 return NewMask;
4156 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4157 return NewMask;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004158 }
4159 }
4160 }
4161
Evan Cheng9eca5e82006-10-25 21:49:50 +00004162 if (Commuted) {
4163 // Commute is back and try unpck* again.
Nate Begeman9008ca62009-04-27 18:41:29 +00004164 // FIXME: this seems wrong.
4165 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4166 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4167 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4168 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4169 X86::isUNPCKLMask(NewSVOp) ||
4170 X86::isUNPCKHMask(NewSVOp))
4171 return NewOp;
Evan Cheng9eca5e82006-10-25 21:49:50 +00004172 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004173
Nate Begemanb9a47b82009-02-23 08:49:38 +00004174 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
Nate Begeman9008ca62009-04-27 18:41:29 +00004175
4176 // Normalize the node to match x86 shuffle ops if needed
4177 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4178 return CommuteVectorShuffle(SVOp, DAG);
4179
4180 // Check for legal shuffle and return?
4181 SmallVector<int, 16> PermMask;
4182 SVOp->getMask(PermMask);
4183 if (isShuffleMaskLegal(PermMask, VT))
Evan Cheng0c0f83f2008-04-05 00:30:36 +00004184 return Op;
Nate Begeman9008ca62009-04-27 18:41:29 +00004185
Evan Cheng14b32e12007-12-11 01:46:18 +00004186 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4187 if (VT == MVT::v8i16) {
Nate Begeman9008ca62009-04-27 18:41:29 +00004188 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
Gabor Greifba36cb52008-08-28 21:40:38 +00004189 if (NewOp.getNode())
Evan Cheng14b32e12007-12-11 01:46:18 +00004190 return NewOp;
4191 }
4192
Nate Begemanb9a47b82009-02-23 08:49:38 +00004193 if (VT == MVT::v16i8) {
Nate Begeman9008ca62009-04-27 18:41:29 +00004194 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
Nate Begemanb9a47b82009-02-23 08:49:38 +00004195 if (NewOp.getNode())
4196 return NewOp;
4197 }
4198
Evan Chengace3c172008-07-22 21:13:36 +00004199 // Handle all 4 wide cases with a number of shuffles except for MMX.
4200 if (NumElems == 4 && !isMMX)
Nate Begeman9008ca62009-04-27 18:41:29 +00004201 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004202
Dan Gohman475871a2008-07-27 21:46:04 +00004203 return SDValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004204}
4205
Dan Gohman475871a2008-07-27 21:46:04 +00004206SDValue
4207X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
Nate Begeman14d12ca2008-02-11 04:19:36 +00004208 SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00004209 MVT VT = Op.getValueType();
Dale Johannesen6f38cb62009-02-07 19:59:05 +00004210 DebugLoc dl = Op.getDebugLoc();
Duncan Sands83ec4b62008-06-06 12:08:01 +00004211 if (VT.getSizeInBits() == 8) {
Dale Johannesenace16102009-02-03 19:33:06 +00004212 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
Nate Begeman14d12ca2008-02-11 04:19:36 +00004213 Op.getOperand(0), Op.getOperand(1));
Dale Johannesenace16102009-02-03 19:33:06 +00004214 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
Nate Begeman14d12ca2008-02-11 04:19:36 +00004215 DAG.getValueType(VT));
Dale Johannesenace16102009-02-03 19:33:06 +00004216 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
Duncan Sands83ec4b62008-06-06 12:08:01 +00004217 } else if (VT.getSizeInBits() == 16) {
Evan Cheng52ceafa2009-01-02 05:29:08 +00004218 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4219 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4220 if (Idx == 0)
Dale Johannesenace16102009-02-03 19:33:06 +00004221 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4222 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4223 DAG.getNode(ISD::BIT_CONVERT, dl,
4224 MVT::v4i32,
Evan Cheng52ceafa2009-01-02 05:29:08 +00004225 Op.getOperand(0)),
4226 Op.getOperand(1)));
Dale Johannesenace16102009-02-03 19:33:06 +00004227 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
Nate Begeman14d12ca2008-02-11 04:19:36 +00004228 Op.getOperand(0), Op.getOperand(1));
Dale Johannesenace16102009-02-03 19:33:06 +00004229 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
Nate Begeman14d12ca2008-02-11 04:19:36 +00004230 DAG.getValueType(VT));
Dale Johannesenace16102009-02-03 19:33:06 +00004231 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
Evan Cheng62a3f152008-03-24 21:52:23 +00004232 } else if (VT == MVT::f32) {
4233 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4234 // the result back to FR32 register. It's only worth matching if the
Dan Gohmand17cfbe2008-10-31 00:57:24 +00004235 // result has a single use which is a store or a bitcast to i32. And in
4236 // the case of a store, it's not worth it if the index is a constant 0,
4237 // because a MOVSSmr can be used instead, which is smaller and faster.
Evan Cheng62a3f152008-03-24 21:52:23 +00004238 if (!Op.hasOneUse())
Dan Gohman475871a2008-07-27 21:46:04 +00004239 return SDValue();
Gabor Greifba36cb52008-08-28 21:40:38 +00004240 SDNode *User = *Op.getNode()->use_begin();
Dan Gohmand17cfbe2008-10-31 00:57:24 +00004241 if ((User->getOpcode() != ISD::STORE ||
4242 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4243 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
Dan Gohman171c11e2008-04-16 02:32:24 +00004244 (User->getOpcode() != ISD::BIT_CONVERT ||
4245 User->getValueType(0) != MVT::i32))
Dan Gohman475871a2008-07-27 21:46:04 +00004246 return SDValue();
Dale Johannesenace16102009-02-03 19:33:06 +00004247 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
Scott Michelfdc40a02009-02-17 22:15:04 +00004248 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
Dale Johannesenace16102009-02-03 19:33:06 +00004249 Op.getOperand(0)),
4250 Op.getOperand(1));
4251 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
Mon P Wangf0fcdd82009-01-15 21:10:20 +00004252 } else if (VT == MVT::i32) {
4253 // ExtractPS works with constant index.
4254 if (isa<ConstantSDNode>(Op.getOperand(1)))
4255 return Op;
Nate Begeman14d12ca2008-02-11 04:19:36 +00004256 }
Dan Gohman475871a2008-07-27 21:46:04 +00004257 return SDValue();
Nate Begeman14d12ca2008-02-11 04:19:36 +00004258}
4259
4260
Dan Gohman475871a2008-07-27 21:46:04 +00004261SDValue
4262X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004263 if (!isa<ConstantSDNode>(Op.getOperand(1)))
Dan Gohman475871a2008-07-27 21:46:04 +00004264 return SDValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004265
Evan Cheng62a3f152008-03-24 21:52:23 +00004266 if (Subtarget->hasSSE41()) {
Dan Gohman475871a2008-07-27 21:46:04 +00004267 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
Gabor Greifba36cb52008-08-28 21:40:38 +00004268 if (Res.getNode())
Evan Cheng62a3f152008-03-24 21:52:23 +00004269 return Res;
4270 }
Nate Begeman14d12ca2008-02-11 04:19:36 +00004271
Duncan Sands83ec4b62008-06-06 12:08:01 +00004272 MVT VT = Op.getValueType();
Dale Johannesen6f38cb62009-02-07 19:59:05 +00004273 DebugLoc dl = Op.getDebugLoc();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004274 // TODO: handle v16i8.
Duncan Sands83ec4b62008-06-06 12:08:01 +00004275 if (VT.getSizeInBits() == 16) {
Dan Gohman475871a2008-07-27 21:46:04 +00004276 SDValue Vec = Op.getOperand(0);
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00004277 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
Evan Cheng14b32e12007-12-11 01:46:18 +00004278 if (Idx == 0)
Dale Johannesenace16102009-02-03 19:33:06 +00004279 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4280 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
Scott Michelfdc40a02009-02-17 22:15:04 +00004281 DAG.getNode(ISD::BIT_CONVERT, dl,
Dale Johannesenace16102009-02-03 19:33:06 +00004282 MVT::v4i32, Vec),
Evan Cheng14b32e12007-12-11 01:46:18 +00004283 Op.getOperand(1)));
Evan Cheng0db9fe62006-04-25 20:13:52 +00004284 // Transform it so it match pextrw which produces a 32-bit result.
Duncan Sands83ec4b62008-06-06 12:08:01 +00004285 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
Dale Johannesenace16102009-02-03 19:33:06 +00004286 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT,
Evan Cheng0db9fe62006-04-25 20:13:52 +00004287 Op.getOperand(0), Op.getOperand(1));
Dale Johannesenace16102009-02-03 19:33:06 +00004288 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract,
Evan Cheng0db9fe62006-04-25 20:13:52 +00004289 DAG.getValueType(VT));
Dale Johannesenace16102009-02-03 19:33:06 +00004290 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
Duncan Sands83ec4b62008-06-06 12:08:01 +00004291 } else if (VT.getSizeInBits() == 32) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00004292 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004293 if (Idx == 0)
4294 return Op;
Nate Begeman9008ca62009-04-27 18:41:29 +00004295
Evan Cheng0db9fe62006-04-25 20:13:52 +00004296 // SHUFPS the element to the lowest double word, then movss.
Nate Begeman9008ca62009-04-27 18:41:29 +00004297 int Mask[4] = { Idx, -1, -1, -1 };
4298 MVT VVT = Op.getOperand(0).getValueType();
4299 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4300 DAG.getUNDEF(VVT), Mask);
Dale Johannesenace16102009-02-03 19:33:06 +00004301 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
Chris Lattner0bd48932008-01-17 07:00:52 +00004302 DAG.getIntPtrConstant(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +00004303 } else if (VT.getSizeInBits() == 64) {
Nate Begeman14d12ca2008-02-11 04:19:36 +00004304 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4305 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4306 // to match extract_elt for f64.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00004307 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004308 if (Idx == 0)
4309 return Op;
4310
4311 // UNPCKHPD the element to the lowest double word, then movsd.
4312 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4313 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
Nate Begeman9008ca62009-04-27 18:41:29 +00004314 int Mask[2] = { 1, -1 };
4315 MVT VVT = Op.getOperand(0).getValueType();
4316 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4317 DAG.getUNDEF(VVT), Mask);
Dale Johannesenace16102009-02-03 19:33:06 +00004318 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
Chris Lattner0bd48932008-01-17 07:00:52 +00004319 DAG.getIntPtrConstant(0));
Evan Cheng0db9fe62006-04-25 20:13:52 +00004320 }
4321
Dan Gohman475871a2008-07-27 21:46:04 +00004322 return SDValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004323}
4324
Dan Gohman475871a2008-07-27 21:46:04 +00004325SDValue
4326X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
Duncan Sands83ec4b62008-06-06 12:08:01 +00004327 MVT VT = Op.getValueType();
4328 MVT EVT = VT.getVectorElementType();
Dale Johannesen6f38cb62009-02-07 19:59:05 +00004329 DebugLoc dl = Op.getDebugLoc();
Nate Begeman14d12ca2008-02-11 04:19:36 +00004330
Dan Gohman475871a2008-07-27 21:46:04 +00004331 SDValue N0 = Op.getOperand(0);
4332 SDValue N1 = Op.getOperand(1);
4333 SDValue N2 = Op.getOperand(2);
Nate Begeman14d12ca2008-02-11 04:19:36 +00004334
Dan Gohmanef521f12008-08-14 22:53:18 +00004335 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4336 isa<ConstantSDNode>(N2)) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00004337 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
Nate Begemanb9a47b82009-02-23 08:49:38 +00004338 : X86ISD::PINSRW;
Nate Begeman14d12ca2008-02-11 04:19:36 +00004339 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4340 // argument.
4341 if (N1.getValueType() != MVT::i32)
Dale Johannesenace16102009-02-03 19:33:06 +00004342 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
Nate Begeman14d12ca2008-02-11 04:19:36 +00004343 if (N2.getValueType() != MVT::i32)
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00004344 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
Dale Johannesenace16102009-02-03 19:33:06 +00004345 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
Dan Gohmanc0573b12008-08-14 22:43:26 +00004346 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
Nate Begeman14d12ca2008-02-11 04:19:36 +00004347 // Bits [7:6] of the constant are the source select. This will always be
4348 // zero here. The DAG Combiner may combine an extract_elt index into these
4349 // bits. For example (insert (extract, 3), 2) could be matched by putting
4350 // the '3' into bits [7:6] of X86ISD::INSERTPS.
Scott Michelfdc40a02009-02-17 22:15:04 +00004351 // Bits [5:4] of the constant are the destination select. This is the
Nate Begeman14d12ca2008-02-11 04:19:36 +00004352 // value of the incoming immediate.
Scott Michelfdc40a02009-02-17 22:15:04 +00004353 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
Nate Begeman14d12ca2008-02-11 04:19:36 +00004354 // combine either bitwise AND or insert of float 0.0 to set these bits.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00004355 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
Dale Johannesenace16102009-02-03 19:33:06 +00004356 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
Mon P Wangf0fcdd82009-01-15 21:10:20 +00004357 } else if (EVT == MVT::i32) {
4358 // InsertPS works with constant index.
4359 if (isa<ConstantSDNode>(N2))
4360 return Op;
Nate Begeman14d12ca2008-02-11 04:19:36 +00004361 }
Dan Gohman475871a2008-07-27 21:46:04 +00004362 return SDValue();
Nate Begeman14d12ca2008-02-11 04:19:36 +00004363}
4364
Dan Gohman475871a2008-07-27 21:46:04 +00004365SDValue
4366X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00004367 MVT VT = Op.getValueType();
4368 MVT EVT = VT.getVectorElementType();
Nate Begeman14d12ca2008-02-11 04:19:36 +00004369
4370 if (Subtarget->hasSSE41())
4371 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4372
Evan Cheng794405e2007-12-12 07:55:34 +00004373 if (EVT == MVT::i8)
Dan Gohman475871a2008-07-27 21:46:04 +00004374 return SDValue();
Evan Cheng794405e2007-12-12 07:55:34 +00004375
Dale Johannesen6f38cb62009-02-07 19:59:05 +00004376 DebugLoc dl = Op.getDebugLoc();
Dan Gohman475871a2008-07-27 21:46:04 +00004377 SDValue N0 = Op.getOperand(0);
4378 SDValue N1 = Op.getOperand(1);
4379 SDValue N2 = Op.getOperand(2);
Evan Cheng794405e2007-12-12 07:55:34 +00004380
Eli Friedman30e71eb2009-06-06 06:32:50 +00004381 if (EVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
Evan Cheng794405e2007-12-12 07:55:34 +00004382 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4383 // as its second argument.
Evan Cheng0db9fe62006-04-25 20:13:52 +00004384 if (N1.getValueType() != MVT::i32)
Dale Johannesenace16102009-02-03 19:33:06 +00004385 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004386 if (N2.getValueType() != MVT::i32)
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00004387 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
Dale Johannesenace16102009-02-03 19:33:06 +00004388 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004389 }
Dan Gohman475871a2008-07-27 21:46:04 +00004390 return SDValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004391}
4392
Dan Gohman475871a2008-07-27 21:46:04 +00004393SDValue
4394X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
Dale Johannesen6f38cb62009-02-07 19:59:05 +00004395 DebugLoc dl = Op.getDebugLoc();
Evan Cheng52672b82008-07-22 18:39:19 +00004396 if (Op.getValueType() == MVT::v2f32)
Dale Johannesenace16102009-02-03 19:33:06 +00004397 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4398 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4399 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
Evan Cheng52672b82008-07-22 18:39:19 +00004400 Op.getOperand(0))));
4401
Dale Johannesenace16102009-02-03 19:33:06 +00004402 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +00004403 MVT VT = MVT::v2i32;
4404 switch (Op.getValueType().getSimpleVT()) {
Evan Chengefec7512008-02-18 23:04:32 +00004405 default: break;
4406 case MVT::v16i8:
4407 case MVT::v8i16:
4408 VT = MVT::v4i32;
4409 break;
4410 }
Dale Johannesenace16102009-02-03 19:33:06 +00004411 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4412 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
Evan Cheng0db9fe62006-04-25 20:13:52 +00004413}
4414
Bill Wendling056292f2008-09-16 21:48:12 +00004415// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4416// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4417// one of the above mentioned nodes. It has to be wrapped because otherwise
4418// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4419// be used to form addressing mode. These wrapped nodes will be selected
4420// into MOV32ri.
Dan Gohman475871a2008-07-27 21:46:04 +00004421SDValue
4422X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004423 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Chris Lattner41621a22009-06-26 19:22:52 +00004424
4425 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4426 // global base reg.
4427 unsigned char OpFlag = 0;
Chris Lattner18c59872009-06-27 04:16:01 +00004428 unsigned WrapperKind = X86ISD::Wrapper;
Chris Lattnere4df7562009-07-09 03:15:51 +00004429
4430 if (Subtarget->is64Bit() &&
4431 getTargetMachine().getCodeModel() == CodeModel::Small) {
4432 WrapperKind = X86ISD::WrapperRIP;
Chris Lattner88e1fd52009-07-09 04:24:46 +00004433 } else if (Subtarget->isPICStyleGOT()) {
4434 OpFlag = X86II::MO_GOTOFF;
4435 } else if (Subtarget->isPICStyleStub() &&
4436 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
4437 OpFlag = X86II::MO_PIC_BASE_OFFSET;
Chris Lattner41621a22009-06-26 19:22:52 +00004438 }
4439
Evan Cheng1606e8e2009-03-13 07:51:59 +00004440 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
Chris Lattner41621a22009-06-26 19:22:52 +00004441 CP->getAlignment(),
4442 CP->getOffset(), OpFlag);
4443 DebugLoc DL = CP->getDebugLoc();
Chris Lattner18c59872009-06-27 04:16:01 +00004444 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
Anton Korobeynikov7f705592007-01-12 19:20:47 +00004445 // With PIC, the address is actually $g + Offset.
Chris Lattner41621a22009-06-26 19:22:52 +00004446 if (OpFlag) {
4447 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
Dale Johannesenb300d2a2009-02-07 00:55:49 +00004448 DAG.getNode(X86ISD::GlobalBaseReg,
Chris Lattner41621a22009-06-26 19:22:52 +00004449 DebugLoc::getUnknownLoc(), getPointerTy()),
Anton Korobeynikov7f705592007-01-12 19:20:47 +00004450 Result);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004451 }
4452
4453 return Result;
4454}
4455
Chris Lattner18c59872009-06-27 04:16:01 +00004456SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4457 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4458
4459 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4460 // global base reg.
4461 unsigned char OpFlag = 0;
4462 unsigned WrapperKind = X86ISD::Wrapper;
Chris Lattnere4df7562009-07-09 03:15:51 +00004463
4464 if (Subtarget->is64Bit()) {
4465 WrapperKind = X86ISD::WrapperRIP;
Chris Lattner88e1fd52009-07-09 04:24:46 +00004466 } else if (Subtarget->isPICStyleGOT()) {
4467 OpFlag = X86II::MO_GOTOFF;
4468 } else if (Subtarget->isPICStyleStub() &&
4469 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
4470 OpFlag = X86II::MO_PIC_BASE_OFFSET;
Chris Lattner18c59872009-06-27 04:16:01 +00004471 }
4472
4473 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4474 OpFlag);
4475 DebugLoc DL = JT->getDebugLoc();
4476 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4477
4478 // With PIC, the address is actually $g + Offset.
4479 if (OpFlag) {
4480 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4481 DAG.getNode(X86ISD::GlobalBaseReg,
4482 DebugLoc::getUnknownLoc(), getPointerTy()),
4483 Result);
4484 }
4485
4486 return Result;
4487}
4488
4489SDValue
4490X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4491 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4492
4493 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4494 // global base reg.
4495 unsigned char OpFlag = 0;
4496 unsigned WrapperKind = X86ISD::Wrapper;
Chris Lattnere4df7562009-07-09 03:15:51 +00004497 if (Subtarget->is64Bit()) {
4498 WrapperKind = X86ISD::WrapperRIP;
Chris Lattner88e1fd52009-07-09 04:24:46 +00004499 } else if (Subtarget->isPICStyleGOT()) {
4500 OpFlag = X86II::MO_GOTOFF;
4501 } else if (Subtarget->isPICStyleStub() &&
4502 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
4503 OpFlag = X86II::MO_PIC_BASE_OFFSET;
Chris Lattner18c59872009-06-27 04:16:01 +00004504 }
4505
4506 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4507
4508 DebugLoc DL = Op.getDebugLoc();
4509 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4510
4511
4512 // With PIC, the address is actually $g + Offset.
4513 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
Chris Lattnere4df7562009-07-09 03:15:51 +00004514 !Subtarget->is64Bit()) {
Chris Lattner18c59872009-06-27 04:16:01 +00004515 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4516 DAG.getNode(X86ISD::GlobalBaseReg,
4517 DebugLoc::getUnknownLoc(),
4518 getPointerTy()),
4519 Result);
4520 }
4521
4522 return Result;
4523}
4524
Dan Gohman475871a2008-07-27 21:46:04 +00004525SDValue
Dale Johannesen33c960f2009-02-04 20:06:27 +00004526X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
Dan Gohman6520e202008-10-18 02:06:02 +00004527 int64_t Offset,
Evan Chengda43bcf2008-09-24 00:05:32 +00004528 SelectionDAG &DAG) const {
Dan Gohman6520e202008-10-18 02:06:02 +00004529 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
4530 bool ExtraLoadRequired =
4531 Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false);
4532
4533 // Create the TargetGlobalAddress node, folding in the constant
4534 // offset if it is legal.
4535 SDValue Result;
Dan Gohman44013612008-10-21 03:38:42 +00004536 if (!IsPic && !ExtraLoadRequired && isInt32(Offset)) {
Chris Lattner4aa21aa2009-07-09 00:58:53 +00004537 // A direct static reference to a global.
Dan Gohman6520e202008-10-18 02:06:02 +00004538 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4539 Offset = 0;
Chris Lattner18c59872009-06-27 04:16:01 +00004540 } else {
Chris Lattnerb1acd682009-06-27 05:39:56 +00004541 unsigned char OpFlags = 0;
4542
Chris Lattner4aa21aa2009-07-09 00:58:53 +00004543 if (GV->hasDLLImportLinkage())
4544 OpFlags = X86II::MO_DLLIMPORT;
Chris Lattner88e1fd52009-07-09 04:24:46 +00004545 else if (Subtarget->isPICStyleRIPRel()) {
Chris Lattnerb1acd682009-06-27 05:39:56 +00004546 if (ExtraLoadRequired)
4547 OpFlags = X86II::MO_GOTPCREL;
Chris Lattner88e1fd52009-07-09 04:24:46 +00004548 } else if (Subtarget->isPICStyleGOT()) {
Chris Lattnerb1acd682009-06-27 05:39:56 +00004549 if (ExtraLoadRequired)
4550 OpFlags = X86II::MO_GOT;
4551 else
4552 OpFlags = X86II::MO_GOTOFF;
4553 }
4554
4555 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
Chris Lattner18c59872009-06-27 04:16:01 +00004556 }
4557
Chris Lattnere4df7562009-07-09 03:15:51 +00004558 if (Subtarget->is64Bit() &&
Chris Lattner18c59872009-06-27 04:16:01 +00004559 getTargetMachine().getCodeModel() == CodeModel::Small)
4560 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4561 else
4562 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
Dan Gohman6520e202008-10-18 02:06:02 +00004563
Anton Korobeynikov7f705592007-01-12 19:20:47 +00004564 // With PIC, the address is actually $g + Offset.
Chris Lattnere4df7562009-07-09 03:15:51 +00004565 if (IsPic && !Subtarget->is64Bit()) {
Dale Johannesen33c960f2009-02-04 20:06:27 +00004566 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4567 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
Anton Korobeynikov7f705592007-01-12 19:20:47 +00004568 Result);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004569 }
Scott Michelfdc40a02009-02-17 22:15:04 +00004570
Anton Korobeynikov2b2bc682006-12-22 22:29:05 +00004571 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4572 // load the value at address GV, not the value of GV itself. This means that
4573 // the GlobalAddress must be in the base or index register of the address, not
4574 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
Anton Korobeynikov7f705592007-01-12 19:20:47 +00004575 // The same applies for external symbols during PIC codegen
Dan Gohman6520e202008-10-18 02:06:02 +00004576 if (ExtraLoadRequired)
Dale Johannesen33c960f2009-02-04 20:06:27 +00004577 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
Dan Gohman3069b872008-02-07 18:41:25 +00004578 PseudoSourceValue::getGOT(), 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004579
Dan Gohman6520e202008-10-18 02:06:02 +00004580 // If there was a non-zero offset that we didn't fold, create an explicit
4581 // addition for it.
4582 if (Offset != 0)
Dale Johannesen33c960f2009-02-04 20:06:27 +00004583 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
Dan Gohman6520e202008-10-18 02:06:02 +00004584 DAG.getConstant(Offset, getPointerTy()));
4585
Evan Cheng0db9fe62006-04-25 20:13:52 +00004586 return Result;
4587}
4588
Evan Chengda43bcf2008-09-24 00:05:32 +00004589SDValue
4590X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4591 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Dan Gohman6520e202008-10-18 02:06:02 +00004592 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
Dale Johannesen6f38cb62009-02-07 19:59:05 +00004593 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
Evan Chengda43bcf2008-09-24 00:05:32 +00004594}
4595
Rafael Espindola2ee3db32009-04-17 14:35:58 +00004596static SDValue
4597GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
Chris Lattnerb903bed2009-06-26 21:20:29 +00004598 SDValue *InFlag, const MVT PtrVT, unsigned ReturnReg,
4599 unsigned char OperandFlags) {
Rafael Espindola2ee3db32009-04-17 14:35:58 +00004600 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4601 DebugLoc dl = GA->getDebugLoc();
4602 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4603 GA->getValueType(0),
Chris Lattnerb903bed2009-06-26 21:20:29 +00004604 GA->getOffset(),
4605 OperandFlags);
Rafael Espindola2ee3db32009-04-17 14:35:58 +00004606 if (InFlag) {
4607 SDValue Ops[] = { Chain, TGA, *InFlag };
Rafael Espindola15f1b662009-04-24 12:59:40 +00004608 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
Rafael Espindola2ee3db32009-04-17 14:35:58 +00004609 } else {
4610 SDValue Ops[] = { Chain, TGA };
Rafael Espindola15f1b662009-04-24 12:59:40 +00004611 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
Rafael Espindola2ee3db32009-04-17 14:35:58 +00004612 }
Rafael Espindola15f1b662009-04-24 12:59:40 +00004613 SDValue Flag = Chain.getValue(1);
4614 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
Rafael Espindola2ee3db32009-04-17 14:35:58 +00004615}
4616
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004617// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
Dan Gohman475871a2008-07-27 21:46:04 +00004618static SDValue
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004619LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
Duncan Sands83ec4b62008-06-06 12:08:01 +00004620 const MVT PtrVT) {
Dan Gohman475871a2008-07-27 21:46:04 +00004621 SDValue InFlag;
Dale Johannesendd64c412009-02-04 00:33:20 +00004622 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4623 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004624 DAG.getNode(X86ISD::GlobalBaseReg,
Dale Johannesenb300d2a2009-02-07 00:55:49 +00004625 DebugLoc::getUnknownLoc(),
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004626 PtrVT), InFlag);
4627 InFlag = Chain.getValue(1);
4628
Chris Lattnerb903bed2009-06-26 21:20:29 +00004629 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004630}
4631
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004632// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
Dan Gohman475871a2008-07-27 21:46:04 +00004633static SDValue
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004634LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
Duncan Sands83ec4b62008-06-06 12:08:01 +00004635 const MVT PtrVT) {
Chris Lattnerb903bed2009-06-26 21:20:29 +00004636 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
4637 X86::RAX, X86II::MO_TLSGD);
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004638}
4639
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004640// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4641// "local exec" model.
Dan Gohman475871a2008-07-27 21:46:04 +00004642static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
Rafael Espindola7ff5bff2009-04-13 13:02:49 +00004643 const MVT PtrVT, TLSModel::Model model,
4644 bool is64Bit) {
Dale Johannesen33c960f2009-02-04 20:06:27 +00004645 DebugLoc dl = GA->getDebugLoc();
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004646 // Get the Thread Pointer
Rafael Espindola094fad32009-04-08 21:14:34 +00004647 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
4648 DebugLoc::getUnknownLoc(), PtrVT,
Rafael Espindola7ff5bff2009-04-13 13:02:49 +00004649 DAG.getRegister(is64Bit? X86::FS : X86::GS,
4650 MVT::i32));
Rafael Espindola094fad32009-04-08 21:14:34 +00004651
4652 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
4653 NULL, 0);
4654
Chris Lattnerb903bed2009-06-26 21:20:29 +00004655 unsigned char OperandFlags = 0;
Chris Lattner18c59872009-06-27 04:16:01 +00004656 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
4657 // initialexec.
4658 unsigned WrapperKind = X86ISD::Wrapper;
4659 if (model == TLSModel::LocalExec) {
Chris Lattnerb903bed2009-06-26 21:20:29 +00004660 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
Chris Lattner18c59872009-06-27 04:16:01 +00004661 } else if (is64Bit) {
4662 assert(model == TLSModel::InitialExec);
4663 OperandFlags = X86II::MO_GOTTPOFF;
4664 WrapperKind = X86ISD::WrapperRIP;
4665 } else {
4666 assert(model == TLSModel::InitialExec);
4667 OperandFlags = X86II::MO_INDNTPOFF;
Chris Lattnerb903bed2009-06-26 21:20:29 +00004668 }
Chris Lattnerb903bed2009-06-26 21:20:29 +00004669
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004670 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4671 // exec)
Chris Lattner4150c082009-06-21 02:22:34 +00004672 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
Chris Lattnerb903bed2009-06-26 21:20:29 +00004673 GA->getOffset(), OperandFlags);
Chris Lattner18c59872009-06-27 04:16:01 +00004674 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
Lauro Ramos Venancio7d2cc2b2007-04-22 22:50:52 +00004675
Rafael Espindola9a580232009-02-27 13:37:18 +00004676 if (model == TLSModel::InitialExec)
Dale Johannesen33c960f2009-02-04 20:06:27 +00004677 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
Dan Gohman3069b872008-02-07 18:41:25 +00004678 PseudoSourceValue::getGOT(), 0);
Lauro Ramos Venancio7d2cc2b2007-04-22 22:50:52 +00004679
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004680 // The address of the thread local variable is the add of the thread
4681 // pointer with the offset of the variable.
Dale Johannesen33c960f2009-02-04 20:06:27 +00004682 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004683}
4684
Dan Gohman475871a2008-07-27 21:46:04 +00004685SDValue
4686X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004687 // TODO: implement the "local dynamic" model
Lauro Ramos Venancio2c5c1112007-04-21 20:56:26 +00004688 // TODO: implement the "initial exec"model for pic executables
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004689 assert(Subtarget->isTargetELF() &&
4690 "TLS not implemented for non-ELF targets");
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004691 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
Chris Lattnerb903bed2009-06-26 21:20:29 +00004692 const GlobalValue *GV = GA->getGlobal();
4693
4694 // If GV is an alias then use the aliasee for determining
4695 // thread-localness.
4696 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
4697 GV = GA->resolveAliasedGlobal(false);
4698
4699 TLSModel::Model model = getTLSModel(GV,
4700 getTargetMachine().getRelocationModel());
4701
4702 switch (model) {
4703 case TLSModel::GeneralDynamic:
4704 case TLSModel::LocalDynamic: // not implemented
4705 if (Subtarget->is64Bit())
Rafael Espindola9a580232009-02-27 13:37:18 +00004706 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
Chris Lattnerb903bed2009-06-26 21:20:29 +00004707 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4708
4709 case TLSModel::InitialExec:
4710 case TLSModel::LocalExec:
4711 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
4712 Subtarget->is64Bit());
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004713 }
Chris Lattnerb903bed2009-06-26 21:20:29 +00004714
Chris Lattner5867de12009-04-01 22:14:45 +00004715 assert(0 && "Unreachable");
4716 return SDValue();
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004717}
4718
Evan Cheng0db9fe62006-04-25 20:13:52 +00004719
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004720/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
Scott Michelfdc40a02009-02-17 22:15:04 +00004721/// take a 2 x i32 value to shift plus a shift amount.
Dan Gohman475871a2008-07-27 21:46:04 +00004722SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
Dan Gohman4c1fa612008-03-03 22:22:09 +00004723 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
Duncan Sands83ec4b62008-06-06 12:08:01 +00004724 MVT VT = Op.getValueType();
4725 unsigned VTBits = VT.getSizeInBits();
Dale Johannesen6f38cb62009-02-07 19:59:05 +00004726 DebugLoc dl = Op.getDebugLoc();
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004727 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
Dan Gohman475871a2008-07-27 21:46:04 +00004728 SDValue ShOpLo = Op.getOperand(0);
4729 SDValue ShOpHi = Op.getOperand(1);
4730 SDValue ShAmt = Op.getOperand(2);
4731 SDValue Tmp1 = isSRA ?
Scott Michelfdc40a02009-02-17 22:15:04 +00004732 DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
Dale Johannesenace16102009-02-03 19:33:06 +00004733 DAG.getConstant(VTBits - 1, MVT::i8)) :
Dan Gohman4c1fa612008-03-03 22:22:09 +00004734 DAG.getConstant(0, VT);
Evan Chenge3413162006-01-09 18:33:28 +00004735
Dan Gohman475871a2008-07-27 21:46:04 +00004736 SDValue Tmp2, Tmp3;
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004737 if (Op.getOpcode() == ISD::SHL_PARTS) {
Dale Johannesenace16102009-02-03 19:33:06 +00004738 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
4739 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004740 } else {
Dale Johannesenace16102009-02-03 19:33:06 +00004741 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
4742 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004743 }
Evan Chenge3413162006-01-09 18:33:28 +00004744
Dale Johannesenace16102009-02-03 19:33:06 +00004745 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
Dan Gohman4c1fa612008-03-03 22:22:09 +00004746 DAG.getConstant(VTBits, MVT::i8));
Dale Johannesenace16102009-02-03 19:33:06 +00004747 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004748 AndNode, DAG.getConstant(0, MVT::i8));
Evan Chenge3413162006-01-09 18:33:28 +00004749
Dan Gohman475871a2008-07-27 21:46:04 +00004750 SDValue Hi, Lo;
4751 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4752 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4753 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
Duncan Sandsf9516202008-06-30 10:19:09 +00004754
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004755 if (Op.getOpcode() == ISD::SHL_PARTS) {
Dale Johannesenace16102009-02-03 19:33:06 +00004756 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4757 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004758 } else {
Dale Johannesenace16102009-02-03 19:33:06 +00004759 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4760 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004761 }
4762
Dan Gohman475871a2008-07-27 21:46:04 +00004763 SDValue Ops[2] = { Lo, Hi };
Dale Johannesenace16102009-02-03 19:33:06 +00004764 return DAG.getMergeValues(Ops, 2, dl);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004765}
Evan Chenga3195e82006-01-12 22:54:21 +00004766
Dan Gohman475871a2008-07-27 21:46:04 +00004767SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00004768 MVT SrcVT = Op.getOperand(0).getValueType();
Eli Friedman23ef1052009-06-06 03:57:58 +00004769
4770 if (SrcVT.isVector()) {
4771 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
4772 return Op;
4773 }
4774 return SDValue();
4775 }
4776
Duncan Sands8e4eb092008-06-08 20:54:56 +00004777 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
Chris Lattnerb09916b2008-02-27 05:57:41 +00004778 "Unknown SINT_TO_FP to lower!");
Scott Michelfdc40a02009-02-17 22:15:04 +00004779
Eli Friedman36df4992009-05-27 00:47:34 +00004780 // These are really Legal; return the operand so the caller accepts it as
4781 // Legal.
Chris Lattnerb09916b2008-02-27 05:57:41 +00004782 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
Eli Friedman36df4992009-05-27 00:47:34 +00004783 return Op;
4784 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
4785 Subtarget->is64Bit()) {
4786 return Op;
4787 }
Scott Michelfdc40a02009-02-17 22:15:04 +00004788
Dale Johannesen6f38cb62009-02-07 19:59:05 +00004789 DebugLoc dl = Op.getDebugLoc();
Duncan Sands83ec4b62008-06-06 12:08:01 +00004790 unsigned Size = SrcVT.getSizeInBits()/8;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004791 MachineFunction &MF = DAG.getMachineFunction();
4792 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
Dan Gohman475871a2008-07-27 21:46:04 +00004793 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
Dale Johannesenace16102009-02-03 19:33:06 +00004794 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
Bill Wendling105be5a2009-03-13 08:41:47 +00004795 StackSlot,
4796 PseudoSourceValue::getFixedStack(SSFI), 0);
Eli Friedman948e95a2009-05-23 09:59:16 +00004797 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
4798}
Evan Cheng0db9fe62006-04-25 20:13:52 +00004799
Eli Friedman948e95a2009-05-23 09:59:16 +00004800SDValue X86TargetLowering::BuildFILD(SDValue Op, MVT SrcVT, SDValue Chain,
4801 SDValue StackSlot,
4802 SelectionDAG &DAG) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004803 // Build the FILD
Eli Friedman948e95a2009-05-23 09:59:16 +00004804 DebugLoc dl = Op.getDebugLoc();
Chris Lattner5a88b832007-02-25 07:10:00 +00004805 SDVTList Tys;
Chris Lattner78631162008-01-16 06:24:21 +00004806 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00004807 if (useSSE)
Chris Lattner5a88b832007-02-25 07:10:00 +00004808 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4809 else
Dale Johannesen849f2142007-07-03 00:53:03 +00004810 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
Dan Gohman475871a2008-07-27 21:46:04 +00004811 SmallVector<SDValue, 8> Ops;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004812 Ops.push_back(Chain);
4813 Ops.push_back(StackSlot);
4814 Ops.push_back(DAG.getValueType(SrcVT));
Dale Johannesenace16102009-02-03 19:33:06 +00004815 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
Chris Lattnerb09916b2008-02-27 05:57:41 +00004816 Tys, &Ops[0], Ops.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00004817
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00004818 if (useSSE) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004819 Chain = Result.getValue(1);
Dan Gohman475871a2008-07-27 21:46:04 +00004820 SDValue InFlag = Result.getValue(2);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004821
4822 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4823 // shouldn't be necessary except that RFP cannot be live across
4824 // multiple blocks. When stackifier is fixed, they can be uncoupled.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004825 MachineFunction &MF = DAG.getMachineFunction();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004826 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
Dan Gohman475871a2008-07-27 21:46:04 +00004827 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
Chris Lattner5a88b832007-02-25 07:10:00 +00004828 Tys = DAG.getVTList(MVT::Other);
Dan Gohman475871a2008-07-27 21:46:04 +00004829 SmallVector<SDValue, 8> Ops;
Evan Chenga3195e82006-01-12 22:54:21 +00004830 Ops.push_back(Chain);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004831 Ops.push_back(Result);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004832 Ops.push_back(StackSlot);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004833 Ops.push_back(DAG.getValueType(Op.getValueType()));
4834 Ops.push_back(InFlag);
Dale Johannesenace16102009-02-03 19:33:06 +00004835 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
4836 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
Dan Gohmana54cf172008-07-11 22:44:52 +00004837 PseudoSourceValue::getFixedStack(SSFI), 0);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004838 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004839
Evan Cheng0db9fe62006-04-25 20:13:52 +00004840 return Result;
4841}
4842
Bill Wendling8b8a6362009-01-17 03:56:04 +00004843// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
4844SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
4845 // This algorithm is not obvious. Here it is in C code, more or less:
4846 /*
4847 double uint64_to_double( uint32_t hi, uint32_t lo ) {
4848 static const __m128i exp = { 0x4330000045300000ULL, 0 };
4849 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
Dale Johannesen040225f2008-10-21 23:07:49 +00004850
Bill Wendling8b8a6362009-01-17 03:56:04 +00004851 // Copy ints to xmm registers.
4852 __m128i xh = _mm_cvtsi32_si128( hi );
4853 __m128i xl = _mm_cvtsi32_si128( lo );
Dale Johannesen040225f2008-10-21 23:07:49 +00004854
Bill Wendling8b8a6362009-01-17 03:56:04 +00004855 // Combine into low half of a single xmm register.
4856 __m128i x = _mm_unpacklo_epi32( xh, xl );
4857 __m128d d;
4858 double sd;
Dale Johannesen040225f2008-10-21 23:07:49 +00004859
Bill Wendling8b8a6362009-01-17 03:56:04 +00004860 // Merge in appropriate exponents to give the integer bits the right
4861 // magnitude.
4862 x = _mm_unpacklo_epi32( x, exp );
Dale Johannesen040225f2008-10-21 23:07:49 +00004863
Bill Wendling8b8a6362009-01-17 03:56:04 +00004864 // Subtract away the biases to deal with the IEEE-754 double precision
4865 // implicit 1.
4866 d = _mm_sub_pd( (__m128d) x, bias );
Dale Johannesen040225f2008-10-21 23:07:49 +00004867
Bill Wendling8b8a6362009-01-17 03:56:04 +00004868 // All conversions up to here are exact. The correctly rounded result is
4869 // calculated using the current rounding mode using the following
4870 // horizontal add.
4871 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
4872 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
4873 // store doesn't really need to be here (except
4874 // maybe to zero the other double)
4875 return sd;
4876 }
4877 */
Dale Johannesen040225f2008-10-21 23:07:49 +00004878
Dale Johannesen6f38cb62009-02-07 19:59:05 +00004879 DebugLoc dl = Op.getDebugLoc();
Dale Johannesenace16102009-02-03 19:33:06 +00004880
Dale Johannesen1c15bf52008-10-21 20:50:01 +00004881 // Build some magic constants.
Bill Wendling8b8a6362009-01-17 03:56:04 +00004882 std::vector<Constant*> CV0;
Dale Johannesen1c15bf52008-10-21 20:50:01 +00004883 CV0.push_back(ConstantInt::get(APInt(32, 0x45300000)));
4884 CV0.push_back(ConstantInt::get(APInt(32, 0x43300000)));
4885 CV0.push_back(ConstantInt::get(APInt(32, 0)));
4886 CV0.push_back(ConstantInt::get(APInt(32, 0)));
4887 Constant *C0 = ConstantVector::get(CV0);
Evan Cheng1606e8e2009-03-13 07:51:59 +00004888 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
Dale Johannesen1c15bf52008-10-21 20:50:01 +00004889
Bill Wendling8b8a6362009-01-17 03:56:04 +00004890 std::vector<Constant*> CV1;
Dale Johannesen1c15bf52008-10-21 20:50:01 +00004891 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4530000000000000ULL))));
4892 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4330000000000000ULL))));
4893 Constant *C1 = ConstantVector::get(CV1);
Evan Cheng1606e8e2009-03-13 07:51:59 +00004894 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
Dale Johannesen1c15bf52008-10-21 20:50:01 +00004895
Dale Johannesenace16102009-02-03 19:33:06 +00004896 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4897 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Duncan Sands6b6aeb32008-10-22 11:24:12 +00004898 Op.getOperand(0),
4899 DAG.getIntPtrConstant(1)));
Dale Johannesenace16102009-02-03 19:33:06 +00004900 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4901 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Duncan Sands6b6aeb32008-10-22 11:24:12 +00004902 Op.getOperand(0),
4903 DAG.getIntPtrConstant(0)));
Nate Begeman9008ca62009-04-27 18:41:29 +00004904 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
Dale Johannesenace16102009-02-03 19:33:06 +00004905 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
Bill Wendling8b8a6362009-01-17 03:56:04 +00004906 PseudoSourceValue::getConstantPool(), 0,
4907 false, 16);
Nate Begeman9008ca62009-04-27 18:41:29 +00004908 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
Dale Johannesenace16102009-02-03 19:33:06 +00004909 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
4910 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
Bill Wendling8b8a6362009-01-17 03:56:04 +00004911 PseudoSourceValue::getConstantPool(), 0,
4912 false, 16);
Dale Johannesenace16102009-02-03 19:33:06 +00004913 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
Bill Wendling8b8a6362009-01-17 03:56:04 +00004914
Dale Johannesen1c15bf52008-10-21 20:50:01 +00004915 // Add the halves; easiest way is to swap them into another reg first.
Nate Begeman9008ca62009-04-27 18:41:29 +00004916 int ShufMask[2] = { 1, -1 };
4917 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
4918 DAG.getUNDEF(MVT::v2f64), ShufMask);
Dale Johannesenace16102009-02-03 19:33:06 +00004919 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
4920 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
Dale Johannesen1c15bf52008-10-21 20:50:01 +00004921 DAG.getIntPtrConstant(0));
4922}
4923
Bill Wendling8b8a6362009-01-17 03:56:04 +00004924// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
4925SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
Dale Johannesen6f38cb62009-02-07 19:59:05 +00004926 DebugLoc dl = Op.getDebugLoc();
Bill Wendling8b8a6362009-01-17 03:56:04 +00004927 // FP constant to bias correct the final result.
4928 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
4929 MVT::f64);
4930
4931 // Load the 32-bit value into an XMM register.
Dale Johannesenace16102009-02-03 19:33:06 +00004932 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4933 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Bill Wendling8b8a6362009-01-17 03:56:04 +00004934 Op.getOperand(0),
4935 DAG.getIntPtrConstant(0)));
4936
Dale Johannesenace16102009-02-03 19:33:06 +00004937 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
4938 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
Bill Wendling8b8a6362009-01-17 03:56:04 +00004939 DAG.getIntPtrConstant(0));
4940
4941 // Or the load with the bias.
Dale Johannesenace16102009-02-03 19:33:06 +00004942 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
4943 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
4944 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
Evan Cheng50c3dfe2009-01-19 08:19:57 +00004945 MVT::v2f64, Load)),
Dale Johannesenace16102009-02-03 19:33:06 +00004946 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
4947 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
Evan Cheng50c3dfe2009-01-19 08:19:57 +00004948 MVT::v2f64, Bias)));
Dale Johannesenace16102009-02-03 19:33:06 +00004949 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
4950 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
Bill Wendling8b8a6362009-01-17 03:56:04 +00004951 DAG.getIntPtrConstant(0));
4952
4953 // Subtract the bias.
Dale Johannesenace16102009-02-03 19:33:06 +00004954 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
Bill Wendling8b8a6362009-01-17 03:56:04 +00004955
4956 // Handle final rounding.
Bill Wendling030939c2009-01-17 07:40:19 +00004957 MVT DestVT = Op.getValueType();
4958
4959 if (DestVT.bitsLT(MVT::f64)) {
Dale Johannesenace16102009-02-03 19:33:06 +00004960 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
Bill Wendling030939c2009-01-17 07:40:19 +00004961 DAG.getIntPtrConstant(0));
4962 } else if (DestVT.bitsGT(MVT::f64)) {
Dale Johannesenace16102009-02-03 19:33:06 +00004963 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
Bill Wendling030939c2009-01-17 07:40:19 +00004964 }
4965
4966 // Handle final rounding.
4967 return Sub;
Bill Wendling8b8a6362009-01-17 03:56:04 +00004968}
4969
4970SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
Evan Chenga06ec9e2009-01-19 08:08:22 +00004971 SDValue N0 = Op.getOperand(0);
Dale Johannesen6f38cb62009-02-07 19:59:05 +00004972 DebugLoc dl = Op.getDebugLoc();
Bill Wendling8b8a6362009-01-17 03:56:04 +00004973
Evan Chenga06ec9e2009-01-19 08:08:22 +00004974 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
4975 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
4976 // the optimization here.
4977 if (DAG.SignBitIsZero(N0))
Dale Johannesenace16102009-02-03 19:33:06 +00004978 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
Evan Chenga06ec9e2009-01-19 08:08:22 +00004979
4980 MVT SrcVT = N0.getValueType();
Bill Wendling8b8a6362009-01-17 03:56:04 +00004981 if (SrcVT == MVT::i64) {
Eli Friedman36df4992009-05-27 00:47:34 +00004982 // We only handle SSE2 f64 target here; caller can expand the rest.
Bill Wendling8b8a6362009-01-17 03:56:04 +00004983 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
Daniel Dunbar82205572009-05-26 21:27:02 +00004984 return SDValue();
Bill Wendling030939c2009-01-17 07:40:19 +00004985
Bill Wendling8b8a6362009-01-17 03:56:04 +00004986 return LowerUINT_TO_FP_i64(Op, DAG);
Eli Friedman948e95a2009-05-23 09:59:16 +00004987 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
Bill Wendling8b8a6362009-01-17 03:56:04 +00004988 return LowerUINT_TO_FP_i32(Op, DAG);
4989 }
4990
Eli Friedman948e95a2009-05-23 09:59:16 +00004991 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
4992
4993 // Make a 64-bit buffer, and use it to build an FILD.
4994 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
4995 SDValue WordOff = DAG.getConstant(4, getPointerTy());
4996 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
4997 getPointerTy(), StackSlot, WordOff);
4998 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
4999 StackSlot, NULL, 0);
5000 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5001 OffsetSlot, NULL, 0);
5002 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
Bill Wendling8b8a6362009-01-17 03:56:04 +00005003}
5004
Dan Gohman475871a2008-07-27 21:46:04 +00005005std::pair<SDValue,SDValue> X86TargetLowering::
Eli Friedman948e95a2009-05-23 09:59:16 +00005006FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
Dale Johannesen6f38cb62009-02-07 19:59:05 +00005007 DebugLoc dl = Op.getDebugLoc();
Eli Friedman948e95a2009-05-23 09:59:16 +00005008
5009 MVT DstTy = Op.getValueType();
5010
5011 if (!IsSigned) {
5012 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5013 DstTy = MVT::i64;
5014 }
5015
5016 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5017 DstTy.getSimpleVT() >= MVT::i16 &&
Evan Cheng0db9fe62006-04-25 20:13:52 +00005018 "Unknown FP_TO_SINT to lower!");
Evan Cheng0db9fe62006-04-25 20:13:52 +00005019
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00005020 // These are really Legal.
Eli Friedman948e95a2009-05-23 09:59:16 +00005021 if (DstTy == MVT::i32 &&
Chris Lattner78631162008-01-16 06:24:21 +00005022 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
Dan Gohman475871a2008-07-27 21:46:04 +00005023 return std::make_pair(SDValue(), SDValue());
Dale Johannesen73328d12007-09-19 23:55:34 +00005024 if (Subtarget->is64Bit() &&
Eli Friedman948e95a2009-05-23 09:59:16 +00005025 DstTy == MVT::i64 &&
Eli Friedman36df4992009-05-27 00:47:34 +00005026 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
Dan Gohman475871a2008-07-27 21:46:04 +00005027 return std::make_pair(SDValue(), SDValue());
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00005028
Evan Cheng87c89352007-10-15 20:11:21 +00005029 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5030 // stack slot.
5031 MachineFunction &MF = DAG.getMachineFunction();
Eli Friedman948e95a2009-05-23 09:59:16 +00005032 unsigned MemSize = DstTy.getSizeInBits()/8;
Evan Cheng87c89352007-10-15 20:11:21 +00005033 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
Dan Gohman475871a2008-07-27 21:46:04 +00005034 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
Eli Friedman948e95a2009-05-23 09:59:16 +00005035
Evan Cheng0db9fe62006-04-25 20:13:52 +00005036 unsigned Opc;
Eli Friedman948e95a2009-05-23 09:59:16 +00005037 switch (DstTy.getSimpleVT()) {
Chris Lattner27a6c732007-11-24 07:07:01 +00005038 default: assert(0 && "Invalid FP_TO_SINT to lower!");
5039 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5040 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5041 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
Evan Cheng0db9fe62006-04-25 20:13:52 +00005042 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00005043
Dan Gohman475871a2008-07-27 21:46:04 +00005044 SDValue Chain = DAG.getEntryNode();
5045 SDValue Value = Op.getOperand(0);
Chris Lattner78631162008-01-16 06:24:21 +00005046 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
Eli Friedman948e95a2009-05-23 09:59:16 +00005047 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
Dale Johannesenace16102009-02-03 19:33:06 +00005048 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
Dan Gohmana54cf172008-07-11 22:44:52 +00005049 PseudoSourceValue::getFixedStack(SSFI), 0);
Dale Johannesen849f2142007-07-03 00:53:03 +00005050 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
Dan Gohman475871a2008-07-27 21:46:04 +00005051 SDValue Ops[] = {
Chris Lattner5a88b832007-02-25 07:10:00 +00005052 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5053 };
Dale Johannesenace16102009-02-03 19:33:06 +00005054 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005055 Chain = Value.getValue(1);
5056 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5057 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5058 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00005059
Evan Cheng0db9fe62006-04-25 20:13:52 +00005060 // Build the FP_TO_INT*_IN_MEM
Dan Gohman475871a2008-07-27 21:46:04 +00005061 SDValue Ops[] = { Chain, Value, StackSlot };
Dale Johannesenace16102009-02-03 19:33:06 +00005062 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
Evan Chengd9558e02006-01-06 00:43:03 +00005063
Chris Lattner27a6c732007-11-24 07:07:01 +00005064 return std::make_pair(FIST, StackSlot);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005065}
5066
Dan Gohman475871a2008-07-27 21:46:04 +00005067SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
Eli Friedman23ef1052009-06-06 03:57:58 +00005068 if (Op.getValueType().isVector()) {
5069 if (Op.getValueType() == MVT::v2i32 &&
5070 Op.getOperand(0).getValueType() == MVT::v2f64) {
5071 return Op;
5072 }
5073 return SDValue();
5074 }
5075
Eli Friedman948e95a2009-05-23 09:59:16 +00005076 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
Dan Gohman475871a2008-07-27 21:46:04 +00005077 SDValue FIST = Vals.first, StackSlot = Vals.second;
Eli Friedman36df4992009-05-27 00:47:34 +00005078 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5079 if (FIST.getNode() == 0) return Op;
Scott Michelfdc40a02009-02-17 22:15:04 +00005080
Chris Lattner27a6c732007-11-24 07:07:01 +00005081 // Load the result.
Dale Johannesen6f38cb62009-02-07 19:59:05 +00005082 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
Dale Johannesenace16102009-02-03 19:33:06 +00005083 FIST, StackSlot, NULL, 0);
Chris Lattner27a6c732007-11-24 07:07:01 +00005084}
5085
Eli Friedman948e95a2009-05-23 09:59:16 +00005086SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5087 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5088 SDValue FIST = Vals.first, StackSlot = Vals.second;
5089 assert(FIST.getNode() && "Unexpected failure");
5090
5091 // Load the result.
5092 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5093 FIST, StackSlot, NULL, 0);
5094}
5095
Dan Gohman475871a2008-07-27 21:46:04 +00005096SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
Dale Johannesen6f38cb62009-02-07 19:59:05 +00005097 DebugLoc dl = Op.getDebugLoc();
Duncan Sands83ec4b62008-06-06 12:08:01 +00005098 MVT VT = Op.getValueType();
5099 MVT EltVT = VT;
5100 if (VT.isVector())
5101 EltVT = VT.getVectorElementType();
Evan Cheng0db9fe62006-04-25 20:13:52 +00005102 std::vector<Constant*> CV;
Dan Gohman20382522007-07-10 00:05:58 +00005103 if (EltVT == MVT::f64) {
Chris Lattner02a260a2008-04-20 00:41:09 +00005104 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
Dan Gohman20382522007-07-10 00:05:58 +00005105 CV.push_back(C);
5106 CV.push_back(C);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005107 } else {
Chris Lattner02a260a2008-04-20 00:41:09 +00005108 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
Dan Gohman20382522007-07-10 00:05:58 +00005109 CV.push_back(C);
5110 CV.push_back(C);
5111 CV.push_back(C);
5112 CV.push_back(C);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005113 }
Dan Gohmand3006222007-07-27 17:16:43 +00005114 Constant *C = ConstantVector::get(CV);
Evan Cheng1606e8e2009-03-13 07:51:59 +00005115 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
Dale Johannesenace16102009-02-03 19:33:06 +00005116 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
Dan Gohman3069b872008-02-07 18:41:25 +00005117 PseudoSourceValue::getConstantPool(), 0,
Dan Gohmand3006222007-07-27 17:16:43 +00005118 false, 16);
Dale Johannesenace16102009-02-03 19:33:06 +00005119 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005120}
5121
Dan Gohman475871a2008-07-27 21:46:04 +00005122SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
Dale Johannesen6f38cb62009-02-07 19:59:05 +00005123 DebugLoc dl = Op.getDebugLoc();
Duncan Sands83ec4b62008-06-06 12:08:01 +00005124 MVT VT = Op.getValueType();
5125 MVT EltVT = VT;
Evan Chengd4d01b72007-07-19 23:36:01 +00005126 unsigned EltNum = 1;
Duncan Sands83ec4b62008-06-06 12:08:01 +00005127 if (VT.isVector()) {
5128 EltVT = VT.getVectorElementType();
5129 EltNum = VT.getVectorNumElements();
Evan Chengd4d01b72007-07-19 23:36:01 +00005130 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00005131 std::vector<Constant*> CV;
Dan Gohman20382522007-07-10 00:05:58 +00005132 if (EltVT == MVT::f64) {
Chris Lattner02a260a2008-04-20 00:41:09 +00005133 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
Dan Gohman20382522007-07-10 00:05:58 +00005134 CV.push_back(C);
5135 CV.push_back(C);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005136 } else {
Chris Lattner02a260a2008-04-20 00:41:09 +00005137 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
Dan Gohman20382522007-07-10 00:05:58 +00005138 CV.push_back(C);
5139 CV.push_back(C);
5140 CV.push_back(C);
5141 CV.push_back(C);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005142 }
Dan Gohmand3006222007-07-27 17:16:43 +00005143 Constant *C = ConstantVector::get(CV);
Evan Cheng1606e8e2009-03-13 07:51:59 +00005144 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
Dale Johannesenace16102009-02-03 19:33:06 +00005145 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
Dan Gohman3069b872008-02-07 18:41:25 +00005146 PseudoSourceValue::getConstantPool(), 0,
Dan Gohmand3006222007-07-27 17:16:43 +00005147 false, 16);
Duncan Sands83ec4b62008-06-06 12:08:01 +00005148 if (VT.isVector()) {
Dale Johannesenace16102009-02-03 19:33:06 +00005149 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5150 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
Scott Michelfdc40a02009-02-17 22:15:04 +00005151 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
Dale Johannesenace16102009-02-03 19:33:06 +00005152 Op.getOperand(0)),
5153 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
Evan Chengd4d01b72007-07-19 23:36:01 +00005154 } else {
Dale Johannesenace16102009-02-03 19:33:06 +00005155 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
Evan Chengd4d01b72007-07-19 23:36:01 +00005156 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00005157}
5158
Dan Gohman475871a2008-07-27 21:46:04 +00005159SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5160 SDValue Op0 = Op.getOperand(0);
5161 SDValue Op1 = Op.getOperand(1);
Dale Johannesen6f38cb62009-02-07 19:59:05 +00005162 DebugLoc dl = Op.getDebugLoc();
Duncan Sands83ec4b62008-06-06 12:08:01 +00005163 MVT VT = Op.getValueType();
5164 MVT SrcVT = Op1.getValueType();
Evan Cheng73d6cf12007-01-05 21:37:56 +00005165
5166 // If second operand is smaller, extend it first.
Duncan Sands8e4eb092008-06-08 20:54:56 +00005167 if (SrcVT.bitsLT(VT)) {
Dale Johannesenace16102009-02-03 19:33:06 +00005168 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
Evan Cheng73d6cf12007-01-05 21:37:56 +00005169 SrcVT = VT;
5170 }
Dale Johannesen61c7ef32007-10-21 01:07:44 +00005171 // And if it is bigger, shrink it first.
Duncan Sands8e4eb092008-06-08 20:54:56 +00005172 if (SrcVT.bitsGT(VT)) {
Dale Johannesenace16102009-02-03 19:33:06 +00005173 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
Dale Johannesen61c7ef32007-10-21 01:07:44 +00005174 SrcVT = VT;
Dale Johannesen61c7ef32007-10-21 01:07:44 +00005175 }
5176
5177 // At this point the operands and the result should have the same
5178 // type, and that won't be f80 since that is not custom lowered.
Evan Cheng73d6cf12007-01-05 21:37:56 +00005179
Evan Cheng68c47cb2007-01-05 07:55:56 +00005180 // First get the sign bit of second operand.
5181 std::vector<Constant*> CV;
5182 if (SrcVT == MVT::f64) {
Chris Lattner02a260a2008-04-20 00:41:09 +00005183 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
5184 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
Evan Cheng68c47cb2007-01-05 07:55:56 +00005185 } else {
Chris Lattner02a260a2008-04-20 00:41:09 +00005186 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
5187 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5188 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5189 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
Evan Cheng68c47cb2007-01-05 07:55:56 +00005190 }
Dan Gohmand3006222007-07-27 17:16:43 +00005191 Constant *C = ConstantVector::get(CV);
Evan Cheng1606e8e2009-03-13 07:51:59 +00005192 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
Dale Johannesenace16102009-02-03 19:33:06 +00005193 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
Dan Gohman3069b872008-02-07 18:41:25 +00005194 PseudoSourceValue::getConstantPool(), 0,
Dan Gohmand3006222007-07-27 17:16:43 +00005195 false, 16);
Dale Johannesenace16102009-02-03 19:33:06 +00005196 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
Evan Cheng68c47cb2007-01-05 07:55:56 +00005197
5198 // Shift sign bit right or left if the two operands have different types.
Duncan Sands8e4eb092008-06-08 20:54:56 +00005199 if (SrcVT.bitsGT(VT)) {
Evan Cheng68c47cb2007-01-05 07:55:56 +00005200 // Op0 is MVT::f32, Op1 is MVT::f64.
Dale Johannesenace16102009-02-03 19:33:06 +00005201 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5202 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
Evan Cheng68c47cb2007-01-05 07:55:56 +00005203 DAG.getConstant(32, MVT::i32));
Dale Johannesenace16102009-02-03 19:33:06 +00005204 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5205 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
Chris Lattner0bd48932008-01-17 07:00:52 +00005206 DAG.getIntPtrConstant(0));
Evan Cheng68c47cb2007-01-05 07:55:56 +00005207 }
5208
Evan Cheng73d6cf12007-01-05 21:37:56 +00005209 // Clear first operand sign bit.
5210 CV.clear();
5211 if (VT == MVT::f64) {
Chris Lattner02a260a2008-04-20 00:41:09 +00005212 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
5213 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
Evan Cheng73d6cf12007-01-05 21:37:56 +00005214 } else {
Chris Lattner02a260a2008-04-20 00:41:09 +00005215 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
5216 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5217 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5218 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
Evan Cheng73d6cf12007-01-05 21:37:56 +00005219 }
Dan Gohmand3006222007-07-27 17:16:43 +00005220 C = ConstantVector::get(CV);
Evan Cheng1606e8e2009-03-13 07:51:59 +00005221 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
Dale Johannesenace16102009-02-03 19:33:06 +00005222 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
Dan Gohman3069b872008-02-07 18:41:25 +00005223 PseudoSourceValue::getConstantPool(), 0,
Dan Gohmand3006222007-07-27 17:16:43 +00005224 false, 16);
Dale Johannesenace16102009-02-03 19:33:06 +00005225 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
Evan Cheng73d6cf12007-01-05 21:37:56 +00005226
5227 // Or the value with the sign bit.
Dale Johannesenace16102009-02-03 19:33:06 +00005228 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
Evan Cheng68c47cb2007-01-05 07:55:56 +00005229}
5230
Dan Gohman076aee32009-03-04 19:44:21 +00005231/// Emit nodes that will be selected as "test Op0,Op0", or something
5232/// equivalent.
Dan Gohman31125812009-03-07 01:58:32 +00005233SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5234 SelectionDAG &DAG) {
Dan Gohman076aee32009-03-04 19:44:21 +00005235 DebugLoc dl = Op.getDebugLoc();
5236
Dan Gohman31125812009-03-07 01:58:32 +00005237 // CF and OF aren't always set the way we want. Determine which
5238 // of these we need.
5239 bool NeedCF = false;
5240 bool NeedOF = false;
5241 switch (X86CC) {
5242 case X86::COND_A: case X86::COND_AE:
5243 case X86::COND_B: case X86::COND_BE:
5244 NeedCF = true;
5245 break;
5246 case X86::COND_G: case X86::COND_GE:
5247 case X86::COND_L: case X86::COND_LE:
5248 case X86::COND_O: case X86::COND_NO:
5249 NeedOF = true;
5250 break;
5251 default: break;
5252 }
5253
Dan Gohman076aee32009-03-04 19:44:21 +00005254 // See if we can use the EFLAGS value from the operand instead of
Dan Gohman31125812009-03-07 01:58:32 +00005255 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5256 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5257 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
Dan Gohman076aee32009-03-04 19:44:21 +00005258 unsigned Opcode = 0;
Dan Gohman51bb4742009-03-05 21:29:28 +00005259 unsigned NumOperands = 0;
Dan Gohman076aee32009-03-04 19:44:21 +00005260 switch (Op.getNode()->getOpcode()) {
5261 case ISD::ADD:
5262 // Due to an isel shortcoming, be conservative if this add is likely to
5263 // be selected as part of a load-modify-store instruction. When the root
5264 // node in a match is a store, isel doesn't know how to remap non-chain
5265 // non-flag uses of other nodes in the match, such as the ADD in this
5266 // case. This leads to the ADD being left around and reselected, with
5267 // the result being two adds in the output.
5268 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5269 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5270 if (UI->getOpcode() == ISD::STORE)
5271 goto default_case;
Dan Gohman076aee32009-03-04 19:44:21 +00005272 if (ConstantSDNode *C =
Dan Gohman4bfcf2a2009-03-05 19:32:48 +00005273 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5274 // An add of one will be selected as an INC.
Dan Gohman076aee32009-03-04 19:44:21 +00005275 if (C->getAPIntValue() == 1) {
5276 Opcode = X86ISD::INC;
Dan Gohman51bb4742009-03-05 21:29:28 +00005277 NumOperands = 1;
Dan Gohman076aee32009-03-04 19:44:21 +00005278 break;
5279 }
Dan Gohman4bfcf2a2009-03-05 19:32:48 +00005280 // An add of negative one (subtract of one) will be selected as a DEC.
5281 if (C->getAPIntValue().isAllOnesValue()) {
5282 Opcode = X86ISD::DEC;
Dan Gohman51bb4742009-03-05 21:29:28 +00005283 NumOperands = 1;
Dan Gohman4bfcf2a2009-03-05 19:32:48 +00005284 break;
5285 }
5286 }
Dan Gohman076aee32009-03-04 19:44:21 +00005287 // Otherwise use a regular EFLAGS-setting add.
5288 Opcode = X86ISD::ADD;
Dan Gohman51bb4742009-03-05 21:29:28 +00005289 NumOperands = 2;
Dan Gohman076aee32009-03-04 19:44:21 +00005290 break;
5291 case ISD::SUB:
5292 // Due to the ISEL shortcoming noted above, be conservative if this sub is
5293 // likely to be selected as part of a load-modify-store instruction.
5294 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5295 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5296 if (UI->getOpcode() == ISD::STORE)
5297 goto default_case;
Dan Gohman076aee32009-03-04 19:44:21 +00005298 // Otherwise use a regular EFLAGS-setting sub.
5299 Opcode = X86ISD::SUB;
Dan Gohman51bb4742009-03-05 21:29:28 +00005300 NumOperands = 2;
Dan Gohman076aee32009-03-04 19:44:21 +00005301 break;
5302 case X86ISD::ADD:
5303 case X86ISD::SUB:
5304 case X86ISD::INC:
5305 case X86ISD::DEC:
5306 return SDValue(Op.getNode(), 1);
5307 default:
5308 default_case:
5309 break;
5310 }
5311 if (Opcode != 0) {
Dan Gohmanfc166572009-04-09 23:54:40 +00005312 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
Dan Gohman076aee32009-03-04 19:44:21 +00005313 SmallVector<SDValue, 4> Ops;
Dan Gohman31125812009-03-07 01:58:32 +00005314 for (unsigned i = 0; i != NumOperands; ++i)
Dan Gohman076aee32009-03-04 19:44:21 +00005315 Ops.push_back(Op.getOperand(i));
Dan Gohmanfc166572009-04-09 23:54:40 +00005316 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
Dan Gohman076aee32009-03-04 19:44:21 +00005317 DAG.ReplaceAllUsesWith(Op, New);
5318 return SDValue(New.getNode(), 1);
5319 }
5320 }
5321
5322 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5323 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5324 DAG.getConstant(0, Op.getValueType()));
5325}
5326
5327/// Emit nodes that will be selected as "cmp Op0,Op1", or something
5328/// equivalent.
Dan Gohman31125812009-03-07 01:58:32 +00005329SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5330 SelectionDAG &DAG) {
Dan Gohman076aee32009-03-04 19:44:21 +00005331 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5332 if (C->getAPIntValue() == 0)
Dan Gohman31125812009-03-07 01:58:32 +00005333 return EmitTest(Op0, X86CC, DAG);
Dan Gohman076aee32009-03-04 19:44:21 +00005334
5335 DebugLoc dl = Op0.getDebugLoc();
5336 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5337}
5338
Dan Gohman475871a2008-07-27 21:46:04 +00005339SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
Evan Cheng0488db92007-09-25 01:57:46 +00005340 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
Dan Gohman475871a2008-07-27 21:46:04 +00005341 SDValue Op0 = Op.getOperand(0);
5342 SDValue Op1 = Op.getOperand(1);
Dale Johannesen6f38cb62009-02-07 19:59:05 +00005343 DebugLoc dl = Op.getDebugLoc();
Chris Lattnere55484e2008-12-25 05:34:37 +00005344 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
Scott Michelfdc40a02009-02-17 22:15:04 +00005345
Dan Gohmane5af2d32009-01-29 01:59:02 +00005346 // Lower (X & (1 << N)) == 0 to BT(X, N).
5347 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5348 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
Dan Gohman286575c2009-01-13 23:25:30 +00005349 if (Op0.getOpcode() == ISD::AND &&
5350 Op0.hasOneUse() &&
5351 Op1.getOpcode() == ISD::Constant &&
Dan Gohmane5af2d32009-01-29 01:59:02 +00005352 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
Chris Lattnere55484e2008-12-25 05:34:37 +00005353 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +00005354 SDValue LHS, RHS;
5355 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5356 if (ConstantSDNode *Op010C =
5357 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5358 if (Op010C->getZExtValue() == 1) {
5359 LHS = Op0.getOperand(0);
5360 RHS = Op0.getOperand(1).getOperand(1);
5361 }
5362 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5363 if (ConstantSDNode *Op000C =
5364 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5365 if (Op000C->getZExtValue() == 1) {
5366 LHS = Op0.getOperand(1);
5367 RHS = Op0.getOperand(0).getOperand(1);
5368 }
5369 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5370 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5371 SDValue AndLHS = Op0.getOperand(0);
5372 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5373 LHS = AndLHS.getOperand(0);
5374 RHS = AndLHS.getOperand(1);
5375 }
5376 }
Evan Cheng0488db92007-09-25 01:57:46 +00005377
Dan Gohmane5af2d32009-01-29 01:59:02 +00005378 if (LHS.getNode()) {
Chris Lattnere55484e2008-12-25 05:34:37 +00005379 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5380 // instruction. Since the shift amount is in-range-or-undefined, we know
5381 // that doing a bittest on the i16 value is ok. We extend to i32 because
5382 // the encoding for the i16 version is larger than the i32 version.
5383 if (LHS.getValueType() == MVT::i8)
Dale Johannesenace16102009-02-03 19:33:06 +00005384 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
Chris Lattnere55484e2008-12-25 05:34:37 +00005385
5386 // If the operand types disagree, extend the shift amount to match. Since
5387 // BT ignores high bits (like shifts) we can use anyextend.
5388 if (LHS.getValueType() != RHS.getValueType())
Dale Johannesenace16102009-02-03 19:33:06 +00005389 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
Dan Gohmane5af2d32009-01-29 01:59:02 +00005390
Dale Johannesenace16102009-02-03 19:33:06 +00005391 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
Dan Gohman653456c2009-01-07 00:15:08 +00005392 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
Dale Johannesenace16102009-02-03 19:33:06 +00005393 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
Chris Lattnere55484e2008-12-25 05:34:37 +00005394 DAG.getConstant(Cond, MVT::i8), BT);
5395 }
5396 }
5397
5398 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5399 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
Scott Michelfdc40a02009-02-17 22:15:04 +00005400
Dan Gohman31125812009-03-07 01:58:32 +00005401 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
Dale Johannesenace16102009-02-03 19:33:06 +00005402 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
Chris Lattner43287082008-12-24 00:11:37 +00005403 DAG.getConstant(X86CC, MVT::i8), Cond);
Evan Cheng0488db92007-09-25 01:57:46 +00005404}
5405
Dan Gohman475871a2008-07-27 21:46:04 +00005406SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5407 SDValue Cond;
5408 SDValue Op0 = Op.getOperand(0);
5409 SDValue Op1 = Op.getOperand(1);
5410 SDValue CC = Op.getOperand(2);
Nate Begeman30a0de92008-07-17 16:51:19 +00005411 MVT VT = Op.getValueType();
5412 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5413 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
Dale Johannesen6f38cb62009-02-07 19:59:05 +00005414 DebugLoc dl = Op.getDebugLoc();
Nate Begeman30a0de92008-07-17 16:51:19 +00005415
5416 if (isFP) {
5417 unsigned SSECC = 8;
Evan Chenge9d50352008-08-05 22:19:15 +00005418 MVT VT0 = Op0.getValueType();
5419 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5420 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
Nate Begeman30a0de92008-07-17 16:51:19 +00005421 bool Swap = false;
5422
5423 switch (SetCCOpcode) {
5424 default: break;
Nate Begemanfb8ead02008-07-25 19:05:58 +00005425 case ISD::SETOEQ:
Nate Begeman30a0de92008-07-17 16:51:19 +00005426 case ISD::SETEQ: SSECC = 0; break;
Scott Michelfdc40a02009-02-17 22:15:04 +00005427 case ISD::SETOGT:
Nate Begeman30a0de92008-07-17 16:51:19 +00005428 case ISD::SETGT: Swap = true; // Fallthrough
5429 case ISD::SETLT:
5430 case ISD::SETOLT: SSECC = 1; break;
5431 case ISD::SETOGE:
5432 case ISD::SETGE: Swap = true; // Fallthrough
5433 case ISD::SETLE:
5434 case ISD::SETOLE: SSECC = 2; break;
5435 case ISD::SETUO: SSECC = 3; break;
Nate Begemanfb8ead02008-07-25 19:05:58 +00005436 case ISD::SETUNE:
Nate Begeman30a0de92008-07-17 16:51:19 +00005437 case ISD::SETNE: SSECC = 4; break;
5438 case ISD::SETULE: Swap = true;
5439 case ISD::SETUGE: SSECC = 5; break;
5440 case ISD::SETULT: Swap = true;
5441 case ISD::SETUGT: SSECC = 6; break;
5442 case ISD::SETO: SSECC = 7; break;
5443 }
5444 if (Swap)
5445 std::swap(Op0, Op1);
5446
Nate Begemanfb8ead02008-07-25 19:05:58 +00005447 // In the two special cases we can't handle, emit two comparisons.
Nate Begeman30a0de92008-07-17 16:51:19 +00005448 if (SSECC == 8) {
Nate Begemanfb8ead02008-07-25 19:05:58 +00005449 if (SetCCOpcode == ISD::SETUEQ) {
Dan Gohman475871a2008-07-27 21:46:04 +00005450 SDValue UNORD, EQ;
Dale Johannesenace16102009-02-03 19:33:06 +00005451 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5452 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5453 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
Nate Begemanfb8ead02008-07-25 19:05:58 +00005454 }
5455 else if (SetCCOpcode == ISD::SETONE) {
Dan Gohman475871a2008-07-27 21:46:04 +00005456 SDValue ORD, NEQ;
Dale Johannesenace16102009-02-03 19:33:06 +00005457 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5458 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5459 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
Nate Begemanfb8ead02008-07-25 19:05:58 +00005460 }
5461 assert(0 && "Illegal FP comparison");
Nate Begeman30a0de92008-07-17 16:51:19 +00005462 }
5463 // Handle all other FP comparisons here.
Dale Johannesenace16102009-02-03 19:33:06 +00005464 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
Nate Begeman30a0de92008-07-17 16:51:19 +00005465 }
Scott Michelfdc40a02009-02-17 22:15:04 +00005466
Nate Begeman30a0de92008-07-17 16:51:19 +00005467 // We are handling one of the integer comparisons here. Since SSE only has
5468 // GT and EQ comparisons for integer, swapping operands and multiple
5469 // operations may be required for some comparisons.
5470 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5471 bool Swap = false, Invert = false, FlipSigns = false;
Scott Michelfdc40a02009-02-17 22:15:04 +00005472
Nate Begeman30a0de92008-07-17 16:51:19 +00005473 switch (VT.getSimpleVT()) {
5474 default: break;
5475 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5476 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5477 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5478 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5479 }
Scott Michelfdc40a02009-02-17 22:15:04 +00005480
Nate Begeman30a0de92008-07-17 16:51:19 +00005481 switch (SetCCOpcode) {
5482 default: break;
5483 case ISD::SETNE: Invert = true;
5484 case ISD::SETEQ: Opc = EQOpc; break;
5485 case ISD::SETLT: Swap = true;
5486 case ISD::SETGT: Opc = GTOpc; break;
5487 case ISD::SETGE: Swap = true;
5488 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5489 case ISD::SETULT: Swap = true;
5490 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5491 case ISD::SETUGE: Swap = true;
5492 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5493 }
5494 if (Swap)
5495 std::swap(Op0, Op1);
Scott Michelfdc40a02009-02-17 22:15:04 +00005496
Nate Begeman30a0de92008-07-17 16:51:19 +00005497 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5498 // bits of the inputs before performing those operations.
5499 if (FlipSigns) {
5500 MVT EltVT = VT.getVectorElementType();
Duncan Sandsb0d5cdd2009-02-01 18:06:53 +00005501 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5502 EltVT);
Dan Gohman475871a2008-07-27 21:46:04 +00005503 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
Evan Chenga87008d2009-02-25 22:49:59 +00005504 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5505 SignBits.size());
Dale Johannesenace16102009-02-03 19:33:06 +00005506 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5507 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
Nate Begeman30a0de92008-07-17 16:51:19 +00005508 }
Scott Michelfdc40a02009-02-17 22:15:04 +00005509
Dale Johannesenace16102009-02-03 19:33:06 +00005510 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
Nate Begeman30a0de92008-07-17 16:51:19 +00005511
5512 // If the logical-not of the result is required, perform that now.
Bob Wilson4c245462009-01-22 17:39:32 +00005513 if (Invert)
Dale Johannesenace16102009-02-03 19:33:06 +00005514 Result = DAG.getNOT(dl, Result, VT);
Bob Wilson4c245462009-01-22 17:39:32 +00005515
Nate Begeman30a0de92008-07-17 16:51:19 +00005516 return Result;
5517}
Evan Cheng0488db92007-09-25 01:57:46 +00005518
Evan Cheng370e5342008-12-03 08:38:43 +00005519// isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
Dan Gohman076aee32009-03-04 19:44:21 +00005520static bool isX86LogicalCmp(SDValue Op) {
5521 unsigned Opc = Op.getNode()->getOpcode();
5522 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
5523 return true;
5524 if (Op.getResNo() == 1 &&
5525 (Opc == X86ISD::ADD ||
5526 Opc == X86ISD::SUB ||
5527 Opc == X86ISD::SMUL ||
5528 Opc == X86ISD::UMUL ||
5529 Opc == X86ISD::INC ||
5530 Opc == X86ISD::DEC))
5531 return true;
5532
5533 return false;
Evan Cheng370e5342008-12-03 08:38:43 +00005534}
5535
Dan Gohman475871a2008-07-27 21:46:04 +00005536SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
Evan Cheng734503b2006-09-11 02:19:56 +00005537 bool addTest = true;
Dan Gohman475871a2008-07-27 21:46:04 +00005538 SDValue Cond = Op.getOperand(0);
Dale Johannesen6f38cb62009-02-07 19:59:05 +00005539 DebugLoc dl = Op.getDebugLoc();
Dan Gohman475871a2008-07-27 21:46:04 +00005540 SDValue CC;
Evan Cheng9bba8942006-01-26 02:13:10 +00005541
Evan Cheng734503b2006-09-11 02:19:56 +00005542 if (Cond.getOpcode() == ISD::SETCC)
Evan Chenge5f62042007-09-29 00:00:36 +00005543 Cond = LowerSETCC(Cond, DAG);
Evan Cheng734503b2006-09-11 02:19:56 +00005544
Evan Cheng3f41d662007-10-08 22:16:29 +00005545 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5546 // setting operand in place of the X86ISD::SETCC.
Evan Cheng734503b2006-09-11 02:19:56 +00005547 if (Cond.getOpcode() == X86ISD::SETCC) {
5548 CC = Cond.getOperand(0);
5549
Dan Gohman475871a2008-07-27 21:46:04 +00005550 SDValue Cmp = Cond.getOperand(1);
Evan Cheng734503b2006-09-11 02:19:56 +00005551 unsigned Opc = Cmp.getOpcode();
Duncan Sands83ec4b62008-06-06 12:08:01 +00005552 MVT VT = Op.getValueType();
Scott Michelfdc40a02009-02-17 22:15:04 +00005553
Evan Cheng3f41d662007-10-08 22:16:29 +00005554 bool IllegalFPCMov = false;
Duncan Sands83ec4b62008-06-06 12:08:01 +00005555 if (VT.isFloatingPoint() && !VT.isVector() &&
Chris Lattner78631162008-01-16 06:24:21 +00005556 !isScalarFPTypeInSSEReg(VT)) // FPStack?
Dan Gohman7810bfe2008-09-26 21:54:37 +00005557 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
Scott Michelfdc40a02009-02-17 22:15:04 +00005558
Chris Lattnerd1980a52009-03-12 06:52:53 +00005559 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
5560 Opc == X86ISD::BT) { // FIXME
Evan Cheng3f41d662007-10-08 22:16:29 +00005561 Cond = Cmp;
Evan Cheng0488db92007-09-25 01:57:46 +00005562 addTest = false;
5563 }
5564 }
5565
5566 if (addTest) {
5567 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
Dan Gohman31125812009-03-07 01:58:32 +00005568 Cond = EmitTest(Cond, X86::COND_NE, DAG);
Evan Cheng0488db92007-09-25 01:57:46 +00005569 }
5570
Dan Gohmanfc166572009-04-09 23:54:40 +00005571 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00005572 SmallVector<SDValue, 4> Ops;
Evan Cheng0488db92007-09-25 01:57:46 +00005573 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5574 // condition is true.
5575 Ops.push_back(Op.getOperand(2));
5576 Ops.push_back(Op.getOperand(1));
5577 Ops.push_back(CC);
5578 Ops.push_back(Cond);
Dan Gohmanfc166572009-04-09 23:54:40 +00005579 return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size());
Evan Cheng0488db92007-09-25 01:57:46 +00005580}
5581
Evan Cheng370e5342008-12-03 08:38:43 +00005582// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5583// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5584// from the AND / OR.
5585static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5586 Opc = Op.getOpcode();
5587 if (Opc != ISD::OR && Opc != ISD::AND)
5588 return false;
5589 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5590 Op.getOperand(0).hasOneUse() &&
5591 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5592 Op.getOperand(1).hasOneUse());
5593}
5594
Evan Cheng961d6d42009-02-02 08:19:07 +00005595// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5596// 1 and that the SETCC node has a single use.
Evan Cheng67ad9db2009-02-02 08:07:36 +00005597static bool isXor1OfSetCC(SDValue Op) {
5598 if (Op.getOpcode() != ISD::XOR)
5599 return false;
5600 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5601 if (N1C && N1C->getAPIntValue() == 1) {
5602 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5603 Op.getOperand(0).hasOneUse();
5604 }
5605 return false;
5606}
5607
Dan Gohman475871a2008-07-27 21:46:04 +00005608SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
Evan Cheng734503b2006-09-11 02:19:56 +00005609 bool addTest = true;
Dan Gohman475871a2008-07-27 21:46:04 +00005610 SDValue Chain = Op.getOperand(0);
5611 SDValue Cond = Op.getOperand(1);
5612 SDValue Dest = Op.getOperand(2);
Dale Johannesen6f38cb62009-02-07 19:59:05 +00005613 DebugLoc dl = Op.getDebugLoc();
Dan Gohman475871a2008-07-27 21:46:04 +00005614 SDValue CC;
Evan Cheng734503b2006-09-11 02:19:56 +00005615
Evan Cheng0db9fe62006-04-25 20:13:52 +00005616 if (Cond.getOpcode() == ISD::SETCC)
Evan Chenge5f62042007-09-29 00:00:36 +00005617 Cond = LowerSETCC(Cond, DAG);
Chris Lattnere55484e2008-12-25 05:34:37 +00005618#if 0
5619 // FIXME: LowerXALUO doesn't handle these!!
Bill Wendlingd350e022008-12-12 21:15:41 +00005620 else if (Cond.getOpcode() == X86ISD::ADD ||
5621 Cond.getOpcode() == X86ISD::SUB ||
5622 Cond.getOpcode() == X86ISD::SMUL ||
5623 Cond.getOpcode() == X86ISD::UMUL)
Bill Wendling74c37652008-12-09 22:08:41 +00005624 Cond = LowerXALUO(Cond, DAG);
Chris Lattnere55484e2008-12-25 05:34:37 +00005625#endif
Scott Michelfdc40a02009-02-17 22:15:04 +00005626
Evan Cheng3f41d662007-10-08 22:16:29 +00005627 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5628 // setting operand in place of the X86ISD::SETCC.
Evan Cheng0db9fe62006-04-25 20:13:52 +00005629 if (Cond.getOpcode() == X86ISD::SETCC) {
Evan Cheng734503b2006-09-11 02:19:56 +00005630 CC = Cond.getOperand(0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005631
Dan Gohman475871a2008-07-27 21:46:04 +00005632 SDValue Cmp = Cond.getOperand(1);
Evan Cheng734503b2006-09-11 02:19:56 +00005633 unsigned Opc = Cmp.getOpcode();
Chris Lattnere55484e2008-12-25 05:34:37 +00005634 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
Dan Gohman076aee32009-03-04 19:44:21 +00005635 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
Evan Cheng3f41d662007-10-08 22:16:29 +00005636 Cond = Cmp;
Evan Cheng0488db92007-09-25 01:57:46 +00005637 addTest = false;
Bill Wendling61edeb52008-12-02 01:06:39 +00005638 } else {
Evan Cheng370e5342008-12-03 08:38:43 +00005639 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
Bill Wendling0ea25cb2008-12-03 08:32:02 +00005640 default: break;
5641 case X86::COND_O:
Dan Gohman653456c2009-01-07 00:15:08 +00005642 case X86::COND_B:
Chris Lattnere55484e2008-12-25 05:34:37 +00005643 // These can only come from an arithmetic instruction with overflow,
5644 // e.g. SADDO, UADDO.
Bill Wendling0ea25cb2008-12-03 08:32:02 +00005645 Cond = Cond.getNode()->getOperand(1);
5646 addTest = false;
5647 break;
Bill Wendling61edeb52008-12-02 01:06:39 +00005648 }
Evan Cheng0488db92007-09-25 01:57:46 +00005649 }
Evan Cheng370e5342008-12-03 08:38:43 +00005650 } else {
5651 unsigned CondOpc;
5652 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
5653 SDValue Cmp = Cond.getOperand(0).getOperand(1);
Evan Cheng370e5342008-12-03 08:38:43 +00005654 if (CondOpc == ISD::OR) {
5655 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5656 // two branches instead of an explicit OR instruction with a
5657 // separate test.
5658 if (Cmp == Cond.getOperand(1).getOperand(1) &&
Dan Gohman076aee32009-03-04 19:44:21 +00005659 isX86LogicalCmp(Cmp)) {
Evan Cheng370e5342008-12-03 08:38:43 +00005660 CC = Cond.getOperand(0).getOperand(0);
Dale Johannesene4d209d2009-02-03 20:21:25 +00005661 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
Evan Cheng370e5342008-12-03 08:38:43 +00005662 Chain, Dest, CC, Cmp);
5663 CC = Cond.getOperand(1).getOperand(0);
5664 Cond = Cmp;
5665 addTest = false;
5666 }
5667 } else { // ISD::AND
5668 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5669 // two branches instead of an explicit AND instruction with a
5670 // separate test. However, we only do this if this block doesn't
5671 // have a fall-through edge, because this requires an explicit
5672 // jmp when the condition is false.
5673 if (Cmp == Cond.getOperand(1).getOperand(1) &&
Dan Gohman076aee32009-03-04 19:44:21 +00005674 isX86LogicalCmp(Cmp) &&
Evan Cheng370e5342008-12-03 08:38:43 +00005675 Op.getNode()->hasOneUse()) {
5676 X86::CondCode CCode =
5677 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5678 CCode = X86::GetOppositeBranchCondition(CCode);
5679 CC = DAG.getConstant(CCode, MVT::i8);
5680 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5681 // Look for an unconditional branch following this conditional branch.
5682 // We need this because we need to reverse the successors in order
5683 // to implement FCMP_OEQ.
5684 if (User.getOpcode() == ISD::BR) {
5685 SDValue FalseBB = User.getOperand(1);
5686 SDValue NewBR =
5687 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5688 assert(NewBR == User);
5689 Dest = FalseBB;
Dan Gohman279c22e2008-10-21 03:29:32 +00005690
Dale Johannesene4d209d2009-02-03 20:21:25 +00005691 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
Evan Cheng370e5342008-12-03 08:38:43 +00005692 Chain, Dest, CC, Cmp);
5693 X86::CondCode CCode =
5694 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5695 CCode = X86::GetOppositeBranchCondition(CCode);
5696 CC = DAG.getConstant(CCode, MVT::i8);
5697 Cond = Cmp;
5698 addTest = false;
5699 }
5700 }
Dan Gohman279c22e2008-10-21 03:29:32 +00005701 }
Evan Cheng67ad9db2009-02-02 08:07:36 +00005702 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
5703 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
5704 // It should be transformed during dag combiner except when the condition
5705 // is set by a arithmetics with overflow node.
5706 X86::CondCode CCode =
5707 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5708 CCode = X86::GetOppositeBranchCondition(CCode);
5709 CC = DAG.getConstant(CCode, MVT::i8);
5710 Cond = Cond.getOperand(0).getOperand(1);
5711 addTest = false;
Dan Gohman279c22e2008-10-21 03:29:32 +00005712 }
Evan Cheng0488db92007-09-25 01:57:46 +00005713 }
5714
5715 if (addTest) {
5716 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
Dan Gohman31125812009-03-07 01:58:32 +00005717 Cond = EmitTest(Cond, X86::COND_NE, DAG);
Evan Cheng0488db92007-09-25 01:57:46 +00005718 }
Dale Johannesene4d209d2009-02-03 20:21:25 +00005719 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
Dan Gohman279c22e2008-10-21 03:29:32 +00005720 Chain, Dest, CC, Cond);
Evan Cheng0488db92007-09-25 01:57:46 +00005721}
5722
Anton Korobeynikove060b532007-04-17 19:34:00 +00005723
5724// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5725// Calls to _alloca is needed to probe the stack when allocating more than 4k
5726// bytes in one go. Touching the stack at 4K increments is necessary to ensure
5727// that the guard pages used by the OS virtual memory manager are allocated in
5728// correct sequence.
Dan Gohman475871a2008-07-27 21:46:04 +00005729SDValue
5730X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00005731 SelectionDAG &DAG) {
Anton Korobeynikove060b532007-04-17 19:34:00 +00005732 assert(Subtarget->isTargetCygMing() &&
5733 "This should be used only on Cygwin/Mingw targets");
Dale Johannesen6f38cb62009-02-07 19:59:05 +00005734 DebugLoc dl = Op.getDebugLoc();
Anton Korobeynikov096b4612008-06-11 20:16:42 +00005735
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00005736 // Get the inputs.
Dan Gohman475871a2008-07-27 21:46:04 +00005737 SDValue Chain = Op.getOperand(0);
5738 SDValue Size = Op.getOperand(1);
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00005739 // FIXME: Ensure alignment here
5740
Dan Gohman475871a2008-07-27 21:46:04 +00005741 SDValue Flag;
Anton Korobeynikov096b4612008-06-11 20:16:42 +00005742
Duncan Sands83ec4b62008-06-06 12:08:01 +00005743 MVT IntPtr = getPointerTy();
5744 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00005745
Chris Lattnere563bbc2008-10-11 22:08:30 +00005746 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
Anton Korobeynikov096b4612008-06-11 20:16:42 +00005747
Dale Johannesendd64c412009-02-04 00:33:20 +00005748 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00005749 Flag = Chain.getValue(1);
5750
5751 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00005752 SDValue Ops[] = { Chain,
Bill Wendling056292f2008-09-16 21:48:12 +00005753 DAG.getTargetExternalSymbol("_alloca", IntPtr),
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00005754 DAG.getRegister(X86::EAX, IntPtr),
Anton Korobeynikov096b4612008-06-11 20:16:42 +00005755 DAG.getRegister(X86StackPtr, SPTy),
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00005756 Flag };
Dale Johannesene4d209d2009-02-03 20:21:25 +00005757 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00005758 Flag = Chain.getValue(1);
5759
Anton Korobeynikov096b4612008-06-11 20:16:42 +00005760 Chain = DAG.getCALLSEQ_END(Chain,
Chris Lattnere563bbc2008-10-11 22:08:30 +00005761 DAG.getIntPtrConstant(0, true),
5762 DAG.getIntPtrConstant(0, true),
Anton Korobeynikov096b4612008-06-11 20:16:42 +00005763 Flag);
5764
Dale Johannesendd64c412009-02-04 00:33:20 +00005765 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
Anton Korobeynikov096b4612008-06-11 20:16:42 +00005766
Dan Gohman475871a2008-07-27 21:46:04 +00005767 SDValue Ops1[2] = { Chain.getValue(0), Chain };
Dale Johannesene4d209d2009-02-03 20:21:25 +00005768 return DAG.getMergeValues(Ops1, 2, dl);
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00005769}
5770
Dan Gohman475871a2008-07-27 21:46:04 +00005771SDValue
Dale Johannesen0f502f62009-02-03 22:26:09 +00005772X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
Bill Wendling6f287b22008-09-30 21:22:07 +00005773 SDValue Chain,
5774 SDValue Dst, SDValue Src,
5775 SDValue Size, unsigned Align,
5776 const Value *DstSV,
Bill Wendling6158d842008-10-01 00:59:58 +00005777 uint64_t DstSVOff) {
Dan Gohman707e0182008-04-12 04:36:06 +00005778 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005779
Bill Wendling6f287b22008-09-30 21:22:07 +00005780 // If not DWORD aligned or size is more than the threshold, call the library.
5781 // The libc version is likely to be faster for these cases. It can use the
5782 // address value and run time information about the CPU.
Evan Cheng1887c1c2008-08-21 21:00:15 +00005783 if ((Align & 3) != 0 ||
Dan Gohman707e0182008-04-12 04:36:06 +00005784 !ConstantSize ||
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00005785 ConstantSize->getZExtValue() >
5786 getSubtarget()->getMaxInlineSizeThreshold()) {
Dan Gohman475871a2008-07-27 21:46:04 +00005787 SDValue InFlag(0, 0);
Dan Gohman68d599d2008-04-01 20:38:36 +00005788
5789 // Check to see if there is a specialized entry-point for memory zeroing.
Dan Gohman707e0182008-04-12 04:36:06 +00005790 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
Bill Wendling6f287b22008-09-30 21:22:07 +00005791
Bill Wendling6158d842008-10-01 00:59:58 +00005792 if (const char *bzeroEntry = V &&
5793 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5794 MVT IntPtr = getPointerTy();
5795 const Type *IntPtrTy = TD->getIntPtrType();
Scott Michelfdc40a02009-02-17 22:15:04 +00005796 TargetLowering::ArgListTy Args;
Bill Wendling6158d842008-10-01 00:59:58 +00005797 TargetLowering::ArgListEntry Entry;
5798 Entry.Node = Dst;
5799 Entry.Ty = IntPtrTy;
5800 Args.push_back(Entry);
5801 Entry.Node = Size;
5802 Args.push_back(Entry);
5803 std::pair<SDValue,SDValue> CallResult =
Scott Michelfdc40a02009-02-17 22:15:04 +00005804 LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
Tilmann Scheller6b61cd12009-07-03 06:44:53 +00005805 0, CallingConv::C, false,
Dale Johannesen0f502f62009-02-03 22:26:09 +00005806 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
Bill Wendling6158d842008-10-01 00:59:58 +00005807 return CallResult.second;
Dan Gohman68d599d2008-04-01 20:38:36 +00005808 }
5809
Dan Gohman707e0182008-04-12 04:36:06 +00005810 // Otherwise have the target-independent code call memset.
Dan Gohman475871a2008-07-27 21:46:04 +00005811 return SDValue();
Evan Cheng48090aa2006-03-21 23:01:21 +00005812 }
Evan Chengb9df0ca2006-03-22 02:53:00 +00005813
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00005814 uint64_t SizeVal = ConstantSize->getZExtValue();
Dan Gohman475871a2008-07-27 21:46:04 +00005815 SDValue InFlag(0, 0);
Duncan Sands83ec4b62008-06-06 12:08:01 +00005816 MVT AVT;
Dan Gohman475871a2008-07-27 21:46:04 +00005817 SDValue Count;
Dan Gohman707e0182008-04-12 04:36:06 +00005818 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005819 unsigned BytesLeft = 0;
5820 bool TwoRepStos = false;
5821 if (ValC) {
5822 unsigned ValReg;
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00005823 uint64_t Val = ValC->getZExtValue() & 255;
Evan Cheng5ced1d82006-04-06 23:23:56 +00005824
Evan Cheng0db9fe62006-04-25 20:13:52 +00005825 // If the value is a constant, then we can potentially use larger sets.
5826 switch (Align & 3) {
Evan Cheng1887c1c2008-08-21 21:00:15 +00005827 case 2: // WORD aligned
5828 AVT = MVT::i16;
5829 ValReg = X86::AX;
5830 Val = (Val << 8) | Val;
5831 break;
5832 case 0: // DWORD aligned
5833 AVT = MVT::i32;
5834 ValReg = X86::EAX;
5835 Val = (Val << 8) | Val;
5836 Val = (Val << 16) | Val;
5837 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5838 AVT = MVT::i64;
5839 ValReg = X86::RAX;
5840 Val = (Val << 32) | Val;
5841 }
5842 break;
5843 default: // Byte aligned
5844 AVT = MVT::i8;
5845 ValReg = X86::AL;
5846 Count = DAG.getIntPtrConstant(SizeVal);
5847 break;
Evan Cheng80d428c2006-04-19 22:48:17 +00005848 }
5849
Duncan Sands8e4eb092008-06-08 20:54:56 +00005850 if (AVT.bitsGT(MVT::i8)) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00005851 unsigned UBytes = AVT.getSizeInBits() / 8;
Dan Gohman707e0182008-04-12 04:36:06 +00005852 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5853 BytesLeft = SizeVal % UBytes;
Evan Cheng25ab6902006-09-08 06:48:29 +00005854 }
5855
Dale Johannesen0f502f62009-02-03 22:26:09 +00005856 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
Evan Cheng0db9fe62006-04-25 20:13:52 +00005857 InFlag);
5858 InFlag = Chain.getValue(1);
5859 } else {
5860 AVT = MVT::i8;
Dan Gohmanbcda2852008-04-16 01:32:32 +00005861 Count = DAG.getIntPtrConstant(SizeVal);
Dale Johannesen0f502f62009-02-03 22:26:09 +00005862 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005863 InFlag = Chain.getValue(1);
Evan Chengb9df0ca2006-03-22 02:53:00 +00005864 }
Evan Chengc78d3b42006-04-24 18:01:45 +00005865
Scott Michelfdc40a02009-02-17 22:15:04 +00005866 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
Dale Johannesen0f502f62009-02-03 22:26:09 +00005867 X86::ECX,
Evan Cheng25ab6902006-09-08 06:48:29 +00005868 Count, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005869 InFlag = Chain.getValue(1);
Scott Michelfdc40a02009-02-17 22:15:04 +00005870 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
Dale Johannesen0f502f62009-02-03 22:26:09 +00005871 X86::EDI,
Dan Gohman707e0182008-04-12 04:36:06 +00005872 Dst, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005873 InFlag = Chain.getValue(1);
Evan Chenga0b3afb2006-03-27 07:00:16 +00005874
Chris Lattnerd96d0722007-02-25 06:40:16 +00005875 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00005876 SmallVector<SDValue, 8> Ops;
Evan Cheng0db9fe62006-04-25 20:13:52 +00005877 Ops.push_back(Chain);
5878 Ops.push_back(DAG.getValueType(AVT));
5879 Ops.push_back(InFlag);
Dale Johannesen0f502f62009-02-03 22:26:09 +00005880 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
Evan Chengc78d3b42006-04-24 18:01:45 +00005881
Evan Cheng0db9fe62006-04-25 20:13:52 +00005882 if (TwoRepStos) {
5883 InFlag = Chain.getValue(1);
Dan Gohman707e0182008-04-12 04:36:06 +00005884 Count = Size;
Duncan Sands83ec4b62008-06-06 12:08:01 +00005885 MVT CVT = Count.getValueType();
Dale Johannesen0f502f62009-02-03 22:26:09 +00005886 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
Evan Cheng25ab6902006-09-08 06:48:29 +00005887 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
Scott Michelfdc40a02009-02-17 22:15:04 +00005888 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
Dale Johannesen0f502f62009-02-03 22:26:09 +00005889 X86::ECX,
Evan Cheng25ab6902006-09-08 06:48:29 +00005890 Left, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005891 InFlag = Chain.getValue(1);
Chris Lattnerd96d0722007-02-25 06:40:16 +00005892 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005893 Ops.clear();
5894 Ops.push_back(Chain);
5895 Ops.push_back(DAG.getValueType(MVT::i8));
5896 Ops.push_back(InFlag);
Dale Johannesen0f502f62009-02-03 22:26:09 +00005897 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00005898 } else if (BytesLeft) {
Dan Gohman707e0182008-04-12 04:36:06 +00005899 // Handle the last 1 - 7 bytes.
5900 unsigned Offset = SizeVal - BytesLeft;
Duncan Sands83ec4b62008-06-06 12:08:01 +00005901 MVT AddrVT = Dst.getValueType();
5902 MVT SizeVT = Size.getValueType();
Dan Gohman707e0182008-04-12 04:36:06 +00005903
Dale Johannesen0f502f62009-02-03 22:26:09 +00005904 Chain = DAG.getMemset(Chain, dl,
5905 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
Dan Gohman707e0182008-04-12 04:36:06 +00005906 DAG.getConstant(Offset, AddrVT)),
5907 Src,
5908 DAG.getConstant(BytesLeft, SizeVT),
Dan Gohman1f13c682008-04-28 17:15:20 +00005909 Align, DstSV, DstSVOff + Offset);
Evan Cheng386031a2006-03-24 07:29:27 +00005910 }
Evan Cheng11e15b32006-04-03 20:53:28 +00005911
Dan Gohman707e0182008-04-12 04:36:06 +00005912 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
Evan Cheng0db9fe62006-04-25 20:13:52 +00005913 return Chain;
5914}
Evan Cheng11e15b32006-04-03 20:53:28 +00005915
Dan Gohman475871a2008-07-27 21:46:04 +00005916SDValue
Dale Johannesen0f502f62009-02-03 22:26:09 +00005917X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
Evan Cheng1887c1c2008-08-21 21:00:15 +00005918 SDValue Chain, SDValue Dst, SDValue Src,
5919 SDValue Size, unsigned Align,
5920 bool AlwaysInline,
5921 const Value *DstSV, uint64_t DstSVOff,
Scott Michelfdc40a02009-02-17 22:15:04 +00005922 const Value *SrcSV, uint64_t SrcSVOff) {
Dan Gohman707e0182008-04-12 04:36:06 +00005923 // This requires the copy size to be a constant, preferrably
5924 // within a subtarget-specific limit.
5925 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5926 if (!ConstantSize)
Dan Gohman475871a2008-07-27 21:46:04 +00005927 return SDValue();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00005928 uint64_t SizeVal = ConstantSize->getZExtValue();
Dan Gohman707e0182008-04-12 04:36:06 +00005929 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
Dan Gohman475871a2008-07-27 21:46:04 +00005930 return SDValue();
Dan Gohman707e0182008-04-12 04:36:06 +00005931
Evan Cheng1887c1c2008-08-21 21:00:15 +00005932 /// If not DWORD aligned, call the library.
5933 if ((Align & 3) != 0)
5934 return SDValue();
5935
5936 // DWORD aligned
5937 MVT AVT = MVT::i32;
5938 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
Dan Gohman707e0182008-04-12 04:36:06 +00005939 AVT = MVT::i64;
Evan Cheng0db9fe62006-04-25 20:13:52 +00005940
Duncan Sands83ec4b62008-06-06 12:08:01 +00005941 unsigned UBytes = AVT.getSizeInBits() / 8;
Dan Gohman707e0182008-04-12 04:36:06 +00005942 unsigned CountVal = SizeVal / UBytes;
Dan Gohman475871a2008-07-27 21:46:04 +00005943 SDValue Count = DAG.getIntPtrConstant(CountVal);
Evan Cheng1887c1c2008-08-21 21:00:15 +00005944 unsigned BytesLeft = SizeVal % UBytes;
Evan Cheng25ab6902006-09-08 06:48:29 +00005945
Dan Gohman475871a2008-07-27 21:46:04 +00005946 SDValue InFlag(0, 0);
Scott Michelfdc40a02009-02-17 22:15:04 +00005947 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
Dale Johannesen0f502f62009-02-03 22:26:09 +00005948 X86::ECX,
Evan Cheng25ab6902006-09-08 06:48:29 +00005949 Count, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005950 InFlag = Chain.getValue(1);
Scott Michelfdc40a02009-02-17 22:15:04 +00005951 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
Dale Johannesen0f502f62009-02-03 22:26:09 +00005952 X86::EDI,
Dan Gohman707e0182008-04-12 04:36:06 +00005953 Dst, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005954 InFlag = Chain.getValue(1);
Scott Michelfdc40a02009-02-17 22:15:04 +00005955 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
Dale Johannesen0f502f62009-02-03 22:26:09 +00005956 X86::ESI,
Dan Gohman707e0182008-04-12 04:36:06 +00005957 Src, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005958 InFlag = Chain.getValue(1);
5959
Chris Lattnerd96d0722007-02-25 06:40:16 +00005960 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00005961 SmallVector<SDValue, 8> Ops;
Evan Cheng0db9fe62006-04-25 20:13:52 +00005962 Ops.push_back(Chain);
5963 Ops.push_back(DAG.getValueType(AVT));
5964 Ops.push_back(InFlag);
Dale Johannesen0f502f62009-02-03 22:26:09 +00005965 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00005966
Dan Gohman475871a2008-07-27 21:46:04 +00005967 SmallVector<SDValue, 4> Results;
Evan Cheng2749c722008-04-25 00:26:43 +00005968 Results.push_back(RepMovs);
Rafael Espindola068317b2007-09-28 12:53:01 +00005969 if (BytesLeft) {
Dan Gohman707e0182008-04-12 04:36:06 +00005970 // Handle the last 1 - 7 bytes.
5971 unsigned Offset = SizeVal - BytesLeft;
Duncan Sands83ec4b62008-06-06 12:08:01 +00005972 MVT DstVT = Dst.getValueType();
5973 MVT SrcVT = Src.getValueType();
5974 MVT SizeVT = Size.getValueType();
Scott Michelfdc40a02009-02-17 22:15:04 +00005975 Results.push_back(DAG.getMemcpy(Chain, dl,
Dale Johannesen0f502f62009-02-03 22:26:09 +00005976 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
Evan Cheng2749c722008-04-25 00:26:43 +00005977 DAG.getConstant(Offset, DstVT)),
Dale Johannesen0f502f62009-02-03 22:26:09 +00005978 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
Evan Cheng2749c722008-04-25 00:26:43 +00005979 DAG.getConstant(Offset, SrcVT)),
Dan Gohman707e0182008-04-12 04:36:06 +00005980 DAG.getConstant(BytesLeft, SizeVT),
5981 Align, AlwaysInline,
Dan Gohman1f13c682008-04-28 17:15:20 +00005982 DstSV, DstSVOff + Offset,
5983 SrcSV, SrcSVOff + Offset));
Evan Chengb067a1e2006-03-31 19:22:53 +00005984 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00005985
Scott Michelfdc40a02009-02-17 22:15:04 +00005986 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Dale Johannesen0f502f62009-02-03 22:26:09 +00005987 &Results[0], Results.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00005988}
5989
Dan Gohman475871a2008-07-27 21:46:04 +00005990SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
Dan Gohman69de1932008-02-06 22:27:42 +00005991 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Dale Johannesen6f38cb62009-02-07 19:59:05 +00005992 DebugLoc dl = Op.getDebugLoc();
Evan Cheng8b2794a2006-10-13 21:14:26 +00005993
Evan Cheng25ab6902006-09-08 06:48:29 +00005994 if (!Subtarget->is64Bit()) {
5995 // vastart just stores the address of the VarArgsFrameIndex slot into the
5996 // memory location argument.
Dan Gohman475871a2008-07-27 21:46:04 +00005997 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
Dale Johannesene4d209d2009-02-03 20:21:25 +00005998 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00005999 }
6000
6001 // __va_list_tag:
6002 // gp_offset (0 - 6 * 8)
6003 // fp_offset (48 - 48 + 8 * 16)
6004 // overflow_arg_area (point to parameters coming in memory).
6005 // reg_save_area
Dan Gohman475871a2008-07-27 21:46:04 +00006006 SmallVector<SDValue, 8> MemOps;
6007 SDValue FIN = Op.getOperand(1);
Evan Cheng25ab6902006-09-08 06:48:29 +00006008 // Store gp_offset
Dale Johannesene4d209d2009-02-03 20:21:25 +00006009 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
Evan Cheng786225a2006-10-05 23:01:46 +00006010 DAG.getConstant(VarArgsGPOffset, MVT::i32),
Dan Gohman69de1932008-02-06 22:27:42 +00006011 FIN, SV, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00006012 MemOps.push_back(Store);
6013
6014 // Store fp_offset
Scott Michelfdc40a02009-02-17 22:15:04 +00006015 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
Dale Johannesene4d209d2009-02-03 20:21:25 +00006016 FIN, DAG.getIntPtrConstant(4));
6017 Store = DAG.getStore(Op.getOperand(0), dl,
Evan Cheng786225a2006-10-05 23:01:46 +00006018 DAG.getConstant(VarArgsFPOffset, MVT::i32),
Dan Gohman69de1932008-02-06 22:27:42 +00006019 FIN, SV, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00006020 MemOps.push_back(Store);
6021
6022 // Store ptr to overflow_arg_area
Scott Michelfdc40a02009-02-17 22:15:04 +00006023 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
Dale Johannesene4d209d2009-02-03 20:21:25 +00006024 FIN, DAG.getIntPtrConstant(4));
Dan Gohman475871a2008-07-27 21:46:04 +00006025 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
Dale Johannesene4d209d2009-02-03 20:21:25 +00006026 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00006027 MemOps.push_back(Store);
6028
6029 // Store ptr to reg_save_area.
Scott Michelfdc40a02009-02-17 22:15:04 +00006030 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
Dale Johannesene4d209d2009-02-03 20:21:25 +00006031 FIN, DAG.getIntPtrConstant(8));
Dan Gohman475871a2008-07-27 21:46:04 +00006032 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
Dale Johannesene4d209d2009-02-03 20:21:25 +00006033 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00006034 MemOps.push_back(Store);
Scott Michelfdc40a02009-02-17 22:15:04 +00006035 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Dale Johannesene4d209d2009-02-03 20:21:25 +00006036 &MemOps[0], MemOps.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00006037}
6038
Dan Gohman475871a2008-07-27 21:46:04 +00006039SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
Dan Gohman9018e832008-05-10 01:26:14 +00006040 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6041 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
Dan Gohman475871a2008-07-27 21:46:04 +00006042 SDValue Chain = Op.getOperand(0);
6043 SDValue SrcPtr = Op.getOperand(1);
6044 SDValue SrcSV = Op.getOperand(2);
Dan Gohman9018e832008-05-10 01:26:14 +00006045
Torok Edwindac237e2009-07-08 20:53:28 +00006046 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
Dan Gohman475871a2008-07-27 21:46:04 +00006047 return SDValue();
Dan Gohman9018e832008-05-10 01:26:14 +00006048}
6049
Dan Gohman475871a2008-07-27 21:46:04 +00006050SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
Evan Chengae642192007-03-02 23:16:35 +00006051 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
Dan Gohman28269132008-04-18 20:55:41 +00006052 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
Dan Gohman475871a2008-07-27 21:46:04 +00006053 SDValue Chain = Op.getOperand(0);
6054 SDValue DstPtr = Op.getOperand(1);
6055 SDValue SrcPtr = Op.getOperand(2);
Dan Gohman69de1932008-02-06 22:27:42 +00006056 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6057 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
Dale Johannesen6f38cb62009-02-07 19:59:05 +00006058 DebugLoc dl = Op.getDebugLoc();
Evan Chengae642192007-03-02 23:16:35 +00006059
Dale Johannesendd64c412009-02-04 00:33:20 +00006060 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
Dan Gohman28269132008-04-18 20:55:41 +00006061 DAG.getIntPtrConstant(24), 8, false,
6062 DstSV, 0, SrcSV, 0);
Evan Chengae642192007-03-02 23:16:35 +00006063}
6064
Dan Gohman475871a2008-07-27 21:46:04 +00006065SDValue
6066X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
Dale Johannesen6f38cb62009-02-07 19:59:05 +00006067 DebugLoc dl = Op.getDebugLoc();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00006068 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00006069 switch (IntNo) {
Dan Gohman475871a2008-07-27 21:46:04 +00006070 default: return SDValue(); // Don't custom lower most intrinsics.
Evan Cheng5759f972008-05-04 09:15:50 +00006071 // Comparison intrinsics.
Evan Cheng0db9fe62006-04-25 20:13:52 +00006072 case Intrinsic::x86_sse_comieq_ss:
6073 case Intrinsic::x86_sse_comilt_ss:
6074 case Intrinsic::x86_sse_comile_ss:
6075 case Intrinsic::x86_sse_comigt_ss:
6076 case Intrinsic::x86_sse_comige_ss:
6077 case Intrinsic::x86_sse_comineq_ss:
6078 case Intrinsic::x86_sse_ucomieq_ss:
6079 case Intrinsic::x86_sse_ucomilt_ss:
6080 case Intrinsic::x86_sse_ucomile_ss:
6081 case Intrinsic::x86_sse_ucomigt_ss:
6082 case Intrinsic::x86_sse_ucomige_ss:
6083 case Intrinsic::x86_sse_ucomineq_ss:
6084 case Intrinsic::x86_sse2_comieq_sd:
6085 case Intrinsic::x86_sse2_comilt_sd:
6086 case Intrinsic::x86_sse2_comile_sd:
6087 case Intrinsic::x86_sse2_comigt_sd:
6088 case Intrinsic::x86_sse2_comige_sd:
6089 case Intrinsic::x86_sse2_comineq_sd:
6090 case Intrinsic::x86_sse2_ucomieq_sd:
6091 case Intrinsic::x86_sse2_ucomilt_sd:
6092 case Intrinsic::x86_sse2_ucomile_sd:
6093 case Intrinsic::x86_sse2_ucomigt_sd:
6094 case Intrinsic::x86_sse2_ucomige_sd:
6095 case Intrinsic::x86_sse2_ucomineq_sd: {
6096 unsigned Opc = 0;
6097 ISD::CondCode CC = ISD::SETCC_INVALID;
6098 switch (IntNo) {
6099 default: break;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006100 case Intrinsic::x86_sse_comieq_ss:
6101 case Intrinsic::x86_sse2_comieq_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00006102 Opc = X86ISD::COMI;
6103 CC = ISD::SETEQ;
6104 break;
Evan Cheng6be2c582006-04-05 23:38:46 +00006105 case Intrinsic::x86_sse_comilt_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00006106 case Intrinsic::x86_sse2_comilt_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00006107 Opc = X86ISD::COMI;
6108 CC = ISD::SETLT;
6109 break;
6110 case Intrinsic::x86_sse_comile_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00006111 case Intrinsic::x86_sse2_comile_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00006112 Opc = X86ISD::COMI;
6113 CC = ISD::SETLE;
6114 break;
6115 case Intrinsic::x86_sse_comigt_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00006116 case Intrinsic::x86_sse2_comigt_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00006117 Opc = X86ISD::COMI;
6118 CC = ISD::SETGT;
6119 break;
6120 case Intrinsic::x86_sse_comige_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00006121 case Intrinsic::x86_sse2_comige_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00006122 Opc = X86ISD::COMI;
6123 CC = ISD::SETGE;
6124 break;
6125 case Intrinsic::x86_sse_comineq_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00006126 case Intrinsic::x86_sse2_comineq_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00006127 Opc = X86ISD::COMI;
6128 CC = ISD::SETNE;
6129 break;
6130 case Intrinsic::x86_sse_ucomieq_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00006131 case Intrinsic::x86_sse2_ucomieq_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00006132 Opc = X86ISD::UCOMI;
6133 CC = ISD::SETEQ;
6134 break;
6135 case Intrinsic::x86_sse_ucomilt_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00006136 case Intrinsic::x86_sse2_ucomilt_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00006137 Opc = X86ISD::UCOMI;
6138 CC = ISD::SETLT;
6139 break;
6140 case Intrinsic::x86_sse_ucomile_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00006141 case Intrinsic::x86_sse2_ucomile_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00006142 Opc = X86ISD::UCOMI;
6143 CC = ISD::SETLE;
6144 break;
6145 case Intrinsic::x86_sse_ucomigt_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00006146 case Intrinsic::x86_sse2_ucomigt_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00006147 Opc = X86ISD::UCOMI;
6148 CC = ISD::SETGT;
6149 break;
6150 case Intrinsic::x86_sse_ucomige_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00006151 case Intrinsic::x86_sse2_ucomige_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00006152 Opc = X86ISD::UCOMI;
6153 CC = ISD::SETGE;
6154 break;
6155 case Intrinsic::x86_sse_ucomineq_ss:
6156 case Intrinsic::x86_sse2_ucomineq_sd:
6157 Opc = X86ISD::UCOMI;
6158 CC = ISD::SETNE;
6159 break;
Evan Cheng6be2c582006-04-05 23:38:46 +00006160 }
Evan Cheng734503b2006-09-11 02:19:56 +00006161
Dan Gohman475871a2008-07-27 21:46:04 +00006162 SDValue LHS = Op.getOperand(1);
6163 SDValue RHS = Op.getOperand(2);
Chris Lattner1c39d4c2008-12-24 23:53:05 +00006164 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
Dale Johannesene4d209d2009-02-03 20:21:25 +00006165 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6166 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
Evan Cheng0ac3fc22008-08-17 19:22:34 +00006167 DAG.getConstant(X86CC, MVT::i8), Cond);
Dale Johannesene4d209d2009-02-03 20:21:25 +00006168 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
Evan Cheng6be2c582006-04-05 23:38:46 +00006169 }
Evan Cheng5759f972008-05-04 09:15:50 +00006170
6171 // Fix vector shift instructions where the last operand is a non-immediate
6172 // i32 value.
6173 case Intrinsic::x86_sse2_pslli_w:
6174 case Intrinsic::x86_sse2_pslli_d:
6175 case Intrinsic::x86_sse2_pslli_q:
6176 case Intrinsic::x86_sse2_psrli_w:
6177 case Intrinsic::x86_sse2_psrli_d:
6178 case Intrinsic::x86_sse2_psrli_q:
6179 case Intrinsic::x86_sse2_psrai_w:
6180 case Intrinsic::x86_sse2_psrai_d:
6181 case Intrinsic::x86_mmx_pslli_w:
6182 case Intrinsic::x86_mmx_pslli_d:
6183 case Intrinsic::x86_mmx_pslli_q:
6184 case Intrinsic::x86_mmx_psrli_w:
6185 case Intrinsic::x86_mmx_psrli_d:
6186 case Intrinsic::x86_mmx_psrli_q:
6187 case Intrinsic::x86_mmx_psrai_w:
6188 case Intrinsic::x86_mmx_psrai_d: {
Dan Gohman475871a2008-07-27 21:46:04 +00006189 SDValue ShAmt = Op.getOperand(2);
Evan Cheng5759f972008-05-04 09:15:50 +00006190 if (isa<ConstantSDNode>(ShAmt))
Dan Gohman475871a2008-07-27 21:46:04 +00006191 return SDValue();
Evan Cheng5759f972008-05-04 09:15:50 +00006192
6193 unsigned NewIntNo = 0;
Duncan Sands83ec4b62008-06-06 12:08:01 +00006194 MVT ShAmtVT = MVT::v4i32;
Evan Cheng5759f972008-05-04 09:15:50 +00006195 switch (IntNo) {
6196 case Intrinsic::x86_sse2_pslli_w:
6197 NewIntNo = Intrinsic::x86_sse2_psll_w;
6198 break;
6199 case Intrinsic::x86_sse2_pslli_d:
6200 NewIntNo = Intrinsic::x86_sse2_psll_d;
6201 break;
6202 case Intrinsic::x86_sse2_pslli_q:
6203 NewIntNo = Intrinsic::x86_sse2_psll_q;
6204 break;
6205 case Intrinsic::x86_sse2_psrli_w:
6206 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6207 break;
6208 case Intrinsic::x86_sse2_psrli_d:
6209 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6210 break;
6211 case Intrinsic::x86_sse2_psrli_q:
6212 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6213 break;
6214 case Intrinsic::x86_sse2_psrai_w:
6215 NewIntNo = Intrinsic::x86_sse2_psra_w;
6216 break;
6217 case Intrinsic::x86_sse2_psrai_d:
6218 NewIntNo = Intrinsic::x86_sse2_psra_d;
6219 break;
6220 default: {
6221 ShAmtVT = MVT::v2i32;
6222 switch (IntNo) {
6223 case Intrinsic::x86_mmx_pslli_w:
6224 NewIntNo = Intrinsic::x86_mmx_psll_w;
6225 break;
6226 case Intrinsic::x86_mmx_pslli_d:
6227 NewIntNo = Intrinsic::x86_mmx_psll_d;
6228 break;
6229 case Intrinsic::x86_mmx_pslli_q:
6230 NewIntNo = Intrinsic::x86_mmx_psll_q;
6231 break;
6232 case Intrinsic::x86_mmx_psrli_w:
6233 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6234 break;
6235 case Intrinsic::x86_mmx_psrli_d:
6236 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6237 break;
6238 case Intrinsic::x86_mmx_psrli_q:
6239 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6240 break;
6241 case Intrinsic::x86_mmx_psrai_w:
6242 NewIntNo = Intrinsic::x86_mmx_psra_w;
6243 break;
6244 case Intrinsic::x86_mmx_psrai_d:
6245 NewIntNo = Intrinsic::x86_mmx_psra_d;
6246 break;
Torok Edwinab7c09b2009-07-08 18:01:40 +00006247 default: LLVM_UNREACHABLE("Impossible intrinsic"); // Can't reach here.
Evan Cheng5759f972008-05-04 09:15:50 +00006248 }
6249 break;
6250 }
6251 }
Duncan Sands83ec4b62008-06-06 12:08:01 +00006252 MVT VT = Op.getValueType();
Dale Johannesene4d209d2009-02-03 20:21:25 +00006253 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT,
6254 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt));
6255 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
Evan Cheng5759f972008-05-04 09:15:50 +00006256 DAG.getConstant(NewIntNo, MVT::i32),
6257 Op.getOperand(1), ShAmt);
6258 }
Evan Cheng38bcbaf2005-12-23 07:31:11 +00006259 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00006260}
Evan Cheng72261582005-12-20 06:22:03 +00006261
Dan Gohman475871a2008-07-27 21:46:04 +00006262SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
Bill Wendling64e87322009-01-16 19:25:27 +00006263 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
Dale Johannesen6f38cb62009-02-07 19:59:05 +00006264 DebugLoc dl = Op.getDebugLoc();
Bill Wendling64e87322009-01-16 19:25:27 +00006265
6266 if (Depth > 0) {
6267 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6268 SDValue Offset =
6269 DAG.getConstant(TD->getPointerSize(),
6270 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
Dale Johannesene4d209d2009-02-03 20:21:25 +00006271 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
Scott Michelfdc40a02009-02-17 22:15:04 +00006272 DAG.getNode(ISD::ADD, dl, getPointerTy(),
Dale Johannesene4d209d2009-02-03 20:21:25 +00006273 FrameAddr, Offset),
Bill Wendling64e87322009-01-16 19:25:27 +00006274 NULL, 0);
6275 }
6276
6277 // Just load the return address.
Dan Gohman475871a2008-07-27 21:46:04 +00006278 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
Scott Michelfdc40a02009-02-17 22:15:04 +00006279 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
Dale Johannesene4d209d2009-02-03 20:21:25 +00006280 RetAddrFI, NULL, 0);
Nate Begemanbcc5f362007-01-29 22:58:52 +00006281}
6282
Dan Gohman475871a2008-07-27 21:46:04 +00006283SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
Evan Cheng184793f2008-09-27 01:56:22 +00006284 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6285 MFI->setFrameAddressIsTaken(true);
6286 MVT VT = Op.getValueType();
Dale Johannesen6f38cb62009-02-07 19:59:05 +00006287 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
Evan Cheng184793f2008-09-27 01:56:22 +00006288 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6289 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
Dale Johannesendd64c412009-02-04 00:33:20 +00006290 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
Evan Cheng184793f2008-09-27 01:56:22 +00006291 while (Depth--)
Dale Johannesendd64c412009-02-04 00:33:20 +00006292 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
Evan Cheng184793f2008-09-27 01:56:22 +00006293 return FrameAddr;
Nate Begemanbcc5f362007-01-29 22:58:52 +00006294}
6295
Dan Gohman475871a2008-07-27 21:46:04 +00006296SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
Anton Korobeynikov260a6b82008-09-08 21:12:11 +00006297 SelectionDAG &DAG) {
Anton Korobeynikovbff66b02008-09-09 18:22:57 +00006298 return DAG.getIntPtrConstant(2*TD->getPointerSize());
Anton Korobeynikov2365f512007-07-14 14:06:15 +00006299}
6300
Dan Gohman475871a2008-07-27 21:46:04 +00006301SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
Anton Korobeynikov2365f512007-07-14 14:06:15 +00006302{
Anton Korobeynikov2365f512007-07-14 14:06:15 +00006303 MachineFunction &MF = DAG.getMachineFunction();
Dan Gohman475871a2008-07-27 21:46:04 +00006304 SDValue Chain = Op.getOperand(0);
6305 SDValue Offset = Op.getOperand(1);
6306 SDValue Handler = Op.getOperand(2);
Dale Johannesen6f38cb62009-02-07 19:59:05 +00006307 DebugLoc dl = Op.getDebugLoc();
Anton Korobeynikov2365f512007-07-14 14:06:15 +00006308
Anton Korobeynikovb84c1672008-09-08 21:12:47 +00006309 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6310 getPointerTy());
6311 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
Anton Korobeynikov2365f512007-07-14 14:06:15 +00006312
Dale Johannesene4d209d2009-02-03 20:21:25 +00006313 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
Anton Korobeynikovbff66b02008-09-09 18:22:57 +00006314 DAG.getIntPtrConstant(-TD->getPointerSize()));
Dale Johannesene4d209d2009-02-03 20:21:25 +00006315 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6316 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
Dale Johannesendd64c412009-02-04 00:33:20 +00006317 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
Anton Korobeynikovb84c1672008-09-08 21:12:47 +00006318 MF.getRegInfo().addLiveOut(StoreAddrReg);
Anton Korobeynikov2365f512007-07-14 14:06:15 +00006319
Dale Johannesene4d209d2009-02-03 20:21:25 +00006320 return DAG.getNode(X86ISD::EH_RETURN, dl,
Anton Korobeynikovb84c1672008-09-08 21:12:47 +00006321 MVT::Other,
6322 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
Anton Korobeynikov2365f512007-07-14 14:06:15 +00006323}
6324
Dan Gohman475871a2008-07-27 21:46:04 +00006325SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
Duncan Sandsb116fac2007-07-27 20:02:49 +00006326 SelectionDAG &DAG) {
Dan Gohman475871a2008-07-27 21:46:04 +00006327 SDValue Root = Op.getOperand(0);
6328 SDValue Trmp = Op.getOperand(1); // trampoline
6329 SDValue FPtr = Op.getOperand(2); // nested function
6330 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
Dale Johannesen6f38cb62009-02-07 19:59:05 +00006331 DebugLoc dl = Op.getDebugLoc();
Duncan Sandsb116fac2007-07-27 20:02:49 +00006332
Dan Gohman69de1932008-02-06 22:27:42 +00006333 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
Duncan Sandsb116fac2007-07-27 20:02:49 +00006334
Duncan Sands339e14f2008-01-16 22:55:25 +00006335 const X86InstrInfo *TII =
6336 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6337
Duncan Sandsb116fac2007-07-27 20:02:49 +00006338 if (Subtarget->is64Bit()) {
Dan Gohman475871a2008-07-27 21:46:04 +00006339 SDValue OutChains[6];
Duncan Sands339e14f2008-01-16 22:55:25 +00006340
6341 // Large code-model.
6342
6343 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6344 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6345
Dan Gohmanc9f5f3f2008-05-14 01:58:56 +00006346 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6347 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
Duncan Sands339e14f2008-01-16 22:55:25 +00006348
6349 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6350
6351 // Load the pointer to the nested function into R11.
6352 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
Dan Gohman475871a2008-07-27 21:46:04 +00006353 SDValue Addr = Trmp;
Dale Johannesene4d209d2009-02-03 20:21:25 +00006354 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6355 Addr, TrmpAddr, 0);
Duncan Sands339e14f2008-01-16 22:55:25 +00006356
Scott Michelfdc40a02009-02-17 22:15:04 +00006357 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
Dale Johannesene4d209d2009-02-03 20:21:25 +00006358 DAG.getConstant(2, MVT::i64));
6359 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
Duncan Sands339e14f2008-01-16 22:55:25 +00006360
6361 // Load the 'nest' parameter value into R10.
6362 // R10 is specified in X86CallingConv.td
6363 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
Scott Michelfdc40a02009-02-17 22:15:04 +00006364 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
Dale Johannesene4d209d2009-02-03 20:21:25 +00006365 DAG.getConstant(10, MVT::i64));
6366 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6367 Addr, TrmpAddr, 10);
Duncan Sands339e14f2008-01-16 22:55:25 +00006368
Scott Michelfdc40a02009-02-17 22:15:04 +00006369 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
Dale Johannesene4d209d2009-02-03 20:21:25 +00006370 DAG.getConstant(12, MVT::i64));
6371 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
Duncan Sands339e14f2008-01-16 22:55:25 +00006372
6373 // Jump to the nested function.
6374 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
Scott Michelfdc40a02009-02-17 22:15:04 +00006375 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
Dale Johannesene4d209d2009-02-03 20:21:25 +00006376 DAG.getConstant(20, MVT::i64));
6377 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6378 Addr, TrmpAddr, 20);
Duncan Sands339e14f2008-01-16 22:55:25 +00006379
6380 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
Scott Michelfdc40a02009-02-17 22:15:04 +00006381 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
Dale Johannesene4d209d2009-02-03 20:21:25 +00006382 DAG.getConstant(22, MVT::i64));
6383 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
Dan Gohman69de1932008-02-06 22:27:42 +00006384 TrmpAddr, 22);
Duncan Sands339e14f2008-01-16 22:55:25 +00006385
Dan Gohman475871a2008-07-27 21:46:04 +00006386 SDValue Ops[] =
Dale Johannesene4d209d2009-02-03 20:21:25 +00006387 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6388 return DAG.getMergeValues(Ops, 2, dl);
Duncan Sandsb116fac2007-07-27 20:02:49 +00006389 } else {
Dan Gohmanbbfb9c52008-01-31 01:01:48 +00006390 const Function *Func =
Duncan Sandsb116fac2007-07-27 20:02:49 +00006391 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6392 unsigned CC = Func->getCallingConv();
Duncan Sandsee465742007-08-29 19:01:20 +00006393 unsigned NestReg;
Duncan Sandsb116fac2007-07-27 20:02:49 +00006394
6395 switch (CC) {
6396 default:
6397 assert(0 && "Unsupported calling convention");
6398 case CallingConv::C:
Duncan Sandsb116fac2007-07-27 20:02:49 +00006399 case CallingConv::X86_StdCall: {
6400 // Pass 'nest' parameter in ECX.
6401 // Must be kept in sync with X86CallingConv.td
Duncan Sandsee465742007-08-29 19:01:20 +00006402 NestReg = X86::ECX;
Duncan Sandsb116fac2007-07-27 20:02:49 +00006403
6404 // Check that ECX wasn't needed by an 'inreg' parameter.
6405 const FunctionType *FTy = Func->getFunctionType();
Devang Patel05988662008-09-25 21:00:45 +00006406 const AttrListPtr &Attrs = Func->getAttributes();
Duncan Sandsb116fac2007-07-27 20:02:49 +00006407
Chris Lattner58d74912008-03-12 17:45:29 +00006408 if (!Attrs.isEmpty() && !Func->isVarArg()) {
Duncan Sandsb116fac2007-07-27 20:02:49 +00006409 unsigned InRegCount = 0;
6410 unsigned Idx = 1;
6411
6412 for (FunctionType::param_iterator I = FTy->param_begin(),
6413 E = FTy->param_end(); I != E; ++I, ++Idx)
Devang Patel05988662008-09-25 21:00:45 +00006414 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
Duncan Sandsb116fac2007-07-27 20:02:49 +00006415 // FIXME: should only count parameters that are lowered to integers.
Anton Korobeynikovbff66b02008-09-09 18:22:57 +00006416 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
Duncan Sandsb116fac2007-07-27 20:02:49 +00006417
6418 if (InRegCount > 2) {
Torok Edwinab7c09b2009-07-08 18:01:40 +00006419 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
Duncan Sandsb116fac2007-07-27 20:02:49 +00006420 }
6421 }
6422 break;
6423 }
6424 case CallingConv::X86_FastCall:
Duncan Sandsbf53c292008-09-10 13:22:10 +00006425 case CallingConv::Fast:
Duncan Sandsb116fac2007-07-27 20:02:49 +00006426 // Pass 'nest' parameter in EAX.
6427 // Must be kept in sync with X86CallingConv.td
Duncan Sandsee465742007-08-29 19:01:20 +00006428 NestReg = X86::EAX;
Duncan Sandsb116fac2007-07-27 20:02:49 +00006429 break;
6430 }
6431
Dan Gohman475871a2008-07-27 21:46:04 +00006432 SDValue OutChains[4];
6433 SDValue Addr, Disp;
Duncan Sandsb116fac2007-07-27 20:02:49 +00006434
Scott Michelfdc40a02009-02-17 22:15:04 +00006435 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
Dale Johannesene4d209d2009-02-03 20:21:25 +00006436 DAG.getConstant(10, MVT::i32));
6437 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
Duncan Sandsb116fac2007-07-27 20:02:49 +00006438
Duncan Sands339e14f2008-01-16 22:55:25 +00006439 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
Dan Gohmanc9f5f3f2008-05-14 01:58:56 +00006440 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
Scott Michelfdc40a02009-02-17 22:15:04 +00006441 OutChains[0] = DAG.getStore(Root, dl,
Dale Johannesene4d209d2009-02-03 20:21:25 +00006442 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
Dan Gohman69de1932008-02-06 22:27:42 +00006443 Trmp, TrmpAddr, 0);
Duncan Sandsb116fac2007-07-27 20:02:49 +00006444
Scott Michelfdc40a02009-02-17 22:15:04 +00006445 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
Dale Johannesene4d209d2009-02-03 20:21:25 +00006446 DAG.getConstant(1, MVT::i32));
6447 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
Duncan Sandsb116fac2007-07-27 20:02:49 +00006448
Duncan Sands339e14f2008-01-16 22:55:25 +00006449 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
Scott Michelfdc40a02009-02-17 22:15:04 +00006450 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
Dale Johannesene4d209d2009-02-03 20:21:25 +00006451 DAG.getConstant(5, MVT::i32));
6452 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
Dan Gohman69de1932008-02-06 22:27:42 +00006453 TrmpAddr, 5, false, 1);
Duncan Sandsb116fac2007-07-27 20:02:49 +00006454
Scott Michelfdc40a02009-02-17 22:15:04 +00006455 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
Dale Johannesene4d209d2009-02-03 20:21:25 +00006456 DAG.getConstant(6, MVT::i32));
6457 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
Duncan Sandsb116fac2007-07-27 20:02:49 +00006458
Dan Gohman475871a2008-07-27 21:46:04 +00006459 SDValue Ops[] =
Dale Johannesene4d209d2009-02-03 20:21:25 +00006460 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6461 return DAG.getMergeValues(Ops, 2, dl);
Duncan Sandsb116fac2007-07-27 20:02:49 +00006462 }
6463}
6464
Dan Gohman475871a2008-07-27 21:46:04 +00006465SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00006466 /*
6467 The rounding mode is in bits 11:10 of FPSR, and has the following
6468 settings:
6469 00 Round to nearest
6470 01 Round to -inf
6471 10 Round to +inf
6472 11 Round to 0
6473
6474 FLT_ROUNDS, on the other hand, expects the following:
6475 -1 Undefined
6476 0 Round to 0
6477 1 Round to nearest
6478 2 Round to +inf
6479 3 Round to -inf
6480
6481 To perform the conversion, we do:
6482 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6483 */
6484
6485 MachineFunction &MF = DAG.getMachineFunction();
6486 const TargetMachine &TM = MF.getTarget();
6487 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6488 unsigned StackAlignment = TFI.getStackAlignment();
Duncan Sands83ec4b62008-06-06 12:08:01 +00006489 MVT VT = Op.getValueType();
Dale Johannesen6f38cb62009-02-07 19:59:05 +00006490 DebugLoc dl = Op.getDebugLoc();
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00006491
6492 // Save FP Control Word to stack slot
6493 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
Dan Gohman475871a2008-07-27 21:46:04 +00006494 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00006495
Dale Johannesene4d209d2009-02-03 20:21:25 +00006496 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
Evan Cheng8a186ae2008-09-24 23:26:36 +00006497 DAG.getEntryNode(), StackSlot);
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00006498
6499 // Load FP Control Word from stack slot
Dale Johannesene4d209d2009-02-03 20:21:25 +00006500 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00006501
6502 // Transform as necessary
Dan Gohman475871a2008-07-27 21:46:04 +00006503 SDValue CWD1 =
Dale Johannesene4d209d2009-02-03 20:21:25 +00006504 DAG.getNode(ISD::SRL, dl, MVT::i16,
6505 DAG.getNode(ISD::AND, dl, MVT::i16,
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00006506 CWD, DAG.getConstant(0x800, MVT::i16)),
6507 DAG.getConstant(11, MVT::i8));
Dan Gohman475871a2008-07-27 21:46:04 +00006508 SDValue CWD2 =
Dale Johannesene4d209d2009-02-03 20:21:25 +00006509 DAG.getNode(ISD::SRL, dl, MVT::i16,
6510 DAG.getNode(ISD::AND, dl, MVT::i16,
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00006511 CWD, DAG.getConstant(0x400, MVT::i16)),
6512 DAG.getConstant(9, MVT::i8));
6513
Dan Gohman475871a2008-07-27 21:46:04 +00006514 SDValue RetVal =
Dale Johannesene4d209d2009-02-03 20:21:25 +00006515 DAG.getNode(ISD::AND, dl, MVT::i16,
6516 DAG.getNode(ISD::ADD, dl, MVT::i16,
6517 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00006518 DAG.getConstant(1, MVT::i16)),
6519 DAG.getConstant(3, MVT::i16));
6520
6521
Duncan Sands83ec4b62008-06-06 12:08:01 +00006522 return DAG.getNode((VT.getSizeInBits() < 16 ?
Dale Johannesenb300d2a2009-02-07 00:55:49 +00006523 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00006524}
6525
Dan Gohman475871a2008-07-27 21:46:04 +00006526SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00006527 MVT VT = Op.getValueType();
6528 MVT OpVT = VT;
6529 unsigned NumBits = VT.getSizeInBits();
Dale Johannesen6f38cb62009-02-07 19:59:05 +00006530 DebugLoc dl = Op.getDebugLoc();
Evan Cheng18efe262007-12-14 02:13:44 +00006531
6532 Op = Op.getOperand(0);
6533 if (VT == MVT::i8) {
Evan Cheng152804e2007-12-14 08:30:15 +00006534 // Zero extend to i32 since there is not an i8 bsr.
Evan Cheng18efe262007-12-14 02:13:44 +00006535 OpVT = MVT::i32;
Dale Johannesene4d209d2009-02-03 20:21:25 +00006536 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
Evan Cheng18efe262007-12-14 02:13:44 +00006537 }
Evan Cheng18efe262007-12-14 02:13:44 +00006538
Evan Cheng152804e2007-12-14 08:30:15 +00006539 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6540 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
Dale Johannesene4d209d2009-02-03 20:21:25 +00006541 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
Evan Cheng152804e2007-12-14 08:30:15 +00006542
6543 // If src is zero (i.e. bsr sets ZF), returns NumBits.
Dan Gohman475871a2008-07-27 21:46:04 +00006544 SmallVector<SDValue, 4> Ops;
Evan Cheng152804e2007-12-14 08:30:15 +00006545 Ops.push_back(Op);
6546 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6547 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6548 Ops.push_back(Op.getValue(1));
Dale Johannesene4d209d2009-02-03 20:21:25 +00006549 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
Evan Cheng152804e2007-12-14 08:30:15 +00006550
6551 // Finally xor with NumBits-1.
Dale Johannesene4d209d2009-02-03 20:21:25 +00006552 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
Evan Cheng152804e2007-12-14 08:30:15 +00006553
Evan Cheng18efe262007-12-14 02:13:44 +00006554 if (VT == MVT::i8)
Dale Johannesene4d209d2009-02-03 20:21:25 +00006555 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
Evan Cheng18efe262007-12-14 02:13:44 +00006556 return Op;
6557}
6558
Dan Gohman475871a2008-07-27 21:46:04 +00006559SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00006560 MVT VT = Op.getValueType();
6561 MVT OpVT = VT;
6562 unsigned NumBits = VT.getSizeInBits();
Dale Johannesen6f38cb62009-02-07 19:59:05 +00006563 DebugLoc dl = Op.getDebugLoc();
Evan Cheng18efe262007-12-14 02:13:44 +00006564
6565 Op = Op.getOperand(0);
6566 if (VT == MVT::i8) {
6567 OpVT = MVT::i32;
Dale Johannesene4d209d2009-02-03 20:21:25 +00006568 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
Evan Cheng18efe262007-12-14 02:13:44 +00006569 }
Evan Cheng152804e2007-12-14 08:30:15 +00006570
6571 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6572 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
Dale Johannesene4d209d2009-02-03 20:21:25 +00006573 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
Evan Cheng152804e2007-12-14 08:30:15 +00006574
6575 // If src is zero (i.e. bsf sets ZF), returns NumBits.
Dan Gohman475871a2008-07-27 21:46:04 +00006576 SmallVector<SDValue, 4> Ops;
Evan Cheng152804e2007-12-14 08:30:15 +00006577 Ops.push_back(Op);
6578 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6579 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6580 Ops.push_back(Op.getValue(1));
Dale Johannesene4d209d2009-02-03 20:21:25 +00006581 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
Evan Cheng152804e2007-12-14 08:30:15 +00006582
Evan Cheng18efe262007-12-14 02:13:44 +00006583 if (VT == MVT::i8)
Dale Johannesene4d209d2009-02-03 20:21:25 +00006584 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
Evan Cheng18efe262007-12-14 02:13:44 +00006585 return Op;
6586}
6587
Mon P Wangaf9b9522008-12-18 21:42:19 +00006588SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
6589 MVT VT = Op.getValueType();
6590 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
Dale Johannesen6f38cb62009-02-07 19:59:05 +00006591 DebugLoc dl = Op.getDebugLoc();
Scott Michelfdc40a02009-02-17 22:15:04 +00006592
Mon P Wangaf9b9522008-12-18 21:42:19 +00006593 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
6594 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
6595 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
6596 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
6597 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
6598 //
6599 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
6600 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
6601 // return AloBlo + AloBhi + AhiBlo;
6602
6603 SDValue A = Op.getOperand(0);
6604 SDValue B = Op.getOperand(1);
Scott Michelfdc40a02009-02-17 22:15:04 +00006605
Dale Johannesene4d209d2009-02-03 20:21:25 +00006606 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
Mon P Wangaf9b9522008-12-18 21:42:19 +00006607 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6608 A, DAG.getConstant(32, MVT::i32));
Dale Johannesene4d209d2009-02-03 20:21:25 +00006609 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
Mon P Wangaf9b9522008-12-18 21:42:19 +00006610 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6611 B, DAG.getConstant(32, MVT::i32));
Dale Johannesene4d209d2009-02-03 20:21:25 +00006612 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
Mon P Wangaf9b9522008-12-18 21:42:19 +00006613 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6614 A, B);
Dale Johannesene4d209d2009-02-03 20:21:25 +00006615 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
Mon P Wangaf9b9522008-12-18 21:42:19 +00006616 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6617 A, Bhi);
Dale Johannesene4d209d2009-02-03 20:21:25 +00006618 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
Mon P Wangaf9b9522008-12-18 21:42:19 +00006619 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6620 Ahi, B);
Dale Johannesene4d209d2009-02-03 20:21:25 +00006621 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
Mon P Wangaf9b9522008-12-18 21:42:19 +00006622 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6623 AloBhi, DAG.getConstant(32, MVT::i32));
Dale Johannesene4d209d2009-02-03 20:21:25 +00006624 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
Mon P Wangaf9b9522008-12-18 21:42:19 +00006625 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6626 AhiBlo, DAG.getConstant(32, MVT::i32));
Dale Johannesene4d209d2009-02-03 20:21:25 +00006627 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
6628 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
Mon P Wangaf9b9522008-12-18 21:42:19 +00006629 return Res;
6630}
6631
6632
Bill Wendling74c37652008-12-09 22:08:41 +00006633SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
6634 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
6635 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
Bill Wendling61edeb52008-12-02 01:06:39 +00006636 // looks for this combo and may remove the "setcc" instruction if the "setcc"
6637 // has only one use.
Bill Wendling3fafd932008-11-26 22:37:40 +00006638 SDNode *N = Op.getNode();
Bill Wendling61edeb52008-12-02 01:06:39 +00006639 SDValue LHS = N->getOperand(0);
6640 SDValue RHS = N->getOperand(1);
Bill Wendling74c37652008-12-09 22:08:41 +00006641 unsigned BaseOp = 0;
6642 unsigned Cond = 0;
Dale Johannesen6f38cb62009-02-07 19:59:05 +00006643 DebugLoc dl = Op.getDebugLoc();
Bill Wendling74c37652008-12-09 22:08:41 +00006644
6645 switch (Op.getOpcode()) {
6646 default: assert(0 && "Unknown ovf instruction!");
6647 case ISD::SADDO:
Dan Gohman076aee32009-03-04 19:44:21 +00006648 // A subtract of one will be selected as a INC. Note that INC doesn't
6649 // set CF, so we can't do this for UADDO.
6650 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6651 if (C->getAPIntValue() == 1) {
6652 BaseOp = X86ISD::INC;
6653 Cond = X86::COND_O;
6654 break;
6655 }
Bill Wendlingab55ebd2008-12-12 00:56:36 +00006656 BaseOp = X86ISD::ADD;
Bill Wendling74c37652008-12-09 22:08:41 +00006657 Cond = X86::COND_O;
6658 break;
6659 case ISD::UADDO:
Bill Wendlingab55ebd2008-12-12 00:56:36 +00006660 BaseOp = X86ISD::ADD;
Dan Gohman653456c2009-01-07 00:15:08 +00006661 Cond = X86::COND_B;
Bill Wendling74c37652008-12-09 22:08:41 +00006662 break;
6663 case ISD::SSUBO:
Dan Gohman076aee32009-03-04 19:44:21 +00006664 // A subtract of one will be selected as a DEC. Note that DEC doesn't
6665 // set CF, so we can't do this for USUBO.
6666 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6667 if (C->getAPIntValue() == 1) {
6668 BaseOp = X86ISD::DEC;
6669 Cond = X86::COND_O;
6670 break;
6671 }
Bill Wendlingab55ebd2008-12-12 00:56:36 +00006672 BaseOp = X86ISD::SUB;
Bill Wendling74c37652008-12-09 22:08:41 +00006673 Cond = X86::COND_O;
6674 break;
6675 case ISD::USUBO:
Bill Wendlingab55ebd2008-12-12 00:56:36 +00006676 BaseOp = X86ISD::SUB;
Dan Gohman653456c2009-01-07 00:15:08 +00006677 Cond = X86::COND_B;
Bill Wendling74c37652008-12-09 22:08:41 +00006678 break;
6679 case ISD::SMULO:
Bill Wendlingd350e022008-12-12 21:15:41 +00006680 BaseOp = X86ISD::SMUL;
Bill Wendling74c37652008-12-09 22:08:41 +00006681 Cond = X86::COND_O;
6682 break;
6683 case ISD::UMULO:
Bill Wendlingd350e022008-12-12 21:15:41 +00006684 BaseOp = X86ISD::UMUL;
Dan Gohman653456c2009-01-07 00:15:08 +00006685 Cond = X86::COND_B;
Bill Wendling74c37652008-12-09 22:08:41 +00006686 break;
6687 }
Bill Wendling3fafd932008-11-26 22:37:40 +00006688
Bill Wendling61edeb52008-12-02 01:06:39 +00006689 // Also sets EFLAGS.
6690 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
Dale Johannesene4d209d2009-02-03 20:21:25 +00006691 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
Bill Wendling3fafd932008-11-26 22:37:40 +00006692
Bill Wendling61edeb52008-12-02 01:06:39 +00006693 SDValue SetCC =
Dale Johannesene4d209d2009-02-03 20:21:25 +00006694 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
Bill Wendlingbc5e15e2008-12-10 02:01:32 +00006695 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
Bill Wendling3fafd932008-11-26 22:37:40 +00006696
Bill Wendling61edeb52008-12-02 01:06:39 +00006697 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
6698 return Sum;
Bill Wendling41ea7e72008-11-24 19:21:46 +00006699}
6700
Dan Gohman475871a2008-07-27 21:46:04 +00006701SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
Dan Gohmanfd4418f2008-06-25 16:07:49 +00006702 MVT T = Op.getValueType();
Dale Johannesen6f38cb62009-02-07 19:59:05 +00006703 DebugLoc dl = Op.getDebugLoc();
Andrew Lenhartha76e2f02008-03-04 21:13:33 +00006704 unsigned Reg = 0;
6705 unsigned size = 0;
Duncan Sands83ec4b62008-06-06 12:08:01 +00006706 switch(T.getSimpleVT()) {
6707 default:
6708 assert(false && "Invalid value type!");
Andrew Lenharth26ed8692008-03-01 21:52:34 +00006709 case MVT::i8: Reg = X86::AL; size = 1; break;
6710 case MVT::i16: Reg = X86::AX; size = 2; break;
6711 case MVT::i32: Reg = X86::EAX; size = 4; break;
Scott Michelfdc40a02009-02-17 22:15:04 +00006712 case MVT::i64:
Duncan Sands1607f052008-12-01 11:39:25 +00006713 assert(Subtarget->is64Bit() && "Node not type legal!");
6714 Reg = X86::RAX; size = 8;
Andrew Lenharthd19189e2008-03-05 01:15:49 +00006715 break;
Bill Wendling61edeb52008-12-02 01:06:39 +00006716 }
Dale Johannesendd64c412009-02-04 00:33:20 +00006717 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
Dale Johannesend18a4622008-09-11 03:12:59 +00006718 Op.getOperand(2), SDValue());
Dan Gohman475871a2008-07-27 21:46:04 +00006719 SDValue Ops[] = { cpIn.getValue(0),
Evan Cheng8a186ae2008-09-24 23:26:36 +00006720 Op.getOperand(1),
6721 Op.getOperand(3),
6722 DAG.getTargetConstant(size, MVT::i8),
6723 cpIn.getValue(1) };
Andrew Lenharth26ed8692008-03-01 21:52:34 +00006724 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Dale Johannesene4d209d2009-02-03 20:21:25 +00006725 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
Scott Michelfdc40a02009-02-17 22:15:04 +00006726 SDValue cpOut =
Dale Johannesendd64c412009-02-04 00:33:20 +00006727 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
Andrew Lenharth26ed8692008-03-01 21:52:34 +00006728 return cpOut;
6729}
6730
Duncan Sands1607f052008-12-01 11:39:25 +00006731SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
Gabor Greif327ef032008-08-28 23:19:51 +00006732 SelectionDAG &DAG) {
Duncan Sands1607f052008-12-01 11:39:25 +00006733 assert(Subtarget->is64Bit() && "Result not type legalized?");
Andrew Lenharthd19189e2008-03-05 01:15:49 +00006734 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Duncan Sands1607f052008-12-01 11:39:25 +00006735 SDValue TheChain = Op.getOperand(0);
Dale Johannesen6f38cb62009-02-07 19:59:05 +00006736 DebugLoc dl = Op.getDebugLoc();
Dale Johannesene4d209d2009-02-03 20:21:25 +00006737 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
Dale Johannesendd64c412009-02-04 00:33:20 +00006738 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
6739 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
Duncan Sands1607f052008-12-01 11:39:25 +00006740 rax.getValue(2));
Dale Johannesene4d209d2009-02-03 20:21:25 +00006741 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
Duncan Sands1607f052008-12-01 11:39:25 +00006742 DAG.getConstant(32, MVT::i8));
6743 SDValue Ops[] = {
Dale Johannesene4d209d2009-02-03 20:21:25 +00006744 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
Duncan Sands1607f052008-12-01 11:39:25 +00006745 rdx.getValue(1)
6746 };
Dale Johannesene4d209d2009-02-03 20:21:25 +00006747 return DAG.getMergeValues(Ops, 2, dl);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00006748}
6749
Dale Johannesen71d1bf52008-09-29 22:25:26 +00006750SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
6751 SDNode *Node = Op.getNode();
Dale Johannesene4d209d2009-02-03 20:21:25 +00006752 DebugLoc dl = Node->getDebugLoc();
Dale Johannesen71d1bf52008-09-29 22:25:26 +00006753 MVT T = Node->getValueType(0);
Dale Johannesene4d209d2009-02-03 20:21:25 +00006754 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
Evan Cheng242b38b2009-02-23 09:03:22 +00006755 DAG.getConstant(0, T), Node->getOperand(2));
Dale Johannesene4d209d2009-02-03 20:21:25 +00006756 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
Dan Gohman0b1d4a72008-12-23 21:37:04 +00006757 cast<AtomicSDNode>(Node)->getMemoryVT(),
Dale Johannesen71d1bf52008-09-29 22:25:26 +00006758 Node->getOperand(0),
6759 Node->getOperand(1), negOp,
6760 cast<AtomicSDNode>(Node)->getSrcValue(),
6761 cast<AtomicSDNode>(Node)->getAlignment());
Mon P Wang63307c32008-05-05 19:05:59 +00006762}
6763
Evan Cheng0db9fe62006-04-25 20:13:52 +00006764/// LowerOperation - Provide custom lowering hooks for some operations.
6765///
Dan Gohman475871a2008-07-27 21:46:04 +00006766SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00006767 switch (Op.getOpcode()) {
6768 default: assert(0 && "Should not custom lower this!");
Dan Gohman0b1d4a72008-12-23 21:37:04 +00006769 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
6770 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00006771 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6772 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6773 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6774 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6775 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6776 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6777 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00006778 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
Bill Wendling056292f2008-09-16 21:48:12 +00006779 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00006780 case ISD::SHL_PARTS:
6781 case ISD::SRA_PARTS:
6782 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
6783 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
Dale Johannesen1c15bf52008-10-21 20:50:01 +00006784 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00006785 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
Eli Friedman948e95a2009-05-23 09:59:16 +00006786 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00006787 case ISD::FABS: return LowerFABS(Op, DAG);
6788 case ISD::FNEG: return LowerFNEG(Op, DAG);
Evan Cheng68c47cb2007-01-05 07:55:56 +00006789 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
Evan Chenge5f62042007-09-29 00:00:36 +00006790 case ISD::SETCC: return LowerSETCC(Op, DAG);
Nate Begeman30a0de92008-07-17 16:51:19 +00006791 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
Evan Chenge5f62042007-09-29 00:00:36 +00006792 case ISD::SELECT: return LowerSELECT(Op, DAG);
6793 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00006794 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
Evan Cheng32fe1032006-05-25 00:59:30 +00006795 case ISD::CALL: return LowerCALL(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00006796 case ISD::RET: return LowerRET(Op, DAG);
Evan Cheng1bc78042006-04-26 01:20:17 +00006797 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00006798 case ISD::VASTART: return LowerVASTART(Op, DAG);
Dan Gohman9018e832008-05-10 01:26:14 +00006799 case ISD::VAARG: return LowerVAARG(Op, DAG);
Evan Chengae642192007-03-02 23:16:35 +00006800 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00006801 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
Nate Begemanbcc5f362007-01-29 22:58:52 +00006802 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6803 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Anton Korobeynikov2365f512007-07-14 14:06:15 +00006804 case ISD::FRAME_TO_ARGS_OFFSET:
6805 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00006806 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
Anton Korobeynikov2365f512007-07-14 14:06:15 +00006807 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
Duncan Sandsb116fac2007-07-27 20:02:49 +00006808 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
Dan Gohman1a024862008-01-31 00:41:03 +00006809 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
Evan Cheng18efe262007-12-14 02:13:44 +00006810 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6811 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
Mon P Wangaf9b9522008-12-18 21:42:19 +00006812 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
Bill Wendling74c37652008-12-09 22:08:41 +00006813 case ISD::SADDO:
6814 case ISD::UADDO:
6815 case ISD::SSUBO:
6816 case ISD::USUBO:
6817 case ISD::SMULO:
6818 case ISD::UMULO: return LowerXALUO(Op, DAG);
Duncan Sands1607f052008-12-01 11:39:25 +00006819 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00006820 }
Chris Lattner27a6c732007-11-24 07:07:01 +00006821}
6822
Duncan Sands1607f052008-12-01 11:39:25 +00006823void X86TargetLowering::
6824ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
6825 SelectionDAG &DAG, unsigned NewOp) {
6826 MVT T = Node->getValueType(0);
Dale Johannesene4d209d2009-02-03 20:21:25 +00006827 DebugLoc dl = Node->getDebugLoc();
Duncan Sands1607f052008-12-01 11:39:25 +00006828 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6829
6830 SDValue Chain = Node->getOperand(0);
6831 SDValue In1 = Node->getOperand(1);
Dale Johannesene4d209d2009-02-03 20:21:25 +00006832 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Duncan Sands1607f052008-12-01 11:39:25 +00006833 Node->getOperand(2), DAG.getIntPtrConstant(0));
Dale Johannesene4d209d2009-02-03 20:21:25 +00006834 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Duncan Sands1607f052008-12-01 11:39:25 +00006835 Node->getOperand(2), DAG.getIntPtrConstant(1));
6836 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
6837 // have a MemOperand. Pass the info through as a normal operand.
6838 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
6839 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
6840 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
Dale Johannesene4d209d2009-02-03 20:21:25 +00006841 SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5);
Duncan Sands1607f052008-12-01 11:39:25 +00006842 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
Dale Johannesene4d209d2009-02-03 20:21:25 +00006843 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
Duncan Sands1607f052008-12-01 11:39:25 +00006844 Results.push_back(Result.getValue(2));
6845}
6846
Duncan Sands126d9072008-07-04 11:47:58 +00006847/// ReplaceNodeResults - Replace a node with an illegal result type
6848/// with a new node built out of custom code.
Duncan Sands1607f052008-12-01 11:39:25 +00006849void X86TargetLowering::ReplaceNodeResults(SDNode *N,
6850 SmallVectorImpl<SDValue>&Results,
6851 SelectionDAG &DAG) {
Dale Johannesene4d209d2009-02-03 20:21:25 +00006852 DebugLoc dl = N->getDebugLoc();
Chris Lattner27a6c732007-11-24 07:07:01 +00006853 switch (N->getOpcode()) {
Duncan Sandsed294c42008-10-20 15:56:33 +00006854 default:
Duncan Sands1607f052008-12-01 11:39:25 +00006855 assert(false && "Do not know how to custom type legalize this operation!");
6856 return;
6857 case ISD::FP_TO_SINT: {
Eli Friedman948e95a2009-05-23 09:59:16 +00006858 std::pair<SDValue,SDValue> Vals =
6859 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
Duncan Sands1607f052008-12-01 11:39:25 +00006860 SDValue FIST = Vals.first, StackSlot = Vals.second;
6861 if (FIST.getNode() != 0) {
6862 MVT VT = N->getValueType(0);
6863 // Return a load from the stack slot.
Dale Johannesene4d209d2009-02-03 20:21:25 +00006864 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
Duncan Sands1607f052008-12-01 11:39:25 +00006865 }
6866 return;
6867 }
6868 case ISD::READCYCLECOUNTER: {
6869 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6870 SDValue TheChain = N->getOperand(0);
Dale Johannesene4d209d2009-02-03 20:21:25 +00006871 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
Scott Michelfdc40a02009-02-17 22:15:04 +00006872 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
Dale Johannesendd64c412009-02-04 00:33:20 +00006873 rd.getValue(1));
6874 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
Duncan Sands1607f052008-12-01 11:39:25 +00006875 eax.getValue(2));
6876 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
6877 SDValue Ops[] = { eax, edx };
Dale Johannesene4d209d2009-02-03 20:21:25 +00006878 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
Duncan Sands1607f052008-12-01 11:39:25 +00006879 Results.push_back(edx.getValue(1));
6880 return;
6881 }
Dan Gohman0b1d4a72008-12-23 21:37:04 +00006882 case ISD::ATOMIC_CMP_SWAP: {
Duncan Sands1607f052008-12-01 11:39:25 +00006883 MVT T = N->getValueType(0);
6884 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
6885 SDValue cpInL, cpInH;
Dale Johannesene4d209d2009-02-03 20:21:25 +00006886 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
Duncan Sands1607f052008-12-01 11:39:25 +00006887 DAG.getConstant(0, MVT::i32));
Dale Johannesene4d209d2009-02-03 20:21:25 +00006888 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
Duncan Sands1607f052008-12-01 11:39:25 +00006889 DAG.getConstant(1, MVT::i32));
Dale Johannesendd64c412009-02-04 00:33:20 +00006890 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
6891 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
Duncan Sands1607f052008-12-01 11:39:25 +00006892 cpInL.getValue(1));
6893 SDValue swapInL, swapInH;
Dale Johannesene4d209d2009-02-03 20:21:25 +00006894 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
Duncan Sands1607f052008-12-01 11:39:25 +00006895 DAG.getConstant(0, MVT::i32));
Dale Johannesene4d209d2009-02-03 20:21:25 +00006896 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
Duncan Sands1607f052008-12-01 11:39:25 +00006897 DAG.getConstant(1, MVT::i32));
Dale Johannesendd64c412009-02-04 00:33:20 +00006898 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
Duncan Sands1607f052008-12-01 11:39:25 +00006899 cpInH.getValue(1));
Dale Johannesendd64c412009-02-04 00:33:20 +00006900 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
Duncan Sands1607f052008-12-01 11:39:25 +00006901 swapInL.getValue(1));
6902 SDValue Ops[] = { swapInH.getValue(0),
6903 N->getOperand(1),
6904 swapInH.getValue(1) };
6905 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Dale Johannesene4d209d2009-02-03 20:21:25 +00006906 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
Dale Johannesendd64c412009-02-04 00:33:20 +00006907 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
6908 MVT::i32, Result.getValue(1));
6909 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
6910 MVT::i32, cpOutL.getValue(2));
Duncan Sands1607f052008-12-01 11:39:25 +00006911 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
Dale Johannesene4d209d2009-02-03 20:21:25 +00006912 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
Duncan Sands1607f052008-12-01 11:39:25 +00006913 Results.push_back(cpOutH.getValue(1));
6914 return;
6915 }
Dan Gohman0b1d4a72008-12-23 21:37:04 +00006916 case ISD::ATOMIC_LOAD_ADD:
Duncan Sands1607f052008-12-01 11:39:25 +00006917 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
6918 return;
Dan Gohman0b1d4a72008-12-23 21:37:04 +00006919 case ISD::ATOMIC_LOAD_AND:
Duncan Sands1607f052008-12-01 11:39:25 +00006920 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
6921 return;
Dan Gohman0b1d4a72008-12-23 21:37:04 +00006922 case ISD::ATOMIC_LOAD_NAND:
Duncan Sands1607f052008-12-01 11:39:25 +00006923 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
6924 return;
Dan Gohman0b1d4a72008-12-23 21:37:04 +00006925 case ISD::ATOMIC_LOAD_OR:
Duncan Sands1607f052008-12-01 11:39:25 +00006926 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
6927 return;
Dan Gohman0b1d4a72008-12-23 21:37:04 +00006928 case ISD::ATOMIC_LOAD_SUB:
Duncan Sands1607f052008-12-01 11:39:25 +00006929 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
6930 return;
Dan Gohman0b1d4a72008-12-23 21:37:04 +00006931 case ISD::ATOMIC_LOAD_XOR:
Duncan Sands1607f052008-12-01 11:39:25 +00006932 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
6933 return;
Dan Gohman0b1d4a72008-12-23 21:37:04 +00006934 case ISD::ATOMIC_SWAP:
Duncan Sands1607f052008-12-01 11:39:25 +00006935 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
6936 return;
Chris Lattner27a6c732007-11-24 07:07:01 +00006937 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00006938}
6939
Evan Cheng72261582005-12-20 06:22:03 +00006940const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
6941 switch (Opcode) {
6942 default: return NULL;
Evan Cheng18efe262007-12-14 02:13:44 +00006943 case X86ISD::BSF: return "X86ISD::BSF";
6944 case X86ISD::BSR: return "X86ISD::BSR";
Evan Chenge3413162006-01-09 18:33:28 +00006945 case X86ISD::SHLD: return "X86ISD::SHLD";
6946 case X86ISD::SHRD: return "X86ISD::SHRD";
Evan Chengef6ffb12006-01-31 03:14:29 +00006947 case X86ISD::FAND: return "X86ISD::FAND";
Evan Cheng68c47cb2007-01-05 07:55:56 +00006948 case X86ISD::FOR: return "X86ISD::FOR";
Evan Cheng223547a2006-01-31 22:28:30 +00006949 case X86ISD::FXOR: return "X86ISD::FXOR";
Evan Cheng68c47cb2007-01-05 07:55:56 +00006950 case X86ISD::FSRL: return "X86ISD::FSRL";
Evan Chenga3195e82006-01-12 22:54:21 +00006951 case X86ISD::FILD: return "X86ISD::FILD";
Evan Chenge3de85b2006-02-04 02:20:30 +00006952 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
Evan Cheng72261582005-12-20 06:22:03 +00006953 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
6954 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
6955 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
Evan Chengb077b842005-12-21 02:39:21 +00006956 case X86ISD::FLD: return "X86ISD::FLD";
Evan Chengd90eb7f2006-01-05 00:27:02 +00006957 case X86ISD::FST: return "X86ISD::FST";
Evan Cheng72261582005-12-20 06:22:03 +00006958 case X86ISD::CALL: return "X86ISD::CALL";
6959 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
6960 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
Dan Gohmanc7a37d42008-12-23 22:45:23 +00006961 case X86ISD::BT: return "X86ISD::BT";
Evan Cheng72261582005-12-20 06:22:03 +00006962 case X86ISD::CMP: return "X86ISD::CMP";
Evan Cheng6be2c582006-04-05 23:38:46 +00006963 case X86ISD::COMI: return "X86ISD::COMI";
6964 case X86ISD::UCOMI: return "X86ISD::UCOMI";
Evan Chengd5781fc2005-12-21 20:21:51 +00006965 case X86ISD::SETCC: return "X86ISD::SETCC";
Evan Cheng72261582005-12-20 06:22:03 +00006966 case X86ISD::CMOV: return "X86ISD::CMOV";
6967 case X86ISD::BRCOND: return "X86ISD::BRCOND";
Evan Chengb077b842005-12-21 02:39:21 +00006968 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
Evan Cheng8df346b2006-03-04 01:12:00 +00006969 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
6970 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
Evan Cheng7ccced62006-02-18 00:15:05 +00006971 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
Evan Cheng020d2e82006-02-23 20:41:18 +00006972 case X86ISD::Wrapper: return "X86ISD::Wrapper";
Chris Lattner18c59872009-06-27 04:16:01 +00006973 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
Nate Begeman14d12ca2008-02-11 04:19:36 +00006974 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
Evan Chengb067a1e2006-03-31 19:22:53 +00006975 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
Nate Begeman14d12ca2008-02-11 04:19:36 +00006976 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
6977 case X86ISD::PINSRB: return "X86ISD::PINSRB";
Evan Cheng653159f2006-03-31 21:55:24 +00006978 case X86ISD::PINSRW: return "X86ISD::PINSRW";
Nate Begemanb9a47b82009-02-23 08:49:38 +00006979 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
Evan Cheng8ca29322006-11-10 21:43:37 +00006980 case X86ISD::FMAX: return "X86ISD::FMAX";
6981 case X86ISD::FMIN: return "X86ISD::FMIN";
Dan Gohman20382522007-07-10 00:05:58 +00006982 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
6983 case X86ISD::FRCP: return "X86ISD::FRCP";
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00006984 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
Rafael Espindola094fad32009-04-08 21:14:34 +00006985 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
Anton Korobeynikov2365f512007-07-14 14:06:15 +00006986 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00006987 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00006988 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
Evan Cheng7e2ff772008-05-08 00:57:18 +00006989 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
6990 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
Dale Johannesen48c1bc22008-10-02 18:53:47 +00006991 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
6992 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
6993 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
6994 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
6995 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
6996 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
Evan Chengd880b972008-05-09 21:53:03 +00006997 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
6998 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
Evan Chengf26ffe92008-05-29 08:22:04 +00006999 case X86ISD::VSHL: return "X86ISD::VSHL";
7000 case X86ISD::VSRL: return "X86ISD::VSRL";
Nate Begeman30a0de92008-07-17 16:51:19 +00007001 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7002 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7003 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7004 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7005 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7006 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7007 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7008 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7009 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7010 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
Bill Wendlingab55ebd2008-12-12 00:56:36 +00007011 case X86ISD::ADD: return "X86ISD::ADD";
7012 case X86ISD::SUB: return "X86ISD::SUB";
Bill Wendlingd350e022008-12-12 21:15:41 +00007013 case X86ISD::SMUL: return "X86ISD::SMUL";
7014 case X86ISD::UMUL: return "X86ISD::UMUL";
Dan Gohman076aee32009-03-04 19:44:21 +00007015 case X86ISD::INC: return "X86ISD::INC";
7016 case X86ISD::DEC: return "X86ISD::DEC";
Evan Cheng73f24c92009-03-30 21:36:47 +00007017 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
Evan Cheng72261582005-12-20 06:22:03 +00007018 }
7019}
Evan Cheng3a03ebb2005-12-21 23:05:39 +00007020
Chris Lattnerc9addb72007-03-30 23:15:24 +00007021// isLegalAddressingMode - Return true if the addressing mode represented
7022// by AM is legal for this target, for a load/store of the specified type.
Scott Michelfdc40a02009-02-17 22:15:04 +00007023bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
Chris Lattnerc9addb72007-03-30 23:15:24 +00007024 const Type *Ty) const {
7025 // X86 supports extremely general addressing modes.
Scott Michelfdc40a02009-02-17 22:15:04 +00007026
Chris Lattnerc9addb72007-03-30 23:15:24 +00007027 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7028 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
7029 return false;
Scott Michelfdc40a02009-02-17 22:15:04 +00007030
Chris Lattnerc9addb72007-03-30 23:15:24 +00007031 if (AM.BaseGV) {
Evan Cheng52787842007-08-01 23:46:47 +00007032 // We can only fold this if we don't need an extra load.
Chris Lattnerc9addb72007-03-30 23:15:24 +00007033 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
7034 return false;
Dale Johannesen203af582008-12-05 21:47:27 +00007035 // If BaseGV requires a register, we cannot also have a BaseReg.
7036 if (Subtarget->GVRequiresRegister(AM.BaseGV, getTargetMachine(), false) &&
7037 AM.HasBaseReg)
7038 return false;
Evan Cheng52787842007-08-01 23:46:47 +00007039
7040 // X86-64 only supports addr of globals in small code model.
7041 if (Subtarget->is64Bit()) {
7042 if (getTargetMachine().getCodeModel() != CodeModel::Small)
7043 return false;
7044 // If lower 4G is not available, then we must use rip-relative addressing.
7045 if (AM.BaseOffs || AM.Scale > 1)
7046 return false;
7047 }
Chris Lattnerc9addb72007-03-30 23:15:24 +00007048 }
Scott Michelfdc40a02009-02-17 22:15:04 +00007049
Chris Lattnerc9addb72007-03-30 23:15:24 +00007050 switch (AM.Scale) {
7051 case 0:
7052 case 1:
7053 case 2:
7054 case 4:
7055 case 8:
7056 // These scales always work.
7057 break;
7058 case 3:
7059 case 5:
7060 case 9:
7061 // These scales are formed with basereg+scalereg. Only accept if there is
7062 // no basereg yet.
7063 if (AM.HasBaseReg)
7064 return false;
7065 break;
7066 default: // Other stuff never works.
7067 return false;
7068 }
Scott Michelfdc40a02009-02-17 22:15:04 +00007069
Chris Lattnerc9addb72007-03-30 23:15:24 +00007070 return true;
7071}
7072
7073
Evan Cheng2bd122c2007-10-26 01:56:11 +00007074bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7075 if (!Ty1->isInteger() || !Ty2->isInteger())
7076 return false;
Evan Chenge127a732007-10-29 07:57:50 +00007077 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7078 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
Evan Cheng260e07e2008-03-20 02:18:41 +00007079 if (NumBits1 <= NumBits2)
Evan Chenge127a732007-10-29 07:57:50 +00007080 return false;
7081 return Subtarget->is64Bit() || NumBits1 < 64;
Evan Cheng2bd122c2007-10-26 01:56:11 +00007082}
7083
Duncan Sands83ec4b62008-06-06 12:08:01 +00007084bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
7085 if (!VT1.isInteger() || !VT2.isInteger())
Evan Cheng3c3ddb32007-10-29 19:58:20 +00007086 return false;
Duncan Sands83ec4b62008-06-06 12:08:01 +00007087 unsigned NumBits1 = VT1.getSizeInBits();
7088 unsigned NumBits2 = VT2.getSizeInBits();
Evan Cheng260e07e2008-03-20 02:18:41 +00007089 if (NumBits1 <= NumBits2)
Evan Cheng3c3ddb32007-10-29 19:58:20 +00007090 return false;
7091 return Subtarget->is64Bit() || NumBits1 < 64;
7092}
Evan Cheng2bd122c2007-10-26 01:56:11 +00007093
Dan Gohman97121ba2009-04-08 00:15:30 +00007094bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
Dan Gohman349ba492009-04-09 02:06:09 +00007095 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
Dan Gohman97121ba2009-04-08 00:15:30 +00007096 return Ty1 == Type::Int32Ty && Ty2 == Type::Int64Ty && Subtarget->is64Bit();
7097}
7098
7099bool X86TargetLowering::isZExtFree(MVT VT1, MVT VT2) const {
Dan Gohman349ba492009-04-09 02:06:09 +00007100 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
Dan Gohman97121ba2009-04-08 00:15:30 +00007101 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7102}
7103
Evan Cheng8b944d32009-05-28 00:35:15 +00007104bool X86TargetLowering::isNarrowingProfitable(MVT VT1, MVT VT2) const {
7105 // i16 instructions are longer (0x66 prefix) and potentially slower.
7106 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7107}
7108
Evan Cheng60c07e12006-07-05 22:17:51 +00007109/// isShuffleMaskLegal - Targets can use this to indicate that they only
7110/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7111/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7112/// are assumed to be legal.
7113bool
Nate Begeman5a5ca152009-04-29 05:20:52 +00007114X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7115 MVT VT) const {
Evan Cheng60c07e12006-07-05 22:17:51 +00007116 // Only do shuffles on 128-bit vector types for now.
Nate Begeman9008ca62009-04-27 18:41:29 +00007117 if (VT.getSizeInBits() == 64)
7118 return false;
7119
7120 // FIXME: pshufb, blends, palignr, shifts.
7121 return (VT.getVectorNumElements() == 2 ||
7122 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7123 isMOVLMask(M, VT) ||
7124 isSHUFPMask(M, VT) ||
7125 isPSHUFDMask(M, VT) ||
7126 isPSHUFHWMask(M, VT) ||
7127 isPSHUFLWMask(M, VT) ||
7128 isUNPCKLMask(M, VT) ||
7129 isUNPCKHMask(M, VT) ||
7130 isUNPCKL_v_undef_Mask(M, VT) ||
7131 isUNPCKH_v_undef_Mask(M, VT));
Evan Cheng60c07e12006-07-05 22:17:51 +00007132}
7133
Dan Gohman7d8143f2008-04-09 20:09:42 +00007134bool
Nate Begeman5a5ca152009-04-29 05:20:52 +00007135X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
Nate Begeman9008ca62009-04-27 18:41:29 +00007136 MVT VT) const {
7137 unsigned NumElts = VT.getVectorNumElements();
7138 // FIXME: This collection of masks seems suspect.
7139 if (NumElts == 2)
7140 return true;
7141 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7142 return (isMOVLMask(Mask, VT) ||
7143 isCommutedMOVLMask(Mask, VT, true) ||
7144 isSHUFPMask(Mask, VT) ||
7145 isCommutedSHUFPMask(Mask, VT));
Evan Cheng60c07e12006-07-05 22:17:51 +00007146 }
7147 return false;
7148}
7149
7150//===----------------------------------------------------------------------===//
7151// X86 Scheduler Hooks
7152//===----------------------------------------------------------------------===//
7153
Mon P Wang63307c32008-05-05 19:05:59 +00007154// private utility function
7155MachineBasicBlock *
7156X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7157 MachineBasicBlock *MBB,
7158 unsigned regOpc,
Andrew Lenharth507a58a2008-06-14 05:48:15 +00007159 unsigned immOpc,
Dale Johannesen140be2d2008-08-19 18:47:28 +00007160 unsigned LoadOpc,
7161 unsigned CXchgOpc,
7162 unsigned copyOpc,
7163 unsigned notOpc,
7164 unsigned EAXreg,
7165 TargetRegisterClass *RC,
Dan Gohman1fdbc1d2009-02-07 16:15:20 +00007166 bool invSrc) const {
Mon P Wang63307c32008-05-05 19:05:59 +00007167 // For the atomic bitwise operator, we generate
7168 // thisMBB:
7169 // newMBB:
Mon P Wangab3e7472008-05-05 22:56:23 +00007170 // ld t1 = [bitinstr.addr]
7171 // op t2 = t1, [bitinstr.val]
7172 // mov EAX = t1
Mon P Wang63307c32008-05-05 19:05:59 +00007173 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7174 // bz newMBB
7175 // fallthrough -->nextMBB
7176 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7177 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
Dan Gohman8e5f2c62008-07-07 23:14:23 +00007178 MachineFunction::iterator MBBIter = MBB;
Mon P Wang63307c32008-05-05 19:05:59 +00007179 ++MBBIter;
Scott Michelfdc40a02009-02-17 22:15:04 +00007180
Mon P Wang63307c32008-05-05 19:05:59 +00007181 /// First build the CFG
7182 MachineFunction *F = MBB->getParent();
7183 MachineBasicBlock *thisMBB = MBB;
Dan Gohman8e5f2c62008-07-07 23:14:23 +00007184 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7185 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7186 F->insert(MBBIter, newMBB);
7187 F->insert(MBBIter, nextMBB);
Scott Michelfdc40a02009-02-17 22:15:04 +00007188
Mon P Wang63307c32008-05-05 19:05:59 +00007189 // Move all successors to thisMBB to nextMBB
7190 nextMBB->transferSuccessors(thisMBB);
Scott Michelfdc40a02009-02-17 22:15:04 +00007191
Mon P Wang63307c32008-05-05 19:05:59 +00007192 // Update thisMBB to fall through to newMBB
7193 thisMBB->addSuccessor(newMBB);
Scott Michelfdc40a02009-02-17 22:15:04 +00007194
Mon P Wang63307c32008-05-05 19:05:59 +00007195 // newMBB jumps to itself and fall through to nextMBB
7196 newMBB->addSuccessor(nextMBB);
7197 newMBB->addSuccessor(newMBB);
Scott Michelfdc40a02009-02-17 22:15:04 +00007198
Mon P Wang63307c32008-05-05 19:05:59 +00007199 // Insert instructions into newMBB based on incoming instruction
Rafael Espindolaa82dfca2009-03-27 15:26:30 +00007200 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
Bill Wendling51b16f42009-05-30 01:09:53 +00007201 "unexpected number of operands");
Dale Johannesene4d209d2009-02-03 20:21:25 +00007202 DebugLoc dl = bInstr->getDebugLoc();
Mon P Wang63307c32008-05-05 19:05:59 +00007203 MachineOperand& destOper = bInstr->getOperand(0);
Rafael Espindolaa82dfca2009-03-27 15:26:30 +00007204 MachineOperand* argOpers[2 + X86AddrNumOperands];
Mon P Wang63307c32008-05-05 19:05:59 +00007205 int numArgs = bInstr->getNumOperands() - 1;
7206 for (int i=0; i < numArgs; ++i)
7207 argOpers[i] = &bInstr->getOperand(i+1);
7208
7209 // x86 address has 4 operands: base, index, scale, and displacement
Rafael Espindolaa82dfca2009-03-27 15:26:30 +00007210 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7211 int valArgIndx = lastAddrIndx + 1;
Scott Michelfdc40a02009-02-17 22:15:04 +00007212
Dale Johannesen140be2d2008-08-19 18:47:28 +00007213 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
Dale Johannesene4d209d2009-02-03 20:21:25 +00007214 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
Mon P Wang63307c32008-05-05 19:05:59 +00007215 for (int i=0; i <= lastAddrIndx; ++i)
7216 (*MIB).addOperand(*argOpers[i]);
Andrew Lenharth507a58a2008-06-14 05:48:15 +00007217
Dale Johannesen140be2d2008-08-19 18:47:28 +00007218 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
Andrew Lenharth507a58a2008-06-14 05:48:15 +00007219 if (invSrc) {
Dale Johannesene4d209d2009-02-03 20:21:25 +00007220 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
Andrew Lenharth507a58a2008-06-14 05:48:15 +00007221 }
Scott Michelfdc40a02009-02-17 22:15:04 +00007222 else
Andrew Lenharth507a58a2008-06-14 05:48:15 +00007223 tt = t1;
7224
Dale Johannesen140be2d2008-08-19 18:47:28 +00007225 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
Dan Gohmand735b802008-10-03 15:45:36 +00007226 assert((argOpers[valArgIndx]->isReg() ||
7227 argOpers[valArgIndx]->isImm()) &&
Dan Gohman014278e2008-09-13 17:58:21 +00007228 "invalid operand");
Dan Gohmand735b802008-10-03 15:45:36 +00007229 if (argOpers[valArgIndx]->isReg())
Dale Johannesene4d209d2009-02-03 20:21:25 +00007230 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
Mon P Wang63307c32008-05-05 19:05:59 +00007231 else
Dale Johannesene4d209d2009-02-03 20:21:25 +00007232 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
Andrew Lenharth507a58a2008-06-14 05:48:15 +00007233 MIB.addReg(tt);
Mon P Wang63307c32008-05-05 19:05:59 +00007234 (*MIB).addOperand(*argOpers[valArgIndx]);
Andrew Lenharth507a58a2008-06-14 05:48:15 +00007235
Dale Johannesene4d209d2009-02-03 20:21:25 +00007236 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
Mon P Wangab3e7472008-05-05 22:56:23 +00007237 MIB.addReg(t1);
Scott Michelfdc40a02009-02-17 22:15:04 +00007238
Dale Johannesene4d209d2009-02-03 20:21:25 +00007239 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
Mon P Wang63307c32008-05-05 19:05:59 +00007240 for (int i=0; i <= lastAddrIndx; ++i)
7241 (*MIB).addOperand(*argOpers[i]);
7242 MIB.addReg(t2);
Mon P Wangf5952662008-07-17 04:54:06 +00007243 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7244 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7245
Dale Johannesene4d209d2009-02-03 20:21:25 +00007246 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
Dale Johannesen140be2d2008-08-19 18:47:28 +00007247 MIB.addReg(EAXreg);
Scott Michelfdc40a02009-02-17 22:15:04 +00007248
Mon P Wang63307c32008-05-05 19:05:59 +00007249 // insert branch
Dale Johannesene4d209d2009-02-03 20:21:25 +00007250 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
Mon P Wang63307c32008-05-05 19:05:59 +00007251
Dan Gohman8e5f2c62008-07-07 23:14:23 +00007252 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
Mon P Wang63307c32008-05-05 19:05:59 +00007253 return nextMBB;
7254}
7255
Dale Johannesen1b54c7f2008-10-03 19:41:08 +00007256// private utility function: 64 bit atomics on 32 bit host.
Mon P Wang63307c32008-05-05 19:05:59 +00007257MachineBasicBlock *
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007258X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7259 MachineBasicBlock *MBB,
7260 unsigned regOpcL,
7261 unsigned regOpcH,
7262 unsigned immOpcL,
7263 unsigned immOpcH,
Dan Gohman1fdbc1d2009-02-07 16:15:20 +00007264 bool invSrc) const {
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007265 // For the atomic bitwise operator, we generate
7266 // thisMBB (instructions are in pairs, except cmpxchg8b)
7267 // ld t1,t2 = [bitinstr.addr]
7268 // newMBB:
7269 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7270 // op t5, t6 <- out1, out2, [bitinstr.val]
Dale Johannesen880ae362008-10-03 22:25:52 +00007271 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007272 // mov ECX, EBX <- t5, t6
7273 // mov EAX, EDX <- t1, t2
7274 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7275 // mov t3, t4 <- EAX, EDX
7276 // bz newMBB
7277 // result in out1, out2
7278 // fallthrough -->nextMBB
7279
7280 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7281 const unsigned LoadOpc = X86::MOV32rm;
7282 const unsigned copyOpc = X86::MOV32rr;
7283 const unsigned NotOpc = X86::NOT32r;
7284 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7285 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7286 MachineFunction::iterator MBBIter = MBB;
7287 ++MBBIter;
Scott Michelfdc40a02009-02-17 22:15:04 +00007288
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007289 /// First build the CFG
7290 MachineFunction *F = MBB->getParent();
7291 MachineBasicBlock *thisMBB = MBB;
7292 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7293 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7294 F->insert(MBBIter, newMBB);
7295 F->insert(MBBIter, nextMBB);
Scott Michelfdc40a02009-02-17 22:15:04 +00007296
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007297 // Move all successors to thisMBB to nextMBB
7298 nextMBB->transferSuccessors(thisMBB);
Scott Michelfdc40a02009-02-17 22:15:04 +00007299
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007300 // Update thisMBB to fall through to newMBB
7301 thisMBB->addSuccessor(newMBB);
Scott Michelfdc40a02009-02-17 22:15:04 +00007302
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007303 // newMBB jumps to itself and fall through to nextMBB
7304 newMBB->addSuccessor(nextMBB);
7305 newMBB->addSuccessor(newMBB);
Scott Michelfdc40a02009-02-17 22:15:04 +00007306
Dale Johannesene4d209d2009-02-03 20:21:25 +00007307 DebugLoc dl = bInstr->getDebugLoc();
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007308 // Insert instructions into newMBB based on incoming instruction
7309 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
Rafael Espindolaa82dfca2009-03-27 15:26:30 +00007310 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
Bill Wendling51b16f42009-05-30 01:09:53 +00007311 "unexpected number of operands");
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007312 MachineOperand& dest1Oper = bInstr->getOperand(0);
7313 MachineOperand& dest2Oper = bInstr->getOperand(1);
Rafael Espindolaa82dfca2009-03-27 15:26:30 +00007314 MachineOperand* argOpers[2 + X86AddrNumOperands];
7315 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007316 argOpers[i] = &bInstr->getOperand(i+2);
7317
7318 // x86 address has 4 operands: base, index, scale, and displacement
Rafael Espindolaa82dfca2009-03-27 15:26:30 +00007319 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
Scott Michelfdc40a02009-02-17 22:15:04 +00007320
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007321 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
Dale Johannesene4d209d2009-02-03 20:21:25 +00007322 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007323 for (int i=0; i <= lastAddrIndx; ++i)
7324 (*MIB).addOperand(*argOpers[i]);
7325 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
Dale Johannesene4d209d2009-02-03 20:21:25 +00007326 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
Dale Johannesen880ae362008-10-03 22:25:52 +00007327 // add 4 to displacement.
Rafael Espindola094fad32009-04-08 21:14:34 +00007328 for (int i=0; i <= lastAddrIndx-2; ++i)
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007329 (*MIB).addOperand(*argOpers[i]);
Dale Johannesen880ae362008-10-03 22:25:52 +00007330 MachineOperand newOp3 = *(argOpers[3]);
7331 if (newOp3.isImm())
7332 newOp3.setImm(newOp3.getImm()+4);
7333 else
7334 newOp3.setOffset(newOp3.getOffset()+4);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007335 (*MIB).addOperand(newOp3);
Rafael Espindola094fad32009-04-08 21:14:34 +00007336 (*MIB).addOperand(*argOpers[lastAddrIndx]);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007337
7338 // t3/4 are defined later, at the bottom of the loop
7339 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7340 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
Dale Johannesene4d209d2009-02-03 20:21:25 +00007341 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007342 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
Dale Johannesene4d209d2009-02-03 20:21:25 +00007343 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007344 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7345
7346 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7347 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
Scott Michelfdc40a02009-02-17 22:15:04 +00007348 if (invSrc) {
Dale Johannesene4d209d2009-02-03 20:21:25 +00007349 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7350 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007351 } else {
7352 tt1 = t1;
7353 tt2 = t2;
7354 }
7355
Rafael Espindolaa82dfca2009-03-27 15:26:30 +00007356 int valArgIndx = lastAddrIndx + 1;
7357 assert((argOpers[valArgIndx]->isReg() ||
Bill Wendling51b16f42009-05-30 01:09:53 +00007358 argOpers[valArgIndx]->isImm()) &&
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007359 "invalid operand");
7360 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7361 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
Rafael Espindolaa82dfca2009-03-27 15:26:30 +00007362 if (argOpers[valArgIndx]->isReg())
Dale Johannesene4d209d2009-02-03 20:21:25 +00007363 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007364 else
Dale Johannesene4d209d2009-02-03 20:21:25 +00007365 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
Dale Johannesen880ae362008-10-03 22:25:52 +00007366 if (regOpcL != X86::MOV32rr)
7367 MIB.addReg(tt1);
Rafael Espindolaa82dfca2009-03-27 15:26:30 +00007368 (*MIB).addOperand(*argOpers[valArgIndx]);
7369 assert(argOpers[valArgIndx + 1]->isReg() ==
Bill Wendling51b16f42009-05-30 01:09:53 +00007370 argOpers[valArgIndx]->isReg());
Rafael Espindolaa82dfca2009-03-27 15:26:30 +00007371 assert(argOpers[valArgIndx + 1]->isImm() ==
Bill Wendling51b16f42009-05-30 01:09:53 +00007372 argOpers[valArgIndx]->isImm());
Rafael Espindolaa82dfca2009-03-27 15:26:30 +00007373 if (argOpers[valArgIndx + 1]->isReg())
Dale Johannesene4d209d2009-02-03 20:21:25 +00007374 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007375 else
Dale Johannesene4d209d2009-02-03 20:21:25 +00007376 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
Dale Johannesen880ae362008-10-03 22:25:52 +00007377 if (regOpcH != X86::MOV32rr)
7378 MIB.addReg(tt2);
Rafael Espindolaa82dfca2009-03-27 15:26:30 +00007379 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007380
Dale Johannesene4d209d2009-02-03 20:21:25 +00007381 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007382 MIB.addReg(t1);
Dale Johannesene4d209d2009-02-03 20:21:25 +00007383 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007384 MIB.addReg(t2);
7385
Dale Johannesene4d209d2009-02-03 20:21:25 +00007386 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007387 MIB.addReg(t5);
Dale Johannesene4d209d2009-02-03 20:21:25 +00007388 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007389 MIB.addReg(t6);
Scott Michelfdc40a02009-02-17 22:15:04 +00007390
Dale Johannesene4d209d2009-02-03 20:21:25 +00007391 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007392 for (int i=0; i <= lastAddrIndx; ++i)
7393 (*MIB).addOperand(*argOpers[i]);
7394
7395 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7396 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7397
Dale Johannesene4d209d2009-02-03 20:21:25 +00007398 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007399 MIB.addReg(X86::EAX);
Dale Johannesene4d209d2009-02-03 20:21:25 +00007400 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007401 MIB.addReg(X86::EDX);
Scott Michelfdc40a02009-02-17 22:15:04 +00007402
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007403 // insert branch
Dale Johannesene4d209d2009-02-03 20:21:25 +00007404 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007405
7406 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7407 return nextMBB;
7408}
7409
7410// private utility function
7411MachineBasicBlock *
Mon P Wang63307c32008-05-05 19:05:59 +00007412X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7413 MachineBasicBlock *MBB,
Dan Gohman1fdbc1d2009-02-07 16:15:20 +00007414 unsigned cmovOpc) const {
Mon P Wang63307c32008-05-05 19:05:59 +00007415 // For the atomic min/max operator, we generate
7416 // thisMBB:
7417 // newMBB:
Mon P Wangab3e7472008-05-05 22:56:23 +00007418 // ld t1 = [min/max.addr]
Scott Michelfdc40a02009-02-17 22:15:04 +00007419 // mov t2 = [min/max.val]
Mon P Wang63307c32008-05-05 19:05:59 +00007420 // cmp t1, t2
7421 // cmov[cond] t2 = t1
Mon P Wangab3e7472008-05-05 22:56:23 +00007422 // mov EAX = t1
Mon P Wang63307c32008-05-05 19:05:59 +00007423 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7424 // bz newMBB
7425 // fallthrough -->nextMBB
7426 //
7427 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7428 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
Dan Gohman8e5f2c62008-07-07 23:14:23 +00007429 MachineFunction::iterator MBBIter = MBB;
Mon P Wang63307c32008-05-05 19:05:59 +00007430 ++MBBIter;
Scott Michelfdc40a02009-02-17 22:15:04 +00007431
Mon P Wang63307c32008-05-05 19:05:59 +00007432 /// First build the CFG
7433 MachineFunction *F = MBB->getParent();
7434 MachineBasicBlock *thisMBB = MBB;
Dan Gohman8e5f2c62008-07-07 23:14:23 +00007435 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7436 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7437 F->insert(MBBIter, newMBB);
7438 F->insert(MBBIter, nextMBB);
Scott Michelfdc40a02009-02-17 22:15:04 +00007439
Mon P Wang63307c32008-05-05 19:05:59 +00007440 // Move all successors to thisMBB to nextMBB
7441 nextMBB->transferSuccessors(thisMBB);
Scott Michelfdc40a02009-02-17 22:15:04 +00007442
Mon P Wang63307c32008-05-05 19:05:59 +00007443 // Update thisMBB to fall through to newMBB
7444 thisMBB->addSuccessor(newMBB);
Scott Michelfdc40a02009-02-17 22:15:04 +00007445
Mon P Wang63307c32008-05-05 19:05:59 +00007446 // newMBB jumps to newMBB and fall through to nextMBB
7447 newMBB->addSuccessor(nextMBB);
7448 newMBB->addSuccessor(newMBB);
Scott Michelfdc40a02009-02-17 22:15:04 +00007449
Dale Johannesene4d209d2009-02-03 20:21:25 +00007450 DebugLoc dl = mInstr->getDebugLoc();
Mon P Wang63307c32008-05-05 19:05:59 +00007451 // Insert instructions into newMBB based on incoming instruction
Rafael Espindolaa82dfca2009-03-27 15:26:30 +00007452 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
Bill Wendling51b16f42009-05-30 01:09:53 +00007453 "unexpected number of operands");
Mon P Wang63307c32008-05-05 19:05:59 +00007454 MachineOperand& destOper = mInstr->getOperand(0);
Rafael Espindolaa82dfca2009-03-27 15:26:30 +00007455 MachineOperand* argOpers[2 + X86AddrNumOperands];
Mon P Wang63307c32008-05-05 19:05:59 +00007456 int numArgs = mInstr->getNumOperands() - 1;
7457 for (int i=0; i < numArgs; ++i)
7458 argOpers[i] = &mInstr->getOperand(i+1);
Scott Michelfdc40a02009-02-17 22:15:04 +00007459
Mon P Wang63307c32008-05-05 19:05:59 +00007460 // x86 address has 4 operands: base, index, scale, and displacement
Rafael Espindolaa82dfca2009-03-27 15:26:30 +00007461 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7462 int valArgIndx = lastAddrIndx + 1;
Scott Michelfdc40a02009-02-17 22:15:04 +00007463
Mon P Wangab3e7472008-05-05 22:56:23 +00007464 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
Dale Johannesene4d209d2009-02-03 20:21:25 +00007465 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
Mon P Wang63307c32008-05-05 19:05:59 +00007466 for (int i=0; i <= lastAddrIndx; ++i)
7467 (*MIB).addOperand(*argOpers[i]);
Mon P Wangab3e7472008-05-05 22:56:23 +00007468
Mon P Wang63307c32008-05-05 19:05:59 +00007469 // We only support register and immediate values
Dan Gohmand735b802008-10-03 15:45:36 +00007470 assert((argOpers[valArgIndx]->isReg() ||
7471 argOpers[valArgIndx]->isImm()) &&
Dan Gohman014278e2008-09-13 17:58:21 +00007472 "invalid operand");
Scott Michelfdc40a02009-02-17 22:15:04 +00007473
7474 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
Dan Gohmand735b802008-10-03 15:45:36 +00007475 if (argOpers[valArgIndx]->isReg())
Dale Johannesene4d209d2009-02-03 20:21:25 +00007476 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
Scott Michelfdc40a02009-02-17 22:15:04 +00007477 else
Dale Johannesene4d209d2009-02-03 20:21:25 +00007478 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
Mon P Wang63307c32008-05-05 19:05:59 +00007479 (*MIB).addOperand(*argOpers[valArgIndx]);
7480
Dale Johannesene4d209d2009-02-03 20:21:25 +00007481 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
Mon P Wangab3e7472008-05-05 22:56:23 +00007482 MIB.addReg(t1);
7483
Dale Johannesene4d209d2009-02-03 20:21:25 +00007484 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
Mon P Wang63307c32008-05-05 19:05:59 +00007485 MIB.addReg(t1);
7486 MIB.addReg(t2);
7487
7488 // Generate movc
7489 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
Dale Johannesene4d209d2009-02-03 20:21:25 +00007490 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
Mon P Wang63307c32008-05-05 19:05:59 +00007491 MIB.addReg(t2);
7492 MIB.addReg(t1);
7493
7494 // Cmp and exchange if none has modified the memory location
Dale Johannesene4d209d2009-02-03 20:21:25 +00007495 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
Mon P Wang63307c32008-05-05 19:05:59 +00007496 for (int i=0; i <= lastAddrIndx; ++i)
7497 (*MIB).addOperand(*argOpers[i]);
7498 MIB.addReg(t3);
Mon P Wangf5952662008-07-17 04:54:06 +00007499 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7500 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
Scott Michelfdc40a02009-02-17 22:15:04 +00007501
Dale Johannesene4d209d2009-02-03 20:21:25 +00007502 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
Mon P Wang63307c32008-05-05 19:05:59 +00007503 MIB.addReg(X86::EAX);
Scott Michelfdc40a02009-02-17 22:15:04 +00007504
Mon P Wang63307c32008-05-05 19:05:59 +00007505 // insert branch
Dale Johannesene4d209d2009-02-03 20:21:25 +00007506 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
Mon P Wang63307c32008-05-05 19:05:59 +00007507
Dan Gohman8e5f2c62008-07-07 23:14:23 +00007508 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
Mon P Wang63307c32008-05-05 19:05:59 +00007509 return nextMBB;
7510}
7511
7512
Evan Cheng60c07e12006-07-05 22:17:51 +00007513MachineBasicBlock *
Evan Chengff9b3732008-01-30 18:18:23 +00007514X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
Dan Gohman1fdbc1d2009-02-07 16:15:20 +00007515 MachineBasicBlock *BB) const {
Dale Johannesene4d209d2009-02-03 20:21:25 +00007516 DebugLoc dl = MI->getDebugLoc();
Evan Chengc0f64ff2006-11-27 23:37:22 +00007517 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
Evan Cheng60c07e12006-07-05 22:17:51 +00007518 switch (MI->getOpcode()) {
7519 default: assert(false && "Unexpected instr type to insert");
Mon P Wang9e5ecb82008-12-12 01:25:51 +00007520 case X86::CMOV_V1I64:
Evan Cheng60c07e12006-07-05 22:17:51 +00007521 case X86::CMOV_FR32:
7522 case X86::CMOV_FR64:
7523 case X86::CMOV_V4F32:
7524 case X86::CMOV_V2F64:
Evan Chenge5f62042007-09-29 00:00:36 +00007525 case X86::CMOV_V2I64: {
Evan Cheng60c07e12006-07-05 22:17:51 +00007526 // To "insert" a SELECT_CC instruction, we actually have to insert the
7527 // diamond control-flow pattern. The incoming instruction knows the
7528 // destination vreg to set, the condition code register to branch on, the
7529 // true/false values to select between, and a branch opcode to use.
7530 const BasicBlock *LLVM_BB = BB->getBasicBlock();
Dan Gohman8e5f2c62008-07-07 23:14:23 +00007531 MachineFunction::iterator It = BB;
Evan Cheng60c07e12006-07-05 22:17:51 +00007532 ++It;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00007533
Evan Cheng60c07e12006-07-05 22:17:51 +00007534 // thisMBB:
7535 // ...
7536 // TrueVal = ...
7537 // cmpTY ccX, r1, r2
7538 // bCC copy1MBB
7539 // fallthrough --> copy0MBB
7540 MachineBasicBlock *thisMBB = BB;
Dan Gohman8e5f2c62008-07-07 23:14:23 +00007541 MachineFunction *F = BB->getParent();
7542 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7543 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00007544 unsigned Opc =
Chris Lattner7fbe9722006-10-20 17:42:20 +00007545 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
Dale Johannesene4d209d2009-02-03 20:21:25 +00007546 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
Dan Gohman8e5f2c62008-07-07 23:14:23 +00007547 F->insert(It, copy0MBB);
7548 F->insert(It, sinkMBB);
Mon P Wang63307c32008-05-05 19:05:59 +00007549 // Update machine-CFG edges by transferring all successors of the current
Evan Cheng60c07e12006-07-05 22:17:51 +00007550 // block to the new block which will contain the Phi node for the select.
Mon P Wang63307c32008-05-05 19:05:59 +00007551 sinkMBB->transferSuccessors(BB);
7552
7553 // Add the true and fallthrough blocks as its successors.
Evan Cheng60c07e12006-07-05 22:17:51 +00007554 BB->addSuccessor(copy0MBB);
7555 BB->addSuccessor(sinkMBB);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00007556
Evan Cheng60c07e12006-07-05 22:17:51 +00007557 // copy0MBB:
7558 // %FalseValue = ...
7559 // # fallthrough to sinkMBB
7560 BB = copy0MBB;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00007561
Evan Cheng60c07e12006-07-05 22:17:51 +00007562 // Update machine-CFG edges
7563 BB->addSuccessor(sinkMBB);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00007564
Evan Cheng60c07e12006-07-05 22:17:51 +00007565 // sinkMBB:
7566 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7567 // ...
7568 BB = sinkMBB;
Dale Johannesene4d209d2009-02-03 20:21:25 +00007569 BuildMI(BB, dl, TII->get(X86::PHI), MI->getOperand(0).getReg())
Evan Cheng60c07e12006-07-05 22:17:51 +00007570 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7571 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7572
Dan Gohman8e5f2c62008-07-07 23:14:23 +00007573 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
Evan Cheng60c07e12006-07-05 22:17:51 +00007574 return BB;
7575 }
7576
Dale Johannesen849f2142007-07-03 00:53:03 +00007577 case X86::FP32_TO_INT16_IN_MEM:
7578 case X86::FP32_TO_INT32_IN_MEM:
7579 case X86::FP32_TO_INT64_IN_MEM:
7580 case X86::FP64_TO_INT16_IN_MEM:
7581 case X86::FP64_TO_INT32_IN_MEM:
Dale Johannesena996d522007-08-07 01:17:37 +00007582 case X86::FP64_TO_INT64_IN_MEM:
7583 case X86::FP80_TO_INT16_IN_MEM:
7584 case X86::FP80_TO_INT32_IN_MEM:
7585 case X86::FP80_TO_INT64_IN_MEM: {
Evan Cheng60c07e12006-07-05 22:17:51 +00007586 // Change the floating point control register to use "round towards zero"
7587 // mode when truncating to an integer value.
7588 MachineFunction *F = BB->getParent();
7589 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
Dale Johannesene4d209d2009-02-03 20:21:25 +00007590 addFrameReference(BuildMI(BB, dl, TII->get(X86::FNSTCW16m)), CWFrameIdx);
Evan Cheng60c07e12006-07-05 22:17:51 +00007591
7592 // Load the old value of the high byte of the control word...
7593 unsigned OldCW =
Chris Lattner84bc5422007-12-31 04:13:23 +00007594 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
Scott Michelfdc40a02009-02-17 22:15:04 +00007595 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW),
Dale Johannesene4d209d2009-02-03 20:21:25 +00007596 CWFrameIdx);
Evan Cheng60c07e12006-07-05 22:17:51 +00007597
7598 // Set the high part to be round to zero...
Dale Johannesene4d209d2009-02-03 20:21:25 +00007599 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mi)), CWFrameIdx)
Evan Chengc0f64ff2006-11-27 23:37:22 +00007600 .addImm(0xC7F);
Evan Cheng60c07e12006-07-05 22:17:51 +00007601
7602 // Reload the modified control word now...
Dale Johannesene4d209d2009-02-03 20:21:25 +00007603 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
Evan Cheng60c07e12006-07-05 22:17:51 +00007604
7605 // Restore the memory image of control word to original value
Dale Johannesene4d209d2009-02-03 20:21:25 +00007606 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mr)), CWFrameIdx)
Evan Chengc0f64ff2006-11-27 23:37:22 +00007607 .addReg(OldCW);
Evan Cheng60c07e12006-07-05 22:17:51 +00007608
7609 // Get the X86 opcode to use.
7610 unsigned Opc;
7611 switch (MI->getOpcode()) {
7612 default: assert(0 && "illegal opcode!");
Dale Johannesene377d4d2007-07-04 21:07:47 +00007613 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
7614 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
7615 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
7616 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
7617 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
7618 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
Dale Johannesena996d522007-08-07 01:17:37 +00007619 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
7620 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
7621 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
Evan Cheng60c07e12006-07-05 22:17:51 +00007622 }
7623
7624 X86AddressMode AM;
7625 MachineOperand &Op = MI->getOperand(0);
Dan Gohmand735b802008-10-03 15:45:36 +00007626 if (Op.isReg()) {
Evan Cheng60c07e12006-07-05 22:17:51 +00007627 AM.BaseType = X86AddressMode::RegBase;
7628 AM.Base.Reg = Op.getReg();
7629 } else {
7630 AM.BaseType = X86AddressMode::FrameIndexBase;
Chris Lattner8aa797a2007-12-30 23:10:15 +00007631 AM.Base.FrameIndex = Op.getIndex();
Evan Cheng60c07e12006-07-05 22:17:51 +00007632 }
7633 Op = MI->getOperand(1);
Dan Gohmand735b802008-10-03 15:45:36 +00007634 if (Op.isImm())
Chris Lattner7fbe9722006-10-20 17:42:20 +00007635 AM.Scale = Op.getImm();
Evan Cheng60c07e12006-07-05 22:17:51 +00007636 Op = MI->getOperand(2);
Dan Gohmand735b802008-10-03 15:45:36 +00007637 if (Op.isImm())
Chris Lattner7fbe9722006-10-20 17:42:20 +00007638 AM.IndexReg = Op.getImm();
Evan Cheng60c07e12006-07-05 22:17:51 +00007639 Op = MI->getOperand(3);
Dan Gohmand735b802008-10-03 15:45:36 +00007640 if (Op.isGlobal()) {
Evan Cheng60c07e12006-07-05 22:17:51 +00007641 AM.GV = Op.getGlobal();
7642 } else {
Chris Lattner7fbe9722006-10-20 17:42:20 +00007643 AM.Disp = Op.getImm();
Evan Cheng60c07e12006-07-05 22:17:51 +00007644 }
Dale Johannesene4d209d2009-02-03 20:21:25 +00007645 addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM)
Rafael Espindola8ef2b892009-04-08 08:09:33 +00007646 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
Evan Cheng60c07e12006-07-05 22:17:51 +00007647
7648 // Reload the original control word now.
Dale Johannesene4d209d2009-02-03 20:21:25 +00007649 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
Evan Cheng60c07e12006-07-05 22:17:51 +00007650
Dan Gohman8e5f2c62008-07-07 23:14:23 +00007651 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
Evan Cheng60c07e12006-07-05 22:17:51 +00007652 return BB;
7653 }
Mon P Wang63307c32008-05-05 19:05:59 +00007654 case X86::ATOMAND32:
7655 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
Scott Michelfdc40a02009-02-17 22:15:04 +00007656 X86::AND32ri, X86::MOV32rm,
Dale Johannesen140be2d2008-08-19 18:47:28 +00007657 X86::LCMPXCHG32, X86::MOV32rr,
7658 X86::NOT32r, X86::EAX,
7659 X86::GR32RegisterClass);
Mon P Wang63307c32008-05-05 19:05:59 +00007660 case X86::ATOMOR32:
Scott Michelfdc40a02009-02-17 22:15:04 +00007661 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
7662 X86::OR32ri, X86::MOV32rm,
Dale Johannesen140be2d2008-08-19 18:47:28 +00007663 X86::LCMPXCHG32, X86::MOV32rr,
7664 X86::NOT32r, X86::EAX,
7665 X86::GR32RegisterClass);
Mon P Wang63307c32008-05-05 19:05:59 +00007666 case X86::ATOMXOR32:
7667 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
Scott Michelfdc40a02009-02-17 22:15:04 +00007668 X86::XOR32ri, X86::MOV32rm,
Dale Johannesen140be2d2008-08-19 18:47:28 +00007669 X86::LCMPXCHG32, X86::MOV32rr,
7670 X86::NOT32r, X86::EAX,
7671 X86::GR32RegisterClass);
Andrew Lenharth507a58a2008-06-14 05:48:15 +00007672 case X86::ATOMNAND32:
7673 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
Dale Johannesen140be2d2008-08-19 18:47:28 +00007674 X86::AND32ri, X86::MOV32rm,
7675 X86::LCMPXCHG32, X86::MOV32rr,
7676 X86::NOT32r, X86::EAX,
7677 X86::GR32RegisterClass, true);
Mon P Wang63307c32008-05-05 19:05:59 +00007678 case X86::ATOMMIN32:
7679 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
7680 case X86::ATOMMAX32:
7681 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
7682 case X86::ATOMUMIN32:
7683 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
7684 case X86::ATOMUMAX32:
7685 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
Dale Johannesen140be2d2008-08-19 18:47:28 +00007686
7687 case X86::ATOMAND16:
7688 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7689 X86::AND16ri, X86::MOV16rm,
7690 X86::LCMPXCHG16, X86::MOV16rr,
7691 X86::NOT16r, X86::AX,
7692 X86::GR16RegisterClass);
7693 case X86::ATOMOR16:
Scott Michelfdc40a02009-02-17 22:15:04 +00007694 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
Dale Johannesen140be2d2008-08-19 18:47:28 +00007695 X86::OR16ri, X86::MOV16rm,
7696 X86::LCMPXCHG16, X86::MOV16rr,
7697 X86::NOT16r, X86::AX,
7698 X86::GR16RegisterClass);
7699 case X86::ATOMXOR16:
7700 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
7701 X86::XOR16ri, X86::MOV16rm,
7702 X86::LCMPXCHG16, X86::MOV16rr,
7703 X86::NOT16r, X86::AX,
7704 X86::GR16RegisterClass);
7705 case X86::ATOMNAND16:
7706 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7707 X86::AND16ri, X86::MOV16rm,
7708 X86::LCMPXCHG16, X86::MOV16rr,
7709 X86::NOT16r, X86::AX,
7710 X86::GR16RegisterClass, true);
7711 case X86::ATOMMIN16:
7712 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
7713 case X86::ATOMMAX16:
7714 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
7715 case X86::ATOMUMIN16:
7716 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
7717 case X86::ATOMUMAX16:
7718 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
7719
7720 case X86::ATOMAND8:
7721 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7722 X86::AND8ri, X86::MOV8rm,
7723 X86::LCMPXCHG8, X86::MOV8rr,
7724 X86::NOT8r, X86::AL,
7725 X86::GR8RegisterClass);
7726 case X86::ATOMOR8:
Scott Michelfdc40a02009-02-17 22:15:04 +00007727 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
Dale Johannesen140be2d2008-08-19 18:47:28 +00007728 X86::OR8ri, X86::MOV8rm,
7729 X86::LCMPXCHG8, X86::MOV8rr,
7730 X86::NOT8r, X86::AL,
7731 X86::GR8RegisterClass);
7732 case X86::ATOMXOR8:
7733 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
7734 X86::XOR8ri, X86::MOV8rm,
7735 X86::LCMPXCHG8, X86::MOV8rr,
7736 X86::NOT8r, X86::AL,
7737 X86::GR8RegisterClass);
7738 case X86::ATOMNAND8:
7739 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7740 X86::AND8ri, X86::MOV8rm,
7741 X86::LCMPXCHG8, X86::MOV8rr,
7742 X86::NOT8r, X86::AL,
7743 X86::GR8RegisterClass, true);
7744 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007745 // This group is for 64-bit host.
Dale Johannesena99e3842008-08-20 00:48:50 +00007746 case X86::ATOMAND64:
7747 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
Scott Michelfdc40a02009-02-17 22:15:04 +00007748 X86::AND64ri32, X86::MOV64rm,
Dale Johannesena99e3842008-08-20 00:48:50 +00007749 X86::LCMPXCHG64, X86::MOV64rr,
7750 X86::NOT64r, X86::RAX,
7751 X86::GR64RegisterClass);
7752 case X86::ATOMOR64:
Scott Michelfdc40a02009-02-17 22:15:04 +00007753 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
7754 X86::OR64ri32, X86::MOV64rm,
Dale Johannesena99e3842008-08-20 00:48:50 +00007755 X86::LCMPXCHG64, X86::MOV64rr,
7756 X86::NOT64r, X86::RAX,
7757 X86::GR64RegisterClass);
7758 case X86::ATOMXOR64:
7759 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
Scott Michelfdc40a02009-02-17 22:15:04 +00007760 X86::XOR64ri32, X86::MOV64rm,
Dale Johannesena99e3842008-08-20 00:48:50 +00007761 X86::LCMPXCHG64, X86::MOV64rr,
7762 X86::NOT64r, X86::RAX,
7763 X86::GR64RegisterClass);
7764 case X86::ATOMNAND64:
7765 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7766 X86::AND64ri32, X86::MOV64rm,
7767 X86::LCMPXCHG64, X86::MOV64rr,
7768 X86::NOT64r, X86::RAX,
7769 X86::GR64RegisterClass, true);
7770 case X86::ATOMMIN64:
7771 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
7772 case X86::ATOMMAX64:
7773 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
7774 case X86::ATOMUMIN64:
7775 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
7776 case X86::ATOMUMAX64:
7777 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007778
7779 // This group does 64-bit operations on a 32-bit host.
7780 case X86::ATOMAND6432:
Scott Michelfdc40a02009-02-17 22:15:04 +00007781 return EmitAtomicBit6432WithCustomInserter(MI, BB,
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007782 X86::AND32rr, X86::AND32rr,
7783 X86::AND32ri, X86::AND32ri,
7784 false);
7785 case X86::ATOMOR6432:
Scott Michelfdc40a02009-02-17 22:15:04 +00007786 return EmitAtomicBit6432WithCustomInserter(MI, BB,
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007787 X86::OR32rr, X86::OR32rr,
7788 X86::OR32ri, X86::OR32ri,
7789 false);
7790 case X86::ATOMXOR6432:
Scott Michelfdc40a02009-02-17 22:15:04 +00007791 return EmitAtomicBit6432WithCustomInserter(MI, BB,
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007792 X86::XOR32rr, X86::XOR32rr,
7793 X86::XOR32ri, X86::XOR32ri,
7794 false);
7795 case X86::ATOMNAND6432:
Scott Michelfdc40a02009-02-17 22:15:04 +00007796 return EmitAtomicBit6432WithCustomInserter(MI, BB,
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007797 X86::AND32rr, X86::AND32rr,
7798 X86::AND32ri, X86::AND32ri,
7799 true);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007800 case X86::ATOMADD6432:
Scott Michelfdc40a02009-02-17 22:15:04 +00007801 return EmitAtomicBit6432WithCustomInserter(MI, BB,
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007802 X86::ADD32rr, X86::ADC32rr,
7803 X86::ADD32ri, X86::ADC32ri,
7804 false);
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007805 case X86::ATOMSUB6432:
Scott Michelfdc40a02009-02-17 22:15:04 +00007806 return EmitAtomicBit6432WithCustomInserter(MI, BB,
Dale Johannesen48c1bc22008-10-02 18:53:47 +00007807 X86::SUB32rr, X86::SBB32rr,
7808 X86::SUB32ri, X86::SBB32ri,
7809 false);
Dale Johannesen880ae362008-10-03 22:25:52 +00007810 case X86::ATOMSWAP6432:
Scott Michelfdc40a02009-02-17 22:15:04 +00007811 return EmitAtomicBit6432WithCustomInserter(MI, BB,
Dale Johannesen880ae362008-10-03 22:25:52 +00007812 X86::MOV32rr, X86::MOV32rr,
7813 X86::MOV32ri, X86::MOV32ri,
7814 false);
Evan Cheng60c07e12006-07-05 22:17:51 +00007815 }
7816}
7817
7818//===----------------------------------------------------------------------===//
7819// X86 Optimization Hooks
7820//===----------------------------------------------------------------------===//
7821
Dan Gohman475871a2008-07-27 21:46:04 +00007822void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman977a76f2008-02-13 22:28:48 +00007823 const APInt &Mask,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +00007824 APInt &KnownZero,
7825 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +00007826 const SelectionDAG &DAG,
Nate Begeman368e18d2006-02-16 21:11:51 +00007827 unsigned Depth) const {
Evan Cheng3a03ebb2005-12-21 23:05:39 +00007828 unsigned Opc = Op.getOpcode();
Evan Cheng865f0602006-04-05 06:11:20 +00007829 assert((Opc >= ISD::BUILTIN_OP_END ||
7830 Opc == ISD::INTRINSIC_WO_CHAIN ||
7831 Opc == ISD::INTRINSIC_W_CHAIN ||
7832 Opc == ISD::INTRINSIC_VOID) &&
7833 "Should use MaskedValueIsZero if you don't know whether Op"
7834 " is a target node!");
Evan Cheng3a03ebb2005-12-21 23:05:39 +00007835
Dan Gohmanf4f92f52008-02-13 23:07:24 +00007836 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
Evan Cheng3a03ebb2005-12-21 23:05:39 +00007837 switch (Opc) {
Evan Cheng865f0602006-04-05 06:11:20 +00007838 default: break;
Evan Cheng97d0e0e2009-02-02 09:15:04 +00007839 case X86ISD::ADD:
7840 case X86ISD::SUB:
7841 case X86ISD::SMUL:
7842 case X86ISD::UMUL:
Dan Gohman076aee32009-03-04 19:44:21 +00007843 case X86ISD::INC:
7844 case X86ISD::DEC:
Evan Cheng97d0e0e2009-02-02 09:15:04 +00007845 // These nodes' second result is a boolean.
7846 if (Op.getResNo() == 0)
7847 break;
7848 // Fallthrough
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00007849 case X86ISD::SETCC:
Dan Gohmanfd29e0e2008-02-13 00:35:47 +00007850 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
7851 Mask.getBitWidth() - 1);
Nate Begeman368e18d2006-02-16 21:11:51 +00007852 break;
Evan Cheng3a03ebb2005-12-21 23:05:39 +00007853 }
Evan Cheng3a03ebb2005-12-21 23:05:39 +00007854}
Chris Lattner259e97c2006-01-31 19:43:35 +00007855
Evan Cheng206ee9d2006-07-07 08:33:52 +00007856/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
Evan Chengad4196b2008-05-12 19:56:52 +00007857/// node is a GlobalAddress + offset.
7858bool X86TargetLowering::isGAPlusOffset(SDNode *N,
7859 GlobalValue* &GA, int64_t &Offset) const{
7860 if (N->getOpcode() == X86ISD::Wrapper) {
7861 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
Evan Cheng206ee9d2006-07-07 08:33:52 +00007862 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
Dan Gohman6520e202008-10-18 02:06:02 +00007863 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
Evan Cheng206ee9d2006-07-07 08:33:52 +00007864 return true;
7865 }
Evan Cheng206ee9d2006-07-07 08:33:52 +00007866 }
Evan Chengad4196b2008-05-12 19:56:52 +00007867 return TargetLowering::isGAPlusOffset(N, GA, Offset);
Evan Cheng206ee9d2006-07-07 08:33:52 +00007868}
7869
Evan Chengad4196b2008-05-12 19:56:52 +00007870static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
7871 const TargetLowering &TLI) {
Evan Cheng206ee9d2006-07-07 08:33:52 +00007872 GlobalValue *GV;
Nick Lewycky916a9f02008-02-02 08:29:58 +00007873 int64_t Offset = 0;
Evan Chengad4196b2008-05-12 19:56:52 +00007874 if (TLI.isGAPlusOffset(Base, GV, Offset))
Evan Cheng7e2ff772008-05-08 00:57:18 +00007875 return (GV->getAlignment() >= N && (Offset % N) == 0);
Chris Lattnerba96fbc2008-01-26 20:07:42 +00007876 // DAG combine handles the stack object case.
Evan Cheng206ee9d2006-07-07 08:33:52 +00007877 return false;
7878}
7879
Nate Begeman9008ca62009-04-27 18:41:29 +00007880static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
Eli Friedman7a5e5552009-06-07 06:52:44 +00007881 MVT EVT, LoadSDNode *&LDBase,
7882 unsigned &LastLoadedElt,
Evan Chengad4196b2008-05-12 19:56:52 +00007883 SelectionDAG &DAG, MachineFrameInfo *MFI,
7884 const TargetLowering &TLI) {
Eli Friedman7a5e5552009-06-07 06:52:44 +00007885 LDBase = NULL;
Anton Korobeynikovb51b6cf2009-06-09 23:00:39 +00007886 LastLoadedElt = -1U;
Evan Cheng7e2ff772008-05-08 00:57:18 +00007887 for (unsigned i = 0; i < NumElems; ++i) {
Nate Begeman9008ca62009-04-27 18:41:29 +00007888 if (N->getMaskElt(i) < 0) {
Eli Friedman7a5e5552009-06-07 06:52:44 +00007889 if (!LDBase)
Evan Cheng7e2ff772008-05-08 00:57:18 +00007890 return false;
7891 continue;
7892 }
7893
Dan Gohman475871a2008-07-27 21:46:04 +00007894 SDValue Elt = DAG.getShuffleScalarElt(N, i);
Gabor Greifba36cb52008-08-28 21:40:38 +00007895 if (!Elt.getNode() ||
7896 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
Evan Cheng7e2ff772008-05-08 00:57:18 +00007897 return false;
Eli Friedman7a5e5552009-06-07 06:52:44 +00007898 if (!LDBase) {
7899 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
Evan Cheng50d9e722008-05-10 06:46:49 +00007900 return false;
Eli Friedman7a5e5552009-06-07 06:52:44 +00007901 LDBase = cast<LoadSDNode>(Elt.getNode());
7902 LastLoadedElt = i;
Evan Cheng7e2ff772008-05-08 00:57:18 +00007903 continue;
7904 }
7905 if (Elt.getOpcode() == ISD::UNDEF)
7906 continue;
7907
Nate Begemanabc01992009-06-05 21:37:30 +00007908 LoadSDNode *LD = cast<LoadSDNode>(Elt);
Nate Begemanabc01992009-06-05 21:37:30 +00007909 if (!TLI.isConsecutiveLoad(LD, LDBase, EVT.getSizeInBits()/8, i, MFI))
Evan Cheng7e2ff772008-05-08 00:57:18 +00007910 return false;
Eli Friedman7a5e5552009-06-07 06:52:44 +00007911 LastLoadedElt = i;
Evan Cheng7e2ff772008-05-08 00:57:18 +00007912 }
7913 return true;
7914}
Evan Cheng206ee9d2006-07-07 08:33:52 +00007915
7916/// PerformShuffleCombine - Combine a vector_shuffle that is equal to
7917/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
7918/// if the load addresses are consecutive, non-overlapping, and in the right
Mon P Wang1e955802009-04-03 02:43:30 +00007919/// order. In the case of v2i64, it will see if it can rewrite the
7920/// shuffle to be an appropriate build vector so it can take advantage of
7921// performBuildVectorCombine.
Dan Gohman475871a2008-07-27 21:46:04 +00007922static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
Nate Begeman9008ca62009-04-27 18:41:29 +00007923 const TargetLowering &TLI) {
Dale Johannesene4d209d2009-02-03 20:21:25 +00007924 DebugLoc dl = N->getDebugLoc();
Duncan Sands83ec4b62008-06-06 12:08:01 +00007925 MVT VT = N->getValueType(0);
7926 MVT EVT = VT.getVectorElementType();
Nate Begeman9008ca62009-04-27 18:41:29 +00007927 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7928 unsigned NumElems = VT.getVectorNumElements();
Mon P Wang1e955802009-04-03 02:43:30 +00007929
Eli Friedman7a5e5552009-06-07 06:52:44 +00007930 if (VT.getSizeInBits() != 128)
7931 return SDValue();
7932
Mon P Wang1e955802009-04-03 02:43:30 +00007933 // Try to combine a vector_shuffle into a 128-bit load.
7934 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
Eli Friedman7a5e5552009-06-07 06:52:44 +00007935 LoadSDNode *LD = NULL;
7936 unsigned LastLoadedElt;
7937 if (!EltsFromConsecutiveLoads(SVN, NumElems, EVT, LD, LastLoadedElt, DAG,
7938 MFI, TLI))
Dan Gohman475871a2008-07-27 21:46:04 +00007939 return SDValue();
Evan Cheng206ee9d2006-07-07 08:33:52 +00007940
Eli Friedman7a5e5552009-06-07 06:52:44 +00007941 if (LastLoadedElt == NumElems - 1) {
7942 if (isBaseAlignmentOfN(16, LD->getBasePtr().getNode(), TLI))
7943 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
7944 LD->getSrcValue(), LD->getSrcValueOffset(),
7945 LD->isVolatile());
Dale Johannesene4d209d2009-02-03 20:21:25 +00007946 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
Scott Michelfdc40a02009-02-17 22:15:04 +00007947 LD->getSrcValue(), LD->getSrcValueOffset(),
Eli Friedman7a5e5552009-06-07 06:52:44 +00007948 LD->isVolatile(), LD->getAlignment());
7949 } else if (NumElems == 4 && LastLoadedElt == 1) {
7950 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
Nate Begemanabc01992009-06-05 21:37:30 +00007951 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
7952 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
Nate Begemanabc01992009-06-05 21:37:30 +00007953 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
7954 }
7955 return SDValue();
Scott Michelfdc40a02009-02-17 22:15:04 +00007956}
Evan Chengd880b972008-05-09 21:53:03 +00007957
Chris Lattner83e6c992006-10-04 06:57:07 +00007958/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
Dan Gohman475871a2008-07-27 21:46:04 +00007959static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
Chris Lattner47b4ce82009-03-11 05:48:52 +00007960 const X86Subtarget *Subtarget) {
7961 DebugLoc DL = N->getDebugLoc();
Dan Gohman475871a2008-07-27 21:46:04 +00007962 SDValue Cond = N->getOperand(0);
Chris Lattner47b4ce82009-03-11 05:48:52 +00007963 // Get the LHS/RHS of the select.
7964 SDValue LHS = N->getOperand(1);
7965 SDValue RHS = N->getOperand(2);
7966
Chris Lattner83e6c992006-10-04 06:57:07 +00007967 // If we have SSE[12] support, try to form min/max nodes.
7968 if (Subtarget->hasSSE2() &&
Chris Lattner47b4ce82009-03-11 05:48:52 +00007969 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
7970 Cond.getOpcode() == ISD::SETCC) {
7971 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00007972
Chris Lattner47b4ce82009-03-11 05:48:52 +00007973 unsigned Opcode = 0;
7974 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
7975 switch (CC) {
7976 default: break;
7977 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
7978 case ISD::SETULE:
7979 case ISD::SETLE:
7980 if (!UnsafeFPMath) break;
7981 // FALL THROUGH.
7982 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
7983 case ISD::SETLT:
7984 Opcode = X86ISD::FMIN;
7985 break;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00007986
Chris Lattner47b4ce82009-03-11 05:48:52 +00007987 case ISD::SETOGT: // (X > Y) ? X : Y -> max
7988 case ISD::SETUGT:
7989 case ISD::SETGT:
7990 if (!UnsafeFPMath) break;
7991 // FALL THROUGH.
7992 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
7993 case ISD::SETGE:
7994 Opcode = X86ISD::FMAX;
7995 break;
Chris Lattner83e6c992006-10-04 06:57:07 +00007996 }
Chris Lattner47b4ce82009-03-11 05:48:52 +00007997 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
7998 switch (CC) {
7999 default: break;
8000 case ISD::SETOGT: // (X > Y) ? Y : X -> min
8001 case ISD::SETUGT:
8002 case ISD::SETGT:
8003 if (!UnsafeFPMath) break;
8004 // FALL THROUGH.
8005 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
8006 case ISD::SETGE:
8007 Opcode = X86ISD::FMIN;
8008 break;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00008009
Chris Lattner47b4ce82009-03-11 05:48:52 +00008010 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
8011 case ISD::SETULE:
8012 case ISD::SETLE:
8013 if (!UnsafeFPMath) break;
8014 // FALL THROUGH.
8015 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
8016 case ISD::SETLT:
8017 Opcode = X86ISD::FMAX;
8018 break;
8019 }
Chris Lattner83e6c992006-10-04 06:57:07 +00008020 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00008021
Chris Lattner47b4ce82009-03-11 05:48:52 +00008022 if (Opcode)
8023 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
Chris Lattner83e6c992006-10-04 06:57:07 +00008024 }
Chris Lattner47b4ce82009-03-11 05:48:52 +00008025
Chris Lattnerd1980a52009-03-12 06:52:53 +00008026 // If this is a select between two integer constants, try to do some
8027 // optimizations.
Chris Lattnercee56e72009-03-13 05:53:31 +00008028 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8029 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
Chris Lattnerd1980a52009-03-12 06:52:53 +00008030 // Don't do this for crazy integer types.
8031 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8032 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
Chris Lattnercee56e72009-03-13 05:53:31 +00008033 // so that TrueC (the true value) is larger than FalseC.
Chris Lattnerd1980a52009-03-12 06:52:53 +00008034 bool NeedsCondInvert = false;
8035
Chris Lattnercee56e72009-03-13 05:53:31 +00008036 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
Chris Lattnerd1980a52009-03-12 06:52:53 +00008037 // Efficiently invertible.
8038 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8039 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8040 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8041 NeedsCondInvert = true;
Chris Lattnercee56e72009-03-13 05:53:31 +00008042 std::swap(TrueC, FalseC);
Chris Lattnerd1980a52009-03-12 06:52:53 +00008043 }
8044
8045 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
Chris Lattnercee56e72009-03-13 05:53:31 +00008046 if (FalseC->getAPIntValue() == 0 &&
8047 TrueC->getAPIntValue().isPowerOf2()) {
Chris Lattnerd1980a52009-03-12 06:52:53 +00008048 if (NeedsCondInvert) // Invert the condition if needed.
8049 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8050 DAG.getConstant(1, Cond.getValueType()));
8051
8052 // Zero extend the condition if needed.
8053 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8054
Chris Lattnercee56e72009-03-13 05:53:31 +00008055 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
Chris Lattnerd1980a52009-03-12 06:52:53 +00008056 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8057 DAG.getConstant(ShAmt, MVT::i8));
8058 }
Chris Lattner97a29a52009-03-13 05:22:11 +00008059
8060 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
Chris Lattnercee56e72009-03-13 05:53:31 +00008061 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
Chris Lattner97a29a52009-03-13 05:22:11 +00008062 if (NeedsCondInvert) // Invert the condition if needed.
8063 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8064 DAG.getConstant(1, Cond.getValueType()));
8065
8066 // Zero extend the condition if needed.
Chris Lattnercee56e72009-03-13 05:53:31 +00008067 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8068 FalseC->getValueType(0), Cond);
Chris Lattner97a29a52009-03-13 05:22:11 +00008069 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
Chris Lattnercee56e72009-03-13 05:53:31 +00008070 SDValue(FalseC, 0));
Chris Lattner97a29a52009-03-13 05:22:11 +00008071 }
Chris Lattnercee56e72009-03-13 05:53:31 +00008072
8073 // Optimize cases that will turn into an LEA instruction. This requires
8074 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8075 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8076 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8077 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8078
8079 bool isFastMultiplier = false;
8080 if (Diff < 10) {
8081 switch ((unsigned char)Diff) {
8082 default: break;
8083 case 1: // result = add base, cond
8084 case 2: // result = lea base( , cond*2)
8085 case 3: // result = lea base(cond, cond*2)
8086 case 4: // result = lea base( , cond*4)
8087 case 5: // result = lea base(cond, cond*4)
8088 case 8: // result = lea base( , cond*8)
8089 case 9: // result = lea base(cond, cond*8)
8090 isFastMultiplier = true;
8091 break;
8092 }
8093 }
8094
8095 if (isFastMultiplier) {
8096 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8097 if (NeedsCondInvert) // Invert the condition if needed.
8098 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8099 DAG.getConstant(1, Cond.getValueType()));
8100
8101 // Zero extend the condition if needed.
8102 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8103 Cond);
8104 // Scale the condition by the difference.
8105 if (Diff != 1)
8106 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8107 DAG.getConstant(Diff, Cond.getValueType()));
8108
8109 // Add the base if non-zero.
8110 if (FalseC->getAPIntValue() != 0)
8111 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8112 SDValue(FalseC, 0));
8113 return Cond;
8114 }
8115 }
Chris Lattnerd1980a52009-03-12 06:52:53 +00008116 }
8117 }
8118
Dan Gohman475871a2008-07-27 21:46:04 +00008119 return SDValue();
Chris Lattner83e6c992006-10-04 06:57:07 +00008120}
8121
Chris Lattnerd1980a52009-03-12 06:52:53 +00008122/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
8123static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
8124 TargetLowering::DAGCombinerInfo &DCI) {
8125 DebugLoc DL = N->getDebugLoc();
8126
8127 // If the flag operand isn't dead, don't touch this CMOV.
8128 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
8129 return SDValue();
8130
8131 // If this is a select between two integer constants, try to do some
8132 // optimizations. Note that the operands are ordered the opposite of SELECT
8133 // operands.
8134 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
8135 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8136 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
8137 // larger than FalseC (the false value).
8138 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
8139
8140 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
8141 CC = X86::GetOppositeBranchCondition(CC);
8142 std::swap(TrueC, FalseC);
8143 }
8144
8145 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
Chris Lattnercee56e72009-03-13 05:53:31 +00008146 // This is efficient for any integer data type (including i8/i16) and
8147 // shift amount.
Chris Lattnerd1980a52009-03-12 06:52:53 +00008148 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
8149 SDValue Cond = N->getOperand(3);
8150 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8151 DAG.getConstant(CC, MVT::i8), Cond);
8152
8153 // Zero extend the condition if needed.
8154 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
8155
8156 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8157 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
8158 DAG.getConstant(ShAmt, MVT::i8));
8159 if (N->getNumValues() == 2) // Dead flag value?
8160 return DCI.CombineTo(N, Cond, SDValue());
8161 return Cond;
8162 }
Chris Lattnercee56e72009-03-13 05:53:31 +00008163
8164 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
8165 // for any integer data type, including i8/i16.
Chris Lattner97a29a52009-03-13 05:22:11 +00008166 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8167 SDValue Cond = N->getOperand(3);
8168 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8169 DAG.getConstant(CC, MVT::i8), Cond);
8170
8171 // Zero extend the condition if needed.
Chris Lattnercee56e72009-03-13 05:53:31 +00008172 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8173 FalseC->getValueType(0), Cond);
Chris Lattner97a29a52009-03-13 05:22:11 +00008174 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8175 SDValue(FalseC, 0));
Chris Lattnercee56e72009-03-13 05:53:31 +00008176
Chris Lattner97a29a52009-03-13 05:22:11 +00008177 if (N->getNumValues() == 2) // Dead flag value?
8178 return DCI.CombineTo(N, Cond, SDValue());
8179 return Cond;
8180 }
Chris Lattnercee56e72009-03-13 05:53:31 +00008181
8182 // Optimize cases that will turn into an LEA instruction. This requires
8183 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8184 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8185 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8186 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8187
8188 bool isFastMultiplier = false;
8189 if (Diff < 10) {
8190 switch ((unsigned char)Diff) {
8191 default: break;
8192 case 1: // result = add base, cond
8193 case 2: // result = lea base( , cond*2)
8194 case 3: // result = lea base(cond, cond*2)
8195 case 4: // result = lea base( , cond*4)
8196 case 5: // result = lea base(cond, cond*4)
8197 case 8: // result = lea base( , cond*8)
8198 case 9: // result = lea base(cond, cond*8)
8199 isFastMultiplier = true;
8200 break;
8201 }
8202 }
8203
8204 if (isFastMultiplier) {
8205 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8206 SDValue Cond = N->getOperand(3);
8207 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8208 DAG.getConstant(CC, MVT::i8), Cond);
8209 // Zero extend the condition if needed.
8210 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8211 Cond);
8212 // Scale the condition by the difference.
8213 if (Diff != 1)
8214 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8215 DAG.getConstant(Diff, Cond.getValueType()));
8216
8217 // Add the base if non-zero.
8218 if (FalseC->getAPIntValue() != 0)
8219 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8220 SDValue(FalseC, 0));
8221 if (N->getNumValues() == 2) // Dead flag value?
8222 return DCI.CombineTo(N, Cond, SDValue());
8223 return Cond;
8224 }
8225 }
Chris Lattnerd1980a52009-03-12 06:52:53 +00008226 }
8227 }
8228 return SDValue();
8229}
8230
8231
Evan Cheng0b0cd912009-03-28 05:57:29 +00008232/// PerformMulCombine - Optimize a single multiply with constant into two
8233/// in order to implement it with two cheaper instructions, e.g.
8234/// LEA + SHL, LEA + LEA.
8235static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
8236 TargetLowering::DAGCombinerInfo &DCI) {
8237 if (DAG.getMachineFunction().
8238 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
8239 return SDValue();
8240
8241 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8242 return SDValue();
8243
8244 MVT VT = N->getValueType(0);
8245 if (VT != MVT::i64)
8246 return SDValue();
8247
8248 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8249 if (!C)
8250 return SDValue();
8251 uint64_t MulAmt = C->getZExtValue();
8252 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
8253 return SDValue();
8254
8255 uint64_t MulAmt1 = 0;
8256 uint64_t MulAmt2 = 0;
8257 if ((MulAmt % 9) == 0) {
8258 MulAmt1 = 9;
8259 MulAmt2 = MulAmt / 9;
8260 } else if ((MulAmt % 5) == 0) {
8261 MulAmt1 = 5;
8262 MulAmt2 = MulAmt / 5;
8263 } else if ((MulAmt % 3) == 0) {
8264 MulAmt1 = 3;
8265 MulAmt2 = MulAmt / 3;
8266 }
8267 if (MulAmt2 &&
8268 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
8269 DebugLoc DL = N->getDebugLoc();
8270
8271 if (isPowerOf2_64(MulAmt2) &&
8272 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
8273 // If second multiplifer is pow2, issue it first. We want the multiply by
8274 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
8275 // is an add.
8276 std::swap(MulAmt1, MulAmt2);
8277
8278 SDValue NewMul;
8279 if (isPowerOf2_64(MulAmt1))
8280 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
8281 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
8282 else
Evan Cheng73f24c92009-03-30 21:36:47 +00008283 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
Evan Cheng0b0cd912009-03-28 05:57:29 +00008284 DAG.getConstant(MulAmt1, VT));
8285
8286 if (isPowerOf2_64(MulAmt2))
8287 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
8288 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
8289 else
Evan Cheng73f24c92009-03-30 21:36:47 +00008290 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
Evan Cheng0b0cd912009-03-28 05:57:29 +00008291 DAG.getConstant(MulAmt2, VT));
8292
8293 // Do not add new nodes to DAG combiner worklist.
8294 DCI.CombineTo(N, NewMul, false);
8295 }
8296 return SDValue();
8297}
8298
8299
Nate Begeman740ab032009-01-26 00:52:55 +00008300/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
8301/// when possible.
8302static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
8303 const X86Subtarget *Subtarget) {
8304 // On X86 with SSE2 support, we can transform this to a vector shift if
8305 // all elements are shifted by the same amount. We can't do this in legalize
8306 // because the a constant vector is typically transformed to a constant pool
8307 // so we have no knowledge of the shift amount.
Nate Begemanc2fd67f2009-01-26 03:15:31 +00008308 if (!Subtarget->hasSSE2())
8309 return SDValue();
Scott Michelfdc40a02009-02-17 22:15:04 +00008310
Nate Begeman740ab032009-01-26 00:52:55 +00008311 MVT VT = N->getValueType(0);
Nate Begemanc2fd67f2009-01-26 03:15:31 +00008312 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
8313 return SDValue();
Scott Michelfdc40a02009-02-17 22:15:04 +00008314
Mon P Wang3becd092009-01-28 08:12:05 +00008315 SDValue ShAmtOp = N->getOperand(1);
8316 MVT EltVT = VT.getVectorElementType();
Chris Lattner47b4ce82009-03-11 05:48:52 +00008317 DebugLoc DL = N->getDebugLoc();
Mon P Wang3becd092009-01-28 08:12:05 +00008318 SDValue BaseShAmt;
8319 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
8320 unsigned NumElts = VT.getVectorNumElements();
8321 unsigned i = 0;
8322 for (; i != NumElts; ++i) {
8323 SDValue Arg = ShAmtOp.getOperand(i);
8324 if (Arg.getOpcode() == ISD::UNDEF) continue;
8325 BaseShAmt = Arg;
8326 break;
8327 }
8328 for (; i != NumElts; ++i) {
8329 SDValue Arg = ShAmtOp.getOperand(i);
8330 if (Arg.getOpcode() == ISD::UNDEF) continue;
8331 if (Arg != BaseShAmt) {
8332 return SDValue();
8333 }
8334 }
8335 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
Nate Begeman9008ca62009-04-27 18:41:29 +00008336 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
8337 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
8338 DAG.getIntPtrConstant(0));
Mon P Wang3becd092009-01-28 08:12:05 +00008339 } else
Nate Begemanc2fd67f2009-01-26 03:15:31 +00008340 return SDValue();
Nate Begeman740ab032009-01-26 00:52:55 +00008341
Nate Begemanc2fd67f2009-01-26 03:15:31 +00008342 if (EltVT.bitsGT(MVT::i32))
Chris Lattner47b4ce82009-03-11 05:48:52 +00008343 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
Nate Begemanc2fd67f2009-01-26 03:15:31 +00008344 else if (EltVT.bitsLT(MVT::i32))
Chris Lattner47b4ce82009-03-11 05:48:52 +00008345 BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, BaseShAmt);
Nate Begeman740ab032009-01-26 00:52:55 +00008346
Nate Begemanc2fd67f2009-01-26 03:15:31 +00008347 // The shift amount is identical so we can do a vector shift.
8348 SDValue ValOp = N->getOperand(0);
8349 switch (N->getOpcode()) {
8350 default:
8351 assert(0 && "Unknown shift opcode!");
8352 break;
8353 case ISD::SHL:
8354 if (VT == MVT::v2i64)
Chris Lattner47b4ce82009-03-11 05:48:52 +00008355 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
Nate Begeman740ab032009-01-26 00:52:55 +00008356 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8357 ValOp, BaseShAmt);
Nate Begemanc2fd67f2009-01-26 03:15:31 +00008358 if (VT == MVT::v4i32)
Chris Lattner47b4ce82009-03-11 05:48:52 +00008359 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
Nate Begeman740ab032009-01-26 00:52:55 +00008360 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8361 ValOp, BaseShAmt);
Nate Begemanc2fd67f2009-01-26 03:15:31 +00008362 if (VT == MVT::v8i16)
Chris Lattner47b4ce82009-03-11 05:48:52 +00008363 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
Nate Begeman740ab032009-01-26 00:52:55 +00008364 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8365 ValOp, BaseShAmt);
Nate Begemanc2fd67f2009-01-26 03:15:31 +00008366 break;
8367 case ISD::SRA:
8368 if (VT == MVT::v4i32)
Chris Lattner47b4ce82009-03-11 05:48:52 +00008369 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
Nate Begeman740ab032009-01-26 00:52:55 +00008370 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
8371 ValOp, BaseShAmt);
Nate Begemanc2fd67f2009-01-26 03:15:31 +00008372 if (VT == MVT::v8i16)
Chris Lattner47b4ce82009-03-11 05:48:52 +00008373 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
Nate Begeman740ab032009-01-26 00:52:55 +00008374 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
8375 ValOp, BaseShAmt);
Nate Begemanc2fd67f2009-01-26 03:15:31 +00008376 break;
8377 case ISD::SRL:
8378 if (VT == MVT::v2i64)
Chris Lattner47b4ce82009-03-11 05:48:52 +00008379 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
Nate Begeman740ab032009-01-26 00:52:55 +00008380 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8381 ValOp, BaseShAmt);
Nate Begemanc2fd67f2009-01-26 03:15:31 +00008382 if (VT == MVT::v4i32)
Chris Lattner47b4ce82009-03-11 05:48:52 +00008383 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
Nate Begeman740ab032009-01-26 00:52:55 +00008384 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
8385 ValOp, BaseShAmt);
Nate Begemanc2fd67f2009-01-26 03:15:31 +00008386 if (VT == MVT::v8i16)
Chris Lattner47b4ce82009-03-11 05:48:52 +00008387 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
Nate Begeman740ab032009-01-26 00:52:55 +00008388 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
8389 ValOp, BaseShAmt);
Nate Begemanc2fd67f2009-01-26 03:15:31 +00008390 break;
Nate Begeman740ab032009-01-26 00:52:55 +00008391 }
8392 return SDValue();
8393}
8394
Chris Lattner149a4e52008-02-22 02:09:43 +00008395/// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
Dan Gohman475871a2008-07-27 21:46:04 +00008396static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
Evan Cheng536e6672009-03-12 05:59:15 +00008397 const X86Subtarget *Subtarget) {
Chris Lattner149a4e52008-02-22 02:09:43 +00008398 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
8399 // the FP state in cases where an emms may be missing.
Dale Johannesen079f2a62008-02-25 19:20:14 +00008400 // A preferable solution to the general problem is to figure out the right
8401 // places to insert EMMS. This qualifies as a quick hack.
Evan Cheng536e6672009-03-12 05:59:15 +00008402
8403 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
Evan Cheng7e2ff772008-05-08 00:57:18 +00008404 StoreSDNode *St = cast<StoreSDNode>(N);
Evan Cheng536e6672009-03-12 05:59:15 +00008405 MVT VT = St->getValue().getValueType();
8406 if (VT.getSizeInBits() != 64)
8407 return SDValue();
8408
Devang Patel578efa92009-06-05 21:57:13 +00008409 const Function *F = DAG.getMachineFunction().getFunction();
8410 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
8411 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
8412 && Subtarget->hasSSE2();
Evan Cheng536e6672009-03-12 05:59:15 +00008413 if ((VT.isVector() ||
8414 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
Dale Johannesen079f2a62008-02-25 19:20:14 +00008415 isa<LoadSDNode>(St->getValue()) &&
8416 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
8417 St->getChain().hasOneUse() && !St->isVolatile()) {
Gabor Greifba36cb52008-08-28 21:40:38 +00008418 SDNode* LdVal = St->getValue().getNode();
Dale Johannesen079f2a62008-02-25 19:20:14 +00008419 LoadSDNode *Ld = 0;
8420 int TokenFactorIndex = -1;
Dan Gohman475871a2008-07-27 21:46:04 +00008421 SmallVector<SDValue, 8> Ops;
Gabor Greifba36cb52008-08-28 21:40:38 +00008422 SDNode* ChainVal = St->getChain().getNode();
Dale Johannesen079f2a62008-02-25 19:20:14 +00008423 // Must be a store of a load. We currently handle two cases: the load
8424 // is a direct child, and it's under an intervening TokenFactor. It is
8425 // possible to dig deeper under nested TokenFactors.
Dale Johannesen14e2ea92008-02-25 22:29:22 +00008426 if (ChainVal == LdVal)
Dale Johannesen079f2a62008-02-25 19:20:14 +00008427 Ld = cast<LoadSDNode>(St->getChain());
8428 else if (St->getValue().hasOneUse() &&
8429 ChainVal->getOpcode() == ISD::TokenFactor) {
8430 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
Gabor Greifba36cb52008-08-28 21:40:38 +00008431 if (ChainVal->getOperand(i).getNode() == LdVal) {
Dale Johannesen079f2a62008-02-25 19:20:14 +00008432 TokenFactorIndex = i;
8433 Ld = cast<LoadSDNode>(St->getValue());
8434 } else
8435 Ops.push_back(ChainVal->getOperand(i));
8436 }
8437 }
Dale Johannesen079f2a62008-02-25 19:20:14 +00008438
Evan Cheng536e6672009-03-12 05:59:15 +00008439 if (!Ld || !ISD::isNormalLoad(Ld))
8440 return SDValue();
Dale Johannesen079f2a62008-02-25 19:20:14 +00008441
Evan Cheng536e6672009-03-12 05:59:15 +00008442 // If this is not the MMX case, i.e. we are just turning i64 load/store
8443 // into f64 load/store, avoid the transformation if there are multiple
8444 // uses of the loaded value.
8445 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
8446 return SDValue();
Dale Johannesen079f2a62008-02-25 19:20:14 +00008447
Evan Cheng536e6672009-03-12 05:59:15 +00008448 DebugLoc LdDL = Ld->getDebugLoc();
8449 DebugLoc StDL = N->getDebugLoc();
8450 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
8451 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
8452 // pair instead.
8453 if (Subtarget->is64Bit() || F64IsLegal) {
8454 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
8455 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
8456 Ld->getBasePtr(), Ld->getSrcValue(),
8457 Ld->getSrcValueOffset(), Ld->isVolatile(),
8458 Ld->getAlignment());
8459 SDValue NewChain = NewLd.getValue(1);
Dale Johannesen079f2a62008-02-25 19:20:14 +00008460 if (TokenFactorIndex != -1) {
Evan Cheng536e6672009-03-12 05:59:15 +00008461 Ops.push_back(NewChain);
8462 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
Dale Johannesen079f2a62008-02-25 19:20:14 +00008463 Ops.size());
8464 }
Evan Cheng536e6672009-03-12 05:59:15 +00008465 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
Chris Lattner149a4e52008-02-22 02:09:43 +00008466 St->getSrcValue(), St->getSrcValueOffset(),
8467 St->isVolatile(), St->getAlignment());
8468 }
Evan Cheng536e6672009-03-12 05:59:15 +00008469
8470 // Otherwise, lower to two pairs of 32-bit loads / stores.
8471 SDValue LoAddr = Ld->getBasePtr();
8472 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
8473 DAG.getConstant(4, MVT::i32));
8474
8475 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
8476 Ld->getSrcValue(), Ld->getSrcValueOffset(),
8477 Ld->isVolatile(), Ld->getAlignment());
8478 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
8479 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
8480 Ld->isVolatile(),
8481 MinAlign(Ld->getAlignment(), 4));
8482
8483 SDValue NewChain = LoLd.getValue(1);
8484 if (TokenFactorIndex != -1) {
8485 Ops.push_back(LoLd);
8486 Ops.push_back(HiLd);
8487 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8488 Ops.size());
8489 }
8490
8491 LoAddr = St->getBasePtr();
8492 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
8493 DAG.getConstant(4, MVT::i32));
8494
8495 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
8496 St->getSrcValue(), St->getSrcValueOffset(),
8497 St->isVolatile(), St->getAlignment());
8498 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
8499 St->getSrcValue(),
8500 St->getSrcValueOffset() + 4,
8501 St->isVolatile(),
8502 MinAlign(St->getAlignment(), 4));
8503 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
Chris Lattner149a4e52008-02-22 02:09:43 +00008504 }
Dan Gohman475871a2008-07-27 21:46:04 +00008505 return SDValue();
Chris Lattner149a4e52008-02-22 02:09:43 +00008506}
8507
Chris Lattner6cf73262008-01-25 06:14:17 +00008508/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
8509/// X86ISD::FXOR nodes.
Dan Gohman475871a2008-07-27 21:46:04 +00008510static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
Chris Lattner6cf73262008-01-25 06:14:17 +00008511 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
8512 // F[X]OR(0.0, x) -> x
8513 // F[X]OR(x, 0.0) -> x
Chris Lattneraf723b92008-01-25 05:46:26 +00008514 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8515 if (C->getValueAPF().isPosZero())
8516 return N->getOperand(1);
8517 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8518 if (C->getValueAPF().isPosZero())
8519 return N->getOperand(0);
Dan Gohman475871a2008-07-27 21:46:04 +00008520 return SDValue();
Chris Lattneraf723b92008-01-25 05:46:26 +00008521}
8522
8523/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
Dan Gohman475871a2008-07-27 21:46:04 +00008524static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
Chris Lattneraf723b92008-01-25 05:46:26 +00008525 // FAND(0.0, x) -> 0.0
8526 // FAND(x, 0.0) -> 0.0
8527 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8528 if (C->getValueAPF().isPosZero())
8529 return N->getOperand(0);
8530 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8531 if (C->getValueAPF().isPosZero())
8532 return N->getOperand(1);
Dan Gohman475871a2008-07-27 21:46:04 +00008533 return SDValue();
Chris Lattneraf723b92008-01-25 05:46:26 +00008534}
8535
Dan Gohmane5af2d32009-01-29 01:59:02 +00008536static SDValue PerformBTCombine(SDNode *N,
8537 SelectionDAG &DAG,
8538 TargetLowering::DAGCombinerInfo &DCI) {
8539 // BT ignores high bits in the bit index operand.
8540 SDValue Op1 = N->getOperand(1);
8541 if (Op1.hasOneUse()) {
8542 unsigned BitWidth = Op1.getValueSizeInBits();
8543 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
8544 APInt KnownZero, KnownOne;
8545 TargetLowering::TargetLoweringOpt TLO(DAG);
8546 TargetLowering &TLI = DAG.getTargetLoweringInfo();
8547 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
8548 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
8549 DCI.CommitTargetLoweringOpt(TLO);
8550 }
8551 return SDValue();
8552}
Chris Lattner83e6c992006-10-04 06:57:07 +00008553
Eli Friedman7a5e5552009-06-07 06:52:44 +00008554static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
8555 SDValue Op = N->getOperand(0);
8556 if (Op.getOpcode() == ISD::BIT_CONVERT)
8557 Op = Op.getOperand(0);
8558 MVT VT = N->getValueType(0), OpVT = Op.getValueType();
8559 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
8560 VT.getVectorElementType().getSizeInBits() ==
8561 OpVT.getVectorElementType().getSizeInBits()) {
8562 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
8563 }
8564 return SDValue();
8565}
8566
Owen Anderson99177002009-06-29 18:04:45 +00008567// On X86 and X86-64, atomic operations are lowered to locked instructions.
8568// Locked instructions, in turn, have implicit fence semantics (all memory
8569// operations are flushed before issuing the locked instruction, and the
8570// are not buffered), so we can fold away the common pattern of
8571// fence-atomic-fence.
8572static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
8573 SDValue atomic = N->getOperand(0);
8574 switch (atomic.getOpcode()) {
8575 case ISD::ATOMIC_CMP_SWAP:
8576 case ISD::ATOMIC_SWAP:
8577 case ISD::ATOMIC_LOAD_ADD:
8578 case ISD::ATOMIC_LOAD_SUB:
8579 case ISD::ATOMIC_LOAD_AND:
8580 case ISD::ATOMIC_LOAD_OR:
8581 case ISD::ATOMIC_LOAD_XOR:
8582 case ISD::ATOMIC_LOAD_NAND:
8583 case ISD::ATOMIC_LOAD_MIN:
8584 case ISD::ATOMIC_LOAD_MAX:
8585 case ISD::ATOMIC_LOAD_UMIN:
8586 case ISD::ATOMIC_LOAD_UMAX:
8587 break;
8588 default:
8589 return SDValue();
8590 }
8591
8592 SDValue fence = atomic.getOperand(0);
8593 if (fence.getOpcode() != ISD::MEMBARRIER)
8594 return SDValue();
8595
8596 switch (atomic.getOpcode()) {
8597 case ISD::ATOMIC_CMP_SWAP:
8598 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
8599 atomic.getOperand(1), atomic.getOperand(2),
8600 atomic.getOperand(3));
8601 case ISD::ATOMIC_SWAP:
8602 case ISD::ATOMIC_LOAD_ADD:
8603 case ISD::ATOMIC_LOAD_SUB:
8604 case ISD::ATOMIC_LOAD_AND:
8605 case ISD::ATOMIC_LOAD_OR:
8606 case ISD::ATOMIC_LOAD_XOR:
8607 case ISD::ATOMIC_LOAD_NAND:
8608 case ISD::ATOMIC_LOAD_MIN:
8609 case ISD::ATOMIC_LOAD_MAX:
8610 case ISD::ATOMIC_LOAD_UMIN:
8611 case ISD::ATOMIC_LOAD_UMAX:
8612 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
8613 atomic.getOperand(1), atomic.getOperand(2));
8614 default:
8615 return SDValue();
8616 }
8617}
8618
Dan Gohman475871a2008-07-27 21:46:04 +00008619SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
Evan Cheng9dd93b32008-11-05 06:03:38 +00008620 DAGCombinerInfo &DCI) const {
Evan Cheng206ee9d2006-07-07 08:33:52 +00008621 SelectionDAG &DAG = DCI.DAG;
8622 switch (N->getOpcode()) {
8623 default: break;
Evan Chengad4196b2008-05-12 19:56:52 +00008624 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
Chris Lattneraf723b92008-01-25 05:46:26 +00008625 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
Chris Lattnerd1980a52009-03-12 06:52:53 +00008626 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
Evan Cheng0b0cd912009-03-28 05:57:29 +00008627 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
Nate Begeman740ab032009-01-26 00:52:55 +00008628 case ISD::SHL:
8629 case ISD::SRA:
8630 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
Evan Cheng7e2ff772008-05-08 00:57:18 +00008631 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
Chris Lattner6cf73262008-01-25 06:14:17 +00008632 case X86ISD::FXOR:
Chris Lattneraf723b92008-01-25 05:46:26 +00008633 case X86ISD::FOR: return PerformFORCombine(N, DAG);
8634 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
Dan Gohmane5af2d32009-01-29 01:59:02 +00008635 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
Eli Friedman7a5e5552009-06-07 06:52:44 +00008636 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
Owen Anderson99177002009-06-29 18:04:45 +00008637 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
Evan Cheng206ee9d2006-07-07 08:33:52 +00008638 }
8639
Dan Gohman475871a2008-07-27 21:46:04 +00008640 return SDValue();
Evan Cheng206ee9d2006-07-07 08:33:52 +00008641}
8642
Evan Cheng60c07e12006-07-05 22:17:51 +00008643//===----------------------------------------------------------------------===//
8644// X86 Inline Assembly Support
8645//===----------------------------------------------------------------------===//
8646
Chris Lattnerf4dff842006-07-11 02:54:03 +00008647/// getConstraintType - Given a constraint letter, return the type of
8648/// constraint it is for this target.
8649X86TargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +00008650X86TargetLowering::getConstraintType(const std::string &Constraint) const {
8651 if (Constraint.size() == 1) {
8652 switch (Constraint[0]) {
8653 case 'A':
Dale Johannesen330169f2008-11-13 21:52:36 +00008654 return C_Register;
Chris Lattnerfce84ac2008-03-11 19:06:29 +00008655 case 'f':
Chris Lattner4234f572007-03-25 02:14:49 +00008656 case 'r':
8657 case 'R':
8658 case 'l':
8659 case 'q':
8660 case 'Q':
8661 case 'x':
Dale Johannesen2ffbcac2008-04-01 00:57:48 +00008662 case 'y':
Chris Lattner4234f572007-03-25 02:14:49 +00008663 case 'Y':
8664 return C_RegisterClass;
Dale Johannesen78e3e522009-02-12 20:58:09 +00008665 case 'e':
8666 case 'Z':
8667 return C_Other;
Chris Lattner4234f572007-03-25 02:14:49 +00008668 default:
8669 break;
8670 }
Chris Lattnerf4dff842006-07-11 02:54:03 +00008671 }
Chris Lattner4234f572007-03-25 02:14:49 +00008672 return TargetLowering::getConstraintType(Constraint);
Chris Lattnerf4dff842006-07-11 02:54:03 +00008673}
8674
Dale Johannesenba2a0b92008-01-29 02:21:21 +00008675/// LowerXConstraint - try to replace an X constraint, which matches anything,
8676/// with another that has more specific requirements based on the type of the
8677/// corresponding operand.
Chris Lattner5e764232008-04-26 23:02:14 +00008678const char *X86TargetLowering::
Duncan Sands83ec4b62008-06-06 12:08:01 +00008679LowerXConstraint(MVT ConstraintVT) const {
Chris Lattner5e764232008-04-26 23:02:14 +00008680 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
8681 // 'f' like normal targets.
Duncan Sands83ec4b62008-06-06 12:08:01 +00008682 if (ConstraintVT.isFloatingPoint()) {
Dale Johannesenba2a0b92008-01-29 02:21:21 +00008683 if (Subtarget->hasSSE2())
Chris Lattner5e764232008-04-26 23:02:14 +00008684 return "Y";
8685 if (Subtarget->hasSSE1())
8686 return "x";
8687 }
Scott Michelfdc40a02009-02-17 22:15:04 +00008688
Chris Lattner5e764232008-04-26 23:02:14 +00008689 return TargetLowering::LowerXConstraint(ConstraintVT);
Dale Johannesenba2a0b92008-01-29 02:21:21 +00008690}
8691
Chris Lattner48884cd2007-08-25 00:47:38 +00008692/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8693/// vector. If it is invalid, don't add anything to Ops.
Dan Gohman475871a2008-07-27 21:46:04 +00008694void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Chris Lattner48884cd2007-08-25 00:47:38 +00008695 char Constraint,
Evan Chengda43bcf2008-09-24 00:05:32 +00008696 bool hasMemory,
Dan Gohman475871a2008-07-27 21:46:04 +00008697 std::vector<SDValue>&Ops,
Chris Lattner5e764232008-04-26 23:02:14 +00008698 SelectionDAG &DAG) const {
Dan Gohman475871a2008-07-27 21:46:04 +00008699 SDValue Result(0, 0);
Scott Michelfdc40a02009-02-17 22:15:04 +00008700
Chris Lattner22aaf1d2006-10-31 20:13:11 +00008701 switch (Constraint) {
8702 default: break;
Devang Patel84f7fd22007-03-17 00:13:28 +00008703 case 'I':
Chris Lattner188b9fe2007-03-25 01:57:35 +00008704 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00008705 if (C->getZExtValue() <= 31) {
8706 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
Chris Lattner48884cd2007-08-25 00:47:38 +00008707 break;
8708 }
Devang Patel84f7fd22007-03-17 00:13:28 +00008709 }
Chris Lattner48884cd2007-08-25 00:47:38 +00008710 return;
Evan Cheng364091e2008-09-22 23:57:37 +00008711 case 'J':
8712 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
Chris Lattner2e06dd22009-06-15 04:39:05 +00008713 if (C->getZExtValue() <= 63) {
Chris Lattnere4935152009-06-15 04:01:39 +00008714 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8715 break;
8716 }
8717 }
8718 return;
8719 case 'K':
8720 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
Chris Lattner2e06dd22009-06-15 04:39:05 +00008721 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
Evan Cheng364091e2008-09-22 23:57:37 +00008722 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8723 break;
8724 }
8725 }
8726 return;
Chris Lattner188b9fe2007-03-25 01:57:35 +00008727 case 'N':
8728 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00008729 if (C->getZExtValue() <= 255) {
8730 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
Chris Lattner48884cd2007-08-25 00:47:38 +00008731 break;
8732 }
Chris Lattner188b9fe2007-03-25 01:57:35 +00008733 }
Chris Lattner48884cd2007-08-25 00:47:38 +00008734 return;
Dale Johannesen78e3e522009-02-12 20:58:09 +00008735 case 'e': {
8736 // 32-bit signed value
8737 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8738 const ConstantInt *CI = C->getConstantIntValue();
8739 if (CI->isValueValidForType(Type::Int32Ty, C->getSExtValue())) {
8740 // Widen to 64 bits here to get it sign extended.
8741 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
8742 break;
8743 }
8744 // FIXME gcc accepts some relocatable values here too, but only in certain
8745 // memory models; it's complicated.
8746 }
8747 return;
8748 }
8749 case 'Z': {
8750 // 32-bit unsigned value
8751 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8752 const ConstantInt *CI = C->getConstantIntValue();
8753 if (CI->isValueValidForType(Type::Int32Ty, C->getZExtValue())) {
8754 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8755 break;
8756 }
8757 }
8758 // FIXME gcc accepts some relocatable values here too, but only in certain
8759 // memory models; it's complicated.
8760 return;
8761 }
Chris Lattnerdc43a882007-05-03 16:52:29 +00008762 case 'i': {
Chris Lattner22aaf1d2006-10-31 20:13:11 +00008763 // Literal immediates are always ok.
Chris Lattner48884cd2007-08-25 00:47:38 +00008764 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
Dale Johannesen78e3e522009-02-12 20:58:09 +00008765 // Widen to 64 bits here to get it sign extended.
8766 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
Chris Lattner48884cd2007-08-25 00:47:38 +00008767 break;
8768 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00008769
Chris Lattnerdc43a882007-05-03 16:52:29 +00008770 // If we are in non-pic codegen mode, we allow the address of a global (with
8771 // an optional displacement) to be used with 'i'.
Chris Lattner49921962009-05-08 18:23:14 +00008772 GlobalAddressSDNode *GA = 0;
Chris Lattnerdc43a882007-05-03 16:52:29 +00008773 int64_t Offset = 0;
Scott Michelfdc40a02009-02-17 22:15:04 +00008774
Chris Lattner49921962009-05-08 18:23:14 +00008775 // Match either (GA), (GA+C), (GA+C1+C2), etc.
8776 while (1) {
8777 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
8778 Offset += GA->getOffset();
8779 break;
8780 } else if (Op.getOpcode() == ISD::ADD) {
8781 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
8782 Offset += C->getZExtValue();
8783 Op = Op.getOperand(0);
8784 continue;
8785 }
8786 } else if (Op.getOpcode() == ISD::SUB) {
8787 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
8788 Offset += -C->getZExtValue();
8789 Op = Op.getOperand(0);
8790 continue;
8791 }
Chris Lattnerdc43a882007-05-03 16:52:29 +00008792 }
Dale Johannesen76a1e2e2009-07-07 00:18:49 +00008793
Chris Lattner49921962009-05-08 18:23:14 +00008794 // Otherwise, this isn't something we can handle, reject it.
8795 return;
Chris Lattnerdc43a882007-05-03 16:52:29 +00008796 }
Dale Johannesen76a1e2e2009-07-07 00:18:49 +00008797 // If we require an extra load to get this address, as in PIC mode, we
8798 // can't accept it.
8799 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(),
8800 getTargetMachine(), false))
8801 return;
Scott Michelfdc40a02009-02-17 22:15:04 +00008802
Chris Lattner49921962009-05-08 18:23:14 +00008803 if (hasMemory)
8804 Op = LowerGlobalAddress(GA->getGlobal(), Op.getDebugLoc(), Offset, DAG);
8805 else
8806 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
8807 Offset);
8808 Result = Op;
8809 break;
Chris Lattner22aaf1d2006-10-31 20:13:11 +00008810 }
Chris Lattnerdc43a882007-05-03 16:52:29 +00008811 }
Scott Michelfdc40a02009-02-17 22:15:04 +00008812
Gabor Greifba36cb52008-08-28 21:40:38 +00008813 if (Result.getNode()) {
Chris Lattner48884cd2007-08-25 00:47:38 +00008814 Ops.push_back(Result);
8815 return;
8816 }
Evan Chengda43bcf2008-09-24 00:05:32 +00008817 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
8818 Ops, DAG);
Chris Lattner22aaf1d2006-10-31 20:13:11 +00008819}
8820
Chris Lattner259e97c2006-01-31 19:43:35 +00008821std::vector<unsigned> X86TargetLowering::
Chris Lattner1efa40f2006-02-22 00:56:39 +00008822getRegClassForInlineAsmConstraint(const std::string &Constraint,
Duncan Sands83ec4b62008-06-06 12:08:01 +00008823 MVT VT) const {
Chris Lattner259e97c2006-01-31 19:43:35 +00008824 if (Constraint.size() == 1) {
8825 // FIXME: not handling fp-stack yet!
Chris Lattner259e97c2006-01-31 19:43:35 +00008826 switch (Constraint[0]) { // GCC X86 Constraint Letters
Chris Lattnerf4dff842006-07-11 02:54:03 +00008827 default: break; // Unknown constraint letter
Chris Lattner259e97c2006-01-31 19:43:35 +00008828 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
8829 case 'Q': // Q_REGS
Chris Lattner80a7ecc2006-05-06 00:29:37 +00008830 if (VT == MVT::i32)
8831 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
8832 else if (VT == MVT::i16)
8833 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
8834 else if (VT == MVT::i8)
Evan Cheng12914382007-08-13 23:27:11 +00008835 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
Chris Lattner03e6c702007-11-04 06:51:12 +00008836 else if (VT == MVT::i64)
8837 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
8838 break;
Chris Lattner259e97c2006-01-31 19:43:35 +00008839 }
8840 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00008841
Chris Lattner1efa40f2006-02-22 00:56:39 +00008842 return std::vector<unsigned>();
Chris Lattner259e97c2006-01-31 19:43:35 +00008843}
Chris Lattnerf76d1802006-07-31 23:26:50 +00008844
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00008845std::pair<unsigned, const TargetRegisterClass*>
Chris Lattnerf76d1802006-07-31 23:26:50 +00008846X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
Duncan Sands83ec4b62008-06-06 12:08:01 +00008847 MVT VT) const {
Chris Lattnerad043e82007-04-09 05:11:28 +00008848 // First, see if this is a constraint that directly corresponds to an LLVM
8849 // register class.
8850 if (Constraint.size() == 1) {
8851 // GCC Constraint Letters
8852 switch (Constraint[0]) {
8853 default: break;
Chris Lattner0f65cad2007-04-09 05:49:22 +00008854 case 'r': // GENERAL_REGS
8855 case 'R': // LEGACY_REGS
8856 case 'l': // INDEX_REGS
Chris Lattner1fa71982008-10-17 18:15:05 +00008857 if (VT == MVT::i8)
Chris Lattner0f65cad2007-04-09 05:49:22 +00008858 return std::make_pair(0U, X86::GR8RegisterClass);
Chris Lattner1fa71982008-10-17 18:15:05 +00008859 if (VT == MVT::i16)
8860 return std::make_pair(0U, X86::GR16RegisterClass);
8861 if (VT == MVT::i32 || !Subtarget->is64Bit())
Scott Michelfdc40a02009-02-17 22:15:04 +00008862 return std::make_pair(0U, X86::GR32RegisterClass);
Chris Lattner1fa71982008-10-17 18:15:05 +00008863 return std::make_pair(0U, X86::GR64RegisterClass);
Chris Lattnerfce84ac2008-03-11 19:06:29 +00008864 case 'f': // FP Stack registers.
8865 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
8866 // value to the correct fpstack register class.
8867 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
8868 return std::make_pair(0U, X86::RFP32RegisterClass);
8869 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
8870 return std::make_pair(0U, X86::RFP64RegisterClass);
8871 return std::make_pair(0U, X86::RFP80RegisterClass);
Chris Lattner6c284d72007-04-12 04:14:49 +00008872 case 'y': // MMX_REGS if MMX allowed.
8873 if (!Subtarget->hasMMX()) break;
8874 return std::make_pair(0U, X86::VR64RegisterClass);
Chris Lattner0f65cad2007-04-09 05:49:22 +00008875 case 'Y': // SSE_REGS if SSE2 allowed
8876 if (!Subtarget->hasSSE2()) break;
8877 // FALL THROUGH.
8878 case 'x': // SSE_REGS if SSE1 allowed
8879 if (!Subtarget->hasSSE1()) break;
Duncan Sands83ec4b62008-06-06 12:08:01 +00008880
8881 switch (VT.getSimpleVT()) {
Chris Lattner0f65cad2007-04-09 05:49:22 +00008882 default: break;
8883 // Scalar SSE types.
8884 case MVT::f32:
8885 case MVT::i32:
Chris Lattnerad043e82007-04-09 05:11:28 +00008886 return std::make_pair(0U, X86::FR32RegisterClass);
Chris Lattner0f65cad2007-04-09 05:49:22 +00008887 case MVT::f64:
8888 case MVT::i64:
Chris Lattnerad043e82007-04-09 05:11:28 +00008889 return std::make_pair(0U, X86::FR64RegisterClass);
Chris Lattner0f65cad2007-04-09 05:49:22 +00008890 // Vector types.
Chris Lattner0f65cad2007-04-09 05:49:22 +00008891 case MVT::v16i8:
8892 case MVT::v8i16:
8893 case MVT::v4i32:
8894 case MVT::v2i64:
8895 case MVT::v4f32:
8896 case MVT::v2f64:
8897 return std::make_pair(0U, X86::VR128RegisterClass);
8898 }
Chris Lattnerad043e82007-04-09 05:11:28 +00008899 break;
8900 }
8901 }
Scott Michelfdc40a02009-02-17 22:15:04 +00008902
Chris Lattnerf76d1802006-07-31 23:26:50 +00008903 // Use the default implementation in TargetLowering to convert the register
8904 // constraint into a member of a register class.
8905 std::pair<unsigned, const TargetRegisterClass*> Res;
8906 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
Chris Lattner1a60aa72006-10-31 19:42:44 +00008907
8908 // Not found as a standard register?
8909 if (Res.second == 0) {
8910 // GCC calls "st(0)" just plain "st".
8911 if (StringsEqualNoCase("{st}", Constraint)) {
8912 Res.first = X86::ST0;
Chris Lattner9b4baf12007-09-24 05:27:37 +00008913 Res.second = X86::RFP80RegisterClass;
Chris Lattner1a60aa72006-10-31 19:42:44 +00008914 }
Dale Johannesen330169f2008-11-13 21:52:36 +00008915 // 'A' means EAX + EDX.
8916 if (Constraint == "A") {
8917 Res.first = X86::EAX;
8918 Res.second = X86::GRADRegisterClass;
8919 }
Chris Lattner1a60aa72006-10-31 19:42:44 +00008920 return Res;
8921 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00008922
Chris Lattnerf76d1802006-07-31 23:26:50 +00008923 // Otherwise, check to see if this is a register class of the wrong value
8924 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
8925 // turn into {ax},{dx}.
8926 if (Res.second->hasType(VT))
8927 return Res; // Correct type already, nothing to do.
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00008928
Chris Lattnerf76d1802006-07-31 23:26:50 +00008929 // All of the single-register GCC register classes map their values onto
8930 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
8931 // really want an 8-bit or 32-bit register, map to the appropriate register
8932 // class and return the appropriate register.
Chris Lattner6ba50a92008-08-26 06:19:02 +00008933 if (Res.second == X86::GR16RegisterClass) {
8934 if (VT == MVT::i8) {
8935 unsigned DestReg = 0;
8936 switch (Res.first) {
8937 default: break;
8938 case X86::AX: DestReg = X86::AL; break;
8939 case X86::DX: DestReg = X86::DL; break;
8940 case X86::CX: DestReg = X86::CL; break;
8941 case X86::BX: DestReg = X86::BL; break;
8942 }
8943 if (DestReg) {
8944 Res.first = DestReg;
Duncan Sands005e7982009-04-21 09:44:39 +00008945 Res.second = X86::GR8RegisterClass;
Chris Lattner6ba50a92008-08-26 06:19:02 +00008946 }
8947 } else if (VT == MVT::i32) {
8948 unsigned DestReg = 0;
8949 switch (Res.first) {
8950 default: break;
8951 case X86::AX: DestReg = X86::EAX; break;
8952 case X86::DX: DestReg = X86::EDX; break;
8953 case X86::CX: DestReg = X86::ECX; break;
8954 case X86::BX: DestReg = X86::EBX; break;
8955 case X86::SI: DestReg = X86::ESI; break;
8956 case X86::DI: DestReg = X86::EDI; break;
8957 case X86::BP: DestReg = X86::EBP; break;
8958 case X86::SP: DestReg = X86::ESP; break;
8959 }
8960 if (DestReg) {
8961 Res.first = DestReg;
Duncan Sands005e7982009-04-21 09:44:39 +00008962 Res.second = X86::GR32RegisterClass;
Chris Lattner6ba50a92008-08-26 06:19:02 +00008963 }
8964 } else if (VT == MVT::i64) {
8965 unsigned DestReg = 0;
8966 switch (Res.first) {
8967 default: break;
8968 case X86::AX: DestReg = X86::RAX; break;
8969 case X86::DX: DestReg = X86::RDX; break;
8970 case X86::CX: DestReg = X86::RCX; break;
8971 case X86::BX: DestReg = X86::RBX; break;
8972 case X86::SI: DestReg = X86::RSI; break;
8973 case X86::DI: DestReg = X86::RDI; break;
8974 case X86::BP: DestReg = X86::RBP; break;
8975 case X86::SP: DestReg = X86::RSP; break;
8976 }
8977 if (DestReg) {
8978 Res.first = DestReg;
Duncan Sands005e7982009-04-21 09:44:39 +00008979 Res.second = X86::GR64RegisterClass;
Chris Lattner6ba50a92008-08-26 06:19:02 +00008980 }
Chris Lattnerf76d1802006-07-31 23:26:50 +00008981 }
Chris Lattner6ba50a92008-08-26 06:19:02 +00008982 } else if (Res.second == X86::FR32RegisterClass ||
8983 Res.second == X86::FR64RegisterClass ||
8984 Res.second == X86::VR128RegisterClass) {
8985 // Handle references to XMM physical registers that got mapped into the
8986 // wrong class. This can happen with constraints like {xmm0} where the
8987 // target independent register mapper will just pick the first match it can
8988 // find, ignoring the required type.
8989 if (VT == MVT::f32)
8990 Res.second = X86::FR32RegisterClass;
8991 else if (VT == MVT::f64)
8992 Res.second = X86::FR64RegisterClass;
8993 else if (X86::VR128RegisterClass->hasType(VT))
8994 Res.second = X86::VR128RegisterClass;
Chris Lattnerf76d1802006-07-31 23:26:50 +00008995 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00008996
Chris Lattnerf76d1802006-07-31 23:26:50 +00008997 return Res;
8998}
Mon P Wang0c397192008-10-30 08:01:45 +00008999
9000//===----------------------------------------------------------------------===//
9001// X86 Widen vector type
9002//===----------------------------------------------------------------------===//
9003
9004/// getWidenVectorType: given a vector type, returns the type to widen
9005/// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
9006/// If there is no vector type that we want to widen to, returns MVT::Other
Mon P Wangf007a8b2008-11-06 05:31:54 +00009007/// When and where to widen is target dependent based on the cost of
Mon P Wang0c397192008-10-30 08:01:45 +00009008/// scalarizing vs using the wider vector type.
9009
Dan Gohmanc13cf132009-01-15 17:34:08 +00009010MVT X86TargetLowering::getWidenVectorType(MVT VT) const {
Mon P Wang0c397192008-10-30 08:01:45 +00009011 assert(VT.isVector());
9012 if (isTypeLegal(VT))
9013 return VT;
Scott Michelfdc40a02009-02-17 22:15:04 +00009014
Mon P Wang0c397192008-10-30 08:01:45 +00009015 // TODO: In computeRegisterProperty, we can compute the list of legal vector
9016 // type based on element type. This would speed up our search (though
9017 // it may not be worth it since the size of the list is relatively
9018 // small).
9019 MVT EltVT = VT.getVectorElementType();
9020 unsigned NElts = VT.getVectorNumElements();
Scott Michelfdc40a02009-02-17 22:15:04 +00009021
Mon P Wang0c397192008-10-30 08:01:45 +00009022 // On X86, it make sense to widen any vector wider than 1
9023 if (NElts <= 1)
9024 return MVT::Other;
Scott Michelfdc40a02009-02-17 22:15:04 +00009025
9026 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
Mon P Wang0c397192008-10-30 08:01:45 +00009027 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
9028 MVT SVT = (MVT::SimpleValueType)nVT;
Scott Michelfdc40a02009-02-17 22:15:04 +00009029
9030 if (isTypeLegal(SVT) &&
9031 SVT.getVectorElementType() == EltVT &&
Mon P Wang0c397192008-10-30 08:01:45 +00009032 SVT.getVectorNumElements() > NElts)
9033 return SVT;
9034 }
9035 return MVT::Other;
9036}