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Jia Liubb481f82012-02-28 07:46:26 +00001//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00007//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00008//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00009//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +000013//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000014
15#define DEBUG_TYPE "mips-lower"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000016#include "MipsISelLowering.h"
Bruno Cardoso Lopesa2b1bb52007-08-28 05:08:16 +000017#include "MipsMachineFunction.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000018#include "MipsTargetMachine.h"
Chris Lattnerb71b9092009-08-13 06:28:06 +000019#include "MipsTargetObjectFile.h"
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000020#include "MipsSubtarget.h"
Craig Topper79aa3412012-03-17 18:46:09 +000021#include "InstPrinter/MipsInstPrinter.h"
22#include "MCTargetDesc/MipsBaseInfo.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000023#include "llvm/DerivedTypes.h"
24#include "llvm/Function.h"
Bruno Cardoso Lopes91fd5322008-07-21 18:52:34 +000025#include "llvm/GlobalVariable.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000026#include "llvm/Intrinsics.h"
27#include "llvm/CallingConv.h"
28#include "llvm/CodeGen/CallingConvLower.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineFunction.h"
31#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000032#include "llvm/CodeGen/MachineRegisterInfo.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000033#include "llvm/CodeGen/SelectionDAGISel.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000034#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/Support/Debug.h"
Torok Edwinc25e7582009-07-11 20:10:48 +000036#include "llvm/Support/ErrorHandling.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000037using namespace llvm;
38
Jia Liubb481f82012-02-28 07:46:26 +000039// If I is a shifted mask, set the size (Size) and the first bit of the
Akira Hatanakadbe9a312011-08-18 20:07:42 +000040// mask (Pos), and return true.
Jia Liubb481f82012-02-28 07:46:26 +000041// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
Akira Hatanaka854a7db2011-08-19 22:59:00 +000042static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
Akira Hatanakad6bc5232011-12-05 21:26:34 +000043 if (!isShiftedMask_64(I))
Akira Hatanaka854a7db2011-08-19 22:59:00 +000044 return false;
Akira Hatanakabb15e112011-08-17 02:05:42 +000045
Akira Hatanakad6bc5232011-12-05 21:26:34 +000046 Size = CountPopulation_64(I);
47 Pos = CountTrailingZeros_64(I);
Akira Hatanakadbe9a312011-08-18 20:07:42 +000048 return true;
Akira Hatanakabb15e112011-08-17 02:05:42 +000049}
50
Akira Hatanaka648f00c2012-02-24 22:34:47 +000051static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) {
52 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
53 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
54}
55
Chris Lattnerf0144122009-07-28 03:13:23 +000056const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
57 switch (Opcode) {
Akira Hatanakabdd2ce92011-05-23 21:13:59 +000058 case MipsISD::JmpLink: return "MipsISD::JmpLink";
59 case MipsISD::Hi: return "MipsISD::Hi";
60 case MipsISD::Lo: return "MipsISD::Lo";
61 case MipsISD::GPRel: return "MipsISD::GPRel";
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +000062 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
Akira Hatanakabdd2ce92011-05-23 21:13:59 +000063 case MipsISD::Ret: return "MipsISD::Ret";
64 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
65 case MipsISD::FPCmp: return "MipsISD::FPCmp";
66 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
67 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
68 case MipsISD::FPRound: return "MipsISD::FPRound";
69 case MipsISD::MAdd: return "MipsISD::MAdd";
70 case MipsISD::MAddu: return "MipsISD::MAddu";
71 case MipsISD::MSub: return "MipsISD::MSub";
72 case MipsISD::MSubu: return "MipsISD::MSubu";
73 case MipsISD::DivRem: return "MipsISD::DivRem";
74 case MipsISD::DivRemU: return "MipsISD::DivRemU";
75 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
76 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
Akira Hatanakabfcb83f2011-12-12 22:38:19 +000077 case MipsISD::Wrapper: return "MipsISD::Wrapper";
Akira Hatanaka21afc632011-06-21 00:40:49 +000078 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
Akira Hatanakadb548262011-07-19 23:30:50 +000079 case MipsISD::Sync: return "MipsISD::Sync";
Akira Hatanakabb15e112011-08-17 02:05:42 +000080 case MipsISD::Ext: return "MipsISD::Ext";
81 case MipsISD::Ins: return "MipsISD::Ins";
Akira Hatanaka0f843822011-06-07 18:58:42 +000082 default: return NULL;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000083 }
84}
85
86MipsTargetLowering::
Chris Lattnerf0144122009-07-28 03:13:23 +000087MipsTargetLowering(MipsTargetMachine &TM)
Akira Hatanaka8b4198d2011-09-26 21:47:02 +000088 : TargetLowering(TM, new MipsTargetObjectFile()),
89 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
Akira Hatanaka2ec69fa2011-10-28 18:47:24 +000090 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
91 IsO32(Subtarget->isABI_O32()) {
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000092
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000093 // Mips does not have i1 type, so use i32 for
Wesley Peckbf17cfa2010-11-23 03:31:01 +000094 // setcc operations results (slt, sgt, ...).
Duncan Sands03228082008-11-23 15:47:28 +000095 setBooleanContents(ZeroOrOneBooleanContent);
Duncan Sands28b77e92011-09-06 19:07:46 +000096 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000097
98 // Set up the register classes
Craig Topper420761a2012-04-20 07:30:17 +000099 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000100
Akira Hatanaka95934842011-09-24 01:34:44 +0000101 if (HasMips64)
Craig Topper420761a2012-04-20 07:30:17 +0000102 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
Akira Hatanaka95934842011-09-24 01:34:44 +0000103
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000104 if (!TM.Options.UseSoftFloat) {
Craig Topper420761a2012-04-20 07:30:17 +0000105 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000106
107 // When dealing with single precision only, use libcalls
108 if (!Subtarget->isSingleFloat()) {
109 if (HasMips64)
Craig Topper420761a2012-04-20 07:30:17 +0000110 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000111 else
Craig Topper420761a2012-04-20 07:30:17 +0000112 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000113 }
Akira Hatanaka792016b2011-09-23 18:28:39 +0000114 }
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000115
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000116 // Load extented operations for i1 types must be promoted
Owen Anderson825b72b2009-08-11 20:47:22 +0000117 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
118 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
119 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000120
Eli Friedman6055a6a2009-07-17 04:07:24 +0000121 // MIPS doesn't have extending float->double load/store
Owen Anderson825b72b2009-08-11 20:47:22 +0000122 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
123 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
Eli Friedman10a36592009-07-17 02:28:12 +0000124
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000125 // Used by legalize types to correctly generate the setcc result.
126 // Without this, every float setcc comes with a AND/OR with the result,
127 // we don't want this, since the fpcmp result goes to a flag register,
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +0000128 // which is used implicitly by brcond and select operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000129 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +0000130
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000131 // Mips Custom Operations
Owen Anderson825b72b2009-08-11 20:47:22 +0000132 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +0000133 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
Owen Anderson825b72b2009-08-11 20:47:22 +0000134 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
135 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
136 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
137 setOperationAction(ISD::SELECT, MVT::f32, Custom);
138 setOperationAction(ISD::SELECT, MVT::f64, Custom);
139 setOperationAction(ISD::SELECT, MVT::i32, Custom);
Akira Hatanaka0a40c232012-03-09 23:46:03 +0000140 setOperationAction(ISD::SETCC, MVT::f32, Custom);
141 setOperationAction(ISD::SETCC, MVT::f64, Custom);
Owen Anderson825b72b2009-08-11 20:47:22 +0000142 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
143 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000144 setOperationAction(ISD::VASTART, MVT::Other, Custom);
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000145 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
146 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
147 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
148 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
149
Akira Hatanakac12a6e62012-04-11 22:49:04 +0000150 if (!TM.Options.NoNaNsFPMath) {
151 setOperationAction(ISD::FABS, MVT::f32, Custom);
152 setOperationAction(ISD::FABS, MVT::f64, Custom);
153 }
154
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000155 if (HasMips64) {
156 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
157 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
158 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
159 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
160 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
161 setOperationAction(ISD::SELECT, MVT::i64, Custom);
162 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
163 }
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000164
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000165 setOperationAction(ISD::SDIV, MVT::i32, Expand);
166 setOperationAction(ISD::SREM, MVT::i32, Expand);
167 setOperationAction(ISD::UDIV, MVT::i32, Expand);
168 setOperationAction(ISD::UREM, MVT::i32, Expand);
Akira Hatanakadda4a072011-10-03 21:06:13 +0000169 setOperationAction(ISD::SDIV, MVT::i64, Expand);
170 setOperationAction(ISD::SREM, MVT::i64, Expand);
171 setOperationAction(ISD::UDIV, MVT::i64, Expand);
172 setOperationAction(ISD::UREM, MVT::i64, Expand);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000173
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000174 // Operations not directly supported by Mips.
Owen Anderson825b72b2009-08-11 20:47:22 +0000175 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
176 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
177 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
178 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
Akira Hatanakae1bcd6b2011-12-20 23:40:56 +0000179 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000180 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
Akira Hatanakae1bcd6b2011-12-20 23:40:56 +0000181 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000182 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
183 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
Akira Hatanaka7f162742011-12-21 00:14:05 +0000184 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000185 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
Akira Hatanaka7f162742011-12-21 00:14:05 +0000186 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
Chandler Carruth63974b22011-12-13 01:56:10 +0000187 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
188 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
189 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
190 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000191 setOperationAction(ISD::ROTL, MVT::i32, Expand);
Akira Hatanakac7bafe92011-09-30 18:51:46 +0000192 setOperationAction(ISD::ROTL, MVT::i64, Expand);
Bruno Cardoso Lopes908b6dd2010-12-09 17:32:30 +0000193
Akira Hatanaka56633442011-09-20 23:53:09 +0000194 if (!Subtarget->hasMips32r2())
Bruno Cardoso Lopes908b6dd2010-12-09 17:32:30 +0000195 setOperationAction(ISD::ROTR, MVT::i32, Expand);
196
Akira Hatanakac7bafe92011-09-30 18:51:46 +0000197 if (!Subtarget->hasMips64r2())
198 setOperationAction(ISD::ROTR, MVT::i64, Expand);
199
Owen Anderson825b72b2009-08-11 20:47:22 +0000200 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
201 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
202 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000203 setOperationAction(ISD::FSIN, MVT::f32, Expand);
Bruno Cardoso Lopes5d6fb5d2011-03-04 18:54:14 +0000204 setOperationAction(ISD::FSIN, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000205 setOperationAction(ISD::FCOS, MVT::f32, Expand);
Bruno Cardoso Lopes5d6fb5d2011-03-04 18:54:14 +0000206 setOperationAction(ISD::FCOS, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000207 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
208 setOperationAction(ISD::FPOW, MVT::f32, Expand);
Akira Hatanaka46da1362011-05-23 22:23:58 +0000209 setOperationAction(ISD::FPOW, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000210 setOperationAction(ISD::FLOG, MVT::f32, Expand);
211 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
212 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
213 setOperationAction(ISD::FEXP, MVT::f32, Expand);
Cameron Zwarich33390842011-07-08 21:39:21 +0000214 setOperationAction(ISD::FMA, MVT::f32, Expand);
215 setOperationAction(ISD::FMA, MVT::f64, Expand);
Akira Hatanaka21ecc2f2012-03-29 18:43:11 +0000216 setOperationAction(ISD::FREM, MVT::f32, Expand);
217 setOperationAction(ISD::FREM, MVT::f64, Expand);
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000218
Akira Hatanaka1cc63332012-04-11 22:59:08 +0000219 if (!TM.Options.NoNaNsFPMath) {
220 setOperationAction(ISD::FNEG, MVT::f32, Expand);
221 setOperationAction(ISD::FNEG, MVT::f64, Expand);
222 }
223
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000224 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
Akira Hatanaka590baca2012-02-02 03:13:40 +0000225 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000226 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
Akira Hatanaka590baca2012-02-02 03:13:40 +0000227 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
Eric Christopher471e4222011-06-08 23:55:35 +0000228
Bruno Cardoso Lopes954dac02011-03-09 19:22:22 +0000229 setOperationAction(ISD::VAARG, MVT::Other, Expand);
230 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
231 setOperationAction(ISD::VAEND, MVT::Other, Expand);
232
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000233 // Use the default for now
Owen Anderson825b72b2009-08-11 20:47:22 +0000234 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
235 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
Eli Friedman14648462011-07-27 22:21:52 +0000236
Jia Liubb481f82012-02-28 07:46:26 +0000237 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
238 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
239 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
240 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
Eli Friedman4db5aca2011-08-29 18:23:02 +0000241
Eli Friedman26689ac2011-08-03 21:06:02 +0000242 setInsertFencesForAtomic(true);
243
Bruno Cardoso Lopesea9d4d62008-08-04 06:44:31 +0000244 if (Subtarget->isSingleFloat())
Owen Anderson825b72b2009-08-11 20:47:22 +0000245 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000246
Bruno Cardoso Lopes7728f7e2008-07-09 05:32:22 +0000247 if (!Subtarget->hasSEInReg()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000248 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
249 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000250 }
251
Akira Hatanakac79507a2011-12-21 00:20:27 +0000252 if (!Subtarget->hasBitCount()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000253 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
Akira Hatanakac79507a2011-12-21 00:20:27 +0000254 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
255 }
Bruno Cardoso Lopes65ad4522008-08-08 06:16:31 +0000256
Akira Hatanakac0ea0432011-12-20 23:56:43 +0000257 if (!Subtarget->hasSwap()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000258 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
Akira Hatanakac0ea0432011-12-20 23:56:43 +0000259 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
260 }
Bruno Cardoso Lopes739e4412008-08-13 07:13:40 +0000261
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000262 setTargetDAGCombine(ISD::ADDE);
263 setTargetDAGCombine(ISD::SUBE);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000264 setTargetDAGCombine(ISD::SDIVREM);
265 setTargetDAGCombine(ISD::UDIVREM);
Akira Hatanakaee8c3b02012-03-08 03:26:37 +0000266 setTargetDAGCombine(ISD::SELECT);
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000267 setTargetDAGCombine(ISD::AND);
268 setTargetDAGCombine(ISD::OR);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000269
Akira Hatanaka5fdf5002012-03-08 01:59:33 +0000270 setMinFunctionAlignment(HasMips64 ? 3 : 2);
Eli Friedmanfc5d3052011-05-06 20:34:06 +0000271
Akira Hatanaka3f5b1072012-02-02 03:17:04 +0000272 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000273 computeRegisterProperties();
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000274
Akira Hatanaka590baca2012-02-02 03:13:40 +0000275 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
276 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000277}
278
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +0000279bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
Akira Hatanaka511961a2011-08-17 18:49:18 +0000280 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
Jia Liubb481f82012-02-28 07:46:26 +0000281
Akira Hatanaka44b6c712012-02-28 02:55:02 +0000282 switch (SVT) {
283 case MVT::i64:
284 case MVT::i32:
285 case MVT::i16:
286 return true;
287 case MVT::f32:
Akira Hatanaka44b6c712012-02-28 02:55:02 +0000288 return Subtarget->hasMips32r2Or64();
289 default:
290 return false;
291 }
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +0000292}
293
Duncan Sands28b77e92011-09-06 19:07:46 +0000294EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
Owen Anderson825b72b2009-08-11 20:47:22 +0000295 return MVT::i32;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000296}
297
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000298// SelectMadd -
299// Transforms a subgraph in CurDAG if the following pattern is found:
300// (addc multLo, Lo0), (adde multHi, Hi0),
301// where,
302// multHi/Lo: product of multiplication
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000303// Lo0: initial value of Lo register
304// Hi0: initial value of Hi register
Akira Hatanaka81bd78b2011-03-30 21:15:35 +0000305// Return true if pattern matching was successful.
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000306static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000307 // ADDENode's second operand must be a flag output of an ADDC node in order
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000308 // for the matching to be successful.
309 SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
310
311 if (ADDCNode->getOpcode() != ISD::ADDC)
312 return false;
313
314 SDValue MultHi = ADDENode->getOperand(0);
315 SDValue MultLo = ADDCNode->getOperand(0);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000316 SDNode* MultNode = MultHi.getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000317 unsigned MultOpc = MultHi.getOpcode();
318
319 // MultHi and MultLo must be generated by the same node,
320 if (MultLo.getNode() != MultNode)
321 return false;
322
323 // and it must be a multiplication.
324 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
325 return false;
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000326
327 // MultLo amd MultHi must be the first and second output of MultNode
328 // respectively.
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000329 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
330 return false;
331
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000332 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000333 // of the values of MultNode, in which case MultNode will be removed in later
334 // phases.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000335 // If there exist users other than ADDENode or ADDCNode, this function returns
336 // here, which will result in MultNode being mapped to a single MULT
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000337 // instruction node rather than a pair of MULT and MADD instructions being
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000338 // produced.
339 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
340 return false;
341
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000342 SDValue Chain = CurDAG->getEntryNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000343 DebugLoc dl = ADDENode->getDebugLoc();
344
345 // create MipsMAdd(u) node
346 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000347
Akira Hatanaka82099682011-12-19 19:52:25 +0000348 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000349 MultNode->getOperand(0),// Factor 0
350 MultNode->getOperand(1),// Factor 1
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000351 ADDCNode->getOperand(1),// Lo0
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000352 ADDENode->getOperand(1));// Hi0
353
354 // create CopyFromReg nodes
355 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
356 MAdd);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000357 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000358 Mips::HI, MVT::i32,
359 CopyFromLo.getValue(2));
360
361 // replace uses of adde and addc here
362 if (!SDValue(ADDCNode, 0).use_empty())
363 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
364
365 if (!SDValue(ADDENode, 0).use_empty())
366 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
367
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000368 return true;
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000369}
370
371// SelectMsub -
372// Transforms a subgraph in CurDAG if the following pattern is found:
373// (addc Lo0, multLo), (sube Hi0, multHi),
374// where,
375// multHi/Lo: product of multiplication
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000376// Lo0: initial value of Lo register
377// Hi0: initial value of Hi register
Akira Hatanaka81bd78b2011-03-30 21:15:35 +0000378// Return true if pattern matching was successful.
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000379static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000380 // SUBENode's second operand must be a flag output of an SUBC node in order
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000381 // for the matching to be successful.
382 SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
383
384 if (SUBCNode->getOpcode() != ISD::SUBC)
385 return false;
386
387 SDValue MultHi = SUBENode->getOperand(1);
388 SDValue MultLo = SUBCNode->getOperand(1);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000389 SDNode* MultNode = MultHi.getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000390 unsigned MultOpc = MultHi.getOpcode();
391
392 // MultHi and MultLo must be generated by the same node,
393 if (MultLo.getNode() != MultNode)
394 return false;
395
396 // and it must be a multiplication.
397 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
398 return false;
399
400 // MultLo amd MultHi must be the first and second output of MultNode
401 // respectively.
402 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
403 return false;
404
405 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
406 // of the values of MultNode, in which case MultNode will be removed in later
407 // phases.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000408 // If there exist users other than SUBENode or SUBCNode, this function returns
409 // here, which will result in MultNode being mapped to a single MULT
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000410 // instruction node rather than a pair of MULT and MSUB instructions being
411 // produced.
412 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
413 return false;
414
415 SDValue Chain = CurDAG->getEntryNode();
416 DebugLoc dl = SUBENode->getDebugLoc();
417
418 // create MipsSub(u) node
419 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
420
Akira Hatanaka82099682011-12-19 19:52:25 +0000421 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000422 MultNode->getOperand(0),// Factor 0
423 MultNode->getOperand(1),// Factor 1
424 SUBCNode->getOperand(0),// Lo0
425 SUBENode->getOperand(0));// Hi0
426
427 // create CopyFromReg nodes
428 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
429 MSub);
430 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
431 Mips::HI, MVT::i32,
432 CopyFromLo.getValue(2));
433
434 // replace uses of sube and subc here
435 if (!SDValue(SUBCNode, 0).use_empty())
436 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
437
438 if (!SDValue(SUBENode, 0).use_empty())
439 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
440
441 return true;
442}
443
444static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
445 TargetLowering::DAGCombinerInfo &DCI,
446 const MipsSubtarget* Subtarget) {
447 if (DCI.isBeforeLegalize())
448 return SDValue();
449
Akira Hatanakae184fec2011-11-11 04:18:21 +0000450 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
451 SelectMadd(N, &DAG))
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000452 return SDValue(N, 0);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000453
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000454 return SDValue();
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000455}
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000456
457static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
458 TargetLowering::DAGCombinerInfo &DCI,
459 const MipsSubtarget* Subtarget) {
460 if (DCI.isBeforeLegalize())
461 return SDValue();
462
Akira Hatanakae184fec2011-11-11 04:18:21 +0000463 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
464 SelectMsub(N, &DAG))
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000465 return SDValue(N, 0);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000466
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000467 return SDValue();
468}
469
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000470static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
471 TargetLowering::DAGCombinerInfo &DCI,
472 const MipsSubtarget* Subtarget) {
473 if (DCI.isBeforeLegalizeOps())
474 return SDValue();
475
Akira Hatanakadda4a072011-10-03 21:06:13 +0000476 EVT Ty = N->getValueType(0);
Jia Liubb481f82012-02-28 07:46:26 +0000477 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
478 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000479 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
480 MipsISD::DivRemU;
481 DebugLoc dl = N->getDebugLoc();
482
483 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
484 N->getOperand(0), N->getOperand(1));
485 SDValue InChain = DAG.getEntryNode();
486 SDValue InGlue = DivRem;
487
488 // insert MFLO
489 if (N->hasAnyUseOfValue(0)) {
Akira Hatanakadda4a072011-10-03 21:06:13 +0000490 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000491 InGlue);
492 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
493 InChain = CopyFromLo.getValue(1);
494 InGlue = CopyFromLo.getValue(2);
495 }
496
497 // insert MFHI
498 if (N->hasAnyUseOfValue(1)) {
499 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
Akira Hatanakadda4a072011-10-03 21:06:13 +0000500 HI, Ty, InGlue);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000501 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
502 }
503
504 return SDValue();
505}
506
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000507static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
508 switch (CC) {
509 default: llvm_unreachable("Unknown fp condition code!");
510 case ISD::SETEQ:
511 case ISD::SETOEQ: return Mips::FCOND_OEQ;
512 case ISD::SETUNE: return Mips::FCOND_UNE;
513 case ISD::SETLT:
514 case ISD::SETOLT: return Mips::FCOND_OLT;
515 case ISD::SETGT:
516 case ISD::SETOGT: return Mips::FCOND_OGT;
517 case ISD::SETLE:
518 case ISD::SETOLE: return Mips::FCOND_OLE;
519 case ISD::SETGE:
520 case ISD::SETOGE: return Mips::FCOND_OGE;
521 case ISD::SETULT: return Mips::FCOND_ULT;
522 case ISD::SETULE: return Mips::FCOND_ULE;
523 case ISD::SETUGT: return Mips::FCOND_UGT;
524 case ISD::SETUGE: return Mips::FCOND_UGE;
525 case ISD::SETUO: return Mips::FCOND_UN;
526 case ISD::SETO: return Mips::FCOND_OR;
527 case ISD::SETNE:
528 case ISD::SETONE: return Mips::FCOND_ONE;
529 case ISD::SETUEQ: return Mips::FCOND_UEQ;
530 }
531}
532
533
534// Returns true if condition code has to be inverted.
535static bool InvertFPCondCode(Mips::CondCode CC) {
536 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
537 return false;
538
Akira Hatanaka82099682011-12-19 19:52:25 +0000539 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
540 "Illegal Condition Code");
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000541
Akira Hatanaka82099682011-12-19 19:52:25 +0000542 return true;
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000543}
544
545// Creates and returns an FPCmp node from a setcc node.
546// Returns Op if setcc is not a floating point comparison.
547static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
548 // must be a SETCC node
549 if (Op.getOpcode() != ISD::SETCC)
550 return Op;
551
552 SDValue LHS = Op.getOperand(0);
553
554 if (!LHS.getValueType().isFloatingPoint())
555 return Op;
556
557 SDValue RHS = Op.getOperand(1);
558 DebugLoc dl = Op.getDebugLoc();
559
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +0000560 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
561 // node if necessary.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000562 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
563
564 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
565 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
566}
567
568// Creates and returns a CMovFPT/F node.
569static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True,
570 SDValue False, DebugLoc DL) {
571 bool invert = InvertFPCondCode((Mips::CondCode)
572 cast<ConstantSDNode>(Cond.getOperand(2))
573 ->getSExtValue());
574
575 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
576 True.getValueType(), True, False, Cond);
577}
578
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000579static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG& DAG,
580 TargetLowering::DAGCombinerInfo &DCI,
581 const MipsSubtarget* Subtarget) {
582 if (DCI.isBeforeLegalizeOps())
583 return SDValue();
584
585 SDValue SetCC = N->getOperand(0);
586
587 if ((SetCC.getOpcode() != ISD::SETCC) ||
588 !SetCC.getOperand(0).getValueType().isInteger())
589 return SDValue();
590
591 SDValue False = N->getOperand(2);
592 EVT FalseTy = False.getValueType();
593
594 if (!FalseTy.isInteger())
595 return SDValue();
596
597 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
598
599 if (!CN || CN->getZExtValue())
600 return SDValue();
601
602 const DebugLoc DL = N->getDebugLoc();
603 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
604 SDValue True = N->getOperand(1);
605
606 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
607 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
608
609 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
610}
611
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000612static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG,
613 TargetLowering::DAGCombinerInfo &DCI,
614 const MipsSubtarget* Subtarget) {
615 // Pattern match EXT.
616 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
617 // => ext $dst, $src, size, pos
Akira Hatanaka56633442011-09-20 23:53:09 +0000618 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000619 return SDValue();
620
621 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000622 unsigned ShiftRightOpc = ShiftRight.getOpcode();
623
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000624 // Op's first operand must be a shift right.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000625 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000626 return SDValue();
627
628 // The second operand of the shift must be an immediate.
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000629 ConstantSDNode *CN;
630 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
631 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000632
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000633 uint64_t Pos = CN->getZExtValue();
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000634 uint64_t SMPos, SMSize;
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000635
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000636 // Op's second operand must be a shifted mask.
637 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000638 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000639 return SDValue();
640
641 // Return if the shifted mask does not start at bit 0 or the sum of its size
642 // and Pos exceeds the word's size.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000643 EVT ValTy = N->getValueType(0);
644 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000645 return SDValue();
646
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000647 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy,
Akira Hatanaka82099682011-12-19 19:52:25 +0000648 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
Akira Hatanaka667645f2011-08-17 22:59:46 +0000649 DAG.getConstant(SMSize, MVT::i32));
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000650}
Jia Liubb481f82012-02-28 07:46:26 +0000651
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000652static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
653 TargetLowering::DAGCombinerInfo &DCI,
654 const MipsSubtarget* Subtarget) {
655 // Pattern match INS.
656 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
Jia Liubb481f82012-02-28 07:46:26 +0000657 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000658 // => ins $dst, $src, size, pos, $src1
Akira Hatanaka56633442011-09-20 23:53:09 +0000659 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000660 return SDValue();
661
662 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
663 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
664 ConstantSDNode *CN;
665
666 // See if Op's first operand matches (and $src1 , mask0).
667 if (And0.getOpcode() != ISD::AND)
668 return SDValue();
669
670 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000671 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000672 return SDValue();
673
674 // See if Op's second operand matches (and (shl $src, pos), mask1).
675 if (And1.getOpcode() != ISD::AND)
676 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000677
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000678 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000679 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000680 return SDValue();
681
682 // The shift masks must have the same position and size.
683 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
684 return SDValue();
685
686 SDValue Shl = And1.getOperand(0);
687 if (Shl.getOpcode() != ISD::SHL)
688 return SDValue();
689
690 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
691 return SDValue();
692
693 unsigned Shamt = CN->getZExtValue();
694
695 // Return if the shift amount and the first bit position of mask are not the
Jia Liubb481f82012-02-28 07:46:26 +0000696 // same.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000697 EVT ValTy = N->getValueType(0);
698 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000699 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000700
Akira Hatanaka82099682011-12-19 19:52:25 +0000701 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0),
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000702 DAG.getConstant(SMPos0, MVT::i32),
Akira Hatanaka82099682011-12-19 19:52:25 +0000703 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000704}
Jia Liubb481f82012-02-28 07:46:26 +0000705
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000706SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000707 const {
708 SelectionDAG &DAG = DCI.DAG;
709 unsigned opc = N->getOpcode();
710
711 switch (opc) {
712 default: break;
713 case ISD::ADDE:
714 return PerformADDECombine(N, DAG, DCI, Subtarget);
715 case ISD::SUBE:
716 return PerformSUBECombine(N, DAG, DCI, Subtarget);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000717 case ISD::SDIVREM:
718 case ISD::UDIVREM:
719 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000720 case ISD::SELECT:
721 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000722 case ISD::AND:
723 return PerformANDCombine(N, DAG, DCI, Subtarget);
724 case ISD::OR:
725 return PerformORCombine(N, DAG, DCI, Subtarget);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000726 }
727
728 return SDValue();
729}
730
Dan Gohman475871a2008-07-27 21:46:04 +0000731SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +0000732LowerOperation(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000733{
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000734 switch (Op.getOpcode())
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000735 {
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000736 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000737 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
738 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000739 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +0000740 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000741 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
742 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000743 case ISD::SELECT: return LowerSELECT(Op, DAG);
Akira Hatanaka0a40c232012-03-09 23:46:03 +0000744 case ISD::SETCC: return LowerSETCC(Op, DAG);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000745 case ISD::VASTART: return LowerVASTART(Op, DAG);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +0000746 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
Akira Hatanakac12a6e62012-04-11 22:49:04 +0000747 case ISD::FABS: return LowerFABS(Op, DAG);
Akira Hatanaka2e591472011-06-02 00:24:44 +0000748 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Akira Hatanakadb548262011-07-19 23:30:50 +0000749 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
Eli Friedman14648462011-07-27 22:21:52 +0000750 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000751 }
Dan Gohman475871a2008-07-27 21:46:04 +0000752 return SDValue();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000753}
754
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000755//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000756// Lower helper functions
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000757//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000758
759// AddLiveIn - This helper function adds the specified physical register to the
760// MachineFunction as a live in value. It also creates a corresponding
761// virtual register for it.
762static unsigned
Craig Topper44d23822012-02-22 05:59:10 +0000763AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000764{
765 assert(RC->contains(PReg) && "Not the correct regclass!");
Chris Lattner84bc5422007-12-31 04:13:23 +0000766 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
767 MF.getRegInfo().addLiveIn(PReg, VReg);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000768 return VReg;
769}
770
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000771// Get fp branch code (not opcode) from condition code.
772static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
773 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
774 return Mips::BRANCH_T;
775
Akira Hatanaka82099682011-12-19 19:52:25 +0000776 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
777 "Invalid CondCode.");
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000778
Akira Hatanaka82099682011-12-19 19:52:25 +0000779 return Mips::BRANCH_F;
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000780}
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000781
Akira Hatanaka8ae330a2011-10-17 18:53:29 +0000782/*
Akira Hatanaka14487d42011-06-07 19:28:39 +0000783static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
784 DebugLoc dl,
785 const MipsSubtarget* Subtarget,
786 const TargetInstrInfo *TII,
787 bool isFPCmp, unsigned Opc) {
788 // There is no need to expand CMov instructions if target has
789 // conditional moves.
790 if (Subtarget->hasCondMov())
791 return BB;
792
793 // To "insert" a SELECT_CC instruction, we actually have to insert the
794 // diamond control-flow pattern. The incoming instruction knows the
795 // destination vreg to set, the condition code register to branch on, the
796 // true/false values to select between, and a branch opcode to use.
797 const BasicBlock *LLVM_BB = BB->getBasicBlock();
798 MachineFunction::iterator It = BB;
799 ++It;
800
801 // thisMBB:
802 // ...
803 // TrueVal = ...
804 // setcc r1, r2, r3
805 // bNE r1, r0, copy1MBB
806 // fallthrough --> copy0MBB
807 MachineBasicBlock *thisMBB = BB;
808 MachineFunction *F = BB->getParent();
809 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
810 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
811 F->insert(It, copy0MBB);
812 F->insert(It, sinkMBB);
813
814 // Transfer the remainder of BB and its successor edges to sinkMBB.
815 sinkMBB->splice(sinkMBB->begin(), BB,
816 llvm::next(MachineBasicBlock::iterator(MI)),
817 BB->end());
818 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
819
820 // Next, add the true and fallthrough blocks as its successors.
821 BB->addSuccessor(copy0MBB);
822 BB->addSuccessor(sinkMBB);
823
824 // Emit the right instruction according to the type of the operands compared
825 if (isFPCmp)
826 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
827 else
828 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
829 .addReg(Mips::ZERO).addMBB(sinkMBB);
830
831 // copy0MBB:
832 // %FalseValue = ...
833 // # fallthrough to sinkMBB
834 BB = copy0MBB;
835
836 // Update machine-CFG edges
837 BB->addSuccessor(sinkMBB);
838
839 // sinkMBB:
840 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
841 // ...
842 BB = sinkMBB;
843
844 if (isFPCmp)
845 BuildMI(*BB, BB->begin(), dl,
846 TII->get(Mips::PHI), MI->getOperand(0).getReg())
847 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
848 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
849 else
850 BuildMI(*BB, BB->begin(), dl,
851 TII->get(Mips::PHI), MI->getOperand(0).getReg())
852 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
853 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
854
855 MI->eraseFromParent(); // The pseudo instruction is gone now.
856 return BB;
857}
Akira Hatanaka8ae330a2011-10-17 18:53:29 +0000858*/
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000859MachineBasicBlock *
860MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
Dan Gohmanaf1d8ca2010-05-01 00:01:06 +0000861 MachineBasicBlock *BB) const {
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000862 switch (MI->getOpcode()) {
Craig Topperbc219812012-02-07 02:50:20 +0000863 default: llvm_unreachable("Unexpected instr type to insert");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000864 case Mips::ATOMIC_LOAD_ADD_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000865 case Mips::ATOMIC_LOAD_ADD_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000866 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
867 case Mips::ATOMIC_LOAD_ADD_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000868 case Mips::ATOMIC_LOAD_ADD_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000869 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
870 case Mips::ATOMIC_LOAD_ADD_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000871 case Mips::ATOMIC_LOAD_ADD_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000872 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
Akira Hatanaka59068062011-11-11 04:14:30 +0000873 case Mips::ATOMIC_LOAD_ADD_I64:
874 case Mips::ATOMIC_LOAD_ADD_I64_P8:
875 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000876
877 case Mips::ATOMIC_LOAD_AND_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000878 case Mips::ATOMIC_LOAD_AND_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000879 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
880 case Mips::ATOMIC_LOAD_AND_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000881 case Mips::ATOMIC_LOAD_AND_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000882 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
883 case Mips::ATOMIC_LOAD_AND_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000884 case Mips::ATOMIC_LOAD_AND_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000885 return EmitAtomicBinary(MI, BB, 4, Mips::AND);
Akira Hatanaka59068062011-11-11 04:14:30 +0000886 case Mips::ATOMIC_LOAD_AND_I64:
887 case Mips::ATOMIC_LOAD_AND_I64_P8:
Akira Hatanaka73866122011-11-12 02:38:12 +0000888 return EmitAtomicBinary(MI, BB, 8, Mips::AND64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000889
890 case Mips::ATOMIC_LOAD_OR_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000891 case Mips::ATOMIC_LOAD_OR_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000892 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
893 case Mips::ATOMIC_LOAD_OR_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000894 case Mips::ATOMIC_LOAD_OR_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000895 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
896 case Mips::ATOMIC_LOAD_OR_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000897 case Mips::ATOMIC_LOAD_OR_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000898 return EmitAtomicBinary(MI, BB, 4, Mips::OR);
Akira Hatanaka59068062011-11-11 04:14:30 +0000899 case Mips::ATOMIC_LOAD_OR_I64:
900 case Mips::ATOMIC_LOAD_OR_I64_P8:
901 return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000902
903 case Mips::ATOMIC_LOAD_XOR_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000904 case Mips::ATOMIC_LOAD_XOR_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000905 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
906 case Mips::ATOMIC_LOAD_XOR_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000907 case Mips::ATOMIC_LOAD_XOR_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000908 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
909 case Mips::ATOMIC_LOAD_XOR_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000910 case Mips::ATOMIC_LOAD_XOR_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000911 return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
Akira Hatanaka59068062011-11-11 04:14:30 +0000912 case Mips::ATOMIC_LOAD_XOR_I64:
913 case Mips::ATOMIC_LOAD_XOR_I64_P8:
914 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000915
916 case Mips::ATOMIC_LOAD_NAND_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000917 case Mips::ATOMIC_LOAD_NAND_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000918 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
919 case Mips::ATOMIC_LOAD_NAND_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000920 case Mips::ATOMIC_LOAD_NAND_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000921 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
922 case Mips::ATOMIC_LOAD_NAND_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000923 case Mips::ATOMIC_LOAD_NAND_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000924 return EmitAtomicBinary(MI, BB, 4, 0, true);
Akira Hatanaka59068062011-11-11 04:14:30 +0000925 case Mips::ATOMIC_LOAD_NAND_I64:
926 case Mips::ATOMIC_LOAD_NAND_I64_P8:
927 return EmitAtomicBinary(MI, BB, 8, 0, true);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000928
929 case Mips::ATOMIC_LOAD_SUB_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000930 case Mips::ATOMIC_LOAD_SUB_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000931 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
932 case Mips::ATOMIC_LOAD_SUB_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000933 case Mips::ATOMIC_LOAD_SUB_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000934 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
935 case Mips::ATOMIC_LOAD_SUB_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000936 case Mips::ATOMIC_LOAD_SUB_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000937 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
Akira Hatanaka59068062011-11-11 04:14:30 +0000938 case Mips::ATOMIC_LOAD_SUB_I64:
939 case Mips::ATOMIC_LOAD_SUB_I64_P8:
940 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000941
942 case Mips::ATOMIC_SWAP_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000943 case Mips::ATOMIC_SWAP_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000944 return EmitAtomicBinaryPartword(MI, BB, 1, 0);
945 case Mips::ATOMIC_SWAP_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000946 case Mips::ATOMIC_SWAP_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000947 return EmitAtomicBinaryPartword(MI, BB, 2, 0);
948 case Mips::ATOMIC_SWAP_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000949 case Mips::ATOMIC_SWAP_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000950 return EmitAtomicBinary(MI, BB, 4, 0);
Akira Hatanaka59068062011-11-11 04:14:30 +0000951 case Mips::ATOMIC_SWAP_I64:
952 case Mips::ATOMIC_SWAP_I64_P8:
953 return EmitAtomicBinary(MI, BB, 8, 0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000954
955 case Mips::ATOMIC_CMP_SWAP_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000956 case Mips::ATOMIC_CMP_SWAP_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000957 return EmitAtomicCmpSwapPartword(MI, BB, 1);
958 case Mips::ATOMIC_CMP_SWAP_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000959 case Mips::ATOMIC_CMP_SWAP_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000960 return EmitAtomicCmpSwapPartword(MI, BB, 2);
961 case Mips::ATOMIC_CMP_SWAP_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000962 case Mips::ATOMIC_CMP_SWAP_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000963 return EmitAtomicCmpSwap(MI, BB, 4);
Akira Hatanaka59068062011-11-11 04:14:30 +0000964 case Mips::ATOMIC_CMP_SWAP_I64:
965 case Mips::ATOMIC_CMP_SWAP_I64_P8:
966 return EmitAtomicCmpSwap(MI, BB, 8);
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000967 }
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000968}
969
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000970// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
971// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
972MachineBasicBlock *
973MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
Eric Christopher471e4222011-06-08 23:55:35 +0000974 unsigned Size, unsigned BinOpcode,
Akira Hatanaka0f843822011-06-07 18:58:42 +0000975 bool Nand) const {
Akira Hatanaka59068062011-11-11 04:14:30 +0000976 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000977
978 MachineFunction *MF = BB->getParent();
979 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Akira Hatanaka59068062011-11-11 04:14:30 +0000980 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000981 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
982 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +0000983 unsigned LL, SC, AND, NOR, ZERO, BEQ;
984
985 if (Size == 4) {
986 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
987 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
988 AND = Mips::AND;
989 NOR = Mips::NOR;
990 ZERO = Mips::ZERO;
991 BEQ = Mips::BEQ;
992 }
993 else {
994 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
995 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
996 AND = Mips::AND64;
997 NOR = Mips::NOR64;
998 ZERO = Mips::ZERO_64;
999 BEQ = Mips::BEQ64;
1000 }
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001001
Akira Hatanaka4061da12011-07-19 20:11:17 +00001002 unsigned OldVal = MI->getOperand(0).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001003 unsigned Ptr = MI->getOperand(1).getReg();
1004 unsigned Incr = MI->getOperand(2).getReg();
1005
Akira Hatanaka4061da12011-07-19 20:11:17 +00001006 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1007 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1008 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001009
1010 // insert new blocks after the current block
1011 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1012 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1013 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1014 MachineFunction::iterator It = BB;
1015 ++It;
1016 MF->insert(It, loopMBB);
1017 MF->insert(It, exitMBB);
1018
1019 // Transfer the remainder of BB and its successor edges to exitMBB.
1020 exitMBB->splice(exitMBB->begin(), BB,
1021 llvm::next(MachineBasicBlock::iterator(MI)),
1022 BB->end());
1023 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1024
1025 // thisMBB:
1026 // ...
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001027 // fallthrough --> loopMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001028 BB->addSuccessor(loopMBB);
Akira Hatanaka81b44112011-07-19 17:09:53 +00001029 loopMBB->addSuccessor(loopMBB);
1030 loopMBB->addSuccessor(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001031
1032 // loopMBB:
1033 // ll oldval, 0(ptr)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001034 // <binop> storeval, oldval, incr
1035 // sc success, storeval, 0(ptr)
1036 // beq success, $0, loopMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001037 BB = loopMBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001038 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001039 if (Nand) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001040 // and andres, oldval, incr
1041 // nor storeval, $0, andres
Akira Hatanaka59068062011-11-11 04:14:30 +00001042 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1043 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001044 } else if (BinOpcode) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001045 // <binop> storeval, oldval, incr
1046 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001047 } else {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001048 StoreVal = Incr;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001049 }
Akira Hatanaka59068062011-11-11 04:14:30 +00001050 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1051 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001052
1053 MI->eraseFromParent(); // The instruction is gone now.
1054
Akira Hatanaka939ece12011-07-19 03:42:13 +00001055 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001056}
1057
1058MachineBasicBlock *
1059MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001060 MachineBasicBlock *BB,
1061 unsigned Size, unsigned BinOpcode,
1062 bool Nand) const {
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001063 assert((Size == 1 || Size == 2) &&
1064 "Unsupported size for EmitAtomicBinaryPartial.");
1065
1066 MachineFunction *MF = BB->getParent();
1067 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1068 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1069 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1070 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001071 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1072 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001073
1074 unsigned Dest = MI->getOperand(0).getReg();
1075 unsigned Ptr = MI->getOperand(1).getReg();
1076 unsigned Incr = MI->getOperand(2).getReg();
1077
Akira Hatanaka4061da12011-07-19 20:11:17 +00001078 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1079 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001080 unsigned Mask = RegInfo.createVirtualRegister(RC);
1081 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001082 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1083 unsigned OldVal = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001084 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001085 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1086 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1087 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1088 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1089 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001090 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001091 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1092 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1093 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1094 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1095 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001096
1097 // insert new blocks after the current block
1098 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1099 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001100 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001101 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1102 MachineFunction::iterator It = BB;
1103 ++It;
1104 MF->insert(It, loopMBB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001105 MF->insert(It, sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001106 MF->insert(It, exitMBB);
1107
1108 // Transfer the remainder of BB and its successor edges to exitMBB.
1109 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001110 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001111 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1112
Akira Hatanaka81b44112011-07-19 17:09:53 +00001113 BB->addSuccessor(loopMBB);
1114 loopMBB->addSuccessor(loopMBB);
1115 loopMBB->addSuccessor(sinkMBB);
1116 sinkMBB->addSuccessor(exitMBB);
1117
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001118 // thisMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001119 // addiu masklsb2,$0,-4 # 0xfffffffc
1120 // and alignedaddr,ptr,masklsb2
1121 // andi ptrlsb2,ptr,3
1122 // sll shiftamt,ptrlsb2,3
1123 // ori maskupper,$0,255 # 0xff
1124 // sll mask,maskupper,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001125 // nor mask2,$0,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001126 // sll incr2,incr,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001127
1128 int64_t MaskImm = (Size == 1) ? 255 : 65535;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001129 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1130 .addReg(Mips::ZERO).addImm(-4);
1131 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1132 .addReg(Ptr).addReg(MaskLSB2);
1133 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1134 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1135 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1136 .addReg(Mips::ZERO).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001137 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1138 .addReg(ShiftAmt).addReg(MaskUpper);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001139 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001140 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
Bruno Cardoso Lopescada2d02011-05-31 20:25:26 +00001141
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001142 // atomic.load.binop
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001143 // loopMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001144 // ll oldval,0(alignedaddr)
1145 // binop binopres,oldval,incr2
1146 // and newval,binopres,mask
1147 // and maskedoldval0,oldval,mask2
1148 // or storeval,maskedoldval0,newval
1149 // sc success,storeval,0(alignedaddr)
1150 // beq success,$0,loopMBB
1151
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001152 // atomic.swap
1153 // loopMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001154 // ll oldval,0(alignedaddr)
Akira Hatanaka70564a92011-07-19 18:14:26 +00001155 // and newval,incr2,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001156 // and maskedoldval0,oldval,mask2
1157 // or storeval,maskedoldval0,newval
1158 // sc success,storeval,0(alignedaddr)
1159 // beq success,$0,loopMBB
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001160
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001161 BB = loopMBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001162 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001163 if (Nand) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001164 // and andres, oldval, incr2
1165 // nor binopres, $0, andres
1166 // and newval, binopres, mask
1167 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1168 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
1169 .addReg(Mips::ZERO).addReg(AndRes);
1170 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001171 } else if (BinOpcode) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001172 // <binop> binopres, oldval, incr2
1173 // and newval, binopres, mask
1174 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1175 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
Akira Hatanaka70564a92011-07-19 18:14:26 +00001176 } else {// atomic.swap
Akira Hatanaka4061da12011-07-19 20:11:17 +00001177 // and newval, incr2, mask
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001178 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
Akira Hatanaka70564a92011-07-19 18:14:26 +00001179 }
Jia Liubb481f82012-02-28 07:46:26 +00001180
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001181 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001182 .addReg(OldVal).addReg(Mask2);
1183 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001184 .addReg(MaskedOldVal0).addReg(NewVal);
Akira Hatanaka59068062011-11-11 04:14:30 +00001185 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001186 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001187 BuildMI(BB, dl, TII->get(Mips::BEQ))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001188 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001189
Akira Hatanaka939ece12011-07-19 03:42:13 +00001190 // sinkMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001191 // and maskedoldval1,oldval,mask
1192 // srl srlres,maskedoldval1,shiftamt
1193 // sll sllres,srlres,24
1194 // sra dest,sllres,24
Akira Hatanaka939ece12011-07-19 03:42:13 +00001195 BB = sinkMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001196 int64_t ShiftImm = (Size == 1) ? 24 : 16;
Akira Hatanakaa308c672011-07-19 03:14:58 +00001197
Akira Hatanaka4061da12011-07-19 20:11:17 +00001198 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1199 .addReg(OldVal).addReg(Mask);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001200 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1201 .addReg(ShiftAmt).addReg(MaskedOldVal1);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001202 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1203 .addReg(SrlRes).addImm(ShiftImm);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001204 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001205 .addReg(SllRes).addImm(ShiftImm);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001206
1207 MI->eraseFromParent(); // The instruction is gone now.
1208
Akira Hatanaka939ece12011-07-19 03:42:13 +00001209 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001210}
1211
1212MachineBasicBlock *
1213MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001214 MachineBasicBlock *BB,
1215 unsigned Size) const {
Akira Hatanaka59068062011-11-11 04:14:30 +00001216 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001217
1218 MachineFunction *MF = BB->getParent();
1219 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Akira Hatanaka59068062011-11-11 04:14:30 +00001220 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001221 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1222 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001223 unsigned LL, SC, ZERO, BNE, BEQ;
1224
1225 if (Size == 4) {
1226 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1227 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1228 ZERO = Mips::ZERO;
1229 BNE = Mips::BNE;
1230 BEQ = Mips::BEQ;
1231 }
1232 else {
1233 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1234 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1235 ZERO = Mips::ZERO_64;
1236 BNE = Mips::BNE64;
1237 BEQ = Mips::BEQ64;
1238 }
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001239
1240 unsigned Dest = MI->getOperand(0).getReg();
1241 unsigned Ptr = MI->getOperand(1).getReg();
Akira Hatanaka4061da12011-07-19 20:11:17 +00001242 unsigned OldVal = MI->getOperand(2).getReg();
1243 unsigned NewVal = MI->getOperand(3).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001244
Akira Hatanaka4061da12011-07-19 20:11:17 +00001245 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001246
1247 // insert new blocks after the current block
1248 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1249 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1250 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1251 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1252 MachineFunction::iterator It = BB;
1253 ++It;
1254 MF->insert(It, loop1MBB);
1255 MF->insert(It, loop2MBB);
1256 MF->insert(It, exitMBB);
1257
1258 // Transfer the remainder of BB and its successor edges to exitMBB.
1259 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001260 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001261 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1262
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001263 // thisMBB:
1264 // ...
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001265 // fallthrough --> loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001266 BB->addSuccessor(loop1MBB);
Akira Hatanaka81b44112011-07-19 17:09:53 +00001267 loop1MBB->addSuccessor(exitMBB);
1268 loop1MBB->addSuccessor(loop2MBB);
1269 loop2MBB->addSuccessor(loop1MBB);
1270 loop2MBB->addSuccessor(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001271
1272 // loop1MBB:
1273 // ll dest, 0(ptr)
1274 // bne dest, oldval, exitMBB
1275 BB = loop1MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001276 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1277 BuildMI(BB, dl, TII->get(BNE))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001278 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001279
1280 // loop2MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001281 // sc success, newval, 0(ptr)
1282 // beq success, $0, loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001283 BB = loop2MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001284 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001285 .addReg(NewVal).addReg(Ptr).addImm(0);
Akira Hatanaka59068062011-11-11 04:14:30 +00001286 BuildMI(BB, dl, TII->get(BEQ))
1287 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001288
1289 MI->eraseFromParent(); // The instruction is gone now.
1290
Akira Hatanaka939ece12011-07-19 03:42:13 +00001291 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001292}
1293
1294MachineBasicBlock *
1295MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001296 MachineBasicBlock *BB,
1297 unsigned Size) const {
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001298 assert((Size == 1 || Size == 2) &&
1299 "Unsupported size for EmitAtomicCmpSwapPartial.");
1300
1301 MachineFunction *MF = BB->getParent();
1302 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1303 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1304 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1305 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001306 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1307 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001308
1309 unsigned Dest = MI->getOperand(0).getReg();
1310 unsigned Ptr = MI->getOperand(1).getReg();
Akira Hatanaka4061da12011-07-19 20:11:17 +00001311 unsigned CmpVal = MI->getOperand(2).getReg();
1312 unsigned NewVal = MI->getOperand(3).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001313
Akira Hatanaka4061da12011-07-19 20:11:17 +00001314 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1315 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001316 unsigned Mask = RegInfo.createVirtualRegister(RC);
1317 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001318 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1319 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1320 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1321 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1322 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1323 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1324 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1325 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1326 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1327 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1328 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1329 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1330 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1331 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001332
1333 // insert new blocks after the current block
1334 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1335 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1336 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001337 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001338 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1339 MachineFunction::iterator It = BB;
1340 ++It;
1341 MF->insert(It, loop1MBB);
1342 MF->insert(It, loop2MBB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001343 MF->insert(It, sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001344 MF->insert(It, exitMBB);
1345
1346 // Transfer the remainder of BB and its successor edges to exitMBB.
1347 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001348 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001349 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1350
Akira Hatanaka81b44112011-07-19 17:09:53 +00001351 BB->addSuccessor(loop1MBB);
1352 loop1MBB->addSuccessor(sinkMBB);
1353 loop1MBB->addSuccessor(loop2MBB);
1354 loop2MBB->addSuccessor(loop1MBB);
1355 loop2MBB->addSuccessor(sinkMBB);
1356 sinkMBB->addSuccessor(exitMBB);
1357
Akira Hatanaka70564a92011-07-19 18:14:26 +00001358 // FIXME: computation of newval2 can be moved to loop2MBB.
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001359 // thisMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001360 // addiu masklsb2,$0,-4 # 0xfffffffc
1361 // and alignedaddr,ptr,masklsb2
1362 // andi ptrlsb2,ptr,3
1363 // sll shiftamt,ptrlsb2,3
1364 // ori maskupper,$0,255 # 0xff
1365 // sll mask,maskupper,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001366 // nor mask2,$0,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001367 // andi maskedcmpval,cmpval,255
1368 // sll shiftedcmpval,maskedcmpval,shiftamt
1369 // andi maskednewval,newval,255
1370 // sll shiftednewval,maskednewval,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001371 int64_t MaskImm = (Size == 1) ? 255 : 65535;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001372 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1373 .addReg(Mips::ZERO).addImm(-4);
1374 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1375 .addReg(Ptr).addReg(MaskLSB2);
1376 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1377 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1378 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1379 .addReg(Mips::ZERO).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001380 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1381 .addReg(ShiftAmt).addReg(MaskUpper);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001382 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001383 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
1384 .addReg(CmpVal).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001385 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
1386 .addReg(ShiftAmt).addReg(MaskedCmpVal);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001387 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
1388 .addReg(NewVal).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001389 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
1390 .addReg(ShiftAmt).addReg(MaskedNewVal);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001391
1392 // loop1MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001393 // ll oldval,0(alginedaddr)
1394 // and maskedoldval0,oldval,mask
1395 // bne maskedoldval0,shiftedcmpval,sinkMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001396 BB = loop1MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001397 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001398 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1399 .addReg(OldVal).addReg(Mask);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001400 BuildMI(BB, dl, TII->get(Mips::BNE))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001401 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001402
1403 // loop2MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001404 // and maskedoldval1,oldval,mask2
1405 // or storeval,maskedoldval1,shiftednewval
1406 // sc success,storeval,0(alignedaddr)
1407 // beq success,$0,loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001408 BB = loop2MBB;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001409 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1410 .addReg(OldVal).addReg(Mask2);
1411 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1412 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
Akira Hatanaka59068062011-11-11 04:14:30 +00001413 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001414 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001415 BuildMI(BB, dl, TII->get(Mips::BEQ))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001416 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001417
Akira Hatanaka939ece12011-07-19 03:42:13 +00001418 // sinkMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001419 // srl srlres,maskedoldval0,shiftamt
1420 // sll sllres,srlres,24
1421 // sra dest,sllres,24
Akira Hatanaka939ece12011-07-19 03:42:13 +00001422 BB = sinkMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001423 int64_t ShiftImm = (Size == 1) ? 24 : 16;
Akira Hatanakaa308c672011-07-19 03:14:58 +00001424
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001425 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1426 .addReg(ShiftAmt).addReg(MaskedOldVal0);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001427 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1428 .addReg(SrlRes).addImm(ShiftImm);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001429 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001430 .addReg(SllRes).addImm(ShiftImm);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001431
1432 MI->eraseFromParent(); // The instruction is gone now.
1433
Akira Hatanaka939ece12011-07-19 03:42:13 +00001434 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001435}
1436
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001437//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001438// Misc Lower Operation implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001439//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesd3bdf192009-05-27 17:23:44 +00001440SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001441LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001442{
Akira Hatanaka21afc632011-06-21 00:40:49 +00001443 MachineFunction &MF = DAG.getMachineFunction();
1444 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001445 unsigned SP = IsN64 ? Mips::SP_64 : Mips::SP;
Akira Hatanaka21afc632011-06-21 00:40:49 +00001446
1447 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >=
Akira Hatanaka053546c2011-05-25 02:20:00 +00001448 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() &&
1449 "Cannot lower if the alignment of the allocated space is larger than \
1450 that of the stack.");
1451
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001452 SDValue Chain = Op.getOperand(0);
1453 SDValue Size = Op.getOperand(1);
Dale Johannesena05dca42009-02-04 23:02:30 +00001454 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001455
1456 // Get a reference from Mips stack pointer
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001457 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SP, getPointerTy());
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001458
1459 // Subtract the dynamic size from the actual stack size to
1460 // obtain the new stack size.
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001461 SDValue Sub = DAG.getNode(ISD::SUB, dl, getPointerTy(), StackPointer, Size);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001462
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001463 // The Sub result contains the new stack start address, so it
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001464 // must be placed in the stack pointer register.
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001465 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, SP, Sub, SDValue());
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001466
1467 // This node always has two return values: a new stack pointer
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001468 // value and a chain
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001469 SDVTList VTLs = DAG.getVTList(getPointerTy(), MVT::Other);
Akira Hatanaka21afc632011-06-21 00:40:49 +00001470 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy());
1471 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) };
1472
1473 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001474}
1475
1476SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001477LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001478{
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001479 // The first operand is the chain, the second is the condition, the third is
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001480 // the block to branch to if the condition is true.
1481 SDValue Chain = Op.getOperand(0);
1482 SDValue Dest = Op.getOperand(2);
Dale Johannesende064702009-02-06 21:50:26 +00001483 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001484
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001485 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
1486
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001487 // Return if flag is not set by a floating point comparison.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001488 if (CondRes.getOpcode() != MipsISD::FPCmp)
Bruno Cardoso Lopes4b877ca2008-07-30 17:06:13 +00001489 return Op;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001490
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +00001491 SDValue CCNode = CondRes.getOperand(2);
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001492 Mips::CondCode CC =
1493 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001494 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001495
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001496 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001497 Dest, CondRes);
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001498}
1499
1500SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001501LowerSELECT(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001502{
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001503 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001504
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001505 // Return if flag is not set by a floating point comparison.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001506 if (Cond.getOpcode() != MipsISD::FPCmp)
1507 return Op;
Bruno Cardoso Lopes739e4412008-08-13 07:13:40 +00001508
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001509 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1510 Op.getDebugLoc());
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001511}
1512
Akira Hatanaka0a40c232012-03-09 23:46:03 +00001513SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1514 SDValue Cond = CreateFPCmp(DAG, Op);
1515
1516 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1517 "Floating point operand expected.");
1518
1519 SDValue True = DAG.getConstant(1, MVT::i32);
1520 SDValue False = DAG.getConstant(0, MVT::i32);
1521
1522 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc());
1523}
1524
Dan Gohmand858e902010-04-17 15:26:15 +00001525SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
1526 SelectionDAG &DAG) const {
Dale Johannesende064702009-02-06 21:50:26 +00001527 // FIXME there isn't actually debug info here
Dale Johannesen33c960f2009-02-04 20:06:27 +00001528 DebugLoc dl = Op.getDebugLoc();
Jia Liubb481f82012-02-28 07:46:26 +00001529 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001530
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001531 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Chris Lattnere3736f82009-08-13 05:41:27 +00001532 SDVTList VTs = DAG.getVTList(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001533
Chris Lattnerb71b9092009-08-13 06:28:06 +00001534 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001535
Chris Lattnere3736f82009-08-13 05:41:27 +00001536 // %gp_rel relocation
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001537 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1538 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00001539 MipsII::MO_GPREL);
Chris Lattnere3736f82009-08-13 05:41:27 +00001540 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
1541 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001542 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
Chris Lattnere3736f82009-08-13 05:41:27 +00001543 }
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001544 // %hi/%lo relocation
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001545 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1546 MipsII::MO_ABS_HI);
1547 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1548 MipsII::MO_ABS_LO);
1549 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
1550 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
Owen Anderson825b72b2009-08-11 20:47:22 +00001551 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001552 }
1553
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001554 EVT ValTy = Op.getValueType();
1555 bool HasGotOfst = (GV->hasInternalLinkage() ||
1556 (GV->hasLocalLinkage() && !isa<Function>(GV)));
Akira Hatanaka56ce6b32012-04-04 22:16:36 +00001557 unsigned GotFlag = HasMips64 ?
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001558 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) :
Bruno Cardoso Lopese3d35722011-12-07 00:28:57 +00001559 (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16);
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001560 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001561 GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), GA);
Akira Hatanaka82099682011-12-19 19:52:25 +00001562 SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA,
1563 MachinePointerInfo(), false, false, false, 0);
Akira Hatanaka0f843822011-06-07 18:58:42 +00001564 // On functions and global targets not internal linked only
1565 // a load from got/GP is necessary for PIC to work.
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001566 if (!HasGotOfst)
Akira Hatanaka0f843822011-06-07 18:58:42 +00001567 return ResNode;
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001568 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0,
Akira Hatanaka56ce6b32012-04-04 22:16:36 +00001569 HasMips64 ? MipsII::MO_GOT_OFST :
1570 MipsII::MO_ABS_LO);
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001571 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo);
1572 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001573}
1574
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001575SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
1576 SelectionDAG &DAG) const {
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001577 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1578 // FIXME there isn't actually debug info here
1579 DebugLoc dl = Op.getDebugLoc();
1580
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001581 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001582 // %hi/%lo relocation
Akira Hatanaka82099682011-12-19 19:52:25 +00001583 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_HI);
1584 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_LO);
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001585 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
1586 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
1587 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001588 }
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001589
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001590 EVT ValTy = Op.getValueType();
Akira Hatanaka03d830e2012-04-04 18:22:53 +00001591 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1592 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001593 SDValue BAGOTOffset = DAG.getBlockAddress(BA, ValTy, true, GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001594 BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy,
1595 GetGlobalReg(DAG, ValTy), BAGOTOffset);
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001596 SDValue BALOOffset = DAG.getBlockAddress(BA, ValTy, true, OFSTFlag);
Akira Hatanaka82099682011-12-19 19:52:25 +00001597 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset,
Pete Cooperd752e0f2011-11-08 18:42:53 +00001598 MachinePointerInfo(), false, false, false, 0);
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001599 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset);
1600 return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001601}
1602
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001603SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001604LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001605{
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001606 // If the relocation model is PIC, use the General Dynamic TLS Model or
1607 // Local Dynamic TLS model, otherwise use the Initial Exec or
1608 // Local Exec TLS Model.
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001609
1610 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1611 DebugLoc dl = GA->getDebugLoc();
1612 const GlobalValue *GV = GA->getGlobal();
1613 EVT PtrVT = getPointerTy();
1614
1615 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1616 // General Dynamic TLS Model
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001617 bool LocalDynamic = GV->hasInternalLinkage();
1618 unsigned Flag = LocalDynamic ? MipsII::MO_TLSLDM :MipsII::MO_TLSGD;
1619 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001620 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT,
1621 GetGlobalReg(DAG, PtrVT), TGA);
Akira Hatanaka7a7194b2011-12-08 21:05:38 +00001622 unsigned PtrSize = PtrVT.getSizeInBits();
1623 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1624
Benjamin Kramer5eccf672011-12-11 12:21:34 +00001625 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001626
1627 ArgListTy Args;
1628 ArgListEntry Entry;
1629 Entry.Node = Argument;
Akira Hatanakaca074792011-12-08 20:34:32 +00001630 Entry.Ty = PtrTy;
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001631 Args.push_back(Entry);
Jia Liubb481f82012-02-28 07:46:26 +00001632
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001633 std::pair<SDValue, SDValue> CallResult =
Akira Hatanakaca074792011-12-08 20:34:32 +00001634 LowerCallTo(DAG.getEntryNode(), PtrTy,
Evan Cheng4bfcd4a2012-02-28 18:51:51 +00001635 false, false, false, false, 0, CallingConv::C,
1636 /*isTailCall=*/false, /*doesNotRet=*/false,
1637 /*isReturnValueUsed=*/true,
Akira Hatanaka7a7194b2011-12-08 21:05:38 +00001638 TlsGetAddr, Args, DAG, dl);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001639
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001640 SDValue Ret = CallResult.first;
1641
1642 if (!LocalDynamic)
1643 return Ret;
1644
1645 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1646 MipsII::MO_DTPREL_HI);
1647 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1648 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1649 MipsII::MO_DTPREL_LO);
1650 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1651 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret);
1652 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001653 }
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001654
1655 SDValue Offset;
1656 if (GV->isDeclaration()) {
1657 // Initial Exec TLS Model
Akira Hatanakaca074792011-12-08 20:34:32 +00001658 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001659 MipsII::MO_GOTTPREL);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001660 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1661 TGA);
Akira Hatanakaca074792011-12-08 20:34:32 +00001662 Offset = DAG.getLoad(PtrVT, dl,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001663 DAG.getEntryNode(), TGA, MachinePointerInfo(),
Pete Cooperd752e0f2011-11-08 18:42:53 +00001664 false, false, false, 0);
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001665 } else {
1666 // Local Exec TLS Model
Akira Hatanakaca074792011-12-08 20:34:32 +00001667 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001668 MipsII::MO_TPREL_HI);
Akira Hatanakaca074792011-12-08 20:34:32 +00001669 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001670 MipsII::MO_TPREL_LO);
Akira Hatanakaca074792011-12-08 20:34:32 +00001671 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1672 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1673 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001674 }
1675
1676 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
1677 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001678}
1679
1680SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001681LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001682{
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001683 SDValue HiPart, JTI, JTILo;
Dale Johannesende064702009-02-06 21:50:26 +00001684 // FIXME there isn't actually debug info here
Dale Johannesen33c960f2009-02-04 20:06:27 +00001685 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00001686 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Owen Andersone50ed302009-08-10 22:56:29 +00001687 EVT PtrVT = Op.getValueType();
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001688 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001689
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001690 if (!IsPIC && !IsN64) {
1691 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI);
1692 HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI);
1693 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO);
Akira Hatanaka342837d2011-05-28 01:07:07 +00001694 } else {// Emit Load from Global Pointer
Akira Hatanakac75ceb72012-04-04 18:31:32 +00001695 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1696 unsigned OfstFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001697 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001698 JTI = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1699 JTI);
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001700 HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI,
1701 MachinePointerInfo(), false, false, false, 0);
1702 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag);
Akira Hatanaka342837d2011-05-28 01:07:07 +00001703 }
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001704
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001705 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo);
1706 return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo);
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001707}
1708
Dan Gohman475871a2008-07-27 21:46:04 +00001709SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001710LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +00001711{
Dan Gohman475871a2008-07-27 21:46:04 +00001712 SDValue ResNode;
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001713 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
Dan Gohman46510a72010-04-15 01:51:59 +00001714 const Constant *C = N->getConstVal();
Dale Johannesende064702009-02-06 21:50:26 +00001715 // FIXME there isn't actually debug info here
1716 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001717
1718 // gp_rel relocation
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001719 // FIXME: we should reference the constant pool using small data sections,
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001720 // but the asm printer currently doesn't support this feature without
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001721 // hacking it. This feature should come soon so we can uncomment the
Bruno Cardoso Lopesf33bc432008-07-28 19:26:25 +00001722 // stuff below.
Eli Friedmane2c74082009-08-03 02:22:28 +00001723 //if (IsInSmallSection(C->getType())) {
Owen Anderson825b72b2009-08-11 20:47:22 +00001724 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1725 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001726 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001727
Akira Hatanaka13daee32012-03-27 02:55:31 +00001728 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001729 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001730 N->getOffset(), MipsII::MO_ABS_HI);
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001731 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001732 N->getOffset(), MipsII::MO_ABS_LO);
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001733 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
1734 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
Owen Anderson825b72b2009-08-11 20:47:22 +00001735 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001736 } else {
Akira Hatanaka620db892011-11-16 22:44:38 +00001737 EVT ValTy = Op.getValueType();
Akira Hatanaka86a27332012-04-04 18:26:12 +00001738 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1739 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Akira Hatanaka620db892011-11-16 22:44:38 +00001740 SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1741 N->getOffset(), GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001742 CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), CP);
Akira Hatanaka82099682011-12-19 19:52:25 +00001743 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP,
1744 MachinePointerInfo::getConstantPool(), false,
1745 false, false, 0);
Akira Hatanaka620db892011-11-16 22:44:38 +00001746 SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1747 N->getOffset(), OFSTFlag);
1748 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo);
1749 ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001750 }
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001751
1752 return ResNode;
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +00001753}
1754
Dan Gohmand858e902010-04-17 15:26:15 +00001755SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
Dan Gohman1e93df62010-04-17 14:41:14 +00001756 MachineFunction &MF = DAG.getMachineFunction();
1757 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1758
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001759 DebugLoc dl = Op.getDebugLoc();
Dan Gohman1e93df62010-04-17 14:41:14 +00001760 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1761 getPointerTy());
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001762
1763 // vastart just stores the address of the VarArgsFrameIndex slot into the
1764 // memory location argument.
1765 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Chris Lattner8026a9d2010-09-21 17:50:43 +00001766 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
Akira Hatanaka82099682011-12-19 19:52:25 +00001767 MachinePointerInfo(SV), false, false, 0);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001768}
Jia Liubb481f82012-02-28 07:46:26 +00001769
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001770static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1771 EVT TyX = Op.getOperand(0).getValueType();
1772 EVT TyY = Op.getOperand(1).getValueType();
1773 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1774 SDValue Const31 = DAG.getConstant(31, MVT::i32);
1775 DebugLoc DL = Op.getDebugLoc();
1776 SDValue Res;
1777
1778 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1779 // to i32.
1780 SDValue X = (TyX == MVT::f32) ?
1781 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1782 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1783 Const1);
1784 SDValue Y = (TyY == MVT::f32) ?
1785 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1786 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1787 Const1);
1788
1789 if (HasR2) {
1790 // ext E, Y, 31, 1 ; extract bit31 of Y
1791 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1792 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1793 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1794 } else {
1795 // sll SllX, X, 1
1796 // srl SrlX, SllX, 1
1797 // srl SrlY, Y, 31
1798 // sll SllY, SrlX, 31
1799 // or Or, SrlX, SllY
1800 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1801 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1802 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1803 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1804 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1805 }
1806
1807 if (TyX == MVT::f32)
1808 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1809
1810 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1811 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1812 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001813}
1814
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001815static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1816 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1817 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1818 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1819 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1820 DebugLoc DL = Op.getDebugLoc();
Eric Christopher471e4222011-06-08 23:55:35 +00001821
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001822 // Bitcast to integer nodes.
1823 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1824 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001825
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001826 if (HasR2) {
1827 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1828 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1829 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1830 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001831
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001832 if (WidthX > WidthY)
1833 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1834 else if (WidthY > WidthX)
1835 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001836
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001837 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1838 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
1839 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1840 }
1841
1842 // (d)sll SllX, X, 1
1843 // (d)srl SrlX, SllX, 1
1844 // (d)srl SrlY, Y, width(Y)-1
1845 // (d)sll SllY, SrlX, width(Y)-1
1846 // or Or, SrlX, SllY
1847 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1848 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1849 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1850 DAG.getConstant(WidthY - 1, MVT::i32));
1851
1852 if (WidthX > WidthY)
1853 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1854 else if (WidthY > WidthX)
1855 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1856
1857 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1858 DAG.getConstant(WidthX - 1, MVT::i32));
1859 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1860 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001861}
1862
Akira Hatanaka82099682011-12-19 19:52:25 +00001863SDValue
1864MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001865 if (Subtarget->hasMips64())
1866 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001867
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001868 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001869}
1870
Akira Hatanakac12a6e62012-04-11 22:49:04 +00001871static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1872 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1873 DebugLoc DL = Op.getDebugLoc();
1874
1875 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1876 // to i32.
1877 SDValue X = (Op.getValueType() == MVT::f32) ?
1878 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1879 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1880 Const1);
1881
1882 // Clear MSB.
1883 if (HasR2)
1884 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
1885 DAG.getRegister(Mips::ZERO, MVT::i32),
1886 DAG.getConstant(31, MVT::i32), Const1, X);
1887 else {
1888 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1889 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1890 }
1891
1892 if (Op.getValueType() == MVT::f32)
1893 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
1894
1895 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1896 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1897 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1898}
1899
1900static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1901 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1902 DebugLoc DL = Op.getDebugLoc();
1903
1904 // Bitcast to integer node.
1905 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
1906
1907 // Clear MSB.
1908 if (HasR2)
1909 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
1910 DAG.getRegister(Mips::ZERO_64, MVT::i64),
1911 DAG.getConstant(63, MVT::i32), Const1, X);
1912 else {
1913 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
1914 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
1915 }
1916
1917 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
1918}
1919
1920SDValue
1921MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
1922 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
1923 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2());
1924
1925 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2());
1926}
1927
Akira Hatanaka2e591472011-06-02 00:24:44 +00001928SDValue MipsTargetLowering::
1929LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
Bruno Cardoso Lopese0b5cfc2011-06-16 00:40:02 +00001930 // check the depth
1931 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
Akira Hatanaka0f843822011-06-07 18:58:42 +00001932 "Frame address can only be determined for current frame.");
Akira Hatanaka2e591472011-06-02 00:24:44 +00001933
1934 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1935 MFI->setFrameAddressIsTaken(true);
1936 EVT VT = Op.getValueType();
1937 DebugLoc dl = Op.getDebugLoc();
Akira Hatanaka46ac4392011-11-11 04:11:56 +00001938 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1939 IsN64 ? Mips::FP_64 : Mips::FP, VT);
Akira Hatanaka2e591472011-06-02 00:24:44 +00001940 return FrameAddr;
1941}
1942
Akira Hatanakadb548262011-07-19 23:30:50 +00001943// TODO: set SType according to the desired memory barrier behavior.
Akira Hatanaka82099682011-12-19 19:52:25 +00001944SDValue
1945MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const {
Akira Hatanakadb548262011-07-19 23:30:50 +00001946 unsigned SType = 0;
1947 DebugLoc dl = Op.getDebugLoc();
1948 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
1949 DAG.getConstant(SType, MVT::i32));
1950}
1951
Eli Friedman14648462011-07-27 22:21:52 +00001952SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
1953 SelectionDAG& DAG) const {
1954 // FIXME: Need pseudo-fence for 'singlethread' fences
1955 // FIXME: Set SType for weaker fences where supported/appropriate.
1956 unsigned SType = 0;
1957 DebugLoc dl = Op.getDebugLoc();
1958 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
1959 DAG.getConstant(SType, MVT::i32));
1960}
1961
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001962//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001963// Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001964//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001965
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001966//===----------------------------------------------------------------------===//
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001967// TODO: Implement a generic logic using tblgen that can support this.
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001968// Mips O32 ABI rules:
1969// ---
1970// i32 - Passed in A0, A1, A2, A3 and stack
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001971// f32 - Only passed in f32 registers if no int reg has been used yet to hold
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001972// an argument. Otherwise, passed in A1, A2, A3 and stack.
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001973// f64 - Only passed in two aliased f32 registers if no int reg has been used
1974// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001975// not used, it must be shadowed. If only A3 is avaiable, shadow it and
1976// go to stack.
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00001977//
1978// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001979//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001980
Duncan Sands1e96bab2010-11-04 10:49:57 +00001981static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
Duncan Sands1440e8b2010-11-03 11:35:31 +00001982 MVT LocVT, CCValAssign::LocInfo LocInfo,
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001983 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1984
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001985 static const unsigned IntRegsSize=4, FloatRegsSize=2;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001986
Craig Topperc5eaae42012-03-11 07:57:25 +00001987 static const uint16_t IntRegs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001988 Mips::A0, Mips::A1, Mips::A2, Mips::A3
1989 };
Craig Topperc5eaae42012-03-11 07:57:25 +00001990 static const uint16_t F32Regs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001991 Mips::F12, Mips::F14
1992 };
Craig Topperc5eaae42012-03-11 07:57:25 +00001993 static const uint16_t F64Regs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001994 Mips::D6, Mips::D7
1995 };
1996
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00001997 // ByVal Args
1998 if (ArgFlags.isByVal()) {
1999 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo,
2000 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags);
2001 unsigned NextReg = (State.getNextStackOffset() + 3) / 4;
2002 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize);
2003 r < std::min(IntRegsSize, NextReg); ++r)
2004 State.AllocateReg(IntRegs[r]);
2005 return false;
2006 }
2007
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002008 // Promote i8 and i16
2009 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2010 LocVT = MVT::i32;
2011 if (ArgFlags.isSExt())
2012 LocInfo = CCValAssign::SExt;
2013 else if (ArgFlags.isZExt())
2014 LocInfo = CCValAssign::ZExt;
2015 else
2016 LocInfo = CCValAssign::AExt;
2017 }
2018
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002019 unsigned Reg;
2020
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002021 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2022 // is true: function is vararg, argument is 3rd or higher, there is previous
2023 // argument which is not f32 or f64.
2024 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
2025 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
Akira Hatanakaa1a7ba82011-05-19 20:29:48 +00002026 unsigned OrigAlign = ArgFlags.getOrigAlign();
2027 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002028
2029 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002030 Reg = State.AllocateReg(IntRegs, IntRegsSize);
Akira Hatanakaa1a7ba82011-05-19 20:29:48 +00002031 // If this is the first part of an i64 arg,
2032 // the allocated register must be either A0 or A2.
2033 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2034 Reg = State.AllocateReg(IntRegs, IntRegsSize);
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002035 LocVT = MVT::i32;
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002036 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2037 // Allocate int register and shadow next int register. If first
2038 // available register is Mips::A1 or Mips::A3, shadow it too.
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002039 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2040 if (Reg == Mips::A1 || Reg == Mips::A3)
2041 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2042 State.AllocateReg(IntRegs, IntRegsSize);
2043 LocVT = MVT::i32;
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002044 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2045 // we are guaranteed to find an available float register
2046 if (ValVT == MVT::f32) {
2047 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2048 // Shadow int register
2049 State.AllocateReg(IntRegs, IntRegsSize);
2050 } else {
2051 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2052 // Shadow int registers
2053 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2054 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2055 State.AllocateReg(IntRegs, IntRegsSize);
2056 State.AllocateReg(IntRegs, IntRegsSize);
2057 }
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002058 } else
2059 llvm_unreachable("Cannot handle this ValVT.");
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002060
Akira Hatanakad37776d2011-05-20 21:39:54 +00002061 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
2062 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign);
2063
2064 if (!Reg)
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002065 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
Akira Hatanakad37776d2011-05-20 21:39:54 +00002066 else
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002067 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002068
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002069 return false; // CC must always match
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002070}
2071
Craig Topperc5eaae42012-03-11 07:57:25 +00002072static const uint16_t Mips64IntRegs[8] =
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002073 {Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
2074 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
Craig Topperc5eaae42012-03-11 07:57:25 +00002075static const uint16_t Mips64DPRegs[8] =
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002076 {Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
2077 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64};
2078
2079static bool CC_Mips64Byval(unsigned ValNo, MVT ValVT, MVT LocVT,
2080 CCValAssign::LocInfo LocInfo,
2081 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2082 unsigned Align = std::max(ArgFlags.getByValAlign(), (unsigned)8);
2083 unsigned Size = (ArgFlags.getByValSize() + 7) / 8 * 8;
2084 unsigned FirstIdx = State.getFirstUnallocated(Mips64IntRegs, 8);
2085
2086 assert(Align <= 16 && "Cannot handle alignments larger than 16.");
2087
Jia Liubb481f82012-02-28 07:46:26 +00002088 // If byval is 16-byte aligned, the first arg register must be even.
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002089 if ((Align == 16) && (FirstIdx % 2)) {
2090 State.AllocateReg(Mips64IntRegs[FirstIdx], Mips64DPRegs[FirstIdx]);
2091 ++FirstIdx;
2092 }
2093
2094 // Mark the registers allocated.
2095 for (unsigned I = FirstIdx; Size && (I < 8); Size -= 8, ++I)
2096 State.AllocateReg(Mips64IntRegs[I], Mips64DPRegs[I]);
2097
2098 // Allocate space on caller's stack.
2099 unsigned Offset = State.AllocateStack(Size, Align);
Jia Liubb481f82012-02-28 07:46:26 +00002100
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002101 if (FirstIdx < 8)
2102 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Mips64IntRegs[FirstIdx],
Jia Liubb481f82012-02-28 07:46:26 +00002103 LocVT, LocInfo));
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002104 else
2105 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2106
2107 return true;
2108}
2109
2110#include "MipsGenCallingConv.inc"
2111
Akira Hatanaka49617092011-11-14 19:02:54 +00002112static void
Akira Hatanaka08067b22012-01-24 22:07:36 +00002113AnalyzeMips64CallOperands(CCState &CCInfo,
Akira Hatanaka49617092011-11-14 19:02:54 +00002114 const SmallVectorImpl<ISD::OutputArg> &Outs) {
2115 unsigned NumOps = Outs.size();
2116 for (unsigned i = 0; i != NumOps; ++i) {
2117 MVT ArgVT = Outs[i].VT;
2118 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2119 bool R;
2120
2121 if (Outs[i].IsFixed)
2122 R = CC_MipsN(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2123 else
2124 R = CC_MipsN_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
Jia Liubb481f82012-02-28 07:46:26 +00002125
Akira Hatanaka49617092011-11-14 19:02:54 +00002126 if (R) {
Benjamin Kramer6296ee32011-11-14 19:51:48 +00002127#ifndef NDEBUG
Akira Hatanaka49617092011-11-14 19:02:54 +00002128 dbgs() << "Call operand #" << i << " has unhandled type "
2129 << EVT(ArgVT).getEVTString();
2130#endif
2131 llvm_unreachable(0);
2132 }
2133 }
2134}
2135
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002136//===----------------------------------------------------------------------===//
Dan Gohman98ca4f22009-08-05 01:29:28 +00002137// Call Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002138//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002139
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002140static const unsigned O32IntRegsSize = 4;
2141
Craig Topperc5eaae42012-03-11 07:57:25 +00002142static const uint16_t O32IntRegs[] = {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002143 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2144};
2145
Akira Hatanaka373e3a42011-09-23 00:58:33 +00002146// Return next O32 integer argument register.
2147static unsigned getNextIntArgReg(unsigned Reg) {
2148 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2149 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2150}
2151
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002152// Write ByVal Arg to arg registers and stack.
2153static void
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002154WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl,
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002155 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass,
2156 SmallVector<SDValue, 8>& MemOpChains, int& LastFI,
2157 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
Akira Hatanakaedacba82011-05-25 17:32:06 +00002158 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002159 MVT PtrType, bool isLittle) {
2160 unsigned LocMemOffset = VA.getLocMemOffset();
2161 unsigned Offset = 0;
2162 uint32_t RemainingSize = Flags.getByValSize();
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +00002163 unsigned ByValAlign = Flags.getByValAlign();
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002164
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002165 // Copy the first 4 words of byval arg to registers A0 - A3.
2166 // FIXME: Use a stricter alignment if it enables better optimization in passes
2167 // run later.
2168 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4;
2169 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002170 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002171 DAG.getConstant(Offset, MVT::i32));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002172 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
Akira Hatanaka82099682011-12-19 19:52:25 +00002173 MachinePointerInfo(), false, false, false,
2174 std::min(ByValAlign, (unsigned )4));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002175 MemOpChains.push_back(LoadVal.getValue(1));
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002176 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002177 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
2178 }
2179
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002180 if (RemainingSize == 0)
2181 return;
2182
2183 // If there still is a register available for argument passing, write the
2184 // remaining part of the structure to it using subword loads and shifts.
2185 if (LocMemOffset < 4 * 4) {
2186 assert(RemainingSize <= 3 && RemainingSize >= 1 &&
2187 "There must be one to three bytes remaining.");
2188 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize);
2189 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2190 DAG.getConstant(Offset, MVT::i32));
2191 unsigned Alignment = std::min(ByValAlign, (unsigned )4);
2192 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
2193 LoadPtr, MachinePointerInfo(),
2194 MVT::getIntegerVT(LoadSize * 8), false,
2195 false, Alignment);
2196 MemOpChains.push_back(LoadVal.getValue(1));
2197
2198 // If target is big endian, shift it to the most significant half-word or
2199 // byte.
2200 if (!isLittle)
2201 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal,
2202 DAG.getConstant(32 - LoadSize * 8, MVT::i32));
2203
2204 Offset += LoadSize;
2205 RemainingSize -= LoadSize;
2206
2207 // Read second subword if necessary.
2208 if (RemainingSize != 0) {
2209 assert(RemainingSize == 1 && "There must be one byte remaining.");
Jia Liubb481f82012-02-28 07:46:26 +00002210 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002211 DAG.getConstant(Offset, MVT::i32));
2212 unsigned Alignment = std::min(ByValAlign, (unsigned )2);
2213 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
2214 LoadPtr, MachinePointerInfo(),
2215 MVT::i8, false, false, Alignment);
2216 MemOpChains.push_back(Subword.getValue(1));
2217 // Insert the loaded byte to LoadVal.
2218 // FIXME: Use INS if supported by target.
2219 unsigned ShiftAmt = isLittle ? 16 : 8;
2220 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword,
2221 DAG.getConstant(ShiftAmt, MVT::i32));
2222 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift);
2223 }
2224
2225 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
2226 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
2227 return;
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002228 }
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002229
2230 // Create a fixed object on stack at offset LocMemOffset and copy
2231 // remaining part of byval arg to it using memcpy.
2232 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2233 DAG.getConstant(Offset, MVT::i32));
2234 LastFI = MFI->CreateFixedObject(RemainingSize, LocMemOffset, true);
2235 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType);
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002236 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src,
2237 DAG.getConstant(RemainingSize, MVT::i32),
2238 std::min(ByValAlign, (unsigned)4),
2239 /*isVolatile=*/false, /*AlwaysInline=*/false,
2240 MachinePointerInfo(0), MachinePointerInfo(0));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002241}
2242
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002243// Copy Mips64 byVal arg to registers and stack.
2244void static
2245PassByValArg64(SDValue& ByValChain, SDValue Chain, DebugLoc dl,
2246 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass,
2247 SmallVector<SDValue, 8>& MemOpChains, int& LastFI,
2248 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
2249 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
2250 EVT PtrTy, bool isLittle) {
2251 unsigned ByValSize = Flags.getByValSize();
2252 unsigned Alignment = std::min(Flags.getByValAlign(), (unsigned)8);
2253 bool IsRegLoc = VA.isRegLoc();
2254 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
2255 unsigned LocMemOffset = 0;
Akira Hatanaka16040852011-11-15 18:42:25 +00002256 unsigned MemCpySize = ByValSize;
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002257
2258 if (!IsRegLoc)
2259 LocMemOffset = VA.getLocMemOffset();
2260 else {
Craig Topperc5eaae42012-03-11 07:57:25 +00002261 const uint16_t *Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8,
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002262 VA.getLocReg());
Craig Topperc5eaae42012-03-11 07:57:25 +00002263 const uint16_t *RegEnd = Mips64IntRegs + 8;
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002264
2265 // Copy double words to registers.
2266 for (; (Reg != RegEnd) && (ByValSize >= Offset + 8); ++Reg, Offset += 8) {
2267 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2268 DAG.getConstant(Offset, PtrTy));
2269 SDValue LoadVal = DAG.getLoad(MVT::i64, dl, Chain, LoadPtr,
2270 MachinePointerInfo(), false, false, false,
2271 Alignment);
2272 MemOpChains.push_back(LoadVal.getValue(1));
2273 RegsToPass.push_back(std::make_pair(*Reg, LoadVal));
2274 }
2275
Jia Liubb481f82012-02-28 07:46:26 +00002276 // Return if the struct has been fully copied.
Akira Hatanaka16040852011-11-15 18:42:25 +00002277 if (!(MemCpySize = ByValSize - Offset))
2278 return;
2279
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002280 // If there is an argument register available, copy the remainder of the
2281 // byval argument with sub-doubleword loads and shifts.
Akira Hatanaka16040852011-11-15 18:42:25 +00002282 if (Reg != RegEnd) {
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002283 assert((ByValSize < Offset + 8) &&
2284 "Size of the remainder should be smaller than 8-byte.");
2285 SDValue Val;
2286 for (unsigned LoadSize = 4; Offset < ByValSize; LoadSize /= 2) {
2287 unsigned RemSize = ByValSize - Offset;
2288
2289 if (RemSize < LoadSize)
2290 continue;
Jia Liubb481f82012-02-28 07:46:26 +00002291
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002292 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2293 DAG.getConstant(Offset, PtrTy));
Jia Liubb481f82012-02-28 07:46:26 +00002294 SDValue LoadVal =
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002295 DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i64, Chain, LoadPtr,
2296 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
2297 false, false, Alignment);
2298 MemOpChains.push_back(LoadVal.getValue(1));
2299
2300 // Offset in number of bits from double word boundary.
2301 unsigned OffsetDW = (Offset % 8) * 8;
2302 unsigned Shamt = isLittle ? OffsetDW : 64 - (OffsetDW + LoadSize * 8);
2303 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i64, LoadVal,
2304 DAG.getConstant(Shamt, MVT::i32));
Jia Liubb481f82012-02-28 07:46:26 +00002305
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002306 Val = Val.getNode() ? DAG.getNode(ISD::OR, dl, MVT::i64, Val, Shift) :
2307 Shift;
2308 Offset += LoadSize;
2309 Alignment = std::min(Alignment, LoadSize);
2310 }
Jia Liubb481f82012-02-28 07:46:26 +00002311
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002312 RegsToPass.push_back(std::make_pair(*Reg, Val));
2313 return;
2314 }
2315 }
2316
Akira Hatanaka16040852011-11-15 18:42:25 +00002317 assert(MemCpySize && "MemCpySize must not be zero.");
2318
2319 // Create a fixed object on stack at offset LocMemOffset and copy
2320 // remainder of byval arg to it with memcpy.
2321 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2322 DAG.getConstant(Offset, PtrTy));
2323 LastFI = MFI->CreateFixedObject(MemCpySize, LocMemOffset, true);
2324 SDValue Dst = DAG.getFrameIndex(LastFI, PtrTy);
2325 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src,
2326 DAG.getConstant(MemCpySize, PtrTy), Alignment,
2327 /*isVolatile=*/false, /*AlwaysInline=*/false,
2328 MachinePointerInfo(0), MachinePointerInfo(0));
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002329}
2330
Dan Gohman98ca4f22009-08-05 01:29:28 +00002331/// LowerCall - functions arguments are copied from virtual regs to
Nate Begeman5bf4b752009-01-26 03:15:54 +00002332/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002333/// TODO: isTailCall.
Dan Gohman98ca4f22009-08-05 01:29:28 +00002334SDValue
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002335MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00002336 CallingConv::ID CallConv, bool isVarArg,
Evan Cheng4bfcd4a2012-02-28 18:51:51 +00002337 bool doesNotRet, bool &isTailCall,
Dan Gohman98ca4f22009-08-05 01:29:28 +00002338 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +00002339 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohman98ca4f22009-08-05 01:29:28 +00002340 const SmallVectorImpl<ISD::InputArg> &Ins,
2341 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +00002342 SmallVectorImpl<SDValue> &InVals) const {
Evan Cheng0c439eb2010-01-27 00:07:07 +00002343 // MIPs target does not yet support tail call optimization.
2344 isTailCall = false;
Dan Gohman98ca4f22009-08-05 01:29:28 +00002345
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002346 MachineFunction &MF = DAG.getMachineFunction();
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002347 MachineFrameInfo *MFI = MF.getFrameInfo();
Akira Hatanakad37776d2011-05-20 21:39:54 +00002348 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00002349 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Akira Hatanaka17a1e872011-05-20 18:39:33 +00002350 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002351
2352 // Analyze operands of the call, assigning locations to each operand.
2353 SmallVector<CCValAssign, 16> ArgLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00002354 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka82099682011-12-19 19:52:25 +00002355 getTargetMachine(), ArgLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002356
Akira Hatanaka2ec69fa2011-10-28 18:47:24 +00002357 if (IsO32)
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002358 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
Akira Hatanaka49617092011-11-14 19:02:54 +00002359 else if (HasMips64)
2360 AnalyzeMips64CallOperands(CCInfo, Outs);
Akira Hatanakabdd2ce92011-05-23 21:13:59 +00002361 else
Dan Gohman98ca4f22009-08-05 01:29:28 +00002362 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002363
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002364 // Get a count of how many bytes are to be pushed on the stack.
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002365 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2366
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002367 // Chain is the output chain of the last Load/Store or CopyToReg node.
2368 // ByValChain is the output chain of the last Memcpy node created for copying
2369 // byval arguments to the stack.
2370 SDValue Chain, CallSeqStart, ByValChain;
2371 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2372 Chain = CallSeqStart = DAG.getCALLSEQ_START(InChain, NextStackOffsetVal);
2373 ByValChain = InChain;
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002374
2375 // If this is the first call, create a stack frame object that points to
2376 // a location to which .cprestore saves $gp.
Akira Hatanaka648f00c2012-02-24 22:34:47 +00002377 if (IsO32 && IsPIC && MipsFI->globalBaseRegFixed() && !MipsFI->getGPFI())
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002378 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true));
2379
Akira Hatanaka21afc632011-06-21 00:40:49 +00002380 // Get the frame index of the stack frame object that points to the location
2381 // of dynamically allocated area on the stack.
2382 int DynAllocFI = MipsFI->getDynAllocFI();
2383
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002384 // Update size of the maximum argument space.
2385 // For O32, a minimum of four words (16 bytes) of argument space is
2386 // allocated.
Akira Hatanaka2ec69fa2011-10-28 18:47:24 +00002387 if (IsO32)
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002388 NextStackOffset = std::max(NextStackOffset, (unsigned)16);
2389
2390 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize();
2391
2392 if (MaxCallFrameSize < NextStackOffset) {
2393 MipsFI->setMaxCallFrameSize(NextStackOffset);
2394
Akira Hatanaka21afc632011-06-21 00:40:49 +00002395 // Set the offsets relative to $sp of the $gp restore slot and dynamically
2396 // allocated stack space. These offsets must be aligned to a boundary
2397 // determined by the stack alignment of the ABI.
2398 unsigned StackAlignment = TFL->getStackAlignment();
2399 NextStackOffset = (NextStackOffset + StackAlignment - 1) /
2400 StackAlignment * StackAlignment;
2401
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002402 if (MipsFI->needGPSaveRestore())
Akira Hatanaka21afc632011-06-21 00:40:49 +00002403 MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset);
2404
2405 MFI->setObjectOffset(DynAllocFI, NextStackOffset);
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002406 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002407
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002408 // With EABI is it possible to have 16 args on registers.
Dan Gohman475871a2008-07-27 21:46:04 +00002409 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
2410 SmallVector<SDValue, 8> MemOpChains;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002411
Eric Christopher471e4222011-06-08 23:55:35 +00002412 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0;
Akira Hatanaka43299772011-05-20 23:22:14 +00002413
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002414 // Walk the register/memloc assignments, inserting copies/loads.
2415 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
Dan Gohmanc9403652010-07-07 15:54:55 +00002416 SDValue Arg = OutVals[i];
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002417 CCValAssign &VA = ArgLocs[i];
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002418 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002419 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2420
2421 // ByVal Arg.
2422 if (Flags.isByVal()) {
2423 assert(Flags.getByValSize() &&
2424 "ByVal args of size 0 should have been ignored by front-end.");
2425 if (IsO32)
2426 WriteByValArg(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI,
2427 MFI, DAG, Arg, VA, Flags, getPointerTy(),
2428 Subtarget->isLittle());
2429 else
2430 PassByValArg64(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI,
Jia Liubb481f82012-02-28 07:46:26 +00002431 MFI, DAG, Arg, VA, Flags, getPointerTy(),
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002432 Subtarget->isLittle());
2433 continue;
2434 }
Jia Liubb481f82012-02-28 07:46:26 +00002435
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002436 // Promote the value if needed.
2437 switch (VA.getLocInfo()) {
Torok Edwinc23197a2009-07-14 16:55:14 +00002438 default: llvm_unreachable("Unknown loc info!");
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002439 case CCValAssign::Full:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002440 if (VA.isRegLoc()) {
2441 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2442 (ValVT == MVT::f64 && LocVT == MVT::i64))
2443 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
2444 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002445 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2446 Arg, DAG.getConstant(0, MVT::i32));
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00002447 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2448 Arg, DAG.getConstant(1, MVT::i32));
Akira Hatanaka99a2e982011-04-15 19:52:08 +00002449 if (!Subtarget->isLittle())
2450 std::swap(Lo, Hi);
Jia Liubb481f82012-02-28 07:46:26 +00002451 unsigned LocRegLo = VA.getLocReg();
Akira Hatanaka373e3a42011-09-23 00:58:33 +00002452 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2453 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2454 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002455 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002456 }
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002457 }
2458 break;
Chris Lattnere0b12152008-03-17 06:57:02 +00002459 case CCValAssign::SExt:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002460 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002461 break;
2462 case CCValAssign::ZExt:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002463 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002464 break;
2465 case CCValAssign::AExt:
Akira Hatanaka38bdc572012-02-17 02:20:26 +00002466 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002467 break;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002468 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002469
2470 // Arguments that can be passed on register must be kept at
Bruno Cardoso Lopesc7db5612007-11-05 03:02:32 +00002471 // RegsToPass vector
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002472 if (VA.isRegLoc()) {
2473 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
Chris Lattnere0b12152008-03-17 06:57:02 +00002474 continue;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002475 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002476
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002477 // Register can't get to this point...
Chris Lattnere0b12152008-03-17 06:57:02 +00002478 assert(VA.isMemLoc());
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002479
Chris Lattnere0b12152008-03-17 06:57:02 +00002480 // Create the frame index object for this incoming parameter
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002481 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002482 VA.getLocMemOffset(), true);
Akira Hatanaka43299772011-05-20 23:22:14 +00002483 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
Chris Lattnere0b12152008-03-17 06:57:02 +00002484
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002485 // emit ISD::STORE whichs stores the
Chris Lattnere0b12152008-03-17 06:57:02 +00002486 // parameter value to a stack Location
Chris Lattner8026a9d2010-09-21 17:50:43 +00002487 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
Akira Hatanaka82099682011-12-19 19:52:25 +00002488 MachinePointerInfo(), false, false, 0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002489 }
2490
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002491 // Extend range of indices of frame objects for outgoing arguments that were
2492 // created during this function call. Skip this step if no such objects were
2493 // created.
2494 if (LastFI)
2495 MipsFI->extendOutArgFIRange(FirstFI, LastFI);
2496
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002497 // If a memcpy has been created to copy a byval arg to a stack, replace the
2498 // chain input of CallSeqStart with ByValChain.
2499 if (InChain != ByValChain)
2500 DAG.UpdateNodeOperands(CallSeqStart.getNode(), ByValChain,
2501 NextStackOffsetVal);
2502
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002503 // Transform all store nodes into one single node because all store
2504 // nodes are independent of each other.
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002505 if (!MemOpChains.empty())
2506 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002507 &MemOpChains[0], MemOpChains.size());
2508
Bill Wendling056292f2008-09-16 21:48:12 +00002509 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002510 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2511 // node so that legalize doesn't hack it.
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002512 unsigned char OpFlag;
2513 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002514 bool GlobalOrExternal = false;
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002515 SDValue CalleeLo;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002516
2517 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002518 if (IsPICCall && G->getGlobal()->hasInternalLinkage()) {
2519 OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE;
2520 unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST;
2521 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
2522 OpFlag);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002523 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002524 0, LoFlag);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002525 } else {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002526 OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002527 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2528 getPointerTy(), 0, OpFlag);
2529 }
2530
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002531 GlobalOrExternal = true;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002532 }
2533 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002534 if (IsN64 || (!IsO32 && IsPIC))
2535 OpFlag = MipsII::MO_GOT_DISP;
2536 else if (!IsPIC) // !N64 && static
2537 OpFlag = MipsII::MO_NO_FLAG;
2538 else // O32 & PIC
2539 OpFlag = MipsII::MO_GOT_CALL;
Akira Hatanaka82099682011-12-19 19:52:25 +00002540 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2541 OpFlag);
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002542 GlobalOrExternal = true;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002543 }
2544
Akira Hatanakacd0f90f2011-05-20 02:30:51 +00002545 SDValue InFlag;
2546
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002547 // Create nodes that load address of callee and copy it to T9
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002548 if (IsPICCall) {
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002549 if (GlobalOrExternal) {
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002550 // Load callee address
Akira Hatanaka648f00c2012-02-24 22:34:47 +00002551 Callee = DAG.getNode(MipsISD::Wrapper, dl, getPointerTy(),
2552 GetGlobalReg(DAG, getPointerTy()), Callee);
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002553 SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
2554 Callee, MachinePointerInfo::getGOT(),
Pete Cooperd752e0f2011-11-08 18:42:53 +00002555 false, false, false, 0);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002556
2557 // Use GOT+LO if callee has internal linkage.
2558 if (CalleeLo.getNode()) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002559 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo);
2560 Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002561 } else
2562 Callee = LoadValue;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002563 }
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002564 }
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002565
Jia Liubb481f82012-02-28 07:46:26 +00002566 // T9 should contain the address of the callee function if
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002567 // -reloction-model=pic or it is an indirect call.
2568 if (IsPICCall || !GlobalOrExternal) {
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002569 // copy to T9
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002570 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
2571 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0));
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002572 InFlag = Chain.getValue(1);
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002573 Callee = DAG.getRegister(T9Reg, getPointerTy());
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002574 }
Bill Wendling056292f2008-09-16 21:48:12 +00002575
Akira Hatanakacd0f90f2011-05-20 02:30:51 +00002576 // Build a sequence of copy-to-reg nodes chained together with token
2577 // chain and flag operands which copy the outgoing args into registers.
2578 // The InFlag in necessary since all emitted instructions must be
2579 // stuck together.
2580 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2581 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2582 RegsToPass[i].second, InFlag);
2583 InFlag = Chain.getValue(1);
2584 }
2585
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002586 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002587 // = Chain, Callee, Reg#1, Reg#2, ...
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002588 //
2589 // Returns a chain & a flag for retval copy to use.
Chris Lattnerf1b4eaf2010-12-21 02:38:05 +00002590 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
Dan Gohman475871a2008-07-27 21:46:04 +00002591 SmallVector<SDValue, 8> Ops;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002592 Ops.push_back(Chain);
2593 Ops.push_back(Callee);
2594
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002595 // Add argument registers to the end of the list so that they are
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002596 // known live into the call.
2597 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2598 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2599 RegsToPass[i].second.getValueType()));
2600
Akira Hatanakab2930b92012-03-01 22:27:29 +00002601 // Add a register mask operand representing the call-preserved registers.
2602 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2603 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2604 assert(Mask && "Missing call preserved mask for calling convention");
2605 Ops.push_back(DAG.getRegisterMask(Mask));
2606
Gabor Greifba36cb52008-08-28 21:40:38 +00002607 if (InFlag.getNode())
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002608 Ops.push_back(InFlag);
2609
Dale Johannesen33c960f2009-02-04 20:06:27 +00002610 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002611 InFlag = Chain.getValue(1);
2612
Bruno Cardoso Lopes3ed6f872010-01-30 18:32:07 +00002613 // Create the CALLSEQ_END node.
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00002614 Chain = DAG.getCALLSEQ_END(Chain,
2615 DAG.getIntPtrConstant(NextStackOffset, true),
Bruno Cardoso Lopes3ed6f872010-01-30 18:32:07 +00002616 DAG.getIntPtrConstant(0, true), InFlag);
2617 InFlag = Chain.getValue(1);
2618
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002619 // Handle result values, copying them out of physregs into vregs that we
2620 // return.
Dan Gohman98ca4f22009-08-05 01:29:28 +00002621 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2622 Ins, dl, DAG, InVals);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002623}
2624
Dan Gohman98ca4f22009-08-05 01:29:28 +00002625/// LowerCallResult - Lower the result values of a call into the
2626/// appropriate copies out of appropriate physical registers.
2627SDValue
2628MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00002629 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +00002630 const SmallVectorImpl<ISD::InputArg> &Ins,
2631 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +00002632 SmallVectorImpl<SDValue> &InVals) const {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002633 // Assign locations to each value returned by this call.
2634 SmallVector<CCValAssign, 16> RVLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00002635 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2636 getTargetMachine(), RVLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002637
Dan Gohman98ca4f22009-08-05 01:29:28 +00002638 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002639
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002640 // Copy all of the result registers out of their specified physreg.
2641 for (unsigned i = 0; i != RVLocs.size(); ++i) {
Dale Johannesen33c960f2009-02-04 20:06:27 +00002642 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
Dan Gohman98ca4f22009-08-05 01:29:28 +00002643 RVLocs[i].getValVT(), InFlag).getValue(1);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002644 InFlag = Chain.getValue(2);
Dan Gohman98ca4f22009-08-05 01:29:28 +00002645 InVals.push_back(Chain.getValue(0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002646 }
Bruno Cardoso Lopesc7db5612007-11-05 03:02:32 +00002647
Dan Gohman98ca4f22009-08-05 01:29:28 +00002648 return Chain;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002649}
2650
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002651//===----------------------------------------------------------------------===//
Dan Gohman98ca4f22009-08-05 01:29:28 +00002652// Formal Arguments Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002653//===----------------------------------------------------------------------===//
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002654static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl,
2655 std::vector<SDValue>& OutChains,
2656 SelectionDAG &DAG, unsigned NumWords, SDValue FIN,
Akira Hatanakab4549e12012-03-27 03:13:56 +00002657 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
2658 const Argument *FuncArg) {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002659 unsigned LocMem = VA.getLocMemOffset();
2660 unsigned FirstWord = LocMem / 4;
2661
2662 // copy register A0 - A3 to frame object
2663 for (unsigned i = 0; i < NumWords; ++i) {
2664 unsigned CurWord = FirstWord + i;
2665 if (CurWord >= O32IntRegsSize)
2666 break;
2667
2668 unsigned SrcReg = O32IntRegs[CurWord];
Craig Topper420761a2012-04-20 07:30:17 +00002669 unsigned Reg = AddLiveIn(MF, SrcReg, &Mips::CPURegsRegClass);
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002670 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
2671 DAG.getConstant(i * 4, MVT::i32));
2672 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32),
Akira Hatanakab4549e12012-03-27 03:13:56 +00002673 StorePtr, MachinePointerInfo(FuncArg, i * 4),
2674 false, false, 0);
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002675 OutChains.push_back(Store);
2676 }
2677}
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002678
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002679// Create frame object on stack and copy registers used for byval passing to it.
2680static unsigned
2681CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl,
2682 std::vector<SDValue>& OutChains, SelectionDAG &DAG,
2683 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
2684 MachineFrameInfo *MFI, bool IsRegLoc,
2685 SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI,
Akira Hatanakab4549e12012-03-27 03:13:56 +00002686 EVT PtrTy, const Argument *FuncArg) {
Craig Topperc5eaae42012-03-11 07:57:25 +00002687 const uint16_t *Reg = Mips64IntRegs + 8;
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002688 int FOOffset; // Frame object offset from virtual frame pointer.
2689
2690 if (IsRegLoc) {
2691 Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, VA.getLocReg());
2692 FOOffset = (Reg - Mips64IntRegs) * 8 - 8 * 8;
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002693 }
2694 else
2695 FOOffset = VA.getLocMemOffset();
2696
2697 // Create frame object.
2698 unsigned NumRegs = (Flags.getByValSize() + 7) / 8;
2699 unsigned LastFI = MFI->CreateFixedObject(NumRegs * 8, FOOffset, true);
2700 SDValue FIN = DAG.getFrameIndex(LastFI, PtrTy);
2701 InVals.push_back(FIN);
2702
2703 // Copy arg registers.
2704 for (unsigned I = 0; (Reg != Mips64IntRegs + 8) && (I < NumRegs);
2705 ++Reg, ++I) {
Craig Topper420761a2012-04-20 07:30:17 +00002706 unsigned VReg = AddLiveIn(MF, *Reg, &Mips::CPU64RegsRegClass);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002707 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, PtrTy, FIN,
2708 DAG.getConstant(I * 8, PtrTy));
2709 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64),
Akira Hatanakab4549e12012-03-27 03:13:56 +00002710 StorePtr, MachinePointerInfo(FuncArg, I * 8),
2711 false, false, 0);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002712 OutChains.push_back(Store);
2713 }
Jia Liubb481f82012-02-28 07:46:26 +00002714
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002715 return LastFI;
2716}
2717
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002718/// LowerFormalArguments - transform physical registers into virtual registers
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002719/// and generate load operations for arguments places on the stack.
Dan Gohman98ca4f22009-08-05 01:29:28 +00002720SDValue
2721MipsTargetLowering::LowerFormalArguments(SDValue Chain,
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00002722 CallingConv::ID CallConv,
2723 bool isVarArg,
Akira Hatanaka82099682011-12-19 19:52:25 +00002724 const SmallVectorImpl<ISD::InputArg> &Ins,
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00002725 DebugLoc dl, SelectionDAG &DAG,
2726 SmallVectorImpl<SDValue> &InVals)
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002727 const {
Bruno Cardoso Lopesf7f3b502008-08-04 07:12:52 +00002728 MachineFunction &MF = DAG.getMachineFunction();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002729 MachineFrameInfo *MFI = MF.getFrameInfo();
Bruno Cardoso Lopesa2b1bb52007-08-28 05:08:16 +00002730 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002731
Dan Gohman1e93df62010-04-17 14:41:14 +00002732 MipsFI->setVarArgsFrameIndex(0);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002733
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002734 // Used with vargs to acumulate store chains.
2735 std::vector<SDValue> OutChains;
2736
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002737 // Assign locations to all of the incoming arguments.
2738 SmallVector<CCValAssign, 16> ArgLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00002739 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka82099682011-12-19 19:52:25 +00002740 getTargetMachine(), ArgLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002741
Akira Hatanaka2ec69fa2011-10-28 18:47:24 +00002742 if (IsO32)
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002743 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002744 else
Dan Gohman98ca4f22009-08-05 01:29:28 +00002745 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002746
Akira Hatanakab4549e12012-03-27 03:13:56 +00002747 Function::const_arg_iterator FuncArg =
2748 DAG.getMachineFunction().getFunction()->arg_begin();
Akira Hatanaka43299772011-05-20 23:22:14 +00002749 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function.
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002750
Akira Hatanakab4549e12012-03-27 03:13:56 +00002751 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++FuncArg) {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002752 CCValAssign &VA = ArgLocs[i];
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00002753 EVT ValVT = VA.getValVT();
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002754 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2755 bool IsRegLoc = VA.isRegLoc();
2756
2757 if (Flags.isByVal()) {
2758 assert(Flags.getByValSize() &&
2759 "ByVal args of size 0 should have been ignored by front-end.");
2760 if (IsO32) {
2761 unsigned NumWords = (Flags.getByValSize() + 3) / 4;
2762 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(),
2763 true);
2764 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
2765 InVals.push_back(FIN);
Akira Hatanakab4549e12012-03-27 03:13:56 +00002766 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags,
2767 &*FuncArg);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002768 } else // N32/64
2769 LastFI = CopyMips64ByValRegs(MF, Chain, dl, OutChains, DAG, VA, Flags,
2770 MFI, IsRegLoc, InVals, MipsFI,
Akira Hatanakab4549e12012-03-27 03:13:56 +00002771 getPointerTy(), &*FuncArg);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002772 continue;
2773 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002774
2775 // Arguments stored on registers
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002776 if (IsRegLoc) {
Owen Andersone50ed302009-08-10 22:56:29 +00002777 EVT RegVT = VA.getLocVT();
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002778 unsigned ArgReg = VA.getLocReg();
Craig Topper44d23822012-02-22 05:59:10 +00002779 const TargetRegisterClass *RC;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002780
Owen Anderson825b72b2009-08-11 20:47:22 +00002781 if (RegVT == MVT::i32)
Craig Topper420761a2012-04-20 07:30:17 +00002782 RC = &Mips::CPURegsRegClass;
Akira Hatanaka95934842011-09-24 01:34:44 +00002783 else if (RegVT == MVT::i64)
Craig Topper420761a2012-04-20 07:30:17 +00002784 RC = &Mips::CPU64RegsRegClass;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002785 else if (RegVT == MVT::f32)
Craig Topper420761a2012-04-20 07:30:17 +00002786 RC = &Mips::FGR32RegClass;
Akira Hatanaka09dd60f2011-09-26 21:37:50 +00002787 else if (RegVT == MVT::f64)
Craig Topper420761a2012-04-20 07:30:17 +00002788 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
Akira Hatanaka09dd60f2011-09-26 21:37:50 +00002789 else
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002790 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002791
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002792 // Transform the arguments stored on
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002793 // physical registers into virtual ones
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002794 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
Dan Gohman98ca4f22009-08-05 01:29:28 +00002795 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002796
2797 // If this is an 8 or 16-bit value, it has been passed promoted
2798 // to 32 bits. Insert an assert[sz]ext to capture this, then
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002799 // truncate to the right size.
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002800 if (VA.getLocInfo() != CCValAssign::Full) {
Chris Lattnerd4015072009-03-26 05:28:14 +00002801 unsigned Opcode = 0;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002802 if (VA.getLocInfo() == CCValAssign::SExt)
2803 Opcode = ISD::AssertSext;
2804 else if (VA.getLocInfo() == CCValAssign::ZExt)
2805 Opcode = ISD::AssertZext;
Chris Lattnerd4015072009-03-26 05:28:14 +00002806 if (Opcode)
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002807 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00002808 DAG.getValueType(ValVT));
2809 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002810 }
2811
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00002812 // Handle floating point arguments passed in integer registers.
2813 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
2814 (RegVT == MVT::i64 && ValVT == MVT::f64))
2815 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
2816 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
2817 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
2818 getNextIntArgReg(ArgReg), RC);
2819 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
2820 if (!Subtarget->isLittle())
2821 std::swap(ArgValue, ArgValue2);
2822 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
2823 ArgValue, ArgValue2);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002824 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002825
Dan Gohman98ca4f22009-08-05 01:29:28 +00002826 InVals.push_back(ArgValue);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002827 } else { // VA.isRegLoc()
2828
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002829 // sanity check
2830 assert(VA.isMemLoc());
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002831
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002832 // The stack pointer offset is relative to the caller stack frame.
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00002833 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002834 VA.getLocMemOffset(), true);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002835
2836 // Create load nodes to retrieve arguments from the stack
Akira Hatanaka43299772011-05-20 23:22:14 +00002837 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00002838 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
Akira Hatanaka43299772011-05-20 23:22:14 +00002839 MachinePointerInfo::getFixedStack(LastFI),
Pete Cooperd752e0f2011-11-08 18:42:53 +00002840 false, false, false, 0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002841 }
2842 }
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002843
2844 // The mips ABIs for returning structs by value requires that we copy
2845 // the sret argument into $v0 for the return. Save the argument into
2846 // a virtual register so that we can access it from the return points.
2847 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2848 unsigned Reg = MipsFI->getSRetReturnReg();
2849 if (!Reg) {
Owen Anderson825b72b2009-08-11 20:47:22 +00002850 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002851 MipsFI->setSRetReturnReg(Reg);
2852 }
Dan Gohman98ca4f22009-08-05 01:29:28 +00002853 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
Owen Anderson825b72b2009-08-11 20:47:22 +00002854 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002855 }
2856
Akira Hatanakabad53f42011-11-14 19:01:09 +00002857 if (isVarArg) {
2858 unsigned NumOfRegs = IsO32 ? 4 : 8;
Craig Topperc5eaae42012-03-11 07:57:25 +00002859 const uint16_t *ArgRegs = IsO32 ? O32IntRegs : Mips64IntRegs;
Akira Hatanakabad53f42011-11-14 19:01:09 +00002860 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumOfRegs);
2861 int FirstRegSlotOffset = IsO32 ? 0 : -64 ; // offset of $a0's slot.
Craig Topper420761a2012-04-20 07:30:17 +00002862 const TargetRegisterClass *RC = IsO32 ?
2863 (const TargetRegisterClass*)&Mips::CPURegsRegClass :
2864 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
Akira Hatanakabad53f42011-11-14 19:01:09 +00002865 unsigned RegSize = RC->getSize();
2866 int RegSlotOffset = FirstRegSlotOffset + Idx * RegSize;
2867
2868 // Offset of the first variable argument from stack pointer.
2869 int FirstVaArgOffset;
2870
2871 if (IsO32 || (Idx == NumOfRegs)) {
2872 FirstVaArgOffset =
2873 (CCInfo.getNextStackOffset() + RegSize - 1) / RegSize * RegSize;
2874 } else
2875 FirstVaArgOffset = RegSlotOffset;
2876
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002877 // Record the frame index of the first variable argument
Eric Christopher471e4222011-06-08 23:55:35 +00002878 // which is a value necessary to VASTART.
Akira Hatanakabad53f42011-11-14 19:01:09 +00002879 LastFI = MFI->CreateFixedObject(RegSize, FirstVaArgOffset, true);
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002880 MipsFI->setVarArgsFrameIndex(LastFI);
Akira Hatanakaedacba82011-05-25 17:32:06 +00002881
Akira Hatanakabad53f42011-11-14 19:01:09 +00002882 // Copy the integer registers that have not been used for argument passing
2883 // to the argument register save area. For O32, the save area is allocated
2884 // in the caller's stack frame, while for N32/64, it is allocated in the
2885 // callee's stack frame.
2886 for (int StackOffset = RegSlotOffset;
2887 Idx < NumOfRegs; ++Idx, StackOffset += RegSize) {
2888 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegs[Idx], RC);
2889 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2890 MVT::getIntegerVT(RegSize * 8));
2891 LastFI = MFI->CreateFixedObject(RegSize, StackOffset, true);
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002892 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
2893 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
Akira Hatanaka82099682011-12-19 19:52:25 +00002894 MachinePointerInfo(), false, false, 0));
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002895 }
2896 }
2897
Akira Hatanaka43299772011-05-20 23:22:14 +00002898 MipsFI->setLastInArgFI(LastFI);
2899
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002900 // All stores are grouped in one node to allow the matching between
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002901 // the size of Ins and InVals. This only happens when on varg functions
2902 if (!OutChains.empty()) {
2903 OutChains.push_back(Chain);
2904 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2905 &OutChains[0], OutChains.size());
2906 }
2907
Dan Gohman98ca4f22009-08-05 01:29:28 +00002908 return Chain;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002909}
2910
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002911//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002912// Return Value Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002913//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002914
Dan Gohman98ca4f22009-08-05 01:29:28 +00002915SDValue
2916MipsTargetLowering::LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00002917 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +00002918 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +00002919 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmand858e902010-04-17 15:26:15 +00002920 DebugLoc dl, SelectionDAG &DAG) const {
Dan Gohman98ca4f22009-08-05 01:29:28 +00002921
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002922 // CCValAssign - represent the assignment of
2923 // the return value to a location
2924 SmallVector<CCValAssign, 16> RVLocs;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002925
2926 // CCState - Info about the registers and stack slot.
Eric Christopher471e4222011-06-08 23:55:35 +00002927 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2928 getTargetMachine(), RVLocs, *DAG.getContext());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002929
Dan Gohman98ca4f22009-08-05 01:29:28 +00002930 // Analize return values.
2931 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002932
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002933 // If this is the first return lowered for this function, add
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002934 // the regs to the liveout set for the function.
Chris Lattner84bc5422007-12-31 04:13:23 +00002935 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002936 for (unsigned i = 0; i != RVLocs.size(); ++i)
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002937 if (RVLocs[i].isRegLoc())
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002938 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002939 }
2940
Dan Gohman475871a2008-07-27 21:46:04 +00002941 SDValue Flag;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002942
2943 // Copy the result values into the output registers.
2944 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2945 CCValAssign &VA = RVLocs[i];
2946 assert(VA.isRegLoc() && "Can only return in registers!");
2947
Akira Hatanaka82099682011-12-19 19:52:25 +00002948 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002949
2950 // guarantee that all emitted copies are
2951 // stuck together, avoiding something bad
2952 Flag = Chain.getValue(1);
2953 }
2954
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002955 // The mips ABIs for returning structs by value requires that we copy
2956 // the sret argument into $v0 for the return. We saved the argument into
2957 // a virtual register in the entry block, so now we copy the value out
2958 // and into $v0.
2959 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2960 MachineFunction &MF = DAG.getMachineFunction();
2961 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2962 unsigned Reg = MipsFI->getSRetReturnReg();
2963
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002964 if (!Reg)
Torok Edwinc23197a2009-07-14 16:55:14 +00002965 llvm_unreachable("sret virtual register not created in the entry block");
Dale Johannesena05dca42009-02-04 23:02:30 +00002966 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002967
Dale Johannesena05dca42009-02-04 23:02:30 +00002968 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002969 Flag = Chain.getValue(1);
2970 }
2971
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002972 // Return on Mips is always a "jr $ra"
Gabor Greifba36cb52008-08-28 21:40:38 +00002973 if (Flag.getNode())
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002974 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
Owen Anderson825b72b2009-08-11 20:47:22 +00002975 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002976 else // Return Void
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002977 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
Owen Anderson825b72b2009-08-11 20:47:22 +00002978 Chain, DAG.getRegister(Mips::RA, MVT::i32));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002979}
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002980
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002981//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002982// Mips Inline Assembly Support
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002983//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002984
2985/// getConstraintType - Given a constraint letter, return the type of
2986/// constraint it is for this target.
2987MipsTargetLowering::ConstraintType MipsTargetLowering::
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002988getConstraintType(const std::string &Constraint) const
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002989{
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002990 // Mips specific constrainy
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002991 // GCC config/mips/constraints.md
2992 //
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002993 // 'd' : An address register. Equivalent to r
2994 // unless generating MIPS16 code.
2995 // 'y' : Equivalent to r; retained for
2996 // backwards compatibility.
2997 // 'f' : Floating Point registers.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002998 if (Constraint.size() == 1) {
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002999 switch (Constraint[0]) {
3000 default : break;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003001 case 'd':
3002 case 'y':
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003003 case 'f':
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003004 return C_RegisterClass;
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003005 }
3006 }
3007 return TargetLowering::getConstraintType(Constraint);
3008}
3009
John Thompson44ab89e2010-10-29 17:29:13 +00003010/// Examine constraint type and operand type and determine a weight value.
3011/// This object must already have been set up with the operand type
3012/// and the current alternative constraint selected.
3013TargetLowering::ConstraintWeight
3014MipsTargetLowering::getSingleConstraintMatchWeight(
3015 AsmOperandInfo &info, const char *constraint) const {
3016 ConstraintWeight weight = CW_Invalid;
3017 Value *CallOperandVal = info.CallOperandVal;
3018 // If we don't have a value, we can't do a match,
3019 // but allow it at the lowest weight.
3020 if (CallOperandVal == NULL)
3021 return CW_Default;
Chris Lattnerdb125cf2011-07-18 04:54:35 +00003022 Type *type = CallOperandVal->getType();
John Thompson44ab89e2010-10-29 17:29:13 +00003023 // Look at the constraint type.
3024 switch (*constraint) {
3025 default:
3026 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3027 break;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003028 case 'd':
3029 case 'y':
John Thompson44ab89e2010-10-29 17:29:13 +00003030 if (type->isIntegerTy())
3031 weight = CW_Register;
3032 break;
3033 case 'f':
3034 if (type->isFloatTy())
3035 weight = CW_Register;
3036 break;
3037 }
3038 return weight;
3039}
3040
Eric Christopher38d64262011-06-29 19:33:04 +00003041/// Given a register class constraint, like 'r', if this corresponds directly
3042/// to an LLVM register class, return a register of 0 and the register class
3043/// pointer.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003044std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
Owen Andersone50ed302009-08-10 22:56:29 +00003045getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003046{
3047 if (Constraint.size() == 1) {
3048 switch (Constraint[0]) {
Eric Christopher314aff12011-06-29 19:04:31 +00003049 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3050 case 'y': // Same as 'r'. Exists for compatibility.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003051 case 'r':
Akira Hatanakacb9dd722012-01-04 02:45:01 +00003052 if (VT == MVT::i32)
Craig Topper420761a2012-04-20 07:30:17 +00003053 return std::make_pair(0U, &Mips::CPURegsRegClass);
Akira Hatanakacb9dd722012-01-04 02:45:01 +00003054 assert(VT == MVT::i64 && "Unexpected type.");
Craig Topper420761a2012-04-20 07:30:17 +00003055 return std::make_pair(0U, &Mips::CPU64RegsRegClass);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003056 case 'f':
Owen Anderson825b72b2009-08-11 20:47:22 +00003057 if (VT == MVT::f32)
Craig Topper420761a2012-04-20 07:30:17 +00003058 return std::make_pair(0U, &Mips::FGR32RegClass);
Akira Hatanakacb9dd722012-01-04 02:45:01 +00003059 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
3060 if (Subtarget->isFP64bit())
Craig Topper420761a2012-04-20 07:30:17 +00003061 return std::make_pair(0U, &Mips::FGR64RegClass);
3062 return std::make_pair(0U, &Mips::AFGR64RegClass);
Akira Hatanakacb9dd722012-01-04 02:45:01 +00003063 }
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003064 }
3065 }
3066 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3067}
3068
Dan Gohman6520e202008-10-18 02:06:02 +00003069bool
3070MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3071 // The Mips target isn't yet aware of offsets.
3072 return false;
3073}
Evan Chengeb2f9692009-10-27 19:56:55 +00003074
Evan Chenga1eaa3c2009-10-28 01:43:28 +00003075bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3076 if (VT != MVT::f32 && VT != MVT::f64)
3077 return false;
Bruno Cardoso Lopes6b902822011-01-18 19:41:41 +00003078 if (Imm.isNegZero())
3079 return false;
Evan Chengeb2f9692009-10-27 19:56:55 +00003080 return Imm.isZero();
3081}
Akira Hatanaka6c2cf8b2012-02-03 04:33:00 +00003082
3083unsigned MipsTargetLowering::getJumpTableEncoding() const {
3084 if (IsN64)
3085 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
Jia Liubb481f82012-02-28 07:46:26 +00003086
Akira Hatanaka6c2cf8b2012-02-03 04:33:00 +00003087 return TargetLowering::getJumpTableEncoding();
3088}