Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame^] | 1 | //===-- ARMHazardRecognizer.h - ARM Hazard Recognizers ----------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines hazard recognizers for scheduling ARM functions. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #ifndef ARMHAZARDRECOGNIZER_H |
| 15 | #define ARMHAZARDRECOGNIZER_H |
| 16 | |
| 17 | #include "llvm/CodeGen/PostRAHazardRecognizer.h" |
| 18 | |
| 19 | namespace llvm { |
| 20 | |
| 21 | class ARMBaseInstrInfo; |
| 22 | class ARMBaseRegisterInfo; |
| 23 | class ARMSubtarget; |
| 24 | class MachineInstr; |
| 25 | |
| 26 | class ARMHazardRecognizer : public PostRAHazardRecognizer { |
| 27 | const ARMBaseInstrInfo &TII; |
| 28 | const ARMBaseRegisterInfo &TRI; |
| 29 | const ARMSubtarget &STI; |
| 30 | |
| 31 | MachineInstr *LastMI; |
| 32 | unsigned Stalls; |
| 33 | unsigned ITBlockSize; // No. of MIs in current IT block yet to be scheduled. |
| 34 | MachineInstr *ITBlockMIs[4]; |
| 35 | |
| 36 | public: |
| 37 | ARMHazardRecognizer(const InstrItineraryData *ItinData, |
| 38 | const ARMBaseInstrInfo &tii, |
| 39 | const ARMBaseRegisterInfo &tri, |
| 40 | const ARMSubtarget &sti) : |
| 41 | PostRAHazardRecognizer(ItinData), TII(tii), TRI(tri), STI(sti), |
| 42 | LastMI(0), ITBlockSize(0) {} |
| 43 | |
| 44 | virtual HazardType getHazardType(SUnit *SU); |
| 45 | virtual void Reset(); |
| 46 | virtual void EmitInstruction(SUnit *SU); |
| 47 | virtual void AdvanceCycle(); |
| 48 | }; |
| 49 | |
| 50 | |
| 51 | } // end namespace llvm |
| 52 | |
| 53 | #endif // ARMHAZARDRECOGNIZER_H |