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Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]6 <title>The LLVM Target-Independent Code Generator</title>
7 <link rel="stylesheet" href="llvm.css" type="text/css">
8</head>
9<body>
10
11<div class="doc_title">
12 The LLVM Target-Independent Code Generator
13</div>
14
15<ol>
16 <li><a href="#introduction">Introduction</a>
17 <ul>
18 <li><a href="#required">Required components in the code generator</a></li>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]19 <li><a href="#high-level-design">The high-level design of the code
20 generator</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]21 <li><a href="#tablegen">Using TableGen for target description</a></li>
22 </ul>
23 </li>
24 <li><a href="#targetdesc">Target description classes</a>
25 <ul>
26 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
27 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]28 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]29 <li><a href="#targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]30 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
31 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]32 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]33 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
34 </ul>
35 </li>
36 <li><a href="#codegendesc">Machine code description classes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]37 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]38 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]39 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
40 class</a></li>
41 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]42 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]43 </li>
44 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]45 <ul>
46 <li><a href="#instselect">Instruction Selection</a>
47 <ul>
48 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
49 <li><a href="#selectiondag_process">SelectionDAG Code Generation
50 Process</a></li>
51 <li><a href="#selectiondag_build">Initial SelectionDAG
52 Construction</a></li>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]53 <li><a href="#selectiondag_legalize_types">SelectionDAG LegalizeTypes Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]54 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
55 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]56 Phase: the DAG Combiner</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]57 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]58 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]59 Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]60 <li><a href="#selectiondag_future">Future directions for the
61 SelectionDAG</a></li>
62 </ul></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]63 <li><a href="#liveintervals">Live Intervals</a>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]64 <ul>
65 <li><a href="#livevariable_analysis">Live Variable Analysis</a></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]66 <li><a href="#liveintervals_analysis">Live Intervals Analysis</a></li>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]67 </ul></li>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]68 <li><a href="#regalloc">Register Allocation</a>
69 <ul>
70 <li><a href="#regAlloc_represent">How registers are represented in
71 LLVM</a></li>
72 <li><a href="#regAlloc_howTo">Mapping virtual registers to physical
73 registers</a></li>
74 <li><a href="#regAlloc_twoAddr">Handling two address instructions</a></li>
75 <li><a href="#regAlloc_ssaDecon">The SSA deconstruction phase</a></li>
76 <li><a href="#regAlloc_fold">Instruction folding</a></li>
77 <li><a href="#regAlloc_builtIn">Built in register allocators</a></li>
78 </ul></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]79 <li><a href="#codeemit">Code Emission</a>
80 <ul>
81 <li><a href="#codeemit_asm">Generating Assembly Code</a></li>
82 <li><a href="#codeemit_bin">Generating Binary Machine Code</a></li>
83 </ul></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]84 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]85 </li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]86 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]87 <ul>
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]88 <li><a href="#tailcallopt">Tail call optimization</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]89 <li><a href="#x86">The X86 backend</a></li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]90 <li><a href="#ppc">The PowerPC backend</a>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]91 <ul>
92 <li><a href="#ppc_abi">LLVM PowerPC ABI</a></li>
93 <li><a href="#ppc_frame">Frame Layout</a></li>
94 <li><a href="#ppc_prolog">Prolog/Epilog</a></li>
95 <li><a href="#ppc_dynamic">Dynamic Allocation</a></li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]96 </ul></li>
97 </ul></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]98
99</ol>
100
101<div class="doc_author">
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]102 <p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a>,
Jim Laskeyd201f4e2007-03-14 19:30:33 +0000[diff] [blame]103 <a href="mailto:isanbard@gmail.com">Bill Wendling</a>,
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]104 <a href="mailto:pronesto@gmail.com">Fernando Magno Quintao
Jim Laskeyd201f4e2007-03-14 19:30:33 +0000[diff] [blame]105 Pereira</a> and
106 <a href="mailto:jlaskey@mac.com">Jim Laskey</a></p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]107</div>
108
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]109<div class="doc_warning">
110 <p>Warning: This is a work in progress.</p>
111</div>
112
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]113<!-- *********************************************************************** -->
114<div class="doc_section">
115 <a name="introduction">Introduction</a>
116</div>
117<!-- *********************************************************************** -->
118
119<div class="doc_text">
120
121<p>The LLVM target-independent code generator is a framework that provides a
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]122 suite of reusable components for translating the LLVM internal representation
123 to the machine code for a specified target&mdash;either in assembly form
124 (suitable for a static compiler) or in binary machine code format (usable for
125 a JIT compiler). The LLVM target-independent code generator consists of five
126 main components:</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]127
128<ol>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]129 <li><a href="#targetdesc">Abstract target description</a> interfaces which
130 capture important properties about various aspects of the machine,
131 independently of how they will be used. These interfaces are defined in
132 <tt>include/llvm/Target/</tt>.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]133
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]134 <li>Classes used to represent the <a href="#codegendesc">machine code</a>
135 being generated for a target. These classes are intended to be abstract
136 enough to represent the machine code for <i>any</i> target machine. These
137 classes are defined in <tt>include/llvm/CodeGen/</tt>.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]138
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]139 <li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
140 various phases of native code generation (register allocation, scheduling,
141 stack frame representation, etc). This code lives
142 in <tt>lib/CodeGen/</tt>.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]143
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]144 <li><a href="#targetimpls">Implementations of the abstract target description
145 interfaces</a> for particular targets. These machine descriptions make
146 use of the components provided by LLVM, and can optionally provide custom
147 target-specific passes, to build complete code generators for a specific
148 target. Target descriptions live in <tt>lib/Target/</tt>.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]149
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]150 <li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
151 completely target independent (it uses the <tt>TargetJITInfo</tt>
152 structure to interface for target-specific issues. The code for the
153 target-independent JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]154</ol>
155
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]156<p>Depending on which part of the code generator you are interested in working
157 on, different pieces of this will be useful to you. In any case, you should
158 be familiar with the <a href="#targetdesc">target description</a>
159 and <a href="#codegendesc">machine code representation</a> classes. If you
160 want to add a backend for a new target, you will need
161 to <a href="#targetimpls">implement the target description</a> classes for
162 your new target and understand the <a href="LangRef.html">LLVM code
163 representation</a>. If you are interested in implementing a
164 new <a href="#codegenalgs">code generation algorithm</a>, it should only
165 depend on the target-description and machine code representation classes,
166 ensuring that it is portable.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]167
168</div>
169
170<!-- ======================================================================= -->
171<div class="doc_subsection">
172 <a name="required">Required components in the code generator</a>
173</div>
174
175<div class="doc_text">
176
177<p>The two pieces of the LLVM code generator are the high-level interface to the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]178 code generator and the set of reusable components that can be used to build
179 target-specific backends. The two most important interfaces
180 (<a href="#targetmachine"><tt>TargetMachine</tt></a>
181 and <a href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
182 required to be defined for a backend to fit into the LLVM system, but the
183 others must be defined if the reusable code generator components are going to
184 be used.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]185
186<p>This design has two important implications. The first is that LLVM can
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]187 support completely non-traditional code generation targets. For example, the
188 C backend does not require register allocation, instruction selection, or any
189 of the other standard components provided by the system. As such, it only
190 implements these two interfaces, and does its own thing. Another example of
191 a code generator like this is a (purely hypothetical) backend that converts
192 LLVM to the GCC RTL form and uses GCC to emit machine code for a target.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]193
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]194<p>This design also implies that it is possible to design and implement
195 radically different code generators in the LLVM system that do not make use
196 of any of the built-in components. Doing so is not recommended at all, but
197 could be required for radically different targets that do not fit into the
198 LLVM machine description model: FPGAs for example.</p>
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]199
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]200</div>
201
202<!-- ======================================================================= -->
203<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]204 <a name="high-level-design">The high-level design of the code generator</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]205</div>
206
207<div class="doc_text">
208
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]209<p>The LLVM target-independent code generator is designed to support efficient
210 and quality code generation for standard register-based microprocessors.
211 Code generation in this model is divided into the following stages:</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]212
213<ol>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]214 <li><b><a href="#instselect">Instruction Selection</a></b> &mdash; This phase
215 determines an efficient way to express the input LLVM code in the target
216 instruction set. This stage produces the initial code for the program in
217 the target instruction set, then makes use of virtual registers in SSA
218 form and physical registers that represent any required register
219 assignments due to target constraints or calling conventions. This step
220 turns the LLVM code into a DAG of target instructions.</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]221
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]222 <li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> &mdash;
223 This phase takes the DAG of target instructions produced by the
224 instruction selection phase, determines an ordering of the instructions,
225 then emits the instructions
226 as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering.
227 Note that we describe this in the <a href="#instselect">instruction
228 selection section</a> because it operates on
229 a <a href="#selectiondag_intro">SelectionDAG</a>.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]230
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]231 <li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> &mdash;
232 This optional stage consists of a series of machine-code optimizations
233 that operate on the SSA-form produced by the instruction selector.
234 Optimizations like modulo-scheduling or peephole optimization work
235 here.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]236
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]237 <li><b><a href="#regalloc">Register Allocation</a></b> &mdash; The target code
238 is transformed from an infinite virtual register file in SSA form to the
239 concrete register file used by the target. This phase introduces spill
240 code and eliminates all virtual register references from the program.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]241
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]242 <li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> &mdash; Once
243 the machine code has been generated for the function and the amount of
244 stack space required is known (used for LLVM alloca's and spill slots),
245 the prolog and epilog code for the function can be inserted and "abstract
246 stack location references" can be eliminated. This stage is responsible
247 for implementing optimizations like frame-pointer elimination and stack
248 packing.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]249
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]250 <li><b><a href="#latemco">Late Machine Code Optimizations</a></b> &mdash;
251 Optimizations that operate on "final" machine code can go here, such as
252 spill code scheduling and peephole optimizations.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]253
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]254 <li><b><a href="#codeemit">Code Emission</a></b> &mdash; The final stage
255 actually puts out the code for the current function, either in the target
256 assembler format or in machine code.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]257</ol>
258
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]259<p>The code generator is based on the assumption that the instruction selector
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]260 will use an optimal pattern matching selector to create high-quality
261 sequences of native instructions. Alternative code generator designs based
262 on pattern expansion and aggressive iterative peephole optimization are much
263 slower. This design permits efficient compilation (important for JIT
264 environments) and aggressive optimization (used when generating code offline)
265 by allowing components of varying levels of sophistication to be used for any
266 step of compilation.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]267
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]268<p>In addition to these stages, target implementations can insert arbitrary
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]269 target-specific passes into the flow. For example, the X86 target uses a
270 special pass to handle the 80x87 floating point stack architecture. Other
271 targets with unusual requirements can be supported with custom passes as
272 needed.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]273
274</div>
275
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]276<!-- ======================================================================= -->
277<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]278 <a name="tablegen">Using TableGen for target description</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]279</div>
280
281<div class="doc_text">
282
Chris Lattner5489e932004-06-01 18:35:00 +0000[diff] [blame]283<p>The target description classes require a detailed description of the target
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]284 architecture. These target descriptions often have a large amount of common
285 information (e.g., an <tt>add</tt> instruction is almost identical to a
286 <tt>sub</tt> instruction). In order to allow the maximum amount of
287 commonality to be factored out, the LLVM code generator uses
288 the <a href="TableGenFundamentals.html">TableGen</a> tool to describe big
289 chunks of the target machine, which allows the use of domain-specific and
290 target-specific abstractions to reduce the amount of repetition.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]291
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]292<p>As LLVM continues to be developed and refined, we plan to move more and more
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]293 of the target description to the <tt>.td</tt> form. Doing so gives us a
294 number of advantages. The most important is that it makes it easier to port
295 LLVM because it reduces the amount of C++ code that has to be written, and
296 the surface area of the code generator that needs to be understood before
297 someone can get something working. Second, it makes it easier to change
298 things. In particular, if tables and other things are all emitted
299 by <tt>tblgen</tt>, we only need a change in one place (<tt>tblgen</tt>) to
300 update all of the targets to a new interface.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]301
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]302</div>
303
304<!-- *********************************************************************** -->
305<div class="doc_section">
306 <a name="targetdesc">Target description classes</a>
307</div>
308<!-- *********************************************************************** -->
309
310<div class="doc_text">
311
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]312<p>The LLVM target description classes (located in the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]313 <tt>include/llvm/Target</tt> directory) provide an abstract description of
314 the target machine independent of any particular client. These classes are
315 designed to capture the <i>abstract</i> properties of the target (such as the
316 instructions and registers it has), and do not incorporate any particular
317 pieces of code generation algorithms.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]318
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]319<p>All of the target description classes (except the
320 <tt><a href="#targetdata">TargetData</a></tt> class) are designed to be
321 subclassed by the concrete target implementation, and have virtual methods
322 implemented. To get to these implementations, the
323 <tt><a href="#targetmachine">TargetMachine</a></tt> class provides accessors
324 that should be implemented by the target.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]325
326</div>
327
328<!-- ======================================================================= -->
329<div class="doc_subsection">
330 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
331</div>
332
333<div class="doc_text">
334
335<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]336 access the target-specific implementations of the various target description
337 classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
338 <tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
339 designed to be specialized by a concrete target implementation
340 (e.g., <tt>X86TargetMachine</tt>) which implements the various virtual
341 methods. The only required target description class is
342 the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the code
343 generator components are to be used, the other interfaces should be
344 implemented as well.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]345
346</div>
347
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]348<!-- ======================================================================= -->
349<div class="doc_subsection">
350 <a name="targetdata">The <tt>TargetData</tt> class</a>
351</div>
352
353<div class="doc_text">
354
355<p>The <tt>TargetData</tt> class is the only required target description class,
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]356 and it is the only class that is not extensible (you cannot derived a new
357 class from it). <tt>TargetData</tt> specifies information about how the
358 target lays out memory for structures, the alignment requirements for various
359 data types, the size of pointers in the target, and whether the target is
360 little-endian or big-endian.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]361
362</div>
363
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]364<!-- ======================================================================= -->
365<div class="doc_subsection">
366 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
367</div>
368
369<div class="doc_text">
370
371<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]372 selectors primarily to describe how LLVM code should be lowered to
373 SelectionDAG operations. Among other things, this class indicates:</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]374
375<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]376 <li>an initial register class to use for various <tt>ValueType</tt>s,</li>
377
378 <li>which operations are natively supported by the target machine,</li>
379
380 <li>the return type of <tt>setcc</tt> operations,</li>
381
382 <li>the type to use for shift amounts, and</li>
383
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]384 <li>various high-level characteristics, like whether it is profitable to turn
385 division by a constant into a multiplication sequence</li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]386</ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]387
388</div>
389
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]390<!-- ======================================================================= -->
391<div class="doc_subsection">
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]392 <a name="targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]393</div>
394
395<div class="doc_text">
396
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]397<p>The <tt>TargetRegisterInfo</tt> class is used to describe the register file
398 of the target and any interactions between the registers.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]399
400<p>Registers in the code generator are represented in the code generator by
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]401 unsigned integers. Physical registers (those that actually exist in the
402 target description) are unique small numbers, and virtual registers are
403 generally large. Note that register #0 is reserved as a flag value.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]404
405<p>Each register in the processor description has an associated
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]406 <tt>TargetRegisterDesc</tt> entry, which provides a textual name for the
407 register (used for assembly output and debugging dumps) and a set of aliases
408 (used to indicate whether one register overlaps with another).</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]409
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]410<p>In addition to the per-register description, the <tt>TargetRegisterInfo</tt>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]411 class exposes a set of processor specific register classes (instances of the
412 <tt>TargetRegisterClass</tt> class). Each register class contains sets of
413 registers that have the same properties (for example, they are all 32-bit
414 integer registers). Each SSA virtual register created by the instruction
415 selector has an associated register class. When the register allocator runs,
416 it replaces virtual registers with a physical register in the set.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]417
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]418<p>The target-specific implementations of these classes is auto-generated from
419 a <a href="TableGenFundamentals.html">TableGen</a> description of the
420 register file.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]421
422</div>
423
424<!-- ======================================================================= -->
425<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]426 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]427</div>
428
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]429<div class="doc_text">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]430
431<p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
432 instructions supported by the target. It is essentially an array of
433 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
434 instruction the target supports. Descriptors define things like the mnemonic
435 for the opcode, the number of operands, the list of implicit register uses
436 and defs, whether the instruction has certain target-independent properties
437 (accesses memory, is commutable, etc), and holds any target-specific
438 flags.</p>
439
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]440</div>
441
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]442<!-- ======================================================================= -->
443<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]444 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]445</div>
446
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]447<div class="doc_text">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]448
449<p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
450 stack frame layout of the target. It holds the direction of stack growth, the
451 known stack alignment on entry to each function, and the offset to the local
452 area. The offset to the local area is the offset from the stack pointer on
453 function entry to the first location where function data (local variables,
454 spill locations) can be stored.</p>
455
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]456</div>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]457
458<!-- ======================================================================= -->
459<div class="doc_subsection">
460 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
461</div>
462
463<div class="doc_text">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]464
465<p>The <tt>TargetSubtarget</tt> class is used to provide information about the
466 specific chip set being targeted. A sub-target informs code generation of
467 which instructions are supported, instruction latencies and instruction
468 execution itinerary; i.e., which processing units are used, in what order,
469 and for how long.</p>
470
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]471</div>
472
473
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]474<!-- ======================================================================= -->
475<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]476 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]477</div>
478
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]479<div class="doc_text">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]480
481<p>The <tt>TargetJITInfo</tt> class exposes an abstract interface used by the
482 Just-In-Time code generator to perform target-specific activities, such as
483 emitting stubs. If a <tt>TargetMachine</tt> supports JIT code generation, it
484 should provide one of these objects through the <tt>getJITInfo</tt>
485 method.</p>
486
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]487</div>
488
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]489<!-- *********************************************************************** -->
490<div class="doc_section">
491 <a name="codegendesc">Machine code description classes</a>
492</div>
493<!-- *********************************************************************** -->
494
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]495<div class="doc_text">
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]496
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]497<p>At the high-level, LLVM code is translated to a machine specific
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]498 representation formed out of
499 <a href="#machinefunction"><tt>MachineFunction</tt></a>,
500 <a href="#machinebasicblock"><tt>MachineBasicBlock</tt></a>,
501 and <a href="#machineinstr"><tt>MachineInstr</tt></a> instances (defined
502 in <tt>include/llvm/CodeGen</tt>). This representation is completely target
503 agnostic, representing instructions in their most abstract form: an opcode
504 and a series of operands. This representation is designed to support both an
505 SSA representation for machine code, as well as a register allocated, non-SSA
506 form.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]507
508</div>
509
510<!-- ======================================================================= -->
511<div class="doc_subsection">
512 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
513</div>
514
515<div class="doc_text">
516
517<p>Target machine instructions are represented as instances of the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]518 <tt>MachineInstr</tt> class. This class is an extremely abstract way of
519 representing machine instructions. In particular, it only keeps track of an
520 opcode number and a set of operands.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]521
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]522<p>The opcode number is a simple unsigned integer that only has meaning to a
523 specific backend. All of the instructions for a target should be defined in
524 the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values are
525 auto-generated from this description. The <tt>MachineInstr</tt> class does
526 not have any information about how to interpret the instruction (i.e., what
527 the semantics of the instruction are); for that you must refer to the
528 <tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]529
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]530<p>The operands of a machine instruction can be of several different types: a
531 register reference, a constant integer, a basic block reference, etc. In
532 addition, a machine operand should be marked as a def or a use of the value
533 (though only registers are allowed to be defs).</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]534
535<p>By convention, the LLVM code generator orders instruction operands so that
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]536 all register definitions come before the register uses, even on architectures
537 that are normally printed in other orders. For example, the SPARC add
538 instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
539 and stores the result into the "%i3" register. In the LLVM code generator,
540 the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the
541 destination first.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]542
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]543<p>Keeping destination (definition) operands at the beginning of the operand
544 list has several advantages. In particular, the debugging printer will print
545 the instruction like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]546
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]547<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]548<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]549%r3 = add %i1, %i2
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]550</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]551</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]552
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]553<p>Also if the first operand is a def, it is easier to <a href="#buildmi">create
554 instructions</a> whose only def is the first operand.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]555
556</div>
557
558<!-- _______________________________________________________________________ -->
559<div class="doc_subsubsection">
560 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
561</div>
562
563<div class="doc_text">
564
565<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]566 located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
567 <tt>BuildMI</tt> functions make it easy to build arbitrary machine
568 instructions. Usage of the <tt>BuildMI</tt> functions look like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]569
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]570<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]571<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]572// Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
573// instruction. The '1' specifies how many operands will be added.
574MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]575
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]576// Create the same instr, but insert it at the end of a basic block.
577MachineBasicBlock &amp;MBB = ...
578BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]579
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]580// Create the same instr, but insert it before a specified iterator point.
581MachineBasicBlock::iterator MBBI = ...
582BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]583
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]584// Create a 'cmp Reg, 0' instruction, no destination reg.
585MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
586// Create an 'sahf' instruction which takes no operands and stores nothing.
587MI = BuildMI(X86::SAHF, 0);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]588
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]589// Create a self looping branch instruction.
590BuildMI(MBB, X86::JNE, 1).addMBB(&amp;MBB);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]591</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]592</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]593
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]594<p>The key thing to remember with the <tt>BuildMI</tt> functions is that you
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]595 have to specify the number of operands that the machine instruction will
596 take. This allows for efficient memory allocation. You also need to specify
597 if operands default to be uses of values, not definitions. If you need to
598 add a definition operand (other than the optional destination register), you
599 must explicitly mark it as such:</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]600
601<div class="doc_code">
602<pre>
Bill Wendling587daed2009-05-13 21:33:08 +0000[diff] [blame]603MI.addReg(Reg, RegState::Define);
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]604</pre>
605</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]606
607</div>
608
609<!-- _______________________________________________________________________ -->
610<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]611 <a name="fixedregs">Fixed (preassigned) registers</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]612</div>
613
614<div class="doc_text">
615
616<p>One important issue that the code generator needs to be aware of is the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]617 presence of fixed registers. In particular, there are often places in the
618 instruction stream where the register allocator <em>must</em> arrange for a
619 particular value to be in a particular register. This can occur due to
620 limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
621 with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like
622 calling conventions. In any case, the instruction selector should emit code
623 that copies a virtual register into or out of a physical register when
624 needed.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]625
626<p>For example, consider this simple LLVM example:</p>
627
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]628<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]629<pre>
Matthijs Kooijman61399af2008-06-04 15:46:35 +0000[diff] [blame]630define i32 @test(i32 %X, i32 %Y) {
631 %Z = udiv i32 %X, %Y
632 ret i32 %Z
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]633}
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]634</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]635</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]636
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]637<p>The X86 instruction selector produces this machine code for the <tt>div</tt>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]638 and <tt>ret</tt> (use "<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to
639 get this):</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]640
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]641<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]642<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]643;; Start of div
644%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
645%reg1027 = sar %reg1024, 31
646%EDX = mov %reg1027 ;; Sign extend X into EDX
647idiv %reg1025 ;; Divide by Y (in reg1025)
648%reg1026 = mov %EAX ;; Read the result (Z) out of EAX
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]649
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]650;; Start of ret
651%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
652ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]653</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]654</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]655
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]656<p>By the end of code generation, the register allocator has coalesced the
657 registers and deleted the resultant identity moves producing the following
658 code:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]659
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]660<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]661<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]662;; X is in EAX, Y is in ECX
663mov %EAX, %EDX
664sar %EDX, 31
665idiv %ECX
666ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]667</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]668</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]669
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]670<p>This approach is extremely general (if it can handle the X86 architecture, it
671 can handle anything!) and allows all of the target specific knowledge about
672 the instruction stream to be isolated in the instruction selector. Note that
673 physical registers should have a short lifetime for good code generation, and
674 all physical registers are assumed dead on entry to and exit from basic
675 blocks (before register allocation). Thus, if you need a value to be live
676 across basic block boundaries, it <em>must</em> live in a virtual
677 register.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]678
679</div>
680
681<!-- _______________________________________________________________________ -->
682<div class="doc_subsubsection">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]683 <a name="ssa">Machine code in SSA form</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]684</div>
685
686<div class="doc_text">
687
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]688<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and are
689 maintained in SSA-form until register allocation happens. For the most part,
690 this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
691 become machine code PHI nodes, and virtual registers are only allowed to have
692 a single definition.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]693
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]694<p>After register allocation, machine code is no longer in SSA-form because
695 there are no virtual registers left in the code.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]696
697</div>
698
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]699<!-- ======================================================================= -->
700<div class="doc_subsection">
701 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
702</div>
703
704<div class="doc_text">
705
706<p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]707 (<tt><a href="#machineinstr">MachineInstr</a></tt> instances). It roughly
708 corresponds to the LLVM code input to the instruction selector, but there can
709 be a one-to-many mapping (i.e. one LLVM basic block can map to multiple
710 machine basic blocks). The <tt>MachineBasicBlock</tt> class has a
711 "<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
712 comes from.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]713
714</div>
715
716<!-- ======================================================================= -->
717<div class="doc_subsection">
718 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
719</div>
720
721<div class="doc_text">
722
723<p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]724 (<tt><a href="#machinebasicblock">MachineBasicBlock</a></tt> instances). It
725 corresponds one-to-one with the LLVM function input to the instruction
726 selector. In addition to a list of basic blocks,
727 the <tt>MachineFunction</tt> contains a a <tt>MachineConstantPool</tt>,
728 a <tt>MachineFrameInfo</tt>, a <tt>MachineFunctionInfo</tt>, and a
729 <tt>MachineRegisterInfo</tt>. See
730 <tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]731
732</div>
733
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]734<!-- *********************************************************************** -->
735<div class="doc_section">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]736 <a name="codegenalgs">Target-independent code generation algorithms</a>
737</div>
738<!-- *********************************************************************** -->
739
740<div class="doc_text">
741
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]742<p>This section documents the phases described in the
743 <a href="#high-level-design">high-level design of the code generator</a>.
744 It explains how they work and some of the rationale behind their design.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]745
746</div>
747
748<!-- ======================================================================= -->
749<div class="doc_subsection">
750 <a name="instselect">Instruction Selection</a>
751</div>
752
753<div class="doc_text">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]754
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]755<p>Instruction Selection is the process of translating LLVM code presented to
756 the code generator into target-specific machine instructions. There are
757 several well-known ways to do this in the literature. LLVM uses a
758 SelectionDAG based instruction selector.</p>
759
760<p>Portions of the DAG instruction selector are generated from the target
761 description (<tt>*.td</tt>) files. Our goal is for the entire instruction
762 selector to be generated from these <tt>.td</tt> files, though currently
763 there are still things that require custom C++ code.</p>
764
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]765</div>
766
767<!-- _______________________________________________________________________ -->
768<div class="doc_subsubsection">
769 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
770</div>
771
772<div class="doc_text">
773
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]774<p>The SelectionDAG provides an abstraction for code representation in a way
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]775 that is amenable to instruction selection using automatic techniques
776 (e.g. dynamic-programming based optimal pattern matching selectors). It is
777 also well-suited to other phases of code generation; in particular,
778 instruction scheduling (SelectionDAG's are very close to scheduling DAGs
779 post-selection). Additionally, the SelectionDAG provides a host
780 representation where a large variety of very-low-level (but
781 target-independent) <a href="#selectiondag_optimize">optimizations</a> may be
782 performed; ones which require extensive information about the instructions
783 efficiently supported by the target.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]784
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]785<p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]786 <tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
787 operation code (Opcode) that indicates what operation the node performs and
788 the operands to the operation. The various operation node types are
789 described at the top of the <tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt>
790 file.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]791
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]792<p>Although most operations define a single value, each node in the graph may
793 define multiple values. For example, a combined div/rem operation will
794 define both the dividend and the remainder. Many other situations require
795 multiple values as well. Each node also has some number of operands, which
796 are edges to the node defining the used value. Because nodes may define
797 multiple values, edges are represented by instances of the <tt>SDValue</tt>
798 class, which is a <tt>&lt;SDNode, unsigned&gt;</tt> pair, indicating the node
799 and result value being used, respectively. Each value produced by
800 an <tt>SDNode</tt> has an associated <tt>MVT</tt> (Machine Value Type)
801 indicating what the type of the value is.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]802
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]803<p>SelectionDAGs contain two different kinds of values: those that represent
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]804 data flow and those that represent control flow dependencies. Data values
805 are simple edges with an integer or floating point value type. Control edges
806 are represented as "chain" edges which are of type <tt>MVT::Other</tt>.
807 These edges provide an ordering between nodes that have side effects (such as
808 loads, stores, calls, returns, etc). All nodes that have side effects should
809 take a token chain as input and produce a new one as output. By convention,
810 token chain inputs are always operand #0, and chain results are always the
811 last value produced by an operation.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]812
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]813<p>A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]814 always a marker node with an Opcode of <tt>ISD::EntryToken</tt>. The Root
815 node is the final side-effecting node in the token chain. For example, in a
816 single basic block function it would be the return node.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]817
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]818<p>One important concept for SelectionDAGs is the notion of a "legal" vs.
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]819 "illegal" DAG. A legal DAG for a target is one that only uses supported
820 operations and supported types. On a 32-bit PowerPC, for example, a DAG with
821 a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that
822 uses a SREM or UREM operation. The
823 <a href="#selectinodag_legalize_types">legalize types</a> and
824 <a href="#selectiondag_legalize">legalize operations</a> phases are
825 responsible for turning an illegal DAG into a legal DAG.</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]826
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]827</div>
828
829<!-- _______________________________________________________________________ -->
830<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]831 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]832</div>
833
834<div class="doc_text">
835
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]836<p>SelectionDAG-based instruction selection consists of the following steps:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]837
838<ol>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]839 <li><a href="#selectiondag_build">Build initial DAG</a> &mdash; This stage
840 performs a simple translation from the input LLVM code to an illegal
841 SelectionDAG.</li>
842
843 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> &mdash; This
844 stage performs simple optimizations on the SelectionDAG to simplify it,
845 and recognize meta instructions (like rotates
846 and <tt>div</tt>/<tt>rem</tt> pairs) for targets that support these meta
847 operations. This makes the resultant code more efficient and
848 the <a href="#selectiondag_select">select instructions from DAG</a> phase
849 (below) simpler.</li>
850
851 <li><a href="#selectiondag_legalize_types">Legalize SelectionDAG Types</a>
852 &mdash; This stage transforms SelectionDAG nodes to eliminate any types
853 that are unsupported on the target.</li>
854
855 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> &mdash; The
856 SelectionDAG optimizer is run to clean up redundancies exposed by type
857 legalization.</li>
858
859 <li><a href="#selectiondag_legalize">Legalize SelectionDAG Types</a> &mdash;
860 This stage transforms SelectionDAG nodes to eliminate any types that are
861 unsupported on the target.</li>
862
863 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> &mdash; The
864 SelectionDAG optimizer is run to eliminate inefficiencies introduced by
865 operation legalization.</li>
866
867 <li><a href="#selectiondag_select">Select instructions from DAG</a> &mdash;
868 Finally, the target instruction selector matches the DAG operations to
869 target instructions. This process translates the target-independent input
870 DAG into another DAG of target instructions.</li>
871
872 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
873 &mdash; The last phase assigns a linear order to the instructions in the
874 target-instruction DAG and emits them into the MachineFunction being
875 compiled. This step uses traditional prepass scheduling techniques.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]876</ol>
877
878<p>After all of these steps are complete, the SelectionDAG is destroyed and the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]879 rest of the code generation passes are run.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]880
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]881<p>One great way to visualize what is going on here is to take advantage of a
882 few LLC command line options. The following options pop up a window
883 displaying the SelectionDAG at specific times (if you only get errors printed
884 to the console while using this, you probably
885 <a href="ProgrammersManual.html#ViewGraph">need to configure your system</a>
886 to add support for it).</p>
Dan Gohman8c9c55f2008-09-10 22:23:41 +0000[diff] [blame]887
888<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]889 <li><tt>-view-dag-combine1-dags</tt> displays the DAG after being built,
890 before the first optimization pass.</li>
891
892 <li><tt>-view-legalize-dags</tt> displays the DAG before Legalization.</li>
893
894 <li><tt>-view-dag-combine2-dags</tt> displays the DAG before the second
895 optimization pass.</li>
896
897 <li><tt>-view-isel-dags</tt> displays the DAG before the Select phase.</li>
898
899 <li><tt>-view-sched-dags</tt> displays the DAG before Scheduling.</li>
Dan Gohman8c9c55f2008-09-10 22:23:41 +0000[diff] [blame]900</ul>
901
902<p>The <tt>-view-sunit-dags</tt> displays the Scheduler's dependency graph.
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]903 This graph is based on the final SelectionDAG, with nodes that must be
904 scheduled together bundled into a single scheduling-unit node, and with
905 immediate operands and other nodes that aren't relevant for scheduling
906 omitted.</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]907
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]908</div>
909
910<!-- _______________________________________________________________________ -->
911<div class="doc_subsubsection">
912 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
913</div>
914
915<div class="doc_text">
916
Bill Wendling16448772006-08-28 03:04:05 +0000[diff] [blame]917<p>The initial SelectionDAG is na&iuml;vely peephole expanded from the LLVM
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]918 input by the <tt>SelectionDAGLowering</tt> class in the
919 <tt>lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp</tt> file. The intent of
920 this pass is to expose as much low-level, target-specific details to the
921 SelectionDAG as possible. This pass is mostly hard-coded (e.g. an
922 LLVM <tt>add</tt> turns into an <tt>SDNode add</tt> while a
923 <tt>getelementptr</tt> is expanded into the obvious arithmetic). This pass
924 requires target-specific hooks to lower calls, returns, varargs, etc. For
925 these features, the <tt><a href="#targetlowering">TargetLowering</a></tt>
926 interface is used.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]927
928</div>
929
930<!-- _______________________________________________________________________ -->
931<div class="doc_subsubsection">
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]932 <a name="selectiondag_legalize_types">SelectionDAG LegalizeTypes Phase</a>
933</div>
934
935<div class="doc_text">
936
937<p>The Legalize phase is in charge of converting a DAG to only use the types
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]938 that are natively supported by the target.</p>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]939
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]940<p>There are two main ways of converting values of unsupported scalar types to
941 values of supported types: converting small types to larger types
942 ("promoting"), and breaking up large integer types into smaller ones
943 ("expanding"). For example, a target might require that all f32 values are
944 promoted to f64 and that all i1/i8/i16 values are promoted to i32. The same
945 target might require that all i64 values be expanded into pairs of i32
946 values. These changes can insert sign and zero extensions as needed to make
947 sure that the final code has the same behavior as the input.</p>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]948
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]949<p>There are two main ways of converting values of unsupported vector types to
950 value of supported types: splitting vector types, multiple times if
951 necessary, until a legal type is found, and extending vector types by adding
952 elements to the end to round them out to legal types ("widening"). If a
953 vector gets split all the way down to single-element parts with no supported
954 vector type being found, the elements are converted to scalars
955 ("scalarizing").</p>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]956
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]957<p>A target implementation tells the legalizer which types are supported (and
958 which register class to use for them) by calling the
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]959 <tt>addRegisterClass</tt> method in its TargetLowering constructor.</p>
960
961</div>
962
963<!-- _______________________________________________________________________ -->
964<div class="doc_subsubsection">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]965 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
966</div>
967
968<div class="doc_text">
969
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]970<p>The Legalize phase is in charge of converting a DAG to only use the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]971 operations that are natively supported by the target.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]972
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]973<p>Targets often have weird constraints, such as not supporting every operation
974 on every supported datatype (e.g. X86 does not support byte conditional moves
975 and PowerPC does not support sign-extending loads from a 16-bit memory
976 location). Legalize takes care of this by open-coding another sequence of
977 operations to emulate the operation ("expansion"), by promoting one type to a
978 larger type that supports the operation ("promotion"), or by using a
979 target-specific hook to implement the legalization ("custom").</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]980
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]981<p>A target implementation tells the legalizer which operations are not
982 supported (and which of the above three actions to take) by calling the
983 <tt>setOperationAction</tt> method in its <tt>TargetLowering</tt>
984 constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]985
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]986<p>Prior to the existence of the Legalize passes, we required that every target
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]987 <a href="#selectiondag_optimize">selector</a> supported and handled every
988 operator and type even if they are not natively supported. The introduction
989 of the Legalize phases allows all of the canonicalization patterns to be
990 shared across targets, and makes it very easy to optimize the canonicalized
991 code because it is still in the form of a DAG.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]992
993</div>
994
995<!-- _______________________________________________________________________ -->
996<div class="doc_subsubsection">
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]997 <a name="selectiondag_optimize">SelectionDAG Optimization Phase: the DAG
998 Combiner</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]999</div>
1000
1001<div class="doc_text">
1002
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1003<p>The SelectionDAG optimization phase is run multiple times for code
1004 generation, immediately after the DAG is built and once after each
1005 legalization. The first run of the pass allows the initial code to be
1006 cleaned up (e.g. performing optimizations that depend on knowing that the
1007 operators have restricted type inputs). Subsequent runs of the pass clean up
1008 the messy code generated by the Legalize passes, which allows Legalize to be
1009 very simple (it can focus on making code legal instead of focusing on
1010 generating <em>good</em> and legal code).</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1011
1012<p>One important class of optimizations performed is optimizing inserted sign
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1013 and zero extension instructions. We currently use ad-hoc techniques, but
1014 could move to more rigorous techniques in the future. Here are some good
1015 papers on the subject:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1016
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1017<p>"<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
1018 integer arithmetic</a>"<br>
1019 Kevin Redwine and Norman Ramsey<br>
1020 International Conference on Compiler Construction (CC) 2004</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1021
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1022<p>"<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
1023 sign extension elimination</a>"<br>
1024 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
1025 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
1026 and Implementation.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1027
1028</div>
1029
1030<!-- _______________________________________________________________________ -->
1031<div class="doc_subsubsection">
1032 <a name="selectiondag_select">SelectionDAG Select Phase</a>
1033</div>
1034
1035<div class="doc_text">
1036
1037<p>The Select phase is the bulk of the target-specific code for instruction
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1038 selection. This phase takes a legal SelectionDAG as input, pattern matches
1039 the instructions supported by the target to this DAG, and produces a new DAG
1040 of target code. For example, consider the following LLVM fragment:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1041
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1042<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1043<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1044%t1 = add float %W, %X
1045%t2 = mul float %t1, %Y
1046%t3 = add float %t2, %Z
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1047</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1048</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1049
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1050<p>This LLVM code corresponds to a SelectionDAG that looks basically like
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1051 this:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1052
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1053<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1054<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1055(fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1056</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1057</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1058
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1059<p>If a target supports floating point multiply-and-add (FMA) operations, one of
1060 the adds can be merged with the multiply. On the PowerPC, for example, the
1061 output of the instruction selector might look like this DAG:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1062
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1063<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1064<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1065(FMADDS (FADDS W, X), Y, Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1066</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1067</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1068
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1069<p>The <tt>FMADDS</tt> instruction is a ternary instruction that multiplies its
1070first two operands and adds the third (as single-precision floating-point
1071numbers). The <tt>FADDS</tt> instruction is a simple binary single-precision
1072add instruction. To perform this pattern match, the PowerPC backend includes
1073the following instruction definitions:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1074
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1075<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1076<pre>
1077def FMADDS : AForm_1&lt;59, 29,
1078 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1079 "fmadds $FRT, $FRA, $FRC, $FRB",
1080 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1081 F4RC:$FRB))</b>]&gt;;
1082def FADDS : AForm_2&lt;59, 21,
1083 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1084 "fadds $FRT, $FRA, $FRB",
1085 [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]&gt;;
1086</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1087</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1088
1089<p>The portion of the instruction definition in bold indicates the pattern used
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1090 to match the instruction. The DAG operators
1091 (like <tt>fmul</tt>/<tt>fadd</tt>) are defined in
1092 the <tt>lib/Target/TargetSelectionDAG.td</tt> file. "<tt>F4RC</tt>" is the
1093 register class of the input and result values.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1094
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1095<p>The TableGen DAG instruction selector generator reads the instruction
1096 patterns in the <tt>.td</tt> file and automatically builds parts of the
1097 pattern matching code for your target. It has the following strengths:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1098
1099<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1100 <li>At compiler-compiler time, it analyzes your instruction patterns and tells
1101 you if your patterns make sense or not.</li>
1102
1103 <li>It can handle arbitrary constraints on operands for the pattern match. In
1104 particular, it is straight-forward to say things like "match any immediate
1105 that is a 13-bit sign-extended value". For examples, see the
1106 <tt>immSExt16</tt> and related <tt>tblgen</tt> classes in the PowerPC
1107 backend.</li>
1108
1109 <li>It knows several important identities for the patterns defined. For
1110 example, it knows that addition is commutative, so it allows the
1111 <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
1112 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1113 to specially handle this case.</li>
1114
1115 <li>It has a full-featured type-inferencing system. In particular, you should
1116 rarely have to explicitly tell the system what type parts of your patterns
1117 are. In the <tt>FMADDS</tt> case above, we didn't have to tell
1118 <tt>tblgen</tt> that all of the nodes in the pattern are of type 'f32'.
1119 It was able to infer and propagate this knowledge from the fact that
1120 <tt>F4RC</tt> has type 'f32'.</li>
1121
1122 <li>Targets can define their own (and rely on built-in) "pattern fragments".
1123 Pattern fragments are chunks of reusable patterns that get inlined into
1124 your patterns during compiler-compiler time. For example, the integer
1125 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment
1126 that expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not
1127 have a native '<tt>not</tt>' operation. Targets can define their own
1128 short-hand fragments as they see fit. See the definition of
1129 '<tt>not</tt>' and '<tt>ineg</tt>' for examples.</li>
1130
1131 <li>In addition to instructions, targets can specify arbitrary patterns that
1132 map to one or more instructions using the 'Pat' class. For example, the
1133 PowerPC has no way to load an arbitrary integer immediate into a register
1134 in one instruction. To tell tblgen how to do this, it defines:
1135 <br>
1136 <br>
1137<div class="doc_code">
1138<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1139// Arbitrary immediate support. Implement in terms of LIS/ORI.
1140def : Pat&lt;(i32 imm:$imm),
1141 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))&gt;;
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1142</pre>
1143</div>
1144 <br>
1145 If none of the single-instruction patterns for loading an immediate into a
1146 register match, this will be used. This rule says "match an arbitrary i32
1147 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and
1148 an <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to
1149 the left 16 bits') instruction". To make this work, the
1150 <tt>LO16</tt>/<tt>HI16</tt> node transformations are used to manipulate
1151 the input immediate (in this case, take the high or low 16-bits of the
1152 immediate).</li>
1153
1154 <li>While the system does automate a lot, it still allows you to write custom
1155 C++ code to match special cases if there is something that is hard to
1156 express.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1157</ul>
1158
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1159<p>While it has many strengths, the system currently has some limitations,
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1160 primarily because it is a work in progress and is not yet finished:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1161
1162<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1163 <li>Overall, there is no way to define or match SelectionDAG nodes that define
Dan Gohmane370c802009-04-22 15:55:31 +0000[diff] [blame]1164 multiple values (e.g. <tt>SMUL_LOHI</tt>, <tt>LOAD</tt>, <tt>CALL</tt>,
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1165 etc). This is the biggest reason that you currently still <em>have
1166 to</em> write custom C++ code for your instruction selector.</li>
1167
1168 <li>There is no great way to support matching complex addressing modes yet.
1169 In the future, we will extend pattern fragments to allow them to define
1170 multiple values (e.g. the four operands of the <a href="#x86_memory">X86
1171 addressing mode</a>, which are currently matched with custom C++ code).
1172 In addition, we'll extend fragments so that a fragment can match multiple
1173 different patterns.</li>
1174
1175 <li>We don't automatically infer flags like isStore/isLoad yet.</li>
1176
1177 <li>We don't automatically generate the set of supported registers and
1178 operations for the <a href="#selectiondag_legalize">Legalizer</a>
1179 yet.</li>
1180
1181 <li>We don't have a way of tying in custom legalized nodes yet.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1182</ul>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1183
1184<p>Despite these limitations, the instruction selector generator is still quite
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1185 useful for most of the binary and logical operations in typical instruction
1186 sets. If you run into any problems or can't figure out how to do something,
1187 please let Chris know!</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1188
1189</div>
1190
1191<!-- _______________________________________________________________________ -->
1192<div class="doc_subsubsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1193 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1194</div>
1195
1196<div class="doc_text">
1197
1198<p>The scheduling phase takes the DAG of target instructions from the selection
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1199 phase and assigns an order. The scheduler can pick an order depending on
1200 various constraints of the machines (i.e. order for minimal register pressure
1201 or try to cover instruction latencies). Once an order is established, the
1202 DAG is converted to a list
1203 of <tt><a href="#machineinstr">MachineInstr</a></tt>s and the SelectionDAG is
1204 destroyed.</p>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1205
Jeff Cohen0b81cda2005-10-24 16:54:55 +0000[diff] [blame]1206<p>Note that this phase is logically separate from the instruction selection
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1207 phase, but is tied to it closely in the code because it operates on
1208 SelectionDAGs.</p>
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]1209
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1210</div>
1211
1212<!-- _______________________________________________________________________ -->
1213<div class="doc_subsubsection">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1214 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
1215</div>
1216
1217<div class="doc_text">
1218
1219<ol>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1220 <li>Optional function-at-a-time selection.</li>
1221
1222 <li>Auto-generate entire selector from <tt>.td</tt> file.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1223</ol>
1224
1225</div>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1226
1227<!-- ======================================================================= -->
1228<div class="doc_subsection">
1229 <a name="ssamco">SSA-based Machine Code Optimizations</a>
1230</div>
1231<div class="doc_text"><p>To Be Written</p></div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1232
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1233<!-- ======================================================================= -->
1234<div class="doc_subsection">
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1235 <a name="liveintervals">Live Intervals</a>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1236</div>
1237
1238<div class="doc_text">
1239
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1240<p>Live Intervals are the ranges (intervals) where a variable is <i>live</i>.
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1241 They are used by some <a href="#regalloc">register allocator</a> passes to
1242 determine if two or more virtual registers which require the same physical
1243 register are live at the same point in the program (i.e., they conflict).
1244 When this situation occurs, one virtual register must be <i>spilled</i>.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1245
1246</div>
1247
1248<!-- _______________________________________________________________________ -->
1249<div class="doc_subsubsection">
1250 <a name="livevariable_analysis">Live Variable Analysis</a>
1251</div>
1252
1253<div class="doc_text">
1254
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1255<p>The first step in determining the live intervals of variables is to calculate
1256 the set of registers that are immediately dead after the instruction (i.e.,
1257 the instruction calculates the value, but it is never used) and the set of
1258 registers that are used by the instruction, but are never used after the
1259 instruction (i.e., they are killed). Live variable information is computed
1260 for each <i>virtual</i> register and <i>register allocatable</i> physical
1261 register in the function. This is done in a very efficient manner because it
1262 uses SSA to sparsely compute lifetime information for virtual registers
1263 (which are in SSA form) and only has to track physical registers within a
1264 block. Before register allocation, LLVM can assume that physical registers
1265 are only live within a single basic block. This allows it to do a single,
1266 local analysis to resolve physical register lifetimes within each basic
1267 block. If a physical register is not register allocatable (e.g., a stack
1268 pointer or condition codes), it is not tracked.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1269
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1270<p>Physical registers may be live in to or out of a function. Live in values are
1271 typically arguments in registers. Live out values are typically return values
1272 in registers. Live in values are marked as such, and are given a dummy
1273 "defining" instruction during live intervals analysis. If the last basic
1274 block of a function is a <tt>return</tt>, then it's marked as using all live
1275 out values in the function.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1276
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1277<p><tt>PHI</tt> nodes need to be handled specially, because the calculation of
1278 the live variable information from a depth first traversal of the CFG of the
1279 function won't guarantee that a virtual register used by the <tt>PHI</tt>
1280 node is defined before it's used. When a <tt>PHI</tt> node is encountered,
1281 only the definition is handled, because the uses will be handled in other
1282 basic blocks.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1283
1284<p>For each <tt>PHI</tt> node of the current basic block, we simulate an
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1285 assignment at the end of the current basic block and traverse the successor
1286 basic blocks. If a successor basic block has a <tt>PHI</tt> node and one of
1287 the <tt>PHI</tt> node's operands is coming from the current basic block, then
1288 the variable is marked as <i>alive</i> within the current basic block and all
1289 of its predecessor basic blocks, until the basic block with the defining
1290 instruction is encountered.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1291
1292</div>
1293
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1294<!-- _______________________________________________________________________ -->
1295<div class="doc_subsubsection">
1296 <a name="liveintervals_analysis">Live Intervals Analysis</a>
1297</div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1298
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1299<div class="doc_text">
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1300
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1301<p>We now have the information available to perform the live intervals analysis
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1302 and build the live intervals themselves. We start off by numbering the basic
1303 blocks and machine instructions. We then handle the "live-in" values. These
1304 are in physical registers, so the physical register is assumed to be killed
1305 by the end of the basic block. Live intervals for virtual registers are
1306 computed for some ordering of the machine instructions <tt>[1, N]</tt>. A
1307 live interval is an interval <tt>[i, j)</tt>, where <tt>1 &lt;= i &lt;= j
1308 &lt; N</tt>, for which a variable is live.</p>
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1309
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1310<p><i><b>More to come...</b></i></p>
1311
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1312</div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1313
1314<!-- ======================================================================= -->
1315<div class="doc_subsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1316 <a name="regalloc">Register Allocation</a>
1317</div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1318
1319<div class="doc_text">
1320
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1321<p>The <i>Register Allocation problem</i> consists in mapping a program
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1322 <i>P<sub>v</sub></i>, that can use an unbounded number of virtual registers,
1323 to a program <i>P<sub>p</sub></i> that contains a finite (possibly small)
1324 number of physical registers. Each target architecture has a different number
1325 of physical registers. If the number of physical registers is not enough to
1326 accommodate all the virtual registers, some of them will have to be mapped
1327 into memory. These virtuals are called <i>spilled virtuals</i>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1328
1329</div>
1330
1331<!-- _______________________________________________________________________ -->
1332
1333<div class="doc_subsubsection">
1334 <a name="regAlloc_represent">How registers are represented in LLVM</a>
1335</div>
1336
1337<div class="doc_text">
1338
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1339<p>In LLVM, physical registers are denoted by integer numbers that normally
1340 range from 1 to 1023. To see how this numbering is defined for a particular
1341 architecture, you can read the <tt>GenRegisterNames.inc</tt> file for that
1342 architecture. For instance, by
1343 inspecting <tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the
1344 32-bit register <tt>EAX</tt> is denoted by 15, and the MMX register
1345 <tt>MM0</tt> is mapped to 48.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1346
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1347<p>Some architectures contain registers that share the same physical location. A
1348 notable example is the X86 platform. For instance, in the X86 architecture,
1349 the registers <tt>EAX</tt>, <tt>AX</tt> and <tt>AL</tt> share the first eight
1350 bits. These physical registers are marked as <i>aliased</i> in LLVM. Given a
1351 particular architecture, you can check which registers are aliased by
1352 inspecting its <tt>RegisterInfo.td</tt> file. Moreover, the method
1353 <tt>TargetRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
1354 all the physical registers aliased to the register <tt>p_reg</tt>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1355
1356<p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>.
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1357 Elements in the same register class are functionally equivalent, and can be
1358 interchangeably used. Each virtual register can only be mapped to physical
1359 registers of a particular class. For instance, in the X86 architecture, some
1360 virtuals can only be allocated to 8 bit registers. A register class is
1361 described by <tt>TargetRegisterClass</tt> objects. To discover if a virtual
1362 register is compatible with a given physical, this code can be used:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1363
1364<div class="doc_code">
1365<pre>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1366bool RegMapping_Fer::compatible_class(MachineFunction &amp;mf,
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1367 unsigned v_reg,
1368 unsigned p_reg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1369 assert(TargetRegisterInfo::isPhysicalRegister(p_reg) &amp;&amp;
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1370 "Target register must be physical");
Chris Lattner534bcfb2007-12-31 04:16:08 +0000[diff] [blame]1371 const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
1372 return trc-&gt;contains(p_reg);
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1373}
1374</pre>
1375</div>
1376
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1377<p>Sometimes, mostly for debugging purposes, it is useful to change the number
1378 of physical registers available in the target architecture. This must be done
1379 statically, inside the <tt>TargetRegsterInfo.td</tt> file. Just <tt>grep</tt>
1380 for <tt>RegisterClass</tt>, the last parameter of which is a list of
1381 registers. Just commenting some out is one simple way to avoid them being
1382 used. A more polite way is to explicitly exclude some registers from
Dan Gohmand2cb3d22009-07-24 00:30:09 +0000[diff] [blame]1383 the <i>allocation order</i>. See the definition of the <tt>GR8</tt> register
1384 class in <tt>lib/Target/X86/X86RegisterInfo.td</tt> for an example of this.
1385 </p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1386
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1387<p>Virtual registers are also denoted by integer numbers. Contrary to physical
1388 registers, different virtual registers never share the same number. The
1389 smallest virtual register is normally assigned the number 1024. This may
1390 change, so, in order to know which is the first virtual register, you should
1391 access <tt>TargetRegisterInfo::FirstVirtualRegister</tt>. Any register whose
1392 number is greater than or equal
1393 to <tt>TargetRegisterInfo::FirstVirtualRegister</tt> is considered a virtual
1394 register. Whereas physical registers are statically defined in
1395 a <tt>TargetRegisterInfo.td</tt> file and cannot be created by the
1396 application developer, that is not the case with virtual registers. In order
1397 to create new virtual registers, use the
1398 method <tt>MachineRegisterInfo::createVirtualRegister()</tt>. This method
1399 will return a virtual register with the highest code.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1400
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1401<p>Before register allocation, the operands of an instruction are mostly virtual
1402 registers, although physical registers may also be used. In order to check if
1403 a given machine operand is a register, use the boolean
1404 function <tt>MachineOperand::isRegister()</tt>. To obtain the integer code of
1405 a register, use <tt>MachineOperand::getReg()</tt>. An instruction may define
1406 or use a register. For instance, <tt>ADD reg:1026 := reg:1025 reg:1024</tt>
1407 defines the registers 1024, and uses registers 1025 and 1026. Given a
1408 register operand, the method <tt>MachineOperand::isUse()</tt> informs if that
1409 register is being used by the instruction. The
1410 method <tt>MachineOperand::isDef()</tt> informs if that registers is being
1411 defined.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1412
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1413<p>We will call physical registers present in the LLVM bitcode before register
1414 allocation <i>pre-colored registers</i>. Pre-colored registers are used in
1415 many different situations, for instance, to pass parameters of functions
1416 calls, and to store results of particular instructions. There are two types
1417 of pre-colored registers: the ones <i>implicitly</i> defined, and
1418 those <i>explicitly</i> defined. Explicitly defined registers are normal
1419 operands, and can be accessed
1420 with <tt>MachineInstr::getOperand(int)::getReg()</tt>. In order to check
1421 which registers are implicitly defined by an instruction, use
1422 the <tt>TargetInstrInfo::get(opcode)::ImplicitDefs</tt>,
1423 where <tt>opcode</tt> is the opcode of the target instruction. One important
1424 difference between explicit and implicit physical registers is that the
1425 latter are defined statically for each instruction, whereas the former may
1426 vary depending on the program being compiled. For example, an instruction
1427 that represents a function call will always implicitly define or use the same
1428 set of physical registers. To read the registers implicitly used by an
1429 instruction,
1430 use <tt>TargetInstrInfo::get(opcode)::ImplicitUses</tt>. Pre-colored
1431 registers impose constraints on any register allocation algorithm. The
1432 register allocator must make sure that none of them is been overwritten by
1433 the values of virtual registers while still alive.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1434
1435</div>
1436
1437<!-- _______________________________________________________________________ -->
1438
1439<div class="doc_subsubsection">
1440 <a name="regAlloc_howTo">Mapping virtual registers to physical registers</a>
1441</div>
1442
1443<div class="doc_text">
1444
1445<p>There are two ways to map virtual registers to physical registers (or to
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1446 memory slots). The first way, that we will call <i>direct mapping</i>, is
1447 based on the use of methods of the classes <tt>TargetRegisterInfo</tt>,
1448 and <tt>MachineOperand</tt>. The second way, that we will call <i>indirect
1449 mapping</i>, relies on the <tt>VirtRegMap</tt> class in order to insert loads
1450 and stores sending and getting values to and from memory.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1451
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1452<p>The direct mapping provides more flexibility to the developer of the register
1453 allocator; however, it is more error prone, and demands more implementation
1454 work. Basically, the programmer will have to specify where load and store
1455 instructions should be inserted in the target function being compiled in
1456 order to get and store values in memory. To assign a physical register to a
1457 virtual register present in a given operand,
1458 use <tt>MachineOperand::setReg(p_reg)</tt>. To insert a store instruction,
1459 use <tt>TargetRegisterInfo::storeRegToStackSlot(...)</tt>, and to insert a
1460 load instruction, use <tt>TargetRegisterInfo::loadRegFromStackSlot</tt>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1461
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1462<p>The indirect mapping shields the application developer from the complexities
1463 of inserting load and store instructions. In order to map a virtual register
1464 to a physical one, use <tt>VirtRegMap::assignVirt2Phys(vreg, preg)</tt>. In
1465 order to map a certain virtual register to memory,
1466 use <tt>VirtRegMap::assignVirt2StackSlot(vreg)</tt>. This method will return
1467 the stack slot where <tt>vreg</tt>'s value will be located. If it is
1468 necessary to map another virtual register to the same stack slot,
1469 use <tt>VirtRegMap::assignVirt2StackSlot(vreg, stack_location)</tt>. One
1470 important point to consider when using the indirect mapping, is that even if
1471 a virtual register is mapped to memory, it still needs to be mapped to a
1472 physical register. This physical register is the location where the virtual
1473 register is supposed to be found before being stored or after being
1474 reloaded.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1475
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1476<p>If the indirect strategy is used, after all the virtual registers have been
1477 mapped to physical registers or stack slots, it is necessary to use a spiller
1478 object to place load and store instructions in the code. Every virtual that
1479 has been mapped to a stack slot will be stored to memory after been defined
1480 and will be loaded before being used. The implementation of the spiller tries
1481 to recycle load/store instructions, avoiding unnecessary instructions. For an
1482 example of how to invoke the spiller,
1483 see <tt>RegAllocLinearScan::runOnMachineFunction</tt>
1484 in <tt>lib/CodeGen/RegAllocLinearScan.cpp</tt>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1485
1486</div>
1487
1488<!-- _______________________________________________________________________ -->
1489<div class="doc_subsubsection">
1490 <a name="regAlloc_twoAddr">Handling two address instructions</a>
1491</div>
1492
1493<div class="doc_text">
1494
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1495<p>With very rare exceptions (e.g., function calls), the LLVM machine code
1496 instructions are three address instructions. That is, each instruction is
1497 expected to define at most one register, and to use at most two registers.
1498 However, some architectures use two address instructions. In this case, the
1499 defined register is also one of the used register. For instance, an
1500 instruction such as <tt>ADD %EAX, %EBX</tt>, in X86 is actually equivalent
1501 to <tt>%EAX = %EAX + %EBX</tt>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1502
1503<p>In order to produce correct code, LLVM must convert three address
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1504 instructions that represent two address instructions into true two address
1505 instructions. LLVM provides the pass <tt>TwoAddressInstructionPass</tt> for
1506 this specific purpose. It must be run before register allocation takes
1507 place. After its execution, the resulting code may no longer be in SSA
1508 form. This happens, for instance, in situations where an instruction such
1509 as <tt>%a = ADD %b %c</tt> is converted to two instructions such as:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1510
1511<div class="doc_code">
1512<pre>
1513%a = MOVE %b
Dan Gohman03e58572008-06-13 17:55:57 +0000[diff] [blame]1514%a = ADD %a %c
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1515</pre>
1516</div>
1517
1518<p>Notice that, internally, the second instruction is represented as
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1519 <tt>ADD %a[def/use] %c</tt>. I.e., the register operand <tt>%a</tt> is both
1520 used and defined by the instruction.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1521
1522</div>
1523
1524<!-- _______________________________________________________________________ -->
1525<div class="doc_subsubsection">
1526 <a name="regAlloc_ssaDecon">The SSA deconstruction phase</a>
1527</div>
1528
1529<div class="doc_text">
1530
1531<p>An important transformation that happens during register allocation is called
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1532 the <i>SSA Deconstruction Phase</i>. The SSA form simplifies many analyses
1533 that are performed on the control flow graph of programs. However,
1534 traditional instruction sets do not implement PHI instructions. Thus, in
1535 order to generate executable code, compilers must replace PHI instructions
1536 with other instructions that preserve their semantics.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1537
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1538<p>There are many ways in which PHI instructions can safely be removed from the
1539 target code. The most traditional PHI deconstruction algorithm replaces PHI
1540 instructions with copy instructions. That is the strategy adopted by
1541 LLVM. The SSA deconstruction algorithm is implemented
1542 in <tt>lib/CodeGen/PHIElimination.cpp</tt>. In order to invoke this pass, the
1543 identifier <tt>PHIEliminationID</tt> must be marked as required in the code
1544 of the register allocator.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1545
1546</div>
1547
1548<!-- _______________________________________________________________________ -->
1549<div class="doc_subsubsection">
1550 <a name="regAlloc_fold">Instruction folding</a>
1551</div>
1552
1553<div class="doc_text">
1554
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1555<p><i>Instruction folding</i> is an optimization performed during register
1556 allocation that removes unnecessary copy instructions. For instance, a
1557 sequence of instructions such as:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1558
1559<div class="doc_code">
1560<pre>
1561%EBX = LOAD %mem_address
1562%EAX = COPY %EBX
1563</pre>
1564</div>
1565
Dan Gohmana7ab2bf2008-11-24 16:35:31 +0000[diff] [blame]1566<p>can be safely substituted by the single instruction:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1567
1568<div class="doc_code">
1569<pre>
1570%EAX = LOAD %mem_address
1571</pre>
1572</div>
1573
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1574<p>Instructions can be folded with
1575 the <tt>TargetRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
1576 taken when folding instructions; a folded instruction can be quite different
1577 from the original
1578 instruction. See <tt>LiveIntervals::addIntervalsForSpills</tt>
1579 in <tt>lib/CodeGen/LiveIntervalAnalysis.cpp</tt> for an example of its
1580 use.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1581
1582</div>
1583
1584<!-- _______________________________________________________________________ -->
1585
1586<div class="doc_subsubsection">
1587 <a name="regAlloc_builtIn">Built in register allocators</a>
1588</div>
1589
1590<div class="doc_text">
1591
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1592<p>The LLVM infrastructure provides the application developer with three
1593 different register allocators:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1594
1595<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1596 <li><i>Simple</i> &mdash; This is a very simple implementation that does not
1597 keep values in registers across instructions. This register allocator
1598 immediately spills every value right after it is computed, and reloads all
1599 used operands from memory to temporary registers before each
1600 instruction.</li>
1601
1602 <li><i>Local</i> &mdash; This register allocator is an improvement on the
1603 <i>Simple</i> implementation. It allocates registers on a basic block
1604 level, attempting to keep values in registers and reusing registers as
1605 appropriate.</li>
1606
1607 <li><i>Linear Scan</i> &mdash; <i>The default allocator</i>. This is the
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1608 well-know linear scan register allocator. Whereas the
1609 <i>Simple</i> and <i>Local</i> algorithms use a direct mapping
1610 implementation technique, the <i>Linear Scan</i> implementation
1611 uses a spiller in order to place load and stores.</li>
1612</ul>
1613
1614<p>The type of register allocator used in <tt>llc</tt> can be chosen with the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1615 command line option <tt>-regalloc=...</tt>:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1616
1617<div class="doc_code">
1618<pre>
Dan Gohman0cabaa52009-08-25 15:54:01 +0000[diff] [blame]1619$ llc -regalloc=simple file.bc -o sp.s;
1620$ llc -regalloc=local file.bc -o lc.s;
1621$ llc -regalloc=linearscan file.bc -o ln.s;
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1622</pre>
1623</div>
1624
1625</div>
1626
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1627<!-- ======================================================================= -->
1628<div class="doc_subsection">
1629 <a name="proepicode">Prolog/Epilog Code Insertion</a>
1630</div>
1631<div class="doc_text"><p>To Be Written</p></div>
1632<!-- ======================================================================= -->
1633<div class="doc_subsection">
1634 <a name="latemco">Late Machine Code Optimizations</a>
1635</div>
1636<div class="doc_text"><p>To Be Written</p></div>
1637<!-- ======================================================================= -->
1638<div class="doc_subsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1639 <a name="codeemit">Code Emission</a>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1640</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1641<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1642<!-- _______________________________________________________________________ -->
1643<div class="doc_subsubsection">
1644 <a name="codeemit_asm">Generating Assembly Code</a>
1645</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1646<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1647<!-- _______________________________________________________________________ -->
1648<div class="doc_subsubsection">
1649 <a name="codeemit_bin">Generating Binary Machine Code</a>
1650</div>
1651
1652<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1653 <p>For the JIT or <tt>.o</tt> file writer</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1654</div>
1655
1656
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1657<!-- *********************************************************************** -->
1658<div class="doc_section">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1659 <a name="targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1660</div>
1661<!-- *********************************************************************** -->
1662
1663<div class="doc_text">
1664
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1665<p>This section of the document explains features or design decisions that are
1666 specific to the code generator for a particular target.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1667
1668</div>
1669
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]1670<!-- ======================================================================= -->
1671<div class="doc_subsection">
1672 <a name="tailcallopt">Tail call optimization</a>
1673</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1674
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]1675<div class="doc_text">
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]1676
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1677<p>Tail call optimization, callee reusing the stack of the caller, is currently
1678 supported on x86/x86-64 and PowerPC. It is performed if:</p>
1679
1680<ul>
1681 <li>Caller and callee have the calling convention <tt>fastcc</tt>.</li>
1682
1683 <li>The call is a tail call - in tail position (ret immediately follows call
1684 and ret uses value of call or is void).</li>
1685
1686 <li>Option <tt>-tailcallopt</tt> is enabled.</li>
1687
1688 <li>Platform specific constraints are met.</li>
1689</ul>
1690
1691<p>x86/x86-64 constraints:</p>
1692
1693<ul>
1694 <li>No variable argument lists are used.</li>
1695
1696 <li>On x86-64 when generating GOT/PIC code only module-local calls (visibility
1697 = hidden or protected) are supported.</li>
1698</ul>
1699
1700<p>PowerPC constraints:</p>
1701
1702<ul>
1703 <li>No variable argument lists are used.</li>
1704
1705 <li>No byval parameters are used.</li>
1706
1707 <li>On ppc32/64 GOT/PIC only module-local calls (visibility = hidden or protected) are supported.</li>
1708</ul>
1709
1710<p>Example:</p>
1711
1712<p>Call as <tt>llc -tailcallopt test.ll</tt>.</p>
1713
1714<div class="doc_code">
1715<pre>
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]1716declare fastcc i32 @tailcallee(i32 inreg %a1, i32 inreg %a2, i32 %a3, i32 %a4)
1717
1718define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
1719 %l1 = add i32 %in1, %in2
1720 %tmp = tail call fastcc i32 @tailcallee(i32 %in1 inreg, i32 %in2 inreg, i32 %in1, i32 %l1)
1721 ret i32 %tmp
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1722}
1723</pre>
1724</div>
1725
1726<p>Implications of <tt>-tailcallopt</tt>:</p>
1727
1728<p>To support tail call optimization in situations where the callee has more
1729 arguments than the caller a 'callee pops arguments' convention is used. This
1730 currently causes each <tt>fastcc</tt> call that is not tail call optimized
1731 (because one or more of above constraints are not met) to be followed by a
1732 readjustment of the stack. So performance might be worse in such cases.</p>
1733
1734<p>On x86 and x86-64 one register is reserved for indirect tail calls (e.g via a
1735 function pointer). So there is one less register for integer argument
1736 passing. For x86 this means 2 registers (if <tt>inreg</tt> parameter
1737 attribute is used) and for x86-64 this means 5 register are used.</p>
1738
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]1739</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1740<!-- ======================================================================= -->
1741<div class="doc_subsection">
1742 <a name="x86">The X86 backend</a>
1743</div>
1744
1745<div class="doc_text">
1746
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1747<p>The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1748 code generator is capable of targeting a variety of x86-32 and x86-64
1749 processors, and includes support for ISA extensions such as MMX and SSE.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1750
1751</div>
1752
1753<!-- _______________________________________________________________________ -->
1754<div class="doc_subsubsection">
Nate Begeman34509842009-01-26 02:54:45 +0000[diff] [blame]1755 <a name="x86_tt">X86 Target Triples supported</a>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1756</div>
1757
1758<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1759
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1760<p>The following are the known target triples that are supported by the X86
1761 backend. This is not an exhaustive list, and it would be useful to add those
1762 that people test.</p>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1763
1764<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1765 <li><b>i686-pc-linux-gnu</b> &mdash; Linux</li>
1766
1767 <li><b>i386-unknown-freebsd5.3</b> &mdash; FreeBSD 5.3</li>
1768
1769 <li><b>i686-pc-cygwin</b> &mdash; Cygwin on Win32</li>
1770
1771 <li><b>i686-pc-mingw32</b> &mdash; MingW on Win32</li>
1772
1773 <li><b>i386-pc-mingw32msvc</b> &mdash; MingW crosscompiler on Linux</li>
1774
1775 <li><b>i686-apple-darwin*</b> &mdash; Apple Darwin on X86</li>
Torok Edwinc457b652009-06-15 12:17:44 +0000[diff] [blame]1776
1777 <li><b>x86_64-unknown-linux-gnu</b> &mdash; Linux</li>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1778</ul>
1779
1780</div>
1781
1782<!-- _______________________________________________________________________ -->
1783<div class="doc_subsubsection">
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]1784 <a name="x86_cc">X86 Calling Conventions supported</a>
1785</div>
1786
1787
1788<div class="doc_text">
1789
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1790<p>The following target-specific calling conventions are known to backend:</p>
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]1791
1792<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1793 <li><b>x86_StdCall</b> &mdash; stdcall calling convention seen on Microsoft
1794 Windows platform (CC ID = 64).</li>
1795
1796 <li><b>x86_FastCall</b> &mdash; fastcall calling convention seen on Microsoft
1797 Windows platform (CC ID = 65).</li>
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]1798</ul>
1799
1800</div>
1801
1802<!-- _______________________________________________________________________ -->
1803<div class="doc_subsubsection">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1804 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
1805</div>
1806
1807<div class="doc_text">
1808
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1809<p>The x86 has a very flexible way of accessing memory. It is capable of
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1810 forming memory addresses of the following expression directly in integer
1811 instructions (which use ModR/M addressing):</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1812
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1813<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1814<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1815Base + [1,2,4,8] * IndexReg + Disp32
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1816</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1817</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1818
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1819<p>In order to represent this, LLVM tracks no less than 4 operands for each
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1820 memory operand of this form. This means that the "load" form of
1821 '<tt>mov</tt>' has the following <tt>MachineOperand</tt>s in this order:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1822
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1823<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1824<pre>
1825Index: 0 | 1 2 3 4
1826Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
1827OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
1828</pre>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1829</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1830
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1831<p>Stores, and all other instructions, treat the four memory operands in the
1832 same way and in the same order.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1833
1834</div>
1835
1836<!-- _______________________________________________________________________ -->
1837<div class="doc_subsubsection">
Nate Begeman34509842009-01-26 02:54:45 +0000[diff] [blame]1838 <a name="x86_memory">X86 address spaces supported</a>
1839</div>
1840
1841<div class="doc_text">
1842
Dan Gohmand26795a2009-05-05 20:48:47 +0000[diff] [blame]1843<p>x86 has an experimental feature which provides
1844 the ability to perform loads and stores to different address spaces
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1845 via the x86 segment registers. A segment override prefix byte on an
1846 instruction causes the instruction's memory access to go to the specified
1847 segment. LLVM address space 0 is the default address space, which includes
1848 the stack, and any unqualified memory accesses in a program. Address spaces
1849 1-255 are currently reserved for user-defined code. The GS-segment is
Chris Lattner1777d0c2009-05-05 18:52:19 +0000[diff] [blame]1850 represented by address space 256, while the FS-segment is represented by
1851 address space 257. Other x86 segments have yet to be allocated address space
1852 numbers.</p>
Nate Begeman34509842009-01-26 02:54:45 +0000[diff] [blame]1853
Dan Gohmand26795a2009-05-05 20:48:47 +0000[diff] [blame]1854<p>While these address spaces may seem similar to TLS via the
1855 <tt>thread_local</tt> keyword, and often use the same underlying hardware,
1856 there are some fundamental differences.</p>
1857
1858<p>The <tt>thread_local</tt> keyword applies to global variables and
1859 specifies that they are to be allocated in thread-local memory. There are
1860 no type qualifiers involved, and these variables can be pointed to with
1861 normal pointers and accessed with normal loads and stores.
1862 The <tt>thread_local</tt> keyword is target-independent at the LLVM IR
1863 level (though LLVM doesn't yet have implementations of it for some
1864 configurations).<p>
1865
1866<p>Special address spaces, in contrast, apply to static types. Every
1867 load and store has a particular address space in its address operand type,
1868 and this is what determines which address space is accessed.
1869 LLVM ignores these special address space qualifiers on global variables,
1870 and does not provide a way to directly allocate storage in them.
1871 At the LLVM IR level, the behavior of these special address spaces depends
1872 in part on the underlying OS or runtime environment, and they are specific
1873 to x86 (and LLVM doesn't yet handle them correctly in some cases).</p>
1874
1875<p>Some operating systems and runtime environments use (or may in the future
1876 use) the FS/GS-segment registers for various low-level purposes, so care
1877 should be taken when considering them.</p>
Nate Begeman34509842009-01-26 02:54:45 +0000[diff] [blame]1878
1879</div>
1880
1881<!-- _______________________________________________________________________ -->
1882<div class="doc_subsubsection">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1883 <a name="x86_names">Instruction naming</a>
1884</div>
1885
1886<div class="doc_text">
1887
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1888<p>An instruction name consists of the base name, a default operand size, and a
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1889 a character per operand with an optional special size. For example:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1890
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1891<div class="doc_code">
1892<pre>
1893ADD8rr -&gt; add, 8-bit register, 8-bit register
1894IMUL16rmi -&gt; imul, 16-bit register, 16-bit memory, 16-bit immediate
1895IMUL16rmi8 -&gt; imul, 16-bit register, 16-bit memory, 8-bit immediate
1896MOVSX32rm16 -&gt; movsx, 32-bit register, 16-bit memory
1897</pre>
1898</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1899
1900</div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1901
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1902<!-- ======================================================================= -->
1903<div class="doc_subsection">
1904 <a name="ppc">The PowerPC backend</a>
1905</div>
1906
1907<div class="doc_text">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1908
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1909<p>The PowerPC code generator lives in the lib/Target/PowerPC directory. The
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1910 code generation is retargetable to several variations or <i>subtargets</i> of
1911 the PowerPC ISA; including ppc32, ppc64 and altivec.</p>
1912
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1913</div>
1914
1915<!-- _______________________________________________________________________ -->
1916<div class="doc_subsubsection">
1917 <a name="ppc_abi">LLVM PowerPC ABI</a>
1918</div>
1919
1920<div class="doc_text">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1921
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1922<p>LLVM follows the AIX PowerPC ABI, with two deviations. LLVM uses a PC
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1923 relative (PIC) or static addressing for accessing global values, so no TOC
1924 (r2) is used. Second, r31 is used as a frame pointer to allow dynamic growth
1925 of a stack frame. LLVM takes advantage of having no TOC to provide space to
1926 save the frame pointer in the PowerPC linkage area of the caller frame.
1927 Other details of PowerPC ABI can be found at <a href=
1928 "http://developer.apple.com/documentation/DeveloperTools/Conceptual/LowLevelABI/Articles/32bitPowerPC.html"
1929 >PowerPC ABI.</a> Note: This link describes the 32 bit ABI. The 64 bit ABI
1930 is similar except space for GPRs are 8 bytes wide (not 4) and r13 is reserved
1931 for system use.</p>
1932
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1933</div>
1934
1935<!-- _______________________________________________________________________ -->
1936<div class="doc_subsubsection">
1937 <a name="ppc_frame">Frame Layout</a>
1938</div>
1939
1940<div class="doc_text">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1941
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1942<p>The size of a PowerPC frame is usually fixed for the duration of a
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1943 function's invocation. Since the frame is fixed size, all references
1944 into the frame can be accessed via fixed offsets from the stack pointer. The
1945 exception to this is when dynamic alloca or variable sized arrays are
1946 present, then a base pointer (r31) is used as a proxy for the stack pointer
1947 and stack pointer is free to grow or shrink. A base pointer is also used if
1948 llvm-gcc is not passed the -fomit-frame-pointer flag. The stack pointer is
1949 always aligned to 16 bytes, so that space allocated for altivec vectors will
1950 be properly aligned.</p>
1951
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1952<p>An invocation frame is laid out as follows (low memory at top);</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1953
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1954<table class="layout">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1955 <tr>
1956 <td>Linkage<br><br></td>
1957 </tr>
1958 <tr>
1959 <td>Parameter area<br><br></td>
1960 </tr>
1961 <tr>
1962 <td>Dynamic area<br><br></td>
1963 </tr>
1964 <tr>
1965 <td>Locals area<br><br></td>
1966 </tr>
1967 <tr>
1968 <td>Saved registers area<br><br></td>
1969 </tr>
1970 <tr style="border-style: none hidden none hidden;">
1971 <td><br></td>
1972 </tr>
1973 <tr>
1974 <td>Previous Frame<br><br></td>
1975 </tr>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1976</table>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1977
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1978<p>The <i>linkage</i> area is used by a callee to save special registers prior
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1979 to allocating its own frame. Only three entries are relevant to LLVM. The
1980 first entry is the previous stack pointer (sp), aka link. This allows
1981 probing tools like gdb or exception handlers to quickly scan the frames in
1982 the stack. A function epilog can also use the link to pop the frame from the
1983 stack. The third entry in the linkage area is used to save the return
1984 address from the lr register. Finally, as mentioned above, the last entry is
1985 used to save the previous frame pointer (r31.) The entries in the linkage
1986 area are the size of a GPR, thus the linkage area is 24 bytes long in 32 bit
1987 mode and 48 bytes in 64 bit mode.</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1988
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1989<p>32 bit linkage area</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1990
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1991<table class="layout">
1992 <tr>
1993 <td>0</td>
1994 <td>Saved SP (r1)</td>
1995 </tr>
1996 <tr>
1997 <td>4</td>
1998 <td>Saved CR</td>
1999 </tr>
2000 <tr>
2001 <td>8</td>
2002 <td>Saved LR</td>
2003 </tr>
2004 <tr>
2005 <td>12</td>
2006 <td>Reserved</td>
2007 </tr>
2008 <tr>
2009 <td>16</td>
2010 <td>Reserved</td>
2011 </tr>
2012 <tr>
2013 <td>20</td>
2014 <td>Saved FP (r31)</td>
2015 </tr>
2016</table>
2017
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2018<p>64 bit linkage area</p>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2019
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2020<table class="layout">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2021 <tr>
2022 <td>0</td>
2023 <td>Saved SP (r1)</td>
2024 </tr>
2025 <tr>
2026 <td>8</td>
2027 <td>Saved CR</td>
2028 </tr>
2029 <tr>
2030 <td>16</td>
2031 <td>Saved LR</td>
2032 </tr>
2033 <tr>
2034 <td>24</td>
2035 <td>Reserved</td>
2036 </tr>
2037 <tr>
2038 <td>32</td>
2039 <td>Reserved</td>
2040 </tr>
2041 <tr>
2042 <td>40</td>
2043 <td>Saved FP (r31)</td>
2044 </tr>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2045</table>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2046
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2047<p>The <i>parameter area</i> is used to store arguments being passed to a callee
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2048 function. Following the PowerPC ABI, the first few arguments are actually
2049 passed in registers, with the space in the parameter area unused. However,
2050 if there are not enough registers or the callee is a thunk or vararg
2051 function, these register arguments can be spilled into the parameter area.
2052 Thus, the parameter area must be large enough to store all the parameters for
2053 the largest call sequence made by the caller. The size must also be
2054 minimally large enough to spill registers r3-r10. This allows callees blind
2055 to the call signature, such as thunks and vararg functions, enough space to
2056 cache the argument registers. Therefore, the parameter area is minimally 32
2057 bytes (64 bytes in 64 bit mode.) Also note that since the parameter area is
2058 a fixed offset from the top of the frame, that a callee can access its spilt
2059 arguments using fixed offsets from the stack pointer (or base pointer.)</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2060
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2061<p>Combining the information about the linkage, parameter areas and alignment. A
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2062 stack frame is minimally 64 bytes in 32 bit mode and 128 bytes in 64 bit
2063 mode.</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2064
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2065<p>The <i>dynamic area</i> starts out as size zero. If a function uses dynamic
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2066 alloca then space is added to the stack, the linkage and parameter areas are
2067 shifted to top of stack, and the new space is available immediately below the
2068 linkage and parameter areas. The cost of shifting the linkage and parameter
2069 areas is minor since only the link value needs to be copied. The link value
2070 can be easily fetched by adding the original frame size to the base pointer.
2071 Note that allocations in the dynamic space need to observe 16 byte
2072 alignment.</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2073
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2074<p>The <i>locals area</i> is where the llvm compiler reserves space for local
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2075 variables.</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2076
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2077<p>The <i>saved registers area</i> is where the llvm compiler spills callee
2078 saved registers on entry to the callee.</p>
2079
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2080</div>
2081
2082<!-- _______________________________________________________________________ -->
2083<div class="doc_subsubsection">
2084 <a name="ppc_prolog">Prolog/Epilog</a>
2085</div>
2086
2087<div class="doc_text">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2088
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2089<p>The llvm prolog and epilog are the same as described in the PowerPC ABI, with
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2090 the following exceptions. Callee saved registers are spilled after the frame
2091 is created. This allows the llvm epilog/prolog support to be common with
2092 other targets. The base pointer callee saved register r31 is saved in the
2093 TOC slot of linkage area. This simplifies allocation of space for the base
2094 pointer and makes it convenient to locate programatically and during
2095 debugging.</p>
2096
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2097</div>
2098
2099<!-- _______________________________________________________________________ -->
2100<div class="doc_subsubsection">
2101 <a name="ppc_dynamic">Dynamic Allocation</a>
2102</div>
2103
2104<div class="doc_text">
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2105
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]2106<p><i>TODO - More to come.</i></p>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2107
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]2108</div>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2109
2110
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]2111<!-- *********************************************************************** -->
2112<hr>
2113<address>
2114 <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
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Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]2118
2119 <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
Reid Spencer05fe4b02006-03-14 05:39:39 +0000[diff] [blame]2120 <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]2121 Last modified: $Date$
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