David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1 | //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file implements a simple register coalescing pass that attempts to |
| 11 | // aggressively coalesce every register copy that it can. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
Evan Cheng | 3b1f55e | 2007-07-31 22:37:44 +0000 | [diff] [blame] | 15 | #define DEBUG_TYPE "regcoalescing" |
Evan Cheng | a461c4d | 2007-11-05 17:41:38 +0000 | [diff] [blame] | 16 | #include "SimpleRegisterCoalescing.h" |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 17 | #include "VirtRegMap.h" |
Evan Cheng | a461c4d | 2007-11-05 17:41:38 +0000 | [diff] [blame] | 18 | #include "llvm/CodeGen/LiveIntervalAnalysis.h" |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 19 | #include "llvm/Value.h" |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 20 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 21 | #include "llvm/CodeGen/MachineInstr.h" |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 22 | #include "llvm/CodeGen/MachineLoopInfo.h" |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 24 | #include "llvm/CodeGen/Passes.h" |
David Greene | 2c17c4d | 2007-09-06 16:18:45 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/RegisterCoalescer.h" |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 26 | #include "llvm/Target/TargetInstrInfo.h" |
| 27 | #include "llvm/Target/TargetMachine.h" |
| 28 | #include "llvm/Support/CommandLine.h" |
| 29 | #include "llvm/Support/Debug.h" |
| 30 | #include "llvm/ADT/SmallSet.h" |
| 31 | #include "llvm/ADT/Statistic.h" |
| 32 | #include "llvm/ADT/STLExtras.h" |
| 33 | #include <algorithm> |
| 34 | #include <cmath> |
| 35 | using namespace llvm; |
| 36 | |
| 37 | STATISTIC(numJoins , "Number of interval joins performed"); |
Evan Cheng | e00f5de | 2008-06-19 01:39:21 +0000 | [diff] [blame] | 38 | STATISTIC(numSubJoins , "Number of subclass joins performed"); |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 39 | STATISTIC(numCommutes , "Number of instruction commuting performed"); |
| 40 | STATISTIC(numExtends , "Number of copies extended"); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 41 | STATISTIC(numPeep , "Number of identity moves eliminated after coalescing"); |
| 42 | STATISTIC(numAborts , "Number of times interval joining aborted"); |
| 43 | |
| 44 | char SimpleRegisterCoalescing::ID = 0; |
Dan Gohman | 844731a | 2008-05-13 00:00:25 +0000 | [diff] [blame] | 45 | static cl::opt<bool> |
| 46 | EnableJoining("join-liveintervals", |
| 47 | cl::desc("Coalesce copies (default=true)"), |
| 48 | cl::init(true)); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 49 | |
Dan Gohman | 844731a | 2008-05-13 00:00:25 +0000 | [diff] [blame] | 50 | static cl::opt<bool> |
| 51 | NewHeuristic("new-coalescer-heuristic", |
Evan Cheng | e00f5de | 2008-06-19 01:39:21 +0000 | [diff] [blame] | 52 | cl::desc("Use new coalescer heuristic"), |
| 53 | cl::init(false), cl::Hidden); |
| 54 | |
| 55 | static cl::opt<bool> |
| 56 | CrossClassJoin("join-subclass-copies", |
| 57 | cl::desc("Coalesce copies to sub- register class"), |
| 58 | cl::init(false), cl::Hidden); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 59 | |
Dan Gohman | 844731a | 2008-05-13 00:00:25 +0000 | [diff] [blame] | 60 | static RegisterPass<SimpleRegisterCoalescing> |
| 61 | X("simple-register-coalescing", "Simple Register Coalescing"); |
David Greene | 2c17c4d | 2007-09-06 16:18:45 +0000 | [diff] [blame] | 62 | |
Dan Gohman | 844731a | 2008-05-13 00:00:25 +0000 | [diff] [blame] | 63 | // Declare that we implement the RegisterCoalescer interface |
| 64 | static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 65 | |
Dan Gohman | 6ddba2b | 2008-05-13 02:05:11 +0000 | [diff] [blame] | 66 | const PassInfo *const llvm::SimpleRegisterCoalescingID = &X; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 67 | |
| 68 | void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 69 | AU.addPreserved<LiveIntervals>(); |
Bill Wendling | 67d65bb | 2008-01-04 20:54:55 +0000 | [diff] [blame] | 70 | AU.addPreserved<MachineLoopInfo>(); |
| 71 | AU.addPreservedID(MachineDominatorsID); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 72 | AU.addPreservedID(PHIEliminationID); |
| 73 | AU.addPreservedID(TwoAddressInstructionPassID); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 74 | AU.addRequired<LiveIntervals>(); |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 75 | AU.addRequired<MachineLoopInfo>(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 76 | MachineFunctionPass::getAnalysisUsage(AU); |
| 77 | } |
| 78 | |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 79 | /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 80 | /// being the source and IntB being the dest, thus this defines a value number |
| 81 | /// in IntB. If the source value number (in IntA) is defined by a copy from B, |
| 82 | /// see if we can merge these two pieces of B into a single value number, |
| 83 | /// eliminating a copy. For example: |
| 84 | /// |
| 85 | /// A3 = B0 |
| 86 | /// ... |
| 87 | /// B1 = A3 <- this copy |
| 88 | /// |
| 89 | /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1 |
| 90 | /// value number to be replaced with B0 (which simplifies the B liveinterval). |
| 91 | /// |
| 92 | /// This returns true if an interval was modified. |
| 93 | /// |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 94 | bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, |
| 95 | LiveInterval &IntB, |
| 96 | MachineInstr *CopyMI) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 97 | unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI)); |
| 98 | |
| 99 | // BValNo is a value number in B that is defined by a copy from A. 'B3' in |
| 100 | // the example above. |
| 101 | LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); |
Evan Cheng | ff7a3e5 | 2008-04-16 18:48:43 +0000 | [diff] [blame] | 102 | if (BLR == IntB.end()) // Should never happen! |
| 103 | return false; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 104 | VNInfo *BValNo = BLR->valno; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 105 | |
| 106 | // Get the location that B is defined at. Two options: either this value has |
| 107 | // an unknown definition point or it is defined at CopyIdx. If unknown, we |
| 108 | // can't process it. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 109 | if (!BValNo->copy) return false; |
| 110 | assert(BValNo->def == CopyIdx && "Copy doesn't define the value?"); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 111 | |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 112 | // AValNo is the value number in A that defines the copy, A3 in the example. |
| 113 | LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1); |
Evan Cheng | ff7a3e5 | 2008-04-16 18:48:43 +0000 | [diff] [blame] | 114 | if (ALR == IntA.end()) // Should never happen! |
| 115 | return false; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 116 | VNInfo *AValNo = ALR->valno; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 117 | |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 118 | // If AValNo is defined as a copy from IntB, we can potentially process this. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 119 | // Get the instruction that defines this value number. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 120 | unsigned SrcReg = li_->getVNInfoSourceReg(AValNo); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 121 | if (!SrcReg) return false; // Not defined by a copy. |
| 122 | |
| 123 | // If the value number is not defined by a copy instruction, ignore it. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 124 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 125 | // If the source register comes from an interval other than IntB, we can't |
| 126 | // handle this. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 127 | if (SrcReg != IntB.reg) return false; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 128 | |
| 129 | // Get the LiveRange in IntB that this value number starts with. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 130 | LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1); |
Evan Cheng | ff7a3e5 | 2008-04-16 18:48:43 +0000 | [diff] [blame] | 131 | if (ValLR == IntB.end()) // Should never happen! |
| 132 | return false; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 133 | |
| 134 | // Make sure that the end of the live range is inside the same block as |
| 135 | // CopyMI. |
| 136 | MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1); |
| 137 | if (!ValLREndInst || |
| 138 | ValLREndInst->getParent() != CopyMI->getParent()) return false; |
| 139 | |
| 140 | // Okay, we now know that ValLR ends in the same block that the CopyMI |
| 141 | // live-range starts. If there are no intervening live ranges between them in |
| 142 | // IntB, we can merge them. |
| 143 | if (ValLR+1 != BLR) return false; |
Evan Cheng | dc5294f | 2007-08-14 23:19:28 +0000 | [diff] [blame] | 144 | |
| 145 | // If a live interval is a physical register, conservatively check if any |
| 146 | // of its sub-registers is overlapping the live interval of the virtual |
| 147 | // register. If so, do not coalesce. |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 148 | if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) && |
| 149 | *tri_->getSubRegisters(IntB.reg)) { |
| 150 | for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) |
Evan Cheng | dc5294f | 2007-08-14 23:19:28 +0000 | [diff] [blame] | 151 | if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) { |
| 152 | DOUT << "Interfere with sub-register "; |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 153 | DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); |
Evan Cheng | dc5294f | 2007-08-14 23:19:28 +0000 | [diff] [blame] | 154 | return false; |
| 155 | } |
| 156 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 157 | |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 158 | DOUT << "\nExtending: "; IntB.print(DOUT, tri_); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 159 | |
Evan Cheng | a8d94f1 | 2007-08-07 23:49:57 +0000 | [diff] [blame] | 160 | unsigned FillerStart = ValLR->end, FillerEnd = BLR->start; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 161 | // We are about to delete CopyMI, so need to remove it as the 'instruction |
Evan Cheng | a8d94f1 | 2007-08-07 23:49:57 +0000 | [diff] [blame] | 162 | // that defines this value #'. Update the the valnum with the new defining |
| 163 | // instruction #. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 164 | BValNo->def = FillerStart; |
| 165 | BValNo->copy = NULL; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 166 | |
| 167 | // Okay, we can merge them. We need to insert a new liverange: |
| 168 | // [ValLR.end, BLR.begin) of either value number, then we merge the |
| 169 | // two value numbers. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 170 | IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo)); |
| 171 | |
| 172 | // If the IntB live range is assigned to a physical register, and if that |
| 173 | // physreg has aliases, |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 174 | if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 175 | // Update the liveintervals of sub-registers. |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 176 | for (const unsigned *AS = tri_->getSubRegisters(IntB.reg); *AS; ++AS) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 177 | LiveInterval &AliasLI = li_->getInterval(*AS); |
| 178 | AliasLI.addRange(LiveRange(FillerStart, FillerEnd, |
Evan Cheng | f3bb2e6 | 2007-09-05 21:46:51 +0000 | [diff] [blame] | 179 | AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator()))); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 180 | } |
| 181 | } |
| 182 | |
| 183 | // Okay, merge "B1" into the same value number as "B0". |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 184 | if (BValNo != ValLR->valno) |
| 185 | IntB.MergeValueNumberInto(BValNo, ValLR->valno); |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 186 | DOUT << " result = "; IntB.print(DOUT, tri_); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 187 | DOUT << "\n"; |
| 188 | |
| 189 | // If the source instruction was killing the source register before the |
| 190 | // merge, unset the isKill marker given the live range has been extended. |
| 191 | int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true); |
| 192 | if (UIdx != -1) |
Chris Lattner | f738230 | 2007-12-30 21:56:09 +0000 | [diff] [blame] | 193 | ValLREndInst->getOperand(UIdx).setIsKill(false); |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 194 | |
| 195 | ++numExtends; |
| 196 | return true; |
| 197 | } |
| 198 | |
Evan Cheng | 559f422 | 2008-02-16 02:32:17 +0000 | [diff] [blame] | 199 | /// HasOtherReachingDefs - Return true if there are definitions of IntB |
| 200 | /// other than BValNo val# that can reach uses of AValno val# of IntA. |
| 201 | bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA, |
| 202 | LiveInterval &IntB, |
| 203 | VNInfo *AValNo, |
| 204 | VNInfo *BValNo) { |
| 205 | for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end(); |
| 206 | AI != AE; ++AI) { |
| 207 | if (AI->valno != AValNo) continue; |
| 208 | LiveInterval::Ranges::iterator BI = |
| 209 | std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start); |
| 210 | if (BI != IntB.ranges.begin()) |
| 211 | --BI; |
| 212 | for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) { |
| 213 | if (BI->valno == BValNo) |
| 214 | continue; |
| 215 | if (BI->start <= AI->start && BI->end > AI->start) |
| 216 | return true; |
| 217 | if (BI->start > AI->start && BI->start < AI->end) |
| 218 | return true; |
| 219 | } |
| 220 | } |
| 221 | return false; |
| 222 | } |
| 223 | |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 224 | /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA |
| 225 | /// being the source and IntB being the dest, thus this defines a value number |
| 226 | /// in IntB. If the source value number (in IntA) is defined by a commutable |
| 227 | /// instruction and its other operand is coalesced to the copy dest register, |
| 228 | /// see if we can transform the copy into a noop by commuting the definition. For |
| 229 | /// example, |
| 230 | /// |
| 231 | /// A3 = op A2 B0<kill> |
| 232 | /// ... |
| 233 | /// B1 = A3 <- this copy |
| 234 | /// ... |
| 235 | /// = op A3 <- more uses |
| 236 | /// |
| 237 | /// ==> |
| 238 | /// |
| 239 | /// B2 = op B0 A2<kill> |
| 240 | /// ... |
| 241 | /// B1 = B2 <- now an identify copy |
| 242 | /// ... |
| 243 | /// = op B2 <- more uses |
| 244 | /// |
| 245 | /// This returns true if an interval was modified. |
| 246 | /// |
| 247 | bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, |
| 248 | LiveInterval &IntB, |
| 249 | MachineInstr *CopyMI) { |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 250 | unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI)); |
| 251 | |
Evan Cheng | a9407f5 | 2008-02-18 18:56:31 +0000 | [diff] [blame] | 252 | // FIXME: For now, only eliminate the copy by commuting its def when the |
| 253 | // source register is a virtual register. We want to guard against cases |
| 254 | // where the copy is a back edge copy and commuting the def lengthen the |
| 255 | // live interval of the source register to the entire loop. |
| 256 | if (TargetRegisterInfo::isPhysicalRegister(IntA.reg)) |
Evan Cheng | 96cfff0 | 2008-02-18 08:40:53 +0000 | [diff] [blame] | 257 | return false; |
| 258 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 259 | // BValNo is a value number in B that is defined by a copy from A. 'B3' in |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 260 | // the example above. |
| 261 | LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); |
Evan Cheng | ff7a3e5 | 2008-04-16 18:48:43 +0000 | [diff] [blame] | 262 | if (BLR == IntB.end()) // Should never happen! |
| 263 | return false; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 264 | VNInfo *BValNo = BLR->valno; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 265 | |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 266 | // Get the location that B is defined at. Two options: either this value has |
| 267 | // an unknown definition point or it is defined at CopyIdx. If unknown, we |
| 268 | // can't process it. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 269 | if (!BValNo->copy) return false; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 270 | assert(BValNo->def == CopyIdx && "Copy doesn't define the value?"); |
| 271 | |
| 272 | // AValNo is the value number in A that defines the copy, A3 in the example. |
| 273 | LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1); |
Evan Cheng | ff7a3e5 | 2008-04-16 18:48:43 +0000 | [diff] [blame] | 274 | if (ALR == IntA.end()) // Should never happen! |
| 275 | return false; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 276 | VNInfo *AValNo = ALR->valno; |
Evan Cheng | e35a6d1 | 2008-02-13 08:41:08 +0000 | [diff] [blame] | 277 | // If other defs can reach uses of this def, then it's not safe to perform |
| 278 | // the optimization. |
| 279 | if (AValNo->def == ~0U || AValNo->def == ~1U || AValNo->hasPHIKill) |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 280 | return false; |
| 281 | MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def); |
| 282 | const TargetInstrDesc &TID = DefMI->getDesc(); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 283 | unsigned NewDstIdx; |
| 284 | if (!TID.isCommutable() || |
| 285 | !tii_->CommuteChangesDestination(DefMI, NewDstIdx)) |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 286 | return false; |
| 287 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 288 | MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); |
| 289 | unsigned NewReg = NewDstMO.getReg(); |
| 290 | if (NewReg != IntB.reg || !NewDstMO.isKill()) |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 291 | return false; |
| 292 | |
| 293 | // Make sure there are no other definitions of IntB that would reach the |
| 294 | // uses which the new definition can reach. |
Evan Cheng | 559f422 | 2008-02-16 02:32:17 +0000 | [diff] [blame] | 295 | if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo)) |
| 296 | return false; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 297 | |
Evan Cheng | ed70cbb3 | 2008-03-26 19:03:01 +0000 | [diff] [blame] | 298 | // If some of the uses of IntA.reg is already coalesced away, return false. |
| 299 | // It's not possible to determine whether it's safe to perform the coalescing. |
| 300 | for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg), |
| 301 | UE = mri_->use_end(); UI != UE; ++UI) { |
| 302 | MachineInstr *UseMI = &*UI; |
| 303 | unsigned UseIdx = li_->getInstructionIndex(UseMI); |
| 304 | LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx); |
Evan Cheng | ff7a3e5 | 2008-04-16 18:48:43 +0000 | [diff] [blame] | 305 | if (ULR == IntA.end()) |
| 306 | continue; |
Evan Cheng | ed70cbb3 | 2008-03-26 19:03:01 +0000 | [diff] [blame] | 307 | if (ULR->valno == AValNo && JoinedCopies.count(UseMI)) |
| 308 | return false; |
| 309 | } |
| 310 | |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 311 | // At this point we have decided that it is legal to do this |
| 312 | // transformation. Start by commuting the instruction. |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 313 | MachineBasicBlock *MBB = DefMI->getParent(); |
| 314 | MachineInstr *NewMI = tii_->commuteInstruction(DefMI); |
Evan Cheng | 559f422 | 2008-02-16 02:32:17 +0000 | [diff] [blame] | 315 | if (!NewMI) |
| 316 | return false; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 317 | if (NewMI != DefMI) { |
| 318 | li_->ReplaceMachineInstrInMaps(DefMI, NewMI); |
| 319 | MBB->insert(DefMI, NewMI); |
| 320 | MBB->erase(DefMI); |
| 321 | } |
Evan Cheng | 6130f66 | 2008-03-05 00:59:57 +0000 | [diff] [blame] | 322 | unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false); |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 323 | NewMI->getOperand(OpIdx).setIsKill(); |
| 324 | |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 325 | bool BHasPHIKill = BValNo->hasPHIKill; |
| 326 | SmallVector<VNInfo*, 4> BDeadValNos; |
| 327 | SmallVector<unsigned, 4> BKills; |
| 328 | std::map<unsigned, unsigned> BExtend; |
Evan Cheng | 4ff3f1c | 2008-03-10 08:11:32 +0000 | [diff] [blame] | 329 | |
| 330 | // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g. |
| 331 | // A = or A, B |
| 332 | // ... |
| 333 | // B = A |
| 334 | // ... |
| 335 | // C = A<kill> |
| 336 | // ... |
| 337 | // = B |
| 338 | // |
| 339 | // then do not add kills of A to the newly created B interval. |
| 340 | bool Extended = BLR->end > ALR->end && ALR->end != ALR->start; |
| 341 | if (Extended) |
| 342 | BExtend[ALR->end] = BLR->end; |
| 343 | |
| 344 | // Update uses of IntA of the specific Val# with IntB. |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 345 | for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg), |
| 346 | UE = mri_->use_end(); UI != UE;) { |
| 347 | MachineOperand &UseMO = UI.getOperand(); |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 348 | MachineInstr *UseMI = &*UI; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 349 | ++UI; |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 350 | if (JoinedCopies.count(UseMI)) |
Evan Cheng | ed70cbb3 | 2008-03-26 19:03:01 +0000 | [diff] [blame] | 351 | continue; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 352 | unsigned UseIdx = li_->getInstructionIndex(UseMI); |
| 353 | LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx); |
Evan Cheng | ff7a3e5 | 2008-04-16 18:48:43 +0000 | [diff] [blame] | 354 | if (ULR == IntA.end() || ULR->valno != AValNo) |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 355 | continue; |
| 356 | UseMO.setReg(NewReg); |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 357 | if (UseMI == CopyMI) |
| 358 | continue; |
Evan Cheng | 4ff3f1c | 2008-03-10 08:11:32 +0000 | [diff] [blame] | 359 | if (UseMO.isKill()) { |
| 360 | if (Extended) |
| 361 | UseMO.setIsKill(false); |
| 362 | else |
| 363 | BKills.push_back(li_->getUseIndex(UseIdx)+1); |
| 364 | } |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 365 | unsigned SrcReg, DstReg; |
| 366 | if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg)) |
| 367 | continue; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 368 | if (DstReg == IntB.reg) { |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 369 | // This copy will become a noop. If it's defining a new val#, |
| 370 | // remove that val# as well. However this live range is being |
| 371 | // extended to the end of the existing live range defined by the copy. |
| 372 | unsigned DefIdx = li_->getDefIndex(UseIdx); |
Evan Cheng | ff7a3e5 | 2008-04-16 18:48:43 +0000 | [diff] [blame] | 373 | const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx); |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 374 | BHasPHIKill |= DLR->valno->hasPHIKill; |
| 375 | assert(DLR->valno->def == DefIdx); |
| 376 | BDeadValNos.push_back(DLR->valno); |
| 377 | BExtend[DLR->start] = DLR->end; |
| 378 | JoinedCopies.insert(UseMI); |
| 379 | // If this is a kill but it's going to be removed, the last use |
| 380 | // of the same val# is the new kill. |
Evan Cheng | 4ff3f1c | 2008-03-10 08:11:32 +0000 | [diff] [blame] | 381 | if (UseMO.isKill()) |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 382 | BKills.pop_back(); |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 383 | } |
| 384 | } |
| 385 | |
| 386 | // We need to insert a new liverange: [ALR.start, LastUse). It may be we can |
| 387 | // simply extend BLR if CopyMI doesn't end the range. |
| 388 | DOUT << "\nExtending: "; IntB.print(DOUT, tri_); |
| 389 | |
Evan Cheng | 739583b | 2008-06-17 20:11:16 +0000 | [diff] [blame] | 390 | // Remove val#'s defined by copies that will be coalesced away. |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 391 | for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) |
| 392 | IntB.removeValNo(BDeadValNos[i]); |
Evan Cheng | 739583b | 2008-06-17 20:11:16 +0000 | [diff] [blame] | 393 | |
| 394 | // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition |
| 395 | // is updated. Kills are also updated. |
| 396 | VNInfo *ValNo = BValNo; |
| 397 | ValNo->def = AValNo->def; |
| 398 | ValNo->copy = NULL; |
| 399 | for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) { |
| 400 | unsigned Kill = ValNo->kills[j]; |
| 401 | if (Kill != BLR->end) |
| 402 | BKills.push_back(Kill); |
| 403 | } |
| 404 | ValNo->kills.clear(); |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 405 | for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end(); |
| 406 | AI != AE; ++AI) { |
| 407 | if (AI->valno != AValNo) continue; |
| 408 | unsigned End = AI->end; |
| 409 | std::map<unsigned, unsigned>::iterator EI = BExtend.find(End); |
| 410 | if (EI != BExtend.end()) |
| 411 | End = EI->second; |
| 412 | IntB.addRange(LiveRange(AI->start, End, ValNo)); |
| 413 | } |
| 414 | IntB.addKills(ValNo, BKills); |
| 415 | ValNo->hasPHIKill = BHasPHIKill; |
| 416 | |
| 417 | DOUT << " result = "; IntB.print(DOUT, tri_); |
| 418 | DOUT << "\n"; |
| 419 | |
| 420 | DOUT << "\nShortening: "; IntA.print(DOUT, tri_); |
| 421 | IntA.removeValNo(AValNo); |
| 422 | DOUT << " result = "; IntA.print(DOUT, tri_); |
| 423 | DOUT << "\n"; |
| 424 | |
| 425 | ++numCommutes; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 426 | return true; |
| 427 | } |
| 428 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 429 | /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy. |
| 430 | /// |
| 431 | bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI, |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 432 | unsigned DstReg) const { |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 433 | MachineBasicBlock *MBB = CopyMI->getParent(); |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 434 | const MachineLoop *L = loopInfo->getLoopFor(MBB); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 435 | if (!L) |
| 436 | return false; |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 437 | if (MBB != L->getLoopLatch()) |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 438 | return false; |
| 439 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 440 | LiveInterval &LI = li_->getInterval(DstReg); |
| 441 | unsigned DefIdx = li_->getInstructionIndex(CopyMI); |
| 442 | LiveInterval::const_iterator DstLR = |
| 443 | LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx)); |
| 444 | if (DstLR == LI.end()) |
| 445 | return false; |
Owen Anderson | b3db9c9 | 2008-06-23 22:12:23 +0000 | [diff] [blame] | 446 | unsigned KillIdx = li_->getMBBEndIdx(MBB) + 1; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 447 | if (DstLR->valno->kills.size() == 1 && |
| 448 | DstLR->valno->kills[0] == KillIdx && DstLR->valno->hasPHIKill) |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 449 | return true; |
| 450 | return false; |
| 451 | } |
| 452 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 453 | /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and |
| 454 | /// update the subregister number if it is not zero. If DstReg is a |
| 455 | /// physical register and the existing subregister number of the def / use |
| 456 | /// being updated is not zero, make sure to set it to the correct physical |
| 457 | /// subregister. |
| 458 | void |
| 459 | SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, |
| 460 | unsigned SubIdx) { |
| 461 | bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); |
| 462 | if (DstIsPhys && SubIdx) { |
| 463 | // Figure out the real physical register we are updating with. |
| 464 | DstReg = tri_->getSubReg(DstReg, SubIdx); |
| 465 | SubIdx = 0; |
| 466 | } |
| 467 | |
| 468 | for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg), |
| 469 | E = mri_->reg_end(); I != E; ) { |
| 470 | MachineOperand &O = I.getOperand(); |
Evan Cheng | 70366b9 | 2008-03-21 19:09:30 +0000 | [diff] [blame] | 471 | MachineInstr *UseMI = &*I; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 472 | ++I; |
Evan Cheng | 621d157 | 2008-04-17 00:06:42 +0000 | [diff] [blame] | 473 | unsigned OldSubIdx = O.getSubReg(); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 474 | if (DstIsPhys) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 475 | unsigned UseDstReg = DstReg; |
Evan Cheng | 621d157 | 2008-04-17 00:06:42 +0000 | [diff] [blame] | 476 | if (OldSubIdx) |
| 477 | UseDstReg = tri_->getSubReg(DstReg, OldSubIdx); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 478 | O.setReg(UseDstReg); |
| 479 | O.setSubReg(0); |
| 480 | } else { |
Evan Cheng | c886c46 | 2008-02-26 08:03:41 +0000 | [diff] [blame] | 481 | // Sub-register indexes goes from small to large. e.g. |
Evan Cheng | a8f720d | 2008-04-18 19:25:26 +0000 | [diff] [blame] | 482 | // RAX: 1 -> AL, 2 -> AX, 3 -> EAX |
| 483 | // EAX: 1 -> AL, 2 -> AX |
Evan Cheng | c886c46 | 2008-02-26 08:03:41 +0000 | [diff] [blame] | 484 | // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose |
| 485 | // sub-register 2 is also AX. |
| 486 | if (SubIdx && OldSubIdx && SubIdx != OldSubIdx) |
| 487 | assert(OldSubIdx < SubIdx && "Conflicting sub-register index!"); |
| 488 | else if (SubIdx) |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 489 | O.setSubReg(SubIdx); |
Evan Cheng | 70366b9 | 2008-03-21 19:09:30 +0000 | [diff] [blame] | 490 | // Remove would-be duplicated kill marker. |
| 491 | if (O.isKill() && UseMI->killsRegister(DstReg)) |
| 492 | O.setIsKill(false); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 493 | O.setReg(DstReg); |
| 494 | } |
| 495 | } |
| 496 | } |
| 497 | |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 498 | /// RemoveDeadImpDef - Remove implicit_def instructions which are "re-defining" |
| 499 | /// registers due to insert_subreg coalescing. e.g. |
| 500 | /// r1024 = op |
| 501 | /// r1025 = implicit_def |
| 502 | /// r1025 = insert_subreg r1025, r1024 |
| 503 | /// = op r1025 |
| 504 | /// => |
| 505 | /// r1025 = op |
| 506 | /// r1025 = implicit_def |
| 507 | /// r1025 = insert_subreg r1025, r1025 |
| 508 | /// = op r1025 |
| 509 | void |
| 510 | SimpleRegisterCoalescing::RemoveDeadImpDef(unsigned Reg, LiveInterval &LI) { |
| 511 | for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg), |
| 512 | E = mri_->reg_end(); I != E; ) { |
| 513 | MachineOperand &O = I.getOperand(); |
| 514 | MachineInstr *DefMI = &*I; |
| 515 | ++I; |
| 516 | if (!O.isDef()) |
| 517 | continue; |
| 518 | if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF) |
| 519 | continue; |
| 520 | if (!LI.liveBeforeAndAt(li_->getInstructionIndex(DefMI))) |
| 521 | continue; |
| 522 | li_->RemoveMachineInstrFromMaps(DefMI); |
| 523 | DefMI->eraseFromParent(); |
| 524 | } |
| 525 | } |
| 526 | |
Evan Cheng | 4ff3f1c | 2008-03-10 08:11:32 +0000 | [diff] [blame] | 527 | /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate |
| 528 | /// due to live range lengthening as the result of coalescing. |
| 529 | void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg, |
| 530 | LiveInterval &LI) { |
| 531 | for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg), |
| 532 | UE = mri_->use_end(); UI != UE; ++UI) { |
| 533 | MachineOperand &UseMO = UI.getOperand(); |
| 534 | if (UseMO.isKill()) { |
| 535 | MachineInstr *UseMI = UseMO.getParent(); |
| 536 | unsigned SReg, DReg; |
| 537 | if (!tii_->isMoveInstr(*UseMI, SReg, DReg)) |
| 538 | continue; |
| 539 | unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI)); |
| 540 | if (JoinedCopies.count(UseMI)) |
| 541 | continue; |
Evan Cheng | ff7a3e5 | 2008-04-16 18:48:43 +0000 | [diff] [blame] | 542 | const LiveRange *UI = LI.getLiveRangeContaining(UseIdx); |
Evan Cheng | 4ff3f1c | 2008-03-10 08:11:32 +0000 | [diff] [blame] | 543 | if (!LI.isKill(UI->valno, UseIdx+1)) |
| 544 | UseMO.setIsKill(false); |
| 545 | } |
| 546 | } |
| 547 | } |
| 548 | |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 549 | /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range |
| 550 | /// from a physical register live interval as well as from the live intervals |
| 551 | /// of its sub-registers. |
| 552 | static void removeRange(LiveInterval &li, unsigned Start, unsigned End, |
| 553 | LiveIntervals *li_, const TargetRegisterInfo *tri_) { |
| 554 | li.removeRange(Start, End, true); |
| 555 | if (TargetRegisterInfo::isPhysicalRegister(li.reg)) { |
| 556 | for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) { |
| 557 | if (!li_->hasInterval(*SR)) |
| 558 | continue; |
| 559 | LiveInterval &sli = li_->getInterval(*SR); |
| 560 | unsigned RemoveEnd = Start; |
| 561 | while (RemoveEnd != End) { |
| 562 | LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start); |
| 563 | if (LR == sli.end()) |
| 564 | break; |
| 565 | RemoveEnd = (LR->end < End) ? LR->end : End; |
| 566 | sli.removeRange(Start, RemoveEnd, true); |
| 567 | Start = RemoveEnd; |
| 568 | } |
| 569 | } |
| 570 | } |
| 571 | } |
| 572 | |
| 573 | /// removeIntervalIfEmpty - Check if the live interval of a physical register |
| 574 | /// is empty, if so remove it and also remove the empty intervals of its |
Evan Cheng | 9c1e06e | 2008-04-16 20:24:25 +0000 | [diff] [blame] | 575 | /// sub-registers. Return true if live interval is removed. |
| 576 | static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_, |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 577 | const TargetRegisterInfo *tri_) { |
| 578 | if (li.empty()) { |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 579 | if (TargetRegisterInfo::isPhysicalRegister(li.reg)) |
| 580 | for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) { |
| 581 | if (!li_->hasInterval(*SR)) |
| 582 | continue; |
| 583 | LiveInterval &sli = li_->getInterval(*SR); |
| 584 | if (sli.empty()) |
| 585 | li_->removeInterval(*SR); |
| 586 | } |
Evan Cheng | d94950c | 2008-04-16 01:22:28 +0000 | [diff] [blame] | 587 | li_->removeInterval(li.reg); |
Evan Cheng | 9c1e06e | 2008-04-16 20:24:25 +0000 | [diff] [blame] | 588 | return true; |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 589 | } |
Evan Cheng | 9c1e06e | 2008-04-16 20:24:25 +0000 | [diff] [blame] | 590 | return false; |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 591 | } |
| 592 | |
| 593 | /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy. |
Evan Cheng | 9c1e06e | 2008-04-16 20:24:25 +0000 | [diff] [blame] | 594 | /// Return true if live interval is removed. |
| 595 | bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li, |
Evan Cheng | ecb2a8b | 2008-03-05 22:09:42 +0000 | [diff] [blame] | 596 | MachineInstr *CopyMI) { |
| 597 | unsigned CopyIdx = li_->getInstructionIndex(CopyMI); |
| 598 | LiveInterval::iterator MLR = |
| 599 | li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx)); |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 600 | if (MLR == li.end()) |
Evan Cheng | 9c1e06e | 2008-04-16 20:24:25 +0000 | [diff] [blame] | 601 | return false; // Already removed by ShortenDeadCopySrcLiveRange. |
Evan Cheng | ecb2a8b | 2008-03-05 22:09:42 +0000 | [diff] [blame] | 602 | unsigned RemoveStart = MLR->start; |
| 603 | unsigned RemoveEnd = MLR->end; |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 604 | // Remove the liverange that's defined by this. |
| 605 | if (RemoveEnd == li_->getDefIndex(CopyIdx)+1) { |
| 606 | removeRange(li, RemoveStart, RemoveEnd, li_, tri_); |
Evan Cheng | 9c1e06e | 2008-04-16 20:24:25 +0000 | [diff] [blame] | 607 | return removeIntervalIfEmpty(li, li_, tri_); |
Evan Cheng | ecb2a8b | 2008-03-05 22:09:42 +0000 | [diff] [blame] | 608 | } |
Evan Cheng | 9c1e06e | 2008-04-16 20:24:25 +0000 | [diff] [blame] | 609 | return false; |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 610 | } |
| 611 | |
Evan Cheng | 0c28432 | 2008-03-26 20:15:49 +0000 | [diff] [blame] | 612 | /// PropagateDeadness - Propagate the dead marker to the instruction which |
| 613 | /// defines the val#. |
| 614 | static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI, |
| 615 | unsigned &LRStart, LiveIntervals *li_, |
| 616 | const TargetRegisterInfo* tri_) { |
| 617 | MachineInstr *DefMI = |
| 618 | li_->getInstructionFromIndex(li_->getDefIndex(LRStart)); |
| 619 | if (DefMI && DefMI != CopyMI) { |
| 620 | int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_); |
| 621 | if (DeadIdx != -1) { |
| 622 | DefMI->getOperand(DeadIdx).setIsDead(); |
| 623 | // A dead def should have a single cycle interval. |
| 624 | ++LRStart; |
| 625 | } |
| 626 | } |
| 627 | } |
| 628 | |
Evan Cheng | 883d260 | 2008-04-18 19:22:23 +0000 | [diff] [blame] | 629 | /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply |
| 630 | /// fallthoughs to SuccMBB. |
| 631 | static bool isSameOrFallThroughBB(MachineBasicBlock *MBB, |
| 632 | MachineBasicBlock *SuccMBB, |
| 633 | const TargetInstrInfo *tii_) { |
| 634 | if (MBB == SuccMBB) |
| 635 | return true; |
| 636 | MachineBasicBlock *TBB = 0, *FBB = 0; |
| 637 | std::vector<MachineOperand> Cond; |
| 638 | return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB && |
| 639 | MBB->isSuccessor(SuccMBB); |
| 640 | } |
| 641 | |
Bill Wendling | f231778 | 2008-04-17 05:20:39 +0000 | [diff] [blame] | 642 | /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially |
| 643 | /// extended by a dead copy. Mark the last use (if any) of the val# as kill as |
| 644 | /// ends the live range there. If there isn't another use, then this live range |
| 645 | /// is dead. Return true if live interval is removed. |
Evan Cheng | 9c1e06e | 2008-04-16 20:24:25 +0000 | [diff] [blame] | 646 | bool |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 647 | SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li, |
| 648 | MachineInstr *CopyMI) { |
| 649 | unsigned CopyIdx = li_->getInstructionIndex(CopyMI); |
| 650 | if (CopyIdx == 0) { |
| 651 | // FIXME: special case: function live in. It can be a general case if the |
| 652 | // first instruction index starts at > 0 value. |
| 653 | assert(TargetRegisterInfo::isPhysicalRegister(li.reg)); |
| 654 | // Live-in to the function but dead. Remove it from entry live-in set. |
Evan Cheng | a971dbd | 2008-04-24 09:06:33 +0000 | [diff] [blame] | 655 | if (mf_->begin()->isLiveIn(li.reg)) |
| 656 | mf_->begin()->removeLiveIn(li.reg); |
Evan Cheng | ff7a3e5 | 2008-04-16 18:48:43 +0000 | [diff] [blame] | 657 | const LiveRange *LR = li.getLiveRangeContaining(CopyIdx); |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 658 | removeRange(li, LR->start, LR->end, li_, tri_); |
Evan Cheng | 9c1e06e | 2008-04-16 20:24:25 +0000 | [diff] [blame] | 659 | return removeIntervalIfEmpty(li, li_, tri_); |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 660 | } |
| 661 | |
| 662 | LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1); |
| 663 | if (LR == li.end()) |
| 664 | // Livein but defined by a phi. |
Evan Cheng | 9c1e06e | 2008-04-16 20:24:25 +0000 | [diff] [blame] | 665 | return false; |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 666 | |
| 667 | unsigned RemoveStart = LR->start; |
| 668 | unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1; |
| 669 | if (LR->end > RemoveEnd) |
| 670 | // More uses past this copy? Nothing to do. |
Evan Cheng | 9c1e06e | 2008-04-16 20:24:25 +0000 | [diff] [blame] | 671 | return false; |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 672 | |
Evan Cheng | 883d260 | 2008-04-18 19:22:23 +0000 | [diff] [blame] | 673 | MachineBasicBlock *CopyMBB = CopyMI->getParent(); |
| 674 | unsigned MBBStart = li_->getMBBStartIdx(CopyMBB); |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 675 | unsigned LastUseIdx; |
Evan Cheng | d2012d0 | 2008-04-10 23:48:35 +0000 | [diff] [blame] | 676 | MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg, |
| 677 | LastUseIdx); |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 678 | if (LastUse) { |
Evan Cheng | 883d260 | 2008-04-18 19:22:23 +0000 | [diff] [blame] | 679 | MachineInstr *LastUseMI = LastUse->getParent(); |
| 680 | if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) { |
| 681 | // r1024 = op |
| 682 | // ... |
| 683 | // BB1: |
| 684 | // = r1024 |
| 685 | // |
| 686 | // BB2: |
| 687 | // r1025<dead> = r1024<kill> |
| 688 | if (MBBStart < LR->end) |
| 689 | removeRange(li, MBBStart, LR->end, li_, tri_); |
| 690 | return false; |
| 691 | } |
| 692 | |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 693 | // There are uses before the copy, just shorten the live range to the end |
| 694 | // of last use. |
| 695 | LastUse->setIsKill(); |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 696 | removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_); |
| 697 | unsigned SrcReg, DstReg; |
| 698 | if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg) && |
| 699 | DstReg == li.reg) { |
| 700 | // Last use is itself an identity code. |
| 701 | int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_); |
| 702 | LastUseMI->getOperand(DeadIdx).setIsDead(); |
| 703 | } |
Evan Cheng | 9c1e06e | 2008-04-16 20:24:25 +0000 | [diff] [blame] | 704 | return false; |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 705 | } |
| 706 | |
| 707 | // Is it livein? |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 708 | if (LR->start <= MBBStart && LR->end > MBBStart) { |
| 709 | if (LR->start == 0) { |
| 710 | assert(TargetRegisterInfo::isPhysicalRegister(li.reg)); |
| 711 | // Live-in to the function but dead. Remove it from entry live-in set. |
| 712 | mf_->begin()->removeLiveIn(li.reg); |
| 713 | } |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 714 | // FIXME: Shorten intervals in BBs that reaches this BB. |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 715 | } |
| 716 | |
Evan Cheng | 0c28432 | 2008-03-26 20:15:49 +0000 | [diff] [blame] | 717 | if (LR->valno->def == RemoveStart) |
| 718 | // If the def MI defines the val#, propagate the dead marker. |
| 719 | PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_); |
| 720 | |
| 721 | removeRange(li, RemoveStart, LR->end, li_, tri_); |
Evan Cheng | 9c1e06e | 2008-04-16 20:24:25 +0000 | [diff] [blame] | 722 | return removeIntervalIfEmpty(li, li_, tri_); |
Evan Cheng | ecb2a8b | 2008-03-05 22:09:42 +0000 | [diff] [blame] | 723 | } |
| 724 | |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 725 | /// CanCoalesceWithImpDef - Returns true if the specified copy instruction |
| 726 | /// from an implicit def to another register can be coalesced away. |
| 727 | bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI, |
| 728 | LiveInterval &li, |
| 729 | LiveInterval &ImpLi) const{ |
| 730 | if (!CopyMI->killsRegister(ImpLi.reg)) |
| 731 | return false; |
| 732 | unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI)); |
| 733 | LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx); |
| 734 | if (LR == li.end()) |
| 735 | return false; |
| 736 | if (LR->valno->hasPHIKill) |
| 737 | return false; |
| 738 | if (LR->valno->def != CopyIdx) |
| 739 | return false; |
| 740 | // Make sure all of val# uses are copies. |
| 741 | for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(li.reg), |
| 742 | UE = mri_->use_end(); UI != UE;) { |
| 743 | MachineInstr *UseMI = &*UI; |
| 744 | ++UI; |
| 745 | if (JoinedCopies.count(UseMI)) |
| 746 | continue; |
| 747 | unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI)); |
| 748 | LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx); |
Evan Cheng | ff7a3e5 | 2008-04-16 18:48:43 +0000 | [diff] [blame] | 749 | if (ULR == li.end() || ULR->valno != LR->valno) |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 750 | continue; |
| 751 | // If the use is not a use, then it's not safe to coalesce the move. |
| 752 | unsigned SrcReg, DstReg; |
| 753 | if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg)) { |
| 754 | if (UseMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG && |
| 755 | UseMI->getOperand(1).getReg() == li.reg) |
| 756 | continue; |
| 757 | return false; |
| 758 | } |
| 759 | } |
| 760 | return true; |
| 761 | } |
| 762 | |
| 763 | |
| 764 | /// RemoveCopiesFromValNo - The specified value# is defined by an implicit |
| 765 | /// def and it is being removed. Turn all copies from this value# into |
| 766 | /// identity copies so they will be removed. |
| 767 | void SimpleRegisterCoalescing::RemoveCopiesFromValNo(LiveInterval &li, |
| 768 | VNInfo *VNI) { |
Evan Cheng | d77d4f9 | 2008-05-28 17:40:10 +0000 | [diff] [blame] | 769 | SmallVector<MachineInstr*, 4> ImpDefs; |
Evan Cheng | d2012d0 | 2008-04-10 23:48:35 +0000 | [diff] [blame] | 770 | MachineOperand *LastUse = NULL; |
| 771 | unsigned LastUseIdx = li_->getUseIndex(VNI->def); |
| 772 | for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg), |
| 773 | RE = mri_->reg_end(); RI != RE;) { |
| 774 | MachineOperand *MO = &RI.getOperand(); |
| 775 | MachineInstr *MI = &*RI; |
| 776 | ++RI; |
| 777 | if (MO->isDef()) { |
| 778 | if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) { |
Evan Cheng | d77d4f9 | 2008-05-28 17:40:10 +0000 | [diff] [blame] | 779 | ImpDefs.push_back(MI); |
Evan Cheng | d2012d0 | 2008-04-10 23:48:35 +0000 | [diff] [blame] | 780 | } |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 781 | continue; |
Evan Cheng | d2012d0 | 2008-04-10 23:48:35 +0000 | [diff] [blame] | 782 | } |
| 783 | if (JoinedCopies.count(MI)) |
| 784 | continue; |
| 785 | unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(MI)); |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 786 | LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx); |
Evan Cheng | ff7a3e5 | 2008-04-16 18:48:43 +0000 | [diff] [blame] | 787 | if (ULR == li.end() || ULR->valno != VNI) |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 788 | continue; |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 789 | // If the use is a copy, turn it into an identity copy. |
| 790 | unsigned SrcReg, DstReg; |
Evan Cheng | d2012d0 | 2008-04-10 23:48:35 +0000 | [diff] [blame] | 791 | if (tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == li.reg) { |
| 792 | // Each use MI may have multiple uses of this register. Change them all. |
| 793 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { |
| 794 | MachineOperand &MO = MI->getOperand(i); |
| 795 | if (MO.isReg() && MO.getReg() == li.reg) |
| 796 | MO.setReg(DstReg); |
| 797 | } |
| 798 | JoinedCopies.insert(MI); |
| 799 | } else if (UseIdx > LastUseIdx) { |
| 800 | LastUseIdx = UseIdx; |
| 801 | LastUse = MO; |
Evan Cheng | 172b70c | 2008-04-10 18:38:47 +0000 | [diff] [blame] | 802 | } |
Evan Cheng | d2012d0 | 2008-04-10 23:48:35 +0000 | [diff] [blame] | 803 | } |
| 804 | if (LastUse) |
| 805 | LastUse->setIsKill(); |
| 806 | else { |
Evan Cheng | d77d4f9 | 2008-05-28 17:40:10 +0000 | [diff] [blame] | 807 | // Remove dead implicit_def's. |
| 808 | while (!ImpDefs.empty()) { |
| 809 | MachineInstr *ImpDef = ImpDefs.back(); |
| 810 | ImpDefs.pop_back(); |
| 811 | li_->RemoveMachineInstrFromMaps(ImpDef); |
| 812 | ImpDef->eraseFromParent(); |
| 813 | } |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 814 | } |
| 815 | } |
| 816 | |
| 817 | static unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, |
| 818 | const TargetRegisterClass *RC, |
| 819 | const TargetRegisterInfo* TRI) { |
| 820 | for (const unsigned *SRs = TRI->getSuperRegisters(Reg); |
| 821 | unsigned SR = *SRs; ++SRs) |
| 822 | if (Reg == TRI->getSubReg(SR, SubIdx) && RC->contains(SR)) |
| 823 | return SR; |
| 824 | return 0; |
| 825 | } |
| 826 | |
Evan Cheng | e00f5de | 2008-06-19 01:39:21 +0000 | [diff] [blame] | 827 | /// isProfitableToCoalesceToSubRC - Given that register class of DstReg is |
| 828 | /// a subset of the register class of SrcReg, return true if it's profitable |
| 829 | /// to coalesce the two registers. |
| 830 | bool |
| 831 | SimpleRegisterCoalescing::isProfitableToCoalesceToSubRC(unsigned SrcReg, |
| 832 | unsigned DstReg, |
| 833 | MachineBasicBlock *MBB){ |
| 834 | if (!CrossClassJoin) |
| 835 | return false; |
| 836 | |
| 837 | // First let's make sure all uses are in the same MBB. |
| 838 | for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(SrcReg), |
| 839 | RE = mri_->reg_end(); RI != RE; ++RI) { |
| 840 | MachineInstr &MI = *RI; |
| 841 | if (MI.getParent() != MBB) |
| 842 | return false; |
| 843 | } |
| 844 | for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(DstReg), |
| 845 | RE = mri_->reg_end(); RI != RE; ++RI) { |
| 846 | MachineInstr &MI = *RI; |
| 847 | if (MI.getParent() != MBB) |
| 848 | return false; |
| 849 | } |
| 850 | |
| 851 | // Then make sure the intervals are *short*. |
| 852 | LiveInterval &SrcInt = li_->getInterval(SrcReg); |
| 853 | LiveInterval &DstInt = li_->getInterval(DstReg); |
Owen Anderson | a1566f2 | 2008-07-22 22:46:49 +0000 | [diff] [blame] | 854 | unsigned SrcSize = li_->getApproximateInstructionCount(SrcInt); |
| 855 | unsigned DstSize = li_->getApproximateInstructionCount(DstInt); |
Evan Cheng | e00f5de | 2008-06-19 01:39:21 +0000 | [diff] [blame] | 856 | const TargetRegisterClass *RC = mri_->getRegClass(DstReg); |
| 857 | unsigned Threshold = allocatableRCRegs_[RC].count() * 2; |
| 858 | return (SrcSize + DstSize) <= Threshold; |
| 859 | } |
| 860 | |
| 861 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 862 | /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, |
| 863 | /// which are the src/dst of the copy instruction CopyMI. This returns true |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 864 | /// if the copy was successfully coalesced away. If it is not currently |
| 865 | /// possible to coalesce this interval, but it may be possible if other |
| 866 | /// things get coalesced, then it returns true by reference in 'Again'. |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 867 | bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) { |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 868 | MachineInstr *CopyMI = TheCopy.MI; |
| 869 | |
| 870 | Again = false; |
| 871 | if (JoinedCopies.count(CopyMI)) |
| 872 | return false; // Already done. |
| 873 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 874 | DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI; |
| 875 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 876 | unsigned SrcReg; |
| 877 | unsigned DstReg; |
| 878 | bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG; |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 879 | bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 880 | unsigned SubIdx = 0; |
| 881 | if (isExtSubReg) { |
| 882 | DstReg = CopyMI->getOperand(0).getReg(); |
| 883 | SrcReg = CopyMI->getOperand(1).getReg(); |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 884 | } else if (isInsSubReg) { |
| 885 | if (CopyMI->getOperand(2).getSubReg()) { |
| 886 | DOUT << "\tSource of insert_subreg is already coalesced " |
| 887 | << "to another register.\n"; |
| 888 | return false; // Not coalescable. |
| 889 | } |
| 890 | DstReg = CopyMI->getOperand(0).getReg(); |
| 891 | SrcReg = CopyMI->getOperand(2).getReg(); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 892 | } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) { |
| 893 | assert(0 && "Unrecognized copy instruction!"); |
| 894 | return false; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 895 | } |
| 896 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 897 | // If they are already joined we continue. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 898 | if (SrcReg == DstReg) { |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 899 | DOUT << "\tCopy already coalesced.\n"; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 900 | return false; // Not coalescable. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 901 | } |
| 902 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 903 | bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); |
| 904 | bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 905 | |
| 906 | // If they are both physical registers, we cannot join them. |
| 907 | if (SrcIsPhys && DstIsPhys) { |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 908 | DOUT << "\tCan not coalesce physregs.\n"; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 909 | return false; // Not coalescable. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 910 | } |
| 911 | |
| 912 | // We only join virtual registers with allocatable physical registers. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 913 | if (SrcIsPhys && !allocatableRegs_[SrcReg]) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 914 | DOUT << "\tSrc reg is unallocatable physreg.\n"; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 915 | return false; // Not coalescable. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 916 | } |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 917 | if (DstIsPhys && !allocatableRegs_[DstReg]) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 918 | DOUT << "\tDst reg is unallocatable physreg.\n"; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 919 | return false; // Not coalescable. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 920 | } |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 921 | |
Evan Cheng | e00f5de | 2008-06-19 01:39:21 +0000 | [diff] [blame] | 922 | // Should be non-null only when coalescing to a sub-register class. |
| 923 | const TargetRegisterClass *SubRC = NULL; |
| 924 | MachineBasicBlock *CopyMBB = CopyMI->getParent(); |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 925 | unsigned RealDstReg = 0; |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 926 | unsigned RealSrcReg = 0; |
| 927 | if (isExtSubReg || isInsSubReg) { |
| 928 | SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm(); |
| 929 | if (SrcIsPhys && isExtSubReg) { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 930 | // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be |
| 931 | // coalesced with AX. |
Evan Cheng | 621d157 | 2008-04-17 00:06:42 +0000 | [diff] [blame] | 932 | unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg(); |
Evan Cheng | 639f493 | 2008-04-17 07:58:04 +0000 | [diff] [blame] | 933 | if (DstSubIdx) { |
| 934 | // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been |
| 935 | // coalesced to a larger register so the subreg indices cancel out. |
| 936 | if (DstSubIdx != SubIdx) { |
| 937 | DOUT << "\t Sub-register indices mismatch.\n"; |
| 938 | return false; // Not coalescable. |
| 939 | } |
| 940 | } else |
Evan Cheng | 621d157 | 2008-04-17 00:06:42 +0000 | [diff] [blame] | 941 | SrcReg = tri_->getSubReg(SrcReg, SubIdx); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 942 | SubIdx = 0; |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 943 | } else if (DstIsPhys && isInsSubReg) { |
| 944 | // EAX = INSERT_SUBREG EAX, r1024, 0 |
Evan Cheng | 621d157 | 2008-04-17 00:06:42 +0000 | [diff] [blame] | 945 | unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg(); |
Evan Cheng | 639f493 | 2008-04-17 07:58:04 +0000 | [diff] [blame] | 946 | if (SrcSubIdx) { |
| 947 | // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been |
| 948 | // coalesced to a larger register so the subreg indices cancel out. |
| 949 | if (SrcSubIdx != SubIdx) { |
| 950 | DOUT << "\t Sub-register indices mismatch.\n"; |
| 951 | return false; // Not coalescable. |
| 952 | } |
| 953 | } else |
| 954 | DstReg = tri_->getSubReg(DstReg, SubIdx); |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 955 | SubIdx = 0; |
| 956 | } else if ((DstIsPhys && isExtSubReg) || (SrcIsPhys && isInsSubReg)) { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 957 | // If this is a extract_subreg where dst is a physical register, e.g. |
| 958 | // cl = EXTRACT_SUBREG reg1024, 1 |
| 959 | // then create and update the actual physical register allocated to RHS. |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 960 | // Ditto for |
| 961 | // reg1024 = INSERT_SUBREG r1024, cl, 1 |
Evan Cheng | 639f493 | 2008-04-17 07:58:04 +0000 | [diff] [blame] | 962 | if (CopyMI->getOperand(1).getSubReg()) { |
| 963 | DOUT << "\tSrc of extract_ / insert_subreg already coalesced with reg" |
| 964 | << " of a super-class.\n"; |
| 965 | return false; // Not coalescable. |
| 966 | } |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 967 | const TargetRegisterClass *RC = |
| 968 | mri_->getRegClass(isExtSubReg ? SrcReg : DstReg); |
| 969 | if (isExtSubReg) { |
| 970 | RealDstReg = getMatchingSuperReg(DstReg, SubIdx, RC, tri_); |
| 971 | assert(RealDstReg && "Invalid extra_subreg instruction!"); |
| 972 | } else { |
| 973 | RealSrcReg = getMatchingSuperReg(SrcReg, SubIdx, RC, tri_); |
| 974 | assert(RealSrcReg && "Invalid extra_subreg instruction!"); |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 975 | } |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 976 | |
| 977 | // For this type of EXTRACT_SUBREG, conservatively |
| 978 | // check if the live interval of the source register interfere with the |
| 979 | // actual super physical register we are trying to coalesce with. |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 980 | unsigned PhysReg = isExtSubReg ? RealDstReg : RealSrcReg; |
| 981 | LiveInterval &RHS = li_->getInterval(isExtSubReg ? SrcReg : DstReg); |
| 982 | if (li_->hasInterval(PhysReg) && |
| 983 | RHS.overlaps(li_->getInterval(PhysReg))) { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 984 | DOUT << "Interfere with register "; |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 985 | DEBUG(li_->getInterval(PhysReg).print(DOUT, tri_)); |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 986 | return false; // Not coalescable |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 987 | } |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 988 | for (const unsigned* SR = tri_->getSubRegisters(PhysReg); *SR; ++SR) |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 989 | if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) { |
| 990 | DOUT << "Interfere with sub-register "; |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 991 | DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 992 | return false; // Not coalescable |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 993 | } |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 994 | SubIdx = 0; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 995 | } else { |
Evan Cheng | 639f493 | 2008-04-17 07:58:04 +0000 | [diff] [blame] | 996 | unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg() |
| 997 | : CopyMI->getOperand(2).getSubReg(); |
| 998 | if (OldSubIdx) { |
Evan Cheng | e00f5de | 2008-06-19 01:39:21 +0000 | [diff] [blame] | 999 | if (OldSubIdx == SubIdx && |
| 1000 | !differingRegisterClasses(SrcReg, DstReg, SubRC)) |
Evan Cheng | 639f493 | 2008-04-17 07:58:04 +0000 | [diff] [blame] | 1001 | // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been |
| 1002 | // coalesced to a larger register so the subreg indices cancel out. |
Evan Cheng | 8509fcf | 2008-04-29 01:41:44 +0000 | [diff] [blame] | 1003 | // Also check if the other larger register is of the same register |
| 1004 | // class as the would be resulting register. |
Evan Cheng | 639f493 | 2008-04-17 07:58:04 +0000 | [diff] [blame] | 1005 | SubIdx = 0; |
| 1006 | else { |
| 1007 | DOUT << "\t Sub-register indices mismatch.\n"; |
| 1008 | return false; // Not coalescable. |
| 1009 | } |
| 1010 | } |
| 1011 | if (SubIdx) { |
| 1012 | unsigned LargeReg = isExtSubReg ? SrcReg : DstReg; |
| 1013 | unsigned SmallReg = isExtSubReg ? DstReg : SrcReg; |
Owen Anderson | a1566f2 | 2008-07-22 22:46:49 +0000 | [diff] [blame] | 1014 | unsigned LargeRegSize = |
| 1015 | li_->getApproximateInstructionCount(li_->getInterval(LargeReg)); |
| 1016 | unsigned SmallRegSize = |
| 1017 | li_->getApproximateInstructionCount(li_->getInterval(SmallReg)); |
Evan Cheng | 639f493 | 2008-04-17 07:58:04 +0000 | [diff] [blame] | 1018 | const TargetRegisterClass *RC = mri_->getRegClass(SmallReg); |
| 1019 | unsigned Threshold = allocatableRCRegs_[RC].count(); |
| 1020 | // Be conservative. If both sides are virtual registers, do not coalesce |
| 1021 | // if this will cause a high use density interval to target a smaller |
| 1022 | // set of registers. |
| 1023 | if (SmallRegSize > Threshold || LargeRegSize > Threshold) { |
Owen Anderson | dbb8137 | 2008-05-30 22:37:27 +0000 | [diff] [blame] | 1024 | if ((float)std::distance(mri_->use_begin(SmallReg), |
| 1025 | mri_->use_end()) / SmallRegSize < |
| 1026 | (float)std::distance(mri_->use_begin(LargeReg), |
| 1027 | mri_->use_end()) / LargeRegSize) { |
Evan Cheng | 639f493 | 2008-04-17 07:58:04 +0000 | [diff] [blame] | 1028 | Again = true; // May be possible to coalesce later. |
| 1029 | return false; |
| 1030 | } |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1031 | } |
| 1032 | } |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1033 | } |
Evan Cheng | e00f5de | 2008-06-19 01:39:21 +0000 | [diff] [blame] | 1034 | } else if (differingRegisterClasses(SrcReg, DstReg, SubRC)) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1035 | // FIXME: What if the resul of a EXTRACT_SUBREG is then coalesced |
| 1036 | // with another? If it's the resulting destination register, then |
| 1037 | // the subidx must be propagated to uses (but only those defined |
| 1038 | // by the EXTRACT_SUBREG). If it's being coalesced into another |
| 1039 | // register, it should be safe because register is assumed to have |
| 1040 | // the register class of the super-register. |
| 1041 | |
Evan Cheng | e00f5de | 2008-06-19 01:39:21 +0000 | [diff] [blame] | 1042 | if (!SubRC || !isProfitableToCoalesceToSubRC(SrcReg, DstReg, CopyMBB)) { |
| 1043 | // If they are not of the same register class, we cannot join them. |
| 1044 | DOUT << "\tSrc/Dest are different register classes.\n"; |
| 1045 | // Allow the coalescer to try again in case either side gets coalesced to |
| 1046 | // a physical register that's compatible with the other side. e.g. |
| 1047 | // r1024 = MOV32to32_ r1025 |
| 1048 | // but later r1024 is assigned EAX then r1025 may be coalesced with EAX. |
| 1049 | Again = true; // May be possible to coalesce later. |
| 1050 | return false; |
| 1051 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1052 | } |
| 1053 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1054 | LiveInterval &SrcInt = li_->getInterval(SrcReg); |
| 1055 | LiveInterval &DstInt = li_->getInterval(DstReg); |
| 1056 | assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg && |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1057 | "Register mapping is horribly broken!"); |
| 1058 | |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1059 | DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_); |
| 1060 | DOUT << " and "; DstInt.print(DOUT, tri_); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1061 | DOUT << ": "; |
| 1062 | |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 1063 | // Check if it is necessary to propagate "isDead" property. |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1064 | if (!isExtSubReg && !isInsSubReg) { |
| 1065 | MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false); |
| 1066 | bool isDead = mopd->isDead(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1067 | |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1068 | // We need to be careful about coalescing a source physical register with a |
| 1069 | // virtual register. Once the coalescing is done, it cannot be broken and |
| 1070 | // these are not spillable! If the destination interval uses are far away, |
| 1071 | // think twice about coalescing them! |
| 1072 | if (!isDead && (SrcIsPhys || DstIsPhys)) { |
| 1073 | LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt; |
| 1074 | unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg; |
| 1075 | unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg; |
| 1076 | const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg); |
| 1077 | unsigned Threshold = allocatableRCRegs_[RC].count() * 2; |
| 1078 | if (TheCopy.isBackEdge) |
| 1079 | Threshold *= 2; // Favors back edge copies. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1080 | |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1081 | // If the virtual register live interval is long but it has low use desity, |
| 1082 | // do not join them, instead mark the physical register as its allocation |
| 1083 | // preference. |
Owen Anderson | a1566f2 | 2008-07-22 22:46:49 +0000 | [diff] [blame] | 1084 | unsigned Length = li_->getApproximateInstructionCount(JoinVInt); |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1085 | if (Length > Threshold && |
Owen Anderson | dbb8137 | 2008-05-30 22:37:27 +0000 | [diff] [blame] | 1086 | (((float)std::distance(mri_->use_begin(JoinVReg), |
| 1087 | mri_->use_end()) / Length) < (1.0 / Threshold))) { |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1088 | JoinVInt.preference = JoinPReg; |
| 1089 | ++numAborts; |
| 1090 | DOUT << "\tMay tie down a physical register, abort!\n"; |
| 1091 | Again = true; // May be possible to coalesce later. |
| 1092 | return false; |
| 1093 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1094 | } |
| 1095 | } |
| 1096 | |
| 1097 | // Okay, attempt to join these two intervals. On failure, this returns false. |
| 1098 | // Otherwise, if one of the intervals being joined is a physreg, this method |
| 1099 | // always canonicalizes DstInt to be it. The output "SrcInt" will not have |
| 1100 | // been modified, so we can use this information below to update aliases. |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 1101 | bool Swapped = false; |
Evan Cheng | db9b1c3 | 2008-04-03 16:41:54 +0000 | [diff] [blame] | 1102 | // If SrcInt is implicitly defined, it's safe to coalesce. |
| 1103 | bool isEmpty = SrcInt.empty(); |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1104 | if (isEmpty && !CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) { |
Evan Cheng | db9b1c3 | 2008-04-03 16:41:54 +0000 | [diff] [blame] | 1105 | // Only coalesce an empty interval (defined by implicit_def) with |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1106 | // another interval which has a valno defined by the CopyMI and the CopyMI |
| 1107 | // is a kill of the implicit def. |
Evan Cheng | db9b1c3 | 2008-04-03 16:41:54 +0000 | [diff] [blame] | 1108 | DOUT << "Not profitable!\n"; |
| 1109 | return false; |
| 1110 | } |
| 1111 | |
| 1112 | if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) { |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1113 | // Coalescing failed. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1114 | |
| 1115 | // If we can eliminate the copy without merging the live ranges, do so now. |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1116 | if (!isExtSubReg && !isInsSubReg && |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 1117 | (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) || |
| 1118 | RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) { |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1119 | JoinedCopies.insert(CopyMI); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1120 | return true; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1121 | } |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 1122 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1123 | // Otherwise, we are unable to join the intervals. |
| 1124 | DOUT << "Interference!\n"; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1125 | Again = true; // May be possible to coalesce later. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1126 | return false; |
| 1127 | } |
| 1128 | |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 1129 | LiveInterval *ResSrcInt = &SrcInt; |
| 1130 | LiveInterval *ResDstInt = &DstInt; |
| 1131 | if (Swapped) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1132 | std::swap(SrcReg, DstReg); |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 1133 | std::swap(ResSrcInt, ResDstInt); |
| 1134 | } |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1135 | assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1136 | "LiveInterval::join didn't work right!"); |
| 1137 | |
| 1138 | // If we're about to merge live ranges into a physical register live range, |
| 1139 | // we have to update any aliased register's live ranges to indicate that they |
| 1140 | // have clobbered values for this range. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1141 | if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1142 | // If this is a extract_subreg where dst is a physical register, e.g. |
| 1143 | // cl = EXTRACT_SUBREG reg1024, 1 |
| 1144 | // then create and update the actual physical register allocated to RHS. |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1145 | if (RealDstReg || RealSrcReg) { |
| 1146 | LiveInterval &RealInt = |
| 1147 | li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg); |
Evan Cheng | f5c7359 | 2007-10-15 18:33:50 +0000 | [diff] [blame] | 1148 | SmallSet<const VNInfo*, 4> CopiedValNos; |
| 1149 | for (LiveInterval::Ranges::const_iterator I = ResSrcInt->ranges.begin(), |
| 1150 | E = ResSrcInt->ranges.end(); I != E; ++I) { |
Evan Cheng | ff7a3e5 | 2008-04-16 18:48:43 +0000 | [diff] [blame] | 1151 | const LiveRange *DstLR = ResDstInt->getLiveRangeContaining(I->start); |
| 1152 | assert(DstLR && "Invalid joined interval!"); |
Evan Cheng | f5c7359 | 2007-10-15 18:33:50 +0000 | [diff] [blame] | 1153 | const VNInfo *DstValNo = DstLR->valno; |
| 1154 | if (CopiedValNos.insert(DstValNo)) { |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1155 | VNInfo *ValNo = RealInt.getNextValue(DstValNo->def, DstValNo->copy, |
| 1156 | li_->getVNInfoAllocator()); |
Evan Cheng | c3fc7d9 | 2007-11-29 09:49:23 +0000 | [diff] [blame] | 1157 | ValNo->hasPHIKill = DstValNo->hasPHIKill; |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1158 | RealInt.addKills(ValNo, DstValNo->kills); |
| 1159 | RealInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo); |
Evan Cheng | f5c7359 | 2007-10-15 18:33:50 +0000 | [diff] [blame] | 1160 | } |
Evan Cheng | 3472925 | 2007-10-14 10:08:34 +0000 | [diff] [blame] | 1161 | } |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1162 | |
| 1163 | DstReg = RealDstReg ? RealDstReg : RealSrcReg; |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1164 | } |
| 1165 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1166 | // Update the liveintervals of sub-registers. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1167 | for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS) |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1168 | li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt, |
Evan Cheng | f3bb2e6 | 2007-09-05 21:46:51 +0000 | [diff] [blame] | 1169 | li_->getVNInfoAllocator()); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1170 | } |
| 1171 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1172 | // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the |
| 1173 | // larger super-register. |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1174 | if ((isExtSubReg || isInsSubReg) && !SrcIsPhys && !DstIsPhys) { |
| 1175 | if ((isExtSubReg && !Swapped) || (isInsSubReg && Swapped)) { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1176 | ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator()); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1177 | std::swap(SrcReg, DstReg); |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1178 | std::swap(ResSrcInt, ResDstInt); |
| 1179 | } |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1180 | } |
| 1181 | |
Evan Cheng | e00f5de | 2008-06-19 01:39:21 +0000 | [diff] [blame] | 1182 | // Coalescing to a virtual register that is of a sub-register class of the |
| 1183 | // other. Make sure the resulting register is set to the right register class. |
| 1184 | if (SubRC) { |
| 1185 | mri_->setRegClass(DstReg, SubRC); |
| 1186 | ++numSubJoins; |
| 1187 | } |
| 1188 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1189 | if (NewHeuristic) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1190 | // Add all copies that define val# in the source interval into the queue. |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1191 | for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(), |
| 1192 | e = ResSrcInt->vni_end(); i != e; ++i) { |
| 1193 | const VNInfo *vni = *i; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1194 | if (!vni->def || vni->def == ~1U || vni->def == ~0U) |
| 1195 | continue; |
| 1196 | MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def); |
| 1197 | unsigned NewSrcReg, NewDstReg; |
| 1198 | if (CopyMI && |
| 1199 | JoinedCopies.count(CopyMI) == 0 && |
| 1200 | tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg)) { |
Evan Cheng | e00f5de | 2008-06-19 01:39:21 +0000 | [diff] [blame] | 1201 | unsigned LoopDepth = loopInfo->getLoopDepth(CopyMBB); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1202 | JoinQueue->push(CopyRec(CopyMI, LoopDepth, |
| 1203 | isBackEdgeCopy(CopyMI, DstReg))); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1204 | } |
| 1205 | } |
| 1206 | } |
| 1207 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1208 | // Remember to delete the copy instruction. |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1209 | JoinedCopies.insert(CopyMI); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1210 | |
Evan Cheng | 4ff3f1c | 2008-03-10 08:11:32 +0000 | [diff] [blame] | 1211 | // Some live range has been lengthened due to colaescing, eliminate the |
| 1212 | // unnecessary kills. |
| 1213 | RemoveUnnecessaryKills(SrcReg, *ResDstInt); |
| 1214 | if (TargetRegisterInfo::isVirtualRegister(DstReg)) |
| 1215 | RemoveUnnecessaryKills(DstReg, *ResDstInt); |
| 1216 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1217 | // SrcReg is guarateed to be the register whose live interval that is |
| 1218 | // being merged. |
| 1219 | li_->removeInterval(SrcReg); |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1220 | if (isInsSubReg) |
| 1221 | // Avoid: |
| 1222 | // r1024 = op |
| 1223 | // r1024 = implicit_def |
| 1224 | // ... |
| 1225 | // = r1024 |
| 1226 | RemoveDeadImpDef(DstReg, *ResDstInt); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1227 | UpdateRegDefsUses(SrcReg, DstReg, SubIdx); |
| 1228 | |
Evan Cheng | db9b1c3 | 2008-04-03 16:41:54 +0000 | [diff] [blame] | 1229 | if (isEmpty) { |
| 1230 | // Now the copy is being coalesced away, the val# previously defined |
| 1231 | // by the copy is being defined by an IMPLICIT_DEF which defines a zero |
| 1232 | // length interval. Remove the val#. |
| 1233 | unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI)); |
Evan Cheng | ff7a3e5 | 2008-04-16 18:48:43 +0000 | [diff] [blame] | 1234 | const LiveRange *LR = ResDstInt->getLiveRangeContaining(CopyIdx); |
Evan Cheng | db9b1c3 | 2008-04-03 16:41:54 +0000 | [diff] [blame] | 1235 | VNInfo *ImpVal = LR->valno; |
| 1236 | assert(ImpVal->def == CopyIdx); |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1237 | unsigned NextDef = LR->end; |
| 1238 | RemoveCopiesFromValNo(*ResDstInt, ImpVal); |
Evan Cheng | db9b1c3 | 2008-04-03 16:41:54 +0000 | [diff] [blame] | 1239 | ResDstInt->removeValNo(ImpVal); |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1240 | LR = ResDstInt->FindLiveRangeContaining(NextDef); |
| 1241 | if (LR != ResDstInt->end() && LR->valno->def == NextDef) { |
| 1242 | // Special case: vr1024 = implicit_def |
| 1243 | // vr1024 = insert_subreg vr1024, vr1025, c |
| 1244 | // The insert_subreg becomes a "copy" that defines a val# which can itself |
| 1245 | // be coalesced away. |
| 1246 | MachineInstr *DefMI = li_->getInstructionFromIndex(NextDef); |
| 1247 | if (DefMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) |
| 1248 | LR->valno->copy = DefMI; |
| 1249 | } |
Evan Cheng | db9b1c3 | 2008-04-03 16:41:54 +0000 | [diff] [blame] | 1250 | } |
| 1251 | |
| 1252 | DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_); |
| 1253 | DOUT << "\n"; |
| 1254 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1255 | ++numJoins; |
| 1256 | return true; |
| 1257 | } |
| 1258 | |
| 1259 | /// ComputeUltimateVN - Assuming we are going to join two live intervals, |
| 1260 | /// compute what the resultant value numbers for each value in the input two |
| 1261 | /// ranges will be. This is complicated by copies between the two which can |
| 1262 | /// and will commonly cause multiple value numbers to be merged into one. |
| 1263 | /// |
| 1264 | /// VN is the value number that we're trying to resolve. InstDefiningValue |
| 1265 | /// keeps track of the new InstDefiningValue assignment for the result |
| 1266 | /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of |
| 1267 | /// whether a value in this or other is a copy from the opposite set. |
| 1268 | /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have |
| 1269 | /// already been assigned. |
| 1270 | /// |
| 1271 | /// ThisFromOther[x] - If x is defined as a copy from the other interval, this |
| 1272 | /// contains the value number the copy is from. |
| 1273 | /// |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1274 | static unsigned ComputeUltimateVN(VNInfo *VNI, |
| 1275 | SmallVector<VNInfo*, 16> &NewVNInfo, |
Evan Cheng | fadfb5b | 2007-08-31 21:23:06 +0000 | [diff] [blame] | 1276 | DenseMap<VNInfo*, VNInfo*> &ThisFromOther, |
| 1277 | DenseMap<VNInfo*, VNInfo*> &OtherFromThis, |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1278 | SmallVector<int, 16> &ThisValNoAssignments, |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1279 | SmallVector<int, 16> &OtherValNoAssignments) { |
| 1280 | unsigned VN = VNI->id; |
| 1281 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1282 | // If the VN has already been computed, just return it. |
| 1283 | if (ThisValNoAssignments[VN] >= 0) |
| 1284 | return ThisValNoAssignments[VN]; |
| 1285 | // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?"); |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1286 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1287 | // If this val is not a copy from the other val, then it must be a new value |
| 1288 | // number in the destination. |
Evan Cheng | fadfb5b | 2007-08-31 21:23:06 +0000 | [diff] [blame] | 1289 | DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI); |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 1290 | if (I == ThisFromOther.end()) { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1291 | NewVNInfo.push_back(VNI); |
| 1292 | return ThisValNoAssignments[VN] = NewVNInfo.size()-1; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1293 | } |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 1294 | VNInfo *OtherValNo = I->second; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1295 | |
| 1296 | // Otherwise, this *is* a copy from the RHS. If the other side has already |
| 1297 | // been computed, return it. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1298 | if (OtherValNoAssignments[OtherValNo->id] >= 0) |
| 1299 | return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id]; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1300 | |
| 1301 | // Mark this value number as currently being computed, then ask what the |
| 1302 | // ultimate value # of the other value is. |
| 1303 | ThisValNoAssignments[VN] = -2; |
| 1304 | unsigned UltimateVN = |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1305 | ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther, |
| 1306 | OtherValNoAssignments, ThisValNoAssignments); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1307 | return ThisValNoAssignments[VN] = UltimateVN; |
| 1308 | } |
| 1309 | |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1310 | static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1311 | return std::find(V.begin(), V.end(), Val) != V.end(); |
| 1312 | } |
| 1313 | |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1314 | /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of |
| 1315 | /// the specified live interval is defined by a copy from the specified |
| 1316 | /// register. |
| 1317 | bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li, |
| 1318 | LiveRange *LR, |
| 1319 | unsigned Reg) { |
| 1320 | unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno); |
| 1321 | if (SrcReg == Reg) |
| 1322 | return true; |
| 1323 | if (LR->valno->def == ~0U && |
| 1324 | TargetRegisterInfo::isPhysicalRegister(li.reg) && |
| 1325 | *tri_->getSuperRegisters(li.reg)) { |
| 1326 | // It's a sub-register live interval, we may not have precise information. |
| 1327 | // Re-compute it. |
| 1328 | MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start); |
| 1329 | unsigned SrcReg, DstReg; |
Evan Cheng | 76a4d58 | 2008-07-17 19:48:53 +0000 | [diff] [blame] | 1330 | if (DefMI && tii_->isMoveInstr(*DefMI, SrcReg, DstReg) && |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1331 | DstReg == li.reg && SrcReg == Reg) { |
| 1332 | // Cache computed info. |
| 1333 | LR->valno->def = LR->start; |
| 1334 | LR->valno->copy = DefMI; |
| 1335 | return true; |
| 1336 | } |
| 1337 | } |
| 1338 | return false; |
| 1339 | } |
| 1340 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1341 | /// SimpleJoin - Attempt to joint the specified interval into this one. The |
| 1342 | /// caller of this method must guarantee that the RHS only contains a single |
| 1343 | /// value number and that the RHS is not defined by a copy from this |
| 1344 | /// interval. This returns false if the intervals are not joinable, or it |
| 1345 | /// joins them and returns true. |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 1346 | bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){ |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1347 | assert(RHS.containsOneValue()); |
| 1348 | |
| 1349 | // Some number (potentially more than one) value numbers in the current |
| 1350 | // interval may be defined as copies from the RHS. Scan the overlapping |
| 1351 | // portions of the LHS and RHS, keeping track of this and looking for |
| 1352 | // overlapping live ranges that are NOT defined as copies. If these exist, we |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1353 | // cannot coalesce. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1354 | |
| 1355 | LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end(); |
| 1356 | LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end(); |
| 1357 | |
| 1358 | if (LHSIt->start < RHSIt->start) { |
| 1359 | LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start); |
| 1360 | if (LHSIt != LHS.begin()) --LHSIt; |
| 1361 | } else if (RHSIt->start < LHSIt->start) { |
| 1362 | RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start); |
| 1363 | if (RHSIt != RHS.begin()) --RHSIt; |
| 1364 | } |
| 1365 | |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1366 | SmallVector<VNInfo*, 8> EliminatedLHSVals; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1367 | |
| 1368 | while (1) { |
| 1369 | // Determine if these live intervals overlap. |
| 1370 | bool Overlaps = false; |
| 1371 | if (LHSIt->start <= RHSIt->start) |
| 1372 | Overlaps = LHSIt->end > RHSIt->start; |
| 1373 | else |
| 1374 | Overlaps = RHSIt->end > LHSIt->start; |
| 1375 | |
| 1376 | // If the live intervals overlap, there are two interesting cases: if the |
| 1377 | // LHS interval is defined by a copy from the RHS, it's ok and we record |
| 1378 | // that the LHS value # is the same as the RHS. If it's not, then we cannot |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1379 | // coalesce these live ranges and we bail out. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1380 | if (Overlaps) { |
| 1381 | // If we haven't already recorded that this value # is safe, check it. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1382 | if (!InVector(LHSIt->valno, EliminatedLHSVals)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1383 | // Copy from the RHS? |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1384 | if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1385 | return false; // Nope, bail out. |
Evan Cheng | f4ea510 | 2008-05-21 22:34:12 +0000 | [diff] [blame] | 1386 | |
| 1387 | if (LHSIt->contains(RHSIt->valno->def)) |
| 1388 | // Here is an interesting situation: |
| 1389 | // BB1: |
| 1390 | // vr1025 = copy vr1024 |
| 1391 | // .. |
| 1392 | // BB2: |
| 1393 | // vr1024 = op |
| 1394 | // = vr1025 |
| 1395 | // Even though vr1025 is copied from vr1024, it's not safe to |
| 1396 | // coalesced them since live range of vr1025 intersects the |
| 1397 | // def of vr1024. This happens because vr1025 is assigned the |
| 1398 | // value of the previous iteration of vr1024. |
| 1399 | return false; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1400 | EliminatedLHSVals.push_back(LHSIt->valno); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1401 | } |
| 1402 | |
| 1403 | // We know this entire LHS live range is okay, so skip it now. |
| 1404 | if (++LHSIt == LHSEnd) break; |
| 1405 | continue; |
| 1406 | } |
| 1407 | |
| 1408 | if (LHSIt->end < RHSIt->end) { |
| 1409 | if (++LHSIt == LHSEnd) break; |
| 1410 | } else { |
| 1411 | // One interesting case to check here. It's possible that we have |
| 1412 | // something like "X3 = Y" which defines a new value number in the LHS, |
| 1413 | // and is the last use of this liverange of the RHS. In this case, we |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1414 | // want to notice this copy (so that it gets coalesced away) even though |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1415 | // the live ranges don't actually overlap. |
| 1416 | if (LHSIt->start == RHSIt->end) { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1417 | if (InVector(LHSIt->valno, EliminatedLHSVals)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1418 | // We already know that this value number is going to be merged in |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1419 | // if coalescing succeeds. Just skip the liverange. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1420 | if (++LHSIt == LHSEnd) break; |
| 1421 | } else { |
| 1422 | // Otherwise, if this is a copy from the RHS, mark it as being merged |
| 1423 | // in. |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1424 | if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) { |
Evan Cheng | f4ea510 | 2008-05-21 22:34:12 +0000 | [diff] [blame] | 1425 | if (LHSIt->contains(RHSIt->valno->def)) |
| 1426 | // Here is an interesting situation: |
| 1427 | // BB1: |
| 1428 | // vr1025 = copy vr1024 |
| 1429 | // .. |
| 1430 | // BB2: |
| 1431 | // vr1024 = op |
| 1432 | // = vr1025 |
| 1433 | // Even though vr1025 is copied from vr1024, it's not safe to |
| 1434 | // coalesced them since live range of vr1025 intersects the |
| 1435 | // def of vr1024. This happens because vr1025 is assigned the |
| 1436 | // value of the previous iteration of vr1024. |
| 1437 | return false; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1438 | EliminatedLHSVals.push_back(LHSIt->valno); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1439 | |
| 1440 | // We know this entire LHS live range is okay, so skip it now. |
| 1441 | if (++LHSIt == LHSEnd) break; |
| 1442 | } |
| 1443 | } |
| 1444 | } |
| 1445 | |
| 1446 | if (++RHSIt == RHSEnd) break; |
| 1447 | } |
| 1448 | } |
| 1449 | |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1450 | // If we got here, we know that the coalescing will be successful and that |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1451 | // the value numbers in EliminatedLHSVals will all be merged together. Since |
| 1452 | // the most common case is that EliminatedLHSVals has a single number, we |
| 1453 | // optimize for it: if there is more than one value, we merge them all into |
| 1454 | // the lowest numbered one, then handle the interval as if we were merging |
| 1455 | // with one value number. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1456 | VNInfo *LHSValNo; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1457 | if (EliminatedLHSVals.size() > 1) { |
| 1458 | // Loop through all the equal value numbers merging them into the smallest |
| 1459 | // one. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1460 | VNInfo *Smallest = EliminatedLHSVals[0]; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1461 | for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1462 | if (EliminatedLHSVals[i]->id < Smallest->id) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1463 | // Merge the current notion of the smallest into the smaller one. |
| 1464 | LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]); |
| 1465 | Smallest = EliminatedLHSVals[i]; |
| 1466 | } else { |
| 1467 | // Merge into the smallest. |
| 1468 | LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest); |
| 1469 | } |
| 1470 | } |
| 1471 | LHSValNo = Smallest; |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1472 | } else if (EliminatedLHSVals.empty()) { |
| 1473 | if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) && |
| 1474 | *tri_->getSuperRegisters(LHS.reg)) |
| 1475 | // Imprecise sub-register information. Can't handle it. |
| 1476 | return false; |
| 1477 | assert(0 && "No copies from the RHS?"); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1478 | } else { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1479 | LHSValNo = EliminatedLHSVals[0]; |
| 1480 | } |
| 1481 | |
| 1482 | // Okay, now that there is a single LHS value number that we're merging the |
| 1483 | // RHS into, update the value number info for the LHS to indicate that the |
| 1484 | // value number is defined where the RHS value number was. |
Evan Cheng | f3bb2e6 | 2007-09-05 21:46:51 +0000 | [diff] [blame] | 1485 | const VNInfo *VNI = RHS.getValNumInfo(0); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1486 | LHSValNo->def = VNI->def; |
| 1487 | LHSValNo->copy = VNI->copy; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1488 | |
| 1489 | // Okay, the final step is to loop over the RHS live intervals, adding them to |
| 1490 | // the LHS. |
Evan Cheng | c3fc7d9 | 2007-11-29 09:49:23 +0000 | [diff] [blame] | 1491 | LHSValNo->hasPHIKill |= VNI->hasPHIKill; |
Evan Cheng | f3bb2e6 | 2007-09-05 21:46:51 +0000 | [diff] [blame] | 1492 | LHS.addKills(LHSValNo, VNI->kills); |
Evan Cheng | 430a7b0 | 2007-08-14 01:56:58 +0000 | [diff] [blame] | 1493 | LHS.MergeRangesInAsValue(RHS, LHSValNo); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1494 | LHS.weight += RHS.weight; |
| 1495 | if (RHS.preference && !LHS.preference) |
| 1496 | LHS.preference = RHS.preference; |
| 1497 | |
| 1498 | return true; |
| 1499 | } |
| 1500 | |
| 1501 | /// JoinIntervals - Attempt to join these two intervals. On failure, this |
| 1502 | /// returns false. Otherwise, if one of the intervals being joined is a |
| 1503 | /// physreg, this method always canonicalizes LHS to be it. The output |
| 1504 | /// "RHS" will not have been modified, so we can use this information |
| 1505 | /// below to update aliases. |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 1506 | bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, |
| 1507 | LiveInterval &RHS, bool &Swapped) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1508 | // Compute the final value assignment, assuming that the live ranges can be |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1509 | // coalesced. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1510 | SmallVector<int, 16> LHSValNoAssignments; |
| 1511 | SmallVector<int, 16> RHSValNoAssignments; |
Evan Cheng | fadfb5b | 2007-08-31 21:23:06 +0000 | [diff] [blame] | 1512 | DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS; |
| 1513 | DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1514 | SmallVector<VNInfo*, 16> NewVNInfo; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1515 | |
| 1516 | // If a live interval is a physical register, conservatively check if any |
| 1517 | // of its sub-registers is overlapping the live interval of the virtual |
| 1518 | // register. If so, do not coalesce. |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1519 | if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) && |
| 1520 | *tri_->getSubRegisters(LHS.reg)) { |
| 1521 | for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1522 | if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) { |
| 1523 | DOUT << "Interfere with sub-register "; |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1524 | DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1525 | return false; |
| 1526 | } |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1527 | } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) && |
| 1528 | *tri_->getSubRegisters(RHS.reg)) { |
| 1529 | for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1530 | if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) { |
| 1531 | DOUT << "Interfere with sub-register "; |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1532 | DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1533 | return false; |
| 1534 | } |
| 1535 | } |
| 1536 | |
| 1537 | // Compute ultimate value numbers for the LHS and RHS values. |
| 1538 | if (RHS.containsOneValue()) { |
| 1539 | // Copies from a liveinterval with a single value are simple to handle and |
| 1540 | // very common, handle the special case here. This is important, because |
| 1541 | // often RHS is small and LHS is large (e.g. a physreg). |
| 1542 | |
| 1543 | // Find out if the RHS is defined as a copy from some value in the LHS. |
Evan Cheng | 4f8ff16 | 2007-08-11 00:59:19 +0000 | [diff] [blame] | 1544 | int RHSVal0DefinedFromLHS = -1; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1545 | int RHSValID = -1; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1546 | VNInfo *RHSValNoInfo = NULL; |
Evan Cheng | f3bb2e6 | 2007-09-05 21:46:51 +0000 | [diff] [blame] | 1547 | VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1548 | unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0); |
| 1549 | if ((RHSSrcReg == 0 || RHSSrcReg != LHS.reg)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1550 | // If RHS is not defined as a copy from the LHS, we can use simpler and |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1551 | // faster checks to see if the live ranges are coalescable. This joiner |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1552 | // can't swap the LHS/RHS intervals though. |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1553 | if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1554 | return SimpleJoin(LHS, RHS); |
| 1555 | } else { |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 1556 | RHSValNoInfo = RHSValNoInfo0; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1557 | } |
| 1558 | } else { |
| 1559 | // It was defined as a copy from the LHS, find out what value # it is. |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 1560 | RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1561 | RHSValID = RHSValNoInfo->id; |
Evan Cheng | 4f8ff16 | 2007-08-11 00:59:19 +0000 | [diff] [blame] | 1562 | RHSVal0DefinedFromLHS = RHSValID; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1563 | } |
| 1564 | |
| 1565 | LHSValNoAssignments.resize(LHS.getNumValNums(), -1); |
| 1566 | RHSValNoAssignments.resize(RHS.getNumValNums(), -1); |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1567 | NewVNInfo.resize(LHS.getNumValNums(), NULL); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1568 | |
| 1569 | // Okay, *all* of the values in LHS that are defined as a copy from RHS |
| 1570 | // should now get updated. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1571 | for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end(); |
| 1572 | i != e; ++i) { |
| 1573 | VNInfo *VNI = *i; |
| 1574 | unsigned VN = VNI->id; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1575 | if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) { |
| 1576 | if (LHSSrcReg != RHS.reg) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1577 | // If this is not a copy from the RHS, its value number will be |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1578 | // unmodified by the coalescing. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1579 | NewVNInfo[VN] = VNI; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1580 | LHSValNoAssignments[VN] = VN; |
| 1581 | } else if (RHSValID == -1) { |
| 1582 | // Otherwise, it is a copy from the RHS, and we don't already have a |
| 1583 | // value# for it. Keep the current value number, but remember it. |
| 1584 | LHSValNoAssignments[VN] = RHSValID = VN; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1585 | NewVNInfo[VN] = RHSValNoInfo; |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 1586 | LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1587 | } else { |
| 1588 | // Otherwise, use the specified value #. |
| 1589 | LHSValNoAssignments[VN] = RHSValID; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1590 | if (VN == (unsigned)RHSValID) { // Else this val# is dead. |
| 1591 | NewVNInfo[VN] = RHSValNoInfo; |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 1592 | LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0; |
Evan Cheng | 4f8ff16 | 2007-08-11 00:59:19 +0000 | [diff] [blame] | 1593 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1594 | } |
| 1595 | } else { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1596 | NewVNInfo[VN] = VNI; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1597 | LHSValNoAssignments[VN] = VN; |
| 1598 | } |
| 1599 | } |
| 1600 | |
| 1601 | assert(RHSValID != -1 && "Didn't find value #?"); |
| 1602 | RHSValNoAssignments[0] = RHSValID; |
Evan Cheng | 4f8ff16 | 2007-08-11 00:59:19 +0000 | [diff] [blame] | 1603 | if (RHSVal0DefinedFromLHS != -1) { |
Evan Cheng | 3430135 | 2007-09-01 02:03:17 +0000 | [diff] [blame] | 1604 | // This path doesn't go through ComputeUltimateVN so just set |
| 1605 | // it to anything. |
| 1606 | RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1; |
Evan Cheng | 4f8ff16 | 2007-08-11 00:59:19 +0000 | [diff] [blame] | 1607 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1608 | } else { |
| 1609 | // Loop over the value numbers of the LHS, seeing if any are defined from |
| 1610 | // the RHS. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1611 | for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end(); |
| 1612 | i != e; ++i) { |
| 1613 | VNInfo *VNI = *i; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1614 | if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy? |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1615 | continue; |
| 1616 | |
| 1617 | // DstReg is known to be a register in the LHS interval. If the src is |
| 1618 | // from the RHS interval, we can use its value #. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1619 | if (li_->getVNInfoSourceReg(VNI) != RHS.reg) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1620 | continue; |
| 1621 | |
| 1622 | // Figure out the value # from the RHS. |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 1623 | LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1624 | } |
| 1625 | |
| 1626 | // Loop over the value numbers of the RHS, seeing if any are defined from |
| 1627 | // the LHS. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1628 | for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end(); |
| 1629 | i != e; ++i) { |
| 1630 | VNInfo *VNI = *i; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1631 | if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy? |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1632 | continue; |
| 1633 | |
| 1634 | // DstReg is known to be a register in the RHS interval. If the src is |
| 1635 | // from the LHS interval, we can use its value #. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1636 | if (li_->getVNInfoSourceReg(VNI) != LHS.reg) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1637 | continue; |
| 1638 | |
| 1639 | // Figure out the value # from the LHS. |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 1640 | RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1641 | } |
| 1642 | |
| 1643 | LHSValNoAssignments.resize(LHS.getNumValNums(), -1); |
| 1644 | RHSValNoAssignments.resize(RHS.getNumValNums(), -1); |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1645 | NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums()); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1646 | |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1647 | for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end(); |
| 1648 | i != e; ++i) { |
| 1649 | VNInfo *VNI = *i; |
| 1650 | unsigned VN = VNI->id; |
| 1651 | if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1652 | continue; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1653 | ComputeUltimateVN(VNI, NewVNInfo, |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1654 | LHSValsDefinedFromRHS, RHSValsDefinedFromLHS, |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1655 | LHSValNoAssignments, RHSValNoAssignments); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1656 | } |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1657 | for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end(); |
| 1658 | i != e; ++i) { |
| 1659 | VNInfo *VNI = *i; |
| 1660 | unsigned VN = VNI->id; |
| 1661 | if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1662 | continue; |
| 1663 | // If this value number isn't a copy from the LHS, it's a new number. |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 1664 | if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1665 | NewVNInfo.push_back(VNI); |
| 1666 | RHSValNoAssignments[VN] = NewVNInfo.size()-1; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1667 | continue; |
| 1668 | } |
| 1669 | |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1670 | ComputeUltimateVN(VNI, NewVNInfo, |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1671 | RHSValsDefinedFromLHS, LHSValsDefinedFromRHS, |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1672 | RHSValNoAssignments, LHSValNoAssignments); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1673 | } |
| 1674 | } |
| 1675 | |
| 1676 | // Armed with the mappings of LHS/RHS values to ultimate values, walk the |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1677 | // interval lists to see if these intervals are coalescable. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1678 | LiveInterval::const_iterator I = LHS.begin(); |
| 1679 | LiveInterval::const_iterator IE = LHS.end(); |
| 1680 | LiveInterval::const_iterator J = RHS.begin(); |
| 1681 | LiveInterval::const_iterator JE = RHS.end(); |
| 1682 | |
| 1683 | // Skip ahead until the first place of potential sharing. |
| 1684 | if (I->start < J->start) { |
| 1685 | I = std::upper_bound(I, IE, J->start); |
| 1686 | if (I != LHS.begin()) --I; |
| 1687 | } else if (J->start < I->start) { |
| 1688 | J = std::upper_bound(J, JE, I->start); |
| 1689 | if (J != RHS.begin()) --J; |
| 1690 | } |
| 1691 | |
| 1692 | while (1) { |
| 1693 | // Determine if these two live ranges overlap. |
| 1694 | bool Overlaps; |
| 1695 | if (I->start < J->start) { |
| 1696 | Overlaps = I->end > J->start; |
| 1697 | } else { |
| 1698 | Overlaps = J->end > I->start; |
| 1699 | } |
| 1700 | |
| 1701 | // If so, check value # info to determine if they are really different. |
| 1702 | if (Overlaps) { |
| 1703 | // If the live range overlap will map to the same value number in the |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1704 | // result liverange, we can still coalesce them. If not, we can't. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1705 | if (LHSValNoAssignments[I->valno->id] != |
| 1706 | RHSValNoAssignments[J->valno->id]) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1707 | return false; |
| 1708 | } |
| 1709 | |
| 1710 | if (I->end < J->end) { |
| 1711 | ++I; |
| 1712 | if (I == IE) break; |
| 1713 | } else { |
| 1714 | ++J; |
| 1715 | if (J == JE) break; |
| 1716 | } |
| 1717 | } |
| 1718 | |
Evan Cheng | 3472925 | 2007-10-14 10:08:34 +0000 | [diff] [blame] | 1719 | // Update kill info. Some live ranges are extended due to copy coalescing. |
| 1720 | for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(), |
| 1721 | E = LHSValsDefinedFromRHS.end(); I != E; ++I) { |
| 1722 | VNInfo *VNI = I->first; |
| 1723 | unsigned LHSValID = LHSValNoAssignments[VNI->id]; |
| 1724 | LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def); |
Evan Cheng | c3fc7d9 | 2007-11-29 09:49:23 +0000 | [diff] [blame] | 1725 | NewVNInfo[LHSValID]->hasPHIKill |= VNI->hasPHIKill; |
Evan Cheng | 3472925 | 2007-10-14 10:08:34 +0000 | [diff] [blame] | 1726 | RHS.addKills(NewVNInfo[LHSValID], VNI->kills); |
| 1727 | } |
| 1728 | |
| 1729 | // Update kill info. Some live ranges are extended due to copy coalescing. |
| 1730 | for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(), |
| 1731 | E = RHSValsDefinedFromLHS.end(); I != E; ++I) { |
| 1732 | VNInfo *VNI = I->first; |
| 1733 | unsigned RHSValID = RHSValNoAssignments[VNI->id]; |
| 1734 | LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def); |
Evan Cheng | c3fc7d9 | 2007-11-29 09:49:23 +0000 | [diff] [blame] | 1735 | NewVNInfo[RHSValID]->hasPHIKill |= VNI->hasPHIKill; |
Evan Cheng | 3472925 | 2007-10-14 10:08:34 +0000 | [diff] [blame] | 1736 | LHS.addKills(NewVNInfo[RHSValID], VNI->kills); |
| 1737 | } |
| 1738 | |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1739 | // If we get here, we know that we can coalesce the live ranges. Ask the |
| 1740 | // intervals to coalesce themselves now. |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 1741 | if ((RHS.ranges.size() > LHS.ranges.size() && |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1742 | TargetRegisterInfo::isVirtualRegister(LHS.reg)) || |
| 1743 | TargetRegisterInfo::isPhysicalRegister(RHS.reg)) { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1744 | RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo); |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 1745 | Swapped = true; |
| 1746 | } else { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1747 | LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo); |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 1748 | Swapped = false; |
| 1749 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1750 | return true; |
| 1751 | } |
| 1752 | |
| 1753 | namespace { |
| 1754 | // DepthMBBCompare - Comparison predicate that sort first based on the loop |
| 1755 | // depth of the basic block (the unsigned), and then on the MBB number. |
| 1756 | struct DepthMBBCompare { |
| 1757 | typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair; |
| 1758 | bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const { |
| 1759 | if (LHS.first > RHS.first) return true; // Deeper loops first |
| 1760 | return LHS.first == RHS.first && |
| 1761 | LHS.second->getNumber() < RHS.second->getNumber(); |
| 1762 | } |
| 1763 | }; |
| 1764 | } |
| 1765 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1766 | /// getRepIntervalSize - Returns the size of the interval that represents the |
| 1767 | /// specified register. |
| 1768 | template<class SF> |
| 1769 | unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) { |
| 1770 | return Rc->getRepIntervalSize(Reg); |
| 1771 | } |
| 1772 | |
| 1773 | /// CopyRecSort::operator - Join priority queue sorting function. |
| 1774 | /// |
| 1775 | bool CopyRecSort::operator()(CopyRec left, CopyRec right) const { |
| 1776 | // Inner loops first. |
| 1777 | if (left.LoopDepth > right.LoopDepth) |
| 1778 | return false; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1779 | else if (left.LoopDepth == right.LoopDepth) |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1780 | if (left.isBackEdge && !right.isBackEdge) |
| 1781 | return false; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1782 | return true; |
| 1783 | } |
| 1784 | |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1785 | void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB, |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1786 | std::vector<CopyRec> &TryAgain) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1787 | DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n"; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1788 | |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1789 | std::vector<CopyRec> VirtCopies; |
| 1790 | std::vector<CopyRec> PhysCopies; |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1791 | std::vector<CopyRec> ImpDefCopies; |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 1792 | unsigned LoopDepth = loopInfo->getLoopDepth(MBB); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1793 | for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end(); |
| 1794 | MII != E;) { |
| 1795 | MachineInstr *Inst = MII++; |
| 1796 | |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1797 | // If this isn't a copy nor a extract_subreg, we can't join intervals. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1798 | unsigned SrcReg, DstReg; |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1799 | if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) { |
| 1800 | DstReg = Inst->getOperand(0).getReg(); |
| 1801 | SrcReg = Inst->getOperand(1).getReg(); |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1802 | } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG) { |
| 1803 | DstReg = Inst->getOperand(0).getReg(); |
| 1804 | SrcReg = Inst->getOperand(2).getReg(); |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1805 | } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) |
| 1806 | continue; |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1807 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1808 | bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); |
| 1809 | bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1810 | if (NewHeuristic) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1811 | JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg))); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1812 | } else { |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1813 | if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty()) |
| 1814 | ImpDefCopies.push_back(CopyRec(Inst, 0, false)); |
| 1815 | else if (SrcIsPhys || DstIsPhys) |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1816 | PhysCopies.push_back(CopyRec(Inst, 0, false)); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1817 | else |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1818 | VirtCopies.push_back(CopyRec(Inst, 0, false)); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1819 | } |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1820 | } |
| 1821 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1822 | if (NewHeuristic) |
| 1823 | return; |
| 1824 | |
Evan Cheng | 7e073ba | 2008-04-09 20:57:25 +0000 | [diff] [blame] | 1825 | // Try coalescing implicit copies first, followed by copies to / from |
| 1826 | // physical registers, then finally copies from virtual registers to |
| 1827 | // virtual registers. |
| 1828 | for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) { |
| 1829 | CopyRec &TheCopy = ImpDefCopies[i]; |
| 1830 | bool Again = false; |
| 1831 | if (!JoinCopy(TheCopy, Again)) |
| 1832 | if (Again) |
| 1833 | TryAgain.push_back(TheCopy); |
| 1834 | } |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1835 | for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) { |
| 1836 | CopyRec &TheCopy = PhysCopies[i]; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1837 | bool Again = false; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1838 | if (!JoinCopy(TheCopy, Again)) |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1839 | if (Again) |
| 1840 | TryAgain.push_back(TheCopy); |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1841 | } |
| 1842 | for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) { |
| 1843 | CopyRec &TheCopy = VirtCopies[i]; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1844 | bool Again = false; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1845 | if (!JoinCopy(TheCopy, Again)) |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1846 | if (Again) |
| 1847 | TryAgain.push_back(TheCopy); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1848 | } |
| 1849 | } |
| 1850 | |
| 1851 | void SimpleRegisterCoalescing::joinIntervals() { |
| 1852 | DOUT << "********** JOINING INTERVALS ***********\n"; |
| 1853 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1854 | if (NewHeuristic) |
| 1855 | JoinQueue = new JoinPriorityQueue<CopyRecSort>(this); |
| 1856 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1857 | std::vector<CopyRec> TryAgainList; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1858 | if (loopInfo->begin() == loopInfo->end()) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1859 | // If there are no loops in the function, join intervals in function order. |
| 1860 | for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); |
| 1861 | I != E; ++I) |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1862 | CopyCoalesceInMBB(I, TryAgainList); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1863 | } else { |
| 1864 | // Otherwise, join intervals in inner loops before other intervals. |
| 1865 | // Unfortunately we can't just iterate over loop hierarchy here because |
| 1866 | // there may be more MBB's than BB's. Collect MBB's for sorting. |
| 1867 | |
| 1868 | // Join intervals in the function prolog first. We want to join physical |
| 1869 | // registers with virtual registers before the intervals got too long. |
| 1870 | std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs; |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 1871 | for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){ |
| 1872 | MachineBasicBlock *MBB = I; |
| 1873 | MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I)); |
| 1874 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1875 | |
| 1876 | // Sort by loop depth. |
| 1877 | std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare()); |
| 1878 | |
| 1879 | // Finally, join intervals in loop nest order. |
| 1880 | for (unsigned i = 0, e = MBBs.size(); i != e; ++i) |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1881 | CopyCoalesceInMBB(MBBs[i].second, TryAgainList); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1882 | } |
| 1883 | |
| 1884 | // Joining intervals can allow other intervals to be joined. Iteratively join |
| 1885 | // until we make no progress. |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1886 | if (NewHeuristic) { |
| 1887 | SmallVector<CopyRec, 16> TryAgain; |
| 1888 | bool ProgressMade = true; |
| 1889 | while (ProgressMade) { |
| 1890 | ProgressMade = false; |
| 1891 | while (!JoinQueue->empty()) { |
| 1892 | CopyRec R = JoinQueue->pop(); |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1893 | bool Again = false; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1894 | bool Success = JoinCopy(R, Again); |
| 1895 | if (Success) |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1896 | ProgressMade = true; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1897 | else if (Again) |
| 1898 | TryAgain.push_back(R); |
| 1899 | } |
| 1900 | |
| 1901 | if (ProgressMade) { |
| 1902 | while (!TryAgain.empty()) { |
| 1903 | JoinQueue->push(TryAgain.back()); |
| 1904 | TryAgain.pop_back(); |
| 1905 | } |
| 1906 | } |
| 1907 | } |
| 1908 | } else { |
| 1909 | bool ProgressMade = true; |
| 1910 | while (ProgressMade) { |
| 1911 | ProgressMade = false; |
| 1912 | |
| 1913 | for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) { |
| 1914 | CopyRec &TheCopy = TryAgainList[i]; |
| 1915 | if (TheCopy.MI) { |
| 1916 | bool Again = false; |
| 1917 | bool Success = JoinCopy(TheCopy, Again); |
| 1918 | if (Success || !Again) { |
| 1919 | TheCopy.MI = 0; // Mark this one as done. |
| 1920 | ProgressMade = true; |
| 1921 | } |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1922 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1923 | } |
| 1924 | } |
| 1925 | } |
| 1926 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1927 | if (NewHeuristic) |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1928 | delete JoinQueue; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1929 | } |
| 1930 | |
| 1931 | /// Return true if the two specified registers belong to different register |
Evan Cheng | e00f5de | 2008-06-19 01:39:21 +0000 | [diff] [blame] | 1932 | /// classes. The registers may be either phys or virt regs. In the |
| 1933 | /// case where both registers are virtual registers, it would also returns |
| 1934 | /// true by reference the RegB register class in SubRC if it is a subset of |
| 1935 | /// RegA's register class. |
| 1936 | bool |
| 1937 | SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA, unsigned RegB, |
| 1938 | const TargetRegisterClass *&SubRC) const { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1939 | |
| 1940 | // Get the register classes for the first reg. |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1941 | if (TargetRegisterInfo::isPhysicalRegister(RegA)) { |
| 1942 | assert(TargetRegisterInfo::isVirtualRegister(RegB) && |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1943 | "Shouldn't consider two physregs!"); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1944 | return !mri_->getRegClass(RegB)->contains(RegA); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1945 | } |
| 1946 | |
| 1947 | // Compare against the regclass for the second reg. |
Evan Cheng | e00f5de | 2008-06-19 01:39:21 +0000 | [diff] [blame] | 1948 | const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA); |
| 1949 | if (TargetRegisterInfo::isVirtualRegister(RegB)) { |
| 1950 | const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB); |
| 1951 | if (RegClassA == RegClassB) |
| 1952 | return false; |
| 1953 | SubRC = (RegClassA->hasSubClass(RegClassB)) ? RegClassB : NULL; |
| 1954 | return true; |
| 1955 | } |
| 1956 | return !RegClassA->contains(RegB); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1957 | } |
| 1958 | |
| 1959 | /// lastRegisterUse - Returns the last use of the specific register between |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1960 | /// cycles Start and End or NULL if there are no uses. |
| 1961 | MachineOperand * |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 1962 | SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1963 | unsigned Reg, unsigned &UseIdx) const{ |
| 1964 | UseIdx = 0; |
| 1965 | if (TargetRegisterInfo::isVirtualRegister(Reg)) { |
| 1966 | MachineOperand *LastUse = NULL; |
| 1967 | for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg), |
| 1968 | E = mri_->use_end(); I != E; ++I) { |
| 1969 | MachineOperand &Use = I.getOperand(); |
| 1970 | MachineInstr *UseMI = Use.getParent(); |
Evan Cheng | a2fb634 | 2008-03-25 02:02:19 +0000 | [diff] [blame] | 1971 | unsigned SrcReg, DstReg; |
| 1972 | if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg) && SrcReg == DstReg) |
| 1973 | // Ignore identity copies. |
| 1974 | continue; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1975 | unsigned Idx = li_->getInstructionIndex(UseMI); |
| 1976 | if (Idx >= Start && Idx < End && Idx >= UseIdx) { |
| 1977 | LastUse = &Use; |
| 1978 | UseIdx = Idx; |
| 1979 | } |
| 1980 | } |
| 1981 | return LastUse; |
| 1982 | } |
| 1983 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1984 | int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM; |
| 1985 | int s = Start; |
| 1986 | while (e >= s) { |
| 1987 | // Skip deleted instructions |
| 1988 | MachineInstr *MI = li_->getInstructionFromIndex(e); |
| 1989 | while ((e - InstrSlots::NUM) >= s && !MI) { |
| 1990 | e -= InstrSlots::NUM; |
| 1991 | MI = li_->getInstructionFromIndex(e); |
| 1992 | } |
| 1993 | if (e < s || MI == NULL) |
| 1994 | return NULL; |
| 1995 | |
Evan Cheng | a2fb634 | 2008-03-25 02:02:19 +0000 | [diff] [blame] | 1996 | // Ignore identity copies. |
| 1997 | unsigned SrcReg, DstReg; |
| 1998 | if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg)) |
| 1999 | for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) { |
| 2000 | MachineOperand &Use = MI->getOperand(i); |
| 2001 | if (Use.isRegister() && Use.isUse() && Use.getReg() && |
| 2002 | tri_->regsOverlap(Use.getReg(), Reg)) { |
| 2003 | UseIdx = e; |
| 2004 | return &Use; |
| 2005 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2006 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2007 | |
| 2008 | e -= InstrSlots::NUM; |
| 2009 | } |
| 2010 | |
| 2011 | return NULL; |
| 2012 | } |
| 2013 | |
| 2014 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2015 | void SimpleRegisterCoalescing::printRegName(unsigned reg) const { |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 2016 | if (TargetRegisterInfo::isPhysicalRegister(reg)) |
Bill Wendling | e6d088a | 2008-02-26 21:47:57 +0000 | [diff] [blame] | 2017 | cerr << tri_->getName(reg); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2018 | else |
| 2019 | cerr << "%reg" << reg; |
| 2020 | } |
| 2021 | |
| 2022 | void SimpleRegisterCoalescing::releaseMemory() { |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 2023 | JoinedCopies.clear(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2024 | } |
| 2025 | |
| 2026 | static bool isZeroLengthInterval(LiveInterval *li) { |
| 2027 | for (LiveInterval::Ranges::const_iterator |
| 2028 | i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i) |
| 2029 | if (i->end - i->start > LiveIntervals::InstrSlots::NUM) |
| 2030 | return false; |
| 2031 | return true; |
| 2032 | } |
| 2033 | |
Evan Cheng | db9b1c3 | 2008-04-03 16:41:54 +0000 | [diff] [blame] | 2034 | /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def, |
| 2035 | /// turn the copy into an implicit def. |
| 2036 | bool |
| 2037 | SimpleRegisterCoalescing::TurnCopyIntoImpDef(MachineBasicBlock::iterator &I, |
| 2038 | MachineBasicBlock *MBB, |
| 2039 | unsigned DstReg, unsigned SrcReg) { |
| 2040 | MachineInstr *CopyMI = &*I; |
| 2041 | unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI)); |
| 2042 | if (!li_->hasInterval(SrcReg)) |
| 2043 | return false; |
| 2044 | LiveInterval &SrcInt = li_->getInterval(SrcReg); |
| 2045 | if (!SrcInt.empty()) |
| 2046 | return false; |
Evan Cheng | f20d943 | 2008-04-09 01:30:15 +0000 | [diff] [blame] | 2047 | if (!li_->hasInterval(DstReg)) |
| 2048 | return false; |
Evan Cheng | db9b1c3 | 2008-04-03 16:41:54 +0000 | [diff] [blame] | 2049 | LiveInterval &DstInt = li_->getInterval(DstReg); |
Evan Cheng | ff7a3e5 | 2008-04-16 18:48:43 +0000 | [diff] [blame] | 2050 | const LiveRange *DstLR = DstInt.getLiveRangeContaining(CopyIdx); |
Evan Cheng | db9b1c3 | 2008-04-03 16:41:54 +0000 | [diff] [blame] | 2051 | DstInt.removeValNo(DstLR->valno); |
| 2052 | CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF)); |
| 2053 | for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i) |
| 2054 | CopyMI->RemoveOperand(i); |
| 2055 | bool NoUse = mri_->use_begin(SrcReg) == mri_->use_end(); |
| 2056 | if (NoUse) { |
| 2057 | for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg), |
| 2058 | E = mri_->reg_end(); I != E; ) { |
| 2059 | assert(I.getOperand().isDef()); |
| 2060 | MachineInstr *DefMI = &*I; |
| 2061 | ++I; |
| 2062 | // The implicit_def source has no other uses, delete it. |
| 2063 | assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF); |
| 2064 | li_->RemoveMachineInstrFromMaps(DefMI); |
| 2065 | DefMI->eraseFromParent(); |
Evan Cheng | db9b1c3 | 2008-04-03 16:41:54 +0000 | [diff] [blame] | 2066 | } |
| 2067 | } |
| 2068 | ++I; |
| 2069 | return true; |
| 2070 | } |
| 2071 | |
| 2072 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2073 | bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { |
| 2074 | mf_ = &fn; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 2075 | mri_ = &fn.getRegInfo(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2076 | tm_ = &fn.getTarget(); |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 2077 | tri_ = tm_->getRegisterInfo(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2078 | tii_ = tm_->getInstrInfo(); |
| 2079 | li_ = &getAnalysis<LiveIntervals>(); |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 2080 | loopInfo = &getAnalysis<MachineLoopInfo>(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2081 | |
| 2082 | DOUT << "********** SIMPLE REGISTER COALESCING **********\n" |
| 2083 | << "********** Function: " |
| 2084 | << ((Value*)mf_->getFunction())->getName() << '\n'; |
| 2085 | |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 2086 | allocatableRegs_ = tri_->getAllocatableSet(fn); |
| 2087 | for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(), |
| 2088 | E = tri_->regclass_end(); I != E; ++I) |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 2089 | allocatableRCRegs_.insert(std::make_pair(*I, |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 2090 | tri_->getAllocatableSet(fn, *I))); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2091 | |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 2092 | // Join (coalesce) intervals if requested. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2093 | if (EnableJoining) { |
| 2094 | joinIntervals(); |
| 2095 | DOUT << "********** INTERVALS POST JOINING **********\n"; |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 2096 | for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){ |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 2097 | I->second.print(DOUT, tri_); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2098 | DOUT << "\n"; |
| 2099 | } |
| 2100 | } |
| 2101 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 2102 | // Perform a final pass over the instructions and compute spill weights |
| 2103 | // and remove identity moves. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2104 | for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); |
| 2105 | mbbi != mbbe; ++mbbi) { |
| 2106 | MachineBasicBlock* mbb = mbbi; |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 2107 | unsigned loopDepth = loopInfo->getLoopDepth(mbb); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2108 | |
| 2109 | for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); |
| 2110 | mii != mie; ) { |
Evan Cheng | a971dbd | 2008-04-24 09:06:33 +0000 | [diff] [blame] | 2111 | MachineInstr *MI = mii; |
| 2112 | unsigned SrcReg, DstReg; |
| 2113 | if (JoinedCopies.count(MI)) { |
| 2114 | // Delete all coalesced copies. |
| 2115 | if (!tii_->isMoveInstr(*MI, SrcReg, DstReg)) { |
| 2116 | assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG || |
| 2117 | MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) && |
| 2118 | "Unrecognized copy instruction"); |
| 2119 | DstReg = MI->getOperand(0).getReg(); |
| 2120 | } |
| 2121 | if (MI->registerDefIsDead(DstReg)) { |
| 2122 | LiveInterval &li = li_->getInterval(DstReg); |
| 2123 | if (!ShortenDeadCopySrcLiveRange(li, MI)) |
| 2124 | ShortenDeadCopyLiveRange(li, MI); |
| 2125 | } |
| 2126 | li_->RemoveMachineInstrFromMaps(MI); |
| 2127 | mii = mbbi->erase(mii); |
| 2128 | ++numPeep; |
| 2129 | continue; |
| 2130 | } |
| 2131 | |
| 2132 | // If the move will be an identity move delete it |
| 2133 | bool isMove = tii_->isMoveInstr(*mii, SrcReg, DstReg); |
| 2134 | if (isMove && SrcReg == DstReg) { |
| 2135 | if (li_->hasInterval(SrcReg)) { |
| 2136 | LiveInterval &RegInt = li_->getInterval(SrcReg); |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 2137 | // If def of this move instruction is dead, remove its live range |
| 2138 | // from the dstination register's live interval. |
Evan Cheng | a971dbd | 2008-04-24 09:06:33 +0000 | [diff] [blame] | 2139 | if (mii->registerDefIsDead(DstReg)) { |
Evan Cheng | 9c1e06e | 2008-04-16 20:24:25 +0000 | [diff] [blame] | 2140 | if (!ShortenDeadCopySrcLiveRange(RegInt, mii)) |
| 2141 | ShortenDeadCopyLiveRange(RegInt, mii); |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 2142 | } |
| 2143 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2144 | li_->RemoveMachineInstrFromMaps(mii); |
| 2145 | mii = mbbi->erase(mii); |
| 2146 | ++numPeep; |
Evan Cheng | a971dbd | 2008-04-24 09:06:33 +0000 | [diff] [blame] | 2147 | } else if (!isMove || !TurnCopyIntoImpDef(mii, mbb, DstReg, SrcReg)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2148 | SmallSet<unsigned, 4> UniqueUses; |
| 2149 | for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { |
| 2150 | const MachineOperand &mop = mii->getOperand(i); |
| 2151 | if (mop.isRegister() && mop.getReg() && |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 2152 | TargetRegisterInfo::isVirtualRegister(mop.getReg())) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 2153 | unsigned reg = mop.getReg(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2154 | // Multiple uses of reg by the same instruction. It should not |
| 2155 | // contribute to spill weight again. |
| 2156 | if (UniqueUses.count(reg) != 0) |
| 2157 | continue; |
| 2158 | LiveInterval &RegInt = li_->getInterval(reg); |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 2159 | RegInt.weight += |
Evan Cheng | c341760 | 2008-06-21 06:45:54 +0000 | [diff] [blame] | 2160 | li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2161 | UniqueUses.insert(reg); |
| 2162 | } |
| 2163 | } |
| 2164 | ++mii; |
| 2165 | } |
| 2166 | } |
| 2167 | } |
| 2168 | |
| 2169 | for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) { |
| 2170 | LiveInterval &LI = I->second; |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 2171 | if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2172 | // If the live interval length is essentially zero, i.e. in every live |
| 2173 | // range the use follows def immediately, it doesn't make sense to spill |
| 2174 | // it and hope it will be easier to allocate for this li. |
| 2175 | if (isZeroLengthInterval(&LI)) |
| 2176 | LI.weight = HUGE_VALF; |
Evan Cheng | 5ef3a04 | 2007-12-06 00:01:56 +0000 | [diff] [blame] | 2177 | else { |
| 2178 | bool isLoad = false; |
Evan Cheng | 63a18c4 | 2008-02-09 08:36:28 +0000 | [diff] [blame] | 2179 | if (li_->isReMaterializable(LI, isLoad)) { |
Evan Cheng | 5ef3a04 | 2007-12-06 00:01:56 +0000 | [diff] [blame] | 2180 | // If all of the definitions of the interval are re-materializable, |
| 2181 | // it is a preferred candidate for spilling. If non of the defs are |
| 2182 | // loads, then it's potentially very cheap to re-materialize. |
| 2183 | // FIXME: this gets much more complicated once we support non-trivial |
| 2184 | // re-materialization. |
| 2185 | if (isLoad) |
| 2186 | LI.weight *= 0.9F; |
| 2187 | else |
| 2188 | LI.weight *= 0.5F; |
| 2189 | } |
| 2190 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2191 | |
| 2192 | // Slightly prefer live interval that has been assigned a preferred reg. |
| 2193 | if (LI.preference) |
| 2194 | LI.weight *= 1.01F; |
| 2195 | |
| 2196 | // Divide the weight of the interval by its size. This encourages |
| 2197 | // spilling of intervals that are large and have few uses, and |
| 2198 | // discourages spilling of small intervals with many uses. |
Owen Anderson | 496bac5 | 2008-07-23 19:47:27 +0000 | [diff] [blame^] | 2199 | LI.weight /= li_->getApproximateInstructionCount(LI) * InstrSlots::NUM; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 2200 | } |
| 2201 | } |
| 2202 | |
| 2203 | DEBUG(dump()); |
| 2204 | return true; |
| 2205 | } |
| 2206 | |
| 2207 | /// print - Implement the dump method. |
| 2208 | void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const { |
| 2209 | li_->print(O, m); |
| 2210 | } |
David Greene | 2c17c4d | 2007-09-06 16:18:45 +0000 | [diff] [blame] | 2211 | |
| 2212 | RegisterCoalescer* llvm::createSimpleRegisterCoalescer() { |
| 2213 | return new SimpleRegisterCoalescing(); |
| 2214 | } |
| 2215 | |
| 2216 | // Make sure that anything that uses RegisterCoalescer pulls in this file... |
| 2217 | DEFINING_FILE_FOR(SimpleRegisterCoalescing) |