Bill Wendling | 2695d8e | 2010-10-15 21:50:45 +0000 | [diff] [blame] | 1 | //===- ARMInstrVFP.td - VFP support for ARM ----------------*- tablegen -*-===// |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Jim Grosbach | e5d20f9 | 2008-09-11 21:41:29 +0000 | [diff] [blame] | 10 | // This file describes the ARM VFP instruction set. |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Bill Wendling | 2695d8e | 2010-10-15 21:50:45 +0000 | [diff] [blame] | 14 | def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; |
| 15 | def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; |
| 16 | def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>; |
| 17 | def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>, |
| 18 | SDTCisSameAs<1, 2>]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 19 | |
Bill Wendling | 2695d8e | 2010-10-15 21:50:45 +0000 | [diff] [blame] | 20 | def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>; |
| 21 | def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>; |
| 22 | def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>; |
| 23 | def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>; |
Chris Lattner | 036609b | 2010-12-23 18:28:41 +0000 | [diff] [blame] | 24 | def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>; |
| 25 | def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>; |
| 26 | def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>; |
Bill Wendling | 2695d8e | 2010-10-15 21:50:45 +0000 | [diff] [blame] | 27 | def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 28 | |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 29 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 30 | //===----------------------------------------------------------------------===// |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 31 | // Operand Definitions. |
| 32 | // |
| 33 | |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 34 | def vfp_f32imm : Operand<f32>, |
| 35 | PatLeaf<(f32 fpimm), [{ |
Jim Grosbach | 4ebbf7b | 2011-09-30 00:50:06 +0000 | [diff] [blame^] | 36 | return ARM_AM::getFP32Imm(N->getValueAPF()) != -1; |
| 37 | }], SDNodeXForm<fpimm, [{ |
| 38 | APFloat InVal = N->getValueAPF(); |
| 39 | uint32_t enc = ARM_AM::getFP32Imm(InVal); |
| 40 | return CurDAG->getTargetConstant(enc, MVT::i32); |
| 41 | }]>> { |
| 42 | let PrintMethod = "printFPImmOperand"; |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 43 | } |
| 44 | |
| 45 | def vfp_f64imm : Operand<f64>, |
| 46 | PatLeaf<(f64 fpimm), [{ |
Jim Grosbach | 4ebbf7b | 2011-09-30 00:50:06 +0000 | [diff] [blame^] | 47 | return ARM_AM::getFP64Imm(N->getValueAPF()) != -1; |
| 48 | }], SDNodeXForm<fpimm, [{ |
| 49 | APFloat InVal = N->getValueAPF(); |
| 50 | uint32_t enc = ARM_AM::getFP64Imm(InVal); |
| 51 | return CurDAG->getTargetConstant(enc, MVT::i32); |
| 52 | }]>> { |
| 53 | let PrintMethod = "printFPImmOperand"; |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 54 | } |
| 55 | |
| 56 | |
| 57 | //===----------------------------------------------------------------------===// |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 58 | // Load / store Instructions. |
| 59 | // |
| 60 | |
Dan Gohman | bc9d98b | 2010-02-27 23:47:46 +0000 | [diff] [blame] | 61 | let canFoldAsLoad = 1, isReMaterializable = 1 in { |
Bill Wendling | 92b5a2e | 2010-11-03 01:49:29 +0000 | [diff] [blame] | 62 | |
Bill Wendling | 7d31a16 | 2010-10-20 22:44:54 +0000 | [diff] [blame] | 63 | def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), |
| 64 | IIC_fpLoad64, "vldr", ".64\t$Dd, $addr", |
Bill Wendling | 2f46f1f | 2010-11-04 00:59:42 +0000 | [diff] [blame] | 65 | [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 66 | |
Bill Wendling | 92b5a2e | 2010-11-03 01:49:29 +0000 | [diff] [blame] | 67 | def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), |
| 68 | IIC_fpLoad32, "vldr", ".32\t$Sd, $addr", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 69 | [(set SPR:$Sd, (load addrmode5:$addr))]> { |
| 70 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 71 | // pipelines. |
| 72 | let D = VFPNeonDomain; |
| 73 | } |
Bill Wendling | 92b5a2e | 2010-11-03 01:49:29 +0000 | [diff] [blame] | 74 | |
| 75 | } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in' |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 76 | |
Bill Wendling | 2f46f1f | 2010-11-04 00:59:42 +0000 | [diff] [blame] | 77 | def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr), |
| 78 | IIC_fpStore64, "vstr", ".64\t$Dd, $addr", |
| 79 | [(store (f64 DPR:$Dd), addrmode5:$addr)]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 80 | |
Bill Wendling | 2f46f1f | 2010-11-04 00:59:42 +0000 | [diff] [blame] | 81 | def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr), |
| 82 | IIC_fpStore32, "vstr", ".32\t$Sd, $addr", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 83 | [(store SPR:$Sd, addrmode5:$addr)]> { |
| 84 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 85 | // pipelines. |
| 86 | let D = VFPNeonDomain; |
| 87 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 88 | |
| 89 | //===----------------------------------------------------------------------===// |
| 90 | // Load / store multiple Instructions. |
| 91 | // |
| 92 | |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 93 | multiclass vfp_ldst_mult<string asm, bit L_bit, |
| 94 | InstrItinClass itin, InstrItinClass itin_upd> { |
| 95 | // Double Precision |
| 96 | def DIA : |
Bill Wendling | 0f63075 | 2010-11-17 04:32:08 +0000 | [diff] [blame] | 97 | AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 98 | IndexModeNone, itin, |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 99 | !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 100 | let Inst{24-23} = 0b01; // Increment After |
| 101 | let Inst{21} = 0; // No writeback |
| 102 | let Inst{20} = L_bit; |
| 103 | } |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 104 | def DIA_UPD : |
Jim Grosbach | f921c0fe | 2011-06-13 22:54:22 +0000 | [diff] [blame] | 105 | AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, |
| 106 | variable_ops), |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 107 | IndexModeUpd, itin_upd, |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 108 | !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 109 | let Inst{24-23} = 0b01; // Increment After |
| 110 | let Inst{21} = 1; // Writeback |
| 111 | let Inst{20} = L_bit; |
| 112 | } |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 113 | def DDB_UPD : |
Jim Grosbach | f921c0fe | 2011-06-13 22:54:22 +0000 | [diff] [blame] | 114 | AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, |
| 115 | variable_ops), |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 116 | IndexModeUpd, itin_upd, |
| 117 | !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { |
| 118 | let Inst{24-23} = 0b10; // Decrement Before |
| 119 | let Inst{21} = 1; // Writeback |
| 120 | let Inst{20} = L_bit; |
| 121 | } |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 122 | |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 123 | // Single Precision |
| 124 | def SIA : |
Bill Wendling | 0f63075 | 2010-11-17 04:32:08 +0000 | [diff] [blame] | 125 | AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops), |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 126 | IndexModeNone, itin, |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 127 | !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 128 | let Inst{24-23} = 0b01; // Increment After |
| 129 | let Inst{21} = 0; // No writeback |
| 130 | let Inst{20} = L_bit; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 131 | |
| 132 | // Some single precision VFP instructions may be executed on both NEON and |
| 133 | // VFP pipelines. |
| 134 | let D = VFPNeonDomain; |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 135 | } |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 136 | def SIA_UPD : |
Jim Grosbach | f921c0fe | 2011-06-13 22:54:22 +0000 | [diff] [blame] | 137 | AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, |
| 138 | variable_ops), |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 139 | IndexModeUpd, itin_upd, |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 140 | !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 141 | let Inst{24-23} = 0b01; // Increment After |
| 142 | let Inst{21} = 1; // Writeback |
| 143 | let Inst{20} = L_bit; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 144 | |
| 145 | // Some single precision VFP instructions may be executed on both NEON and |
| 146 | // VFP pipelines. |
| 147 | let D = VFPNeonDomain; |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 148 | } |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 149 | def SDB_UPD : |
Jim Grosbach | f921c0fe | 2011-06-13 22:54:22 +0000 | [diff] [blame] | 150 | AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, |
| 151 | variable_ops), |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 152 | IndexModeUpd, itin_upd, |
| 153 | !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { |
| 154 | let Inst{24-23} = 0b10; // Decrement Before |
| 155 | let Inst{21} = 1; // Writeback |
| 156 | let Inst{20} = L_bit; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 157 | |
| 158 | // Some single precision VFP instructions may be executed on both NEON and |
| 159 | // VFP pipelines. |
| 160 | let D = VFPNeonDomain; |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 161 | } |
| 162 | } |
| 163 | |
Bill Wendling | ddc918b | 2010-11-13 10:57:02 +0000 | [diff] [blame] | 164 | let neverHasSideEffects = 1 in { |
| 165 | |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 166 | let mayLoad = 1, hasExtraDefRegAllocReq = 1 in |
| 167 | defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>; |
Bill Wendling | ddc918b | 2010-11-13 10:57:02 +0000 | [diff] [blame] | 168 | |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 169 | let mayStore = 1, hasExtraSrcRegAllocReq = 1 in |
| 170 | defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpLoad_m, IIC_fpLoad_mu>; |
Bill Wendling | ddc918b | 2010-11-13 10:57:02 +0000 | [diff] [blame] | 171 | |
| 172 | } // neverHasSideEffects |
| 173 | |
Bill Wendling | 73c57e1 | 2010-11-16 02:00:24 +0000 | [diff] [blame] | 174 | def : MnemonicAlias<"vldm", "vldmia">; |
| 175 | def : MnemonicAlias<"vstm", "vstmia">; |
| 176 | |
Jim Grosbach | 0d06bb9 | 2011-06-27 20:00:07 +0000 | [diff] [blame] | 177 | def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>, |
| 178 | Requires<[HasVFP2]>; |
| 179 | def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>, |
| 180 | Requires<[HasVFP2]>; |
| 181 | def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>, |
| 182 | Requires<[HasVFP2]>; |
| 183 | def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>, |
| 184 | Requires<[HasVFP2]>; |
| 185 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 186 | // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores |
| 187 | |
| 188 | //===----------------------------------------------------------------------===// |
| 189 | // FP Binary Operations. |
| 190 | // |
| 191 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 192 | def VADDD : ADbI<0b11100, 0b11, 0, 0, |
| 193 | (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), |
| 194 | IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm", |
| 195 | [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>; |
Bill Wendling | 174777b | 2010-10-12 22:08:41 +0000 | [diff] [blame] | 196 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 197 | def VADDS : ASbIn<0b11100, 0b11, 0, 0, |
| 198 | (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), |
| 199 | IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 200 | [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 201 | // Some single precision VFP instructions may be executed on both NEON and |
| 202 | // VFP pipelines on A8. |
| 203 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 204 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 205 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 206 | def VSUBD : ADbI<0b11100, 0b11, 1, 0, |
| 207 | (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), |
| 208 | IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm", |
| 209 | [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>; |
Jim Grosbach | 499e886 | 2010-10-12 21:22:40 +0000 | [diff] [blame] | 210 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 211 | def VSUBS : ASbIn<0b11100, 0b11, 1, 0, |
| 212 | (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), |
| 213 | IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 214 | [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 215 | // Some single precision VFP instructions may be executed on both NEON and |
| 216 | // VFP pipelines on A8. |
| 217 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 218 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 219 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 220 | def VDIVD : ADbI<0b11101, 0b00, 0, 0, |
| 221 | (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), |
| 222 | IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm", |
| 223 | [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 224 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 225 | def VDIVS : ASbI<0b11101, 0b00, 0, 0, |
| 226 | (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), |
| 227 | IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm", |
| 228 | [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 229 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 230 | def VMULD : ADbI<0b11100, 0b10, 0, 0, |
| 231 | (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), |
| 232 | IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm", |
| 233 | [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 234 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 235 | def VMULS : ASbIn<0b11100, 0b10, 0, 0, |
| 236 | (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), |
| 237 | IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 238 | [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 239 | // Some single precision VFP instructions may be executed on both NEON and |
| 240 | // VFP pipelines on A8. |
| 241 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 242 | } |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 243 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 244 | def VNMULD : ADbI<0b11100, 0b10, 1, 0, |
| 245 | (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), |
| 246 | IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm", |
| 247 | [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 248 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 249 | def VNMULS : ASbI<0b11100, 0b10, 1, 0, |
| 250 | (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), |
| 251 | IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 252 | [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 253 | // Some single precision VFP instructions may be executed on both NEON and |
| 254 | // VFP pipelines on A8. |
| 255 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 256 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 257 | |
Chris Lattner | 7293912 | 2007-05-03 00:32:00 +0000 | [diff] [blame] | 258 | // Match reassociated forms only if not sign dependent rounding. |
Chris Lattner | d10a53d | 2010-03-08 18:51:21 +0000 | [diff] [blame] | 259 | def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)), |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 260 | (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>; |
Chris Lattner | 7293912 | 2007-05-03 00:32:00 +0000 | [diff] [blame] | 261 | def : Pat<(fmul (fneg SPR:$a), SPR:$b), |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 262 | (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>; |
Chris Lattner | 7293912 | 2007-05-03 00:32:00 +0000 | [diff] [blame] | 263 | |
Bill Wendling | dd3bc11 | 2010-10-12 22:55:35 +0000 | [diff] [blame] | 264 | // These are encoded as unary instructions. |
| 265 | let Defs = [FPSCR] in { |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 266 | def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, |
| 267 | (outs), (ins DPR:$Dd, DPR:$Dm), |
| 268 | IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", |
| 269 | [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 270 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 271 | def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0, |
| 272 | (outs), (ins SPR:$Sd, SPR:$Sm), |
| 273 | IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 274 | [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 275 | // Some single precision VFP instructions may be executed on both NEON and |
| 276 | // VFP pipelines on A8. |
| 277 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 278 | } |
Bill Wendling | dd3bc11 | 2010-10-12 22:55:35 +0000 | [diff] [blame] | 279 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 280 | // FIXME: Verify encoding after integrated assembler is working. |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 281 | def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, |
| 282 | (outs), (ins DPR:$Dd, DPR:$Dm), |
| 283 | IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", |
| 284 | [/* For disassembly only; pattern left blank */]>; |
Bill Wendling | dd3bc11 | 2010-10-12 22:55:35 +0000 | [diff] [blame] | 285 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 286 | def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, |
| 287 | (outs), (ins SPR:$Sd, SPR:$Sm), |
| 288 | IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 289 | [/* For disassembly only; pattern left blank */]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 290 | // Some single precision VFP instructions may be executed on both NEON and |
| 291 | // VFP pipelines on A8. |
| 292 | let D = VFPNeonA8Domain; |
Bill Wendling | dd3bc11 | 2010-10-12 22:55:35 +0000 | [diff] [blame] | 293 | } |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 294 | } // Defs = [FPSCR] |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 295 | |
| 296 | //===----------------------------------------------------------------------===// |
| 297 | // FP Unary Operations. |
| 298 | // |
| 299 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 300 | def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, |
| 301 | (outs DPR:$Dd), (ins DPR:$Dm), |
| 302 | IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm", |
| 303 | [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 304 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 305 | def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0, |
| 306 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 307 | IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 308 | [(set SPR:$Sd, (fabs SPR:$Sm))]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 309 | // Some single precision VFP instructions may be executed on both NEON and |
| 310 | // VFP pipelines on A8. |
| 311 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 312 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 313 | |
Evan Cheng | 91449a8 | 2009-07-20 02:12:31 +0000 | [diff] [blame] | 314 | let Defs = [FPSCR] in { |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 315 | def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, |
| 316 | (outs), (ins DPR:$Dd), |
| 317 | IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", |
| 318 | [(arm_cmpfp0 (f64 DPR:$Dd))]> { |
| 319 | let Inst{3-0} = 0b0000; |
| 320 | let Inst{5} = 0; |
Bill Wendling | 1fc6d88 | 2010-10-13 00:38:07 +0000 | [diff] [blame] | 321 | } |
| 322 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 323 | def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0, |
| 324 | (outs), (ins SPR:$Sd), |
| 325 | IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", |
| 326 | [(arm_cmpfp0 SPR:$Sd)]> { |
| 327 | let Inst{3-0} = 0b0000; |
| 328 | let Inst{5} = 0; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 329 | |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 330 | // Some single precision VFP instructions may be executed on both NEON and |
| 331 | // VFP pipelines on A8. |
| 332 | let D = VFPNeonA8Domain; |
Bill Wendling | 1fc6d88 | 2010-10-13 00:38:07 +0000 | [diff] [blame] | 333 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 334 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 335 | // FIXME: Verify encoding after integrated assembler is working. |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 336 | def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, |
| 337 | (outs), (ins DPR:$Dd), |
| 338 | IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", |
| 339 | [/* For disassembly only; pattern left blank */]> { |
| 340 | let Inst{3-0} = 0b0000; |
| 341 | let Inst{5} = 0; |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 342 | } |
Johnny Chen | 7edd8e3 | 2010-02-08 19:41:48 +0000 | [diff] [blame] | 343 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 344 | def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, |
| 345 | (outs), (ins SPR:$Sd), |
| 346 | IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", |
| 347 | [/* For disassembly only; pattern left blank */]> { |
| 348 | let Inst{3-0} = 0b0000; |
| 349 | let Inst{5} = 0; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 350 | |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 351 | // Some single precision VFP instructions may be executed on both NEON and |
| 352 | // VFP pipelines on A8. |
| 353 | let D = VFPNeonA8Domain; |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 354 | } |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 355 | } // Defs = [FPSCR] |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 356 | |
Bill Wendling | 54908dd | 2010-10-13 00:56:35 +0000 | [diff] [blame] | 357 | def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0, |
| 358 | (outs DPR:$Dd), (ins SPR:$Sm), |
| 359 | IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm", |
| 360 | [(set DPR:$Dd, (fextend SPR:$Sm))]> { |
| 361 | // Instruction operands. |
| 362 | bits<5> Dd; |
| 363 | bits<5> Sm; |
| 364 | |
| 365 | // Encode instruction operands. |
| 366 | let Inst{3-0} = Sm{4-1}; |
| 367 | let Inst{5} = Sm{0}; |
| 368 | let Inst{15-12} = Dd{3-0}; |
| 369 | let Inst{22} = Dd{4}; |
| 370 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 371 | |
Evan Cheng | 96581d3 | 2008-11-11 02:11:05 +0000 | [diff] [blame] | 372 | // Special case encoding: bits 11-8 is 0b1011. |
Bill Wendling | 54908dd | 2010-10-13 00:56:35 +0000 | [diff] [blame] | 373 | def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm, |
| 374 | IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm", |
| 375 | [(set SPR:$Sd, (fround DPR:$Dm))]> { |
| 376 | // Instruction operands. |
| 377 | bits<5> Sd; |
| 378 | bits<5> Dm; |
| 379 | |
| 380 | // Encode instruction operands. |
| 381 | let Inst{3-0} = Dm{3-0}; |
| 382 | let Inst{5} = Dm{4}; |
| 383 | let Inst{15-12} = Sd{4-1}; |
| 384 | let Inst{22} = Sd{0}; |
| 385 | |
Evan Cheng | 96581d3 | 2008-11-11 02:11:05 +0000 | [diff] [blame] | 386 | let Inst{27-23} = 0b11101; |
| 387 | let Inst{21-16} = 0b110111; |
| 388 | let Inst{11-8} = 0b1011; |
Johnny Chen | 69a8c7f | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 389 | let Inst{7-6} = 0b11; |
| 390 | let Inst{4} = 0; |
Evan Cheng | 96581d3 | 2008-11-11 02:11:05 +0000 | [diff] [blame] | 391 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 392 | |
Johnny Chen | 2d658df | 2010-02-09 17:21:56 +0000 | [diff] [blame] | 393 | // Between half-precision and single-precision. For disassembly only. |
| 394 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 395 | // FIXME: Verify encoding after integrated assembler is working. |
Owen Anderson | 838130e | 2011-08-22 21:34:00 +0000 | [diff] [blame] | 396 | def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), |
| 397 | /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", |
Anton Korobeynikov | f0d5007 | 2010-03-18 22:35:37 +0000 | [diff] [blame] | 398 | [/* For disassembly only; pattern left blank */]>; |
| 399 | |
Bob Wilson | 76a312b | 2010-03-19 22:51:32 +0000 | [diff] [blame] | 400 | def : ARMPat<(f32_to_f16 SPR:$a), |
| 401 | (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>; |
Johnny Chen | 2d658df | 2010-02-09 17:21:56 +0000 | [diff] [blame] | 402 | |
Owen Anderson | 838130e | 2011-08-22 21:34:00 +0000 | [diff] [blame] | 403 | def VCVTBHS: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), |
| 404 | /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", |
Anton Korobeynikov | f0d5007 | 2010-03-18 22:35:37 +0000 | [diff] [blame] | 405 | [/* For disassembly only; pattern left blank */]>; |
| 406 | |
Bob Wilson | 76a312b | 2010-03-19 22:51:32 +0000 | [diff] [blame] | 407 | def : ARMPat<(f16_to_f32 GPR:$a), |
| 408 | (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>; |
Johnny Chen | 2d658df | 2010-02-09 17:21:56 +0000 | [diff] [blame] | 409 | |
Owen Anderson | 838130e | 2011-08-22 21:34:00 +0000 | [diff] [blame] | 410 | def VCVTTSH: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), |
| 411 | /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", |
Johnny Chen | 2d658df | 2010-02-09 17:21:56 +0000 | [diff] [blame] | 412 | [/* For disassembly only; pattern left blank */]>; |
| 413 | |
Owen Anderson | 838130e | 2011-08-22 21:34:00 +0000 | [diff] [blame] | 414 | def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), |
| 415 | /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", |
Johnny Chen | 2d658df | 2010-02-09 17:21:56 +0000 | [diff] [blame] | 416 | [/* For disassembly only; pattern left blank */]>; |
| 417 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 418 | def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, |
| 419 | (outs DPR:$Dd), (ins DPR:$Dm), |
| 420 | IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", |
| 421 | [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 422 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 423 | def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0, |
| 424 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 425 | IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 426 | [(set SPR:$Sd, (fneg SPR:$Sm))]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 427 | // Some single precision VFP instructions may be executed on both NEON and |
| 428 | // VFP pipelines on A8. |
| 429 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 430 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 431 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 432 | def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, |
| 433 | (outs DPR:$Dd), (ins DPR:$Dm), |
| 434 | IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm", |
| 435 | [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 436 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 437 | def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, |
| 438 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 439 | IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", |
| 440 | [(set SPR:$Sd, (fsqrt SPR:$Sm))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 441 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 442 | let neverHasSideEffects = 1 in { |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 443 | def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0, |
| 444 | (outs DPR:$Dd), (ins DPR:$Dm), |
| 445 | IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>; |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 446 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 447 | def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0, |
| 448 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 449 | IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>; |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 450 | } // neverHasSideEffects |
| 451 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 452 | //===----------------------------------------------------------------------===// |
| 453 | // FP <-> GPR Copies. Int <-> FP Conversions. |
| 454 | // |
| 455 | |
Bill Wendling | 7d31a16 | 2010-10-20 22:44:54 +0000 | [diff] [blame] | 456 | def VMOVRS : AVConv2I<0b11100001, 0b1010, |
| 457 | (outs GPR:$Rt), (ins SPR:$Sn), |
| 458 | IIC_fpMOVSI, "vmov", "\t$Rt, $Sn", |
| 459 | [(set GPR:$Rt, (bitconvert SPR:$Sn))]> { |
| 460 | // Instruction operands. |
| 461 | bits<4> Rt; |
| 462 | bits<5> Sn; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 463 | |
Bill Wendling | 7d31a16 | 2010-10-20 22:44:54 +0000 | [diff] [blame] | 464 | // Encode instruction operands. |
| 465 | let Inst{19-16} = Sn{4-1}; |
| 466 | let Inst{7} = Sn{0}; |
| 467 | let Inst{15-12} = Rt; |
| 468 | |
| 469 | let Inst{6-5} = 0b00; |
| 470 | let Inst{3-0} = 0b0000; |
Bob Wilson | b34d837 | 2011-04-19 18:11:38 +0000 | [diff] [blame] | 471 | |
| 472 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 473 | // pipelines. |
| 474 | let D = VFPNeonDomain; |
Bill Wendling | 7d31a16 | 2010-10-20 22:44:54 +0000 | [diff] [blame] | 475 | } |
| 476 | |
| 477 | def VMOVSR : AVConv4I<0b11100000, 0b1010, |
| 478 | (outs SPR:$Sn), (ins GPR:$Rt), |
| 479 | IIC_fpMOVIS, "vmov", "\t$Sn, $Rt", |
| 480 | [(set SPR:$Sn, (bitconvert GPR:$Rt))]> { |
| 481 | // Instruction operands. |
| 482 | bits<5> Sn; |
| 483 | bits<4> Rt; |
| 484 | |
| 485 | // Encode instruction operands. |
| 486 | let Inst{19-16} = Sn{4-1}; |
| 487 | let Inst{7} = Sn{0}; |
| 488 | let Inst{15-12} = Rt; |
| 489 | |
| 490 | let Inst{6-5} = 0b00; |
| 491 | let Inst{3-0} = 0b0000; |
Bob Wilson | b34d837 | 2011-04-19 18:11:38 +0000 | [diff] [blame] | 492 | |
| 493 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 494 | // pipelines. |
| 495 | let D = VFPNeonDomain; |
Bill Wendling | 7d31a16 | 2010-10-20 22:44:54 +0000 | [diff] [blame] | 496 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 497 | |
Evan Cheng | 020cc1b | 2010-05-13 00:16:46 +0000 | [diff] [blame] | 498 | let neverHasSideEffects = 1 in { |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 499 | def VMOVRRD : AVConv3I<0b11000101, 0b1011, |
Bill Wendling | 01aabda | 2010-10-20 23:37:40 +0000 | [diff] [blame] | 500 | (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm), |
| 501 | IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm", |
Johnny Chen | 7acca67 | 2010-02-05 18:04:58 +0000 | [diff] [blame] | 502 | [/* FIXME: Can't write pattern for multiple result instr*/]> { |
Bill Wendling | 01aabda | 2010-10-20 23:37:40 +0000 | [diff] [blame] | 503 | // Instruction operands. |
| 504 | bits<5> Dm; |
| 505 | bits<4> Rt; |
| 506 | bits<4> Rt2; |
| 507 | |
| 508 | // Encode instruction operands. |
| 509 | let Inst{3-0} = Dm{3-0}; |
| 510 | let Inst{5} = Dm{4}; |
| 511 | let Inst{15-12} = Rt; |
| 512 | let Inst{19-16} = Rt2; |
| 513 | |
Johnny Chen | 7acca67 | 2010-02-05 18:04:58 +0000 | [diff] [blame] | 514 | let Inst{7-6} = 0b00; |
Bob Wilson | b34d837 | 2011-04-19 18:11:38 +0000 | [diff] [blame] | 515 | |
| 516 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 517 | // pipelines. |
| 518 | let D = VFPNeonDomain; |
Johnny Chen | 7acca67 | 2010-02-05 18:04:58 +0000 | [diff] [blame] | 519 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 520 | |
Johnny Chen | 23401d6 | 2010-02-08 17:26:09 +0000 | [diff] [blame] | 521 | def VMOVRRS : AVConv3I<0b11000101, 0b1010, |
Owen Anderson | 694e0ff | 2011-08-29 23:15:25 +0000 | [diff] [blame] | 522 | (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2), |
| 523 | IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2", |
Johnny Chen | 23401d6 | 2010-02-08 17:26:09 +0000 | [diff] [blame] | 524 | [/* For disassembly only; pattern left blank */]> { |
Owen Anderson | 694e0ff | 2011-08-29 23:15:25 +0000 | [diff] [blame] | 525 | bits<5> src1; |
| 526 | bits<4> Rt; |
| 527 | bits<4> Rt2; |
| 528 | |
| 529 | // Encode instruction operands. |
| 530 | let Inst{3-0} = src1{3-0}; |
| 531 | let Inst{5} = src1{4}; |
| 532 | let Inst{15-12} = Rt; |
| 533 | let Inst{19-16} = Rt2; |
| 534 | |
Johnny Chen | 23401d6 | 2010-02-08 17:26:09 +0000 | [diff] [blame] | 535 | let Inst{7-6} = 0b00; |
Bob Wilson | b34d837 | 2011-04-19 18:11:38 +0000 | [diff] [blame] | 536 | |
| 537 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 538 | // pipelines. |
| 539 | let D = VFPNeonDomain; |
Owen Anderson | 357ec68 | 2011-08-22 20:27:12 +0000 | [diff] [blame] | 540 | let DecoderMethod = "DecodeVMOVRRS"; |
Johnny Chen | 23401d6 | 2010-02-08 17:26:09 +0000 | [diff] [blame] | 541 | } |
Evan Cheng | 020cc1b | 2010-05-13 00:16:46 +0000 | [diff] [blame] | 542 | } // neverHasSideEffects |
Johnny Chen | 23401d6 | 2010-02-08 17:26:09 +0000 | [diff] [blame] | 543 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 544 | // FMDHR: GPR -> SPR |
| 545 | // FMDLR: GPR -> SPR |
| 546 | |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 547 | def VMOVDRR : AVConv5I<0b11000100, 0b1011, |
Bill Wendling | 01aabda | 2010-10-20 23:37:40 +0000 | [diff] [blame] | 548 | (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2), |
| 549 | IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2", |
| 550 | [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> { |
| 551 | // Instruction operands. |
| 552 | bits<5> Dm; |
| 553 | bits<4> Rt; |
| 554 | bits<4> Rt2; |
| 555 | |
| 556 | // Encode instruction operands. |
| 557 | let Inst{3-0} = Dm{3-0}; |
| 558 | let Inst{5} = Dm{4}; |
| 559 | let Inst{15-12} = Rt; |
| 560 | let Inst{19-16} = Rt2; |
| 561 | |
| 562 | let Inst{7-6} = 0b00; |
Bob Wilson | b34d837 | 2011-04-19 18:11:38 +0000 | [diff] [blame] | 563 | |
| 564 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 565 | // pipelines. |
| 566 | let D = VFPNeonDomain; |
Johnny Chen | 7acca67 | 2010-02-05 18:04:58 +0000 | [diff] [blame] | 567 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 568 | |
Evan Cheng | 020cc1b | 2010-05-13 00:16:46 +0000 | [diff] [blame] | 569 | let neverHasSideEffects = 1 in |
Johnny Chen | 23401d6 | 2010-02-08 17:26:09 +0000 | [diff] [blame] | 570 | def VMOVSRR : AVConv5I<0b11000100, 0b1010, |
| 571 | (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2), |
Anton Korobeynikov | a31c6fb | 2010-04-07 18:20:02 +0000 | [diff] [blame] | 572 | IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2", |
Johnny Chen | 23401d6 | 2010-02-08 17:26:09 +0000 | [diff] [blame] | 573 | [/* For disassembly only; pattern left blank */]> { |
Owen Anderson | 694e0ff | 2011-08-29 23:15:25 +0000 | [diff] [blame] | 574 | // Instruction operands. |
| 575 | bits<5> dst1; |
| 576 | bits<4> src1; |
| 577 | bits<4> src2; |
| 578 | |
| 579 | // Encode instruction operands. |
| 580 | let Inst{3-0} = dst1{3-0}; |
| 581 | let Inst{5} = dst1{4}; |
| 582 | let Inst{15-12} = src1; |
| 583 | let Inst{19-16} = src2; |
| 584 | |
Johnny Chen | 23401d6 | 2010-02-08 17:26:09 +0000 | [diff] [blame] | 585 | let Inst{7-6} = 0b00; |
Bob Wilson | b34d837 | 2011-04-19 18:11:38 +0000 | [diff] [blame] | 586 | |
| 587 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 588 | // pipelines. |
| 589 | let D = VFPNeonDomain; |
Owen Anderson | 357ec68 | 2011-08-22 20:27:12 +0000 | [diff] [blame] | 590 | |
| 591 | let DecoderMethod = "DecodeVMOVSRR"; |
Johnny Chen | 23401d6 | 2010-02-08 17:26:09 +0000 | [diff] [blame] | 592 | } |
| 593 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 594 | // FMRDH: SPR -> GPR |
| 595 | // FMRDL: SPR -> GPR |
| 596 | // FMRRS: SPR -> GPR |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 597 | // FMRX: SPR system reg -> GPR |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 598 | // FMSRR: GPR -> SPR |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 599 | // FMXR: GPR -> VFP system reg |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 600 | |
| 601 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 602 | // Int -> FP: |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 603 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 604 | class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, |
| 605 | bits<4> opcod4, dag oops, dag iops, |
| 606 | InstrItinClass itin, string opc, string asm, |
| 607 | list<dag> pattern> |
| 608 | : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, |
| 609 | pattern> { |
| 610 | // Instruction operands. |
| 611 | bits<5> Dd; |
| 612 | bits<5> Sm; |
| 613 | |
| 614 | // Encode instruction operands. |
| 615 | let Inst{3-0} = Sm{4-1}; |
| 616 | let Inst{5} = Sm{0}; |
| 617 | let Inst{15-12} = Dd{3-0}; |
| 618 | let Inst{22} = Dd{4}; |
| 619 | } |
| 620 | |
| 621 | class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, |
| 622 | bits<4> opcod4, dag oops, dag iops,InstrItinClass itin, |
| 623 | string opc, string asm, list<dag> pattern> |
| 624 | : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, |
| 625 | pattern> { |
| 626 | // Instruction operands. |
| 627 | bits<5> Sd; |
| 628 | bits<5> Sm; |
| 629 | |
| 630 | // Encode instruction operands. |
| 631 | let Inst{3-0} = Sm{4-1}; |
| 632 | let Inst{5} = Sm{0}; |
| 633 | let Inst{15-12} = Sd{4-1}; |
| 634 | let Inst{22} = Sd{0}; |
| 635 | } |
| 636 | |
| 637 | def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, |
| 638 | (outs DPR:$Dd), (ins SPR:$Sm), |
| 639 | IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm", |
| 640 | [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> { |
Johnny Chen | 69a8c7f | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 641 | let Inst{7} = 1; // s32 |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 642 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 643 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 644 | def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, |
| 645 | (outs SPR:$Sd),(ins SPR:$Sm), |
| 646 | IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm", |
| 647 | [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> { |
Johnny Chen | 69a8c7f | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 648 | let Inst{7} = 1; // s32 |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 649 | |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 650 | // Some single precision VFP instructions may be executed on both NEON and |
| 651 | // VFP pipelines on A8. |
| 652 | let D = VFPNeonA8Domain; |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 653 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 654 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 655 | def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, |
| 656 | (outs DPR:$Dd), (ins SPR:$Sm), |
| 657 | IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm", |
| 658 | [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> { |
Johnny Chen | 69a8c7f | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 659 | let Inst{7} = 0; // u32 |
| 660 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 661 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 662 | def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, |
| 663 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 664 | IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm", |
| 665 | [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> { |
Johnny Chen | 69a8c7f | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 666 | let Inst{7} = 0; // u32 |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 667 | |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 668 | // Some single precision VFP instructions may be executed on both NEON and |
| 669 | // VFP pipelines on A8. |
| 670 | let D = VFPNeonA8Domain; |
Johnny Chen | 69a8c7f | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 671 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 672 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 673 | // FP -> Int: |
| 674 | |
| 675 | class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, |
| 676 | bits<4> opcod4, dag oops, dag iops, |
| 677 | InstrItinClass itin, string opc, string asm, |
| 678 | list<dag> pattern> |
| 679 | : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, |
| 680 | pattern> { |
| 681 | // Instruction operands. |
| 682 | bits<5> Sd; |
| 683 | bits<5> Dm; |
| 684 | |
| 685 | // Encode instruction operands. |
| 686 | let Inst{3-0} = Dm{3-0}; |
| 687 | let Inst{5} = Dm{4}; |
| 688 | let Inst{15-12} = Sd{4-1}; |
| 689 | let Inst{22} = Sd{0}; |
| 690 | } |
| 691 | |
| 692 | class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, |
| 693 | bits<4> opcod4, dag oops, dag iops, |
| 694 | InstrItinClass itin, string opc, string asm, |
| 695 | list<dag> pattern> |
| 696 | : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, |
| 697 | pattern> { |
| 698 | // Instruction operands. |
| 699 | bits<5> Sd; |
| 700 | bits<5> Sm; |
| 701 | |
| 702 | // Encode instruction operands. |
| 703 | let Inst{3-0} = Sm{4-1}; |
| 704 | let Inst{5} = Sm{0}; |
| 705 | let Inst{15-12} = Sd{4-1}; |
| 706 | let Inst{22} = Sd{0}; |
| 707 | } |
| 708 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 709 | // Always set Z bit in the instruction, i.e. "round towards zero" variants. |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 710 | def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, |
| 711 | (outs SPR:$Sd), (ins DPR:$Dm), |
| 712 | IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm", |
| 713 | [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> { |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 714 | let Inst{7} = 1; // Z bit |
| 715 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 716 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 717 | def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, |
| 718 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 719 | IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm", |
| 720 | [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> { |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 721 | let Inst{7} = 1; // Z bit |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 722 | |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 723 | // Some single precision VFP instructions may be executed on both NEON and |
| 724 | // VFP pipelines on A8. |
| 725 | let D = VFPNeonA8Domain; |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 726 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 727 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 728 | def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, |
| 729 | (outs SPR:$Sd), (ins DPR:$Dm), |
| 730 | IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm", |
| 731 | [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> { |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 732 | let Inst{7} = 1; // Z bit |
| 733 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 734 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 735 | def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, |
| 736 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 737 | IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm", |
| 738 | [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> { |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 739 | let Inst{7} = 1; // Z bit |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 740 | |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 741 | // Some single precision VFP instructions may be executed on both NEON and |
| 742 | // VFP pipelines on A8. |
| 743 | let D = VFPNeonA8Domain; |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 744 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 745 | |
Johnny Chen | 15b423f | 2010-02-08 22:02:41 +0000 | [diff] [blame] | 746 | // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR. |
Nate Begeman | d1fb583 | 2010-08-03 21:31:55 +0000 | [diff] [blame] | 747 | let Uses = [FPSCR] in { |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 748 | // FIXME: Verify encoding after integrated assembler is working. |
| 749 | def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, |
| 750 | (outs SPR:$Sd), (ins DPR:$Dm), |
| 751 | IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm", |
| 752 | [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{ |
Johnny Chen | 15b423f | 2010-02-08 22:02:41 +0000 | [diff] [blame] | 753 | let Inst{7} = 0; // Z bit |
| 754 | } |
| 755 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 756 | def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, |
| 757 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 758 | IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm", |
| 759 | [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> { |
Johnny Chen | 15b423f | 2010-02-08 22:02:41 +0000 | [diff] [blame] | 760 | let Inst{7} = 0; // Z bit |
| 761 | } |
| 762 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 763 | def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, |
| 764 | (outs SPR:$Sd), (ins DPR:$Dm), |
| 765 | IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm", |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 766 | [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{ |
Johnny Chen | 15b423f | 2010-02-08 22:02:41 +0000 | [diff] [blame] | 767 | let Inst{7} = 0; // Z bit |
| 768 | } |
| 769 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 770 | def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, |
| 771 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 772 | IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm", |
| 773 | [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> { |
Johnny Chen | 15b423f | 2010-02-08 22:02:41 +0000 | [diff] [blame] | 774 | let Inst{7} = 0; // Z bit |
| 775 | } |
Nate Begeman | d1fb583 | 2010-08-03 21:31:55 +0000 | [diff] [blame] | 776 | } |
Johnny Chen | 15b423f | 2010-02-08 22:02:41 +0000 | [diff] [blame] | 777 | |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 778 | // Convert between floating-point and fixed-point |
| 779 | // Data type for fixed-point naming convention: |
| 780 | // S16 (U=0, sx=0) -> SH |
| 781 | // U16 (U=1, sx=0) -> UH |
| 782 | // S32 (U=0, sx=1) -> SL |
| 783 | // U32 (U=1, sx=1) -> UL |
| 784 | |
Bill Wendling | 160acca | 2010-11-01 23:11:22 +0000 | [diff] [blame] | 785 | // FIXME: Marking these as codegen only seems wrong. They are real |
| 786 | // instructions(?) |
| 787 | let Constraints = "$a = $dst", isCodeGenOnly = 1 in { |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 788 | |
| 789 | // FP to Fixed-Point: |
| 790 | |
| 791 | def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0, |
Bill Wendling | cd944a4 | 2010-11-01 23:17:54 +0000 | [diff] [blame] | 792 | (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 793 | IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 794 | [/* For disassembly only; pattern left blank */]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 795 | // Some single precision VFP instructions may be executed on both NEON and |
| 796 | // VFP pipelines on A8. |
| 797 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 798 | } |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 799 | |
| 800 | def VTOUHS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 0, |
| 801 | (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), |
| 802 | IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 803 | [/* For disassembly only; pattern left blank */]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 804 | // Some single precision VFP instructions may be executed on both NEON and |
| 805 | // VFP pipelines on A8. |
| 806 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 807 | } |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 808 | |
| 809 | def VTOSLS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 1, |
| 810 | (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), |
| 811 | IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 812 | [/* For disassembly only; pattern left blank */]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 813 | // Some single precision VFP instructions may be executed on both NEON and |
| 814 | // VFP pipelines on A8. |
| 815 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 816 | } |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 817 | |
| 818 | def VTOULS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 1, |
| 819 | (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), |
| 820 | IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 821 | [/* For disassembly only; pattern left blank */]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 822 | // Some single precision VFP instructions may be executed on both NEON and |
| 823 | // VFP pipelines on A8. |
| 824 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 825 | } |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 826 | |
| 827 | def VTOSHD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 0, |
| 828 | (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), |
| 829 | IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", |
| 830 | [/* For disassembly only; pattern left blank */]>; |
| 831 | |
| 832 | def VTOUHD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 0, |
| 833 | (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), |
| 834 | IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", |
| 835 | [/* For disassembly only; pattern left blank */]>; |
| 836 | |
| 837 | def VTOSLD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 1, |
| 838 | (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), |
| 839 | IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", |
| 840 | [/* For disassembly only; pattern left blank */]>; |
| 841 | |
| 842 | def VTOULD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 1, |
| 843 | (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), |
| 844 | IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", |
| 845 | [/* For disassembly only; pattern left blank */]>; |
| 846 | |
| 847 | // Fixed-Point to FP: |
| 848 | |
| 849 | def VSHTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 0, |
| 850 | (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), |
| 851 | IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 852 | [/* For disassembly only; pattern left blank */]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 853 | // Some single precision VFP instructions may be executed on both NEON and |
| 854 | // VFP pipelines on A8. |
| 855 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 856 | } |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 857 | |
| 858 | def VUHTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 0, |
| 859 | (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), |
| 860 | IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 861 | [/* For disassembly only; pattern left blank */]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 862 | // Some single precision VFP instructions may be executed on both NEON and |
| 863 | // VFP pipelines on A8. |
| 864 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 865 | } |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 866 | |
| 867 | def VSLTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 1, |
| 868 | (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), |
| 869 | IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 870 | [/* For disassembly only; pattern left blank */]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 871 | // Some single precision VFP instructions may be executed on both NEON and |
| 872 | // VFP pipelines on A8. |
| 873 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 874 | } |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 875 | |
| 876 | def VULTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 1, |
| 877 | (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), |
| 878 | IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 879 | [/* For disassembly only; pattern left blank */]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 880 | // Some single precision VFP instructions may be executed on both NEON and |
| 881 | // VFP pipelines on A8. |
| 882 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 883 | } |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 884 | |
| 885 | def VSHTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 0, |
| 886 | (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), |
| 887 | IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", |
| 888 | [/* For disassembly only; pattern left blank */]>; |
| 889 | |
| 890 | def VUHTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 0, |
| 891 | (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), |
| 892 | IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", |
| 893 | [/* For disassembly only; pattern left blank */]>; |
| 894 | |
| 895 | def VSLTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 1, |
| 896 | (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), |
| 897 | IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", |
| 898 | [/* For disassembly only; pattern left blank */]>; |
| 899 | |
| 900 | def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1, |
| 901 | (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), |
| 902 | IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", |
| 903 | [/* For disassembly only; pattern left blank */]>; |
| 904 | |
Bill Wendling | 160acca | 2010-11-01 23:11:22 +0000 | [diff] [blame] | 905 | } // End of 'let Constraints = "$a = $dst", isCodeGenOnly = 1 in' |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 906 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 907 | //===----------------------------------------------------------------------===// |
Cameron Zwarich | 375db7f | 2011-07-07 08:28:52 +0000 | [diff] [blame] | 908 | // FP Multiply-Accumulate Operations. |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 909 | // |
| 910 | |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 911 | def VMLAD : ADbI<0b11100, 0b00, 0, 0, |
| 912 | (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), |
| 913 | IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 914 | [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), |
| 915 | (f64 DPR:$Ddin)))]>, |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 916 | RegConstraint<"$Ddin = $Dd">, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 917 | Requires<[HasVFP2,UseFPVMLx]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 918 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 919 | def VMLAS : ASbIn<0b11100, 0b00, 0, 0, |
| 920 | (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), |
| 921 | IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 922 | [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), |
| 923 | SPR:$Sdin))]>, |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 924 | RegConstraint<"$Sdin = $Sd">, |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 925 | Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 926 | // Some single precision VFP instructions may be executed on both NEON and |
| 927 | // VFP pipelines on A8. |
| 928 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 929 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 930 | |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 931 | def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 932 | (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 933 | Requires<[HasVFP2,UseFPVMLx]>; |
| 934 | def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 935 | (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 936 | Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 937 | |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 938 | def VMLSD : ADbI<0b11100, 0b00, 1, 0, |
| 939 | (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), |
| 940 | IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 941 | [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), |
| 942 | (f64 DPR:$Ddin)))]>, |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 943 | RegConstraint<"$Ddin = $Dd">, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 944 | Requires<[HasVFP2,UseFPVMLx]>; |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 945 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 946 | def VMLSS : ASbIn<0b11100, 0b00, 1, 0, |
| 947 | (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), |
| 948 | IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 949 | [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), |
| 950 | SPR:$Sdin))]>, |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 951 | RegConstraint<"$Sdin = $Sd">, |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 952 | Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 953 | // Some single precision VFP instructions may be executed on both NEON and |
| 954 | // VFP pipelines on A8. |
| 955 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 956 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 957 | |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 958 | def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 959 | (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 960 | Requires<[HasVFP2,UseFPVMLx]>; |
| 961 | def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 962 | (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 963 | Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; |
David Goodwin | b84f3d4 | 2009-08-04 18:44:29 +0000 | [diff] [blame] | 964 | |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 965 | def VNMLAD : ADbI<0b11100, 0b01, 1, 0, |
| 966 | (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), |
| 967 | IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 968 | [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), |
| 969 | (f64 DPR:$Ddin)))]>, |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 970 | RegConstraint<"$Ddin = $Dd">, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 971 | Requires<[HasVFP2,UseFPVMLx]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 972 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 973 | def VNMLAS : ASbI<0b11100, 0b01, 1, 0, |
| 974 | (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), |
| 975 | IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 976 | [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), |
| 977 | SPR:$Sdin))]>, |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 978 | RegConstraint<"$Sdin = $Sd">, |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 979 | Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 980 | // Some single precision VFP instructions may be executed on both NEON and |
| 981 | // VFP pipelines on A8. |
| 982 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 983 | } |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 984 | |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 985 | def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 986 | (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 987 | Requires<[HasVFP2,UseFPVMLx]>; |
| 988 | def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 989 | (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 990 | Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 991 | |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 992 | def VNMLSD : ADbI<0b11100, 0b01, 0, 0, |
| 993 | (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), |
| 994 | IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 995 | [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), |
| 996 | (f64 DPR:$Ddin)))]>, |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 997 | RegConstraint<"$Ddin = $Dd">, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 998 | Requires<[HasVFP2,UseFPVMLx]>; |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 999 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 1000 | def VNMLSS : ASbI<0b11100, 0b01, 0, 0, |
| 1001 | (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), |
| 1002 | IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 1003 | [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 1004 | RegConstraint<"$Sdin = $Sd">, |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 1005 | Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> { |
Evan Cheng | 6557bce | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 1006 | // Some single precision VFP instructions may be executed on both NEON and |
| 1007 | // VFP pipelines on A8. |
| 1008 | let D = VFPNeonA8Domain; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 1009 | } |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 1010 | |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 1011 | def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 1012 | (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 1013 | Requires<[HasVFP2,UseFPVMLx]>; |
| 1014 | def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 1015 | (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 1016 | Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 1017 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1018 | |
| 1019 | //===----------------------------------------------------------------------===// |
| 1020 | // FP Conditional moves. |
| 1021 | // |
| 1022 | |
Evan Cheng | 020cc1b | 2010-05-13 00:16:46 +0000 | [diff] [blame] | 1023 | let neverHasSideEffects = 1 in { |
Jim Grosbach | f219f31 | 2011-03-11 23:09:50 +0000 | [diff] [blame] | 1024 | def VMOVDcc : ARMPseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, pred:$p), |
Owen Anderson | 1688441 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1025 | 4, IIC_fpUNA64, |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 1026 | [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>, |
| 1027 | RegConstraint<"$Dn = $Dd">; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1028 | |
Jim Grosbach | f219f31 | 2011-03-11 23:09:50 +0000 | [diff] [blame] | 1029 | def VMOVScc : ARMPseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, pred:$p), |
Owen Anderson | 1688441 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1030 | 4, IIC_fpUNA32, |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 1031 | [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>, |
| 1032 | RegConstraint<"$Sn = $Sd">; |
Evan Cheng | 020cc1b | 2010-05-13 00:16:46 +0000 | [diff] [blame] | 1033 | } // neverHasSideEffects |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 1034 | |
| 1035 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | 6150590 | 2011-01-18 21:58:20 +0000 | [diff] [blame] | 1036 | // Move from VFP System Register to ARM core register. |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 1037 | // |
| 1038 | |
Bruno Cardoso Lopes | 6150590 | 2011-01-18 21:58:20 +0000 | [diff] [blame] | 1039 | class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, |
| 1040 | list<dag> pattern>: |
| 1041 | VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 1042 | |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 1043 | // Instruction operand. |
| 1044 | bits<4> Rt; |
| 1045 | |
Johnny Chen | c974504 | 2010-02-09 22:35:38 +0000 | [diff] [blame] | 1046 | let Inst{27-20} = 0b11101111; |
Bruno Cardoso Lopes | 6150590 | 2011-01-18 21:58:20 +0000 | [diff] [blame] | 1047 | let Inst{19-16} = opc19_16; |
| 1048 | let Inst{15-12} = Rt; |
Johnny Chen | c974504 | 2010-02-09 22:35:38 +0000 | [diff] [blame] | 1049 | let Inst{11-8} = 0b1010; |
| 1050 | let Inst{7} = 0; |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 1051 | let Inst{6-5} = 0b00; |
Johnny Chen | c974504 | 2010-02-09 22:35:38 +0000 | [diff] [blame] | 1052 | let Inst{4} = 1; |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 1053 | let Inst{3-0} = 0b0000; |
Johnny Chen | c974504 | 2010-02-09 22:35:38 +0000 | [diff] [blame] | 1054 | } |
Johnny Chen | c974504 | 2010-02-09 22:35:38 +0000 | [diff] [blame] | 1055 | |
Bruno Cardoso Lopes | 6150590 | 2011-01-18 21:58:20 +0000 | [diff] [blame] | 1056 | // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags |
| 1057 | // to APSR. |
| 1058 | let Defs = [CPSR], Uses = [FPSCR], Rt = 0b1111 /* apsr_nzcv */ in |
| 1059 | def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins), |
| 1060 | "vmrs", "\tapsr_nzcv, fpscr", [(arm_fmstat)]>; |
| 1061 | |
| 1062 | // Application level FPSCR -> GPR |
| 1063 | let hasSideEffects = 1, Uses = [FPSCR] in |
| 1064 | def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins), |
| 1065 | "vmrs", "\t$Rt, fpscr", |
| 1066 | [(set GPR:$Rt, (int_arm_get_fpscr))]>; |
| 1067 | |
| 1068 | // System level FPEXC, FPSID -> GPR |
| 1069 | let Uses = [FPSCR] in { |
| 1070 | def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins), |
| 1071 | "vmrs", "\t$Rt, fpexc", []>; |
| 1072 | def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins), |
| 1073 | "vmrs", "\t$Rt, fpsid", []>; |
| 1074 | } |
| 1075 | |
| 1076 | //===----------------------------------------------------------------------===// |
| 1077 | // Move from ARM core register to VFP System Register. |
| 1078 | // |
| 1079 | |
| 1080 | class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, |
| 1081 | list<dag> pattern>: |
| 1082 | VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { |
| 1083 | |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 1084 | // Instruction operand. |
| 1085 | bits<4> src; |
| 1086 | |
| 1087 | // Encode instruction operand. |
| 1088 | let Inst{15-12} = src; |
| 1089 | |
Johnny Chen | c974504 | 2010-02-09 22:35:38 +0000 | [diff] [blame] | 1090 | let Inst{27-20} = 0b11101110; |
Bruno Cardoso Lopes | 6150590 | 2011-01-18 21:58:20 +0000 | [diff] [blame] | 1091 | let Inst{19-16} = opc19_16; |
Johnny Chen | c974504 | 2010-02-09 22:35:38 +0000 | [diff] [blame] | 1092 | let Inst{11-8} = 0b1010; |
| 1093 | let Inst{7} = 0; |
| 1094 | let Inst{4} = 1; |
| 1095 | } |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 1096 | |
Bruno Cardoso Lopes | 6150590 | 2011-01-18 21:58:20 +0000 | [diff] [blame] | 1097 | let Defs = [FPSCR] in { |
| 1098 | // Application level GPR -> FPSCR |
| 1099 | def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src), |
| 1100 | "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>; |
| 1101 | // System level GPR -> FPEXC |
| 1102 | def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src), |
| 1103 | "vmsr", "\tfpexc, $src", []>; |
| 1104 | // System level GPR -> FPSID |
| 1105 | def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src), |
| 1106 | "vmsr", "\tfpsid, $src", []>; |
| 1107 | } |
| 1108 | |
| 1109 | //===----------------------------------------------------------------------===// |
| 1110 | // Misc. |
| 1111 | // |
| 1112 | |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 1113 | // Materialize FP immediates. VFP3 only. |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 1114 | let isReMaterializable = 1 in { |
Bill Wendling | bbbdcd4 | 2010-10-14 02:33:26 +0000 | [diff] [blame] | 1115 | def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm), |
Anton Korobeynikov | 63401e3 | 2010-04-07 18:19:56 +0000 | [diff] [blame] | 1116 | VFPMiscFrm, IIC_fpUNA64, |
Bill Wendling | bbbdcd4 | 2010-10-14 02:33:26 +0000 | [diff] [blame] | 1117 | "vmov", ".f64\t$Dd, $imm", |
| 1118 | [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> { |
Jim Grosbach | 4ebbf7b | 2011-09-30 00:50:06 +0000 | [diff] [blame^] | 1119 | bits<5> Dd; |
| 1120 | bits<8> imm; |
Bill Wendling | bbbdcd4 | 2010-10-14 02:33:26 +0000 | [diff] [blame] | 1121 | |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 1122 | let Inst{27-23} = 0b11101; |
Jim Grosbach | 4ebbf7b | 2011-09-30 00:50:06 +0000 | [diff] [blame^] | 1123 | let Inst{22} = Dd{4}; |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 1124 | let Inst{21-20} = 0b11; |
Jim Grosbach | 4ebbf7b | 2011-09-30 00:50:06 +0000 | [diff] [blame^] | 1125 | let Inst{19-16} = imm{7-4}; |
| 1126 | let Inst{15-12} = Dd{3-0}; |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 1127 | let Inst{11-9} = 0b101; |
Bill Wendling | bbbdcd4 | 2010-10-14 02:33:26 +0000 | [diff] [blame] | 1128 | let Inst{8} = 1; // Double precision. |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 1129 | let Inst{7-4} = 0b0000; |
Jim Grosbach | 4ebbf7b | 2011-09-30 00:50:06 +0000 | [diff] [blame^] | 1130 | let Inst{3-0} = imm{3-0}; |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 1131 | } |
| 1132 | |
Bill Wendling | bbbdcd4 | 2010-10-14 02:33:26 +0000 | [diff] [blame] | 1133 | def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm), |
| 1134 | VFPMiscFrm, IIC_fpUNA32, |
| 1135 | "vmov", ".f32\t$Sd, $imm", |
| 1136 | [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> { |
Jim Grosbach | 4ebbf7b | 2011-09-30 00:50:06 +0000 | [diff] [blame^] | 1137 | bits<5> Sd; |
| 1138 | bits<8> imm; |
Bill Wendling | bbbdcd4 | 2010-10-14 02:33:26 +0000 | [diff] [blame] | 1139 | |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 1140 | let Inst{27-23} = 0b11101; |
Jim Grosbach | 4ebbf7b | 2011-09-30 00:50:06 +0000 | [diff] [blame^] | 1141 | let Inst{22} = Sd{0}; |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 1142 | let Inst{21-20} = 0b11; |
Jim Grosbach | 4ebbf7b | 2011-09-30 00:50:06 +0000 | [diff] [blame^] | 1143 | let Inst{19-16} = imm{7-4}; |
| 1144 | let Inst{15-12} = Sd{4-1}; |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 1145 | let Inst{11-9} = 0b101; |
Bill Wendling | bbbdcd4 | 2010-10-14 02:33:26 +0000 | [diff] [blame] | 1146 | let Inst{8} = 0; // Single precision. |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 1147 | let Inst{7-4} = 0b0000; |
Jim Grosbach | 4ebbf7b | 2011-09-30 00:50:06 +0000 | [diff] [blame^] | 1148 | let Inst{3-0} = imm{3-0}; |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 1149 | } |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 1150 | } |