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Scott Michel266bc8f2007-12-04 22:23:35 +00001//===-- SPUHazardRecognizers.cpp - Cell Hazard Recognizer Impls -----------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by a team from the Computer Systems Research
Scott Michel2466c372007-12-05 01:40:25 +00006// Department at The Aerospace Corporation and is distributed under the
7// University of Illinois Open Source License. See LICENSE.TXT for details.
Scott Michel266bc8f2007-12-04 22:23:35 +00008//
9//===----------------------------------------------------------------------===//
10//
11// This file implements hazard recognizers for scheduling on Cell SPU
12// processors.
13//
14//===----------------------------------------------------------------------===//
15
16#define DEBUG_TYPE "sched"
17
18#include "SPUHazardRecognizers.h"
19#include "SPU.h"
20#include "SPUInstrInfo.h"
21#include "llvm/Support/Debug.h"
22
23using namespace llvm;
24
25//===----------------------------------------------------------------------===//
26// Cell SPU hazard recognizer
27//
28// This is the pipeline hazard recognizer for the Cell SPU processor. It does
29// very little right now.
30//===----------------------------------------------------------------------===//
31
32SPUHazardRecognizer::SPUHazardRecognizer(const TargetInstrInfo &tii) :
33 TII(tii),
34 EvenOdd(0)
35{
36}
37
38/// Return the pipeline hazard type encountered or generated by this
39/// instruction. Currently returns NoHazard.
40///
41/// \return NoHazard
42HazardRecognizer::HazardType
43SPUHazardRecognizer::getHazardType(SDNode *Node)
44{
45 // Initial thoughts on how to do this, but this code cannot work unless the
46 // function's prolog and epilog code are also being scheduled so that we can
47 // accurately determine which pipeline is being scheduled.
48#if 0
49 HazardRecognizer::HazardType retval = NoHazard;
50 bool mustBeOdd = false;
51
52 switch (Node->getOpcode()) {
53 case SPU::LQDv16i8:
54 case SPU::LQDv8i16:
55 case SPU::LQDv4i32:
56 case SPU::LQDv4f32:
57 case SPU::LQDv2f64:
58 case SPU::LQDr128:
59 case SPU::LQDr64:
60 case SPU::LQDr32:
61 case SPU::LQDr16:
62 case SPU::LQAv16i8:
63 case SPU::LQAv8i16:
64 case SPU::LQAv4i32:
65 case SPU::LQAv4f32:
66 case SPU::LQAv2f64:
67 case SPU::LQAr128:
68 case SPU::LQAr64:
69 case SPU::LQAr32:
70 case SPU::LQXv4i32:
71 case SPU::LQXr128:
72 case SPU::LQXr64:
73 case SPU::LQXr32:
74 case SPU::LQXr16:
75 case SPU::STQDv16i8:
76 case SPU::STQDv8i16:
77 case SPU::STQDv4i32:
78 case SPU::STQDv4f32:
79 case SPU::STQDv2f64:
80 case SPU::STQDr128:
81 case SPU::STQDr64:
82 case SPU::STQDr32:
83 case SPU::STQDr16:
84 case SPU::STQDr8:
85 case SPU::STQAv16i8:
86 case SPU::STQAv8i16:
87 case SPU::STQAv4i32:
88 case SPU::STQAv4f32:
89 case SPU::STQAv2f64:
90 case SPU::STQAr128:
91 case SPU::STQAr64:
92 case SPU::STQAr32:
93 case SPU::STQAr16:
94 case SPU::STQAr8:
95 case SPU::STQXv16i8:
96 case SPU::STQXv8i16:
97 case SPU::STQXv4i32:
98 case SPU::STQXv4f32:
99 case SPU::STQXv2f64:
100 case SPU::STQXr128:
101 case SPU::STQXr64:
102 case SPU::STQXr32:
103 case SPU::STQXr16:
104 case SPU::STQXr8:
105 case SPU::RET:
106 mustBeOdd = true;
107 break;
108 default:
109 // Assume that this instruction can be on the even pipe
110 break;
111 }
112
113 if (mustBeOdd && !EvenOdd)
114 retval = Hazard;
115
116 DOUT << "SPUHazardRecognizer EvenOdd " << EvenOdd << " Hazard " << retval << "\n";
117 EvenOdd ^= 1;
118 return retval;
119#else
120 return NoHazard;
121#endif
122}
123
124void SPUHazardRecognizer::EmitInstruction(SDNode *Node)
125{
126}
127
128void SPUHazardRecognizer::AdvanceCycle()
129{
130 DOUT << "SPUHazardRecognizer::AdvanceCycle\n";
131}
132
133void SPUHazardRecognizer::EmitNoop()
134{
135 AdvanceCycle();
136}