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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 4f2f3f6dce7d350282947012884573f9ef19677c / . / lib / Target / Alpha / AlphaInstrInfo.h
blob: 20d6388e737e07b1a65c4141220c709f24c056dc [file] [log] [blame]
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1//===- AlphaInstrInfo.h - Alpha Instruction Information ---------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner081ce942007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Alpha implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ALPHAINSTRUCTIONINFO_H
15#define ALPHAINSTRUCTIONINFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18#include "AlphaRegisterInfo.h"
19
20namespace llvm {
21
Chris Lattnerd2fd6db2008-01-01 01:03:04 +0000[diff] [blame]22class AlphaInstrInfo : public TargetInstrInfoImpl {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]23 const AlphaRegisterInfo RI;
24public:
25 AlphaInstrInfo();
26
27 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
28 /// such, whenever a client has an instance of instruction info, it should
29 /// always be able to get register info as well (through this method).
30 ///
31 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
32
33 /// Return true if the instruction is a register to register move and
34 /// leave the source and dest operands in the passed parameters.
35 ///
36 virtual bool isMoveInstr(const MachineInstr &MI,
37 unsigned &SrcReg, unsigned &DstReg) const;
38
39 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
40 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
41
42 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
43 MachineBasicBlock *FBB,
44 const std::vector<MachineOperand> &Cond) const;
Owen Anderson8f2c8932007-12-31 06:32:00 +0000[diff] [blame]45 virtual void copyRegToReg(MachineBasicBlock &MBB,
46 MachineBasicBlock::iterator MI,
47 unsigned DestReg, unsigned SrcReg,
48 const TargetRegisterClass *DestRC,
49 const TargetRegisterClass *SrcRC) const;
Owen Anderson81875432008-01-01 21:11:32 +0000[diff] [blame]50 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator MBBI,
52 unsigned SrcReg, bool isKill, int FrameIndex,
53 const TargetRegisterClass *RC) const;
54
55 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
56 SmallVectorImpl<MachineOperand> &Addr,
57 const TargetRegisterClass *RC,
58 SmallVectorImpl<MachineInstr*> &NewMIs) const;
59
60 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator MBBI,
62 unsigned DestReg, int FrameIndex,
63 const TargetRegisterClass *RC) const;
64
65 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
66 SmallVectorImpl<MachineOperand> &Addr,
67 const TargetRegisterClass *RC,
68 SmallVectorImpl<MachineInstr*> &NewMIs) const;
Owen Anderson9a184ef2008-01-07 01:35:02 +0000[diff] [blame]69
Evan Cheng4f2f3f62008-02-08 21:20:40 +0000[diff] [blame^]70 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
71 MachineInstr* MI,
Owen Anderson9a184ef2008-01-07 01:35:02 +0000[diff] [blame]72 SmallVectorImpl<unsigned> &Ops,
73 int FrameIndex) const;
74
Evan Cheng4f2f3f62008-02-08 21:20:40 +0000[diff] [blame^]75 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
76 MachineInstr* MI,
Owen Anderson9a184ef2008-01-07 01:35:02 +0000[diff] [blame]77 SmallVectorImpl<unsigned> &Ops,
78 MachineInstr* LoadMI) const {
79 return 0;
80 }
81
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]82 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
83 MachineBasicBlock *&FBB,
84 std::vector<MachineOperand> &Cond) const;
85 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
86 void insertNoop(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator MI) const;
88 bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
89 bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
90};
91
92}
93
94#endif