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Evan Chenga8e29892007-01-19 07:51:42 +00001//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00006// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the ARM instructions in TableGen format.
11//
12//===----------------------------------------------------------------------===//
13
Evan Chenga8e29892007-01-19 07:51:42 +000014//===----------------------------------------------------------------------===//
15// ARM specific DAG Nodes.
16//
Rafael Espindola7cca7c52006-09-11 17:25:40 +000017
Evan Chenga8e29892007-01-19 07:51:42 +000018// Type profiles.
Bill Wendlingc69107c2007-11-13 09:19:02 +000019def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
Rafael Espindola6e8c6492006-11-08 17:07:32 +000021
Evan Chenga8e29892007-01-19 07:51:42 +000022def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
Rafael Espindola32bd5f42006-10-17 18:04:53 +000023
Evan Chenga8e29892007-01-19 07:51:42 +000024def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
Rafael Espindola7cca7c52006-09-11 17:25:40 +000025
Evan Chenga8e29892007-01-19 07:51:42 +000026def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
28 SDTCisVT<3, i32>]>;
Rafael Espindola6e8c6492006-11-08 17:07:32 +000029
Evan Chenga8e29892007-01-19 07:51:42 +000030def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
32
33def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
35 SDTCisVT<2, i32>]>;
36
37def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
38
39def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
41
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +000042def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
Jim Grosbachf9570122009-05-14 00:46:35 +000043def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +000044
Evan Chenga8e29892007-01-19 07:51:42 +000045// Node definitions.
46def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
Evan Chenga8e29892007-01-19 07:51:42 +000047def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
48
Bill Wendlingc69107c2007-11-13 09:19:02 +000049def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
Bill Wendling6ef781f2008-02-27 06:33:05 +000050 [SDNPHasChain, SDNPOutFlag]>;
Bill Wendlingc69107c2007-11-13 09:19:02 +000051def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
Bill Wendling6ef781f2008-02-27 06:33:05 +000052 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Evan Chenga8e29892007-01-19 07:51:42 +000053
54def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
55 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Evan Cheng277f0742007-06-19 21:05:09 +000056def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
57 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Evan Chenga8e29892007-01-19 07:51:42 +000058def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60
Chris Lattner48be23c2008-01-15 22:02:54 +000061def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
Evan Chenga8e29892007-01-19 07:51:42 +000062 [SDNPHasChain, SDNPOptInFlag]>;
63
64def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
65 [SDNPInFlag]>;
66def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
67 [SDNPInFlag]>;
68
69def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
70 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
71
72def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
73 [SDNPHasChain]>;
74
75def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
76 [SDNPOutFlag]>;
77
Lauro Ramos Venancio99966632007-04-02 01:30:03 +000078def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
79 [SDNPOutFlag]>;
80
Evan Chenga8e29892007-01-19 07:51:42 +000081def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
82
83def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
84def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
85def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
Rafael Espindola32bd5f42006-10-17 18:04:53 +000086
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +000087def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
Jim Grosbachf9570122009-05-14 00:46:35 +000088def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +000089
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000090//===----------------------------------------------------------------------===//
Evan Chenga8e29892007-01-19 07:51:42 +000091// ARM Instruction Predicate Definitions.
92//
Anton Korobeynikovbb629622009-06-15 21:46:20 +000093def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
94def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
95def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
96def IsThumb : Predicate<"Subtarget->isThumb()">;
97def HasThumb2 : Predicate<"Subtarget->hasThumb2()">;
98def IsARM : Predicate<"!Subtarget->isThumb()">;
Evan Chenga8e29892007-01-19 07:51:42 +000099
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000100//===----------------------------------------------------------------------===//
Evan Chenga8e29892007-01-19 07:51:42 +0000101// ARM Flag Definitions.
102
103class RegConstraint<string C> {
104 string Constraints = C;
105}
106
107//===----------------------------------------------------------------------===//
108// ARM specific transformation functions and pattern fragments.
109//
110
111// so_imm_XFORM - Return a so_imm value packed into the format described for
112// so_imm def below.
113def so_imm_XFORM : SDNodeXForm<imm, [{
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000114 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getZExtValue()),
Evan Chenga8e29892007-01-19 07:51:42 +0000115 MVT::i32);
116}]>;
117
118// so_imm_neg_XFORM - Return a so_imm value packed into the format described for
119// so_imm_neg def below.
120def so_imm_neg_XFORM : SDNodeXForm<imm, [{
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000121 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getZExtValue()),
Evan Chenga8e29892007-01-19 07:51:42 +0000122 MVT::i32);
123}]>;
124
125// so_imm_not_XFORM - Return a so_imm value packed into the format described for
126// so_imm_not def below.
127def so_imm_not_XFORM : SDNodeXForm<imm, [{
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000128 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getZExtValue()),
Evan Chenga8e29892007-01-19 07:51:42 +0000129 MVT::i32);
130}]>;
131
132// rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
133def rot_imm : PatLeaf<(i32 imm), [{
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000134 int32_t v = (int32_t)N->getZExtValue();
Evan Chenga8e29892007-01-19 07:51:42 +0000135 return v == 8 || v == 16 || v == 24;
136}]>;
137
138/// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
139def imm1_15 : PatLeaf<(i32 imm), [{
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000140 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
Evan Chenga8e29892007-01-19 07:51:42 +0000141}]>;
142
143/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
144def imm16_31 : PatLeaf<(i32 imm), [{
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000145 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
Evan Chenga8e29892007-01-19 07:51:42 +0000146}]>;
147
148def so_imm_neg :
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000149 PatLeaf<(imm), [{
150 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
151 }], so_imm_neg_XFORM>;
Evan Chenga8e29892007-01-19 07:51:42 +0000152
Evan Chenga2515702007-03-19 07:09:02 +0000153def so_imm_not :
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000154 PatLeaf<(imm), [{
155 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
156 }], so_imm_not_XFORM>;
Evan Chenga8e29892007-01-19 07:51:42 +0000157
158// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
159def sext_16_node : PatLeaf<(i32 GPR:$a), [{
Dan Gohman475871a2008-07-27 21:46:04 +0000160 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
Evan Chenga8e29892007-01-19 07:51:42 +0000161}]>;
162
Evan Cheng37f25d92008-08-28 23:39:26 +0000163class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
164class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
Evan Chenga8e29892007-01-19 07:51:42 +0000165
166//===----------------------------------------------------------------------===//
167// Operand Definitions.
168//
169
170// Branch target.
171def brtarget : Operand<OtherVT>;
172
Evan Chenga8e29892007-01-19 07:51:42 +0000173// A list of registers separated by comma. Used by load/store multiple.
174def reglist : Operand<i32> {
175 let PrintMethod = "printRegisterList";
176}
177
178// An operand for the CONSTPOOL_ENTRY pseudo-instruction.
179def cpinst_operand : Operand<i32> {
180 let PrintMethod = "printCPInstOperand";
181}
182
183def jtblock_operand : Operand<i32> {
184 let PrintMethod = "printJTBlockOperand";
185}
186
187// Local PC labels.
188def pclabel : Operand<i32> {
189 let PrintMethod = "printPCLabel";
190}
191
192// shifter_operand operands: so_reg and so_imm.
193def so_reg : Operand<i32>, // reg reg imm
194 ComplexPattern<i32, 3, "SelectShifterOperandReg",
195 [shl,srl,sra,rotr]> {
196 let PrintMethod = "printSORegOperand";
197 let MIOperandInfo = (ops GPR, GPR, i32imm);
198}
199
200// so_imm - Match a 32-bit shifter_operand immediate operand, which is an
201// 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
202// represented in the imm field in the same 12-bit form that they are encoded
203// into so_imm instructions: the 8-bit immediate is the least significant bits
204// [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
205def so_imm : Operand<i32>,
206 PatLeaf<(imm),
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000207 [{ return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; }],
Evan Chenga8e29892007-01-19 07:51:42 +0000208 so_imm_XFORM> {
209 let PrintMethod = "printSOImmOperand";
210}
211
Evan Chengc70d1842007-03-20 08:11:30 +0000212// Break so_imm's up into two pieces. This handles immediates with up to 16
213// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
214// get the first/second pieces.
215def so_imm2part : Operand<i32>,
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000216 PatLeaf<(imm), [{
217 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
218 }]> {
Evan Chengc70d1842007-03-20 08:11:30 +0000219 let PrintMethod = "printSOImm2PartOperand";
220}
221
222def so_imm2part_1 : SDNodeXForm<imm, [{
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000223 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
Evan Chengc70d1842007-03-20 08:11:30 +0000224 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
225}]>;
226
227def so_imm2part_2 : SDNodeXForm<imm, [{
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000228 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
Evan Chengc70d1842007-03-20 08:11:30 +0000229 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
230}]>;
231
Evan Chenga8e29892007-01-19 07:51:42 +0000232
233// Define ARM specific addressing modes.
234
235// addrmode2 := reg +/- reg shop imm
236// addrmode2 := reg +/- imm12
237//
238def addrmode2 : Operand<i32>,
239 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
240 let PrintMethod = "printAddrMode2Operand";
241 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
242}
243
244def am2offset : Operand<i32>,
245 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
246 let PrintMethod = "printAddrMode2OffsetOperand";
247 let MIOperandInfo = (ops GPR, i32imm);
248}
249
250// addrmode3 := reg +/- reg
251// addrmode3 := reg +/- imm8
252//
253def addrmode3 : Operand<i32>,
254 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
255 let PrintMethod = "printAddrMode3Operand";
256 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
257}
258
259def am3offset : Operand<i32>,
260 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
261 let PrintMethod = "printAddrMode3OffsetOperand";
262 let MIOperandInfo = (ops GPR, i32imm);
263}
264
265// addrmode4 := reg, <mode|W>
266//
267def addrmode4 : Operand<i32>,
268 ComplexPattern<i32, 2, "", []> {
269 let PrintMethod = "printAddrMode4Operand";
270 let MIOperandInfo = (ops GPR, i32imm);
271}
272
273// addrmode5 := reg +/- imm8*4
274//
275def addrmode5 : Operand<i32>,
276 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
277 let PrintMethod = "printAddrMode5Operand";
278 let MIOperandInfo = (ops GPR, i32imm);
279}
280
281// addrmodepc := pc + reg
282//
283def addrmodepc : Operand<i32>,
284 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
285 let PrintMethod = "printAddrModePCOperand";
286 let MIOperandInfo = (ops GPR, i32imm);
287}
288
Evan Chengc85e8322007-07-05 07:13:32 +0000289// ARM Predicate operand. Default to 14 = always (AL). Second part is CC
290// register whose default is 0 (no register).
291def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
292 (ops (i32 14), (i32 zero_reg))> {
Evan Cheng42d712b2007-05-08 21:08:43 +0000293 let PrintMethod = "printPredicateOperand";
294}
295
Evan Cheng04c813d2007-07-06 01:00:49 +0000296// Conditional code result for instructions whose 's' bit is set, e.g. subs.
Evan Chengc85e8322007-07-05 07:13:32 +0000297//
Evan Cheng04c813d2007-07-06 01:00:49 +0000298def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
299 let PrintMethod = "printSBitModifierOperand";
Evan Cheng42d712b2007-05-08 21:08:43 +0000300}
301
Evan Chenga8e29892007-01-19 07:51:42 +0000302//===----------------------------------------------------------------------===//
303// ARM Instruction flags. These need to match ARMInstrInfo.h.
304//
305
306// Addressing mode.
307class AddrMode<bits<4> val> {
308 bits<4> Value = val;
309}
310def AddrModeNone : AddrMode<0>;
311def AddrMode1 : AddrMode<1>;
312def AddrMode2 : AddrMode<2>;
313def AddrMode3 : AddrMode<3>;
314def AddrMode4 : AddrMode<4>;
315def AddrMode5 : AddrMode<5>;
Evan Chengedda31c2008-11-05 18:35:52 +0000316def AddrModeT1 : AddrMode<6>;
317def AddrModeT2 : AddrMode<7>;
318def AddrModeT4 : AddrMode<8>;
319def AddrModeTs : AddrMode<9>;
Evan Chenga8e29892007-01-19 07:51:42 +0000320
321// Instruction size.
322class SizeFlagVal<bits<3> val> {
323 bits<3> Value = val;
324}
325def SizeInvalid : SizeFlagVal<0>; // Unset.
326def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
327def Size8Bytes : SizeFlagVal<2>;
328def Size4Bytes : SizeFlagVal<3>;
329def Size2Bytes : SizeFlagVal<4>;
330
331// Load / store index mode.
332class IndexMode<bits<2> val> {
333 bits<2> Value = val;
334}
335def IndexModeNone : IndexMode<0>;
336def IndexModePre : IndexMode<1>;
337def IndexModePost : IndexMode<2>;
338
339//===----------------------------------------------------------------------===//
Evan Cheng0ff94f72007-08-07 01:37:15 +0000340
Evan Cheng37f25d92008-08-28 23:39:26 +0000341include "ARMInstrFormats.td"
Evan Cheng0ff94f72007-08-07 01:37:15 +0000342
343//===----------------------------------------------------------------------===//
Evan Cheng37f25d92008-08-28 23:39:26 +0000344// Multiclass helpers...
Evan Chenga8e29892007-01-19 07:51:42 +0000345//
346
Evan Cheng3924f782008-08-29 07:36:24 +0000347/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
Evan Chenga8e29892007-01-19 07:51:42 +0000348/// binop that produces a value.
Evan Cheng0ff94f72007-08-07 01:37:15 +0000349multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
Evan Chengedda31c2008-11-05 18:35:52 +0000350 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
Evan Chengc85e8322007-07-05 07:13:32 +0000351 opc, " $dst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000352 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
Evan Chengedda31c2008-11-05 18:35:52 +0000353 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
Evan Chengc85e8322007-07-05 07:13:32 +0000354 opc, " $dst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000355 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
Evan Chengedda31c2008-11-05 18:35:52 +0000356 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
Evan Chengc85e8322007-07-05 07:13:32 +0000357 opc, " $dst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000358 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
359}
360
Evan Cheng13ab0202007-07-10 18:08:01 +0000361/// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
Evan Chengc85e8322007-07-05 07:13:32 +0000362/// instruction modifies the CSPR register.
Evan Cheng071a2792007-09-11 19:55:27 +0000363let Defs = [CPSR] in {
Evan Cheng0ff94f72007-08-07 01:37:15 +0000364multiclass ASI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
Evan Chengedda31c2008-11-05 18:35:52 +0000365 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
Evan Chengc85e8322007-07-05 07:13:32 +0000366 opc, "s $dst, $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000367 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
Evan Chengedda31c2008-11-05 18:35:52 +0000368 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
Evan Chengc85e8322007-07-05 07:13:32 +0000369 opc, "s $dst, $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000370 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
Evan Chengedda31c2008-11-05 18:35:52 +0000371 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
Evan Chengc85e8322007-07-05 07:13:32 +0000372 opc, "s $dst, $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000373 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
374}
Evan Chengc85e8322007-07-05 07:13:32 +0000375}
376
377/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
Evan Cheng13ab0202007-07-10 18:08:01 +0000378/// patterns. Similar to AsI1_bin_irs except the instruction does not produce
Evan Chengc85e8322007-07-05 07:13:32 +0000379/// a explicit result, only implicitly set CPSR.
Evan Cheng071a2792007-09-11 19:55:27 +0000380let Defs = [CPSR] in {
Evan Cheng0ff94f72007-08-07 01:37:15 +0000381multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
Evan Chengedda31c2008-11-05 18:35:52 +0000382 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm,
Evan Cheng44bec522007-05-15 01:29:07 +0000383 opc, " $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000384 [(opnode GPR:$a, so_imm:$b)]>;
Evan Chengedda31c2008-11-05 18:35:52 +0000385 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm,
Evan Cheng44bec522007-05-15 01:29:07 +0000386 opc, " $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000387 [(opnode GPR:$a, GPR:$b)]>;
Evan Chengedda31c2008-11-05 18:35:52 +0000388 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
Evan Cheng44bec522007-05-15 01:29:07 +0000389 opc, " $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000390 [(opnode GPR:$a, so_reg:$b)]>;
391}
Evan Chenga8e29892007-01-19 07:51:42 +0000392}
393
Evan Chenga8e29892007-01-19 07:51:42 +0000394/// AI_unary_rrot - A unary operation with two forms: one whose operand is a
395/// register and one whose operand is a register rotated by 8/16/24.
Evan Cheng97f48c32008-11-06 22:15:19 +0000396/// FIXME: Remove the 'r' variant. Its rot_imm is zero.
397multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
398 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src),
Evan Cheng44bec522007-05-15 01:29:07 +0000399 opc, " $dst, $Src",
Evan Cheng97f48c32008-11-06 22:15:19 +0000400 [(set GPR:$dst, (opnode GPR:$Src))]>,
401 Requires<[IsARM, HasV6]> {
402 let Inst{19-16} = 0b1111;
403 }
404 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
Evan Cheng44bec522007-05-15 01:29:07 +0000405 opc, " $dst, $Src, ror $rot",
Evan Chenga8e29892007-01-19 07:51:42 +0000406 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
Evan Cheng97f48c32008-11-06 22:15:19 +0000407 Requires<[IsARM, HasV6]> {
408 let Inst{19-16} = 0b1111;
409 }
Evan Chenga8e29892007-01-19 07:51:42 +0000410}
411
412/// AI_bin_rrot - A binary operation with two forms: one whose operand is a
413/// register and one whose operand is a register rotated by 8/16/24.
Evan Cheng97f48c32008-11-06 22:15:19 +0000414multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
415 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
416 opc, " $dst, $LHS, $RHS",
Evan Chenga8e29892007-01-19 07:51:42 +0000417 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
418 Requires<[IsARM, HasV6]>;
Evan Cheng97f48c32008-11-06 22:15:19 +0000419 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
420 opc, " $dst, $LHS, $RHS, ror $rot",
Evan Chenga8e29892007-01-19 07:51:42 +0000421 [(set GPR:$dst, (opnode GPR:$LHS,
422 (rotr GPR:$RHS, rot_imm:$rot)))]>,
423 Requires<[IsARM, HasV6]>;
424}
425
Evan Cheng13ab0202007-07-10 18:08:01 +0000426/// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
427/// setting carry bit. But it can optionally set CPSR.
Evan Cheng071a2792007-09-11 19:55:27 +0000428let Uses = [CPSR] in {
Evan Cheng0ff94f72007-08-07 01:37:15 +0000429multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> {
430 def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
Evan Chengedda31c2008-11-05 18:35:52 +0000431 DPFrm, !strconcat(opc, "${s} $dst, $a, $b"),
Evan Cheng071a2792007-09-11 19:55:27 +0000432 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
Evan Cheng0ff94f72007-08-07 01:37:15 +0000433 def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s),
Evan Chengedda31c2008-11-05 18:35:52 +0000434 DPFrm, !strconcat(opc, "${s} $dst, $a, $b"),
Evan Cheng071a2792007-09-11 19:55:27 +0000435 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
Evan Cheng0ff94f72007-08-07 01:37:15 +0000436 def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
Evan Chengedda31c2008-11-05 18:35:52 +0000437 DPSoRegFrm, !strconcat(opc, "${s} $dst, $a, $b"),
Evan Cheng071a2792007-09-11 19:55:27 +0000438 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
439}
Evan Chengc85e8322007-07-05 07:13:32 +0000440}
441
Rafael Espindola15a6c3e2006-10-16 17:57:20 +0000442//===----------------------------------------------------------------------===//
443// Instructions
444//===----------------------------------------------------------------------===//
445
Evan Chenga8e29892007-01-19 07:51:42 +0000446//===----------------------------------------------------------------------===//
447// Miscellaneous Instructions.
448//
Rafael Espindola6f602de2006-08-24 16:13:15 +0000449
Evan Chenga8e29892007-01-19 07:51:42 +0000450/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
451/// the function. The first operand is the ID# for this instruction, the second
452/// is the index into the MachineConstantPool that this is, the third is the
453/// size in bytes of this constant pool entry.
Evan Chengcd799b92009-06-12 20:46:18 +0000454let neverHasSideEffects = 1, isNotDuplicable = 1 in
Evan Chenga8e29892007-01-19 07:51:42 +0000455def CONSTPOOL_ENTRY :
Evan Cheng64d80e32007-07-19 01:14:50 +0000456PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
Evan Cheng12c3a532008-11-06 17:48:05 +0000457 i32imm:$size),
Evan Chenga8e29892007-01-19 07:51:42 +0000458 "${instid:label} ${cpidx:cpentry}", []>;
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000459
Evan Cheng071a2792007-09-11 19:55:27 +0000460let Defs = [SP], Uses = [SP] in {
Evan Chenga8e29892007-01-19 07:51:42 +0000461def ADJCALLSTACKUP :
Bill Wendling0f8d9c02007-11-13 00:44:25 +0000462PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p),
463 "@ ADJCALLSTACKUP $amt1",
Chris Lattnere563bbc2008-10-11 22:08:30 +0000464 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
Rafael Espindolacdda88c2006-08-24 17:19:08 +0000465
Evan Chenga8e29892007-01-19 07:51:42 +0000466def ADJCALLSTACKDOWN :
Evan Cheng64d80e32007-07-19 01:14:50 +0000467PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
Evan Chenga8e29892007-01-19 07:51:42 +0000468 "@ ADJCALLSTACKDOWN $amt",
Chris Lattnere563bbc2008-10-11 22:08:30 +0000469 [(ARMcallseq_start timm:$amt)]>;
Evan Cheng071a2792007-09-11 19:55:27 +0000470}
Rafael Espindola3c000bf2006-08-21 22:00:32 +0000471
Evan Chenga8e29892007-01-19 07:51:42 +0000472def DWARF_LOC :
Evan Cheng64d80e32007-07-19 01:14:50 +0000473PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
Evan Chenga8e29892007-01-19 07:51:42 +0000474 ".loc $file, $line, $col",
475 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
Rafael Espindola4b20fbc2006-10-10 12:56:00 +0000476
Evan Cheng12c3a532008-11-06 17:48:05 +0000477
478// Address computation and loads and stores in PIC mode.
Evan Chengeaa91b02007-06-19 01:26:51 +0000479let isNotDuplicable = 1 in {
Evan Chengc0729662008-10-31 19:11:09 +0000480def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000481 Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
Evan Cheng44bec522007-05-15 01:29:07 +0000482 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
Dale Johannesen86d40692007-05-21 22:14:33 +0000483
Evan Cheng325474e2008-01-07 23:56:57 +0000484let AddedComplexity = 10 in {
Dan Gohman15511cf2008-12-03 18:15:48 +0000485let canFoldAsLoad = 1 in
Evan Chengd87293c2008-11-06 08:47:38 +0000486def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000487 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000488 [(set GPR:$dst, (load addrmodepc:$addr))]>;
Rafael Espindola84b19be2006-07-16 01:02:57 +0000489
Evan Chengd87293c2008-11-06 08:47:38 +0000490def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000491 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
Dale Johannesen86d40692007-05-21 22:14:33 +0000492 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
493
Evan Chengd87293c2008-11-06 08:47:38 +0000494def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000495 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
Dale Johannesen86d40692007-05-21 22:14:33 +0000496 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
497
Evan Chengd87293c2008-11-06 08:47:38 +0000498def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000499 Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
Dale Johannesen86d40692007-05-21 22:14:33 +0000500 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
501
Evan Chengd87293c2008-11-06 08:47:38 +0000502def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000503 Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
Dale Johannesen86d40692007-05-21 22:14:33 +0000504 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
505}
Chris Lattner13c63102008-01-06 05:55:01 +0000506let AddedComplexity = 10 in {
Evan Chengd87293c2008-11-06 08:47:38 +0000507def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000508 Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
Dale Johannesen86d40692007-05-21 22:14:33 +0000509 [(store GPR:$src, addrmodepc:$addr)]>;
510
Evan Chengd87293c2008-11-06 08:47:38 +0000511def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000512 Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
Dale Johannesen86d40692007-05-21 22:14:33 +0000513 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
514
Evan Chengd87293c2008-11-06 08:47:38 +0000515def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000516 Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
Dale Johannesen86d40692007-05-21 22:14:33 +0000517 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
518}
Evan Cheng12c3a532008-11-06 17:48:05 +0000519} // isNotDuplicable = 1
Dale Johannesen86d40692007-05-21 22:14:33 +0000520
Evan Chenga8e29892007-01-19 07:51:42 +0000521//===----------------------------------------------------------------------===//
522// Control Flow Instructions.
523//
Rafael Espindola9e071f02006-10-02 19:30:56 +0000524
Evan Chenga8e29892007-01-19 07:51:42 +0000525let isReturn = 1, isTerminator = 1 in
Evan Cheng12c3a532008-11-06 17:48:05 +0000526 def BX_RET : AI<(outs), (ins), BrMiscFrm, "bx", " lr", [(ARMretflag)]> {
Jim Grosbach26421962008-10-14 20:36:24 +0000527 let Inst{7-4} = 0b0001;
528 let Inst{19-8} = 0b111111111111;
529 let Inst{27-20} = 0b00010010;
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000530}
Rafael Espindola27185192006-09-29 21:20:16 +0000531
Evan Chenga8e29892007-01-19 07:51:42 +0000532// FIXME: remove when we have a way to marking a MI with these properties.
Evan Cheng64d80e32007-07-19 01:14:50 +0000533// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
534// operand list.
Evan Cheng12c3a532008-11-06 17:48:05 +0000535// FIXME: Should pc be an implicit operand like PICADD, etc?
Evan Cheng325474e2008-01-07 23:56:57 +0000536let isReturn = 1, isTerminator = 1 in
Evan Cheng12c3a532008-11-06 17:48:05 +0000537 def LDM_RET : AXI4ld<(outs),
Evan Cheng64d80e32007-07-19 01:14:50 +0000538 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
Evan Cheng3c4a4ff2008-11-12 07:18:38 +0000539 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
Evan Chenga8e29892007-01-19 07:51:42 +0000540 []>;
Rafael Espindolaa2845842006-10-05 16:48:49 +0000541
Evan Chengffbacca2007-07-21 00:34:19 +0000542let isCall = 1,
Evan Chenga8e29892007-01-19 07:51:42 +0000543 Defs = [R0, R1, R2, R3, R12, LR,
Evan Chengc85e8322007-07-05 07:13:32 +0000544 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
Evan Cheng12c3a532008-11-06 17:48:05 +0000545 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
Evan Chengdcc50a42007-05-18 01:53:54 +0000546 "bl ${func:call}",
Evan Cheng44bec522007-05-15 01:29:07 +0000547 [(ARMcall tglobaladdr:$func)]>;
Evan Cheng277f0742007-06-19 21:05:09 +0000548
Evan Cheng12c3a532008-11-06 17:48:05 +0000549 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
Evan Cheng3aac7882008-09-01 08:25:56 +0000550 "bl", " ${func:call}",
Evan Cheng0ff94f72007-08-07 01:37:15 +0000551 [(ARMcall_pred tglobaladdr:$func)]>;
Evan Cheng277f0742007-06-19 21:05:09 +0000552
Evan Chenga8e29892007-01-19 07:51:42 +0000553 // ARMv5T and above
Evan Cheng12c3a532008-11-06 17:48:05 +0000554 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
Evan Cheng64d80e32007-07-19 01:14:50 +0000555 "blx $func",
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000556 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]> {
Jim Grosbach26421962008-10-14 20:36:24 +0000557 let Inst{7-4} = 0b0011;
558 let Inst{19-8} = 0b111111111111;
559 let Inst{27-20} = 0b00010010;
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000560 }
561
Lauro Ramos Venancio64c88d72007-03-20 17:57:23 +0000562 let Uses = [LR] in {
563 // ARMv4T
Evan Cheng12c3a532008-11-06 17:48:05 +0000564 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
565 "mov lr, pc\n\tbx $func",
566 [(ARMcall_nolink GPR:$func)]>;
Lauro Ramos Venancio64c88d72007-03-20 17:57:23 +0000567 }
Rafael Espindola35574632006-07-18 17:00:30 +0000568}
Rafael Espindoladc124a22006-05-18 21:45:49 +0000569
Evan Chengffbacca2007-07-21 00:34:19 +0000570let isBranch = 1, isTerminator = 1 in {
Evan Cheng5ada1992007-05-16 20:50:01 +0000571 // B is "predicable" since it can be xformed into a Bcc.
Evan Chengaeafca02007-05-16 07:45:54 +0000572 let isBarrier = 1 in {
Evan Cheng5ada1992007-05-16 20:50:01 +0000573 let isPredicable = 1 in
Evan Cheng12c3a532008-11-06 17:48:05 +0000574 def B : ABXI<0b1010, (outs), (ins brtarget:$target), "b $target",
Evan Cheng64d80e32007-07-19 01:14:50 +0000575 [(br bb:$target)]>;
Evan Cheng44bec522007-05-15 01:29:07 +0000576
Owen Anderson20ab2902007-11-12 07:39:39 +0000577 let isNotDuplicable = 1, isIndirectBranch = 1 in {
Evan Cheng4df60f52008-11-07 09:06:08 +0000578 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
Evan Cheng64d80e32007-07-19 01:14:50 +0000579 "mov pc, $target \n$jt",
Evan Cheng4df60f52008-11-07 09:06:08 +0000580 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
581 let Inst{20} = 0; // S Bit
582 let Inst{24-21} = 0b1101;
583 let Inst{27-26} = {0,0};
Evan Chengaeafca02007-05-16 07:45:54 +0000584 }
Evan Cheng4df60f52008-11-07 09:06:08 +0000585 def BR_JTm : JTI<(outs),
586 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
587 "ldr pc, $target \n$jt",
588 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
589 imm:$id)]> {
590 let Inst{20} = 1; // L bit
591 let Inst{21} = 0; // W bit
592 let Inst{22} = 0; // B bit
593 let Inst{24} = 1; // P bit
594 let Inst{27-26} = {0,1};
Evan Chengeaa91b02007-06-19 01:26:51 +0000595 }
Evan Cheng4df60f52008-11-07 09:06:08 +0000596 def BR_JTadd : JTI<(outs),
597 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
598 "add pc, $target, $idx \n$jt",
599 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
600 imm:$id)]> {
601 let Inst{20} = 0; // S bit
602 let Inst{24-21} = 0b0100;
603 let Inst{27-26} = {0,0};
604 }
605 } // isNotDuplicable = 1, isIndirectBranch = 1
606 } // isBarrier = 1
Evan Chengaeafca02007-05-16 07:45:54 +0000607
Evan Chengc85e8322007-07-05 07:13:32 +0000608 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
609 // a two-value operand where a dag node expects two operands. :(
Evan Cheng12c3a532008-11-06 17:48:05 +0000610 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000611 "b", " $target",
612 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
Rafael Espindola1ed3af12006-08-01 18:53:10 +0000613}
Rafael Espindola84b19be2006-07-16 01:02:57 +0000614
Evan Chenga8e29892007-01-19 07:51:42 +0000615//===----------------------------------------------------------------------===//
616// Load / store Instructions.
617//
Rafael Espindola82c678b2006-10-16 17:17:22 +0000618
Evan Chenga8e29892007-01-19 07:51:42 +0000619// Load
Dan Gohman15511cf2008-12-03 18:15:48 +0000620let canFoldAsLoad = 1 in
Evan Cheng148cad82008-11-13 07:34:59 +0000621def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
Evan Cheng44bec522007-05-15 01:29:07 +0000622 "ldr", " $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000623 [(set GPR:$dst, (load addrmode2:$addr))]>;
Rafael Espindola82c678b2006-10-16 17:17:22 +0000624
Evan Chengfa775d02007-03-19 07:20:03 +0000625// Special LDR for loads from non-pc-relative constpools.
Dan Gohman15511cf2008-12-03 18:15:48 +0000626let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
Evan Cheng148cad82008-11-13 07:34:59 +0000627def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
Evan Cheng44bec522007-05-15 01:29:07 +0000628 "ldr", " $dst, $addr", []>;
Evan Chengfa775d02007-03-19 07:20:03 +0000629
Evan Chenga8e29892007-01-19 07:51:42 +0000630// Loads with zero extension
Evan Cheng148cad82008-11-13 07:34:59 +0000631def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000632 "ldr", "h $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000633 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
Rafael Espindola82c678b2006-10-16 17:17:22 +0000634
Evan Cheng148cad82008-11-13 07:34:59 +0000635def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000636 "ldr", "b $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000637 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
Rafael Espindola82c678b2006-10-16 17:17:22 +0000638
Evan Chenga8e29892007-01-19 07:51:42 +0000639// Loads with sign extension
Evan Cheng148cad82008-11-13 07:34:59 +0000640def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000641 "ldr", "sh $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000642 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000643
Evan Cheng148cad82008-11-13 07:34:59 +0000644def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000645 "ldr", "sb $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000646 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
Rafael Espindolac391d162006-10-23 20:34:27 +0000647
Chris Lattner9b37aaf2008-01-10 05:12:37 +0000648let mayLoad = 1 in {
Evan Chenga8e29892007-01-19 07:51:42 +0000649// Load doubleword
Evan Cheng358dec52009-06-15 08:28:29 +0000650def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
651 "ldr", "d $dst1, $addr", []>, Requires<[IsARM, HasV5T]>;
Rafael Espindolac391d162006-10-23 20:34:27 +0000652
Evan Chenga8e29892007-01-19 07:51:42 +0000653// Indexed loads
Evan Chengd87293c2008-11-06 08:47:38 +0000654def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000655 (ins addrmode2:$addr), LdFrm,
Evan Cheng0ff94f72007-08-07 01:37:15 +0000656 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
Rafael Espindoladc124a22006-05-18 21:45:49 +0000657
Evan Chengd87293c2008-11-06 08:47:38 +0000658def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000659 (ins GPR:$base, am2offset:$offset), LdFrm,
Evan Cheng0ff94f72007-08-07 01:37:15 +0000660 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
Rafael Espindola450856d2006-12-12 00:37:38 +0000661
Evan Chengd87293c2008-11-06 08:47:38 +0000662def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000663 (ins addrmode3:$addr), LdMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000664 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
Rafael Espindola4e307642006-09-08 16:59:47 +0000665
Evan Chengd87293c2008-11-06 08:47:38 +0000666def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000667 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000668 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
Lauro Ramos Venancio301009a2006-12-28 13:11:14 +0000669
Evan Chengd87293c2008-11-06 08:47:38 +0000670def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000671 (ins addrmode2:$addr), LdFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000672 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
Lauro Ramos Venancio301009a2006-12-28 13:11:14 +0000673
Evan Chengd87293c2008-11-06 08:47:38 +0000674def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000675 (ins GPR:$base,am2offset:$offset), LdFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000676 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000677
Evan Chengd87293c2008-11-06 08:47:38 +0000678def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000679 (ins addrmode3:$addr), LdMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000680 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000681
Evan Chengd87293c2008-11-06 08:47:38 +0000682def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000683 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
684 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000685
Evan Chengd87293c2008-11-06 08:47:38 +0000686def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000687 (ins addrmode3:$addr), LdMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000688 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000689
Evan Chengd87293c2008-11-06 08:47:38 +0000690def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000691 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000692 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
Chris Lattner9b37aaf2008-01-10 05:12:37 +0000693}
Evan Chenga8e29892007-01-19 07:51:42 +0000694
695// Store
Evan Cheng148cad82008-11-13 07:34:59 +0000696def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
Evan Cheng44bec522007-05-15 01:29:07 +0000697 "str", " $src, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000698 [(store GPR:$src, addrmode2:$addr)]>;
699
700// Stores with truncate
Evan Cheng148cad82008-11-13 07:34:59 +0000701def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000702 "str", "h $src, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000703 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
704
Evan Cheng148cad82008-11-13 07:34:59 +0000705def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000706 "str", "b $src, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000707 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
708
709// Store doubleword
Chris Lattner2e48a702008-01-06 08:36:04 +0000710let mayStore = 1 in
Evan Cheng358dec52009-06-15 08:28:29 +0000711def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),StMiscFrm,
712 "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5T]>;
Evan Chenga8e29892007-01-19 07:51:42 +0000713
714// Indexed stores
Evan Chengd87293c2008-11-06 08:47:38 +0000715def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000716 (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
Evan Cheng44bec522007-05-15 01:29:07 +0000717 "str", " $src, [$base, $offset]!", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000718 [(set GPR:$base_wb,
719 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
720
Evan Chengd87293c2008-11-06 08:47:38 +0000721def STR_POST : AI2stwpo<(outs GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000722 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
Evan Cheng44bec522007-05-15 01:29:07 +0000723 "str", " $src, [$base], $offset", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000724 [(set GPR:$base_wb,
725 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
726
Evan Chengd87293c2008-11-06 08:47:38 +0000727def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000728 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000729 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000730 [(set GPR:$base_wb,
731 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
732
Evan Chengd87293c2008-11-06 08:47:38 +0000733def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000734 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000735 "str", "h $src, [$base], $offset", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000736 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
737 GPR:$base, am3offset:$offset))]>;
738
Evan Chengd87293c2008-11-06 08:47:38 +0000739def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000740 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000741 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000742 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
743 GPR:$base, am2offset:$offset))]>;
744
Evan Chengd87293c2008-11-06 08:47:38 +0000745def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000746 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000747 "str", "b $src, [$base], $offset", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000748 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
749 GPR:$base, am2offset:$offset))]>;
Evan Chenga8e29892007-01-19 07:51:42 +0000750
751//===----------------------------------------------------------------------===//
752// Load / store multiple Instructions.
753//
754
Evan Cheng64d80e32007-07-19 01:14:50 +0000755// FIXME: $dst1 should be a def.
Chris Lattner9b37aaf2008-01-10 05:12:37 +0000756let mayLoad = 1 in
Evan Chengd87293c2008-11-06 08:47:38 +0000757def LDM : AXI4ld<(outs),
Evan Cheng64d80e32007-07-19 01:14:50 +0000758 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
Evan Cheng3c4a4ff2008-11-12 07:18:38 +0000759 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
Evan Cheng44bec522007-05-15 01:29:07 +0000760 []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000761
Chris Lattner2e48a702008-01-06 08:36:04 +0000762let mayStore = 1 in
Evan Chengd87293c2008-11-06 08:47:38 +0000763def STM : AXI4st<(outs),
Evan Cheng64d80e32007-07-19 01:14:50 +0000764 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
Evan Cheng3c4a4ff2008-11-12 07:18:38 +0000765 LdStMulFrm, "stm${p}${addr:submode} $addr, $src1",
Evan Cheng44bec522007-05-15 01:29:07 +0000766 []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000767
768//===----------------------------------------------------------------------===//
769// Move Instructions.
770//
771
Evan Chengcd799b92009-06-12 20:46:18 +0000772let neverHasSideEffects = 1 in
Evan Chengedda31c2008-11-05 18:35:52 +0000773def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm,
774 "mov", " $dst, $src", []>, UnaryDP;
775def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
776 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP;
Evan Chenga2515702007-03-19 07:09:02 +0000777
Evan Chengb3379fb2009-02-05 08:42:55 +0000778let isReMaterializable = 1, isAsCheapAsAMove = 1 in
Evan Chengedda31c2008-11-05 18:35:52 +0000779def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm,
780 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP;
Evan Cheng13ab0202007-07-10 18:08:01 +0000781
Evan Chenga9562552008-11-14 20:09:11 +0000782def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
Evan Cheng64d80e32007-07-19 01:14:50 +0000783 "mov", " $dst, $src, rrx",
Evan Chengedda31c2008-11-05 18:35:52 +0000784 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
Evan Chenga8e29892007-01-19 07:51:42 +0000785
786// These aren't really mov instructions, but we have to define them this way
787// due to flag operands.
788
Evan Cheng071a2792007-09-11 19:55:27 +0000789let Defs = [CPSR] in {
Evan Chenga9562552008-11-14 20:09:11 +0000790def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
Evan Chengfd488ed2007-05-29 23:32:06 +0000791 "mov", "s $dst, $src, lsr #1",
Evan Chengedda31c2008-11-05 18:35:52 +0000792 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
Evan Chenga9562552008-11-14 20:09:11 +0000793def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
Evan Chengfd488ed2007-05-29 23:32:06 +0000794 "mov", "s $dst, $src, asr #1",
Evan Chengedda31c2008-11-05 18:35:52 +0000795 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
Evan Cheng071a2792007-09-11 19:55:27 +0000796}
Evan Chenga8e29892007-01-19 07:51:42 +0000797
Evan Chenga8e29892007-01-19 07:51:42 +0000798//===----------------------------------------------------------------------===//
799// Extend Instructions.
800//
801
802// Sign extenders
803
Evan Cheng97f48c32008-11-06 22:15:19 +0000804defm SXTB : AI_unary_rrot<0b01101010,
805 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
806defm SXTH : AI_unary_rrot<0b01101011,
807 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
Evan Chenga8e29892007-01-19 07:51:42 +0000808
Evan Cheng97f48c32008-11-06 22:15:19 +0000809defm SXTAB : AI_bin_rrot<0b01101010,
810 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
811defm SXTAH : AI_bin_rrot<0b01101011,
812 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
Evan Chenga8e29892007-01-19 07:51:42 +0000813
814// TODO: SXT(A){B|H}16
815
816// Zero extenders
817
818let AddedComplexity = 16 in {
Evan Cheng97f48c32008-11-06 22:15:19 +0000819defm UXTB : AI_unary_rrot<0b01101110,
820 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
821defm UXTH : AI_unary_rrot<0b01101111,
822 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
823defm UXTB16 : AI_unary_rrot<0b01101100,
824 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
Evan Chenga8e29892007-01-19 07:51:42 +0000825
826def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
827 (UXTB16r_rot GPR:$Src, 24)>;
828def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
829 (UXTB16r_rot GPR:$Src, 8)>;
830
Evan Cheng97f48c32008-11-06 22:15:19 +0000831defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
Evan Chenga8e29892007-01-19 07:51:42 +0000832 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
Evan Cheng97f48c32008-11-06 22:15:19 +0000833defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
Evan Chenga8e29892007-01-19 07:51:42 +0000834 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
Rafael Espindola3c000bf2006-08-21 22:00:32 +0000835}
836
Evan Chenga8e29892007-01-19 07:51:42 +0000837// This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
838//defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
Rafael Espindola817e7fd2006-09-11 19:24:19 +0000839
Evan Chenga8e29892007-01-19 07:51:42 +0000840// TODO: UXT(A){B|H}16
841
842//===----------------------------------------------------------------------===//
843// Arithmetic Instructions.
844//
845
Jim Grosbach26421962008-10-14 20:36:24 +0000846defm ADD : AsI1_bin_irs<0b0100, "add",
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000847 BinOpFrag<(add node:$LHS, node:$RHS)>>;
Jim Grosbach26421962008-10-14 20:36:24 +0000848defm SUB : AsI1_bin_irs<0b0010, "sub",
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000849 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
Evan Chenga8e29892007-01-19 07:51:42 +0000850
Evan Chengc85e8322007-07-05 07:13:32 +0000851// ADD and SUB with 's' bit set.
Jim Grosbach26421962008-10-14 20:36:24 +0000852defm ADDS : ASI1_bin_s_irs<0b0100, "add",
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000853 BinOpFrag<(addc node:$LHS, node:$RHS)>>;
Jim Grosbach26421962008-10-14 20:36:24 +0000854defm SUBS : ASI1_bin_s_irs<0b0010, "sub",
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000855 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
Evan Cheng2c614c52007-06-06 10:17:05 +0000856
Evan Chengc85e8322007-07-05 07:13:32 +0000857// FIXME: Do not allow ADC / SBC to be predicated for now.
Jim Grosbach26421962008-10-14 20:36:24 +0000858defm ADC : AsXI1_bin_c_irs<0b0101, "adc",
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000859 BinOpFrag<(adde node:$LHS, node:$RHS)>>;
Jim Grosbach26421962008-10-14 20:36:24 +0000860defm SBC : AsXI1_bin_c_irs<0b0110, "sbc",
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000861 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
Evan Chenga8e29892007-01-19 07:51:42 +0000862
Evan Chengc85e8322007-07-05 07:13:32 +0000863// These don't define reg/reg forms, because they are handled above.
Evan Chengedda31c2008-11-05 18:35:52 +0000864def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
Evan Cheng13ab0202007-07-10 18:08:01 +0000865 "rsb", " $dst, $a, $b",
866 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
867
Evan Chengedda31c2008-11-05 18:35:52 +0000868def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
Evan Cheng13ab0202007-07-10 18:08:01 +0000869 "rsb", " $dst, $a, $b",
870 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
Evan Chengc85e8322007-07-05 07:13:32 +0000871
872// RSB with 's' bit set.
Evan Cheng071a2792007-09-11 19:55:27 +0000873let Defs = [CPSR] in {
Evan Chengedda31c2008-11-05 18:35:52 +0000874def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
Evan Chengc85e8322007-07-05 07:13:32 +0000875 "rsb", "s $dst, $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000876 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
Evan Chengedda31c2008-11-05 18:35:52 +0000877def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
Evan Chengc85e8322007-07-05 07:13:32 +0000878 "rsb", "s $dst, $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000879 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
880}
Evan Chengc85e8322007-07-05 07:13:32 +0000881
Evan Cheng13ab0202007-07-10 18:08:01 +0000882// FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
Evan Cheng071a2792007-09-11 19:55:27 +0000883let Uses = [CPSR] in {
Jim Grosbach26421962008-10-14 20:36:24 +0000884def RSCri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
Evan Chengedda31c2008-11-05 18:35:52 +0000885 DPFrm, "rsc${s} $dst, $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000886 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
Jim Grosbach26421962008-10-14 20:36:24 +0000887def RSCrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
Evan Chengedda31c2008-11-05 18:35:52 +0000888 DPSoRegFrm, "rsc${s} $dst, $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000889 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
890}
Evan Cheng2c614c52007-06-06 10:17:05 +0000891
Evan Chenga8e29892007-01-19 07:51:42 +0000892// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
893def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
894 (SUBri GPR:$src, so_imm_neg:$imm)>;
895
896//def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
897// (SUBSri GPR:$src, so_imm_neg:$imm)>;
898//def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
899// (SBCri GPR:$src, so_imm_neg:$imm)>;
900
901// Note: These are implemented in C++ code, because they have to generate
902// ADD/SUBrs instructions, which use a complex pattern that a xform function
903// cannot produce.
904// (mul X, 2^n+1) -> (add (X << n), X)
905// (mul X, 2^n-1) -> (rsb X, (X << n))
906
907
908//===----------------------------------------------------------------------===//
909// Bitwise Instructions.
910//
911
Jim Grosbach26421962008-10-14 20:36:24 +0000912defm AND : AsI1_bin_irs<0b0000, "and",
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000913 BinOpFrag<(and node:$LHS, node:$RHS)>>;
Jim Grosbach26421962008-10-14 20:36:24 +0000914defm ORR : AsI1_bin_irs<0b1100, "orr",
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000915 BinOpFrag<(or node:$LHS, node:$RHS)>>;
Jim Grosbach26421962008-10-14 20:36:24 +0000916defm EOR : AsI1_bin_irs<0b0001, "eor",
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000917 BinOpFrag<(xor node:$LHS, node:$RHS)>>;
Jim Grosbach26421962008-10-14 20:36:24 +0000918defm BIC : AsI1_bin_irs<0b1110, "bic",
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000919 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
Evan Chenga8e29892007-01-19 07:51:42 +0000920
Evan Chengedda31c2008-11-05 18:35:52 +0000921def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm,
922 "mvn", " $dst, $src",
923 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP;
924def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
925 "mvn", " $dst, $src",
926 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
Evan Chengb3379fb2009-02-05 08:42:55 +0000927let isReMaterializable = 1, isAsCheapAsAMove = 1 in
Evan Chengedda31c2008-11-05 18:35:52 +0000928def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
929 "mvn", " $dst, $imm",
930 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP;
Evan Chenga8e29892007-01-19 07:51:42 +0000931
932def : ARMPat<(and GPR:$src, so_imm_not:$imm),
933 (BICri GPR:$src, so_imm_not:$imm)>;
934
935//===----------------------------------------------------------------------===//
936// Multiply Instructions.
937//
938
Evan Chengfbc9d412008-11-06 01:21:28 +0000939def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
Evan Cheng12c3a532008-11-06 17:48:05 +0000940 "mul", " $dst, $a, $b",
941 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
Evan Chenga8e29892007-01-19 07:51:42 +0000942
Evan Chengfbc9d412008-11-06 01:21:28 +0000943def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
Evan Cheng12c3a532008-11-06 17:48:05 +0000944 "mla", " $dst, $a, $b, $c",
945 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
Evan Chenga8e29892007-01-19 07:51:42 +0000946
947// Extra precision multiplies with low / high results
Evan Chengcd799b92009-06-12 20:46:18 +0000948let neverHasSideEffects = 1 in {
Evan Chengfbc9d412008-11-06 01:21:28 +0000949def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
950 (ins GPR:$a, GPR:$b),
951 "smull", " $ldst, $hdst, $a, $b", []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000952
Evan Chengfbc9d412008-11-06 01:21:28 +0000953def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
954 (ins GPR:$a, GPR:$b),
955 "umull", " $ldst, $hdst, $a, $b", []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000956
957// Multiply + accumulate
Evan Chengfbc9d412008-11-06 01:21:28 +0000958def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
959 (ins GPR:$a, GPR:$b),
960 "smlal", " $ldst, $hdst, $a, $b", []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000961
Evan Chengfbc9d412008-11-06 01:21:28 +0000962def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
963 (ins GPR:$a, GPR:$b),
964 "umlal", " $ldst, $hdst, $a, $b", []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000965
Evan Chengfbc9d412008-11-06 01:21:28 +0000966def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
967 (ins GPR:$a, GPR:$b),
968 "umaal", " $ldst, $hdst, $a, $b", []>,
969 Requires<[IsARM, HasV6]>;
Evan Chengcd799b92009-06-12 20:46:18 +0000970} // neverHasSideEffects
Evan Chenga8e29892007-01-19 07:51:42 +0000971
972// Most significant word multiply
Evan Chengfbc9d412008-11-06 01:21:28 +0000973def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
Evan Cheng13ab0202007-07-10 18:08:01 +0000974 "smmul", " $dst, $a, $b",
975 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
Evan Chengfbc9d412008-11-06 01:21:28 +0000976 Requires<[IsARM, HasV6]> {
977 let Inst{7-4} = 0b0001;
978 let Inst{15-12} = 0b1111;
979}
Evan Cheng13ab0202007-07-10 18:08:01 +0000980
Evan Chengfbc9d412008-11-06 01:21:28 +0000981def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
Evan Cheng13ab0202007-07-10 18:08:01 +0000982 "smmla", " $dst, $a, $b, $c",
983 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
Evan Chengfbc9d412008-11-06 01:21:28 +0000984 Requires<[IsARM, HasV6]> {
985 let Inst{7-4} = 0b0001;
986}
Evan Chenga8e29892007-01-19 07:51:42 +0000987
988
Evan Chengfbc9d412008-11-06 01:21:28 +0000989def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
Evan Cheng44bec522007-05-15 01:29:07 +0000990 "smmls", " $dst, $a, $b, $c",
Evan Chenga8e29892007-01-19 07:51:42 +0000991 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
Evan Chengfbc9d412008-11-06 01:21:28 +0000992 Requires<[IsARM, HasV6]> {
993 let Inst{7-4} = 0b1101;
994}
Evan Chenga8e29892007-01-19 07:51:42 +0000995
Raul Herbster37fb5b12007-08-30 23:25:47 +0000996multiclass AI_smul<string opc, PatFrag opnode> {
Evan Chengeb4f52e2008-11-06 03:35:07 +0000997 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +0000998 !strconcat(opc, "bb"), " $dst, $a, $b",
Evan Cheng34b12d22007-01-19 20:27:35 +0000999 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1000 (sext_inreg GPR:$b, i16)))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001001 Requires<[IsARM, HasV5TE]> {
1002 let Inst{5} = 0;
1003 let Inst{6} = 0;
1004 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001005
Evan Chengeb4f52e2008-11-06 03:35:07 +00001006 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +00001007 !strconcat(opc, "bt"), " $dst, $a, $b",
Evan Cheng34b12d22007-01-19 20:27:35 +00001008 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1009 (sra GPR:$b, 16)))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001010 Requires<[IsARM, HasV5TE]> {
1011 let Inst{5} = 0;
1012 let Inst{6} = 1;
1013 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001014
Evan Chengeb4f52e2008-11-06 03:35:07 +00001015 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +00001016 !strconcat(opc, "tb"), " $dst, $a, $b",
Evan Cheng34b12d22007-01-19 20:27:35 +00001017 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1018 (sext_inreg GPR:$b, i16)))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001019 Requires<[IsARM, HasV5TE]> {
1020 let Inst{5} = 1;
1021 let Inst{6} = 0;
1022 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001023
Evan Chengeb4f52e2008-11-06 03:35:07 +00001024 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +00001025 !strconcat(opc, "tt"), " $dst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +00001026 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1027 (sra GPR:$b, 16)))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001028 Requires<[IsARM, HasV5TE]> {
1029 let Inst{5} = 1;
1030 let Inst{6} = 1;
1031 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001032
Evan Chengeb4f52e2008-11-06 03:35:07 +00001033 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +00001034 !strconcat(opc, "wb"), " $dst, $a, $b",
Evan Cheng34b12d22007-01-19 20:27:35 +00001035 [(set GPR:$dst, (sra (opnode GPR:$a,
1036 (sext_inreg GPR:$b, i16)), 16))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001037 Requires<[IsARM, HasV5TE]> {
1038 let Inst{5} = 1;
1039 let Inst{6} = 0;
1040 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001041
Evan Chengeb4f52e2008-11-06 03:35:07 +00001042 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +00001043 !strconcat(opc, "wt"), " $dst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +00001044 [(set GPR:$dst, (sra (opnode GPR:$a,
1045 (sra GPR:$b, 16)), 16))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001046 Requires<[IsARM, HasV5TE]> {
1047 let Inst{5} = 1;
1048 let Inst{6} = 1;
1049 }
Rafael Espindolabec2e382006-10-16 16:33:29 +00001050}
1051
Raul Herbster37fb5b12007-08-30 23:25:47 +00001052
1053multiclass AI_smla<string opc, PatFrag opnode> {
Evan Chengeb4f52e2008-11-06 03:35:07 +00001054 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +00001055 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
Evan Cheng34b12d22007-01-19 20:27:35 +00001056 [(set GPR:$dst, (add GPR:$acc,
1057 (opnode (sext_inreg GPR:$a, i16),
1058 (sext_inreg GPR:$b, i16))))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001059 Requires<[IsARM, HasV5TE]> {
1060 let Inst{5} = 0;
1061 let Inst{6} = 0;
1062 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001063
Evan Chengeb4f52e2008-11-06 03:35:07 +00001064 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +00001065 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
Evan Cheng34b12d22007-01-19 20:27:35 +00001066 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
Evan Chenga8e29892007-01-19 07:51:42 +00001067 (sra GPR:$b, 16))))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001068 Requires<[IsARM, HasV5TE]> {
1069 let Inst{5} = 0;
1070 let Inst{6} = 1;
1071 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001072
Evan Chengeb4f52e2008-11-06 03:35:07 +00001073 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +00001074 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
Evan Cheng34b12d22007-01-19 20:27:35 +00001075 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1076 (sext_inreg GPR:$b, i16))))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001077 Requires<[IsARM, HasV5TE]> {
1078 let Inst{5} = 1;
1079 let Inst{6} = 0;
1080 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001081
Evan Chengeb4f52e2008-11-06 03:35:07 +00001082 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +00001083 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
Evan Chenga8e29892007-01-19 07:51:42 +00001084 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1085 (sra GPR:$b, 16))))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001086 Requires<[IsARM, HasV5TE]> {
1087 let Inst{5} = 1;
1088 let Inst{6} = 1;
1089 }
Evan Chenga8e29892007-01-19 07:51:42 +00001090
Evan Chengeb4f52e2008-11-06 03:35:07 +00001091 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +00001092 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
Evan Cheng34b12d22007-01-19 20:27:35 +00001093 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1094 (sext_inreg GPR:$b, i16)), 16)))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001095 Requires<[IsARM, HasV5TE]> {
1096 let Inst{5} = 0;
1097 let Inst{6} = 0;
1098 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001099
Evan Chengeb4f52e2008-11-06 03:35:07 +00001100 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +00001101 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
Evan Chenga8e29892007-01-19 07:51:42 +00001102 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1103 (sra GPR:$b, 16)), 16)))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001104 Requires<[IsARM, HasV5TE]> {
1105 let Inst{5} = 0;
1106 let Inst{6} = 1;
1107 }
Rafael Espindola70673a12006-10-18 16:20:57 +00001108}
Rafael Espindola5c2aa0a2006-09-08 12:47:03 +00001109
Raul Herbster37fb5b12007-08-30 23:25:47 +00001110defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1111defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
Rafael Espindola27185192006-09-29 21:20:16 +00001112
Evan Chenga8e29892007-01-19 07:51:42 +00001113// TODO: Halfword multiple accumulate long: SMLAL<x><y>
1114// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
Rafael Espindola42b62f32006-10-13 13:14:59 +00001115
Evan Chenga8e29892007-01-19 07:51:42 +00001116//===----------------------------------------------------------------------===//
1117// Misc. Arithmetic Instructions.
1118//
Rafael Espindola0d9fe762006-10-10 16:33:47 +00001119
Evan Cheng8b59db32008-11-07 01:41:35 +00001120def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src),
Evan Cheng44bec522007-05-15 01:29:07 +00001121 "clz", " $dst, $src",
Evan Cheng8b59db32008-11-07 01:41:35 +00001122 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1123 let Inst{7-4} = 0b0001;
1124 let Inst{11-8} = 0b1111;
1125 let Inst{19-16} = 0b1111;
1126}
Rafael Espindola199dd672006-10-17 13:13:23 +00001127
Evan Cheng8b59db32008-11-07 01:41:35 +00001128def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
Evan Cheng44bec522007-05-15 01:29:07 +00001129 "rev", " $dst, $src",
Evan Cheng8b59db32008-11-07 01:41:35 +00001130 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1131 let Inst{7-4} = 0b0011;
1132 let Inst{11-8} = 0b1111;
1133 let Inst{19-16} = 0b1111;
1134}
Rafael Espindola199dd672006-10-17 13:13:23 +00001135
Evan Cheng8b59db32008-11-07 01:41:35 +00001136def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
Evan Cheng44bec522007-05-15 01:29:07 +00001137 "rev16", " $dst, $src",
Evan Chenga8e29892007-01-19 07:51:42 +00001138 [(set GPR:$dst,
1139 (or (and (srl GPR:$src, 8), 0xFF),
1140 (or (and (shl GPR:$src, 8), 0xFF00),
1141 (or (and (srl GPR:$src, 8), 0xFF0000),
1142 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
Evan Cheng8b59db32008-11-07 01:41:35 +00001143 Requires<[IsARM, HasV6]> {
1144 let Inst{7-4} = 0b1011;
1145 let Inst{11-8} = 0b1111;
1146 let Inst{19-16} = 0b1111;
1147}
Rafael Espindola27185192006-09-29 21:20:16 +00001148
Evan Cheng8b59db32008-11-07 01:41:35 +00001149def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src),
Evan Cheng44bec522007-05-15 01:29:07 +00001150 "revsh", " $dst, $src",
Evan Chenga8e29892007-01-19 07:51:42 +00001151 [(set GPR:$dst,
1152 (sext_inreg
Chris Lattner120fba92007-04-17 22:39:58 +00001153 (or (srl (and GPR:$src, 0xFF00), 8),
Evan Chenga8e29892007-01-19 07:51:42 +00001154 (shl GPR:$src, 8)), i16))]>,
Evan Cheng8b59db32008-11-07 01:41:35 +00001155 Requires<[IsARM, HasV6]> {
1156 let Inst{7-4} = 0b1011;
1157 let Inst{11-8} = 0b1111;
1158 let Inst{19-16} = 0b1111;
1159}
Rafael Espindola27185192006-09-29 21:20:16 +00001160
Evan Cheng8b59db32008-11-07 01:41:35 +00001161def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1162 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1163 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
Evan Chenga8e29892007-01-19 07:51:42 +00001164 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1165 (and (shl GPR:$src2, (i32 imm:$shamt)),
1166 0xFFFF0000)))]>,
Evan Cheng8b59db32008-11-07 01:41:35 +00001167 Requires<[IsARM, HasV6]> {
1168 let Inst{6-4} = 0b001;
1169}
Rafael Espindola27185192006-09-29 21:20:16 +00001170
Evan Chenga8e29892007-01-19 07:51:42 +00001171// Alternate cases for PKHBT where identities eliminate some nodes.
1172def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1173 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1174def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1175 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
Rafael Espindola9e071f02006-10-02 19:30:56 +00001176
Rafael Espindolaa2845842006-10-05 16:48:49 +00001177
Evan Cheng8b59db32008-11-07 01:41:35 +00001178def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1179 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1180 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
Evan Chenga8e29892007-01-19 07:51:42 +00001181 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1182 (and (sra GPR:$src2, imm16_31:$shamt),
Evan Cheng8b59db32008-11-07 01:41:35 +00001183 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1184 let Inst{6-4} = 0b101;
1185}
Rafael Espindola9e071f02006-10-02 19:30:56 +00001186
Evan Chenga8e29892007-01-19 07:51:42 +00001187// Alternate cases for PKHTB where identities eliminate some nodes. Note that
1188// a shift amount of 0 is *not legal* here, it is PKHBT instead.
1189def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)),
1190 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1191def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1192 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1193 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
Rafael Espindolab47e1d02006-10-10 18:55:14 +00001194
Evan Chenga8e29892007-01-19 07:51:42 +00001195//===----------------------------------------------------------------------===//
1196// Comparison Instructions...
1197//
Rafael Espindolab47e1d02006-10-10 18:55:14 +00001198
Jim Grosbach26421962008-10-14 20:36:24 +00001199defm CMP : AI1_cmp_irs<0b1010, "cmp",
Evan Cheng0ff94f72007-08-07 01:37:15 +00001200 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
Jim Grosbach26421962008-10-14 20:36:24 +00001201defm CMN : AI1_cmp_irs<0b1011, "cmn",
Evan Cheng0ff94f72007-08-07 01:37:15 +00001202 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
Rafael Espindolae5bbd6d2006-10-07 14:24:52 +00001203
Evan Chenga8e29892007-01-19 07:51:42 +00001204// Note that TST/TEQ don't set all the same flags that CMP does!
Evan Chengd87293c2008-11-06 08:47:38 +00001205defm TST : AI1_cmp_irs<0b1000, "tst",
Evan Cheng0ff94f72007-08-07 01:37:15 +00001206 BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
Evan Chengd87293c2008-11-06 08:47:38 +00001207defm TEQ : AI1_cmp_irs<0b1001, "teq",
Evan Cheng0ff94f72007-08-07 01:37:15 +00001208 BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
Lauro Ramos Venancio99966632007-04-02 01:30:03 +00001209
Jim Grosbach26421962008-10-14 20:36:24 +00001210defm CMPnz : AI1_cmp_irs<0b1010, "cmp",
Evan Cheng0ff94f72007-08-07 01:37:15 +00001211 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
Jim Grosbach26421962008-10-14 20:36:24 +00001212defm CMNnz : AI1_cmp_irs<0b1011, "cmn",
Evan Cheng0ff94f72007-08-07 01:37:15 +00001213 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
Evan Cheng2c614c52007-06-06 10:17:05 +00001214
1215def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1216 (CMNri GPR:$src, so_imm_neg:$imm)>;
Lauro Ramos Venancio99966632007-04-02 01:30:03 +00001217
1218def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1219 (CMNri GPR:$src, so_imm_neg:$imm)>;
1220
Rafael Espindolae5bbd6d2006-10-07 14:24:52 +00001221
Evan Chenga8e29892007-01-19 07:51:42 +00001222// Conditional moves
Evan Chengc85e8322007-07-05 07:13:32 +00001223// FIXME: should be able to write a pattern for ARMcmov, but can't use
1224// a two-value operand where a dag node expects two operands. :(
Evan Chengd87293c2008-11-06 08:47:38 +00001225def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
Evan Chengedda31c2008-11-05 18:35:52 +00001226 "mov", " $dst, $true",
Evan Chengc85e8322007-07-05 07:13:32 +00001227 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
Evan Chengd87293c2008-11-06 08:47:38 +00001228 RegConstraint<"$false = $dst">, UnaryDP;
Rafael Espindola493a7fc2006-10-10 20:38:57 +00001229
Evan Chengd87293c2008-11-06 08:47:38 +00001230def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1231 (ins GPR:$false, so_reg:$true), DPSoRegFrm,
Evan Chengedda31c2008-11-05 18:35:52 +00001232 "mov", " $dst, $true",
Evan Chengc85e8322007-07-05 07:13:32 +00001233 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
Evan Chengedda31c2008-11-05 18:35:52 +00001234 RegConstraint<"$false = $dst">, UnaryDP;
Rafael Espindola2dc0f2b2006-10-09 17:50:29 +00001235
Evan Chengd87293c2008-11-06 08:47:38 +00001236def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1237 (ins GPR:$false, so_imm:$true), DPFrm,
Evan Chengedda31c2008-11-05 18:35:52 +00001238 "mov", " $dst, $true",
Evan Chengc85e8322007-07-05 07:13:32 +00001239 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
Evan Chengedda31c2008-11-05 18:35:52 +00001240 RegConstraint<"$false = $dst">, UnaryDP;
Rafael Espindolad9ae7782006-10-07 13:46:42 +00001241
Rafael Espindola4b20fbc2006-10-10 12:56:00 +00001242
Evan Chenga8e29892007-01-19 07:51:42 +00001243// LEApcrel - Load a pc-relative address into a register without offending the
1244// assembler.
Evan Cheng0ff94f72007-08-07 01:37:15 +00001245def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo,
Evan Chenga8e29892007-01-19 07:51:42 +00001246 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
1247 "${:private}PCRELL${:uid}+8))\n"),
1248 !strconcat("${:private}PCRELL${:uid}:\n\t",
Evan Cheng44bec522007-05-15 01:29:07 +00001249 "add$p $dst, pc, #PCRELV${:uid}")),
Evan Chenga8e29892007-01-19 07:51:42 +00001250 []>;
Rafael Espindola667c3492006-10-10 19:35:01 +00001251
Evan Cheng0ff94f72007-08-07 01:37:15 +00001252def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p),
1253 Pseudo,
Evan Chenga8e29892007-01-19 07:51:42 +00001254 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
1255 "${:private}PCRELL${:uid}+8))\n"),
1256 !strconcat("${:private}PCRELL${:uid}:\n\t",
Evan Cheng44bec522007-05-15 01:29:07 +00001257 "add$p $dst, pc, #PCRELV${:uid}")),
Evan Chenga8e29892007-01-19 07:51:42 +00001258 []>;
Evan Chengeaa91b02007-06-19 01:26:51 +00001259
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001260//===----------------------------------------------------------------------===//
1261// TLS Instructions
1262//
1263
1264// __aeabi_read_tp preserves the registers r1-r3.
Evan Cheng13ab0202007-07-10 18:08:01 +00001265let isCall = 1,
1266 Defs = [R0, R12, LR, CPSR] in {
Evan Cheng12c3a532008-11-06 17:48:05 +00001267 def TPsoft : ABXI<0b1011, (outs), (ins),
Evan Chengdcc50a42007-05-18 01:53:54 +00001268 "bl __aeabi_read_tp",
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001269 [(set R0, ARMthread_pointer)]>;
1270}
Rafael Espindolac01c87c2006-10-17 20:33:13 +00001271
Evan Chenga8e29892007-01-19 07:51:42 +00001272//===----------------------------------------------------------------------===//
Jim Grosbach0e0da732009-05-12 23:59:14 +00001273// SJLJ Exception handling intrinsics
Jim Grosbachf9570122009-05-14 00:46:35 +00001274// eh_sjlj_setjmp() is a three instruction sequence to store the return
1275// address and save #0 in R0 for the non-longjmp case.
Jim Grosbach0e0da732009-05-12 23:59:14 +00001276// Since by its nature we may be coming from some other function to get
1277// here, and we're using the stack frame for the containing function to
1278// save/restore registers, we can't keep anything live in regs across
Jim Grosbachf9570122009-05-14 00:46:35 +00001279// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
Jim Grosbach0e0da732009-05-12 23:59:14 +00001280// when we get here from a longjmp(). We force everthing out of registers
Jim Grosbachf9570122009-05-14 00:46:35 +00001281// except for our own input by listing the relevant registers in Defs. By
1282// doing so, we also cause the prologue/epilogue code to actively preserve
1283// all of the callee-saved resgisters, which is exactly what we want.
Jim Grosbach0e0da732009-05-12 23:59:14 +00001284let Defs =
1285 [ R0, R1, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR,
1286 D0, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 ] in {
Jim Grosbachf9570122009-05-14 00:46:35 +00001287 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
Jim Grosbach0e0da732009-05-12 23:59:14 +00001288 AddrModeNone, SizeSpecial, IndexModeNone, Pseudo,
1289 "add r0, pc, #4\n\t"
1290 "str r0, [$src, #+4]\n\t"
Jim Grosbachf9570122009-05-14 00:46:35 +00001291 "mov r0, #0 @ eh_setjmp", "",
1292 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
Jim Grosbach0e0da732009-05-12 23:59:14 +00001293}
1294
1295//===----------------------------------------------------------------------===//
Evan Chenga8e29892007-01-19 07:51:42 +00001296// Non-Instruction Patterns
1297//
Rafael Espindola5aca9272006-10-07 14:03:39 +00001298
Evan Chenga8e29892007-01-19 07:51:42 +00001299// ConstantPool, GlobalAddress, and JumpTable
1300def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1301def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1302def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
Evan Chengc70d1842007-03-20 08:11:30 +00001303 (LEApcrelJT tjumptable:$dst, imm:$id)>;
Rafael Espindola5aca9272006-10-07 14:03:39 +00001304
Evan Chenga8e29892007-01-19 07:51:42 +00001305// Large immediate handling.
Rafael Espindola0505be02006-10-16 21:10:32 +00001306
Evan Chenga8e29892007-01-19 07:51:42 +00001307// Two piece so_imms.
Dan Gohmand45eddd2007-06-26 00:48:07 +00001308let isReMaterializable = 1 in
Evan Chengd87293c2008-11-06 08:47:38 +00001309def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), Pseudo,
Evan Cheng44bec522007-05-15 01:29:07 +00001310 "mov", " $dst, $src",
Evan Cheng90922132008-11-06 02:25:39 +00001311 [(set GPR:$dst, so_imm2part:$src)]>;
Rafael Espindolaf621abc2006-10-17 13:36:07 +00001312
Evan Chenga8e29892007-01-19 07:51:42 +00001313def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1314 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1315 (so_imm2part_2 imm:$RHS))>;
1316def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1317 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1318 (so_imm2part_2 imm:$RHS))>;
Rafael Espindolaf621abc2006-10-17 13:36:07 +00001319
Evan Chenga8e29892007-01-19 07:51:42 +00001320// TODO: add,sub,and, 3-instr forms?
Rafael Espindola0505be02006-10-16 21:10:32 +00001321
Rafael Espindola24357862006-10-19 17:05:03 +00001322
Evan Chenga8e29892007-01-19 07:51:42 +00001323// Direct calls
1324def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
Rafael Espindola9dca7ad2006-11-01 14:13:27 +00001325
Evan Chenga8e29892007-01-19 07:51:42 +00001326// zextload i1 -> zextload i8
1327def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
Lauro Ramos Venancioa8f9f4a2006-12-26 19:30:42 +00001328
Evan Chenga8e29892007-01-19 07:51:42 +00001329// extload -> zextload
1330def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1331def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1332def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
Rafael Espindola9dca7ad2006-11-01 14:13:27 +00001333
Evan Cheng83b5cf02008-11-05 23:22:34 +00001334def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1335def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1336
Evan Cheng34b12d22007-01-19 20:27:35 +00001337// smul* and smla*
1338def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
1339 (SMULBB GPR:$a, GPR:$b)>;
1340def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1341 (SMULBB GPR:$a, GPR:$b)>;
1342def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)),
1343 (SMULBT GPR:$a, GPR:$b)>;
1344def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)),
1345 (SMULBT GPR:$a, GPR:$b)>;
1346def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)),
1347 (SMULTB GPR:$a, GPR:$b)>;
1348def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b),
1349 (SMULTB GPR:$a, GPR:$b)>;
1350def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16),
1351 (SMULWB GPR:$a, GPR:$b)>;
1352def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16),
1353 (SMULWB GPR:$a, GPR:$b)>;
1354
1355def : ARMV5TEPat<(add GPR:$acc,
1356 (mul (sra (shl GPR:$a, 16), 16),
1357 (sra (shl GPR:$b, 16), 16))),
1358 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1359def : ARMV5TEPat<(add GPR:$acc,
1360 (mul sext_16_node:$a, sext_16_node:$b)),
1361 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1362def : ARMV5TEPat<(add GPR:$acc,
1363 (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))),
1364 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1365def : ARMV5TEPat<(add GPR:$acc,
1366 (mul sext_16_node:$a, (sra GPR:$b, 16))),
1367 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1368def : ARMV5TEPat<(add GPR:$acc,
1369 (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))),
1370 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1371def : ARMV5TEPat<(add GPR:$acc,
1372 (mul (sra GPR:$a, 16), sext_16_node:$b)),
1373 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1374def : ARMV5TEPat<(add GPR:$acc,
1375 (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)),
1376 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1377def : ARMV5TEPat<(add GPR:$acc,
1378 (sra (mul GPR:$a, sext_16_node:$b), 16)),
1379 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1380
Evan Chenga8e29892007-01-19 07:51:42 +00001381//===----------------------------------------------------------------------===//
1382// Thumb Support
1383//
1384
1385include "ARMInstrThumb.td"
1386
1387//===----------------------------------------------------------------------===//
Anton Korobeynikov52237112009-06-17 18:13:58 +00001388// Thumb2 Support
1389//
1390
1391include "ARMInstrThumb2.td"
1392
1393//===----------------------------------------------------------------------===//
Evan Chenga8e29892007-01-19 07:51:42 +00001394// Floating Point Support
1395//
1396
1397include "ARMInstrVFP.td"