| Chris Lattner | 4c7b43b | 2005-10-14 23:37:35 +0000 | [diff] [blame] | 1 | //===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This is the top level entry point for the PowerPC target. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | // Get the target-independent interfaces which we are implementing. |
| 15 | // |
| 16 | include "../Target.td" |
| 17 | |
| 18 | //===----------------------------------------------------------------------===// |
| 19 | // Register File Description |
| 20 | //===----------------------------------------------------------------------===// |
| 21 | |
| Chris Lattner | f379997 | 2005-10-14 23:40:39 +0000 | [diff] [blame] | 22 | include "PPCRegisterInfo.td" |
| Jim Laskey | 5384214 | 2005-10-19 19:51:16 +0000 | [diff] [blame] | 23 | include "PPCSchedule.td" |
| Chris Lattner | f379997 | 2005-10-14 23:40:39 +0000 | [diff] [blame] | 24 | include "PPCInstrInfo.td" |
| Chris Lattner | 4c7b43b | 2005-10-14 23:37:35 +0000 | [diff] [blame] | 25 | |
| Jim Laskey | 5384214 | 2005-10-19 19:51:16 +0000 | [diff] [blame] | 26 | |
| 27 | |
| 28 | //===----------------------------------------------------------------------===// |
| Jim Laskey | f5fc2cb | 2005-10-21 19:05:19 +0000 | [diff] [blame] | 29 | // PowerPC Subtarget features (sorted by name). |
| Jim Laskey | 5384214 | 2005-10-19 19:51:16 +0000 | [diff] [blame] | 30 | // |
| 31 | |
| Jim Laskey | f5fc2cb | 2005-10-21 19:05:19 +0000 | [diff] [blame] | 32 | def Feature64Bit : SubtargetFeature<"64bit", |
| 33 | "Should 64 bit instructions be used">; |
| 34 | def Feature64BitRegs : SubtargetFeature<"64bitregs", |
| 35 | "Should 64 bit registers be used">; |
| 36 | def FeatureAltivec : SubtargetFeature<"altivec", |
| 37 | "Should Altivec instructions be used">; |
| 38 | def FeatureFSqrt : SubtargetFeature<"fsqrt", |
| 39 | "Should the fsqrt instruction be used">; |
| 40 | def FeatureGPUL : SubtargetFeature<"gpul", |
| 41 | "Should GPUL instructions be used">; |
| Jim Laskey | 5384214 | 2005-10-19 19:51:16 +0000 | [diff] [blame] | 42 | |
| 43 | //===----------------------------------------------------------------------===// |
| Jim Laskey | f5fc2cb | 2005-10-21 19:05:19 +0000 | [diff] [blame] | 44 | // PowerPC chips sets supported (sorted by name) |
| Jim Laskey | 5384214 | 2005-10-19 19:51:16 +0000 | [diff] [blame] | 45 | // |
| 46 | |
| 47 | def : Processor<"601", G3Itineraries, []>; |
| 48 | def : Processor<"602", G3Itineraries, []>; |
| 49 | def : Processor<"603", G3Itineraries, []>; |
| Jim Laskey | f5fc2cb | 2005-10-21 19:05:19 +0000 | [diff] [blame] | 50 | def : Processor<"603e", G3Itineraries, []>; |
| 51 | def : Processor<"603ev", G3Itineraries, []>; |
| Jim Laskey | 5384214 | 2005-10-19 19:51:16 +0000 | [diff] [blame] | 52 | def : Processor<"604", G3Itineraries, []>; |
| Jim Laskey | f5fc2cb | 2005-10-21 19:05:19 +0000 | [diff] [blame] | 53 | def : Processor<"604e", G3Itineraries, []>; |
| 54 | def : Processor<"620", G3Itineraries, []>; |
| 55 | def : Processor<"7400", G4Itineraries, [FeatureAltivec]>; |
| 56 | def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>; |
| Jim Laskey | 5384214 | 2005-10-19 19:51:16 +0000 | [diff] [blame] | 57 | def : Processor<"750", G3Itineraries, []>; |
| Jim Laskey | 5384214 | 2005-10-19 19:51:16 +0000 | [diff] [blame] | 58 | def : Processor<"970", G5Itineraries, |
| Jim Laskey | f5fc2cb | 2005-10-21 19:05:19 +0000 | [diff] [blame] | 59 | [FeatureAltivec, FeatureGPUL, FeatureFSqrt, |
| Chris Lattner | 4245f1d | 2005-10-21 22:15:43 +0000 | [diff] [blame] | 60 | Feature64Bit /*, Feature64BitRegs*/]>; |
| Jim Laskey | f5fc2cb | 2005-10-21 19:05:19 +0000 | [diff] [blame] | 61 | def : Processor<"g4", G4Itineraries, [FeatureAltivec]>; |
| 62 | def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>; |
| Jim Laskey | 5384214 | 2005-10-19 19:51:16 +0000 | [diff] [blame] | 63 | def : Processor<"g5", G5Itineraries, |
| Jim Laskey | f5fc2cb | 2005-10-21 19:05:19 +0000 | [diff] [blame] | 64 | [FeatureAltivec, FeatureGPUL, FeatureFSqrt, |
| Chris Lattner | 4245f1d | 2005-10-21 22:15:43 +0000 | [diff] [blame] | 65 | Feature64Bit /*, Feature64BitRegs*/]>; |
| Jim Laskey | f5fc2cb | 2005-10-21 19:05:19 +0000 | [diff] [blame] | 66 | def : Processor<"generic", G3Itineraries, []>; |
| Jim Laskey | 5384214 | 2005-10-19 19:51:16 +0000 | [diff] [blame] | 67 | |
| 68 | |
| Chris Lattner | 4c7b43b | 2005-10-14 23:37:35 +0000 | [diff] [blame] | 69 | def PPC : Target { |
| 70 | // Pointers on PPC are 32-bits in size. |
| 71 | let PointerType = i32; |
| 72 | |
| 73 | // According to the Mach-O Runtime ABI, these regs are nonvolatile across |
| 74 | // calls |
| 75 | let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19, |
| 76 | R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15, |
| 77 | F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, |
| 78 | F30, F31, CR2, CR3, CR4, LR]; |
| 79 | |
| 80 | // Pull in Instruction Info: |
| 81 | let InstructionSet = PowerPCInstrInfo; |
| 82 | } |