blob: 3ae0c88d0c941343d3e7be0564a58f2e36b44fc3 [file] [log] [blame]
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000029#include "llvm/ADT/Statistic.h"
30#include "llvm/ADT/STLExtras.h"
Chris Lattner27f29162004-10-26 15:35:58 +000031#include <algorithm>
Chris Lattner2c2c6c62006-01-22 23:41:00 +000032#include <iostream>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000033using namespace llvm;
34
35namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000036 Statistic<> NumSpills("spiller", "Number of register spills");
37 Statistic<> NumStores("spiller", "Number of stores added");
38 Statistic<> NumLoads ("spiller", "Number of loads added");
Chris Lattner7fb64342004-10-01 19:04:51 +000039 Statistic<> NumReused("spiller", "Number of values reused");
Chris Lattner52b25db2004-10-01 19:47:12 +000040 Statistic<> NumDSE ("spiller", "Number of dead stores elided");
Chris Lattner1118d252006-02-03 02:02:59 +000041 Statistic<> NumDCE ("spiller", "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000042
Chris Lattner8c4d88d2004-09-30 01:54:45 +000043 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000044
Chris Lattner8c4d88d2004-09-30 01:54:45 +000045 cl::opt<SpillerName>
46 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000047 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000048 cl::Prefix,
49 cl::values(clEnumVal(simple, " simple spiller"),
50 clEnumVal(local, " local spiller"),
51 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000052 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000053}
54
Chris Lattner8c4d88d2004-09-30 01:54:45 +000055//===----------------------------------------------------------------------===//
56// VirtRegMap implementation
57//===----------------------------------------------------------------------===//
58
59void VirtRegMap::grow() {
Chris Lattner7f690e62004-09-30 02:15:18 +000060 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
61 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000062}
63
Chris Lattner8c4d88d2004-09-30 01:54:45 +000064int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
65 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000066 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000067 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000068 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
69 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
70 RC->getAlignment());
71 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000072 ++NumSpills;
73 return frameIndex;
74}
75
76void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
77 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000078 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000079 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000080 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000081}
82
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000083void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
84 unsigned OpNo, MachineInstr *NewMI) {
85 // Move previous memory references folded to new instruction.
86 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +000087 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000088 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
89 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +000090 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +000091 }
Chris Lattnerdbea9732004-09-30 16:35:08 +000092
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000093 ModRef MRInfo;
94 if (!OldMI->getOperand(OpNo).isDef()) {
95 assert(OldMI->getOperand(OpNo).isUse() && "Operand is not use or def?");
96 MRInfo = isRef;
97 } else {
98 MRInfo = OldMI->getOperand(OpNo).isUse() ? isModRef : isMod;
99 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000100
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000101 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000102 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000103}
104
Chris Lattner7f690e62004-09-30 02:15:18 +0000105void VirtRegMap::print(std::ostream &OS) const {
106 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000107
Chris Lattner7f690e62004-09-30 02:15:18 +0000108 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000109 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000110 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
111 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
112 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000113
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000114 }
115
116 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000117 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
118 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
119 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
120 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000121}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000122
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000123void VirtRegMap::dump() const { print(std::cerr); }
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000124
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000125
126//===----------------------------------------------------------------------===//
127// Simple Spiller Implementation
128//===----------------------------------------------------------------------===//
129
130Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000131
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000132namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000133 struct SimpleSpiller : public Spiller {
134 bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap &VRM);
135 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000136}
137
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000138bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF,
139 const VirtRegMap &VRM) {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000140 DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
141 DEBUG(std::cerr << "********** Function: "
142 << MF.getFunction()->getName() << '\n');
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000143 const TargetMachine &TM = MF.getTarget();
144 const MRegisterInfo &MRI = *TM.getRegisterInfo();
145 bool *PhysRegsUsed = MF.getUsedPhysregs();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000146
Chris Lattner4ea1b822004-09-30 02:33:48 +0000147 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
148 // each vreg once (in the case where a spilled vreg is used by multiple
149 // operands). This is always smaller than the number of operands to the
150 // current machine instr, so it should be small.
151 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000152
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000153 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
154 MBBI != E; ++MBBI) {
155 DEBUG(std::cerr << MBBI->getBasicBlock()->getName() << ":\n");
156 MachineBasicBlock &MBB = *MBBI;
157 for (MachineBasicBlock::iterator MII = MBB.begin(),
158 E = MBB.end(); MII != E; ++MII) {
159 MachineInstr &MI = *MII;
160 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000161 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000162 if (MO.isRegister() && MO.getReg())
163 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
164 unsigned VirtReg = MO.getReg();
165 unsigned PhysReg = VRM.getPhys(VirtReg);
166 if (VRM.hasStackSlot(VirtReg)) {
167 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000168 const TargetRegisterClass* RC =
169 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000170
Chris Lattner886dd912005-04-04 21:35:34 +0000171 if (MO.isUse() &&
172 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
173 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000174 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000175 LoadedRegs.push_back(VirtReg);
176 ++NumLoads;
177 DEBUG(std::cerr << '\t' << *prior(MII));
178 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000179
Chris Lattner886dd912005-04-04 21:35:34 +0000180 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000181 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000182 ++NumStores;
183 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000184 }
Chris Lattner886dd912005-04-04 21:35:34 +0000185 PhysRegsUsed[PhysReg] = true;
186 MI.SetMachineOperandReg(i, PhysReg);
187 } else {
188 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000189 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000190 }
Chris Lattner886dd912005-04-04 21:35:34 +0000191
Chris Lattner477e4552004-09-30 16:10:45 +0000192 DEBUG(std::cerr << '\t' << MI);
Chris Lattner4ea1b822004-09-30 02:33:48 +0000193 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000194 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000195 }
196 return true;
197}
198
199//===----------------------------------------------------------------------===//
200// Local Spiller Implementation
201//===----------------------------------------------------------------------===//
202
203namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000204 /// LocalSpiller - This spiller does a simple pass over the machine basic
205 /// block to attempt to keep spills in registers as much as possible for
206 /// blocks that have low register pressure (the vreg may be spilled due to
207 /// register pressure in other blocks).
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000208 class LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000209 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000210 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000211 public:
Chris Lattner7fb64342004-10-01 19:04:51 +0000212 bool runOnMachineFunction(MachineFunction &MF, const VirtRegMap &VRM) {
213 MRI = MF.getTarget().getRegisterInfo();
214 TII = MF.getTarget().getInstrInfo();
215 DEBUG(std::cerr << "\n**** Local spiller rewriting function '"
216 << MF.getFunction()->getName() << "':\n");
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000217
Chris Lattner7fb64342004-10-01 19:04:51 +0000218 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
219 MBB != E; ++MBB)
220 RewriteMBB(*MBB, VRM);
221 return true;
222 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000223 private:
Chris Lattner7fb64342004-10-01 19:04:51 +0000224 void RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM);
225 void ClobberPhysReg(unsigned PR, std::map<int, unsigned> &SpillSlots,
Chris Lattner07cf1412006-02-03 00:36:31 +0000226 std::multimap<unsigned, int> &PhysRegs);
Chris Lattner7fb64342004-10-01 19:04:51 +0000227 void ClobberPhysRegOnly(unsigned PR, std::map<int, unsigned> &SpillSlots,
Chris Lattner07cf1412006-02-03 00:36:31 +0000228 std::multimap<unsigned, int> &PhysRegs);
229 void ModifyStackSlot(int Slot, std::map<int, unsigned> &SpillSlots,
230 std::multimap<unsigned, int> &PhysRegs);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000231 };
232}
233
Chris Lattner66cf80f2006-02-03 23:13:58 +0000234/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
235/// top down, keep track of which spills slots are available in each register.
236class AvailableSpills {
237 const MRegisterInfo *MRI;
238 const TargetInstrInfo *TII;
239
240 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
241 // register values that are still available, due to being loaded or stored to,
242 // but not invalidated yet.
243 std::map<int, unsigned> SpillSlotsAvailable;
244
245 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
246 // which stack slot values are currently held by a physreg. This is used to
247 // invalidate entries in SpillSlotsAvailable when a physreg is modified.
248 std::multimap<unsigned, int> PhysRegsAvailable;
249
250 void ClobberPhysRegOnly(unsigned PhysReg);
251public:
252 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
253 : MRI(mri), TII(tii) {
254 }
255
256 /// getSpillSlotPhysReg - If the specified stack slot is available in a
257 /// physical register, return that PhysReg, otherwise return 0.
258 unsigned getSpillSlotPhysReg(int Slot) const {
259 std::map<int, unsigned>::const_iterator I = SpillSlotsAvailable.find(Slot);
260 if (I != SpillSlotsAvailable.end())
261 return I->second;
262 return 0;
263 }
264
265 /// addAvailable - Mark that the specified stack slot is available in the
266 /// specified physreg.
267 void addAvailable(int Slot, unsigned Reg) {
268 PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
269 SpillSlotsAvailable[Slot] = Reg;
270
271 DEBUG(std::cerr << "Remembering SS#" << Slot << " in physreg "
272 << MRI->getName(Reg) << "\n");
273 }
274
275
276 /// ClobberPhysReg - This is called when the specified physreg changes
277 /// value. We use this to invalidate any info about stuff we thing lives in
278 /// it and any of its aliases.
279 void ClobberPhysReg(unsigned PhysReg);
280
281 /// ModifyStackSlot - This method is called when the value in a stack slot
282 /// changes. This removes information about which register the previous value
283 /// for this slot lives in (as the previous value is dead now).
284 void ModifyStackSlot(int Slot);
285};
286
287/// ClobberPhysRegOnly - This is called when the specified physreg changes
288/// value. We use this to invalidate any info about stuff we thing lives in it.
289void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
290 std::multimap<unsigned, int>::iterator I =
291 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000292 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000293 int Slot = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000294 PhysRegsAvailable.erase(I++);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000295 assert(SpillSlotsAvailable[Slot] == PhysReg &&
296 "Bidirectional map mismatch!");
297 SpillSlotsAvailable.erase(Slot);
Chris Lattner7fb64342004-10-01 19:04:51 +0000298 DEBUG(std::cerr << "PhysReg " << MRI->getName(PhysReg)
Chris Lattner07cf1412006-02-03 00:36:31 +0000299 << " clobbered, invalidating SS#" << Slot << "\n");
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000300 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000301}
302
Chris Lattner66cf80f2006-02-03 23:13:58 +0000303/// ClobberPhysReg - This is called when the specified physreg changes
304/// value. We use this to invalidate any info about stuff we thing lives in
305/// it and any of its aliases.
306void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000307 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000308 ClobberPhysRegOnly(*AS);
309 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000310}
311
Chris Lattner07cf1412006-02-03 00:36:31 +0000312/// ModifyStackSlot - This method is called when the value in a stack slot
313/// changes. This removes information about which register the previous value
314/// for this slot lives in (as the previous value is dead now).
Chris Lattner66cf80f2006-02-03 23:13:58 +0000315void AvailableSpills::ModifyStackSlot(int Slot) {
316 std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(Slot);
317 if (It == SpillSlotsAvailable.end()) return;
Chris Lattner07cf1412006-02-03 00:36:31 +0000318 unsigned Reg = It->second;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000319 SpillSlotsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000320
321 // This register may hold the value of multiple stack slots, only remove this
322 // stack slot from the set of values the register contains.
323 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
324 for (; ; ++I) {
325 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
326 "Map inverse broken!");
327 if (I->second == Slot) break;
328 }
329 PhysRegsAvailable.erase(I);
330}
331
332
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000333
Chris Lattner7fb64342004-10-01 19:04:51 +0000334// ReusedOp - For each reused operand, we keep track of a bit of information, in
335// case we need to rollback upon processing a new operand. See comments below.
336namespace {
337 struct ReusedOp {
338 // The MachineInstr operand that reused an available value.
339 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000340
Chris Lattner7fb64342004-10-01 19:04:51 +0000341 // StackSlot - The spill slot of the value being reused.
342 unsigned StackSlot;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000343
Chris Lattner7fb64342004-10-01 19:04:51 +0000344 // PhysRegReused - The physical register the value was available in.
345 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000346
Chris Lattner7fb64342004-10-01 19:04:51 +0000347 // AssignedPhysReg - The physreg that was assigned for use by the reload.
348 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000349
350 // VirtReg - The virtual register itself.
351 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000352
Chris Lattner8a61a752005-10-06 17:19:06 +0000353 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
354 unsigned vreg)
355 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
356 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000357 };
358}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000359
Chris Lattner7fb64342004-10-01 19:04:51 +0000360
361/// rewriteMBB - Keep track of which spills are available even after the
362/// register allocator is done with them. If possible, avoid reloading vregs.
363void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
364
Chris Lattner7fb64342004-10-01 19:04:51 +0000365 DEBUG(std::cerr << MBB.getBasicBlock()->getName() << ":\n");
366
Chris Lattner66cf80f2006-02-03 23:13:58 +0000367 // Spills - Keep track of which spilled values are available in physregs so
368 // that we can choose to reuse the physregs instead of emitting reloads.
369 AvailableSpills Spills(MRI, TII);
370
Chris Lattner7fb64342004-10-01 19:04:51 +0000371 std::vector<ReusedOp> ReusedOperands;
372
373 // DefAndUseVReg - When we see a def&use operand that is spilled, keep track
374 // of it. ".first" is the machine operand index (should always be 0 for now),
375 // and ".second" is the virtual register that is spilled.
376 std::vector<std::pair<unsigned, unsigned> > DefAndUseVReg;
377
Chris Lattner52b25db2004-10-01 19:47:12 +0000378 // MaybeDeadStores - When we need to write a value back into a stack slot,
379 // keep track of the inserted store. If the stack slot value is never read
380 // (because the value was used from some available register, for example), and
381 // subsequently stored to, the original store is dead. This map keeps track
382 // of inserted stores that are not used. If we see a subsequent store to the
383 // same stack slot, the original store is deleted.
384 std::map<int, MachineInstr*> MaybeDeadStores;
385
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000386 bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
387
Chris Lattner7fb64342004-10-01 19:04:51 +0000388 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
389 MII != E; ) {
390 MachineInstr &MI = *MII;
391 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
392
393 ReusedOperands.clear();
394 DefAndUseVReg.clear();
395
396 // Process all of the spilled uses and all non spilled reg references.
397 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
398 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000399 if (!MO.isRegister() || MO.getReg() == 0)
400 continue; // Ignore non-register operands.
401
402 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
403 // Ignore physregs for spilling, but remember that it is used by this
404 // function.
Chris Lattner886dd912005-04-04 21:35:34 +0000405 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner50ea01e2005-09-09 20:29:51 +0000406 continue;
407 }
408
409 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
410 "Not a virtual or a physical register?");
411
412 unsigned VirtReg = MO.getReg();
413 if (!VRM.hasStackSlot(VirtReg)) {
414 // This virtual register was assigned a physreg!
415 unsigned Phys = VRM.getPhys(VirtReg);
416 PhysRegsUsed[Phys] = true;
417 MI.SetMachineOperandReg(i, Phys);
418 continue;
419 }
420
421 // This virtual register is now known to be a spilled value.
422 if (!MO.isUse())
423 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000424
Chris Lattner50ea01e2005-09-09 20:29:51 +0000425 // If this is both a def and a use, we need to emit a store to the
426 // stack slot after the instruction. Keep track of D&U operands
427 // because we are about to change it to a physreg here.
428 if (MO.isDef()) {
429 // Remember that this was a def-and-use operand, and that the
430 // stack slot is live after this instruction executes.
431 DefAndUseVReg.push_back(std::make_pair(i, VirtReg));
432 }
433
434 int StackSlot = VRM.getStackSlot(VirtReg);
435 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000436
Chris Lattner50ea01e2005-09-09 20:29:51 +0000437 // Check to see if this stack slot is available.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000438 if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot))) {
439 // If this stack slot value is already available, reuse it!
Chris Lattner50ea01e2005-09-09 20:29:51 +0000440 DEBUG(std::cerr << "Reusing SS#" << StackSlot << " from physreg "
Chris Lattner66cf80f2006-02-03 23:13:58 +0000441 << MRI->getName(PhysReg) << " for vreg"
Chris Lattner50ea01e2005-09-09 20:29:51 +0000442 << VirtReg <<" instead of reloading into physreg "
443 << MRI->getName(VRM.getPhys(VirtReg)) << "\n");
Chris Lattner50ea01e2005-09-09 20:29:51 +0000444 MI.SetMachineOperandReg(i, PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000445
Chris Lattner50ea01e2005-09-09 20:29:51 +0000446 // The only technical detail we have is that we don't know that
447 // PhysReg won't be clobbered by a reloaded stack slot that occurs
448 // later in the instruction. In particular, consider 'op V1, V2'.
449 // If V1 is available in physreg R0, we would choose to reuse it
450 // here, instead of reloading it into the register the allocator
451 // indicated (say R1). However, V2 might have to be reloaded
452 // later, and it might indicate that it needs to live in R0. When
453 // this occurs, we need to have information available that
454 // indicates it is safe to use R1 for the reload instead of R0.
455 //
456 // To further complicate matters, we might conflict with an alias,
457 // or R0 and R1 might not be compatible with each other. In this
458 // case, we actually insert a reload for V1 in R1, ensuring that
459 // we can get at R0 or its alias.
460 ReusedOperands.push_back(ReusedOp(i, StackSlot, PhysReg,
Chris Lattner8a61a752005-10-06 17:19:06 +0000461 VRM.getPhys(VirtReg), VirtReg));
Chris Lattner50ea01e2005-09-09 20:29:51 +0000462 ++NumReused;
463 continue;
464 }
465
466 // Otherwise, reload it and remember that we have it.
467 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000468 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000469 const TargetRegisterClass* RC =
470 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000471
Chris Lattner50ea01e2005-09-09 20:29:51 +0000472 RecheckRegister:
473 // Note that, if we reused a register for a previous operand, the
474 // register we want to reload into might not actually be
475 // available. If this occurs, use the register indicated by the
476 // reuser.
477 if (!ReusedOperands.empty()) // This is most often empty.
478 for (unsigned ro = 0, e = ReusedOperands.size(); ro != e; ++ro)
479 if (ReusedOperands[ro].PhysRegReused == PhysReg) {
480 // Yup, use the reload register that we didn't use before.
481 PhysReg = ReusedOperands[ro].AssignedPhysReg;
482 goto RecheckRegister;
483 } else {
484 ReusedOp &Op = ReusedOperands[ro];
485 unsigned PRRU = Op.PhysRegReused;
486 if (MRI->areAliases(PRRU, PhysReg)) {
487 // Okay, we found out that an alias of a reused register
488 // was used. This isn't good because it means we have
489 // to undo a previous reuse.
Chris Lattner8a61a752005-10-06 17:19:06 +0000490 const TargetRegisterClass *AliasRC =
491 MBB.getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000492 MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg,
Chris Lattner8a61a752005-10-06 17:19:06 +0000493 Op.StackSlot, AliasRC);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000494 Spills.ClobberPhysReg(Op.AssignedPhysReg);
495 Spills.ClobberPhysReg(Op.PhysRegReused);
496
Chris Lattner52b25db2004-10-01 19:47:12 +0000497 // Any stores to this stack slot are not dead anymore.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000498 MaybeDeadStores.erase(Op.StackSlot);
Chris Lattner52b25db2004-10-01 19:47:12 +0000499
Chris Lattner50ea01e2005-09-09 20:29:51 +0000500 MI.SetMachineOperandReg(Op.Operand, Op.AssignedPhysReg);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000501
502 Spills.addAvailable(Op.StackSlot, Op.AssignedPhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000503 ++NumLoads;
504 DEBUG(std::cerr << '\t' << *prior(MII));
Chris Lattner7fb64342004-10-01 19:04:51 +0000505
Chris Lattner50ea01e2005-09-09 20:29:51 +0000506 DEBUG(std::cerr << "Reuse undone!\n");
507 ReusedOperands.erase(ReusedOperands.begin()+ro);
508 --NumReused;
509 goto ContinueReload;
Chris Lattner7fb64342004-10-01 19:04:51 +0000510 }
511 }
Chris Lattner50ea01e2005-09-09 20:29:51 +0000512 ContinueReload:
513 PhysRegsUsed[PhysReg] = true;
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000514 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000515 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000516 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000517
518 // Any stores to this stack slot are not dead anymore.
519 MaybeDeadStores.erase(StackSlot);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000520 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000521 ++NumLoads;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000522 MI.SetMachineOperandReg(i, PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000523 DEBUG(std::cerr << '\t' << *prior(MII));
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000524 }
525
Chris Lattner7fb64342004-10-01 19:04:51 +0000526 // Loop over all of the implicit defs, clearing them from our available
527 // sets.
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000528 for (const unsigned *ImpDef = TII->getImplicitDefs(MI.getOpcode());
529 *ImpDef; ++ImpDef) {
530 PhysRegsUsed[*ImpDef] = true;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000531 Spills.ClobberPhysReg(*ImpDef);
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000532 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000533
Chris Lattner7fb64342004-10-01 19:04:51 +0000534 DEBUG(std::cerr << '\t' << MI);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000535
Chris Lattner7fb64342004-10-01 19:04:51 +0000536 // If we have folded references to memory operands, make sure we clear all
537 // physical registers that may contain the value of the spilled virtual
538 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000539 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
540 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000541 DEBUG(std::cerr << "Folded vreg: " << I->second.first << " MR: "
542 << I->second.second);
543 unsigned VirtReg = I->second.first;
544 VirtRegMap::ModRef MR = I->second.second;
Chris Lattnercea86882005-09-19 06:56:21 +0000545 if (!VRM.hasStackSlot(VirtReg)) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000546 DEBUG(std::cerr << ": No stack slot!\n");
Chris Lattnercea86882005-09-19 06:56:21 +0000547 continue;
548 }
549 int SS = VRM.getStackSlot(VirtReg);
550 DEBUG(std::cerr << " - StackSlot: " << SS << "\n");
551
552 // If this folded instruction is just a use, check to see if it's a
553 // straight load from the virt reg slot.
554 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
555 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000556 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
557 // If this spill slot is available, turn it into a copy (or nothing)
558 // instead of leaving it as a load!
Chris Lattner66cf80f2006-02-03 23:13:58 +0000559 unsigned InReg;
560 if (FrameIdx == SS && (InReg = Spills.getSpillSlotPhysReg(SS))) {
Chris Lattnercea86882005-09-19 06:56:21 +0000561 DEBUG(std::cerr << "Promoted Load To Copy: " << MI);
562 MachineFunction &MF = *MBB.getParent();
Chris Lattner66cf80f2006-02-03 23:13:58 +0000563 if (DestReg != InReg) {
564 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
Chris Lattnercea86882005-09-19 06:56:21 +0000565 MF.getSSARegMap()->getRegClass(VirtReg));
Chris Lattner22480c42005-10-05 18:30:19 +0000566 // Revisit the copy so we make sure to notice the effects of the
567 // operation on the destreg (either needing to RA it if it's
568 // virtual or needing to clobber any values if it's physical).
569 NextMII = &MI;
570 --NextMII; // backtrack to the copy.
Chris Lattnercea86882005-09-19 06:56:21 +0000571 }
572 MBB.erase(&MI);
573 goto ProcessNextInst;
574 }
575 }
576 }
577
578 // If this reference is not a use, any previous store is now dead.
579 // Otherwise, the store to this stack slot is not dead anymore.
580 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
581 if (MDSI != MaybeDeadStores.end()) {
582 if (MR & VirtRegMap::isRef) // Previous store is not dead.
583 MaybeDeadStores.erase(MDSI);
584 else {
585 // If we get here, the store is dead, nuke it now.
586 assert(MR == VirtRegMap::isMod && "Can't be modref!");
587 MBB.erase(MDSI->second);
588 MaybeDeadStores.erase(MDSI);
589 ++NumDSE;
590 }
591 }
592
593 // If the spill slot value is available, and this is a new definition of
594 // the value, the value is not available anymore.
595 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +0000596 // Notice that the value in this stack slot has been modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000597 Spills.ModifyStackSlot(SS);
Chris Lattnercd816392006-02-02 23:29:36 +0000598
599 // If this is *just* a mod of the value, check to see if this is just a
600 // store to the spill slot (i.e. the spill got merged into the copy). If
601 // so, realize that the vreg is available now, and add the store to the
602 // MaybeDeadStore info.
603 int StackSlot;
604 if (!(MR & VirtRegMap::isRef)) {
605 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
606 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
607 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +0000608 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +0000609 // this as a potentially dead store in case there is a subsequent
610 // store into the stack slot without a read from it.
611 MaybeDeadStores[StackSlot] = &MI;
612
Chris Lattnercd816392006-02-02 23:29:36 +0000613 // If the stack slot value was previously available in some other
614 // register, change it now. Otherwise, make the register available,
615 // in PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000616 Spills.addAvailable(StackSlot, SrcReg);
Chris Lattnercd816392006-02-02 23:29:36 +0000617 }
618 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000619 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000620 }
621
Chris Lattner7fb64342004-10-01 19:04:51 +0000622 // Process all of the spilled defs.
623 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
624 MachineOperand &MO = MI.getOperand(i);
625 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
626 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000627
Chris Lattner7fb64342004-10-01 19:04:51 +0000628 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
629 // Check to see if this is a def-and-use vreg operand that we do need
630 // to insert a store for.
631 bool OpTakenCareOf = false;
632 if (MO.isUse() && !DefAndUseVReg.empty()) {
633 for (unsigned dau = 0, e = DefAndUseVReg.size(); dau != e; ++dau)
634 if (DefAndUseVReg[dau].first == i) {
635 VirtReg = DefAndUseVReg[dau].second;
636 OpTakenCareOf = true;
637 break;
638 }
639 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000640
Chris Lattner7fb64342004-10-01 19:04:51 +0000641 if (!OpTakenCareOf) {
Chris Lattner109afed2006-02-03 03:16:14 +0000642 // Check to see if this is a noop copy. If so, eliminate the
643 // instruction before considering the dest reg to be changed.
644 unsigned Src, Dst;
645 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
646 ++NumDCE;
647 DEBUG(std::cerr << "Removing now-noop copy: " << MI);
648 MBB.erase(&MI);
649 goto ProcessNextInst;
650 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000651 Spills.ClobberPhysReg(VirtReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000652 continue;
Chris Lattner7fb64342004-10-01 19:04:51 +0000653 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000654 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000655
Chris Lattner84e752a2006-02-03 03:06:49 +0000656 // The only vregs left are stack slot definitions.
657 int StackSlot = VRM.getStackSlot(VirtReg);
658 const TargetRegisterClass *RC =
659 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
660 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000661
Chris Lattner84e752a2006-02-03 03:06:49 +0000662 // If this is a def&use operand, and we used a different physreg for
663 // it than the one assigned, make sure to execute the store from the
664 // correct physical register.
665 if (MO.getReg() == VirtReg)
666 PhysReg = VRM.getPhys(VirtReg);
667 else
668 PhysReg = MO.getReg();
Chris Lattner7fb64342004-10-01 19:04:51 +0000669
Chris Lattner84e752a2006-02-03 03:06:49 +0000670 PhysRegsUsed[PhysReg] = true;
671 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
672 DEBUG(std::cerr << "Store:\t" << *next(MII));
673 MI.SetMachineOperandReg(i, PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000674
Chris Lattner109afed2006-02-03 03:16:14 +0000675 // Check to see if this is a noop copy. If so, eliminate the
676 // instruction before considering the dest reg to be changed.
677 {
678 unsigned Src, Dst;
679 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
680 ++NumDCE;
681 DEBUG(std::cerr << "Removing now-noop copy: " << MI);
682 MBB.erase(&MI);
683 goto ProcessNextInst;
684 }
685 }
686
Chris Lattner84e752a2006-02-03 03:06:49 +0000687 // If there is a dead store to this stack slot, nuke it now.
688 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
689 if (LastStore) {
690 DEBUG(std::cerr << " Killed store:\t" << *LastStore);
691 ++NumDSE;
692 MBB.erase(LastStore);
Chris Lattner7fb64342004-10-01 19:04:51 +0000693 }
Chris Lattner84e752a2006-02-03 03:06:49 +0000694 LastStore = next(MII);
695
696 // If the stack slot value was previously available in some other
697 // register, change it now. Otherwise, make the register available,
698 // in PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000699 Spills.ModifyStackSlot(StackSlot);
700 Spills.ClobberPhysReg(PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000701
Chris Lattner66cf80f2006-02-03 23:13:58 +0000702 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000703 ++NumStores;
Chris Lattner7fb64342004-10-01 19:04:51 +0000704 }
705 }
Chris Lattnercea86882005-09-19 06:56:21 +0000706 ProcessNextInst:
Chris Lattner7fb64342004-10-01 19:04:51 +0000707 MII = NextMII;
708 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000709}
710
711
Chris Lattner7fb64342004-10-01 19:04:51 +0000712
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000713llvm::Spiller* llvm::createSpiller() {
714 switch (SpillerOpt) {
715 default: assert(0 && "Unreachable!");
716 case local:
717 return new LocalSpiller();
718 case simple:
719 return new SimpleSpiller();
720 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000721}