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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 598751ed2544291ba623e013b4e0b61bf56ca9c4 / . / lib / CodeGen / SelectionDAG / TargetLowering.cpp
blob: 9d4f90717b204b35491ca5b4beaee1d7625a7f91 [file] [log] [blame]
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]2//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]7//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
Chris Lattneraf76e592009-08-22 20:48:53 +0000[diff] [blame]15#include "llvm/MC/MCAsmInfo.h"
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]16#include "llvm/MC/MCExpr.h"
Owen Anderson07000c62006-05-12 06:33:49 +0000[diff] [blame]17#include "llvm/Target/TargetData.h"
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]18#include "llvm/Target/TargetLoweringObjectFile.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]19#include "llvm/Target/TargetMachine.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]20#include "llvm/Target/TargetRegisterInfo.h"
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]21#include "llvm/GlobalVariable.h"
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]22#include "llvm/DerivedTypes.h"
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]23#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]24#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]25#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]26#include "llvm/CodeGen/SelectionDAG.h"
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]27#include "llvm/ADT/STLExtras.h"
Torok Edwinc25e7582009-07-11 20:10:48 +0000[diff] [blame]28#include "llvm/Support/ErrorHandling.h"
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]29#include "llvm/Support/MathExtras.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]30using namespace llvm;
31
Rafael Espindola9a580232009-02-27 13:37:18 +0000[diff] [blame]32namespace llvm {
33TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
34 bool isLocal = GV->hasLocalLinkage();
35 bool isDeclaration = GV->isDeclaration();
36 // FIXME: what should we do for protected and internal visibility?
37 // For variables, is internal different from hidden?
38 bool isHidden = GV->hasHiddenVisibility();
39
40 if (reloc == Reloc::PIC_) {
41 if (isLocal || isHidden)
42 return TLSModel::LocalDynamic;
43 else
44 return TLSModel::GeneralDynamic;
45 } else {
46 if (!isDeclaration || isHidden)
47 return TLSModel::LocalExec;
48 else
49 return TLSModel::InitialExec;
50 }
51}
52}
53
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]54/// InitLibcallNames - Set default libcall names.
55///
Evan Cheng79cca502007-01-12 22:51:10 +0000[diff] [blame]56static void InitLibcallNames(const char **Names) {
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]57 Names[RTLIB::SHL_I16] = "__ashlhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]58 Names[RTLIB::SHL_I32] = "__ashlsi3";
59 Names[RTLIB::SHL_I64] = "__ashldi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]60 Names[RTLIB::SHL_I128] = "__ashlti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]61 Names[RTLIB::SRL_I16] = "__lshrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]62 Names[RTLIB::SRL_I32] = "__lshrsi3";
63 Names[RTLIB::SRL_I64] = "__lshrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]64 Names[RTLIB::SRL_I128] = "__lshrti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]65 Names[RTLIB::SRA_I16] = "__ashrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]66 Names[RTLIB::SRA_I32] = "__ashrsi3";
67 Names[RTLIB::SRA_I64] = "__ashrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]68 Names[RTLIB::SRA_I128] = "__ashrti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]69 Names[RTLIB::MUL_I8] = "__mulqi3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]70 Names[RTLIB::MUL_I16] = "__mulhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]71 Names[RTLIB::MUL_I32] = "__mulsi3";
72 Names[RTLIB::MUL_I64] = "__muldi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]73 Names[RTLIB::MUL_I128] = "__multi3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]74 Names[RTLIB::SDIV_I8] = "__divqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]75 Names[RTLIB::SDIV_I16] = "__divhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]76 Names[RTLIB::SDIV_I32] = "__divsi3";
77 Names[RTLIB::SDIV_I64] = "__divdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]78 Names[RTLIB::SDIV_I128] = "__divti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]79 Names[RTLIB::UDIV_I8] = "__udivqi3";
Anton Korobeynikovfb3f84f2009-05-08 18:50:54 +0000[diff] [blame]80 Names[RTLIB::UDIV_I16] = "__udivhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]81 Names[RTLIB::UDIV_I32] = "__udivsi3";
82 Names[RTLIB::UDIV_I64] = "__udivdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]83 Names[RTLIB::UDIV_I128] = "__udivti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]84 Names[RTLIB::SREM_I8] = "__modqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]85 Names[RTLIB::SREM_I16] = "__modhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]86 Names[RTLIB::SREM_I32] = "__modsi3";
87 Names[RTLIB::SREM_I64] = "__moddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]88 Names[RTLIB::SREM_I128] = "__modti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]89 Names[RTLIB::UREM_I8] = "__umodqi3";
Anton Korobeynikov9fe9c8e2009-05-03 13:19:57 +0000[diff] [blame]90 Names[RTLIB::UREM_I16] = "__umodhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]91 Names[RTLIB::UREM_I32] = "__umodsi3";
92 Names[RTLIB::UREM_I64] = "__umoddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]93 Names[RTLIB::UREM_I128] = "__umodti3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]94 Names[RTLIB::NEG_I32] = "__negsi2";
95 Names[RTLIB::NEG_I64] = "__negdi2";
96 Names[RTLIB::ADD_F32] = "__addsf3";
97 Names[RTLIB::ADD_F64] = "__adddf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]98 Names[RTLIB::ADD_F80] = "__addxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]99 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]100 Names[RTLIB::SUB_F32] = "__subsf3";
101 Names[RTLIB::SUB_F64] = "__subdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]102 Names[RTLIB::SUB_F80] = "__subxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]103 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]104 Names[RTLIB::MUL_F32] = "__mulsf3";
105 Names[RTLIB::MUL_F64] = "__muldf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]106 Names[RTLIB::MUL_F80] = "__mulxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]107 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]108 Names[RTLIB::DIV_F32] = "__divsf3";
109 Names[RTLIB::DIV_F64] = "__divdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]110 Names[RTLIB::DIV_F80] = "__divxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]111 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]112 Names[RTLIB::REM_F32] = "fmodf";
113 Names[RTLIB::REM_F64] = "fmod";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]114 Names[RTLIB::REM_F80] = "fmodl";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]115 Names[RTLIB::REM_PPCF128] = "fmodl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]116 Names[RTLIB::POWI_F32] = "__powisf2";
117 Names[RTLIB::POWI_F64] = "__powidf2";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]118 Names[RTLIB::POWI_F80] = "__powixf2";
119 Names[RTLIB::POWI_PPCF128] = "__powitf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]120 Names[RTLIB::SQRT_F32] = "sqrtf";
121 Names[RTLIB::SQRT_F64] = "sqrt";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]122 Names[RTLIB::SQRT_F80] = "sqrtl";
123 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000[diff] [blame]124 Names[RTLIB::LOG_F32] = "logf";
125 Names[RTLIB::LOG_F64] = "log";
126 Names[RTLIB::LOG_F80] = "logl";
127 Names[RTLIB::LOG_PPCF128] = "logl";
128 Names[RTLIB::LOG2_F32] = "log2f";
129 Names[RTLIB::LOG2_F64] = "log2";
130 Names[RTLIB::LOG2_F80] = "log2l";
131 Names[RTLIB::LOG2_PPCF128] = "log2l";
132 Names[RTLIB::LOG10_F32] = "log10f";
133 Names[RTLIB::LOG10_F64] = "log10";
134 Names[RTLIB::LOG10_F80] = "log10l";
135 Names[RTLIB::LOG10_PPCF128] = "log10l";
136 Names[RTLIB::EXP_F32] = "expf";
137 Names[RTLIB::EXP_F64] = "exp";
138 Names[RTLIB::EXP_F80] = "expl";
139 Names[RTLIB::EXP_PPCF128] = "expl";
140 Names[RTLIB::EXP2_F32] = "exp2f";
141 Names[RTLIB::EXP2_F64] = "exp2";
142 Names[RTLIB::EXP2_F80] = "exp2l";
143 Names[RTLIB::EXP2_PPCF128] = "exp2l";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]144 Names[RTLIB::SIN_F32] = "sinf";
145 Names[RTLIB::SIN_F64] = "sin";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]146 Names[RTLIB::SIN_F80] = "sinl";
147 Names[RTLIB::SIN_PPCF128] = "sinl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]148 Names[RTLIB::COS_F32] = "cosf";
149 Names[RTLIB::COS_F64] = "cos";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]150 Names[RTLIB::COS_F80] = "cosl";
151 Names[RTLIB::COS_PPCF128] = "cosl";
Dan Gohmane54be102007-10-11 23:09:10 +0000[diff] [blame]152 Names[RTLIB::POW_F32] = "powf";
153 Names[RTLIB::POW_F64] = "pow";
154 Names[RTLIB::POW_F80] = "powl";
155 Names[RTLIB::POW_PPCF128] = "powl";
Dan Gohman2bb1e3e2008-08-21 18:38:14 +0000[diff] [blame]156 Names[RTLIB::CEIL_F32] = "ceilf";
157 Names[RTLIB::CEIL_F64] = "ceil";
158 Names[RTLIB::CEIL_F80] = "ceill";
159 Names[RTLIB::CEIL_PPCF128] = "ceill";
160 Names[RTLIB::TRUNC_F32] = "truncf";
161 Names[RTLIB::TRUNC_F64] = "trunc";
162 Names[RTLIB::TRUNC_F80] = "truncl";
163 Names[RTLIB::TRUNC_PPCF128] = "truncl";
164 Names[RTLIB::RINT_F32] = "rintf";
165 Names[RTLIB::RINT_F64] = "rint";
166 Names[RTLIB::RINT_F80] = "rintl";
167 Names[RTLIB::RINT_PPCF128] = "rintl";
168 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
169 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
170 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
171 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
172 Names[RTLIB::FLOOR_F32] = "floorf";
173 Names[RTLIB::FLOOR_F64] = "floor";
174 Names[RTLIB::FLOOR_F80] = "floorl";
175 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Duncan Sandsd2c817e2010-03-14 21:08:40 +0000[diff] [blame]176 Names[RTLIB::COPYSIGN_F32] = "copysignf";
177 Names[RTLIB::COPYSIGN_F64] = "copysign";
178 Names[RTLIB::COPYSIGN_F80] = "copysignl";
179 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]180 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]181 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
182 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]183 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]184 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
185 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
186 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
187 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]188 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
189 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]190 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
191 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]192 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]193 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
194 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]195 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
196 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]197 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
Duncan Sandsbe1ad4d2008-07-10 15:33:02 +0000[diff] [blame]198 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]199 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]200 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]201 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]202 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]203 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]204 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
205 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]206 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
207 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]208 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]209 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
210 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]211 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
212 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]213 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]214 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
215 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]216 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]217 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]218 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]219 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]220 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
221 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
Duncan Sands9bed0f52008-07-11 16:57:02 +0000[diff] [blame]222 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
223 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]224 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
225 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]226 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
227 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
Dan Gohmand91446d2008-03-05 01:08:17 +0000[diff] [blame]228 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
229 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
230 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
231 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]232 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
233 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]234 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
235 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]236 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
237 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]238 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
239 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
240 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
241 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
242 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
243 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]244 Names[RTLIB::OEQ_F32] = "__eqsf2";
245 Names[RTLIB::OEQ_F64] = "__eqdf2";
246 Names[RTLIB::UNE_F32] = "__nesf2";
247 Names[RTLIB::UNE_F64] = "__nedf2";
248 Names[RTLIB::OGE_F32] = "__gesf2";
249 Names[RTLIB::OGE_F64] = "__gedf2";
250 Names[RTLIB::OLT_F32] = "__ltsf2";
251 Names[RTLIB::OLT_F64] = "__ltdf2";
252 Names[RTLIB::OLE_F32] = "__lesf2";
253 Names[RTLIB::OLE_F64] = "__ledf2";
254 Names[RTLIB::OGT_F32] = "__gtsf2";
255 Names[RTLIB::OGT_F64] = "__gtdf2";
256 Names[RTLIB::UO_F32] = "__unordsf2";
257 Names[RTLIB::UO_F64] = "__unorddf2";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]258 Names[RTLIB::O_F32] = "__unordsf2";
259 Names[RTLIB::O_F64] = "__unorddf2";
Sanjiv Guptaa114baa2009-07-30 09:12:56 +0000[diff] [blame]260 Names[RTLIB::MEMCPY] = "memcpy";
261 Names[RTLIB::MEMMOVE] = "memmove";
262 Names[RTLIB::MEMSET] = "memset";
Duncan Sandsb0f1e172009-05-22 20:36:31 +0000[diff] [blame]263 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]264 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
265 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
Jim Grosbachef6eb9c2010-06-18 23:03:10 +0000[diff] [blame]268 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
269 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]272 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
273 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
274 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
275 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
276 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
277 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
278 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
279 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
280 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
281 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
282 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
283 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
284 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
285 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
286 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
287 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
288 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
289 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
290 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4";
291 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
292 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
293 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
294 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
295 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]296}
297
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]298/// InitLibcallCallingConvs - Set default libcall CallingConvs.
299///
300static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
301 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
302 CCs[i] = CallingConv::C;
303 }
304}
305
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]306/// getFPEXT - Return the FPEXT_*_* value for the given types, or
307/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]308RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]309 if (OpVT == MVT::f32) {
310 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]311 return FPEXT_F32_F64;
312 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]313
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]314 return UNKNOWN_LIBCALL;
315}
316
317/// getFPROUND - Return the FPROUND_*_* value for the given types, or
318/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]319RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]320 if (RetVT == MVT::f32) {
321 if (OpVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]322 return FPROUND_F64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]323 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]324 return FPROUND_F80_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]325 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]326 return FPROUND_PPCF128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]327 } else if (RetVT == MVT::f64) {
328 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]329 return FPROUND_F80_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]330 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]331 return FPROUND_PPCF128_F64;
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]332 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]333
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]334 return UNKNOWN_LIBCALL;
335}
336
337/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
338/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]339RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]340 if (OpVT == MVT::f32) {
341 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]342 return FPTOSINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]343 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]344 return FPTOSINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]345 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]346 return FPTOSINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]347 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]348 return FPTOSINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]349 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]350 return FPTOSINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]351 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]352 if (RetVT == MVT::i8)
353 return FPTOSINT_F64_I8;
354 if (RetVT == MVT::i16)
355 return FPTOSINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]356 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]357 return FPTOSINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]358 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]359 return FPTOSINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]360 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]361 return FPTOSINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]362 } else if (OpVT == MVT::f80) {
363 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]364 return FPTOSINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]365 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]366 return FPTOSINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]367 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]368 return FPTOSINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]369 } else if (OpVT == MVT::ppcf128) {
370 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]371 return FPTOSINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]372 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]373 return FPTOSINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]374 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]375 return FPTOSINT_PPCF128_I128;
376 }
377 return UNKNOWN_LIBCALL;
378}
379
380/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
381/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]382RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]383 if (OpVT == MVT::f32) {
384 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]385 return FPTOUINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]386 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]387 return FPTOUINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]388 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]389 return FPTOUINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]390 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]391 return FPTOUINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]392 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]393 return FPTOUINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]394 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]395 if (RetVT == MVT::i8)
396 return FPTOUINT_F64_I8;
397 if (RetVT == MVT::i16)
398 return FPTOUINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]399 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]400 return FPTOUINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]401 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]402 return FPTOUINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]403 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]404 return FPTOUINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]405 } else if (OpVT == MVT::f80) {
406 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]407 return FPTOUINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]408 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]409 return FPTOUINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]410 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]411 return FPTOUINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]412 } else if (OpVT == MVT::ppcf128) {
413 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]414 return FPTOUINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]415 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]416 return FPTOUINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]417 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]418 return FPTOUINT_PPCF128_I128;
419 }
420 return UNKNOWN_LIBCALL;
421}
422
423/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
424/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]425RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]426 if (OpVT == MVT::i32) {
427 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]428 return SINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]429 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]430 return SINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]431 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]432 return SINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]433 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]434 return SINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]435 } else if (OpVT == MVT::i64) {
436 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]437 return SINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]438 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]439 return SINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]440 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]441 return SINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]442 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]443 return SINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]444 } else if (OpVT == MVT::i128) {
445 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]446 return SINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]447 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]448 return SINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]449 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]450 return SINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]451 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]452 return SINTTOFP_I128_PPCF128;
453 }
454 return UNKNOWN_LIBCALL;
455}
456
457/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
458/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]459RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]460 if (OpVT == MVT::i32) {
461 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]462 return UINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]463 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]464 return UINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]465 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]466 return UINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]467 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]468 return UINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]469 } else if (OpVT == MVT::i64) {
470 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]471 return UINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]472 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]473 return UINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]474 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]475 return UINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]476 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]477 return UINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]478 } else if (OpVT == MVT::i128) {
479 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]480 return UINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]481 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]482 return UINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]483 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]484 return UINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]485 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]486 return UINTTOFP_I128_PPCF128;
487 }
488 return UNKNOWN_LIBCALL;
489}
490
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]491/// InitCmpLibcallCCs - Set default comparison libcall CC.
492///
493static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
494 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
495 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
496 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
497 CCs[RTLIB::UNE_F32] = ISD::SETNE;
498 CCs[RTLIB::UNE_F64] = ISD::SETNE;
499 CCs[RTLIB::OGE_F32] = ISD::SETGE;
500 CCs[RTLIB::OGE_F64] = ISD::SETGE;
501 CCs[RTLIB::OLT_F32] = ISD::SETLT;
502 CCs[RTLIB::OLT_F64] = ISD::SETLT;
503 CCs[RTLIB::OLE_F32] = ISD::SETLE;
504 CCs[RTLIB::OLE_F64] = ISD::SETLE;
505 CCs[RTLIB::OGT_F32] = ISD::SETGT;
506 CCs[RTLIB::OGT_F64] = ISD::SETGT;
507 CCs[RTLIB::UO_F32] = ISD::SETNE;
508 CCs[RTLIB::UO_F64] = ISD::SETNE;
509 CCs[RTLIB::O_F32] = ISD::SETEQ;
510 CCs[RTLIB::O_F64] = ISD::SETEQ;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]511}
512
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]513/// NOTE: The constructor takes ownership of TLOF.
Dan Gohmanf0757b02010-04-21 01:34:56 +0000[diff] [blame]514TargetLowering::TargetLowering(const TargetMachine &tm,
515 const TargetLoweringObjectFile *tlof)
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]516 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]517 // All operations default to being supported.
518 memset(OpActions, 0, sizeof(OpActions));
Evan Cheng03294662008-10-14 21:26:46 +0000[diff] [blame]519 memset(LoadExtActions, 0, sizeof(LoadExtActions));
Chris Lattnerddf89562008-01-17 19:59:44 +0000[diff] [blame]520 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
Chris Lattnerc9133f92008-01-18 19:36:20 +0000[diff] [blame]521 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
Evan Cheng7f042682008-10-15 02:05:31 +0000[diff] [blame]522 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Dan Gohman93f81e22007-07-09 20:49:44 +0000[diff] [blame]523
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]524 // Set default actions for various operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]525 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]526 // Default all indexed load / store to expand.
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]527 for (unsigned IM = (unsigned)ISD::PRE_INC;
528 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]529 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
530 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]531 }
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]532
533 // These operations default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]534 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
535 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]536 }
Evan Chengd2cde682008-03-10 19:38:10 +0000[diff] [blame]537
538 // Most targets ignore the @llvm.prefetch intrinsic.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]539 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
Nate Begemane1795842008-02-14 08:57:00 +0000[diff] [blame]540
541 // ConstantFP nodes default to expand. Targets can either change this to
Evan Chengeb2f9692009-10-27 19:56:55 +0000[diff] [blame]542 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
Nate Begemane1795842008-02-14 08:57:00 +0000[diff] [blame]543 // to optimize expansions for certain constants.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]544 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
545 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
546 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]547
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]548 // These library functions default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]549 setOperationAction(ISD::FLOG , MVT::f64, Expand);
550 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
551 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
552 setOperationAction(ISD::FEXP , MVT::f64, Expand);
553 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
554 setOperationAction(ISD::FLOG , MVT::f32, Expand);
555 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
556 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
557 setOperationAction(ISD::FEXP , MVT::f32, Expand);
558 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]559
Chris Lattner41bab0b2008-01-15 21:58:08 +0000[diff] [blame]560 // Default ISD::TRAP to expand (which turns it into abort).
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]561 setOperationAction(ISD::TRAP, MVT::Other, Expand);
Chris Lattner41bab0b2008-01-15 21:58:08 +0000[diff] [blame]562
Owen Andersona69571c2006-05-03 01:29:57 +0000[diff] [blame]563 IsLittleEndian = TD->isLittleEndian();
Owen Anderson1d0be152009-08-13 21:58:54 +0000[diff] [blame]564 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]565 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]566 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Evan Chenga03a5dc2006-02-14 08:38:30 +0000[diff] [blame]567 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
Evan Cheng6ebf7bc2009-05-13 21:42:09 +0000[diff] [blame]568 benefitFromCodePlacementOpt = false;
Anton Korobeynikovd27a2582006-12-10 23:12:42 +0000[diff] [blame]569 UseUnderscoreSetJmp = false;
570 UseUnderscoreLongJmp = false;
Chris Lattner66180392007-02-25 01:28:05 +0000[diff] [blame]571 SelectIsExpensive = false;
Nate Begeman405e3ec2005-10-21 00:02:42 +0000[diff] [blame]572 IntDivIsCheap = false;
573 Pow2DivIsCheap = false;
Chris Lattneree4a7652006-01-25 18:57:15 +0000[diff] [blame]574 StackPointerRegisterToSaveRestore = 0;
Jim Laskey9bb3c932007-02-22 18:04:49 +0000[diff] [blame]575 ExceptionPointerRegister = 0;
576 ExceptionSelectorRegister = 0;
Duncan Sands03228082008-11-23 15:47:28 +0000[diff] [blame]577 BooleanContents = UndefinedBooleanContent;
Evan Cheng211ffa12010-05-19 20:19:50 +0000[diff] [blame]578 SchedPreferenceInfo = Sched::Latency;
Chris Lattner7acf5f32006-09-05 17:39:15 +0000[diff] [blame]579 JumpBufSize = 0;
Duraid Madina0c9e0ff2006-09-04 07:44:11 +0000[diff] [blame]580 JumpBufAlignment = 0;
Evan Chengfb8075d2008-02-28 00:43:03 +0000[diff] [blame]581 PrefLoopAlignment = 0;
Jim Grosbach9a526492010-06-23 16:07:42 +0000[diff] [blame]582 ShouldFoldAtomicFences = false;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]583
584 InitLibcallNames(LibcallRoutineNames);
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]585 InitCmpLibcallCCs(CmpLibcallCCs);
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]586 InitLibcallCallingConvs(LibcallCallingConvs);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]587}
588
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]589TargetLowering::~TargetLowering() {
590 delete &TLOF;
591}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]592
Mon P Wangf7ea6c32010-02-10 23:37:45 +0000[diff] [blame]593/// canOpTrap - Returns true if the operation can trap for the value type.
594/// VT must be a legal type.
595bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
596 assert(isTypeLegal(VT));
597 switch (Op) {
598 default:
599 return false;
600 case ISD::FDIV:
601 case ISD::FREM:
602 case ISD::SDIV:
603 case ISD::UDIV:
604 case ISD::SREM:
605 case ISD::UREM:
606 return true;
607 }
608}
609
610
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]611static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame^]612 unsigned &NumIntermediates,
613 EVT &RegisterVT,
614 TargetLowering *TLI) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]615 // Figure out the right, legal destination reg to copy into.
616 unsigned NumElts = VT.getVectorNumElements();
617 MVT EltTy = VT.getVectorElementType();
618
619 unsigned NumVectorRegs = 1;
620
621 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
622 // could break down into LHS/RHS like LegalizeDAG does.
623 if (!isPowerOf2_32(NumElts)) {
624 NumVectorRegs = NumElts;
625 NumElts = 1;
626 }
627
628 // Divide the input until we get to a supported size. This will always
629 // end with a scalar if the target doesn't support vectors.
630 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
631 NumElts >>= 1;
632 NumVectorRegs <<= 1;
633 }
634
635 NumIntermediates = NumVectorRegs;
636
637 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
638 if (!TLI->isTypeLegal(NewVT))
639 NewVT = EltTy;
640 IntermediateVT = NewVT;
641
642 EVT DestVT = TLI->getRegisterType(NewVT);
643 RegisterVT = DestVT;
644 if (EVT(DestVT).bitsLT(NewVT)) {
645 // Value is expanded, e.g. i64 -> i16.
646 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
647 } else {
648 // Otherwise, promotion or legal types use the same number of registers as
649 // the vector decimated to the appropriate level.
650 return NumVectorRegs;
651 }
652
653 return 1;
654}
655
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]656/// computeRegisterProperties - Once all of the register classes are added,
657/// this allows us to compute derived properties we expose.
658void TargetLowering::computeRegisterProperties() {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]659 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]660 "Too many value types for ValueTypeActions to hold!");
661
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]662 // Everything defaults to needing one register.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]663 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]664 NumRegistersForVT[i] = 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]665 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]666 }
667 // ...except isVoid, which doesn't need any registers.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]668 NumRegistersForVT[MVT::isVoid] = 0;
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]669
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]670 // Find the largest integer register class.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]671 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]672 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]673 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]674
675 // Every integer value type larger than this largest register takes twice as
676 // many registers to represent as the previous ValueType.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]677 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
Dan Gohman8a55ce42009-09-23 21:02:20 +0000[diff] [blame]678 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
679 if (!ExpandedVT.isInteger())
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]680 break;
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]681 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]682 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
683 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
Dan Gohman8a55ce42009-09-23 21:02:20 +0000[diff] [blame]684 ValueTypeActions.setTypeAction(ExpandedVT, Expand);
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]685 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]686
687 // Inspect all of the ValueType's smaller than the largest integer
688 // register to see which ones need promotion.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]689 unsigned LegalIntReg = LargestIntReg;
690 for (unsigned IntReg = LargestIntReg - 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]691 IntReg >= (unsigned)MVT::i1; --IntReg) {
692 EVT IVT = (MVT::SimpleValueType)IntReg;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]693 if (isTypeLegal(IVT)) {
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]694 LegalIntReg = IntReg;
695 } else {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]696 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]697 (MVT::SimpleValueType)LegalIntReg;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]698 ValueTypeActions.setTypeAction(IVT, Promote);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]699 }
700 }
701
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]702 // ppcf128 type is really two f64's.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]703 if (!isTypeLegal(MVT::ppcf128)) {
704 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
705 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
706 TransformToType[MVT::ppcf128] = MVT::f64;
707 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]708 }
709
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]710 // Decide how to handle f64. If the target does not have native f64 support,
711 // expand it to i64 and we will be generating soft float library calls.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]712 if (!isTypeLegal(MVT::f64)) {
713 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
714 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
715 TransformToType[MVT::f64] = MVT::i64;
716 ValueTypeActions.setTypeAction(MVT::f64, Expand);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]717 }
718
719 // Decide how to handle f32. If the target does not have native support for
720 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]721 if (!isTypeLegal(MVT::f32)) {
722 if (isTypeLegal(MVT::f64)) {
723 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
724 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
725 TransformToType[MVT::f32] = MVT::f64;
726 ValueTypeActions.setTypeAction(MVT::f32, Promote);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]727 } else {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]728 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
729 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
730 TransformToType[MVT::f32] = MVT::i32;
731 ValueTypeActions.setTypeAction(MVT::f32, Expand);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]732 }
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]733 }
Nate Begeman4ef3b812005-11-22 01:29:36 +0000[diff] [blame]734
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]735 // Loop over all of the vector value types to see which need transformations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]736 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
737 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]738 MVT VT = (MVT::SimpleValueType)i;
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame^]739 if (isTypeLegal(VT)) continue;
740
741 MVT IntermediateVT;
742 EVT RegisterVT;
743 unsigned NumIntermediates;
744 NumRegistersForVT[i] =
745 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
746 RegisterVT, this);
747 RegisterTypeForVT[i] = RegisterVT;
748
749 // Determine if there is a legal wider type.
750 bool IsLegalWiderType = false;
751 EVT EltVT = VT.getVectorElementType();
752 unsigned NElts = VT.getVectorNumElements();
753 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
754 EVT SVT = (MVT::SimpleValueType)nVT;
755 if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT &&
756 SVT.getVectorNumElements() > NElts && NElts != 1) {
757 TransformToType[i] = SVT;
758 ValueTypeActions.setTypeAction(VT, Promote);
759 IsLegalWiderType = true;
760 break;
Mon P Wang87c8a8f2008-12-18 20:03:17 +0000[diff] [blame]761 }
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame^]762 }
763 if (!IsLegalWiderType) {
764 EVT NVT = VT.getPow2VectorType();
765 if (NVT == VT) {
766 // Type is already a power of 2. The default action is to split.
767 TransformToType[i] = MVT::Other;
768 ValueTypeActions.setTypeAction(VT, Expand);
769 } else {
770 TransformToType[i] = NVT;
771 ValueTypeActions.setTypeAction(VT, Promote);
Mon P Wang87c8a8f2008-12-18 20:03:17 +0000[diff] [blame]772 }
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]773 }
Chris Lattner3a5935842006-03-16 19:50:01 +0000[diff] [blame]774 }
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]775}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]776
Evan Cheng72261582005-12-20 06:22:03 +0000[diff] [blame]777const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
778 return NULL;
779}
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]780
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]781
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]782MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
Owen Anderson1d0be152009-08-13 21:58:54 +0000[diff] [blame]783 return PointerTy.SimpleTy;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]784}
785
Sanjiv Gupta8f17a362009-12-28 02:40:33 +0000[diff] [blame]786MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
787 return MVT::i32; // return the default value
788}
789
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]790/// getVectorTypeBreakdown - Vector types are broken down into some number of
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]791/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
792/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
793/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]794///
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]795/// This method returns the number of registers needed, and the VT for each
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]796/// register. It also returns the VT and quantity of the intermediate values
797/// before they are promoted/expanded.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]798///
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]799unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]800 EVT &IntermediateVT,
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]801 unsigned &NumIntermediates,
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]802 EVT &RegisterVT) const {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]803 // Figure out the right, legal destination reg to copy into.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]804 unsigned NumElts = VT.getVectorNumElements();
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]805 EVT EltTy = VT.getVectorElementType();
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]806
807 unsigned NumVectorRegs = 1;
808
Nate Begemand73ab882007-11-27 19:28:48 +0000[diff] [blame]809 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
810 // could break down into LHS/RHS like LegalizeDAG does.
811 if (!isPowerOf2_32(NumElts)) {
812 NumVectorRegs = NumElts;
813 NumElts = 1;
814 }
815
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]816 // Divide the input until we get to a supported size. This will always
817 // end with a scalar if the target doesn't support vectors.
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]818 while (NumElts > 1 && !isTypeLegal(
819 EVT::getVectorVT(Context, EltTy, NumElts))) {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]820 NumElts >>= 1;
821 NumVectorRegs <<= 1;
822 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]823
824 NumIntermediates = NumVectorRegs;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]825
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]826 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]827 if (!isTypeLegal(NewVT))
828 NewVT = EltTy;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]829 IntermediateVT = NewVT;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]830
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]831 EVT DestVT = getRegisterType(Context, NewVT);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]832 RegisterVT = DestVT;
Duncan Sands8e4eb092008-06-08 20:54:56 +0000[diff] [blame]833 if (DestVT.bitsLT(NewVT)) {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]834 // Value is expanded, e.g. i64 -> i16.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]835 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]836 } else {
837 // Otherwise, promotion or legal types use the same number of registers as
838 // the vector decimated to the appropriate level.
Chris Lattner79227e22006-03-31 00:46:36 +0000[diff] [blame]839 return NumVectorRegs;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]840 }
841
Evan Chenge9b3da12006-05-17 18:10:06 +0000[diff] [blame]842 return 1;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]843}
844
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]845/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]846/// function arguments in the caller parameter area. This is the actual
847/// alignment, not its logarithm.
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]848unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]849 return TD->getCallFrameTypeAlignment(Ty);
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]850}
851
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]852/// getJumpTableEncoding - Return the entry encoding for a jump table in the
853/// current function. The returned value is a member of the
854/// MachineJumpTableInfo::JTEntryKind enum.
855unsigned TargetLowering::getJumpTableEncoding() const {
856 // In non-pic modes, just use the address of a block.
857 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
858 return MachineJumpTableInfo::EK_BlockAddress;
859
860 // In PIC mode, if the target supports a GPRel32 directive, use it.
861 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
862 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
863
864 // Otherwise, use a label difference.
865 return MachineJumpTableInfo::EK_LabelDifference32;
866}
867
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]868SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
869 SelectionDAG &DAG) const {
Chris Lattnerf1214cb2010-01-26 06:53:37 +0000[diff] [blame]870 // If our PIC model is GP relative, use the global offset table as the base.
871 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
Dale Johannesenb300d2a2009-02-07 00:55:49 +0000[diff] [blame]872 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
Evan Chengcc415862007-11-09 01:32:10 +0000[diff] [blame]873 return Table;
874}
875
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]876/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
877/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
878/// MCExpr.
879const MCExpr *
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]880TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
881 unsigned JTI,MCContext &Ctx) const{
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]882 // The normal PIC reloc base is the label at the start of the jump table.
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]883 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]884}
885
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]886bool
887TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
888 // Assume that everything is safe in static mode.
889 if (getTargetMachine().getRelocationModel() == Reloc::Static)
890 return true;
891
892 // In dynamic-no-pic mode, assume that known defined values are safe.
893 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
894 GA &&
895 !GA->getGlobal()->isDeclaration() &&
Duncan Sands667d4b82009-03-07 15:45:40 +0000[diff] [blame]896 !GA->getGlobal()->isWeakForLinker())
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]897 return true;
898
899 // Otherwise assume nothing is safe.
900 return false;
901}
902
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]903//===----------------------------------------------------------------------===//
904// Optimization Methods
905//===----------------------------------------------------------------------===//
906
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]907/// ShrinkDemandedConstant - Check to see if the specified operand of the
908/// specified instruction is a constant integer. If so, check to see if there
909/// are any bits set in the constant that are not demanded. If so, shrink the
910/// constant and return true.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]911bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]912 const APInt &Demanded) {
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]913 DebugLoc dl = Op.getDebugLoc();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]914
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]915 // FIXME: ISD::SELECT, ISD::SELECT_CC
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]916 switch (Op.getOpcode()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]917 default: break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]918 case ISD::XOR:
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]919 case ISD::AND:
920 case ISD::OR: {
921 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
922 if (!C) return false;
923
924 if (Op.getOpcode() == ISD::XOR &&
925 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
926 return false;
927
928 // if we can expand it to have all bits set, do it
929 if (C->getAPIntValue().intersects(~Demanded)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]930 EVT VT = Op.getValueType();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]931 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
932 DAG.getConstant(Demanded &
933 C->getAPIntValue(),
934 VT));
935 return CombineTo(Op, New);
936 }
937
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]938 break;
939 }
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]940 }
941
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]942 return false;
943}
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]944
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]945/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
946/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
947/// cast, but it could be generalized for targets with other types of
948/// implicit widening casts.
949bool
950TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
951 unsigned BitWidth,
952 const APInt &Demanded,
953 DebugLoc dl) {
954 assert(Op.getNumOperands() == 2 &&
955 "ShrinkDemandedOp only supports binary operators!");
956 assert(Op.getNode()->getNumValues() == 1 &&
957 "ShrinkDemandedOp only supports nodes with one result!");
958
959 // Don't do this if the node has another user, which may require the
960 // full value.
961 if (!Op.getNode()->hasOneUse())
962 return false;
963
964 // Search for the smallest integer type with free casts to and from
965 // Op's type. For expedience, just check power-of-2 integer types.
966 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
967 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
968 if (!isPowerOf2_32(SmallVTBits))
969 SmallVTBits = NextPowerOf2(SmallVTBits);
970 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]971 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]972 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
973 TLI.isZExtFree(SmallVT, Op.getValueType())) {
974 // We found a type with free casts.
975 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
976 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
977 Op.getNode()->getOperand(0)),
978 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
979 Op.getNode()->getOperand(1)));
980 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
981 return CombineTo(Op, Z);
982 }
983 }
984 return false;
985}
986
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]987/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
988/// DemandedMask bits of the result of Op are ever used downstream. If we can
989/// use this information to simplify Op, create a new simplified DAG node and
990/// return true, returning the original and new nodes in Old and New. Otherwise,
991/// analyze the expression and return a mask of KnownOne and KnownZero bits for
992/// the expression (used to simplify the caller). The KnownZero/One bits may
993/// only be accurate for those bits in the DemandedMask.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]994bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]995 const APInt &DemandedMask,
996 APInt &KnownZero,
997 APInt &KnownOne,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]998 TargetLoweringOpt &TLO,
999 unsigned Depth) const {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1000 unsigned BitWidth = DemandedMask.getBitWidth();
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1001 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1002 "Mask size mismatches value type size!");
1003 APInt NewMask = DemandedMask;
Dale Johannesen6f38cb62009-02-07 19:59:05 +0000[diff] [blame]1004 DebugLoc dl = Op.getDebugLoc();
Chris Lattner3fc5b012007-05-17 18:19:23 +0000[diff] [blame]1005
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1006 // Don't know anything.
1007 KnownZero = KnownOne = APInt(BitWidth, 0);
1008
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1009 // Other users may use these bits.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1010 if (!Op.getNode()->hasOneUse()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1011 if (Depth != 0) {
1012 // If not at the root, Just compute the KnownZero/KnownOne bits to
1013 // simplify things downstream.
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1014 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1015 return false;
1016 }
1017 // If this is the root being simplified, allow it to have multiple uses,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1018 // just set the NewMask to all bits.
1019 NewMask = APInt::getAllOnesValue(BitWidth);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1020 } else if (DemandedMask == 0) {
1021 // Not demanding any bits from Op.
1022 if (Op.getOpcode() != ISD::UNDEF)
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]1023 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1024 return false;
1025 } else if (Depth == 6) { // Limit search depth.
1026 return false;
1027 }
1028
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1029 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1030 switch (Op.getOpcode()) {
1031 case ISD::Constant:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1032 // We know all of the bits for a constant!
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1033 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
1034 KnownZero = ~KnownOne & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1035 return false; // Don't fall through, will infinitely loop.
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1036 case ISD::AND:
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1037 // If the RHS is a constant, check to see if the LHS would be zero without
1038 // using the bits from the RHS. Below, we use knowledge about the RHS to
1039 // simplify the LHS, here we're using information from the LHS to simplify
1040 // the RHS.
1041 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1042 APInt LHSZero, LHSOne;
1043 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1044 LHSZero, LHSOne, Depth+1);
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1045 // If the LHS already has zeros where RHSC does, this and is dead.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1046 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1047 return TLO.CombineTo(Op, Op.getOperand(0));
1048 // If any of the set bits in the RHS are known zero on the LHS, shrink
1049 // the constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1050 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1051 return true;
1052 }
1053
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1054 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1055 KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1056 return true;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1057 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1058 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1059 KnownZero2, KnownOne2, TLO, Depth+1))
1060 return true;
1061 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1062
1063 // If all of the demanded bits are known one on one side, return the other.
1064 // These bits cannot contribute to the result of the 'and'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1065 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1066 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1067 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1068 return TLO.CombineTo(Op, Op.getOperand(1));
1069 // If all of the demanded bits in the inputs are known zeros, return zero.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1070 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1071 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1072 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1073 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1074 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1075 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1076 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1077 return true;
1078
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1079 // Output known-1 bits are only known if set in both the LHS & RHS.
1080 KnownOne &= KnownOne2;
1081 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1082 KnownZero |= KnownZero2;
1083 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1084 case ISD::OR:
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1085 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1086 KnownOne, TLO, Depth+1))
1087 return true;
1088 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1089 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1090 KnownZero2, KnownOne2, TLO, Depth+1))
1091 return true;
1092 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1093
1094 // If all of the demanded bits are known zero on one side, return the other.
1095 // These bits cannot contribute to the result of the 'or'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1096 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1097 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1098 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1099 return TLO.CombineTo(Op, Op.getOperand(1));
1100 // If all of the potentially set bits on one side are known to be set on
1101 // the other side, just use the 'other' side.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1102 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1103 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1104 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1105 return TLO.CombineTo(Op, Op.getOperand(1));
1106 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1107 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1108 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1109 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1110 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1111 return true;
1112
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1113 // Output known-0 bits are only known if clear in both the LHS & RHS.
1114 KnownZero &= KnownZero2;
1115 // Output known-1 are known to be set if set in either the LHS | RHS.
1116 KnownOne |= KnownOne2;
1117 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1118 case ISD::XOR:
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1119 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1120 KnownOne, TLO, Depth+1))
1121 return true;
1122 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1123 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1124 KnownOne2, TLO, Depth+1))
1125 return true;
1126 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1127
1128 // If all of the demanded bits are known zero on one side, return the other.
1129 // These bits cannot contribute to the result of the 'xor'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1130 if ((KnownZero & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1131 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1132 if ((KnownZero2 & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1133 return TLO.CombineTo(Op, Op.getOperand(1));
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1134 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1135 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1136 return true;
1137
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1138 // If all of the unknown bits are known to be zero on one side or the other
1139 // (but not both) turn this into an *inclusive* or.
1140 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1141 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1142 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1143 Op.getOperand(0),
1144 Op.getOperand(1)));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1145
1146 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1147 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1148 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1149 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1150
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1151 // If all of the demanded bits on one side are known, and all of the set
1152 // bits on that side are also known to be set on the other side, turn this
1153 // into an AND, as we know the bits will be cleared.
1154 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1155 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1156 if ((KnownOne & KnownOne2) == KnownOne) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1157 EVT VT = Op.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1158 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1159 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1160 Op.getOperand(0), ANDC));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1161 }
1162 }
1163
1164 // If the RHS is a constant, see if we can simplify it.
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1165 // for XOR, we prefer to force bits to 1 if they will make a -1.
1166 // if we can't force bits, try to shrink constant
1167 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1168 APInt Expanded = C->getAPIntValue() | (~NewMask);
1169 // if we can expand it to have all bits set, do it
1170 if (Expanded.isAllOnesValue()) {
1171 if (Expanded != C->getAPIntValue()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1172 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1173 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1174 TLO.DAG.getConstant(Expanded, VT));
1175 return TLO.CombineTo(Op, New);
1176 }
1177 // if it already has all the bits set, nothing to change
1178 // but don't shrink either!
1179 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1180 return true;
1181 }
1182 }
1183
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1184 KnownZero = KnownZeroOut;
1185 KnownOne = KnownOneOut;
1186 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1187 case ISD::SELECT:
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1188 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1189 KnownOne, TLO, Depth+1))
1190 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1191 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1192 KnownOne2, TLO, Depth+1))
1193 return true;
1194 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1195 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1196
1197 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1198 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1199 return true;
1200
1201 // Only known if known in both the LHS and RHS.
1202 KnownOne &= KnownOne2;
1203 KnownZero &= KnownZero2;
1204 break;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1205 case ISD::SELECT_CC:
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1206 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1207 KnownOne, TLO, Depth+1))
1208 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1209 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1210 KnownOne2, TLO, Depth+1))
1211 return true;
1212 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1213 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1214
1215 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1216 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1217 return true;
1218
1219 // Only known if known in both the LHS and RHS.
1220 KnownOne &= KnownOne2;
1221 KnownZero &= KnownZero2;
1222 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1223 case ISD::SHL:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1224 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1225 unsigned ShAmt = SA->getZExtValue();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1226 SDValue InOp = Op.getOperand(0);
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1227
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1228 // If the shift count is an invalid immediate, don't do anything.
1229 if (ShAmt >= BitWidth)
1230 break;
1231
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1232 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1233 // single shift. We can do this if the bottom bits (which are shifted
1234 // out) are never demanded.
1235 if (InOp.getOpcode() == ISD::SRL &&
1236 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1237 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1238 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1239 unsigned Opc = ISD::SHL;
1240 int Diff = ShAmt-C1;
1241 if (Diff < 0) {
1242 Diff = -Diff;
1243 Opc = ISD::SRL;
1244 }
1245
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1246 SDValue NewSA =
Chris Lattner4e7e6cd2007-05-30 16:30:06 +0000[diff] [blame]1247 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1248 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1249 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1250 InOp.getOperand(0), NewSA));
1251 }
1252 }
1253
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1254 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1255 KnownZero, KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1256 return true;
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1257 KnownZero <<= SA->getZExtValue();
1258 KnownOne <<= SA->getZExtValue();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1259 // low bits known zero.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1260 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1261 }
1262 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1263 case ISD::SRL:
1264 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1265 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1266 unsigned ShAmt = SA->getZExtValue();
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1267 unsigned VTSize = VT.getSizeInBits();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1268 SDValue InOp = Op.getOperand(0);
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1269
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1270 // If the shift count is an invalid immediate, don't do anything.
1271 if (ShAmt >= BitWidth)
1272 break;
1273
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1274 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1275 // single shift. We can do this if the top bits (which are shifted out)
1276 // are never demanded.
1277 if (InOp.getOpcode() == ISD::SHL &&
1278 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1279 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1280 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1281 unsigned Opc = ISD::SRL;
1282 int Diff = ShAmt-C1;
1283 if (Diff < 0) {
1284 Diff = -Diff;
1285 Opc = ISD::SHL;
1286 }
1287
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1288 SDValue NewSA =
Chris Lattner8c7d2d52007-04-17 22:53:02 +0000[diff] [blame]1289 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1290 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1291 InOp.getOperand(0), NewSA));
1292 }
1293 }
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1294
1295 // Compute the new bits that are at the top now.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1296 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1297 KnownZero, KnownOne, TLO, Depth+1))
1298 return true;
1299 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1300 KnownZero = KnownZero.lshr(ShAmt);
1301 KnownOne = KnownOne.lshr(ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1302
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1303 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1304 KnownZero |= HighBits; // High bits known zero.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1305 }
1306 break;
1307 case ISD::SRA:
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1308 // If this is an arithmetic shift right and only the low-bit is set, we can
1309 // always convert this into a logical shr, even if the shift amount is
1310 // variable. The low bit of the shift cannot be an input sign bit unless
1311 // the shift amount is >= the size of the datatype, which is undefined.
1312 if (DemandedMask == 1)
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1313 return TLO.CombineTo(Op,
1314 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1315 Op.getOperand(0), Op.getOperand(1)));
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1316
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1317 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1318 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1319 unsigned ShAmt = SA->getZExtValue();
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1320
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1321 // If the shift count is an invalid immediate, don't do anything.
1322 if (ShAmt >= BitWidth)
1323 break;
1324
1325 APInt InDemandedMask = (NewMask << ShAmt);
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1326
1327 // If any of the demanded bits are produced by the sign extension, we also
1328 // demand the input sign bit.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1329 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1330 if (HighBits.intersects(NewMask))
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1331 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1332
1333 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1334 KnownZero, KnownOne, TLO, Depth+1))
1335 return true;
1336 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1337 KnownZero = KnownZero.lshr(ShAmt);
1338 KnownOne = KnownOne.lshr(ShAmt);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1339
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1340 // Handle the sign bit, adjusted to where it is now in the mask.
1341 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1342
1343 // If the input sign bit is known to be zero, or if none of the top bits
1344 // are demanded, turn this into an unsigned shift right.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1345 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1346 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1347 Op.getOperand(0),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1348 Op.getOperand(1)));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1349 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1350 KnownOne |= HighBits;
1351 }
1352 }
1353 break;
1354 case ISD::SIGN_EXTEND_INREG: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1355 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1356
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1357 // Sign extension. Compute the demanded bits in the result that are not
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1358 // present in the input.
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1359 APInt NewBits =
1360 APInt::getHighBitsSet(BitWidth,
1361 BitWidth - EVT.getScalarType().getSizeInBits()) &
1362 NewMask;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1363
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1364 // If none of the extended bits are demanded, eliminate the sextinreg.
1365 if (NewBits == 0)
1366 return TLO.CombineTo(Op, Op.getOperand(0));
1367
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1368 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits());
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1369 InSignBit.zext(BitWidth);
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1370 APInt InputDemandedBits =
1371 APInt::getLowBitsSet(BitWidth,
1372 EVT.getScalarType().getSizeInBits()) &
1373 NewMask;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1374
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1375 // Since the sign extended bits are demanded, we know that the sign
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1376 // bit is demanded.
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1377 InputDemandedBits |= InSignBit;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1378
1379 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1380 KnownZero, KnownOne, TLO, Depth+1))
1381 return true;
1382 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1383
1384 // If the sign bit of the input is known set or clear, then we know the
1385 // top bits of the result.
1386
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1387 // If the input sign bit is known zero, convert this into a zero extension.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1388 if (KnownZero.intersects(InSignBit))
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1389 return TLO.CombineTo(Op,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1390 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1391
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1392 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1393 KnownOne |= NewBits;
1394 KnownZero &= ~NewBits;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1395 } else { // Input sign bit unknown
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1396 KnownZero &= ~NewBits;
1397 KnownOne &= ~NewBits;
1398 }
1399 break;
1400 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1401 case ISD::ZERO_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1402 unsigned OperandBitWidth =
1403 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1404 APInt InMask = NewMask;
1405 InMask.trunc(OperandBitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1406
1407 // If none of the top bits are demanded, convert this into an any_extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1408 APInt NewBits =
1409 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1410 if (!NewBits.intersects(NewMask))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1411 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1412 Op.getValueType(),
1413 Op.getOperand(0)));
1414
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1415 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1416 KnownZero, KnownOne, TLO, Depth+1))
1417 return true;
1418 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1419 KnownZero.zext(BitWidth);
1420 KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1421 KnownZero |= NewBits;
1422 break;
1423 }
1424 case ISD::SIGN_EXTEND: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1425 EVT InVT = Op.getOperand(0).getValueType();
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1426 unsigned InBits = InVT.getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1427 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
Dan Gohman97360282008-03-11 21:29:43 +0000[diff] [blame]1428 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1429 APInt NewBits = ~InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1430
1431 // If none of the top bits are demanded, convert this into an any_extend.
1432 if (NewBits == 0)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1433 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1434 Op.getValueType(),
1435 Op.getOperand(0)));
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1436
1437 // Since some of the sign extended bits are demanded, we know that the sign
1438 // bit is demanded.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1439 APInt InDemandedBits = InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1440 InDemandedBits |= InSignBit;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1441 InDemandedBits.trunc(InBits);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1442
1443 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1444 KnownOne, TLO, Depth+1))
1445 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1446 KnownZero.zext(BitWidth);
1447 KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1448
1449 // If the sign bit is known zero, convert this to a zero extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1450 if (KnownZero.intersects(InSignBit))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1451 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1452 Op.getValueType(),
1453 Op.getOperand(0)));
1454
1455 // If the sign bit is known one, the top bits match.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1456 if (KnownOne.intersects(InSignBit)) {
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1457 KnownOne |= NewBits;
1458 KnownZero &= ~NewBits;
1459 } else { // Otherwise, top bits aren't known.
1460 KnownOne &= ~NewBits;
1461 KnownZero &= ~NewBits;
1462 }
1463 break;
1464 }
1465 case ISD::ANY_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1466 unsigned OperandBitWidth =
1467 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1468 APInt InMask = NewMask;
1469 InMask.trunc(OperandBitWidth);
1470 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1471 KnownZero, KnownOne, TLO, Depth+1))
1472 return true;
1473 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1474 KnownZero.zext(BitWidth);
1475 KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1476 break;
1477 }
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1478 case ISD::TRUNCATE: {
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1479 // Simplify the input, using demanded bit information, and compute the known
1480 // zero/one bits live out.
Dan Gohman042919c2010-03-01 17:59:21 +0000[diff] [blame]1481 unsigned OperandBitWidth =
1482 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1483 APInt TruncMask = NewMask;
Dan Gohman042919c2010-03-01 17:59:21 +0000[diff] [blame]1484 TruncMask.zext(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1485 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1486 KnownZero, KnownOne, TLO, Depth+1))
1487 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1488 KnownZero.trunc(BitWidth);
1489 KnownOne.trunc(BitWidth);
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1490
1491 // If the input is only used by this truncate, see if we can shrink it based
1492 // on the known demanded bits.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1493 if (Op.getOperand(0).getNode()->hasOneUse()) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1494 SDValue In = Op.getOperand(0);
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1495 switch (In.getOpcode()) {
1496 default: break;
1497 case ISD::SRL:
1498 // Shrink SRL by a constant if none of the high bits shifted in are
1499 // demanded.
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1500 if (TLO.LegalTypes() &&
1501 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1502 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1503 // undesirable.
1504 break;
1505 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1506 if (!ShAmt)
1507 break;
1508 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1509 OperandBitWidth - BitWidth);
1510 HighBits = HighBits.lshr(ShAmt->getZExtValue());
1511 HighBits.trunc(BitWidth);
1512
1513 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1514 // None of the shifted in bits are needed. Add a truncate of the
1515 // shift input, then shift it.
1516 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1517 Op.getValueType(),
1518 In.getOperand(0));
1519 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1520 Op.getValueType(),
1521 NewTrunc,
1522 In.getOperand(1)));
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1523 }
1524 break;
1525 }
1526 }
1527
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1528 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1529 break;
1530 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1531 case ISD::AssertZext: {
Dan Gohman400f75c2010-06-03 20:21:33 +0000[diff] [blame]1532 // Demand all the bits of the input that are demanded in the output.
1533 // The low bits are obvious; the high bits are demanded because we're
1534 // asserting that they're zero here.
1535 if (SimplifyDemandedBits(Op.getOperand(0), NewMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1536 KnownZero, KnownOne, TLO, Depth+1))
1537 return true;
1538 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman400f75c2010-06-03 20:21:33 +0000[diff] [blame]1539
1540 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1541 APInt InMask = APInt::getLowBitsSet(BitWidth,
1542 VT.getSizeInBits());
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1543 KnownZero |= ~InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1544 break;
1545 }
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1546 case ISD::BIT_CONVERT:
1547#if 0
1548 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1549 // is demanded, turn this into a FGETSIGN.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1550 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]1551 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1552 !MVT::isVector(Op.getOperand(0).getValueType())) {
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1553 // Only do this xform if FGETSIGN is valid or if before legalize.
1554 if (!TLO.AfterLegalize ||
1555 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1556 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1557 // place. We expect the SHL to be eliminated by other optimizations.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1558 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1559 Op.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1560 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1561 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1562 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1563 Sign, ShAmt));
1564 }
1565 }
1566#endif
1567 break;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1568 case ISD::ADD:
1569 case ISD::MUL:
1570 case ISD::SUB: {
1571 // Add, Sub, and Mul don't demand any bits in positions beyond that
1572 // of the highest bit demanded of them.
1573 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1574 BitWidth - NewMask.countLeadingZeros());
1575 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1576 KnownOne2, TLO, Depth+1))
1577 return true;
1578 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1579 KnownOne2, TLO, Depth+1))
1580 return true;
1581 // See if the operation should be performed at a smaller bit width.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1582 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1583 return true;
1584 }
1585 // FALL THROUGH
Dan Gohman54eed372008-05-06 00:53:29 +0000[diff] [blame]1586 default:
Chris Lattner1482b5f2006-04-02 06:15:09 +0000[diff] [blame]1587 // Just use ComputeMaskedBits to compute output bits.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1588 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
Chris Lattnera6bc5a42006-02-27 01:00:42 +0000[diff] [blame]1589 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1590 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1591
1592 // If we know the value of all of the demanded bits, return this as a
1593 // constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1594 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1595 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1596
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1597 return false;
1598}
1599
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1600/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1601/// in Mask are known to be either zero or one and return them in the
1602/// KnownZero/KnownOne bitsets.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1603void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]1604 const APInt &Mask,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]1605 APInt &KnownZero,
1606 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1607 const SelectionDAG &DAG,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1608 unsigned Depth) const {
Chris Lattner1b5232a2006-04-02 06:19:46 +0000[diff] [blame]1609 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1610 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1611 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1612 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1613 "Should use MaskedValueIsZero if you don't know whether Op"
1614 " is a target node!");
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]1615 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]1616}
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]1617
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1618/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1619/// targets that want to expose additional information about sign bits to the
1620/// DAG Combiner.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1621unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1622 unsigned Depth) const {
1623 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1624 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1625 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1626 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1627 "Should use ComputeNumSignBits if you don't know whether Op"
1628 " is a target node!");
1629 return 1;
1630}
1631
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1632/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1633/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1634/// determine which bit is set.
1635///
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1636static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1637 // A left-shift of a constant one will have exactly one bit set, because
1638 // shifting the bit off the end is undefined.
1639 if (Val.getOpcode() == ISD::SHL)
1640 if (ConstantSDNode *C =
1641 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1642 if (C->getAPIntValue() == 1)
1643 return true;
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1644
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1645 // Similarly, a right-shift of a constant sign-bit will have exactly
1646 // one bit set.
1647 if (Val.getOpcode() == ISD::SRL)
1648 if (ConstantSDNode *C =
1649 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1650 if (C->getAPIntValue().isSignBit())
1651 return true;
1652
1653 // More could be done here, though the above checks are enough
1654 // to handle some common cases.
1655
1656 // Fall back to ComputeMaskedBits to catch other known cases.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1657 EVT OpVT = Val.getValueType();
Dan Gohman5b870af2010-03-02 02:14:38 +0000[diff] [blame]1658 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1659 APInt Mask = APInt::getAllOnesValue(BitWidth);
1660 APInt KnownZero, KnownOne;
1661 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1662 return (KnownZero.countPopulation() == BitWidth - 1) &&
1663 (KnownOne.countPopulation() == 1);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1664}
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1665
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1666/// SimplifySetCC - Try to simplify a setcc built with the specified operands
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1667/// and cc. If it is unable to simplify it, return a null SDValue.
1668SDValue
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1669TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1670 ISD::CondCode Cond, bool foldBooleans,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1671 DAGCombinerInfo &DCI, DebugLoc dl) const {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1672 SelectionDAG &DAG = DCI.DAG;
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1673 LLVMContext &Context = *DAG.getContext();
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1674
1675 // These setcc operations always fold.
1676 switch (Cond) {
1677 default: break;
1678 case ISD::SETFALSE:
1679 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1680 case ISD::SETTRUE:
1681 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1682 }
1683
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1684 if (isa<ConstantSDNode>(N0.getNode())) {
1685 // Ensure that the constant occurs on the RHS, and fold constant
1686 // comparisons.
1687 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1688 }
1689
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1690 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
Dan Gohman6c6cd1c2008-03-03 22:22:56 +0000[diff] [blame]1691 const APInt &C1 = N1C->getAPIntValue();
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1692
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1693 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1694 // equality comparison, then we're just comparing whether X itself is
1695 // zero.
1696 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1697 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1698 N0.getOperand(1).getOpcode() == ISD::Constant) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1699 const APInt &ShAmt
1700 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1701 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1702 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1703 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1704 // (srl (ctlz x), 5) == 0 -> X != 0
1705 // (srl (ctlz x), 5) != 1 -> X != 0
1706 Cond = ISD::SETNE;
1707 } else {
1708 // (srl (ctlz x), 5) != 0 -> X == 0
1709 // (srl (ctlz x), 5) == 1 -> X == 0
1710 Cond = ISD::SETEQ;
1711 }
1712 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1713 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1714 Zero, Cond);
1715 }
1716 }
1717
1718 // If the LHS is '(and load, const)', the RHS is 0,
1719 // the test is for equality or unsigned, and all 1 bits of the const are
1720 // in the same partial word, see if we can shorten the load.
1721 if (DCI.isBeforeLegalize() &&
1722 N0.getOpcode() == ISD::AND && C1 == 0 &&
1723 N0.getNode()->hasOneUse() &&
1724 isa<LoadSDNode>(N0.getOperand(0)) &&
1725 N0.getOperand(0).getNode()->hasOneUse() &&
1726 isa<ConstantSDNode>(N0.getOperand(1))) {
1727 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1728 APInt bestMask;
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1729 unsigned bestWidth = 0, bestOffset = 0;
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1730 if (!Lod->isVolatile() && Lod->isUnindexed()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1731 unsigned origWidth = N0.getValueType().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1732 unsigned maskWidth = origWidth;
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1733 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1734 // 8 bits, but have to be careful...
1735 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1736 origWidth = Lod->getMemoryVT().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1737 const APInt &Mask =
1738 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1739 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1740 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1741 for (unsigned offset=0; offset<origWidth/width; offset++) {
1742 if ((newMask & Mask) == Mask) {
1743 if (!TD->isLittleEndian())
1744 bestOffset = (origWidth/width - offset - 1) * (width/8);
1745 else
1746 bestOffset = (uint64_t)offset * (width/8);
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1747 bestMask = Mask.lshr(offset * (width/8) * 8);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1748 bestWidth = width;
1749 break;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1750 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1751 newMask = newMask << width;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1752 }
1753 }
1754 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1755 if (bestWidth) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1756 EVT newVT = EVT::getIntegerVT(Context, bestWidth);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1757 if (newVT.isRound()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1758 EVT PtrType = Lod->getOperand(1).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1759 SDValue Ptr = Lod->getBasePtr();
1760 if (bestOffset != 0)
1761 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1762 DAG.getConstant(bestOffset, PtrType));
1763 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1764 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1765 Lod->getSrcValue(),
1766 Lod->getSrcValueOffset() + bestOffset,
David Greene1e559442010-02-15 17:00:31 +0000[diff] [blame]1767 false, false, NewAlign);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1768 return DAG.getSetCC(dl, VT,
1769 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1770 DAG.getConstant(bestMask.trunc(bestWidth),
1771 newVT)),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1772 DAG.getConstant(0LL, newVT), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1773 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1774 }
1775 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1776
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1777 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1778 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1779 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1780
1781 // If the comparison constant has bits in the upper part, the
1782 // zero-extended value could never match.
1783 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1784 C1.getBitWidth() - InSize))) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1785 switch (Cond) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1786 case ISD::SETUGT:
1787 case ISD::SETUGE:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1788 case ISD::SETEQ: return DAG.getConstant(0, VT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1789 case ISD::SETULT:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1790 case ISD::SETULE:
1791 case ISD::SETNE: return DAG.getConstant(1, VT);
1792 case ISD::SETGT:
1793 case ISD::SETGE:
1794 // True if the sign bit of C1 is set.
1795 return DAG.getConstant(C1.isNegative(), VT);
1796 case ISD::SETLT:
1797 case ISD::SETLE:
1798 // True if the sign bit of C1 isn't set.
1799 return DAG.getConstant(C1.isNonNegative(), VT);
1800 default:
Jakob Stoklund Olesen78d12642009-07-24 18:22:59 +0000[diff] [blame]1801 break;
1802 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1803 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1804
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1805 // Otherwise, we can perform the comparison with the low bits.
1806 switch (Cond) {
1807 case ISD::SETEQ:
1808 case ISD::SETNE:
1809 case ISD::SETUGT:
1810 case ISD::SETUGE:
1811 case ISD::SETULT:
1812 case ISD::SETULE: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1813 EVT newVT = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1814 if (DCI.isBeforeLegalizeOps() ||
1815 (isOperationLegal(ISD::SETCC, newVT) &&
1816 getCondCodeAction(Cond, newVT)==Legal))
1817 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1818 DAG.getConstant(APInt(C1).trunc(InSize), newVT),
1819 Cond);
1820 break;
1821 }
1822 default:
1823 break; // todo, be more careful with signed comparisons
1824 }
1825 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1826 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1827 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1828 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1829 EVT ExtDstTy = N0.getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1830 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1831
1832 // If the extended part has any inconsistent bits, it cannot ever
1833 // compare equal. In other words, they have to be all ones or all
1834 // zeros.
1835 APInt ExtBits =
1836 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1837 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1838 return DAG.getConstant(Cond == ISD::SETNE, VT);
1839
1840 SDValue ZextOp;
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1841 EVT Op0Ty = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1842 if (Op0Ty == ExtSrcTy) {
1843 ZextOp = N0.getOperand(0);
1844 } else {
1845 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1846 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1847 DAG.getConstant(Imm, Op0Ty));
1848 }
1849 if (!DCI.isCalledByLegalizer())
1850 DCI.AddToWorklist(ZextOp.getNode());
1851 // Otherwise, make this a use of a zext.
1852 return DAG.getSetCC(dl, VT, ZextOp,
1853 DAG.getConstant(C1 & APInt::getLowBitsSet(
1854 ExtDstTyBits,
1855 ExtSrcTyBits),
1856 ExtDstTy),
1857 Cond);
1858 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1859 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1860 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1861 if (N0.getOpcode() == ISD::SETCC &&
1862 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1863 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1864 if (TrueWhenTrue)
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1865 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1866 // Invert the condition.
1867 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1868 CC = ISD::getSetCCInverse(CC,
1869 N0.getOperand(0).getValueType().isInteger());
1870 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1871 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1872
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1873 if ((N0.getOpcode() == ISD::XOR ||
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1874 (N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1875 N0.getOperand(0).getOpcode() == ISD::XOR &&
1876 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1877 isa<ConstantSDNode>(N0.getOperand(1)) &&
1878 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1879 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1880 // can only do this if the top bits are known zero.
1881 unsigned BitWidth = N0.getValueSizeInBits();
1882 if (DAG.MaskedValueIsZero(N0,
1883 APInt::getHighBitsSet(BitWidth,
1884 BitWidth-1))) {
1885 // Okay, get the un-inverted input value.
1886 SDValue Val;
1887 if (N0.getOpcode() == ISD::XOR)
1888 Val = N0.getOperand(0);
1889 else {
1890 assert(N0.getOpcode() == ISD::AND &&
1891 N0.getOperand(0).getOpcode() == ISD::XOR);
1892 // ((X^1)&1)^1 -> X & 1
1893 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1894 N0.getOperand(0).getOperand(0),
1895 N0.getOperand(1));
1896 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1897
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1898 return DAG.getSetCC(dl, VT, Val, N1,
1899 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1900 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1901 } else if (N1C->getAPIntValue() == 1 &&
1902 (VT == MVT::i1 ||
1903 getBooleanContents() == ZeroOrOneBooleanContent)) {
1904 SDValue Op0 = N0;
1905 if (Op0.getOpcode() == ISD::TRUNCATE)
1906 Op0 = Op0.getOperand(0);
1907
1908 if ((Op0.getOpcode() == ISD::XOR) &&
1909 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1910 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1911 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1912 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1913 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1914 Cond);
1915 } else if (Op0.getOpcode() == ISD::AND &&
1916 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1917 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1918 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]1919 if (Op0.getValueType().bitsGT(VT))
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1920 Op0 = DAG.getNode(ISD::AND, dl, VT,
1921 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1922 DAG.getConstant(1, VT));
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]1923 else if (Op0.getValueType().bitsLT(VT))
1924 Op0 = DAG.getNode(ISD::AND, dl, VT,
1925 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1926 DAG.getConstant(1, VT));
1927
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1928 return DAG.getSetCC(dl, VT, Op0,
1929 DAG.getConstant(0, Op0.getValueType()),
1930 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1931 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1932 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1933 }
1934
1935 APInt MinVal, MaxVal;
1936 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1937 if (ISD::isSignedIntSetCC(Cond)) {
1938 MinVal = APInt::getSignedMinValue(OperandBitSize);
1939 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1940 } else {
1941 MinVal = APInt::getMinValue(OperandBitSize);
1942 MaxVal = APInt::getMaxValue(OperandBitSize);
1943 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1944
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1945 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1946 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1947 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1948 // X >= C0 --> X > (C0-1)
1949 return DAG.getSetCC(dl, VT, N0,
1950 DAG.getConstant(C1-1, N1.getValueType()),
1951 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1952 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1953
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1954 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1955 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1956 // X <= C0 --> X < (C0+1)
1957 return DAG.getSetCC(dl, VT, N0,
1958 DAG.getConstant(C1+1, N1.getValueType()),
1959 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1960 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1961
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1962 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1963 return DAG.getConstant(0, VT); // X < MIN --> false
1964 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1965 return DAG.getConstant(1, VT); // X >= MIN --> true
1966 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1967 return DAG.getConstant(0, VT); // X > MAX --> false
1968 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1969 return DAG.getConstant(1, VT); // X <= MAX --> true
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1970
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1971 // Canonicalize setgt X, Min --> setne X, Min
1972 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1973 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1974 // Canonicalize setlt X, Max --> setne X, Max
1975 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1976 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1977
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1978 // If we have setult X, 1, turn it into seteq X, 0
1979 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1980 return DAG.getSetCC(dl, VT, N0,
1981 DAG.getConstant(MinVal, N0.getValueType()),
1982 ISD::SETEQ);
1983 // If we have setugt X, Max-1, turn it into seteq X, Max
1984 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1985 return DAG.getSetCC(dl, VT, N0,
1986 DAG.getConstant(MaxVal, N0.getValueType()),
1987 ISD::SETEQ);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1988
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1989 // If we have "setcc X, C0", check to see if we can shrink the immediate
1990 // by changing cc.
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1991
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1992 // SETUGT X, SINTMAX -> SETLT X, 0
1993 if (Cond == ISD::SETUGT &&
1994 C1 == APInt::getSignedMaxValue(OperandBitSize))
1995 return DAG.getSetCC(dl, VT, N0,
1996 DAG.getConstant(0, N1.getValueType()),
1997 ISD::SETLT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1998
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1999 // SETULT X, SINTMIN -> SETGT X, -1
2000 if (Cond == ISD::SETULT &&
2001 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2002 SDValue ConstMinusOne =
2003 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2004 N1.getValueType());
2005 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2006 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2007
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2008 // Fold bit comparisons when we can.
2009 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2010 (VT == N0.getValueType() ||
2011 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2012 N0.getOpcode() == ISD::AND)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2013 if (ConstantSDNode *AndRHS =
2014 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2015 EVT ShiftTy = DCI.isBeforeLegalize() ?
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2016 getPointerTy() : getShiftAmountTy();
2017 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2018 // Perform the xform if the AND RHS is a single bit.
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2019 if (AndRHS->getAPIntValue().isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2020 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2021 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2022 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2023 }
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2024 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2025 // (X & 8) == 8 --> (X & 8) >> 3
2026 // Perform the xform if C1 is a single bit.
2027 if (C1.isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2028 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2029 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2030 DAG.getConstant(C1.logBase2(), ShiftTy)));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2031 }
2032 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2033 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2034 }
2035
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2036 if (isa<ConstantFPSDNode>(N0.getNode())) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2037 // Constant fold or commute setcc.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2038 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2039 if (O.getNode()) return O;
2040 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2041 // If the RHS of an FP comparison is a constant, simplify it away in
2042 // some cases.
2043 if (CFP->getValueAPF().isNaN()) {
2044 // If an operand is known to be a nan, we can fold it.
2045 switch (ISD::getUnorderedFlavor(Cond)) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2046 default: llvm_unreachable("Unknown flavor!");
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2047 case 0: // Known false.
2048 return DAG.getConstant(0, VT);
2049 case 1: // Known true.
2050 return DAG.getConstant(1, VT);
Chris Lattner1c3e1e22007-12-30 21:21:10 +0000[diff] [blame]2051 case 2: // Undefined.
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]2052 return DAG.getUNDEF(VT);
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2053 }
2054 }
2055
2056 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2057 // constant if knowing that the operand is non-nan is enough. We prefer to
2058 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2059 // materialize 0.0.
2060 if (Cond == ISD::SETO || Cond == ISD::SETUO)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2061 return DAG.getSetCC(dl, VT, N0, N0, Cond);
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2062
2063 // If the condition is not legal, see if we can find an equivalent one
2064 // which is legal.
2065 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2066 // If the comparison was an awkward floating-point == or != and one of
2067 // the comparison operands is infinity or negative infinity, convert the
2068 // condition to a less-awkward <= or >=.
2069 if (CFP->getValueAPF().isInfinity()) {
2070 if (CFP->getValueAPF().isNegative()) {
2071 if (Cond == ISD::SETOEQ &&
2072 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2073 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2074 if (Cond == ISD::SETUEQ &&
2075 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2076 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2077 if (Cond == ISD::SETUNE &&
2078 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2079 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2080 if (Cond == ISD::SETONE &&
2081 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2082 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2083 } else {
2084 if (Cond == ISD::SETOEQ &&
2085 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2086 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2087 if (Cond == ISD::SETUEQ &&
2088 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2089 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2090 if (Cond == ISD::SETUNE &&
2091 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2092 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2093 if (Cond == ISD::SETONE &&
2094 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2095 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2096 }
2097 }
2098 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2099 }
2100
2101 if (N0 == N1) {
2102 // We can always fold X == X for integer setcc's.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2103 if (N0.getValueType().isInteger())
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2104 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2105 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2106 if (UOF == 2) // FP operators that are undefined on NaNs.
2107 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2108 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2109 return DAG.getConstant(UOF, VT);
2110 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2111 // if it is not already.
2112 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2113 if (NewCond != Cond)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2114 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2115 }
2116
2117 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2118 N0.getValueType().isInteger()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2119 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2120 N0.getOpcode() == ISD::XOR) {
2121 // Simplify (X+Y) == (X+Z) --> Y == Z
2122 if (N0.getOpcode() == N1.getOpcode()) {
2123 if (N0.getOperand(0) == N1.getOperand(0))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2124 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2125 if (N0.getOperand(1) == N1.getOperand(1))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2126 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2127 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2128 // If X op Y == Y op X, try other combinations.
2129 if (N0.getOperand(0) == N1.getOperand(1))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2130 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2131 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2132 if (N0.getOperand(1) == N1.getOperand(0))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2133 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2134 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2135 }
2136 }
2137
2138 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2139 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2140 // Turn (X+C1) == C2 --> X == C2-C1
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2141 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2142 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2143 DAG.getConstant(RHSC->getAPIntValue()-
2144 LHSR->getAPIntValue(),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2145 N0.getValueType()), Cond);
2146 }
2147
2148 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2149 if (N0.getOpcode() == ISD::XOR)
2150 // If we know that all of the inverted bits are zero, don't bother
2151 // performing the inversion.
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2152 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2153 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2154 DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2155 DAG.getConstant(LHSR->getAPIntValue() ^
2156 RHSC->getAPIntValue(),
2157 N0.getValueType()),
2158 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2159 }
2160
2161 // Turn (C1-X) == C2 --> X == C1-C2
2162 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2163 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2164 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2165 DAG.getSetCC(dl, VT, N0.getOperand(1),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2166 DAG.getConstant(SUBC->getAPIntValue() -
2167 RHSC->getAPIntValue(),
2168 N0.getValueType()),
2169 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2170 }
2171 }
2172 }
2173
2174 // Simplify (X+Z) == X --> Z == 0
2175 if (N0.getOperand(0) == N1)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2176 return DAG.getSetCC(dl, VT, N0.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2177 DAG.getConstant(0, N0.getValueType()), Cond);
2178 if (N0.getOperand(1) == N1) {
2179 if (DAG.isCommutativeBinOp(N0.getOpcode()))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2180 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2181 DAG.getConstant(0, N0.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2182 else if (N0.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2183 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2184 // (Z-X) == X --> Z == X<<1
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2185 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2186 N1,
2187 DAG.getConstant(1, getShiftAmountTy()));
2188 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2189 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2190 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2191 }
2192 }
2193 }
2194
2195 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2196 N1.getOpcode() == ISD::XOR) {
2197 // Simplify X == (X+Z) --> Z == 0
2198 if (N1.getOperand(0) == N0) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2199 return DAG.getSetCC(dl, VT, N1.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2200 DAG.getConstant(0, N1.getValueType()), Cond);
2201 } else if (N1.getOperand(1) == N0) {
2202 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2203 return DAG.getSetCC(dl, VT, N1.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2204 DAG.getConstant(0, N1.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2205 } else if (N1.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2206 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2207 // X == (Z-X) --> X<<1 == Z
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2208 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2209 DAG.getConstant(1, getShiftAmountTy()));
2210 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2211 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2212 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2213 }
2214 }
2215 }
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2216
Dan Gohman2c65c3d2009-01-29 16:18:12 +0000[diff] [blame]2217 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2218 // Note that where y is variable and is known to have at most
2219 // one bit set (for example, if it is z&1) we cannot do this;
2220 // the expressions are not equivalent when y==0.
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2221 if (N0.getOpcode() == ISD::AND)
2222 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2223 if (ValueHasExactlyOneBitSet(N1, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2224 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2225 SDValue Zero = DAG.getConstant(0, N1.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2226 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2227 }
2228 }
2229 if (N1.getOpcode() == ISD::AND)
2230 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2231 if (ValueHasExactlyOneBitSet(N0, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2232 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2233 SDValue Zero = DAG.getConstant(0, N0.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2234 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2235 }
2236 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2237 }
2238
2239 // Fold away ALL boolean setcc's.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2240 SDValue Temp;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2241 if (N0.getValueType() == MVT::i1 && foldBooleans) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2242 switch (Cond) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2243 default: llvm_unreachable("Unknown integer setcc!");
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2244 case ISD::SETEQ: // X == Y -> ~(X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2245 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2246 N0 = DAG.getNOT(dl, Temp, MVT::i1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2247 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2248 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2249 break;
2250 case ISD::SETNE: // X != Y --> (X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2251 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2252 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2253 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2254 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2255 Temp = DAG.getNOT(dl, N0, MVT::i1);
2256 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2257 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2258 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2259 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2260 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2261 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2262 Temp = DAG.getNOT(dl, N1, MVT::i1);
2263 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2264 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2265 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2266 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2267 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2268 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2269 Temp = DAG.getNOT(dl, N0, MVT::i1);
2270 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2271 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2272 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2273 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2274 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2275 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2276 Temp = DAG.getNOT(dl, N1, MVT::i1);
2277 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2278 break;
2279 }
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2280 if (VT != MVT::i1) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2281 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2282 DCI.AddToWorklist(N0.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2283 // FIXME: If running after legalize, we probably can't do this.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2284 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2285 }
2286 return N0;
2287 }
2288
2289 // Could not fold it.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2290 return SDValue();
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2291}
2292
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2293/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2294/// node is a GlobalAddress + offset.
Dan Gohman46510a72010-04-15 01:51:59 +0000[diff] [blame]2295bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2296 int64_t &Offset) const {
2297 if (isa<GlobalAddressSDNode>(N)) {
Dan Gohman9ea3f562008-06-09 22:05:52 +0000[diff] [blame]2298 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2299 GA = GASD->getGlobal();
2300 Offset += GASD->getOffset();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2301 return true;
2302 }
2303
2304 if (N->getOpcode() == ISD::ADD) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2305 SDValue N1 = N->getOperand(0);
2306 SDValue N2 = N->getOperand(1);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2307 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2308 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2309 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2310 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2311 return true;
2312 }
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2313 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2314 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2315 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2316 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2317 return true;
2318 }
2319 }
2320 }
2321 return false;
2322}
2323
2324
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2325SDValue TargetLowering::
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2326PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2327 // Default implementation: no optimization.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2328 return SDValue();
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2329}
2330
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2331//===----------------------------------------------------------------------===//
2332// Inline Assembler Implementation Methods
2333//===----------------------------------------------------------------------===//
2334
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2335
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2336TargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2337TargetLowering::getConstraintType(const std::string &Constraint) const {
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2338 // FIXME: lots more standard ones to handle.
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2339 if (Constraint.size() == 1) {
2340 switch (Constraint[0]) {
2341 default: break;
2342 case 'r': return C_RegisterClass;
2343 case 'm': // memory
2344 case 'o': // offsetable
2345 case 'V': // not offsetable
2346 return C_Memory;
2347 case 'i': // Simple Integer or Relocatable Constant
2348 case 'n': // Simple Integer
2349 case 's': // Relocatable Constant
Chris Lattnerc13dd1c2007-03-25 04:35:41 +0000[diff] [blame]2350 case 'X': // Allow ANY value.
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2351 case 'I': // Target registers.
2352 case 'J':
2353 case 'K':
2354 case 'L':
2355 case 'M':
2356 case 'N':
2357 case 'O':
2358 case 'P':
2359 return C_Other;
2360 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2361 }
Chris Lattner065421f2007-03-25 02:18:14 +0000[diff] [blame]2362
2363 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2364 Constraint[Constraint.size()-1] == '}')
2365 return C_Register;
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2366 return C_Unknown;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2367}
2368
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2369/// LowerXConstraint - try to replace an X constraint, which matches anything,
2370/// with another that has more specific requirements based on the type of the
2371/// corresponding operand.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2372const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2373 if (ConstraintVT.isInteger())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2374 return "r";
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2375 if (ConstraintVT.isFloatingPoint())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2376 return "f"; // works for many targets
2377 return 0;
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2378}
2379
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2380/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2381/// vector. If it is invalid, don't add anything to Ops.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2382void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2383 char ConstraintLetter,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2384 std::vector<SDValue> &Ops,
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2385 SelectionDAG &DAG) const {
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2386 switch (ConstraintLetter) {
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2387 default: break;
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2388 case 'X': // Allows any operand; labels (basic block) use this.
2389 if (Op.getOpcode() == ISD::BasicBlock) {
2390 Ops.push_back(Op);
2391 return;
2392 }
2393 // fall through
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2394 case 'i': // Simple Integer or Relocatable Constant
2395 case 'n': // Simple Integer
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2396 case 's': { // Relocatable Constant
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2397 // These operands are interested in values of the form (GV+C), where C may
2398 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2399 // is possible and fine if either GV or C are missing.
2400 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2401 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2402
2403 // If we have "(add GV, C)", pull out GV/C
2404 if (Op.getOpcode() == ISD::ADD) {
2405 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2406 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2407 if (C == 0 || GA == 0) {
2408 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2409 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2410 }
2411 if (C == 0 || GA == 0)
2412 C = 0, GA = 0;
2413 }
2414
2415 // If we find a valid operand, map to the TargetXXX version so that the
2416 // value itself doesn't get selected.
2417 if (GA) { // Either &GV or &GV+C
2418 if (ConstraintLetter != 'n') {
2419 int64_t Offs = GA->getOffset();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2420 if (C) Offs += C->getZExtValue();
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2421 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2422 Op.getValueType(), Offs));
2423 return;
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2424 }
2425 }
2426 if (C) { // just C, no GV.
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2427 // Simple constants are not allowed for 's'.
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2428 if (ConstraintLetter != 's') {
Dale Johannesen78e3e522009-02-12 20:58:09 +0000[diff] [blame]2429 // gcc prints these as sign extended. Sign extend value to 64 bits
2430 // now; without this it would get ZExt'd later in
2431 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2432 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2433 MVT::i64));
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2434 return;
2435 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2436 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2437 break;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2438 }
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2439 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2440}
2441
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2442std::vector<unsigned> TargetLowering::
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2443getRegClassForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2444 EVT VT) const {
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2445 return std::vector<unsigned>();
2446}
2447
2448
2449std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
Chris Lattner4217ca8dc2006-02-21 23:11:00 +0000[diff] [blame]2450getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2451 EVT VT) const {
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2452 if (Constraint[0] != '{')
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2453 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
Chris Lattnera55079a2006-02-01 01:29:47 +0000[diff] [blame]2454 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2455
2456 // Remove the braces from around the name.
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2457 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2458
2459 // Figure out which register class contains this reg.
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]2460 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2461 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2462 E = RI->regclass_end(); RCI != E; ++RCI) {
2463 const TargetRegisterClass *RC = *RCI;
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]2464
Dan Gohmanf451cb82010-02-10 16:03:48 +0000[diff] [blame]2465 // If none of the value types for this register class are valid, we
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]2466 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2467 bool isLegal = false;
2468 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2469 I != E; ++I) {
2470 if (isTypeLegal(*I)) {
2471 isLegal = true;
2472 break;
2473 }
2474 }
2475
2476 if (!isLegal) continue;
2477
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2478 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2479 I != E; ++I) {
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2480 if (RegName.equals_lower(RI->getName(*I)))
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2481 return std::make_pair(*I, RC);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2482 }
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2483 }
Chris Lattnera55079a2006-02-01 01:29:47 +0000[diff] [blame]2484
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2485 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2486}
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]2487
2488//===----------------------------------------------------------------------===//
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2489// Constraint Selection.
2490
Chris Lattner6bdcda32008-10-17 16:47:46 +0000[diff] [blame]2491/// isMatchingInputConstraint - Return true of this is an input operand that is
2492/// a matching constraint like "4".
2493bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]2494 assert(!ConstraintCode.empty() && "No known constraint!");
2495 return isdigit(ConstraintCode[0]);
2496}
2497
2498/// getMatchedOperand - If this is an input matching constraint, this method
2499/// returns the output operand it matches.
2500unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2501 assert(!ConstraintCode.empty() && "No known constraint!");
2502 return atoi(ConstraintCode.c_str());
2503}
2504
2505
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2506/// getConstraintGenerality - Return an integer indicating how general CT
2507/// is.
2508static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2509 switch (CT) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2510 default: llvm_unreachable("Unknown constraint type!");
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2511 case TargetLowering::C_Other:
2512 case TargetLowering::C_Unknown:
2513 return 0;
2514 case TargetLowering::C_Register:
2515 return 1;
2516 case TargetLowering::C_RegisterClass:
2517 return 2;
2518 case TargetLowering::C_Memory:
2519 return 3;
2520 }
2521}
2522
2523/// ChooseConstraint - If there are multiple different constraints that we
2524/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
Chris Lattner24e1a9d2008-04-27 01:49:46 +0000[diff] [blame]2525/// This is somewhat tricky: constraints fall into four classes:
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2526/// Other -> immediates and magic values
2527/// Register -> one specific register
2528/// RegisterClass -> a group of regs
2529/// Memory -> memory
2530/// Ideally, we would pick the most specific constraint possible: if we have
2531/// something that fits into a register, we would pick it. The problem here
2532/// is that if we have something that could either be in a register or in
2533/// memory that use of the register could cause selection of *other*
2534/// operands to fail: they might only succeed if we pick memory. Because of
2535/// this the heuristic we use is:
2536///
2537/// 1) If there is an 'other' constraint, and if the operand is valid for
2538/// that constraint, use it. This makes us take advantage of 'i'
2539/// constraints when available.
2540/// 2) Otherwise, pick the most general constraint present. This prefers
2541/// 'm' over 'r', for example.
2542///
2543static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]2544 const TargetLowering &TLI,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2545 SDValue Op, SelectionDAG *DAG) {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2546 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2547 unsigned BestIdx = 0;
2548 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2549 int BestGenerality = -1;
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]2550
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2551 // Loop over the options, keeping track of the most general one.
2552 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2553 TargetLowering::ConstraintType CType =
2554 TLI.getConstraintType(OpInfo.Codes[i]);
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]2555
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2556 // If this is an 'other' constraint, see if the operand is valid for it.
2557 // For example, on X86 we might have an 'rI' constraint. If the operand
2558 // is an integer in the range [0..31] we want to use I (saving a load
2559 // of a register), otherwise we must use 'r'.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2560 if (CType == TargetLowering::C_Other && Op.getNode()) {
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2561 assert(OpInfo.Codes[i].size() == 1 &&
2562 "Unhandled multi-letter 'other' constraint");
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2563 std::vector<SDValue> ResultOps;
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]2564 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0],
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2565 ResultOps, *DAG);
2566 if (!ResultOps.empty()) {
2567 BestType = CType;
2568 BestIdx = i;
2569 break;
2570 }
2571 }
2572
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]2573 // Things with matching constraints can only be registers, per gcc
2574 // documentation. This mainly affects "g" constraints.
2575 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2576 continue;
2577
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2578 // This constraint letter is more general than the previous one, use it.
2579 int Generality = getConstraintGenerality(CType);
2580 if (Generality > BestGenerality) {
2581 BestType = CType;
2582 BestIdx = i;
2583 BestGenerality = Generality;
2584 }
2585 }
2586
2587 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2588 OpInfo.ConstraintType = BestType;
2589}
2590
2591/// ComputeConstraintToUse - Determines the constraint code and constraint
2592/// type to use for the specific AsmOperandInfo, setting
2593/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2594void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2595 SDValue Op,
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2596 SelectionDAG *DAG) const {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2597 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2598
2599 // Single-letter constraints ('r') are very common.
2600 if (OpInfo.Codes.size() == 1) {
2601 OpInfo.ConstraintCode = OpInfo.Codes[0];
2602 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2603 } else {
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]2604 ChooseConstraint(OpInfo, *this, Op, DAG);
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2605 }
2606
2607 // 'X' matches anything.
2608 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2609 // Labels and constants are handled elsewhere ('X' is the only thing
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]2610 // that matches labels). For Functions, the type here is the type of
Dale Johannesen5339c552009-07-20 23:27:39 +0000[diff] [blame]2611 // the result, which is not what we want to look at; leave them alone.
2612 Value *v = OpInfo.CallOperandVal;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]2613 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2614 OpInfo.CallOperandVal = v;
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2615 return;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]2616 }
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2617
2618 // Otherwise, try to resolve it to something we know about by looking at
2619 // the actual operand type.
2620 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2621 OpInfo.ConstraintCode = Repl;
2622 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2623 }
2624 }
2625}
2626
2627//===----------------------------------------------------------------------===//
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]2628// Loop Strength Reduction hooks
2629//===----------------------------------------------------------------------===//
2630
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]2631/// isLegalAddressingMode - Return true if the addressing mode represented
2632/// by AM is legal for this target, for a load/store of the specified type.
2633bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2634 const Type *Ty) const {
2635 // The default implementation of this implements a conservative RISCy, r+r and
2636 // r+i addr mode.
2637
2638 // Allows a sign-extended 16-bit immediate field.
2639 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2640 return false;
2641
2642 // No global is ever allowed as a base.
2643 if (AM.BaseGV)
2644 return false;
2645
2646 // Only support r+r,
2647 switch (AM.Scale) {
2648 case 0: // "r+i" or just "i", depending on HasBaseReg.
2649 break;
2650 case 1:
2651 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2652 return false;
2653 // Otherwise we have r+r or r+i.
2654 break;
2655 case 2:
2656 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2657 return false;
2658 // Allow 2*r as r+r.
2659 break;
2660 }
2661
2662 return true;
2663}
2664
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2665/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2666/// return a DAG expression to select that will generate the same value by
2667/// multiplying by a magic number. See:
2668/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2669SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2670 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2671 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2672 DebugLoc dl= N->getDebugLoc();
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2673
2674 // Check to see if we can do this.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2675 // FIXME: We should be more aggressive here.
2676 if (!isTypeLegal(VT))
2677 return SDValue();
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2678
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2679 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
Jay Foad4e5ea552009-04-30 10:15:35 +0000[diff] [blame]2680 APInt::ms magics = d.magic();
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2681
2682 // Multiply the numerator (operand 0) by the magic value
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2683 // FIXME: We should support doing a MUL in a wider type
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2684 SDValue Q;
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]2685 if (isOperationLegalOrCustom(ISD::MULHS, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2686 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2687 DAG.getConstant(magics.m, VT));
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]2688 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2689 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2690 N->getOperand(0),
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2691 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2692 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2693 return SDValue(); // No mulhs or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2694 // If d > 0 and m < 0, add the numerator
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2695 if (d.isStrictlyPositive() && magics.m.isNegative()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2696 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2697 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2698 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2699 }
2700 // If d < 0 and m > 0, subtract the numerator.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2701 if (d.isNegative() && magics.m.isStrictlyPositive()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2702 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2703 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2704 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2705 }
2706 // Shift right algebraic if shift value is nonzero
2707 if (magics.s > 0) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2708 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2709 DAG.getConstant(magics.s, getShiftAmountTy()));
2710 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2711 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2712 }
2713 // Extract the sign bit and add it to the quotient
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2714 SDValue T =
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2715 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2716 getShiftAmountTy()));
2717 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2718 Created->push_back(T.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2719 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2720}
2721
2722/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2723/// return a DAG expression to select that will generate the same value by
2724/// multiplying by a magic number. See:
2725/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2726SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2727 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2728 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2729 DebugLoc dl = N->getDebugLoc();
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2730
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2731 // Check to see if we can do this.
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2732 // FIXME: We should be more aggressive here.
2733 if (!isTypeLegal(VT))
2734 return SDValue();
2735
2736 // FIXME: We should use a narrower constant when the upper
2737 // bits are known to be zero.
2738 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
Jay Foad4e5ea552009-04-30 10:15:35 +0000[diff] [blame]2739 APInt::mu magics = N1C->getAPIntValue().magicu();
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2740
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2741 // Multiply the numerator (operand 0) by the magic value
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2742 // FIXME: We should support doing a MUL in a wider type
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2743 SDValue Q;
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]2744 if (isOperationLegalOrCustom(ISD::MULHU, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2745 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2746 DAG.getConstant(magics.m, VT));
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]2747 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2748 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2749 N->getOperand(0),
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2750 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2751 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2752 return SDValue(); // No mulhu or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2753 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2754 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2755
2756 if (magics.a == 0) {
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2757 assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2758 "We shouldn't generate an undefined shift!");
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2759 return DAG.getNode(ISD::SRL, dl, VT, Q,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2760 DAG.getConstant(magics.s, getShiftAmountTy()));
2761 } else {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2762 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2763 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2764 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2765 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2766 DAG.getConstant(1, getShiftAmountTy()));
2767 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2768 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2769 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2770 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2771 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2772 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2773 DAG.getConstant(magics.s-1, getShiftAmountTy()));
2774 }
2775}