| Bill Schmidt | 34a9d4b | 2012-11-27 17:35:46 +0000 | [diff] [blame] | 1 | ; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s |
| Bill Schmidt | 53b0b0e | 2013-02-21 17:12:27 +0000 | [diff] [blame] | 2 | ; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s |
| Bill Schmidt | 34a9d4b | 2012-11-27 17:35:46 +0000 | [diff] [blame] | 3 | |
| Bill Schmidt | 53b0b0e | 2013-02-21 17:12:27 +0000 | [diff] [blame] | 4 | ; Test correct code generation for medium and large code model |
| Bill Schmidt | 34a9d4b | 2012-11-27 17:35:46 +0000 | [diff] [blame] | 5 | ; for loading the address of a jump table from the TOC. |
| 6 | |
| 7 | target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" |
| 8 | target triple = "powerpc64-unknown-linux-gnu" |
| 9 | |
| 10 | define signext i32 @test_jump_table(i32 signext %i) nounwind { |
| 11 | entry: |
| 12 | %i.addr = alloca i32, align 4 |
| 13 | store i32 %i, i32* %i.addr, align 4 |
| 14 | %0 = load i32* %i.addr, align 4 |
| 15 | switch i32 %0, label %sw.default [ |
| 16 | i32 3, label %sw.bb |
| 17 | i32 4, label %sw.bb1 |
| 18 | i32 5, label %sw.bb2 |
| 19 | i32 6, label %sw.bb3 |
| 20 | ] |
| 21 | |
| 22 | sw.default: ; preds = %entry |
| 23 | br label %sw.epilog |
| 24 | |
| 25 | sw.bb: ; preds = %entry |
| 26 | %1 = load i32* %i.addr, align 4 |
| 27 | %mul = mul nsw i32 %1, 7 |
| 28 | store i32 %mul, i32* %i.addr, align 4 |
| 29 | br label %sw.bb1 |
| 30 | |
| 31 | sw.bb1: ; preds = %entry, %sw.bb |
| 32 | %2 = load i32* %i.addr, align 4 |
| 33 | %dec = add nsw i32 %2, -1 |
| 34 | store i32 %dec, i32* %i.addr, align 4 |
| 35 | br label %sw.bb2 |
| 36 | |
| 37 | sw.bb2: ; preds = %entry, %sw.bb1 |
| 38 | %3 = load i32* %i.addr, align 4 |
| 39 | %add = add nsw i32 %3, 3 |
| 40 | store i32 %add, i32* %i.addr, align 4 |
| 41 | br label %sw.bb3 |
| 42 | |
| 43 | sw.bb3: ; preds = %entry, %sw.bb2 |
| 44 | %4 = load i32* %i.addr, align 4 |
| 45 | %shl = shl i32 %4, 1 |
| 46 | store i32 %shl, i32* %i.addr, align 4 |
| 47 | br label %sw.epilog |
| 48 | |
| 49 | sw.epilog: ; preds = %sw.bb3, %sw.default |
| 50 | %5 = load i32* %i.addr, align 4 |
| 51 | ret i32 %5 |
| 52 | } |
| 53 | |
| 54 | ; CHECK: test_jump_table: |
| 55 | ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha |
| 56 | ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) |
| 57 | ; CHECK: ldx {{[0-9]+}}, {{[0-9]+}}, [[REG2]] |
| 58 | ; CHECK: .section .toc |
| 59 | ; CHECK: .LC[[TOCNUM]]: |
| 60 | ; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}} |