Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 5b51fd5b550a9589f95e677fca801cea565e8d9f / . / test / CodeGen / PowerPC / crsave.ll
blob: a9b4b3607830821fc1f7362d139a4ea871517394 [file] [log] [blame]
Ulrich Weigand33efedc2013-07-03 17:59:07 +0000[diff] [blame]1; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC32
2; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC64
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]3
4declare void @foo()
5
Rafael Espindola0225d5a2013-05-16 03:48:50 +0000[diff] [blame]6define i32 @test_cr2() nounwind uwtable {
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]7entry:
8 %ret = alloca i32, align 4
9 %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmp 2,$2,$1\0A\09mfcr $0", "=r,r,r,r,r,~{cr2}"(i32 1, i32 2, i32 3, i32 0) nounwind
10 store i32 %0, i32* %ret, align 4
11 call void @foo()
12 %1 = load i32* %ret, align 4
13 ret i32 %1
14}
15
Bill Schmidtded53bf2013-05-14 16:08:32 +0000[diff] [blame]16; PPC32: stw 31, -4(1)
17; PPC32: stwu 1, -32(1)
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]18; PPC32: mfcr 12
Bill Schmidtded53bf2013-05-14 16:08:32 +0000[diff] [blame]19; PPC32-NEXT: stw 12, 24(31)
20; PPC32: lwz 12, 24(31)
Ulrich Weigand33efedc2013-07-03 17:59:07 +0000[diff] [blame]21; PPC32-NEXT: mtocrf 32, 12
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]22
Rafael Espindola0225d5a2013-05-16 03:48:50 +0000[diff] [blame]23; PPC64: .cfi_startproc
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]24; PPC64: mfcr 12
Hal Finkelfb6fe0a2013-04-15 02:07:05 +0000[diff] [blame]25; PPC64: stw 12, 8(1)
26; PPC64: stdu 1, -[[AMT:[0-9]+]](1)
Rafael Espindola0225d5a2013-05-16 03:48:50 +0000[diff] [blame]27; PPC64: .cfi_def_cfa_offset 128
28; PPC64: .cfi_offset lr, 16
29; PPC64: .cfi_offset cr2, 8
Hal Finkelfb6fe0a2013-04-15 02:07:05 +0000[diff] [blame]30; PPC64: addi 1, 1, [[AMT]]
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]31; PPC64: lwz 12, 8(1)
Ulrich Weigand33efedc2013-07-03 17:59:07 +0000[diff] [blame]32; PPC64: mtocrf 32, 12
Rafael Espindola0225d5a2013-05-16 03:48:50 +0000[diff] [blame]33; PPC64: .cfi_endproc
Hal Finkelb99c9952013-04-13 08:09:20 +0000[diff] [blame]34
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]35define i32 @test_cr234() nounwind {
36entry:
37 %ret = alloca i32, align 4
38 %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmp 2,$2,$1\0A\09cmp 3,$2,$2\0A\09cmp 4,$2,$3\0A\09mfcr $0", "=r,r,r,r,r,~{cr2},~{cr3},~{cr4}"(i32 1, i32 2, i32 3, i32 0) nounwind
39 store i32 %0, i32* %ret, align 4
40 call void @foo()
41 %1 = load i32* %ret, align 4
42 ret i32 %1
43}
44
Bill Schmidtded53bf2013-05-14 16:08:32 +0000[diff] [blame]45; PPC32: stw 31, -4(1)
46; PPC32: stwu 1, -32(1)
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]47; PPC32: mfcr 12
Bill Schmidtded53bf2013-05-14 16:08:32 +0000[diff] [blame]48; PPC32-NEXT: stw 12, 24(31)
49; PPC32: lwz 12, 24(31)
Ulrich Weigand33efedc2013-07-03 17:59:07 +0000[diff] [blame]50; PPC32-NEXT: mtocrf 32, 12
51; PPC32-NEXT: mtocrf 16, 12
52; PPC32-NEXT: mtocrf 8, 12
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]53
54; PPC64: mfcr 12
Hal Finkelfb6fe0a2013-04-15 02:07:05 +0000[diff] [blame]55; PPC64: stw 12, 8(1)
56; PPC64: stdu 1, -[[AMT:[0-9]+]](1)
57; PPC64: addi 1, 1, [[AMT]]
Roman Divacky9d760ae2012-09-12 14:47:47 +0000[diff] [blame]58; PPC64: lwz 12, 8(1)
Ulrich Weigand33efedc2013-07-03 17:59:07 +0000[diff] [blame]59; PPC64: mtocrf 32, 12
60; PPC64: mtocrf 16, 12
61; PPC64: mtocrf 8, 12
Hal Finkelb99c9952013-04-13 08:09:20 +0000[diff] [blame]62