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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 5b51fd5b550a9589f95e677fca801cea565e8d9f / . / test / CodeGen / PowerPC / i32-to-float.ll
blob: 2707d0352de1aa059b67a368cfb879b392b586df [file] [log] [blame]
Hal Finkel9ad0f492013-03-31 01:58:02 +0000[diff] [blame]1; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s
Hal Finkel46479192013-04-01 17:52:07 +0000[diff] [blame]2; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr6 | FileCheck -check-prefix=CHECK-PWR6 %s
Hal Finkel8049ab12013-03-31 10:12:51 +0000[diff] [blame]3; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck -check-prefix=CHECK-A2 %s
Hal Finkel9ad0f492013-03-31 01:58:02 +0000[diff] [blame]4target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
5target triple = "powerpc64-unknown-linux-gnu"
6
7define float @foo(i32 %a) nounwind {
8entry:
9 %x = sitofp i32 %a to float
10 ret float %x
11
12; CHECK: @foo
13; CHECK: extsw [[REG:[0-9]+]], 3
14; CHECK: std [[REG]],
15; CHECK: lfd [[REG2:[0-9]+]],
16; CHECK: fcfid [[REG3:[0-9]+]], [[REG2]]
17; CHECK: frsp 1, [[REG3]]
18; CHECK: blr
Hal Finkel8049ab12013-03-31 10:12:51 +0000[diff] [blame]19
Hal Finkel46479192013-04-01 17:52:07 +0000[diff] [blame]20; CHECK-PWR6: @foo
21; CHECK-PWR6: stw 3,
22; CHECK-PWR6: lfiwax [[REG:[0-9]+]],
23; CHECK-PWR6: fcfid [[REG2:[0-9]+]], [[REG]]
24; CHECK-PWR6: frsp 1, [[REG2]]
25; CHECK-PWR6: blr
26
Hal Finkel8049ab12013-03-31 10:12:51 +0000[diff] [blame]27; CHECK-A2: @foo
28; CHECK-A2: stw 3,
29; CHECK-A2: lfiwax [[REG:[0-9]+]],
Hal Finkel46479192013-04-01 17:52:07 +0000[diff] [blame]30; CHECK-A2: fcfids 1, [[REG]]
Hal Finkel8049ab12013-03-31 10:12:51 +0000[diff] [blame]31; CHECK-A2: blr
Hal Finkel9ad0f492013-03-31 01:58:02 +0000[diff] [blame]32}
33
34define double @goo(i32 %a) nounwind {
35entry:
36 %x = sitofp i32 %a to double
37 ret double %x
38
39; CHECK: @goo
40; CHECK: extsw [[REG:[0-9]+]], 3
41; CHECK: std [[REG]],
42; CHECK: lfd [[REG2:[0-9]+]],
43; CHECK: fcfid 1, [[REG2]]
44; CHECK: blr
Hal Finkel8049ab12013-03-31 10:12:51 +0000[diff] [blame]45
Hal Finkel46479192013-04-01 17:52:07 +0000[diff] [blame]46; CHECK-PWR6: @goo
47; CHECK-PWR6: stw 3,
48; CHECK-PWR6: lfiwax [[REG:[0-9]+]],
49; CHECK-PWR6: fcfid 1, [[REG]]
50; CHECK-PWR6: blr
51
Hal Finkel8049ab12013-03-31 10:12:51 +0000[diff] [blame]52; CHECK-A2: @goo
53; CHECK-A2: stw 3,
54; CHECK-A2: lfiwax [[REG:[0-9]+]],
55; CHECK-A2: fcfid 1, [[REG]]
56; CHECK-A2: blr
Hal Finkel9ad0f492013-03-31 01:58:02 +0000[diff] [blame]57}
58
Hal Finkel46479192013-04-01 17:52:07 +0000[diff] [blame]59define float @foou(i32 %a) nounwind {
60entry:
61 %x = uitofp i32 %a to float
62 ret float %x
63
64; CHECK-A2: @foou
65; CHECK-A2: stw 3,
66; CHECK-A2: lfiwzx [[REG:[0-9]+]],
67; CHECK-A2: fcfidus 1, [[REG]]
68; CHECK-A2: blr
69}
70
71define double @goou(i32 %a) nounwind {
72entry:
73 %x = uitofp i32 %a to double
74 ret double %x
75
76; CHECK-A2: @goou
77; CHECK-A2: stw 3,
78; CHECK-A2: lfiwzx [[REG:[0-9]+]],
79; CHECK-A2: fcfidu 1, [[REG]]
80; CHECK-A2: blr
81}
82