| Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame^] | 1 | ; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t |
| 2 | ; RUN: grep {vpadal\\.s8} %t | count 2 |
| 3 | ; RUN: grep {vpadal\\.s16} %t | count 2 |
| 4 | ; RUN: grep {vpadal\\.s32} %t | count 2 |
| 5 | ; RUN: grep {vpadal\\.u8} %t | count 2 |
| 6 | ; RUN: grep {vpadal\\.u16} %t | count 2 |
| 7 | ; RUN: grep {vpadal\\.u32} %t | count 2 |
| 8 | |
| 9 | define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind { |
| 10 | %tmp1 = load <4 x i16>* %A |
| 11 | %tmp2 = load <8 x i8>* %B |
| 12 | %tmp3 = call <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2) |
| 13 | ret <4 x i16> %tmp3 |
| 14 | } |
| 15 | |
| 16 | define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind { |
| 17 | %tmp1 = load <2 x i32>* %A |
| 18 | %tmp2 = load <4 x i16>* %B |
| 19 | %tmp3 = call <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2) |
| 20 | ret <2 x i32> %tmp3 |
| 21 | } |
| 22 | |
| 23 | define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind { |
| 24 | %tmp1 = load <1 x i64>* %A |
| 25 | %tmp2 = load <2 x i32>* %B |
| 26 | %tmp3 = call <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2) |
| 27 | ret <1 x i64> %tmp3 |
| 28 | } |
| 29 | |
| 30 | define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind { |
| 31 | %tmp1 = load <4 x i16>* %A |
| 32 | %tmp2 = load <8 x i8>* %B |
| 33 | %tmp3 = call <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2) |
| 34 | ret <4 x i16> %tmp3 |
| 35 | } |
| 36 | |
| 37 | define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind { |
| 38 | %tmp1 = load <2 x i32>* %A |
| 39 | %tmp2 = load <4 x i16>* %B |
| 40 | %tmp3 = call <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2) |
| 41 | ret <2 x i32> %tmp3 |
| 42 | } |
| 43 | |
| 44 | define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind { |
| 45 | %tmp1 = load <1 x i64>* %A |
| 46 | %tmp2 = load <2 x i32>* %B |
| 47 | %tmp3 = call <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2) |
| 48 | ret <1 x i64> %tmp3 |
| 49 | } |
| 50 | |
| 51 | define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind { |
| 52 | %tmp1 = load <8 x i16>* %A |
| 53 | %tmp2 = load <16 x i8>* %B |
| 54 | %tmp3 = call <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2) |
| 55 | ret <8 x i16> %tmp3 |
| 56 | } |
| 57 | |
| 58 | define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind { |
| 59 | %tmp1 = load <4 x i32>* %A |
| 60 | %tmp2 = load <8 x i16>* %B |
| 61 | %tmp3 = call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2) |
| 62 | ret <4 x i32> %tmp3 |
| 63 | } |
| 64 | |
| 65 | define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind { |
| 66 | %tmp1 = load <2 x i64>* %A |
| 67 | %tmp2 = load <4 x i32>* %B |
| 68 | %tmp3 = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2) |
| 69 | ret <2 x i64> %tmp3 |
| 70 | } |
| 71 | |
| 72 | define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind { |
| 73 | %tmp1 = load <8 x i16>* %A |
| 74 | %tmp2 = load <16 x i8>* %B |
| 75 | %tmp3 = call <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2) |
| 76 | ret <8 x i16> %tmp3 |
| 77 | } |
| 78 | |
| 79 | define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind { |
| 80 | %tmp1 = load <4 x i32>* %A |
| 81 | %tmp2 = load <8 x i16>* %B |
| 82 | %tmp3 = call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2) |
| 83 | ret <4 x i32> %tmp3 |
| 84 | } |
| 85 | |
| 86 | define <2 x i64> @vpadalQu32(<2 x i64>* %A, <4 x i32>* %B) nounwind { |
| 87 | %tmp1 = load <2 x i64>* %A |
| 88 | %tmp2 = load <4 x i32>* %B |
| 89 | %tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2) |
| 90 | ret <2 x i64> %tmp3 |
| 91 | } |
| 92 | |
| 93 | declare <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16>, <8 x i8>) nounwind readnone |
| 94 | declare <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32>, <4 x i16>) nounwind readnone |
| 95 | declare <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone |
| 96 | |
| 97 | declare <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16>, <8 x i8>) nounwind readnone |
| 98 | declare <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32>, <4 x i16>) nounwind readnone |
| 99 | declare <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone |
| 100 | |
| 101 | declare <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16>, <16 x i8>) nounwind readnone |
| 102 | declare <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone |
| 103 | declare <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone |
| 104 | |
| 105 | declare <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16>, <16 x i8>) nounwind readnone |
| 106 | declare <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone |
| 107 | declare <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone |