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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 5bafff36c798608a189c517d37527e4a38863071 / . / test / CodeGen / ARM / vshiftins.ll
blob: cb7cbb89ecdb3542fd52b175cbd0302c1e86dd99 [file] [log] [blame]
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame^]1; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
2; RUN: grep {vsli\\.8} %t | count 2
3; RUN: grep {vsli\\.16} %t | count 2
4; RUN: grep {vsli\\.32} %t | count 2
5; RUN: grep {vsli\\.64} %t | count 2
6; RUN: grep {vsri\\.8} %t | count 2
7; RUN: grep {vsri\\.16} %t | count 2
8; RUN: grep {vsri\\.32} %t | count 2
9; RUN: grep {vsri\\.64} %t | count 2
10
11define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
12 %tmp1 = load <8 x i8>* %A
13 %tmp2 = load <8 x i8>* %B
14 %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
15 ret <8 x i8> %tmp3
16}
17
18define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
19 %tmp1 = load <4 x i16>* %A
20 %tmp2 = load <4 x i16>* %B
21 %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
22 ret <4 x i16> %tmp3
23}
24
25define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
26 %tmp1 = load <2 x i32>* %A
27 %tmp2 = load <2 x i32>* %B
28 %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 31, i32 31 >)
29 ret <2 x i32> %tmp3
30}
31
32define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
33 %tmp1 = load <1 x i64>* %A
34 %tmp2 = load <1 x i64>* %B
35 %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 63 >)
36 ret <1 x i64> %tmp3
37}
38
39define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
40 %tmp1 = load <16 x i8>* %A
41 %tmp2 = load <16 x i8>* %B
42 %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
43 ret <16 x i8> %tmp3
44}
45
46define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
47 %tmp1 = load <8 x i16>* %A
48 %tmp2 = load <8 x i16>* %B
49 %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
50 ret <8 x i16> %tmp3
51}
52
53define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
54 %tmp1 = load <4 x i32>* %A
55 %tmp2 = load <4 x i32>* %B
56 %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
57 ret <4 x i32> %tmp3
58}
59
60define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
61 %tmp1 = load <2 x i64>* %A
62 %tmp2 = load <2 x i64>* %B
63 %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 63, i64 63 >)
64 ret <2 x i64> %tmp3
65}
66
67define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
68 %tmp1 = load <8 x i8>* %A
69 %tmp2 = load <8 x i8>* %B
70 %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
71 ret <8 x i8> %tmp3
72}
73
74define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
75 %tmp1 = load <4 x i16>* %A
76 %tmp2 = load <4 x i16>* %B
77 %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
78 ret <4 x i16> %tmp3
79}
80
81define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
82 %tmp1 = load <2 x i32>* %A
83 %tmp2 = load <2 x i32>* %B
84 %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
85 ret <2 x i32> %tmp3
86}
87
88define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
89 %tmp1 = load <1 x i64>* %A
90 %tmp2 = load <1 x i64>* %B
91 %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 -64 >)
92 ret <1 x i64> %tmp3
93}
94
95define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
96 %tmp1 = load <16 x i8>* %A
97 %tmp2 = load <16 x i8>* %B
98 %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
99 ret <16 x i8> %tmp3
100}
101
102define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
103 %tmp1 = load <8 x i16>* %A
104 %tmp2 = load <8 x i16>* %B
105 %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
106 ret <8 x i16> %tmp3
107}
108
109define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
110 %tmp1 = load <4 x i32>* %A
111 %tmp2 = load <4 x i32>* %B
112 %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
113 ret <4 x i32> %tmp3
114}
115
116define <2 x i64> @vsriQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
117 %tmp1 = load <2 x i64>* %A
118 %tmp2 = load <2 x i64>* %B
119 %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
120 ret <2 x i64> %tmp3
121}
122
123declare <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
124declare <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone
125declare <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone
126declare <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64>, <1 x i64>, <1 x i64>) nounwind readnone
127
128declare <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
129declare <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
130declare <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
131declare <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone