Bill Wendling | 2695d8e | 2010-10-15 21:50:45 +0000 | [diff] [blame] | 1 | //===- ARMInstrVFP.td - VFP support for ARM ----------------*- tablegen -*-===// |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Jim Grosbach | e5d20f9 | 2008-09-11 21:41:29 +0000 | [diff] [blame] | 10 | // This file describes the ARM VFP instruction set. |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Bill Wendling | 2695d8e | 2010-10-15 21:50:45 +0000 | [diff] [blame] | 14 | def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; |
| 15 | def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; |
| 16 | def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>; |
| 17 | def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>, |
| 18 | SDTCisSameAs<1, 2>]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 19 | |
Bill Wendling | 2695d8e | 2010-10-15 21:50:45 +0000 | [diff] [blame] | 20 | def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>; |
| 21 | def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>; |
| 22 | def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>; |
| 23 | def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>; |
Chris Lattner | 036609b | 2010-12-23 18:28:41 +0000 | [diff] [blame] | 24 | def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>; |
| 25 | def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>; |
| 26 | def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>; |
Bill Wendling | 2695d8e | 2010-10-15 21:50:45 +0000 | [diff] [blame] | 27 | def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 28 | |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 29 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 30 | //===----------------------------------------------------------------------===// |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 31 | // Operand Definitions. |
| 32 | // |
| 33 | |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 34 | def vfp_f32imm : Operand<f32>, |
| 35 | PatLeaf<(f32 fpimm), [{ |
| 36 | return ARM::getVFPf32Imm(N->getValueAPF()) != -1; |
| 37 | }]> { |
| 38 | let PrintMethod = "printVFPf32ImmOperand"; |
| 39 | } |
| 40 | |
| 41 | def vfp_f64imm : Operand<f64>, |
| 42 | PatLeaf<(f64 fpimm), [{ |
| 43 | return ARM::getVFPf64Imm(N->getValueAPF()) != -1; |
| 44 | }]> { |
| 45 | let PrintMethod = "printVFPf64ImmOperand"; |
| 46 | } |
| 47 | |
| 48 | |
| 49 | //===----------------------------------------------------------------------===// |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 50 | // Load / store Instructions. |
| 51 | // |
| 52 | |
Dan Gohman | bc9d98b | 2010-02-27 23:47:46 +0000 | [diff] [blame] | 53 | let canFoldAsLoad = 1, isReMaterializable = 1 in { |
Bill Wendling | 92b5a2e | 2010-11-03 01:49:29 +0000 | [diff] [blame] | 54 | |
Bill Wendling | 7d31a16 | 2010-10-20 22:44:54 +0000 | [diff] [blame] | 55 | def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), |
| 56 | IIC_fpLoad64, "vldr", ".64\t$Dd, $addr", |
Bill Wendling | 2f46f1f | 2010-11-04 00:59:42 +0000 | [diff] [blame] | 57 | [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 58 | |
Bill Wendling | 92b5a2e | 2010-11-03 01:49:29 +0000 | [diff] [blame] | 59 | def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), |
| 60 | IIC_fpLoad32, "vldr", ".32\t$Sd, $addr", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 61 | [(set SPR:$Sd, (load addrmode5:$addr))]> { |
| 62 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 63 | // pipelines. |
| 64 | let D = VFPNeonDomain; |
| 65 | } |
Bill Wendling | 92b5a2e | 2010-11-03 01:49:29 +0000 | [diff] [blame] | 66 | |
| 67 | } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in' |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 68 | |
Bill Wendling | 2f46f1f | 2010-11-04 00:59:42 +0000 | [diff] [blame] | 69 | def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr), |
| 70 | IIC_fpStore64, "vstr", ".64\t$Dd, $addr", |
| 71 | [(store (f64 DPR:$Dd), addrmode5:$addr)]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 72 | |
Bill Wendling | 2f46f1f | 2010-11-04 00:59:42 +0000 | [diff] [blame] | 73 | def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr), |
| 74 | IIC_fpStore32, "vstr", ".32\t$Sd, $addr", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 75 | [(store SPR:$Sd, addrmode5:$addr)]> { |
| 76 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 77 | // pipelines. |
| 78 | let D = VFPNeonDomain; |
| 79 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 80 | |
| 81 | //===----------------------------------------------------------------------===// |
| 82 | // Load / store multiple Instructions. |
| 83 | // |
| 84 | |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 85 | multiclass vfp_ldst_mult<string asm, bit L_bit, |
| 86 | InstrItinClass itin, InstrItinClass itin_upd> { |
| 87 | // Double Precision |
| 88 | def DIA : |
Bill Wendling | 0f63075 | 2010-11-17 04:32:08 +0000 | [diff] [blame] | 89 | AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 90 | IndexModeNone, itin, |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 91 | !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 92 | let Inst{24-23} = 0b01; // Increment After |
| 93 | let Inst{21} = 0; // No writeback |
| 94 | let Inst{20} = L_bit; |
| 95 | } |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 96 | def DIA_UPD : |
Bill Wendling | 0f63075 | 2010-11-17 04:32:08 +0000 | [diff] [blame] | 97 | AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 98 | IndexModeUpd, itin_upd, |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 99 | !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 100 | let Inst{24-23} = 0b01; // Increment After |
| 101 | let Inst{21} = 1; // Writeback |
| 102 | let Inst{20} = L_bit; |
| 103 | } |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 104 | def DDB : |
Bill Wendling | 0f63075 | 2010-11-17 04:32:08 +0000 | [diff] [blame] | 105 | AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 106 | IndexModeNone, itin, |
| 107 | !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> { |
| 108 | let Inst{24-23} = 0b10; // Decrement Before |
| 109 | let Inst{21} = 0; // No writeback |
| 110 | let Inst{20} = L_bit; |
| 111 | } |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 112 | def DDB_UPD : |
Bill Wendling | 0f63075 | 2010-11-17 04:32:08 +0000 | [diff] [blame] | 113 | AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 114 | IndexModeUpd, itin_upd, |
| 115 | !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { |
| 116 | let Inst{24-23} = 0b10; // Decrement Before |
| 117 | let Inst{21} = 1; // Writeback |
| 118 | let Inst{20} = L_bit; |
| 119 | } |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 120 | |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 121 | // Single Precision |
| 122 | def SIA : |
Bill Wendling | 0f63075 | 2010-11-17 04:32:08 +0000 | [diff] [blame] | 123 | AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops), |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 124 | IndexModeNone, itin, |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 125 | !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 126 | let Inst{24-23} = 0b01; // Increment After |
| 127 | let Inst{21} = 0; // No writeback |
| 128 | let Inst{20} = L_bit; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 129 | |
| 130 | // Some single precision VFP instructions may be executed on both NEON and |
| 131 | // VFP pipelines. |
| 132 | let D = VFPNeonDomain; |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 133 | } |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 134 | def SIA_UPD : |
Bill Wendling | 0f63075 | 2010-11-17 04:32:08 +0000 | [diff] [blame] | 135 | AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops), |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 136 | IndexModeUpd, itin_upd, |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 137 | !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 138 | let Inst{24-23} = 0b01; // Increment After |
| 139 | let Inst{21} = 1; // Writeback |
| 140 | let Inst{20} = L_bit; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 141 | |
| 142 | // Some single precision VFP instructions may be executed on both NEON and |
| 143 | // VFP pipelines. |
| 144 | let D = VFPNeonDomain; |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 145 | } |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 146 | def SDB : |
Bill Wendling | 0f63075 | 2010-11-17 04:32:08 +0000 | [diff] [blame] | 147 | AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops), |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 148 | IndexModeNone, itin, |
| 149 | !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> { |
| 150 | let Inst{24-23} = 0b10; // Decrement Before |
| 151 | let Inst{21} = 0; // No writeback |
| 152 | let Inst{20} = L_bit; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 153 | |
| 154 | // Some single precision VFP instructions may be executed on both NEON and |
| 155 | // VFP pipelines. |
| 156 | let D = VFPNeonDomain; |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 157 | } |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 158 | def SDB_UPD : |
Bill Wendling | 0f63075 | 2010-11-17 04:32:08 +0000 | [diff] [blame] | 159 | AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops), |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 160 | IndexModeUpd, itin_upd, |
| 161 | !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { |
| 162 | let Inst{24-23} = 0b10; // Decrement Before |
| 163 | let Inst{21} = 1; // Writeback |
| 164 | let Inst{20} = L_bit; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 165 | |
| 166 | // Some single precision VFP instructions may be executed on both NEON and |
| 167 | // VFP pipelines. |
| 168 | let D = VFPNeonDomain; |
Bill Wendling | 6c470b8 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 169 | } |
| 170 | } |
| 171 | |
Bill Wendling | ddc918b | 2010-11-13 10:57:02 +0000 | [diff] [blame] | 172 | let neverHasSideEffects = 1 in { |
| 173 | |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 174 | let mayLoad = 1, hasExtraDefRegAllocReq = 1 in |
| 175 | defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>; |
Bill Wendling | ddc918b | 2010-11-13 10:57:02 +0000 | [diff] [blame] | 176 | |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 177 | let mayStore = 1, hasExtraSrcRegAllocReq = 1 in |
| 178 | defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpLoad_m, IIC_fpLoad_mu>; |
Bill Wendling | ddc918b | 2010-11-13 10:57:02 +0000 | [diff] [blame] | 179 | |
| 180 | } // neverHasSideEffects |
| 181 | |
Bill Wendling | 73c57e1 | 2010-11-16 02:00:24 +0000 | [diff] [blame] | 182 | def : MnemonicAlias<"vldm", "vldmia">; |
| 183 | def : MnemonicAlias<"vstm", "vstmia">; |
| 184 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 185 | // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores |
| 186 | |
| 187 | //===----------------------------------------------------------------------===// |
| 188 | // FP Binary Operations. |
| 189 | // |
| 190 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 191 | def VADDD : ADbI<0b11100, 0b11, 0, 0, |
| 192 | (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), |
| 193 | IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm", |
| 194 | [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>; |
Bill Wendling | 174777b | 2010-10-12 22:08:41 +0000 | [diff] [blame] | 195 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 196 | def VADDS : ASbIn<0b11100, 0b11, 0, 0, |
| 197 | (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), |
| 198 | IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 199 | [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> { |
| 200 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 201 | // pipelines. |
| 202 | let D = VFPNeonDomain; |
| 203 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 204 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 205 | def VSUBD : ADbI<0b11100, 0b11, 1, 0, |
| 206 | (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), |
| 207 | IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm", |
| 208 | [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>; |
Jim Grosbach | 499e886 | 2010-10-12 21:22:40 +0000 | [diff] [blame] | 209 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 210 | def VSUBS : ASbIn<0b11100, 0b11, 1, 0, |
| 211 | (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), |
| 212 | IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 213 | [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> { |
| 214 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 215 | // pipelines. |
| 216 | let D = VFPNeonDomain; |
| 217 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 218 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 219 | def VDIVD : ADbI<0b11101, 0b00, 0, 0, |
| 220 | (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), |
| 221 | IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm", |
| 222 | [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 223 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 224 | def VDIVS : ASbI<0b11101, 0b00, 0, 0, |
| 225 | (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), |
| 226 | IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm", |
| 227 | [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 228 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 229 | def VMULD : ADbI<0b11100, 0b10, 0, 0, |
| 230 | (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), |
| 231 | IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm", |
| 232 | [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 233 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 234 | def VMULS : ASbIn<0b11100, 0b10, 0, 0, |
| 235 | (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), |
| 236 | IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 237 | [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> { |
| 238 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 239 | // pipelines. |
| 240 | let D = VFPNeonDomain; |
| 241 | } |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 242 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 243 | def VNMULD : ADbI<0b11100, 0b10, 1, 0, |
| 244 | (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), |
| 245 | IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm", |
| 246 | [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 247 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 248 | def VNMULS : ASbI<0b11100, 0b10, 1, 0, |
| 249 | (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), |
| 250 | IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 251 | [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> { |
| 252 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 253 | // pipelines. |
| 254 | let D = VFPNeonDomain; |
| 255 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 256 | |
Chris Lattner | 7293912 | 2007-05-03 00:32:00 +0000 | [diff] [blame] | 257 | // Match reassociated forms only if not sign dependent rounding. |
Chris Lattner | d10a53d | 2010-03-08 18:51:21 +0000 | [diff] [blame] | 258 | def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)), |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 259 | (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>; |
Chris Lattner | 7293912 | 2007-05-03 00:32:00 +0000 | [diff] [blame] | 260 | def : Pat<(fmul (fneg SPR:$a), SPR:$b), |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 261 | (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>; |
Chris Lattner | 7293912 | 2007-05-03 00:32:00 +0000 | [diff] [blame] | 262 | |
Bill Wendling | dd3bc11 | 2010-10-12 22:55:35 +0000 | [diff] [blame] | 263 | // These are encoded as unary instructions. |
| 264 | let Defs = [FPSCR] in { |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 265 | def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, |
| 266 | (outs), (ins DPR:$Dd, DPR:$Dm), |
| 267 | IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", |
| 268 | [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 269 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 270 | def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0, |
| 271 | (outs), (ins SPR:$Sd, SPR:$Sm), |
| 272 | IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 273 | [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> { |
| 274 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 275 | // pipelines. |
| 276 | let D = VFPNeonDomain; |
| 277 | } |
Bill Wendling | dd3bc11 | 2010-10-12 22:55:35 +0000 | [diff] [blame] | 278 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 279 | // FIXME: Verify encoding after integrated assembler is working. |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 280 | def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, |
| 281 | (outs), (ins DPR:$Dd, DPR:$Dm), |
| 282 | IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", |
| 283 | [/* For disassembly only; pattern left blank */]>; |
Bill Wendling | dd3bc11 | 2010-10-12 22:55:35 +0000 | [diff] [blame] | 284 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 285 | def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, |
| 286 | (outs), (ins SPR:$Sd, SPR:$Sm), |
| 287 | IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 288 | [/* For disassembly only; pattern left blank */]> { |
| 289 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 290 | // pipelines. |
| 291 | let D = VFPNeonDomain; |
Bill Wendling | dd3bc11 | 2010-10-12 22:55:35 +0000 | [diff] [blame] | 292 | } |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 293 | } // Defs = [FPSCR] |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 294 | |
| 295 | //===----------------------------------------------------------------------===// |
| 296 | // FP Unary Operations. |
| 297 | // |
| 298 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 299 | def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, |
| 300 | (outs DPR:$Dd), (ins DPR:$Dm), |
| 301 | IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm", |
| 302 | [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 303 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 304 | def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0, |
| 305 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 306 | IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 307 | [(set SPR:$Sd, (fabs SPR:$Sm))]> { |
| 308 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 309 | // pipelines. |
| 310 | let D = VFPNeonDomain; |
| 311 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 312 | |
Evan Cheng | 91449a8 | 2009-07-20 02:12:31 +0000 | [diff] [blame] | 313 | let Defs = [FPSCR] in { |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 314 | def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, |
| 315 | (outs), (ins DPR:$Dd), |
| 316 | IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", |
| 317 | [(arm_cmpfp0 (f64 DPR:$Dd))]> { |
| 318 | let Inst{3-0} = 0b0000; |
| 319 | let Inst{5} = 0; |
Bill Wendling | 1fc6d88 | 2010-10-13 00:38:07 +0000 | [diff] [blame] | 320 | } |
| 321 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 322 | def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0, |
| 323 | (outs), (ins SPR:$Sd), |
| 324 | IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", |
| 325 | [(arm_cmpfp0 SPR:$Sd)]> { |
| 326 | let Inst{3-0} = 0b0000; |
| 327 | let Inst{5} = 0; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 328 | |
| 329 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 330 | // pipelines. |
| 331 | let D = VFPNeonDomain; |
Bill Wendling | 1fc6d88 | 2010-10-13 00:38:07 +0000 | [diff] [blame] | 332 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 333 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 334 | // FIXME: Verify encoding after integrated assembler is working. |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 335 | def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, |
| 336 | (outs), (ins DPR:$Dd), |
| 337 | IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", |
| 338 | [/* For disassembly only; pattern left blank */]> { |
| 339 | let Inst{3-0} = 0b0000; |
| 340 | let Inst{5} = 0; |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 341 | } |
Johnny Chen | 7edd8e3 | 2010-02-08 19:41:48 +0000 | [diff] [blame] | 342 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 343 | def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, |
| 344 | (outs), (ins SPR:$Sd), |
| 345 | IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", |
| 346 | [/* For disassembly only; pattern left blank */]> { |
| 347 | let Inst{3-0} = 0b0000; |
| 348 | let Inst{5} = 0; |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 349 | |
| 350 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 351 | // pipelines. |
| 352 | let D = VFPNeonDomain; |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 353 | } |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 354 | } // Defs = [FPSCR] |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 355 | |
Bill Wendling | 54908dd | 2010-10-13 00:56:35 +0000 | [diff] [blame] | 356 | def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0, |
| 357 | (outs DPR:$Dd), (ins SPR:$Sm), |
| 358 | IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm", |
| 359 | [(set DPR:$Dd, (fextend SPR:$Sm))]> { |
| 360 | // Instruction operands. |
| 361 | bits<5> Dd; |
| 362 | bits<5> Sm; |
| 363 | |
| 364 | // Encode instruction operands. |
| 365 | let Inst{3-0} = Sm{4-1}; |
| 366 | let Inst{5} = Sm{0}; |
| 367 | let Inst{15-12} = Dd{3-0}; |
| 368 | let Inst{22} = Dd{4}; |
| 369 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 370 | |
Evan Cheng | 96581d3 | 2008-11-11 02:11:05 +0000 | [diff] [blame] | 371 | // Special case encoding: bits 11-8 is 0b1011. |
Bill Wendling | 54908dd | 2010-10-13 00:56:35 +0000 | [diff] [blame] | 372 | def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm, |
| 373 | IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm", |
| 374 | [(set SPR:$Sd, (fround DPR:$Dm))]> { |
| 375 | // Instruction operands. |
| 376 | bits<5> Sd; |
| 377 | bits<5> Dm; |
| 378 | |
| 379 | // Encode instruction operands. |
| 380 | let Inst{3-0} = Dm{3-0}; |
| 381 | let Inst{5} = Dm{4}; |
| 382 | let Inst{15-12} = Sd{4-1}; |
| 383 | let Inst{22} = Sd{0}; |
| 384 | |
Evan Cheng | 96581d3 | 2008-11-11 02:11:05 +0000 | [diff] [blame] | 385 | let Inst{27-23} = 0b11101; |
| 386 | let Inst{21-16} = 0b110111; |
| 387 | let Inst{11-8} = 0b1011; |
Johnny Chen | 69a8c7f | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 388 | let Inst{7-6} = 0b11; |
| 389 | let Inst{4} = 0; |
Evan Cheng | 96581d3 | 2008-11-11 02:11:05 +0000 | [diff] [blame] | 390 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 391 | |
Johnny Chen | 2d658df | 2010-02-09 17:21:56 +0000 | [diff] [blame] | 392 | // Between half-precision and single-precision. For disassembly only. |
| 393 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 394 | // FIXME: Verify encoding after integrated assembler is working. |
Jim Grosbach | 18f30e6 | 2010-06-02 21:53:11 +0000 | [diff] [blame] | 395 | def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$dst), (ins SPR:$a), |
Anton Korobeynikov | c492e09 | 2010-04-07 18:19:46 +0000 | [diff] [blame] | 396 | /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$dst, $a", |
Anton Korobeynikov | f0d5007 | 2010-03-18 22:35:37 +0000 | [diff] [blame] | 397 | [/* For disassembly only; pattern left blank */]>; |
| 398 | |
Bob Wilson | 76a312b | 2010-03-19 22:51:32 +0000 | [diff] [blame] | 399 | def : ARMPat<(f32_to_f16 SPR:$a), |
| 400 | (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>; |
Johnny Chen | 2d658df | 2010-02-09 17:21:56 +0000 | [diff] [blame] | 401 | |
Jim Grosbach | 18f30e6 | 2010-06-02 21:53:11 +0000 | [diff] [blame] | 402 | def VCVTBHS: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$dst), (ins SPR:$a), |
Anton Korobeynikov | c492e09 | 2010-04-07 18:19:46 +0000 | [diff] [blame] | 403 | /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$dst, $a", |
Anton Korobeynikov | f0d5007 | 2010-03-18 22:35:37 +0000 | [diff] [blame] | 404 | [/* For disassembly only; pattern left blank */]>; |
| 405 | |
Bob Wilson | 76a312b | 2010-03-19 22:51:32 +0000 | [diff] [blame] | 406 | def : ARMPat<(f16_to_f32 GPR:$a), |
| 407 | (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>; |
Johnny Chen | 2d658df | 2010-02-09 17:21:56 +0000 | [diff] [blame] | 408 | |
Jim Grosbach | 18f30e6 | 2010-06-02 21:53:11 +0000 | [diff] [blame] | 409 | def VCVTTSH: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$dst), (ins SPR:$a), |
Anton Korobeynikov | c492e09 | 2010-04-07 18:19:46 +0000 | [diff] [blame] | 410 | /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$dst, $a", |
Johnny Chen | 2d658df | 2010-02-09 17:21:56 +0000 | [diff] [blame] | 411 | [/* For disassembly only; pattern left blank */]>; |
| 412 | |
Jim Grosbach | 18f30e6 | 2010-06-02 21:53:11 +0000 | [diff] [blame] | 413 | def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$dst), (ins SPR:$a), |
Anton Korobeynikov | c492e09 | 2010-04-07 18:19:46 +0000 | [diff] [blame] | 414 | /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$dst, $a", |
Johnny Chen | 2d658df | 2010-02-09 17:21:56 +0000 | [diff] [blame] | 415 | [/* For disassembly only; pattern left blank */]>; |
| 416 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 417 | def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, |
| 418 | (outs DPR:$Dd), (ins DPR:$Dm), |
| 419 | IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", |
| 420 | [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 421 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 422 | def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0, |
| 423 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 424 | IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 425 | [(set SPR:$Sd, (fneg SPR:$Sm))]> { |
| 426 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 427 | // pipelines. |
| 428 | let D = VFPNeonDomain; |
| 429 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 430 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 431 | def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, |
| 432 | (outs DPR:$Dd), (ins DPR:$Dm), |
| 433 | IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm", |
| 434 | [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 435 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 436 | def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, |
| 437 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 438 | IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", |
| 439 | [(set SPR:$Sd, (fsqrt SPR:$Sm))]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 440 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 441 | let neverHasSideEffects = 1 in { |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 442 | def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0, |
| 443 | (outs DPR:$Dd), (ins DPR:$Dm), |
| 444 | IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>; |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 445 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 446 | def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0, |
| 447 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 448 | IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>; |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 449 | } // neverHasSideEffects |
| 450 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 451 | //===----------------------------------------------------------------------===// |
| 452 | // FP <-> GPR Copies. Int <-> FP Conversions. |
| 453 | // |
| 454 | |
Bill Wendling | 7d31a16 | 2010-10-20 22:44:54 +0000 | [diff] [blame] | 455 | def VMOVRS : AVConv2I<0b11100001, 0b1010, |
| 456 | (outs GPR:$Rt), (ins SPR:$Sn), |
| 457 | IIC_fpMOVSI, "vmov", "\t$Rt, $Sn", |
| 458 | [(set GPR:$Rt, (bitconvert SPR:$Sn))]> { |
| 459 | // Instruction operands. |
| 460 | bits<4> Rt; |
| 461 | bits<5> Sn; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 462 | |
Bill Wendling | 7d31a16 | 2010-10-20 22:44:54 +0000 | [diff] [blame] | 463 | // Encode instruction operands. |
| 464 | let Inst{19-16} = Sn{4-1}; |
| 465 | let Inst{7} = Sn{0}; |
| 466 | let Inst{15-12} = Rt; |
| 467 | |
| 468 | let Inst{6-5} = 0b00; |
| 469 | let Inst{3-0} = 0b0000; |
| 470 | } |
| 471 | |
| 472 | def VMOVSR : AVConv4I<0b11100000, 0b1010, |
| 473 | (outs SPR:$Sn), (ins GPR:$Rt), |
| 474 | IIC_fpMOVIS, "vmov", "\t$Sn, $Rt", |
| 475 | [(set SPR:$Sn, (bitconvert GPR:$Rt))]> { |
| 476 | // Instruction operands. |
| 477 | bits<5> Sn; |
| 478 | bits<4> Rt; |
| 479 | |
| 480 | // Encode instruction operands. |
| 481 | let Inst{19-16} = Sn{4-1}; |
| 482 | let Inst{7} = Sn{0}; |
| 483 | let Inst{15-12} = Rt; |
| 484 | |
| 485 | let Inst{6-5} = 0b00; |
| 486 | let Inst{3-0} = 0b0000; |
| 487 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 488 | |
Evan Cheng | 020cc1b | 2010-05-13 00:16:46 +0000 | [diff] [blame] | 489 | let neverHasSideEffects = 1 in { |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 490 | def VMOVRRD : AVConv3I<0b11000101, 0b1011, |
Bill Wendling | 01aabda | 2010-10-20 23:37:40 +0000 | [diff] [blame] | 491 | (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm), |
| 492 | IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm", |
Johnny Chen | 7acca67 | 2010-02-05 18:04:58 +0000 | [diff] [blame] | 493 | [/* FIXME: Can't write pattern for multiple result instr*/]> { |
Bill Wendling | 01aabda | 2010-10-20 23:37:40 +0000 | [diff] [blame] | 494 | // Instruction operands. |
| 495 | bits<5> Dm; |
| 496 | bits<4> Rt; |
| 497 | bits<4> Rt2; |
| 498 | |
| 499 | // Encode instruction operands. |
| 500 | let Inst{3-0} = Dm{3-0}; |
| 501 | let Inst{5} = Dm{4}; |
| 502 | let Inst{15-12} = Rt; |
| 503 | let Inst{19-16} = Rt2; |
| 504 | |
Johnny Chen | 7acca67 | 2010-02-05 18:04:58 +0000 | [diff] [blame] | 505 | let Inst{7-6} = 0b00; |
| 506 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 507 | |
Johnny Chen | 23401d6 | 2010-02-08 17:26:09 +0000 | [diff] [blame] | 508 | def VMOVRRS : AVConv3I<0b11000101, 0b1010, |
| 509 | (outs GPR:$wb, GPR:$dst2), (ins SPR:$src1, SPR:$src2), |
Anton Korobeynikov | a31c6fb | 2010-04-07 18:20:02 +0000 | [diff] [blame] | 510 | IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2", |
Johnny Chen | 23401d6 | 2010-02-08 17:26:09 +0000 | [diff] [blame] | 511 | [/* For disassembly only; pattern left blank */]> { |
| 512 | let Inst{7-6} = 0b00; |
| 513 | } |
Evan Cheng | 020cc1b | 2010-05-13 00:16:46 +0000 | [diff] [blame] | 514 | } // neverHasSideEffects |
Johnny Chen | 23401d6 | 2010-02-08 17:26:09 +0000 | [diff] [blame] | 515 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 516 | // FMDHR: GPR -> SPR |
| 517 | // FMDLR: GPR -> SPR |
| 518 | |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 519 | def VMOVDRR : AVConv5I<0b11000100, 0b1011, |
Bill Wendling | 01aabda | 2010-10-20 23:37:40 +0000 | [diff] [blame] | 520 | (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2), |
| 521 | IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2", |
| 522 | [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> { |
| 523 | // Instruction operands. |
| 524 | bits<5> Dm; |
| 525 | bits<4> Rt; |
| 526 | bits<4> Rt2; |
| 527 | |
| 528 | // Encode instruction operands. |
| 529 | let Inst{3-0} = Dm{3-0}; |
| 530 | let Inst{5} = Dm{4}; |
| 531 | let Inst{15-12} = Rt; |
| 532 | let Inst{19-16} = Rt2; |
| 533 | |
| 534 | let Inst{7-6} = 0b00; |
Johnny Chen | 7acca67 | 2010-02-05 18:04:58 +0000 | [diff] [blame] | 535 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 536 | |
Evan Cheng | 020cc1b | 2010-05-13 00:16:46 +0000 | [diff] [blame] | 537 | let neverHasSideEffects = 1 in |
Johnny Chen | 23401d6 | 2010-02-08 17:26:09 +0000 | [diff] [blame] | 538 | def VMOVSRR : AVConv5I<0b11000100, 0b1010, |
| 539 | (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2), |
Anton Korobeynikov | a31c6fb | 2010-04-07 18:20:02 +0000 | [diff] [blame] | 540 | IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2", |
Johnny Chen | 23401d6 | 2010-02-08 17:26:09 +0000 | [diff] [blame] | 541 | [/* For disassembly only; pattern left blank */]> { |
| 542 | let Inst{7-6} = 0b00; |
| 543 | } |
| 544 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 545 | // FMRDH: SPR -> GPR |
| 546 | // FMRDL: SPR -> GPR |
| 547 | // FMRRS: SPR -> GPR |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 548 | // FMRX: SPR system reg -> GPR |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 549 | // FMSRR: GPR -> SPR |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 550 | // FMXR: GPR -> VFP system reg |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 551 | |
| 552 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 553 | // Int -> FP: |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 554 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 555 | class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, |
| 556 | bits<4> opcod4, dag oops, dag iops, |
| 557 | InstrItinClass itin, string opc, string asm, |
| 558 | list<dag> pattern> |
| 559 | : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, |
| 560 | pattern> { |
| 561 | // Instruction operands. |
| 562 | bits<5> Dd; |
| 563 | bits<5> Sm; |
| 564 | |
| 565 | // Encode instruction operands. |
| 566 | let Inst{3-0} = Sm{4-1}; |
| 567 | let Inst{5} = Sm{0}; |
| 568 | let Inst{15-12} = Dd{3-0}; |
| 569 | let Inst{22} = Dd{4}; |
| 570 | } |
| 571 | |
| 572 | class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, |
| 573 | bits<4> opcod4, dag oops, dag iops,InstrItinClass itin, |
| 574 | string opc, string asm, list<dag> pattern> |
| 575 | : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, |
| 576 | pattern> { |
| 577 | // Instruction operands. |
| 578 | bits<5> Sd; |
| 579 | bits<5> Sm; |
| 580 | |
| 581 | // Encode instruction operands. |
| 582 | let Inst{3-0} = Sm{4-1}; |
| 583 | let Inst{5} = Sm{0}; |
| 584 | let Inst{15-12} = Sd{4-1}; |
| 585 | let Inst{22} = Sd{0}; |
| 586 | } |
| 587 | |
| 588 | def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, |
| 589 | (outs DPR:$Dd), (ins SPR:$Sm), |
| 590 | IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm", |
| 591 | [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> { |
Johnny Chen | 69a8c7f | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 592 | let Inst{7} = 1; // s32 |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 593 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 594 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 595 | def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, |
| 596 | (outs SPR:$Sd),(ins SPR:$Sm), |
| 597 | IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm", |
| 598 | [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> { |
Johnny Chen | 69a8c7f | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 599 | let Inst{7} = 1; // s32 |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 600 | |
| 601 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 602 | // pipelines. |
| 603 | let D = VFPNeonDomain; |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 604 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 605 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 606 | def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, |
| 607 | (outs DPR:$Dd), (ins SPR:$Sm), |
| 608 | IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm", |
| 609 | [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> { |
Johnny Chen | 69a8c7f | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 610 | let Inst{7} = 0; // u32 |
| 611 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 612 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 613 | def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, |
| 614 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 615 | IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm", |
| 616 | [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> { |
Johnny Chen | 69a8c7f | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 617 | let Inst{7} = 0; // u32 |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 618 | |
| 619 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 620 | // pipelines. |
| 621 | let D = VFPNeonDomain; |
Johnny Chen | 69a8c7f | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 622 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 623 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 624 | // FP -> Int: |
| 625 | |
| 626 | class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, |
| 627 | bits<4> opcod4, dag oops, dag iops, |
| 628 | InstrItinClass itin, string opc, string asm, |
| 629 | list<dag> pattern> |
| 630 | : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, |
| 631 | pattern> { |
| 632 | // Instruction operands. |
| 633 | bits<5> Sd; |
| 634 | bits<5> Dm; |
| 635 | |
| 636 | // Encode instruction operands. |
| 637 | let Inst{3-0} = Dm{3-0}; |
| 638 | let Inst{5} = Dm{4}; |
| 639 | let Inst{15-12} = Sd{4-1}; |
| 640 | let Inst{22} = Sd{0}; |
| 641 | } |
| 642 | |
| 643 | class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, |
| 644 | bits<4> opcod4, dag oops, dag iops, |
| 645 | InstrItinClass itin, string opc, string asm, |
| 646 | list<dag> pattern> |
| 647 | : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, |
| 648 | pattern> { |
| 649 | // Instruction operands. |
| 650 | bits<5> Sd; |
| 651 | bits<5> Sm; |
| 652 | |
| 653 | // Encode instruction operands. |
| 654 | let Inst{3-0} = Sm{4-1}; |
| 655 | let Inst{5} = Sm{0}; |
| 656 | let Inst{15-12} = Sd{4-1}; |
| 657 | let Inst{22} = Sd{0}; |
| 658 | } |
| 659 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 660 | // Always set Z bit in the instruction, i.e. "round towards zero" variants. |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 661 | def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, |
| 662 | (outs SPR:$Sd), (ins DPR:$Dm), |
| 663 | IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm", |
| 664 | [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> { |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 665 | let Inst{7} = 1; // Z bit |
| 666 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 667 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 668 | def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, |
| 669 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 670 | IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm", |
| 671 | [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> { |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 672 | let Inst{7} = 1; // Z bit |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 673 | |
| 674 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 675 | // pipelines. |
| 676 | let D = VFPNeonDomain; |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 677 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 678 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 679 | def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, |
| 680 | (outs SPR:$Sd), (ins DPR:$Dm), |
| 681 | IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm", |
| 682 | [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> { |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 683 | let Inst{7} = 1; // Z bit |
| 684 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 685 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 686 | def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, |
| 687 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 688 | IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm", |
| 689 | [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> { |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 690 | let Inst{7} = 1; // Z bit |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 691 | |
| 692 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 693 | // pipelines. |
| 694 | let D = VFPNeonDomain; |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 695 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 696 | |
Johnny Chen | 15b423f | 2010-02-08 22:02:41 +0000 | [diff] [blame] | 697 | // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR. |
Nate Begeman | d1fb583 | 2010-08-03 21:31:55 +0000 | [diff] [blame] | 698 | let Uses = [FPSCR] in { |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 699 | // FIXME: Verify encoding after integrated assembler is working. |
| 700 | def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, |
| 701 | (outs SPR:$Sd), (ins DPR:$Dm), |
| 702 | IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm", |
| 703 | [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{ |
Johnny Chen | 15b423f | 2010-02-08 22:02:41 +0000 | [diff] [blame] | 704 | let Inst{7} = 0; // Z bit |
| 705 | } |
| 706 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 707 | def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, |
| 708 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 709 | IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm", |
| 710 | [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> { |
Johnny Chen | 15b423f | 2010-02-08 22:02:41 +0000 | [diff] [blame] | 711 | let Inst{7} = 0; // Z bit |
| 712 | } |
| 713 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 714 | def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, |
| 715 | (outs SPR:$Sd), (ins DPR:$Dm), |
| 716 | IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm", |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 717 | [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{ |
Johnny Chen | 15b423f | 2010-02-08 22:02:41 +0000 | [diff] [blame] | 718 | let Inst{7} = 0; // Z bit |
| 719 | } |
| 720 | |
Bill Wendling | 67a704d | 2010-10-13 20:58:46 +0000 | [diff] [blame] | 721 | def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, |
| 722 | (outs SPR:$Sd), (ins SPR:$Sm), |
| 723 | IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm", |
| 724 | [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> { |
Johnny Chen | 15b423f | 2010-02-08 22:02:41 +0000 | [diff] [blame] | 725 | let Inst{7} = 0; // Z bit |
| 726 | } |
Nate Begeman | d1fb583 | 2010-08-03 21:31:55 +0000 | [diff] [blame] | 727 | } |
Johnny Chen | 15b423f | 2010-02-08 22:02:41 +0000 | [diff] [blame] | 728 | |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 729 | // Convert between floating-point and fixed-point |
| 730 | // Data type for fixed-point naming convention: |
| 731 | // S16 (U=0, sx=0) -> SH |
| 732 | // U16 (U=1, sx=0) -> UH |
| 733 | // S32 (U=0, sx=1) -> SL |
| 734 | // U32 (U=1, sx=1) -> UL |
| 735 | |
Bill Wendling | 160acca | 2010-11-01 23:11:22 +0000 | [diff] [blame] | 736 | // FIXME: Marking these as codegen only seems wrong. They are real |
| 737 | // instructions(?) |
| 738 | let Constraints = "$a = $dst", isCodeGenOnly = 1 in { |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 739 | |
| 740 | // FP to Fixed-Point: |
| 741 | |
| 742 | def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0, |
Bill Wendling | cd944a4 | 2010-11-01 23:17:54 +0000 | [diff] [blame] | 743 | (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 744 | IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 745 | [/* For disassembly only; pattern left blank */]> { |
| 746 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 747 | // pipelines. |
| 748 | let D = VFPNeonDomain; |
| 749 | } |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 750 | |
| 751 | def VTOUHS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 0, |
| 752 | (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), |
| 753 | IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 754 | [/* For disassembly only; pattern left blank */]> { |
| 755 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 756 | // pipelines. |
| 757 | let D = VFPNeonDomain; |
| 758 | } |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 759 | |
| 760 | def VTOSLS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 1, |
| 761 | (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), |
| 762 | IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 763 | [/* For disassembly only; pattern left blank */]> { |
| 764 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 765 | // pipelines. |
| 766 | let D = VFPNeonDomain; |
| 767 | } |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 768 | |
| 769 | def VTOULS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 1, |
| 770 | (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), |
| 771 | IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 772 | [/* For disassembly only; pattern left blank */]> { |
| 773 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 774 | // pipelines. |
| 775 | let D = VFPNeonDomain; |
| 776 | } |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 777 | |
| 778 | def VTOSHD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 0, |
| 779 | (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), |
| 780 | IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", |
| 781 | [/* For disassembly only; pattern left blank */]>; |
| 782 | |
| 783 | def VTOUHD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 0, |
| 784 | (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), |
| 785 | IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", |
| 786 | [/* For disassembly only; pattern left blank */]>; |
| 787 | |
| 788 | def VTOSLD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 1, |
| 789 | (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), |
| 790 | IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", |
| 791 | [/* For disassembly only; pattern left blank */]>; |
| 792 | |
| 793 | def VTOULD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 1, |
| 794 | (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), |
| 795 | IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", |
| 796 | [/* For disassembly only; pattern left blank */]>; |
| 797 | |
| 798 | // Fixed-Point to FP: |
| 799 | |
| 800 | def VSHTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 0, |
| 801 | (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), |
| 802 | IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 803 | [/* For disassembly only; pattern left blank */]> { |
| 804 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 805 | // pipelines. |
| 806 | let D = VFPNeonDomain; |
| 807 | } |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 808 | |
| 809 | def VUHTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 0, |
| 810 | (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), |
| 811 | IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 812 | [/* For disassembly only; pattern left blank */]> { |
| 813 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 814 | // pipelines. |
| 815 | let D = VFPNeonDomain; |
| 816 | } |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 817 | |
| 818 | def VSLTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 1, |
| 819 | (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), |
| 820 | IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 821 | [/* For disassembly only; pattern left blank */]> { |
| 822 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 823 | // pipelines. |
| 824 | let D = VFPNeonDomain; |
| 825 | } |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 826 | |
| 827 | def VULTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 1, |
| 828 | (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), |
| 829 | IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 830 | [/* For disassembly only; pattern left blank */]> { |
| 831 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 832 | // pipelines. |
| 833 | let D = VFPNeonDomain; |
| 834 | } |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 835 | |
| 836 | def VSHTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 0, |
| 837 | (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), |
| 838 | IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", |
| 839 | [/* For disassembly only; pattern left blank */]>; |
| 840 | |
| 841 | def VUHTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 0, |
| 842 | (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), |
| 843 | IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", |
| 844 | [/* For disassembly only; pattern left blank */]>; |
| 845 | |
| 846 | def VSLTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 1, |
| 847 | (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), |
| 848 | IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", |
| 849 | [/* For disassembly only; pattern left blank */]>; |
| 850 | |
| 851 | def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1, |
| 852 | (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), |
| 853 | IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", |
| 854 | [/* For disassembly only; pattern left blank */]>; |
| 855 | |
Bill Wendling | 160acca | 2010-11-01 23:11:22 +0000 | [diff] [blame] | 856 | } // End of 'let Constraints = "$a = $dst", isCodeGenOnly = 1 in' |
Johnny Chen | 27bb8d0 | 2010-02-11 18:17:16 +0000 | [diff] [blame] | 857 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 858 | //===----------------------------------------------------------------------===// |
| 859 | // FP FMA Operations. |
| 860 | // |
| 861 | |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 862 | def VMLAD : ADbI<0b11100, 0b00, 0, 0, |
| 863 | (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), |
| 864 | IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 865 | [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), |
| 866 | (f64 DPR:$Ddin)))]>, |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 867 | RegConstraint<"$Ddin = $Dd">, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 868 | Requires<[HasVFP2,UseFPVMLx]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 869 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 870 | def VMLAS : ASbIn<0b11100, 0b00, 0, 0, |
| 871 | (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), |
| 872 | IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 873 | [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), |
| 874 | SPR:$Sdin))]>, |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 875 | RegConstraint<"$Sdin = $Sd">, |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 876 | Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> { |
| 877 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 878 | // pipelines. |
| 879 | let D = VFPNeonDomain; |
| 880 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 881 | |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 882 | def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 883 | (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 884 | Requires<[HasVFP2,UseFPVMLx]>; |
| 885 | def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 886 | (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 887 | Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 888 | |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 889 | def VMLSD : ADbI<0b11100, 0b00, 1, 0, |
| 890 | (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), |
| 891 | IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 892 | [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), |
| 893 | (f64 DPR:$Ddin)))]>, |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 894 | RegConstraint<"$Ddin = $Dd">, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 895 | Requires<[HasVFP2,UseFPVMLx]>; |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 896 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 897 | def VMLSS : ASbIn<0b11100, 0b00, 1, 0, |
| 898 | (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), |
| 899 | IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 900 | [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), |
| 901 | SPR:$Sdin))]>, |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 902 | RegConstraint<"$Sdin = $Sd">, |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 903 | Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> { |
| 904 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 905 | // pipelines. |
| 906 | let D = VFPNeonDomain; |
| 907 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 908 | |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 909 | def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 910 | (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 911 | Requires<[HasVFP2,UseFPVMLx]>; |
| 912 | def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 913 | (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 914 | Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; |
David Goodwin | b84f3d4 | 2009-08-04 18:44:29 +0000 | [diff] [blame] | 915 | |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 916 | def VNMLAD : ADbI<0b11100, 0b01, 1, 0, |
| 917 | (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), |
| 918 | IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 919 | [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), |
| 920 | (f64 DPR:$Ddin)))]>, |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 921 | RegConstraint<"$Ddin = $Dd">, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 922 | Requires<[HasVFP2,UseFPVMLx]>; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 923 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 924 | def VNMLAS : ASbI<0b11100, 0b01, 1, 0, |
| 925 | (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), |
| 926 | IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 927 | [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), |
| 928 | SPR:$Sdin))]>, |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 929 | RegConstraint<"$Sdin = $Sd">, |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 930 | Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> { |
| 931 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 932 | // pipelines. |
| 933 | let D = VFPNeonDomain; |
| 934 | } |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 935 | |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 936 | def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 937 | (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 938 | Requires<[HasVFP2,UseFPVMLx]>; |
| 939 | def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 940 | (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 941 | Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 942 | |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 943 | def VNMLSD : ADbI<0b11100, 0b01, 0, 0, |
| 944 | (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), |
| 945 | IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 946 | [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), |
| 947 | (f64 DPR:$Ddin)))]>, |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 948 | RegConstraint<"$Ddin = $Dd">, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 949 | Requires<[HasVFP2,UseFPVMLx]>; |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 950 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 951 | def VNMLSS : ASbI<0b11100, 0b01, 0, 0, |
| 952 | (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), |
| 953 | IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 954 | [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 955 | RegConstraint<"$Sdin = $Sd">, |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 956 | Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> { |
| 957 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 958 | // pipelines. |
| 959 | let D = VFPNeonDomain; |
| 960 | } |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 961 | |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 962 | def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 963 | (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 964 | Requires<[HasVFP2,UseFPVMLx]>; |
| 965 | def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), |
Evan Cheng | 529916c | 2010-11-12 20:32:20 +0000 | [diff] [blame] | 966 | (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 967 | Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 968 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 969 | |
| 970 | //===----------------------------------------------------------------------===// |
| 971 | // FP Conditional moves. |
| 972 | // |
| 973 | |
Evan Cheng | 020cc1b | 2010-05-13 00:16:46 +0000 | [diff] [blame] | 974 | let neverHasSideEffects = 1 in { |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 975 | def VMOVDcc : ADuI<0b11101, 0b11, 0b0000, 0b01, 0, |
| 976 | (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), |
| 977 | IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", |
| 978 | [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>, |
| 979 | RegConstraint<"$Dn = $Dd">; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 980 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 981 | def VMOVScc : ASuI<0b11101, 0b11, 0b0000, 0b01, 0, |
| 982 | (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), |
| 983 | IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", |
| 984 | [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>, |
| 985 | RegConstraint<"$Sn = $Sd">; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 986 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 987 | def VNEGDcc : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, |
| 988 | (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), |
| 989 | IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", |
| 990 | [/*(set DPR:$Dd, (ARMcneg DPR:$Dn, DPR:$Dm, imm:$cc))*/]>, |
| 991 | RegConstraint<"$Dn = $Dd">; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 992 | |
Bill Wendling | 6966119 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 993 | def VNEGScc : ASuI<0b11101, 0b11, 0b0001, 0b01, 0, |
| 994 | (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), |
| 995 | IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm", |
| 996 | [/*(set SPR:$Sd, (ARMcneg SPR:$Sn, SPR:$Sm, imm:$cc))*/]>, |
Evan Cheng | 5eda282 | 2011-02-16 00:35:02 +0000 | [diff] [blame^] | 997 | RegConstraint<"$Sn = $Sd"> { |
| 998 | // Some single precision VFP instructions may be executed on both NEON and VFP |
| 999 | // pipelines. |
| 1000 | let D = VFPNeonDomain; |
| 1001 | } |
Evan Cheng | 020cc1b | 2010-05-13 00:16:46 +0000 | [diff] [blame] | 1002 | } // neverHasSideEffects |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 1003 | |
| 1004 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | 6150590 | 2011-01-18 21:58:20 +0000 | [diff] [blame] | 1005 | // Move from VFP System Register to ARM core register. |
Evan Cheng | 78be83d | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 1006 | // |
| 1007 | |
Bruno Cardoso Lopes | 6150590 | 2011-01-18 21:58:20 +0000 | [diff] [blame] | 1008 | class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, |
| 1009 | list<dag> pattern>: |
| 1010 | VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 1011 | |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 1012 | // Instruction operand. |
| 1013 | bits<4> Rt; |
| 1014 | |
Johnny Chen | c974504 | 2010-02-09 22:35:38 +0000 | [diff] [blame] | 1015 | let Inst{27-20} = 0b11101111; |
Bruno Cardoso Lopes | 6150590 | 2011-01-18 21:58:20 +0000 | [diff] [blame] | 1016 | let Inst{19-16} = opc19_16; |
| 1017 | let Inst{15-12} = Rt; |
Johnny Chen | c974504 | 2010-02-09 22:35:38 +0000 | [diff] [blame] | 1018 | let Inst{11-8} = 0b1010; |
| 1019 | let Inst{7} = 0; |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 1020 | let Inst{6-5} = 0b00; |
Johnny Chen | c974504 | 2010-02-09 22:35:38 +0000 | [diff] [blame] | 1021 | let Inst{4} = 1; |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 1022 | let Inst{3-0} = 0b0000; |
Johnny Chen | c974504 | 2010-02-09 22:35:38 +0000 | [diff] [blame] | 1023 | } |
Johnny Chen | c974504 | 2010-02-09 22:35:38 +0000 | [diff] [blame] | 1024 | |
Bruno Cardoso Lopes | 6150590 | 2011-01-18 21:58:20 +0000 | [diff] [blame] | 1025 | // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags |
| 1026 | // to APSR. |
| 1027 | let Defs = [CPSR], Uses = [FPSCR], Rt = 0b1111 /* apsr_nzcv */ in |
| 1028 | def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins), |
| 1029 | "vmrs", "\tapsr_nzcv, fpscr", [(arm_fmstat)]>; |
| 1030 | |
| 1031 | // Application level FPSCR -> GPR |
| 1032 | let hasSideEffects = 1, Uses = [FPSCR] in |
| 1033 | def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins), |
| 1034 | "vmrs", "\t$Rt, fpscr", |
| 1035 | [(set GPR:$Rt, (int_arm_get_fpscr))]>; |
| 1036 | |
| 1037 | // System level FPEXC, FPSID -> GPR |
| 1038 | let Uses = [FPSCR] in { |
| 1039 | def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins), |
| 1040 | "vmrs", "\t$Rt, fpexc", []>; |
| 1041 | def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins), |
| 1042 | "vmrs", "\t$Rt, fpsid", []>; |
| 1043 | } |
| 1044 | |
| 1045 | //===----------------------------------------------------------------------===// |
| 1046 | // Move from ARM core register to VFP System Register. |
| 1047 | // |
| 1048 | |
| 1049 | class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, |
| 1050 | list<dag> pattern>: |
| 1051 | VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { |
| 1052 | |
Bill Wendling | 88cf038 | 2010-10-14 01:02:08 +0000 | [diff] [blame] | 1053 | // Instruction operand. |
| 1054 | bits<4> src; |
| 1055 | |
| 1056 | // Encode instruction operand. |
| 1057 | let Inst{15-12} = src; |
| 1058 | |
Johnny Chen | c974504 | 2010-02-09 22:35:38 +0000 | [diff] [blame] | 1059 | let Inst{27-20} = 0b11101110; |
Bruno Cardoso Lopes | 6150590 | 2011-01-18 21:58:20 +0000 | [diff] [blame] | 1060 | let Inst{19-16} = opc19_16; |
Johnny Chen | c974504 | 2010-02-09 22:35:38 +0000 | [diff] [blame] | 1061 | let Inst{11-8} = 0b1010; |
| 1062 | let Inst{7} = 0; |
| 1063 | let Inst{4} = 1; |
| 1064 | } |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 1065 | |
Bruno Cardoso Lopes | 6150590 | 2011-01-18 21:58:20 +0000 | [diff] [blame] | 1066 | let Defs = [FPSCR] in { |
| 1067 | // Application level GPR -> FPSCR |
| 1068 | def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src), |
| 1069 | "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>; |
| 1070 | // System level GPR -> FPEXC |
| 1071 | def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src), |
| 1072 | "vmsr", "\tfpexc, $src", []>; |
| 1073 | // System level GPR -> FPSID |
| 1074 | def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src), |
| 1075 | "vmsr", "\tfpsid, $src", []>; |
| 1076 | } |
| 1077 | |
| 1078 | //===----------------------------------------------------------------------===// |
| 1079 | // Misc. |
| 1080 | // |
| 1081 | |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 1082 | // Materialize FP immediates. VFP3 only. |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 1083 | let isReMaterializable = 1 in { |
Bill Wendling | bbbdcd4 | 2010-10-14 02:33:26 +0000 | [diff] [blame] | 1084 | def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm), |
Anton Korobeynikov | 63401e3 | 2010-04-07 18:19:56 +0000 | [diff] [blame] | 1085 | VFPMiscFrm, IIC_fpUNA64, |
Bill Wendling | bbbdcd4 | 2010-10-14 02:33:26 +0000 | [diff] [blame] | 1086 | "vmov", ".f64\t$Dd, $imm", |
| 1087 | [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> { |
| 1088 | // Instruction operands. |
| 1089 | bits<5> Dd; |
| 1090 | bits<32> imm; |
| 1091 | |
| 1092 | // Encode instruction operands. |
| 1093 | let Inst{15-12} = Dd{3-0}; |
| 1094 | let Inst{22} = Dd{4}; |
| 1095 | let Inst{19} = imm{31}; |
| 1096 | let Inst{18-16} = imm{22-20}; |
| 1097 | let Inst{3-0} = imm{19-16}; |
| 1098 | |
| 1099 | // Encode remaining instruction bits. |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 1100 | let Inst{27-23} = 0b11101; |
| 1101 | let Inst{21-20} = 0b11; |
| 1102 | let Inst{11-9} = 0b101; |
Bill Wendling | bbbdcd4 | 2010-10-14 02:33:26 +0000 | [diff] [blame] | 1103 | let Inst{8} = 1; // Double precision. |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 1104 | let Inst{7-4} = 0b0000; |
| 1105 | } |
| 1106 | |
Bill Wendling | bbbdcd4 | 2010-10-14 02:33:26 +0000 | [diff] [blame] | 1107 | def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm), |
| 1108 | VFPMiscFrm, IIC_fpUNA32, |
| 1109 | "vmov", ".f32\t$Sd, $imm", |
| 1110 | [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> { |
| 1111 | // Instruction operands. |
| 1112 | bits<5> Sd; |
| 1113 | bits<32> imm; |
| 1114 | |
| 1115 | // Encode instruction operands. |
| 1116 | let Inst{15-12} = Sd{4-1}; |
| 1117 | let Inst{22} = Sd{0}; |
| 1118 | let Inst{19} = imm{31}; // The immediate is handled as a double. |
| 1119 | let Inst{18-16} = imm{22-20}; |
| 1120 | let Inst{3-0} = imm{19-16}; |
| 1121 | |
| 1122 | // Encode remaining instruction bits. |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 1123 | let Inst{27-23} = 0b11101; |
| 1124 | let Inst{21-20} = 0b11; |
| 1125 | let Inst{11-9} = 0b101; |
Bill Wendling | bbbdcd4 | 2010-10-14 02:33:26 +0000 | [diff] [blame] | 1126 | let Inst{8} = 0; // Single precision. |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 1127 | let Inst{7-4} = 0b0000; |
| 1128 | } |
Evan Cheng | 3938242 | 2009-10-28 01:44:26 +0000 | [diff] [blame] | 1129 | } |