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Rafael Espindola7bc59bc2006-05-14 22:18:28 +00001//===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the "Instituto Nokia de Tecnologia" and
6// is distributed under the University of Illinois Open Source
7// License. See LICENSE.TXT for details.
8//
9//===----------------------------------------------------------------------===//
10//
11// This file contains the entry points for global functions defined in the LLVM
12// ARM back-end.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef TARGET_ARM_H
17#define TARGET_ARM_H
18
19#include <iosfwd>
20#include <cassert>
21
22namespace llvm {
Rafael Espindola6f602de2006-08-24 16:13:15 +000023 // Enums corresponding to ARM condition codes
24 namespace ARMCC {
25 enum CondCodes {
Rafael Espindola5f450d22006-09-02 20:24:25 +000026 EQ,
Rafael Espindolacdda88c2006-08-24 17:19:08 +000027 NE,
Rafael Espindola5f450d22006-09-02 20:24:25 +000028 CS,
29 CC,
30 MI,
31 PL,
32 VS,
33 VC,
34 HI,
35 LS,
36 GE,
37 LT,
38 GT,
39 LE,
40 AL
Rafael Espindola6f602de2006-08-24 16:13:15 +000041 };
42 }
43
44 static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
45 switch (CC) {
46 default: assert(0 && "Unknown condition code");
Rafael Espindolacdda88c2006-08-24 17:19:08 +000047 case ARMCC::EQ: return "eq";
Rafael Espindola5f450d22006-09-02 20:24:25 +000048 case ARMCC::NE: return "ne";
49 case ARMCC::CS: return "cs";
50 case ARMCC::CC: return "cc";
51 case ARMCC::MI: return "mi";
52 case ARMCC::PL: return "pl";
53 case ARMCC::VS: return "vs";
54 case ARMCC::VC: return "vc";
55 case ARMCC::HI: return "hi";
56 case ARMCC::LS: return "ls";
57 case ARMCC::GE: return "ge";
58 case ARMCC::LT: return "lt";
59 case ARMCC::GT: return "gt";
60 case ARMCC::LE: return "le";
61 case ARMCC::AL: return "al";
Rafael Espindola6f602de2006-08-24 16:13:15 +000062 }
63 }
64
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000065 class FunctionPass;
66 class TargetMachine;
67
68 FunctionPass *createARMISelDag(TargetMachine &TM);
69 FunctionPass *createARMCodePrinterPass(std::ostream &OS, TargetMachine &TM);
70} // end namespace llvm;
71
72// Defines symbolic names for ARM registers. This defines a mapping from
73// register name to register number.
74//
75#include "ARMGenRegisterNames.inc"
76
77// Defines symbolic names for the ARM instructions.
78//
79#include "ARMGenInstrNames.inc"
80
81
82#endif