blob: 7773fc9ee50b3a45be06beef20ea239f5a4cc4c8 [file] [log] [blame]
Nate Begeman1d9d7422005-10-18 00:28:58 +00001//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
Chris Lattner7c5a3d32005-08-16 17:14:42 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Chris Lattner7c5a3d32005-08-16 17:14:42 +00007//
8//===----------------------------------------------------------------------===//
9//
Nate Begeman21e463b2005-10-16 05:39:50 +000010// This file implements the PPCISelLowering class.
Chris Lattner7c5a3d32005-08-16 17:14:42 +000011//
12//===----------------------------------------------------------------------===//
13
Chris Lattner16e71f22005-10-14 23:59:06 +000014#include "PPCISelLowering.h"
Jim Laskey2f616bf2006-11-16 22:43:37 +000015#include "PPCMachineFunctionInfo.h"
Chris Lattnerdf4ed632006-11-17 22:10:59 +000016#include "PPCPredicates.h"
Chris Lattner16e71f22005-10-14 23:59:06 +000017#include "PPCTargetMachine.h"
Chris Lattner59138102006-04-17 05:28:54 +000018#include "PPCPerfectShuffle.h"
Owen Anderson718cb662007-09-07 04:06:50 +000019#include "llvm/ADT/STLExtras.h"
Nate Begeman750ac1b2006-02-01 07:19:44 +000020#include "llvm/ADT/VectorExtras.h"
Evan Chengc4c62572006-03-13 23:20:37 +000021#include "llvm/Analysis/ScalarEvolutionExpressions.h"
Chris Lattnerb9a7bea2007-03-06 00:59:59 +000022#include "llvm/CodeGen/CallingConvLower.h"
Chris Lattner7c5a3d32005-08-16 17:14:42 +000023#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner8a2d3ca2005-08-26 21:23:58 +000025#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000026#include "llvm/CodeGen/MachineRegisterInfo.h"
Dan Gohman69de1932008-02-06 22:27:42 +000027#include "llvm/CodeGen/PseudoSourceValue.h"
Chris Lattner7c5a3d32005-08-16 17:14:42 +000028#include "llvm/CodeGen/SelectionDAG.h"
Chris Lattner0b1e4e52005-08-26 17:36:52 +000029#include "llvm/Constants.h"
Chris Lattner7c5a3d32005-08-16 17:14:42 +000030#include "llvm/Function.h"
Chris Lattner6d92cad2006-03-26 10:06:40 +000031#include "llvm/Intrinsics.h"
Nate Begeman750ac1b2006-02-01 07:19:44 +000032#include "llvm/Support/MathExtras.h"
Evan Chengd2ee2182006-02-18 00:08:58 +000033#include "llvm/Target/TargetOptions.h"
Chris Lattner4eab7142006-11-10 02:08:47 +000034#include "llvm/Support/CommandLine.h"
Chris Lattner7c5a3d32005-08-16 17:14:42 +000035using namespace llvm;
36
Chris Lattner3ee77402007-06-19 05:46:06 +000037static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
38cl::desc("enable preincrement load/store generation on PPC (experimental)"),
39 cl::Hidden);
Chris Lattner4eab7142006-11-10 02:08:47 +000040
Chris Lattner331d1bc2006-11-02 01:44:04 +000041PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
42 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
Chris Lattner7c5a3d32005-08-16 17:14:42 +000043
Nate Begeman405e3ec2005-10-21 00:02:42 +000044 setPow2DivIsCheap();
Chris Lattner7c5a3d32005-08-16 17:14:42 +000045
Chris Lattnerd145a612005-09-27 22:18:25 +000046 // Use _setjmp/_longjmp instead of setjmp/longjmp.
Anton Korobeynikovd27a2582006-12-10 23:12:42 +000047 setUseUnderscoreSetJmp(true);
48 setUseUnderscoreLongJmp(true);
Chris Lattnerd145a612005-09-27 22:18:25 +000049
Chris Lattner7c5a3d32005-08-16 17:14:42 +000050 // Set up the register classes.
Nate Begeman1d9d7422005-10-18 00:28:58 +000051 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
52 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
53 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
Chris Lattner7c5a3d32005-08-16 17:14:42 +000054
Evan Chengc5484282006-10-04 00:56:09 +000055 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
Duncan Sandsf9c98e62008-01-23 20:39:46 +000056 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
Evan Chengc5484282006-10-04 00:56:09 +000057 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
Duncan Sandsf9c98e62008-01-23 20:39:46 +000058
Chris Lattnerddf89562008-01-17 19:59:44 +000059 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
60
Chris Lattner94e509c2006-11-10 23:58:45 +000061 // PowerPC has pre-inc load and store's.
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
Evan Chengcd633192006-11-09 19:11:50 +000065 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
Chris Lattner94e509c2006-11-10 23:58:45 +000067 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
Evan Chengcd633192006-11-09 19:11:50 +000070 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
72
Dale Johannesen638ccd52007-10-06 01:24:11 +000073 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
74 setConvertAction(MVT::ppcf128, MVT::f64, Expand);
75 setConvertAction(MVT::ppcf128, MVT::f32, Expand);
Dale Johannesen6eaeff22007-10-10 01:01:31 +000076 // This is used in the ppcf128->int sequence. Note it has different semantics
77 // from FP_ROUND: that rounds to nearest, this rounds to zero.
78 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
Dale Johannesen638ccd52007-10-06 01:24:11 +000079
Chris Lattner7c5a3d32005-08-16 17:14:42 +000080 // PowerPC has no intrinsics for these particular operations
81 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
82 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
83 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
Andrew Lenharthd497d9f2008-02-16 14:46:26 +000084 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
85
Chris Lattner7c5a3d32005-08-16 17:14:42 +000086 // PowerPC has no SREM/UREM instructions
87 setOperationAction(ISD::SREM, MVT::i32, Expand);
88 setOperationAction(ISD::UREM, MVT::i32, Expand);
Chris Lattner563ecfb2006-06-27 18:18:41 +000089 setOperationAction(ISD::SREM, MVT::i64, Expand);
90 setOperationAction(ISD::UREM, MVT::i64, Expand);
Dan Gohman3ce990d2007-10-08 17:28:24 +000091
92 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
93 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
94 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
95 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
96 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
97 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
98 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
99 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
100 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000101
Dan Gohmanf96e4de2007-10-11 23:21:31 +0000102 // We don't support sin/cos/sqrt/fmod/pow
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000103 setOperationAction(ISD::FSIN , MVT::f64, Expand);
104 setOperationAction(ISD::FCOS , MVT::f64, Expand);
Chris Lattner615c2d02005-09-28 22:29:58 +0000105 setOperationAction(ISD::FREM , MVT::f64, Expand);
Dan Gohmanf96e4de2007-10-11 23:21:31 +0000106 setOperationAction(ISD::FPOW , MVT::f64, Expand);
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000107 setOperationAction(ISD::FSIN , MVT::f32, Expand);
108 setOperationAction(ISD::FCOS , MVT::f32, Expand);
Chris Lattner615c2d02005-09-28 22:29:58 +0000109 setOperationAction(ISD::FREM , MVT::f32, Expand);
Dan Gohmanf96e4de2007-10-11 23:21:31 +0000110 setOperationAction(ISD::FPOW , MVT::f32, Expand);
Dale Johannesen5c5eb802008-01-18 19:55:37 +0000111
Dan Gohman1a024862008-01-31 00:41:03 +0000112 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000113
114 // If we're enabling GP optimizations, use hardware square root
Chris Lattner1e9de3e2005-09-02 18:33:05 +0000115 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000116 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
117 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
118 }
119
Chris Lattner9601a862006-03-05 05:08:37 +0000120 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
121 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
122
Nate Begemand88fc032006-01-14 03:14:10 +0000123 // PowerPC does not have BSWAP, CTPOP or CTTZ
124 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000125 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
126 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
Chris Lattnerf89437d2006-06-27 20:14:52 +0000127 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
128 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
129 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000130
Nate Begeman35ef9132006-01-11 21:21:00 +0000131 // PowerPC does not have ROTR
132 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
133
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000134 // PowerPC does not have Select
135 setOperationAction(ISD::SELECT, MVT::i32, Expand);
Chris Lattnerf89437d2006-06-27 20:14:52 +0000136 setOperationAction(ISD::SELECT, MVT::i64, Expand);
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000137 setOperationAction(ISD::SELECT, MVT::f32, Expand);
138 setOperationAction(ISD::SELECT, MVT::f64, Expand);
Chris Lattnere4bc9ea2005-08-26 00:52:45 +0000139
Chris Lattner0b1e4e52005-08-26 17:36:52 +0000140 // PowerPC wants to turn select_cc of FP into fsel when possible.
141 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
Nate Begeman44775902006-01-31 08:17:29 +0000143
Nate Begeman750ac1b2006-02-01 07:19:44 +0000144 // PowerPC wants to optimize integer setcc a bit
Nate Begeman44775902006-01-31 08:17:29 +0000145 setOperationAction(ISD::SETCC, MVT::i32, Custom);
Chris Lattnereb9b62e2005-08-31 19:09:57 +0000146
Nate Begeman81e80972006-03-17 01:40:33 +0000147 // PowerPC does not have BRCOND which requires SetCC
148 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
Evan Chengc35497f2006-10-30 08:02:39 +0000149
150 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000151
Chris Lattnerf7605322005-08-31 21:09:52 +0000152 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
153 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
Nate Begemanc09eeec2005-09-06 22:03:27 +0000154
Jim Laskeyad23c9d2005-08-17 00:40:22 +0000155 // PowerPC does not have [U|S]INT_TO_FP
156 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
157 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
158
Chris Lattner53e88452005-12-23 05:13:35 +0000159 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
160 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
Chris Lattner5f9faea2006-06-27 18:40:08 +0000161 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
162 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
Chris Lattner53e88452005-12-23 05:13:35 +0000163
Chris Lattner25b8b8c2006-04-28 21:56:10 +0000164 // We cannot sextinreg(i1). Expand to shifts.
165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
Jim Laskey2ad9f172007-02-22 14:56:36 +0000166
Jim Laskeyabf6d172006-01-05 01:25:28 +0000167 // Support label based line numbers.
Chris Lattnerf73bae12005-11-29 06:16:21 +0000168 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
Jim Laskeye0bce712006-01-05 01:47:43 +0000169 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
Nicolas Geoffray616585b2007-12-21 12:19:44 +0000170
171 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
172 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
173 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
174 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
175
Chris Lattnere6ec9f22005-09-10 00:21:06 +0000176
Nate Begeman28a6b022005-12-10 02:36:00 +0000177 // We want to legalize GlobalAddress and ConstantPool nodes into the
178 // appropriate instructions to materialize the address.
Chris Lattner3eef4e32005-11-17 18:26:56 +0000179 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
Lauro Ramos Venancio75ce0102007-07-11 17:19:51 +0000180 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
Nate Begeman28a6b022005-12-10 02:36:00 +0000181 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
Nate Begeman37efe672006-04-22 18:53:45 +0000182 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
Chris Lattner059ca0f2006-06-16 21:01:35 +0000183 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
Lauro Ramos Venancio75ce0102007-07-11 17:19:51 +0000184 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
Chris Lattner059ca0f2006-06-16 21:01:35 +0000185 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
186 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
187
Nate Begemanee625572006-01-27 21:09:22 +0000188 // RET must be custom lowered, to meet ABI requirements
189 setOperationAction(ISD::RET , MVT::Other, Custom);
Duncan Sands36397f52007-07-27 12:58:54 +0000190
Nate Begemanacc398c2006-01-25 18:21:52 +0000191 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
192 setOperationAction(ISD::VASTART , MVT::Other, Custom);
193
Nicolas Geoffray01119992007-04-03 13:59:52 +0000194 // VAARG is custom lowered with ELF 32 ABI
195 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
196 setOperationAction(ISD::VAARG, MVT::Other, Custom);
197 else
198 setOperationAction(ISD::VAARG, MVT::Other, Expand);
199
Chris Lattnerb22c08b2006-01-15 09:02:48 +0000200 // Use the default implementation.
Nate Begemanacc398c2006-01-25 18:21:52 +0000201 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
202 setOperationAction(ISD::VAEND , MVT::Other, Expand);
Chris Lattnerb22c08b2006-01-15 09:02:48 +0000203 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
Jim Laskeyefc7e522006-12-04 22:04:42 +0000204 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
Jim Laskey2f616bf2006-11-16 22:43:37 +0000205 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
Chris Lattner56a752e2006-10-18 01:18:48 +0000207
Chris Lattner6d92cad2006-03-26 10:06:40 +0000208 // We want to custom lower some of our intrinsics.
Chris Lattner48b61a72006-03-28 00:40:33 +0000209 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
Chris Lattner6d92cad2006-03-26 10:06:40 +0000210
Chris Lattnera7a58542006-06-16 17:34:12 +0000211 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
Nate Begeman1d9d7422005-10-18 00:28:58 +0000212 // They also have instructions for converting between i64 and fp.
Nate Begemanc09eeec2005-09-06 22:03:27 +0000213 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
Jim Laskeyca367b42006-12-15 14:32:57 +0000214 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
Nate Begemanc09eeec2005-09-06 22:03:27 +0000215 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
Chris Lattner85c671b2006-12-07 01:24:16 +0000216 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
Jim Laskeyca367b42006-12-15 14:32:57 +0000217 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
218
Chris Lattner7fbcef72006-03-24 07:53:47 +0000219 // FIXME: disable this lowered code. This generates 64-bit register values,
220 // and we don't model the fact that the top part is clobbered by calls. We
221 // need to flag these together so that the value isn't live across a call.
222 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
223
Nate Begemanae749a92005-10-25 23:48:36 +0000224 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
225 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
226 } else {
Chris Lattner860e8862005-11-17 07:30:41 +0000227 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
Nate Begemanae749a92005-10-25 23:48:36 +0000228 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
Nate Begeman9d2b8172005-10-18 00:56:42 +0000229 }
230
Chris Lattnera7a58542006-06-16 17:34:12 +0000231 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
Chris Lattner26cb2862007-10-19 04:08:28 +0000232 // 64-bit PowerPC implementations can support i64 types directly
Nate Begeman9d2b8172005-10-18 00:56:42 +0000233 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
Nate Begeman1d9d7422005-10-18 00:28:58 +0000234 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
235 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
Dan Gohman9ed06db2008-03-07 20:36:53 +0000236 // 64-bit PowerPC wants to expand i128 shifts itself.
237 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
238 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
239 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
Nate Begeman1d9d7422005-10-18 00:28:58 +0000240 } else {
Chris Lattner26cb2862007-10-19 04:08:28 +0000241 // 32-bit PowerPC wants to expand i64 shifts itself.
Chris Lattner3fe6c1d2006-09-20 03:47:40 +0000242 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
243 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
244 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
Nate Begemanc09eeec2005-09-06 22:03:27 +0000245 }
Evan Chengd30bf012006-03-01 01:11:20 +0000246
Nate Begeman425a9692005-11-29 08:17:20 +0000247 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
Chris Lattnere3fea5a2006-03-31 19:52:36 +0000248 // First set operation action for all vector types to expand. Then we
249 // will selectively turn on ones that can be effectively codegen'd.
250 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
Dan Gohmanf5135be2007-05-18 23:21:46 +0000251 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
Chris Lattnerf3f69de2006-04-16 01:37:57 +0000252 // add/sub are legal for all supported vector VT's.
Chris Lattnere3fea5a2006-03-31 19:52:36 +0000253 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
254 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
Chris Lattnere3fea5a2006-03-31 19:52:36 +0000255
Chris Lattner7ff7e672006-04-04 17:25:31 +0000256 // We promote all shuffles to v16i8.
257 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
Chris Lattnerf3f69de2006-04-16 01:37:57 +0000258 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
259
260 // We promote all non-typed operations to v4i32.
261 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
262 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
263 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
264 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
265 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
266 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
267 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
268 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
269 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
270 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
271 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
272 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
Chris Lattnere3fea5a2006-03-31 19:52:36 +0000273
Chris Lattnerf3f69de2006-04-16 01:37:57 +0000274 // No other operations are legal.
Chris Lattnere3fea5a2006-03-31 19:52:36 +0000275 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
276 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
277 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
278 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
279 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
Chris Lattner2ef5e892006-05-24 00:15:25 +0000280 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
Evan Cheng66ffe6b2007-07-30 07:51:22 +0000281 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
Chris Lattnere3fea5a2006-03-31 19:52:36 +0000282 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
283 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
284 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
Dan Gohman3ce990d2007-10-08 17:28:24 +0000285 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
286 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand);
287 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
288 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
Chris Lattner01cae072006-04-03 23:55:43 +0000289 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
Dan Gohmana3f269f2007-10-12 14:08:57 +0000290 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
291 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
292 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
293 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
Chris Lattnere3fea5a2006-03-31 19:52:36 +0000294 }
295
Chris Lattner7ff7e672006-04-04 17:25:31 +0000296 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
297 // with merges, splats, etc.
298 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
299
Chris Lattnerf3f69de2006-04-16 01:37:57 +0000300 setOperationAction(ISD::AND , MVT::v4i32, Legal);
301 setOperationAction(ISD::OR , MVT::v4i32, Legal);
302 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
303 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
304 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
305 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
306
Nate Begeman425a9692005-11-29 08:17:20 +0000307 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
Nate Begeman7fd1edd2005-12-19 23:25:09 +0000308 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
Chris Lattner8d052bc2006-03-25 07:39:07 +0000309 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
310 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
Chris Lattnerec4a0c72006-01-29 06:32:58 +0000311
Chris Lattnere3fea5a2006-03-31 19:52:36 +0000312 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
Chris Lattnere7c768e2006-04-18 03:24:30 +0000313 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
Chris Lattner72dd9bd2006-04-18 03:43:48 +0000314 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
Chris Lattner19a81522006-04-18 03:57:35 +0000315 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
Chris Lattnerf1d0b2b2006-03-20 01:53:53 +0000316
Chris Lattnerb2177b92006-03-19 06:55:52 +0000317 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
318 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
Chris Lattner64b3a082006-03-24 07:48:08 +0000319
Chris Lattner541f91b2006-04-02 00:43:36 +0000320 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
321 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
Chris Lattner64b3a082006-03-24 07:48:08 +0000322 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
323 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
Nate Begeman425a9692005-11-29 08:17:20 +0000324 }
325
Chris Lattnerc08f9022006-06-27 00:04:13 +0000326 setSetCCResultType(MVT::i32);
Chris Lattner7b0c58c2006-06-27 17:34:57 +0000327 setShiftAmountType(MVT::i32);
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000328 setSetCCResultContents(ZeroOrOneSetCCResult);
Chris Lattner10da9572006-10-18 01:20:43 +0000329
Jim Laskey2ad9f172007-02-22 14:56:36 +0000330 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
Chris Lattner10da9572006-10-18 01:20:43 +0000331 setStackPointerRegisterToSaveRestore(PPC::X1);
Jim Laskey2ad9f172007-02-22 14:56:36 +0000332 setExceptionPointerRegister(PPC::X3);
333 setExceptionSelectorRegister(PPC::X4);
334 } else {
Chris Lattner10da9572006-10-18 01:20:43 +0000335 setStackPointerRegisterToSaveRestore(PPC::R1);
Jim Laskey2ad9f172007-02-22 14:56:36 +0000336 setExceptionPointerRegister(PPC::R3);
337 setExceptionSelectorRegister(PPC::R4);
338 }
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000339
Chris Lattner8c13d0a2006-03-01 04:57:39 +0000340 // We have target-specific dag combine patterns for the following nodes:
341 setTargetDAGCombine(ISD::SINT_TO_FP);
Chris Lattner51269842006-03-01 05:50:56 +0000342 setTargetDAGCombine(ISD::STORE);
Chris Lattner90564f22006-04-18 17:59:36 +0000343 setTargetDAGCombine(ISD::BR_CC);
Chris Lattnerd9989382006-07-10 20:56:58 +0000344 setTargetDAGCombine(ISD::BSWAP);
Chris Lattner8c13d0a2006-03-01 04:57:39 +0000345
Dale Johannesenfabd32d2007-10-19 00:59:18 +0000346 // Darwin long double math library functions have $LDBL128 appended.
347 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
Duncan Sands007f9842008-01-10 10:28:30 +0000348 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
Dale Johannesenfabd32d2007-10-19 00:59:18 +0000349 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
350 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
Duncan Sands007f9842008-01-10 10:28:30 +0000351 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
352 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
Dale Johannesenfabd32d2007-10-19 00:59:18 +0000353 }
354
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000355 computeRegisterProperties();
356}
357
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000358/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
359/// function arguments in the caller parameter area.
360unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
361 TargetMachine &TM = getTargetMachine();
362 // Darwin passes everything on 4 byte boundary.
363 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
364 return 4;
365 // FIXME Elf TBD
366 return 4;
367}
368
Chris Lattnerda6d20f2006-01-09 23:52:17 +0000369const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
370 switch (Opcode) {
371 default: return 0;
372 case PPCISD::FSEL: return "PPCISD::FSEL";
373 case PPCISD::FCFID: return "PPCISD::FCFID";
374 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
375 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
Chris Lattner51269842006-03-01 05:50:56 +0000376 case PPCISD::STFIWX: return "PPCISD::STFIWX";
Chris Lattnerda6d20f2006-01-09 23:52:17 +0000377 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
378 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
Chris Lattnerf1d0b2b2006-03-20 01:53:53 +0000379 case PPCISD::VPERM: return "PPCISD::VPERM";
Chris Lattnerda6d20f2006-01-09 23:52:17 +0000380 case PPCISD::Hi: return "PPCISD::Hi";
381 case PPCISD::Lo: return "PPCISD::Lo";
Jim Laskey2060a822006-12-11 18:45:56 +0000382 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
Chris Lattnerda6d20f2006-01-09 23:52:17 +0000383 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
384 case PPCISD::SRL: return "PPCISD::SRL";
385 case PPCISD::SRA: return "PPCISD::SRA";
386 case PPCISD::SHL: return "PPCISD::SHL";
Chris Lattnerecfe55e2006-03-22 05:30:33 +0000387 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
388 case PPCISD::STD_32: return "PPCISD::STD_32";
Nicolas Geoffray63f8fb12007-02-27 13:01:19 +0000389 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
390 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
Chris Lattnerc703a8f2006-05-17 19:00:46 +0000391 case PPCISD::MTCTR: return "PPCISD::MTCTR";
Chris Lattner9f0bc652007-02-25 05:34:32 +0000392 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
393 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
Chris Lattnerda6d20f2006-01-09 23:52:17 +0000394 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
Chris Lattner6d92cad2006-03-26 10:06:40 +0000395 case PPCISD::MFCR: return "PPCISD::MFCR";
Chris Lattnera17b1552006-03-31 05:13:27 +0000396 case PPCISD::VCMP: return "PPCISD::VCMP";
Chris Lattner6d92cad2006-03-26 10:06:40 +0000397 case PPCISD::VCMPo: return "PPCISD::VCMPo";
Chris Lattnerd9989382006-07-10 20:56:58 +0000398 case PPCISD::LBRX: return "PPCISD::LBRX";
399 case PPCISD::STBRX: return "PPCISD::STBRX";
Chris Lattnerf70f8d92006-04-18 18:05:58 +0000400 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
Chris Lattneref97c672008-01-18 18:51:16 +0000401 case PPCISD::MFFS: return "PPCISD::MFFS";
402 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
403 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
404 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
405 case PPCISD::MTFSF: return "PPCISD::MTFSF";
Chris Lattnerda6d20f2006-01-09 23:52:17 +0000406 }
407}
408
Chris Lattner1a635d62006-04-14 06:01:58 +0000409//===----------------------------------------------------------------------===//
410// Node matching predicates, for use by the tblgen matching code.
411//===----------------------------------------------------------------------===//
412
Chris Lattner0b1e4e52005-08-26 17:36:52 +0000413/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
414static bool isFloatingPointZero(SDOperand Op) {
415 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
Dale Johanneseneaf08942007-08-31 04:03:46 +0000416 return CFP->getValueAPF().isZero();
Evan Cheng466685d2006-10-09 20:57:25 +0000417 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
Chris Lattner0b1e4e52005-08-26 17:36:52 +0000418 // Maybe this has already been legalized into the constant pool?
419 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
Evan Chengc356a572006-09-12 21:04:05 +0000420 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
Dale Johanneseneaf08942007-08-31 04:03:46 +0000421 return CFP->getValueAPF().isZero();
Chris Lattner0b1e4e52005-08-26 17:36:52 +0000422 }
423 return false;
424}
425
Chris Lattnerddb739e2006-04-06 17:23:16 +0000426/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
427/// true if Op is undef or if it matches the specified value.
428static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
429 return Op.getOpcode() == ISD::UNDEF ||
430 cast<ConstantSDNode>(Op)->getValue() == Val;
431}
432
433/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
434/// VPKUHUM instruction.
Chris Lattnerf24380e2006-04-06 22:28:36 +0000435bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
436 if (!isUnary) {
437 for (unsigned i = 0; i != 16; ++i)
438 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
439 return false;
440 } else {
441 for (unsigned i = 0; i != 8; ++i)
442 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
443 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
444 return false;
445 }
Chris Lattnerd0608e12006-04-06 18:26:28 +0000446 return true;
Chris Lattnerddb739e2006-04-06 17:23:16 +0000447}
448
449/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
450/// VPKUWUM instruction.
Chris Lattnerf24380e2006-04-06 22:28:36 +0000451bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
452 if (!isUnary) {
453 for (unsigned i = 0; i != 16; i += 2)
454 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
455 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
456 return false;
457 } else {
458 for (unsigned i = 0; i != 8; i += 2)
459 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
460 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
461 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
462 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
463 return false;
464 }
Chris Lattnerd0608e12006-04-06 18:26:28 +0000465 return true;
Chris Lattnerddb739e2006-04-06 17:23:16 +0000466}
467
Chris Lattnercaad1632006-04-06 22:02:42 +0000468/// isVMerge - Common function, used to match vmrg* shuffles.
469///
470static bool isVMerge(SDNode *N, unsigned UnitSize,
471 unsigned LHSStart, unsigned RHSStart) {
Chris Lattner116cc482006-04-06 21:11:54 +0000472 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
473 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
474 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
475 "Unsupported merge size!");
476
477 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
478 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
479 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
Chris Lattnercaad1632006-04-06 22:02:42 +0000480 LHSStart+j+i*UnitSize) ||
Chris Lattner116cc482006-04-06 21:11:54 +0000481 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
Chris Lattnercaad1632006-04-06 22:02:42 +0000482 RHSStart+j+i*UnitSize))
Chris Lattner116cc482006-04-06 21:11:54 +0000483 return false;
484 }
Chris Lattnercaad1632006-04-06 22:02:42 +0000485 return true;
486}
487
488/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
489/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
490bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
491 if (!isUnary)
492 return isVMerge(N, UnitSize, 8, 24);
493 return isVMerge(N, UnitSize, 8, 8);
Chris Lattner116cc482006-04-06 21:11:54 +0000494}
495
496/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
497/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
Chris Lattnercaad1632006-04-06 22:02:42 +0000498bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
499 if (!isUnary)
500 return isVMerge(N, UnitSize, 0, 16);
501 return isVMerge(N, UnitSize, 0, 0);
Chris Lattner116cc482006-04-06 21:11:54 +0000502}
503
504
Chris Lattnerd0608e12006-04-06 18:26:28 +0000505/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
506/// amount, otherwise return -1.
Chris Lattnerf24380e2006-04-06 22:28:36 +0000507int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
Chris Lattner116cc482006-04-06 21:11:54 +0000508 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
509 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
Chris Lattnerd0608e12006-04-06 18:26:28 +0000510 // Find the first non-undef value in the shuffle mask.
511 unsigned i;
512 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
513 /*search*/;
514
515 if (i == 16) return -1; // all undef.
516
517 // Otherwise, check to see if the rest of the elements are consequtively
518 // numbered from this value.
519 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
520 if (ShiftAmt < i) return -1;
521 ShiftAmt -= i;
Chris Lattnerddb739e2006-04-06 17:23:16 +0000522
Chris Lattnerf24380e2006-04-06 22:28:36 +0000523 if (!isUnary) {
524 // Check the rest of the elements to see if they are consequtive.
525 for (++i; i != 16; ++i)
526 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
527 return -1;
528 } else {
529 // Check the rest of the elements to see if they are consequtive.
530 for (++i; i != 16; ++i)
531 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
532 return -1;
533 }
Chris Lattnerd0608e12006-04-06 18:26:28 +0000534
535 return ShiftAmt;
536}
Chris Lattneref819f82006-03-20 06:33:01 +0000537
538/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
539/// specifies a splat of a single element that is suitable for input to
540/// VSPLTB/VSPLTH/VSPLTW.
Chris Lattner7ff7e672006-04-04 17:25:31 +0000541bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
542 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
543 N->getNumOperands() == 16 &&
544 (EltSize == 1 || EltSize == 2 || EltSize == 4));
Chris Lattnerdd4d2d02006-03-20 06:51:10 +0000545
Chris Lattner88a99ef2006-03-20 06:37:44 +0000546 // This is a splat operation if each element of the permute is the same, and
547 // if the value doesn't reference the second vector.
Chris Lattner7ff7e672006-04-04 17:25:31 +0000548 unsigned ElementBase = 0;
Chris Lattner88a99ef2006-03-20 06:37:44 +0000549 SDOperand Elt = N->getOperand(0);
Chris Lattner7ff7e672006-04-04 17:25:31 +0000550 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
551 ElementBase = EltV->getValue();
552 else
553 return false; // FIXME: Handle UNDEF elements too!
554
555 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
556 return false;
557
558 // Check that they are consequtive.
559 for (unsigned i = 1; i != EltSize; ++i) {
560 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
561 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
562 return false;
563 }
564
Chris Lattner88a99ef2006-03-20 06:37:44 +0000565 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
Chris Lattner7ff7e672006-04-04 17:25:31 +0000566 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
Chris Lattnerb097aa92006-04-14 23:19:08 +0000567 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
Chris Lattner88a99ef2006-03-20 06:37:44 +0000568 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
569 "Invalid VECTOR_SHUFFLE mask!");
Chris Lattner7ff7e672006-04-04 17:25:31 +0000570 for (unsigned j = 0; j != EltSize; ++j)
571 if (N->getOperand(i+j) != N->getOperand(j))
572 return false;
Chris Lattner88a99ef2006-03-20 06:37:44 +0000573 }
574
Chris Lattner7ff7e672006-04-04 17:25:31 +0000575 return true;
Chris Lattneref819f82006-03-20 06:33:01 +0000576}
577
Evan Cheng66ffe6b2007-07-30 07:51:22 +0000578/// isAllNegativeZeroVector - Returns true if all elements of build_vector
579/// are -0.0.
580bool PPC::isAllNegativeZeroVector(SDNode *N) {
581 assert(N->getOpcode() == ISD::BUILD_VECTOR);
582 if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
583 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
Dale Johanneseneaf08942007-08-31 04:03:46 +0000584 return CFP->getValueAPF().isNegZero();
Evan Cheng66ffe6b2007-07-30 07:51:22 +0000585 return false;
586}
587
Chris Lattneref819f82006-03-20 06:33:01 +0000588/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
589/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
Chris Lattner7ff7e672006-04-04 17:25:31 +0000590unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
591 assert(isSplatShuffleMask(N, EltSize));
592 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
Chris Lattneref819f82006-03-20 06:33:01 +0000593}
594
Chris Lattnere87192a2006-04-12 17:37:20 +0000595/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
Chris Lattner140a58f2006-04-08 06:46:53 +0000596/// by using a vspltis[bhw] instruction of the specified element size, return
597/// the constant being splatted. The ByteSize field indicates the number of
598/// bytes of each element [124] -> [bhw].
Chris Lattnere87192a2006-04-12 17:37:20 +0000599SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000600 SDOperand OpVal(0, 0);
Chris Lattner79d9a882006-04-08 07:14:26 +0000601
602 // If ByteSize of the splat is bigger than the element size of the
603 // build_vector, then we have a case where we are checking for a splat where
604 // multiple elements of the buildvector are folded together into a single
605 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
606 unsigned EltSize = 16/N->getNumOperands();
607 if (EltSize < ByteSize) {
608 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
609 SDOperand UniquedVals[4];
610 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
611
612 // See if all of the elements in the buildvector agree across.
613 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
614 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
615 // If the element isn't a constant, bail fully out.
616 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
617
618
619 if (UniquedVals[i&(Multiple-1)].Val == 0)
620 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
621 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
622 return SDOperand(); // no match.
623 }
624
625 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
626 // either constant or undef values that are identical for each chunk. See
627 // if these chunks can form into a larger vspltis*.
628
629 // Check to see if all of the leading entries are either 0 or -1. If
630 // neither, then this won't fit into the immediate field.
631 bool LeadingZero = true;
632 bool LeadingOnes = true;
633 for (unsigned i = 0; i != Multiple-1; ++i) {
634 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
635
636 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
637 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
638 }
639 // Finally, check the least significant entry.
640 if (LeadingZero) {
641 if (UniquedVals[Multiple-1].Val == 0)
642 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
643 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
644 if (Val < 16)
645 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
646 }
647 if (LeadingOnes) {
648 if (UniquedVals[Multiple-1].Val == 0)
649 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
650 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
651 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
652 return DAG.getTargetConstant(Val, MVT::i32);
653 }
654
655 return SDOperand();
656 }
657
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000658 // Check to see if this buildvec has a single non-undef value in its elements.
659 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
660 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
661 if (OpVal.Val == 0)
662 OpVal = N->getOperand(i);
663 else if (OpVal != N->getOperand(i))
Chris Lattner140a58f2006-04-08 06:46:53 +0000664 return SDOperand();
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000665 }
666
Chris Lattner140a58f2006-04-08 06:46:53 +0000667 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000668
Nate Begeman98e70cc2006-03-28 04:15:58 +0000669 unsigned ValSizeInBytes = 0;
670 uint64_t Value = 0;
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000671 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
672 Value = CN->getValue();
673 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
674 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
675 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
Dale Johanneseneaf08942007-08-31 04:03:46 +0000676 Value = FloatToBits(CN->getValueAPF().convertToFloat());
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000677 ValSizeInBytes = 4;
678 }
679
680 // If the splat value is larger than the element value, then we can never do
681 // this splat. The only case that we could fit the replicated bits into our
682 // immediate field for would be zero, and we prefer to use vxor for it.
Chris Lattner140a58f2006-04-08 06:46:53 +0000683 if (ValSizeInBytes < ByteSize) return SDOperand();
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000684
685 // If the element value is larger than the splat value, cut it in half and
686 // check to see if the two halves are equal. Continue doing this until we
687 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
688 while (ValSizeInBytes > ByteSize) {
689 ValSizeInBytes >>= 1;
690
691 // If the top half equals the bottom half, we're still ok.
Chris Lattner9b42bdd2006-04-05 17:39:25 +0000692 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
693 (Value & ((1 << (8*ValSizeInBytes))-1)))
Chris Lattner140a58f2006-04-08 06:46:53 +0000694 return SDOperand();
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000695 }
696
697 // Properly sign extend the value.
698 int ShAmt = (4-ByteSize)*8;
699 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
700
Evan Cheng5b6a01b2006-03-26 09:52:32 +0000701 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
Chris Lattner140a58f2006-04-08 06:46:53 +0000702 if (MaskVal == 0) return SDOperand();
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000703
Chris Lattner140a58f2006-04-08 06:46:53 +0000704 // Finally, if this value fits in a 5 bit sext field, return it
705 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
706 return DAG.getTargetConstant(MaskVal, MVT::i32);
707 return SDOperand();
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000708}
709
Chris Lattner1a635d62006-04-14 06:01:58 +0000710//===----------------------------------------------------------------------===//
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000711// Addressing Mode Selection
712//===----------------------------------------------------------------------===//
713
714/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
715/// or 64-bit immediate, and if the value can be accurately represented as a
716/// sign extension from a 16-bit value. If so, this returns true and the
717/// immediate.
718static bool isIntS16Immediate(SDNode *N, short &Imm) {
719 if (N->getOpcode() != ISD::Constant)
720 return false;
721
722 Imm = (short)cast<ConstantSDNode>(N)->getValue();
723 if (N->getValueType(0) == MVT::i32)
724 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
725 else
726 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
727}
728static bool isIntS16Immediate(SDOperand Op, short &Imm) {
729 return isIntS16Immediate(Op.Val, Imm);
730}
731
732
733/// SelectAddressRegReg - Given the specified addressed, check to see if it
734/// can be represented as an indexed [r+r] operation. Returns false if it
735/// can be more efficiently represented with [r+imm].
736bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
737 SDOperand &Index,
738 SelectionDAG &DAG) {
739 short imm = 0;
740 if (N.getOpcode() == ISD::ADD) {
741 if (isIntS16Immediate(N.getOperand(1), imm))
742 return false; // r+i
743 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
744 return false; // r+i
745
746 Base = N.getOperand(0);
747 Index = N.getOperand(1);
748 return true;
749 } else if (N.getOpcode() == ISD::OR) {
750 if (isIntS16Immediate(N.getOperand(1), imm))
751 return false; // r+i can fold it if we can.
752
753 // If this is an or of disjoint bitfields, we can codegen this as an add
754 // (for better address arithmetic) if the LHS and RHS of the OR are provably
755 // disjoint.
Dan Gohmanb3564aa2008-02-27 01:23:58 +0000756 APInt LHSKnownZero, LHSKnownOne;
757 APInt RHSKnownZero, RHSKnownOne;
758 DAG.ComputeMaskedBits(N.getOperand(0),
Dan Gohmanec59b952008-02-27 21:12:32 +0000759 APInt::getAllOnesValue(N.getOperand(0)
760 .getValueSizeInBits()),
Dan Gohmanb3564aa2008-02-27 01:23:58 +0000761 LHSKnownZero, LHSKnownOne);
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000762
Dan Gohmanb3564aa2008-02-27 01:23:58 +0000763 if (LHSKnownZero.getBoolValue()) {
764 DAG.ComputeMaskedBits(N.getOperand(1),
Dan Gohmanec59b952008-02-27 21:12:32 +0000765 APInt::getAllOnesValue(N.getOperand(1)
766 .getValueSizeInBits()),
Dan Gohmanb3564aa2008-02-27 01:23:58 +0000767 RHSKnownZero, RHSKnownOne);
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000768 // If all of the bits are known zero on the LHS or RHS, the add won't
769 // carry.
Dan Gohmanec59b952008-02-27 21:12:32 +0000770 if (~(LHSKnownZero | RHSKnownZero) == 0) {
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000771 Base = N.getOperand(0);
772 Index = N.getOperand(1);
773 return true;
774 }
775 }
776 }
777
778 return false;
779}
780
781/// Returns true if the address N can be represented by a base register plus
782/// a signed 16-bit displacement [r+imm], and if it is not better
783/// represented as reg+reg.
784bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
785 SDOperand &Base, SelectionDAG &DAG){
786 // If this can be more profitably realized as r+r, fail.
787 if (SelectAddressRegReg(N, Disp, Base, DAG))
788 return false;
789
790 if (N.getOpcode() == ISD::ADD) {
791 short imm = 0;
792 if (isIntS16Immediate(N.getOperand(1), imm)) {
793 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
794 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
795 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
796 } else {
797 Base = N.getOperand(0);
798 }
799 return true; // [r+i]
800 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
801 // Match LOAD (ADD (X, Lo(G))).
802 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
803 && "Cannot handle constant offsets yet!");
804 Disp = N.getOperand(1).getOperand(0); // The global address.
805 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
806 Disp.getOpcode() == ISD::TargetConstantPool ||
807 Disp.getOpcode() == ISD::TargetJumpTable);
808 Base = N.getOperand(0);
809 return true; // [&g+r]
810 }
811 } else if (N.getOpcode() == ISD::OR) {
812 short imm = 0;
813 if (isIntS16Immediate(N.getOperand(1), imm)) {
814 // If this is an or of disjoint bitfields, we can codegen this as an add
815 // (for better address arithmetic) if the LHS and RHS of the OR are
816 // provably disjoint.
Dan Gohmanb3564aa2008-02-27 01:23:58 +0000817 APInt LHSKnownZero, LHSKnownOne;
818 DAG.ComputeMaskedBits(N.getOperand(0),
819 APInt::getAllOnesValue(32),
820 LHSKnownZero, LHSKnownOne);
821 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000822 // If all of the bits are known zero on the LHS or RHS, the add won't
823 // carry.
824 Base = N.getOperand(0);
825 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
826 return true;
827 }
828 }
829 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
830 // Loading from a constant address.
831
832 // If this address fits entirely in a 16-bit sext immediate field, codegen
833 // this as "d, 0"
834 short Imm;
835 if (isIntS16Immediate(CN, Imm)) {
836 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
837 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
838 return true;
839 }
Chris Lattnerbc681d62007-02-17 06:44:03 +0000840
841 // Handle 32-bit sext immediates with LIS + addr mode.
842 if (CN->getValueType(0) == MVT::i32 ||
843 (int64_t)CN->getValue() == (int)CN->getValue()) {
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000844 int Addr = (int)CN->getValue();
845
846 // Otherwise, break this down into an LIS + disp.
Chris Lattnerbc681d62007-02-17 06:44:03 +0000847 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
848
849 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
850 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
851 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000852 return true;
853 }
854 }
855
856 Disp = DAG.getTargetConstant(0, getPointerTy());
857 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
858 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
859 else
860 Base = N;
861 return true; // [r+0]
862}
863
864/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
865/// represented as an indexed [r+r] operation.
866bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
867 SDOperand &Index,
868 SelectionDAG &DAG) {
869 // Check to see if we can easily represent this as an [r+r] address. This
870 // will fail if it thinks that the address is more profitably represented as
871 // reg+imm, e.g. where imm = 0.
872 if (SelectAddressRegReg(N, Base, Index, DAG))
873 return true;
874
875 // If the operand is an addition, always emit this as [r+r], since this is
876 // better (for code size, and execution, as the memop does the add for free)
877 // than emitting an explicit add.
878 if (N.getOpcode() == ISD::ADD) {
879 Base = N.getOperand(0);
880 Index = N.getOperand(1);
881 return true;
882 }
883
884 // Otherwise, do it the hard way, using R0 as the base register.
885 Base = DAG.getRegister(PPC::R0, N.getValueType());
886 Index = N;
887 return true;
888}
889
890/// SelectAddressRegImmShift - Returns true if the address N can be
891/// represented by a base register plus a signed 14-bit displacement
892/// [r+imm*4]. Suitable for use by STD and friends.
893bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
894 SDOperand &Base,
895 SelectionDAG &DAG) {
896 // If this can be more profitably realized as r+r, fail.
897 if (SelectAddressRegReg(N, Disp, Base, DAG))
898 return false;
899
900 if (N.getOpcode() == ISD::ADD) {
901 short imm = 0;
902 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
903 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
904 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
905 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
906 } else {
907 Base = N.getOperand(0);
908 }
909 return true; // [r+i]
910 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
911 // Match LOAD (ADD (X, Lo(G))).
912 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
913 && "Cannot handle constant offsets yet!");
914 Disp = N.getOperand(1).getOperand(0); // The global address.
915 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
916 Disp.getOpcode() == ISD::TargetConstantPool ||
917 Disp.getOpcode() == ISD::TargetJumpTable);
918 Base = N.getOperand(0);
919 return true; // [&g+r]
920 }
921 } else if (N.getOpcode() == ISD::OR) {
922 short imm = 0;
923 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
924 // If this is an or of disjoint bitfields, we can codegen this as an add
925 // (for better address arithmetic) if the LHS and RHS of the OR are
926 // provably disjoint.
Dan Gohmanb3564aa2008-02-27 01:23:58 +0000927 APInt LHSKnownZero, LHSKnownOne;
928 DAG.ComputeMaskedBits(N.getOperand(0),
929 APInt::getAllOnesValue(32),
930 LHSKnownZero, LHSKnownOne);
931 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000932 // If all of the bits are known zero on the LHS or RHS, the add won't
933 // carry.
934 Base = N.getOperand(0);
935 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
936 return true;
937 }
938 }
939 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
Chris Lattnerdee5a5a2007-02-17 06:57:26 +0000940 // Loading from a constant address. Verify low two bits are clear.
941 if ((CN->getValue() & 3) == 0) {
942 // If this address fits entirely in a 14-bit sext immediate field, codegen
943 // this as "d, 0"
944 short Imm;
945 if (isIntS16Immediate(CN, Imm)) {
946 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
947 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
948 return true;
949 }
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000950
Chris Lattnerdee5a5a2007-02-17 06:57:26 +0000951 // Fold the low-part of 32-bit absolute addresses into addr mode.
952 if (CN->getValueType(0) == MVT::i32 ||
953 (int64_t)CN->getValue() == (int)CN->getValue()) {
954 int Addr = (int)CN->getValue();
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000955
Chris Lattnerdee5a5a2007-02-17 06:57:26 +0000956 // Otherwise, break this down into an LIS + disp.
957 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
958
959 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
960 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
961 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
962 return true;
963 }
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000964 }
965 }
966
967 Disp = DAG.getTargetConstant(0, getPointerTy());
968 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
969 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
970 else
971 Base = N;
972 return true; // [r+0]
973}
974
975
976/// getPreIndexedAddressParts - returns true by value, base pointer and
977/// offset pointer and addressing mode by reference if the node's address
978/// can be legally represented as pre-indexed load / store address.
979bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
980 SDOperand &Offset,
Evan Cheng144d8f02006-11-09 17:55:04 +0000981 ISD::MemIndexedMode &AM,
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000982 SelectionDAG &DAG) {
Chris Lattner4eab7142006-11-10 02:08:47 +0000983 // Disabled by default for now.
984 if (!EnablePPCPreinc) return false;
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000985
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000986 SDOperand Ptr;
Chris Lattner2fe4bf42006-11-14 01:38:31 +0000987 MVT::ValueType VT;
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000988 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
989 Ptr = LD->getBasePtr();
Dan Gohmanb625f2f2008-01-30 00:15:11 +0000990 VT = LD->getMemoryVT();
Chris Lattner0851b4f2006-11-15 19:55:13 +0000991
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000992 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
Chris Lattner4eab7142006-11-10 02:08:47 +0000993 ST = ST;
Chris Lattner2fe4bf42006-11-14 01:38:31 +0000994 Ptr = ST->getBasePtr();
Dan Gohmanb625f2f2008-01-30 00:15:11 +0000995 VT = ST->getMemoryVT();
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000996 } else
997 return false;
998
Chris Lattner2fe4bf42006-11-14 01:38:31 +0000999 // PowerPC doesn't have preinc load/store instructions for vectors.
1000 if (MVT::isVector(VT))
1001 return false;
1002
Chris Lattner0851b4f2006-11-15 19:55:13 +00001003 // TODO: Check reg+reg first.
1004
1005 // LDU/STU use reg+imm*4, others use reg+imm.
1006 if (VT != MVT::i64) {
1007 // reg + imm
1008 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1009 return false;
1010 } else {
1011 // reg + imm * 4.
1012 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1013 return false;
1014 }
Chris Lattnerf6edf4d2006-11-11 00:08:42 +00001015
Chris Lattnerf6edf4d2006-11-11 00:08:42 +00001016 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Chris Lattner0851b4f2006-11-15 19:55:13 +00001017 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1018 // sext i32 to i64 when addr mode is r+i.
Dan Gohmanb625f2f2008-01-30 00:15:11 +00001019 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
Chris Lattnerf6edf4d2006-11-11 00:08:42 +00001020 LD->getExtensionType() == ISD::SEXTLOAD &&
1021 isa<ConstantSDNode>(Offset))
1022 return false;
Chris Lattner0851b4f2006-11-15 19:55:13 +00001023 }
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +00001024
Chris Lattner4eab7142006-11-10 02:08:47 +00001025 AM = ISD::PRE_INC;
1026 return true;
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +00001027}
1028
1029//===----------------------------------------------------------------------===//
Chris Lattner1a635d62006-04-14 06:01:58 +00001030// LowerOperation implementation
1031//===----------------------------------------------------------------------===//
1032
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001033SDOperand PPCTargetLowering::LowerConstantPool(SDOperand Op,
1034 SelectionDAG &DAG) {
Chris Lattner059ca0f2006-06-16 21:01:35 +00001035 MVT::ValueType PtrVT = Op.getValueType();
Chris Lattner1a635d62006-04-14 06:01:58 +00001036 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Evan Chengc356a572006-09-12 21:04:05 +00001037 Constant *C = CP->getConstVal();
Chris Lattner059ca0f2006-06-16 21:01:35 +00001038 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1039 SDOperand Zero = DAG.getConstant(0, PtrVT);
Chris Lattner1a635d62006-04-14 06:01:58 +00001040
1041 const TargetMachine &TM = DAG.getTarget();
1042
Chris Lattner059ca0f2006-06-16 21:01:35 +00001043 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
1044 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
1045
Chris Lattner1a635d62006-04-14 06:01:58 +00001046 // If this is a non-darwin platform, we don't support non-static relo models
1047 // yet.
1048 if (TM.getRelocationModel() == Reloc::Static ||
1049 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1050 // Generate non-pic code that has direct accesses to the constant pool.
1051 // The address of the global is just (hi(&g)+lo(&g)).
Chris Lattner059ca0f2006-06-16 21:01:35 +00001052 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
Chris Lattner1a635d62006-04-14 06:01:58 +00001053 }
1054
Chris Lattner35d86fe2006-07-26 21:12:04 +00001055 if (TM.getRelocationModel() == Reloc::PIC_) {
Chris Lattner1a635d62006-04-14 06:01:58 +00001056 // With PIC, the first instruction is actually "GR+hi(&G)".
Chris Lattner059ca0f2006-06-16 21:01:35 +00001057 Hi = DAG.getNode(ISD::ADD, PtrVT,
1058 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
Chris Lattner1a635d62006-04-14 06:01:58 +00001059 }
1060
Chris Lattner059ca0f2006-06-16 21:01:35 +00001061 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
Chris Lattner1a635d62006-04-14 06:01:58 +00001062 return Lo;
1063}
1064
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001065SDOperand PPCTargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner059ca0f2006-06-16 21:01:35 +00001066 MVT::ValueType PtrVT = Op.getValueType();
Nate Begeman37efe672006-04-22 18:53:45 +00001067 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
Chris Lattner059ca0f2006-06-16 21:01:35 +00001068 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1069 SDOperand Zero = DAG.getConstant(0, PtrVT);
Nate Begeman37efe672006-04-22 18:53:45 +00001070
1071 const TargetMachine &TM = DAG.getTarget();
Chris Lattner059ca0f2006-06-16 21:01:35 +00001072
1073 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
1074 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
1075
Nate Begeman37efe672006-04-22 18:53:45 +00001076 // If this is a non-darwin platform, we don't support non-static relo models
1077 // yet.
1078 if (TM.getRelocationModel() == Reloc::Static ||
1079 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1080 // Generate non-pic code that has direct accesses to the constant pool.
1081 // The address of the global is just (hi(&g)+lo(&g)).
Chris Lattner059ca0f2006-06-16 21:01:35 +00001082 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
Nate Begeman37efe672006-04-22 18:53:45 +00001083 }
1084
Chris Lattner35d86fe2006-07-26 21:12:04 +00001085 if (TM.getRelocationModel() == Reloc::PIC_) {
Nate Begeman37efe672006-04-22 18:53:45 +00001086 // With PIC, the first instruction is actually "GR+hi(&G)".
Chris Lattner059ca0f2006-06-16 21:01:35 +00001087 Hi = DAG.getNode(ISD::ADD, PtrVT,
Chris Lattner0d72a202006-07-28 16:45:47 +00001088 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
Nate Begeman37efe672006-04-22 18:53:45 +00001089 }
1090
Chris Lattner059ca0f2006-06-16 21:01:35 +00001091 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
Nate Begeman37efe672006-04-22 18:53:45 +00001092 return Lo;
1093}
1094
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001095SDOperand PPCTargetLowering::LowerGlobalTLSAddress(SDOperand Op,
1096 SelectionDAG &DAG) {
Lauro Ramos Venancio75ce0102007-07-11 17:19:51 +00001097 assert(0 && "TLS not implemented for PPC.");
1098}
1099
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001100SDOperand PPCTargetLowering::LowerGlobalAddress(SDOperand Op,
1101 SelectionDAG &DAG) {
Chris Lattner059ca0f2006-06-16 21:01:35 +00001102 MVT::ValueType PtrVT = Op.getValueType();
Chris Lattner1a635d62006-04-14 06:01:58 +00001103 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1104 GlobalValue *GV = GSDN->getGlobal();
Chris Lattner059ca0f2006-06-16 21:01:35 +00001105 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
Evan Chengfcf5d4f2008-02-02 05:06:29 +00001106 // If it's a debug information descriptor, don't mess with it.
1107 if (DAG.isVerifiedDebugInfoDesc(Op))
1108 return GA;
Chris Lattner059ca0f2006-06-16 21:01:35 +00001109 SDOperand Zero = DAG.getConstant(0, PtrVT);
Chris Lattner1a635d62006-04-14 06:01:58 +00001110
1111 const TargetMachine &TM = DAG.getTarget();
1112
Chris Lattner059ca0f2006-06-16 21:01:35 +00001113 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1114 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1115
Chris Lattner1a635d62006-04-14 06:01:58 +00001116 // If this is a non-darwin platform, we don't support non-static relo models
1117 // yet.
1118 if (TM.getRelocationModel() == Reloc::Static ||
1119 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1120 // Generate non-pic code that has direct accesses to globals.
1121 // The address of the global is just (hi(&g)+lo(&g)).
Chris Lattner059ca0f2006-06-16 21:01:35 +00001122 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
Chris Lattner1a635d62006-04-14 06:01:58 +00001123 }
1124
Chris Lattner35d86fe2006-07-26 21:12:04 +00001125 if (TM.getRelocationModel() == Reloc::PIC_) {
Chris Lattner1a635d62006-04-14 06:01:58 +00001126 // With PIC, the first instruction is actually "GR+hi(&G)".
Chris Lattner059ca0f2006-06-16 21:01:35 +00001127 Hi = DAG.getNode(ISD::ADD, PtrVT,
1128 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
Chris Lattner1a635d62006-04-14 06:01:58 +00001129 }
1130
Chris Lattner059ca0f2006-06-16 21:01:35 +00001131 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
Chris Lattner1a635d62006-04-14 06:01:58 +00001132
Chris Lattner57fc62c2006-12-11 23:22:45 +00001133 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
Chris Lattner1a635d62006-04-14 06:01:58 +00001134 return Lo;
1135
1136 // If the global is weak or external, we have to go through the lazy
1137 // resolution stub.
Evan Cheng466685d2006-10-09 20:57:25 +00001138 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
Chris Lattner1a635d62006-04-14 06:01:58 +00001139}
1140
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001141SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner1a635d62006-04-14 06:01:58 +00001142 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1143
1144 // If we're comparing for equality to zero, expose the fact that this is
1145 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1146 // fold the new nodes.
1147 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1148 if (C->isNullValue() && CC == ISD::SETEQ) {
1149 MVT::ValueType VT = Op.getOperand(0).getValueType();
1150 SDOperand Zext = Op.getOperand(0);
1151 if (VT < MVT::i32) {
1152 VT = MVT::i32;
1153 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1154 }
1155 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1156 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1157 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1158 DAG.getConstant(Log2b, MVT::i32));
1159 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1160 }
1161 // Leave comparisons against 0 and -1 alone for now, since they're usually
1162 // optimized. FIXME: revisit this when we can custom lower all setcc
1163 // optimizations.
1164 if (C->isAllOnesValue() || C->isNullValue())
1165 return SDOperand();
1166 }
1167
1168 // If we have an integer seteq/setne, turn it into a compare against zero
Chris Lattnerac011bc2006-11-14 05:28:08 +00001169 // by xor'ing the rhs with the lhs, which is faster than setting a
1170 // condition register, reading it back out, and masking the correct bit. The
1171 // normal approach here uses sub to do this instead of xor. Using xor exposes
1172 // the result to other bit-twiddling opportunities.
Chris Lattner1a635d62006-04-14 06:01:58 +00001173 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1174 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1175 MVT::ValueType VT = Op.getValueType();
Chris Lattnerac011bc2006-11-14 05:28:08 +00001176 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
Chris Lattner1a635d62006-04-14 06:01:58 +00001177 Op.getOperand(1));
1178 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1179 }
1180 return SDOperand();
1181}
1182
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001183SDOperand PPCTargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG,
Nicolas Geoffray01119992007-04-03 13:59:52 +00001184 int VarArgsFrameIndex,
1185 int VarArgsStackOffset,
1186 unsigned VarArgsNumGPR,
1187 unsigned VarArgsNumFPR,
1188 const PPCSubtarget &Subtarget) {
1189
1190 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1191}
1192
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001193SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG,
Nicolas Geoffray01119992007-04-03 13:59:52 +00001194 int VarArgsFrameIndex,
1195 int VarArgsStackOffset,
1196 unsigned VarArgsNumGPR,
1197 unsigned VarArgsNumFPR,
1198 const PPCSubtarget &Subtarget) {
1199
1200 if (Subtarget.isMachoABI()) {
1201 // vastart just stores the address of the VarArgsFrameIndex slot into the
1202 // memory location argument.
1203 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1204 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
Dan Gohman69de1932008-02-06 22:27:42 +00001205 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1206 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
Nicolas Geoffray01119992007-04-03 13:59:52 +00001207 }
1208
1209 // For ELF 32 ABI we follow the layout of the va_list struct.
1210 // We suppose the given va_list is already allocated.
1211 //
1212 // typedef struct {
1213 // char gpr; /* index into the array of 8 GPRs
1214 // * stored in the register save area
1215 // * gpr=0 corresponds to r3,
1216 // * gpr=1 to r4, etc.
1217 // */
1218 // char fpr; /* index into the array of 8 FPRs
1219 // * stored in the register save area
1220 // * fpr=0 corresponds to f1,
1221 // * fpr=1 to f2, etc.
1222 // */
1223 // char *overflow_arg_area;
1224 // /* location on stack that holds
1225 // * the next overflow argument
1226 // */
1227 // char *reg_save_area;
1228 // /* where r3:r10 and f1:f8 (if saved)
1229 // * are stored
1230 // */
1231 // } va_list[1];
1232
1233
1234 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1235 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1236
1237
Chris Lattner0d72a202006-07-28 16:45:47 +00001238 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Nicolas Geoffray01119992007-04-03 13:59:52 +00001239
Dan Gohman69de1932008-02-06 22:27:42 +00001240 SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
Chris Lattner0d72a202006-07-28 16:45:47 +00001241 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
Nicolas Geoffray01119992007-04-03 13:59:52 +00001242
Dan Gohman69de1932008-02-06 22:27:42 +00001243 uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8;
1244 SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1245
1246 uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1;
1247 SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1248
1249 uint64_t FPROffset = 1;
1250 SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
Nicolas Geoffray01119992007-04-03 13:59:52 +00001251
Dan Gohman69de1932008-02-06 22:27:42 +00001252 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Nicolas Geoffray01119992007-04-03 13:59:52 +00001253
1254 // Store first byte : number of int regs
1255 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
Dan Gohman69de1932008-02-06 22:27:42 +00001256 Op.getOperand(1), SV, 0);
1257 uint64_t nextOffset = FPROffset;
Nicolas Geoffray01119992007-04-03 13:59:52 +00001258 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
1259 ConstFPROffset);
1260
1261 // Store second byte : number of float regs
Dan Gohman69de1932008-02-06 22:27:42 +00001262 SDOperand secondStore =
1263 DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset);
1264 nextOffset += StackOffset;
Nicolas Geoffray01119992007-04-03 13:59:52 +00001265 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
1266
1267 // Store second word : arguments given on stack
Dan Gohman69de1932008-02-06 22:27:42 +00001268 SDOperand thirdStore =
1269 DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset);
1270 nextOffset += FrameOffset;
Nicolas Geoffray01119992007-04-03 13:59:52 +00001271 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
1272
1273 // Store third word : arguments given in registers
Dan Gohman69de1932008-02-06 22:27:42 +00001274 return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset);
Nicolas Geoffray01119992007-04-03 13:59:52 +00001275
Chris Lattner1a635d62006-04-14 06:01:58 +00001276}
1277
Chris Lattnerb9a7bea2007-03-06 00:59:59 +00001278#include "PPCGenCallingConv.inc"
1279
Chris Lattner9f0bc652007-02-25 05:34:32 +00001280/// GetFPR - Get the set of FP registers that should be allocated for arguments,
1281/// depending on which subtarget is selected.
1282static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1283 if (Subtarget.isMachoABI()) {
1284 static const unsigned FPR[] = {
1285 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1286 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1287 };
1288 return FPR;
1289 }
1290
1291
1292 static const unsigned FPR[] = {
1293 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
Nicolas Geoffrayef3c0302007-04-03 10:27:07 +00001294 PPC::F8
Chris Lattner9f0bc652007-02-25 05:34:32 +00001295 };
1296 return FPR;
1297}
1298
Bill Wendling5f5bf3a2008-03-07 20:49:02 +00001299SDOperand
1300PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
1301 SelectionDAG &DAG,
1302 int &VarArgsFrameIndex,
1303 int &VarArgsStackOffset,
1304 unsigned &VarArgsNumGPR,
1305 unsigned &VarArgsNumFPR,
1306 const PPCSubtarget &Subtarget) {
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001307 // TODO: add description of PPC stack frame format, or at least some docs.
1308 //
1309 MachineFunction &MF = DAG.getMachineFunction();
1310 MachineFrameInfo *MFI = MF.getFrameInfo();
Chris Lattner84bc5422007-12-31 04:13:23 +00001311 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Chris Lattner79e490a2006-08-11 17:18:05 +00001312 SmallVector<SDOperand, 8> ArgValues;
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001313 SDOperand Root = Op.getOperand(0);
1314
Jim Laskey2f616bf2006-11-16 22:43:37 +00001315 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1316 bool isPPC64 = PtrVT == MVT::i64;
Chris Lattner9f0bc652007-02-25 05:34:32 +00001317 bool isMachoABI = Subtarget.isMachoABI();
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00001318 bool isELF32_ABI = Subtarget.isELF32_ABI();
Jim Laskeye9bd7b22006-11-28 14:53:52 +00001319 unsigned PtrByteSize = isPPC64 ? 8 : 4;
Jim Laskey2f616bf2006-11-16 22:43:37 +00001320
Chris Lattner9f0bc652007-02-25 05:34:32 +00001321 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
Chris Lattnerc91a4752006-06-26 22:48:35 +00001322
1323 static const unsigned GPR_32[] = { // 32-bit registers.
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001324 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1325 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1326 };
Chris Lattnerc91a4752006-06-26 22:48:35 +00001327 static const unsigned GPR_64[] = { // 64-bit registers.
1328 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1329 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1330 };
Chris Lattner9f0bc652007-02-25 05:34:32 +00001331
1332 static const unsigned *FPR = GetFPR(Subtarget);
1333
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001334 static const unsigned VR[] = {
1335 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1336 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1337 };
Chris Lattnerc91a4752006-06-26 22:48:35 +00001338
Owen Anderson718cb662007-09-07 04:06:50 +00001339 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
Nicolas Geoffrayef3c0302007-04-03 10:27:07 +00001340 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
Owen Anderson718cb662007-09-07 04:06:50 +00001341 const unsigned Num_VR_Regs = array_lengthof( VR);
Jim Laskey2f616bf2006-11-16 22:43:37 +00001342
1343 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1344
Chris Lattnerc91a4752006-06-26 22:48:35 +00001345 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001346
1347 // Add DAG nodes to load the arguments or copy them out of registers. On
Jim Laskey2f616bf2006-11-16 22:43:37 +00001348 // entry to a function on PPC, the arguments start after the linkage area,
1349 // although the first ones are often in registers.
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001350 //
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00001351 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001352 // represented with two words (long long or double) must be copied to an
1353 // even GPR_idx value or to an even ArgOffset value.
1354
Dale Johannesen8419dd62008-03-07 20:27:40 +00001355 SmallVector<SDOperand, 8> MemOps;
1356
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001357 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1358 SDOperand ArgVal;
1359 bool needsLoad = false;
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001360 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1361 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
Jim Laskey619965d2006-11-29 13:37:09 +00001362 unsigned ArgSize = ObjSize;
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001363 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue();
1364 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
Dale Johannesen8419dd62008-03-07 20:27:40 +00001365 unsigned isByVal = Flags & ISD::ParamFlags::ByVal;
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001366 // See if next argument requires stack alignment in ELF
1367 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) &&
1368 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) &&
1369 (!(Flags & AlignFlag)));
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001370
Chris Lattnerbe4849a2006-05-16 18:51:52 +00001371 unsigned CurArgOffset = ArgOffset;
Dale Johannesen8419dd62008-03-07 20:27:40 +00001372
1373 // FIXME alignment for ELF may not be right
1374 // FIXME the codegen can be much improved in some cases.
1375 // We do not have to keep everything in memory.
1376 if (isByVal) {
1377 // Double word align in ELF
1378 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1379 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1380 ObjSize = (Flags & ISD::ParamFlags::ByValSize) >>
1381 ISD::ParamFlags::ByValSizeOffs;
1382 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1383 // The value of the object is its address.
1384 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
1385 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1386 ArgValues.push_back(FIN);
1387 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1388 // Store whatever pieces of the object are in registers
1389 // to memory. ArgVal will be address of the beginning of
1390 // the object.
1391 if (GPR_idx != Num_GPR_Regs) {
1392 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1393 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1394 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
1395 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1396 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1397 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1398 MemOps.push_back(Store);
1399 ++GPR_idx;
1400 if (isMachoABI) ArgOffset += PtrByteSize;
1401 } else {
1402 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1403 break;
1404 }
1405 }
1406 continue;
1407 }
1408
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001409 switch (ObjectVT) {
1410 default: assert(0 && "Unhandled argument type!");
1411 case MVT::i32:
Bill Wendling5f5bf3a2008-03-07 20:49:02 +00001412 if (!isPPC64) {
1413 // Double word align in ELF
1414 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1415
1416 if (GPR_idx != Num_GPR_Regs) {
1417 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1418 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1419 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1420 ++GPR_idx;
1421 } else {
1422 needsLoad = true;
1423 ArgSize = PtrByteSize;
1424 }
1425 // Stack align in ELF
1426 if (needsLoad && Expand && isELF32_ABI)
1427 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1428 // All int arguments reserve stack space in Macho ABI.
1429 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1430 break;
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001431 }
Bill Wendling5f5bf3a2008-03-07 20:49:02 +00001432 // FALLTHROUGH
Chris Lattner9f0bc652007-02-25 05:34:32 +00001433 case MVT::i64: // PPC64
Chris Lattnerc91a4752006-06-26 22:48:35 +00001434 if (GPR_idx != Num_GPR_Regs) {
Chris Lattner84bc5422007-12-31 04:13:23 +00001435 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1436 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
Chris Lattnerc91a4752006-06-26 22:48:35 +00001437 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
Bill Wendling5f5bf3a2008-03-07 20:49:02 +00001438
1439 if (ObjectVT == MVT::i32) {
1440 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1441 // value to MVT::i64 and then truncate to the correct register size.
1442 if (Flags & ISD::ParamFlags::SExt)
1443 ArgVal = DAG.getNode(ISD::AssertSext, MVT::i64, ArgVal,
1444 DAG.getValueType(ObjectVT));
1445 else if (Flags & ISD::ParamFlags::ZExt)
1446 ArgVal = DAG.getNode(ISD::AssertZext, MVT::i64, ArgVal,
1447 DAG.getValueType(ObjectVT));
1448
1449 ArgVal = DAG.getNode(ISD::TRUNCATE, MVT::i32, ArgVal);
1450 }
1451
Chris Lattnerc91a4752006-06-26 22:48:35 +00001452 ++GPR_idx;
1453 } else {
1454 needsLoad = true;
1455 }
Chris Lattner9f0bc652007-02-25 05:34:32 +00001456 // All int arguments reserve stack space in Macho ABI.
1457 if (isMachoABI || needsLoad) ArgOffset += 8;
Chris Lattnerc91a4752006-06-26 22:48:35 +00001458 break;
Chris Lattner9f0bc652007-02-25 05:34:32 +00001459
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001460 case MVT::f32:
1461 case MVT::f64:
Chris Lattnerbe4849a2006-05-16 18:51:52 +00001462 // Every 4 bytes of argument space consumes one of the GPRs available for
1463 // argument passing.
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001464 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
Chris Lattneraf4ec0c2006-05-16 18:58:15 +00001465 ++GPR_idx;
Chris Lattnerb1eb9872006-11-18 01:57:19 +00001466 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
Chris Lattneraf4ec0c2006-05-16 18:58:15 +00001467 ++GPR_idx;
Chris Lattnerbe4849a2006-05-16 18:51:52 +00001468 }
Chris Lattneraf4ec0c2006-05-16 18:58:15 +00001469 if (FPR_idx != Num_FPR_Regs) {
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001470 unsigned VReg;
1471 if (ObjectVT == MVT::f32)
Chris Lattner84bc5422007-12-31 04:13:23 +00001472 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass);
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001473 else
Chris Lattner84bc5422007-12-31 04:13:23 +00001474 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1475 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001476 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001477 ++FPR_idx;
1478 } else {
1479 needsLoad = true;
1480 }
Chris Lattner9f0bc652007-02-25 05:34:32 +00001481
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001482 // Stack align in ELF
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00001483 if (needsLoad && Expand && isELF32_ABI)
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001484 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
Chris Lattner9f0bc652007-02-25 05:34:32 +00001485 // All FP arguments reserve stack space in Macho ABI.
1486 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001487 break;
1488 case MVT::v4f32:
1489 case MVT::v4i32:
1490 case MVT::v8i16:
1491 case MVT::v16i8:
Chris Lattnerbe4849a2006-05-16 18:51:52 +00001492 // Note that vector arguments in registers don't reserve stack space.
Chris Lattneraf4ec0c2006-05-16 18:58:15 +00001493 if (VR_idx != Num_VR_Regs) {
Chris Lattner84bc5422007-12-31 04:13:23 +00001494 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
1495 RegInfo.addLiveIn(VR[VR_idx], VReg);
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001496 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001497 ++VR_idx;
1498 } else {
1499 // This should be simple, but requires getting 16-byte aligned stack
1500 // values.
1501 assert(0 && "Loading VR argument not implemented yet!");
1502 needsLoad = true;
1503 }
1504 break;
1505 }
1506
1507 // We need to load the argument to a virtual register if we determined above
Chris Lattner9f72d1a2008-02-13 07:35:30 +00001508 // that we ran out of physical registers of the appropriate type.
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001509 if (needsLoad) {
Chris Lattner9f72d1a2008-02-13 07:35:30 +00001510 int FI = MFI->CreateFixedObject(ObjSize,
1511 CurArgOffset + (ArgSize - ObjSize));
1512 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1513 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001514 }
1515
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001516 ArgValues.push_back(ArgVal);
1517 }
Dale Johannesen8419dd62008-03-07 20:27:40 +00001518
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001519 // If the function takes variable number of arguments, make a frame index for
1520 // the start of the first vararg value... for expansion of llvm.va_start.
1521 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1522 if (isVarArg) {
Nicolas Geoffray01119992007-04-03 13:59:52 +00001523
1524 int depth;
1525 if (isELF32_ABI) {
1526 VarArgsNumGPR = GPR_idx;
1527 VarArgsNumFPR = FPR_idx;
1528
1529 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1530 // pointer.
1531 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 +
1532 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 +
1533 MVT::getSizeInBits(PtrVT)/8);
1534
1535 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1536 ArgOffset);
1537
1538 }
1539 else
1540 depth = ArgOffset;
1541
Chris Lattnerc91a4752006-06-26 22:48:35 +00001542 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
Nicolas Geoffray01119992007-04-03 13:59:52 +00001543 depth);
Chris Lattnerc91a4752006-06-26 22:48:35 +00001544 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
Nicolas Geoffray01119992007-04-03 13:59:52 +00001545
Nicolas Geoffray01119992007-04-03 13:59:52 +00001546 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1547 // stored to the VarArgsFrameIndex on the stack.
1548 if (isELF32_ABI) {
1549 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1550 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1551 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1552 MemOps.push_back(Store);
1553 // Increment the address by four for the next argument to store
1554 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1555 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1556 }
1557 }
1558
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001559 // If this function is vararg, store any remaining integer argument regs
1560 // to their spots on the stack so that they may be loaded by deferencing the
1561 // result of va_next.
Chris Lattneraf4ec0c2006-05-16 18:58:15 +00001562 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
Chris Lattnerb1eb9872006-11-18 01:57:19 +00001563 unsigned VReg;
1564 if (isPPC64)
Chris Lattner84bc5422007-12-31 04:13:23 +00001565 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
Chris Lattnerb1eb9872006-11-18 01:57:19 +00001566 else
Chris Lattner84bc5422007-12-31 04:13:23 +00001567 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
Chris Lattnerb1eb9872006-11-18 01:57:19 +00001568
Chris Lattner84bc5422007-12-31 04:13:23 +00001569 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
Chris Lattnerc91a4752006-06-26 22:48:35 +00001570 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
Evan Cheng8b2794a2006-10-13 21:14:26 +00001571 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001572 MemOps.push_back(Store);
1573 // Increment the address by four for the next argument to store
Chris Lattnerc91a4752006-06-26 22:48:35 +00001574 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1575 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001576 }
Nicolas Geoffray01119992007-04-03 13:59:52 +00001577
1578 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1579 // on the stack.
1580 if (isELF32_ABI) {
1581 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1582 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1583 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1584 MemOps.push_back(Store);
1585 // Increment the address by eight for the next argument to store
1586 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1587 PtrVT);
1588 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1589 }
1590
1591 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1592 unsigned VReg;
Chris Lattner84bc5422007-12-31 04:13:23 +00001593 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
Nicolas Geoffray01119992007-04-03 13:59:52 +00001594
Chris Lattner84bc5422007-12-31 04:13:23 +00001595 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
Nicolas Geoffray01119992007-04-03 13:59:52 +00001596 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1597 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1598 MemOps.push_back(Store);
1599 // Increment the address by eight for the next argument to store
1600 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1601 PtrVT);
1602 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1603 }
1604 }
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001605 }
1606
Dale Johannesen8419dd62008-03-07 20:27:40 +00001607 if (!MemOps.empty())
1608 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1609
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001610 ArgValues.push_back(Root);
1611
1612 // Return the new list of results.
1613 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1614 Op.Val->value_end());
Chris Lattner79e490a2006-08-11 17:18:05 +00001615 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001616}
1617
Chris Lattnerc703a8f2006-05-17 19:00:46 +00001618/// isCallCompatibleAddress - Return the immediate to use if the specified
1619/// 32-bit value is representable in the immediate field of a BxA instruction.
1620static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1621 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1622 if (!C) return 0;
1623
1624 int Addr = C->getValue();
1625 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1626 (Addr << 6 >> 6) != Addr)
1627 return 0; // Top 6 bits have to be sext of immediate.
1628
Evan Cheng33118762007-10-22 19:46:19 +00001629 return DAG.getConstant((int)C->getValue() >> 2,
1630 DAG.getTargetLoweringInfo().getPointerTy()).Val;
Chris Lattnerc703a8f2006-05-17 19:00:46 +00001631}
1632
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001633/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1634/// by "Src" to address "Dst" of size "Size". Alignment information is
1635/// specified by the specific parameter attribute. The copy will be passed as
1636/// a byval function parameter.
1637/// Sometimes what we are copying is the end of a larger object, the part that
1638/// does not fit in registers.
1639static SDOperand
1640CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain,
Bill Wendling5f5bf3a2008-03-07 20:49:02 +00001641 unsigned Flags, SelectionDAG &DAG, unsigned Size) {
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001642 unsigned Align = 1 <<
1643 ((Flags & ISD::ParamFlags::ByValAlign) >> ISD::ParamFlags::ByValAlignOffs);
1644 SDOperand AlignNode = DAG.getConstant(Align, MVT::i32);
1645 SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
Dale Johannesen1f797a32008-03-05 23:31:27 +00001646 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i32);
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001647 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, AlignNode, AlwaysInline);
1648}
Chris Lattner9f0bc652007-02-25 05:34:32 +00001649
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001650SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG,
1651 const PPCSubtarget &Subtarget) {
Chris Lattner9f0bc652007-02-25 05:34:32 +00001652 SDOperand Chain = Op.getOperand(0);
1653 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1654 SDOperand Callee = Op.getOperand(4);
1655 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1656
1657 bool isMachoABI = Subtarget.isMachoABI();
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00001658 bool isELF32_ABI = Subtarget.isELF32_ABI();
Evan Cheng4360bdc2006-05-25 00:57:32 +00001659
Chris Lattnerc91a4752006-06-26 22:48:35 +00001660 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1661 bool isPPC64 = PtrVT == MVT::i64;
1662 unsigned PtrByteSize = isPPC64 ? 8 : 4;
Chris Lattnerc91a4752006-06-26 22:48:35 +00001663
Chris Lattnerabde4602006-05-16 22:56:08 +00001664 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1665 // SelectExpr to use to put the arguments in the appropriate registers.
1666 std::vector<SDOperand> args_to_use;
1667
1668 // Count how many bytes are to be pushed on the stack, including the linkage
Chris Lattnerc91a4752006-06-26 22:48:35 +00001669 // area, and parameter passing area. We start with 24/48 bytes, which is
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001670 // prereserved space for [SP][CR][LR][3 x unused].
Chris Lattner9f0bc652007-02-25 05:34:32 +00001671 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
Chris Lattnerabde4602006-05-16 22:56:08 +00001672
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001673 // Add up all the space actually used.
Jim Laskeye9bd7b22006-11-28 14:53:52 +00001674 for (unsigned i = 0; i != NumOps; ++i) {
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001675 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
Jim Laskeye9bd7b22006-11-28 14:53:52 +00001676 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001677 if (Flags & ISD::ParamFlags::ByVal)
1678 ArgSize = (Flags & ISD::ParamFlags::ByValSize) >>
1679 ISD::ParamFlags::ByValSizeOffs;
Jim Laskeye9bd7b22006-11-28 14:53:52 +00001680 ArgSize = std::max(ArgSize, PtrByteSize);
1681 NumBytes += ArgSize;
1682 }
Chris Lattnerc04ba7a2006-05-16 23:54:25 +00001683
Chris Lattner7b053502006-05-30 21:21:04 +00001684 // The prolog code of the callee may store up to 8 GPR argument registers to
1685 // the stack, allowing va_start to index over them in memory if its varargs.
1686 // Because we cannot tell if this is needed on the caller side, we have to
1687 // conservatively assume that it is needed. As such, make sure we have at
1688 // least enough stack space for the caller to store the 8 GPRs.
Chris Lattner9f0bc652007-02-25 05:34:32 +00001689 NumBytes = std::max(NumBytes,
1690 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001691
1692 // Adjust the stack pointer for the new arguments...
1693 // These operations are automatically eliminated by the prolog/epilog pass
1694 Chain = DAG.getCALLSEQ_START(Chain,
Chris Lattnerc91a4752006-06-26 22:48:35 +00001695 DAG.getConstant(NumBytes, PtrVT));
Dale Johannesen1f797a32008-03-05 23:31:27 +00001696 SDOperand CallSeqStart = Chain;
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001697
1698 // Set up a copy of the stack pointer for use loading and storing any
1699 // arguments that may not fit in the registers available for argument
1700 // passing.
Chris Lattnerc91a4752006-06-26 22:48:35 +00001701 SDOperand StackPtr;
1702 if (isPPC64)
1703 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
1704 else
1705 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001706
1707 // Figure out which arguments are going to go in registers, and which in
1708 // memory. Also, if this is a vararg function, floating point operations
1709 // must be stored to our stack, and loaded into integer regs as well, if
1710 // any integer regs are available for argument passing.
Chris Lattner9f0bc652007-02-25 05:34:32 +00001711 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
Chris Lattner9a2a4972006-05-17 06:01:33 +00001712 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
Jim Laskey2f616bf2006-11-16 22:43:37 +00001713
Chris Lattnerc91a4752006-06-26 22:48:35 +00001714 static const unsigned GPR_32[] = { // 32-bit registers.
Chris Lattner9a2a4972006-05-17 06:01:33 +00001715 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1716 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1717 };
Chris Lattnerc91a4752006-06-26 22:48:35 +00001718 static const unsigned GPR_64[] = { // 64-bit registers.
1719 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1720 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1721 };
Chris Lattner9f0bc652007-02-25 05:34:32 +00001722 static const unsigned *FPR = GetFPR(Subtarget);
1723
Chris Lattner9a2a4972006-05-17 06:01:33 +00001724 static const unsigned VR[] = {
1725 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1726 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1727 };
Owen Anderson718cb662007-09-07 04:06:50 +00001728 const unsigned NumGPRs = array_lengthof(GPR_32);
Nicolas Geoffrayef3c0302007-04-03 10:27:07 +00001729 const unsigned NumFPRs = isMachoABI ? 13 : 8;
Owen Anderson718cb662007-09-07 04:06:50 +00001730 const unsigned NumVRs = array_lengthof( VR);
Chris Lattner9a2a4972006-05-17 06:01:33 +00001731
Chris Lattnerc91a4752006-06-26 22:48:35 +00001732 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1733
Chris Lattner9a2a4972006-05-17 06:01:33 +00001734 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
Chris Lattnere2199452006-08-11 17:38:39 +00001735 SmallVector<SDOperand, 8> MemOpChains;
Evan Cheng4360bdc2006-05-25 00:57:32 +00001736 for (unsigned i = 0; i != NumOps; ++i) {
Chris Lattner9f0bc652007-02-25 05:34:32 +00001737 bool inMem = false;
Evan Cheng4360bdc2006-05-25 00:57:32 +00001738 SDOperand Arg = Op.getOperand(5+2*i);
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001739 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
1740 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1741 // See if next argument requires stack alignment in ELF
1742 unsigned next = 5+2*(i+1)+1;
1743 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) &&
1744 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) &&
1745 (!(Flags & AlignFlag)));
1746
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001747 // PtrOff will be used to store the current argument to the stack if a
1748 // register cannot be found for it.
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001749 SDOperand PtrOff;
1750
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00001751 // Stack align in ELF 32
1752 if (isELF32_ABI && Expand)
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001753 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
1754 StackPtr.getValueType());
1755 else
1756 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1757
Chris Lattnerc91a4752006-06-26 22:48:35 +00001758 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1759
1760 // On PPC64, promote integers to 64-bit values.
1761 if (isPPC64 && Arg.getValueType() == MVT::i32) {
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001762 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
Chris Lattnerc91a4752006-06-26 22:48:35 +00001763 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1764 }
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001765
1766 // FIXME Elf untested, what are alignment rules?
Dale Johannesen8419dd62008-03-07 20:27:40 +00001767 // FIXME memcpy is used way more than necessary. Correctness first.
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001768 if (Flags & ISD::ParamFlags::ByVal) {
1769 unsigned Size = (Flags & ISD::ParamFlags::ByValSize) >>
1770 ISD::ParamFlags::ByValSizeOffs;
1771 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
Dale Johannesen8419dd62008-03-07 20:27:40 +00001772 if (Size==1 || Size==2) {
1773 // Very small objects are passed right-justified.
1774 // Everything else is passed left-justified.
1775 MVT::ValueType VT = (Size==1) ? MVT::i8 : MVT::i16;
1776 if (GPR_idx != NumGPRs) {
1777 SDOperand Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg,
1778 NULL, 0, VT);
1779 MemOpChains.push_back(Load.getValue(1));
1780 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1781 if (isMachoABI)
1782 ArgOffset += PtrByteSize;
1783 } else {
1784 SDOperand Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
1785 SDOperand AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const);
1786 SDOperand MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
1787 CallSeqStart.Val->getOperand(0),
1788 Flags, DAG, Size);
1789 // This must go outside the CALLSEQ_START..END.
1790 SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
1791 CallSeqStart.Val->getOperand(1));
1792 DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
1793 Chain = CallSeqStart = NewCallSeqStart;
1794 ArgOffset += PtrByteSize;
1795 }
1796 continue;
1797 }
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001798 for (unsigned j=0; j<Size; j+=PtrByteSize) {
1799 SDOperand Const = DAG.getConstant(j, PtrOff.getValueType());
1800 SDOperand AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const);
1801 if (GPR_idx != NumGPRs) {
1802 SDOperand Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0);
Dale Johannesen1f797a32008-03-05 23:31:27 +00001803 MemOpChains.push_back(Load.getValue(1));
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001804 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1805 if (isMachoABI)
1806 ArgOffset += PtrByteSize;
1807 } else {
1808 SDOperand AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const);
Dale Johannesen1f797a32008-03-05 23:31:27 +00001809 SDOperand MemcpyCall = CreateCopyOfByValArgument(AddArg, AddPtr,
1810 CallSeqStart.Val->getOperand(0),
1811 Flags, DAG, Size - j);
1812 // This must go outside the CALLSEQ_START..END.
1813 SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
1814 CallSeqStart.Val->getOperand(1));
1815 DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
Dale Johannesen8419dd62008-03-07 20:27:40 +00001816 Chain = CallSeqStart = NewCallSeqStart;
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001817 ArgOffset += ((Size - j + 3)/4)*4;
Dale Johannesen8419dd62008-03-07 20:27:40 +00001818 break;
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001819 }
1820 }
1821 continue;
1822 }
1823
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001824 switch (Arg.getValueType()) {
1825 default: assert(0 && "Unexpected ValueType for argument!");
1826 case MVT::i32:
Chris Lattnerc91a4752006-06-26 22:48:35 +00001827 case MVT::i64:
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001828 // Double word align in ELF
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00001829 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
Chris Lattner9a2a4972006-05-17 06:01:33 +00001830 if (GPR_idx != NumGPRs) {
1831 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001832 } else {
Evan Cheng8b2794a2006-10-13 21:14:26 +00001833 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
Chris Lattner9f0bc652007-02-25 05:34:32 +00001834 inMem = true;
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001835 }
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001836 if (inMem || isMachoABI) {
1837 // Stack align in ELF
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00001838 if (isELF32_ABI && Expand)
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001839 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1840
1841 ArgOffset += PtrByteSize;
1842 }
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001843 break;
1844 case MVT::f32:
1845 case MVT::f64:
Chris Lattner4ddf7a42007-02-25 20:01:40 +00001846 if (isVarArg) {
Jim Laskeyfbb74e62006-12-01 16:30:47 +00001847 // Float varargs need to be promoted to double.
1848 if (Arg.getValueType() == MVT::f32)
1849 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
1850 }
1851
Chris Lattner9a2a4972006-05-17 06:01:33 +00001852 if (FPR_idx != NumFPRs) {
1853 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1854
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001855 if (isVarArg) {
Evan Cheng8b2794a2006-10-13 21:14:26 +00001856 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
Chris Lattner9a2a4972006-05-17 06:01:33 +00001857 MemOpChains.push_back(Store);
1858
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001859 // Float varargs are always shadowed in available integer registers
Chris Lattner9a2a4972006-05-17 06:01:33 +00001860 if (GPR_idx != NumGPRs) {
Evan Cheng466685d2006-10-09 20:57:25 +00001861 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
Chris Lattner9a2a4972006-05-17 06:01:33 +00001862 MemOpChains.push_back(Load.getValue(1));
Chris Lattner9f0bc652007-02-25 05:34:32 +00001863 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1864 Load));
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001865 }
Jim Laskeyfbb74e62006-12-01 16:30:47 +00001866 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001867 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
Chris Lattnerc91a4752006-06-26 22:48:35 +00001868 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
Evan Cheng466685d2006-10-09 20:57:25 +00001869 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
Chris Lattner9a2a4972006-05-17 06:01:33 +00001870 MemOpChains.push_back(Load.getValue(1));
Chris Lattner9f0bc652007-02-25 05:34:32 +00001871 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1872 Load));
Chris Lattnerabde4602006-05-16 22:56:08 +00001873 }
1874 } else {
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001875 // If we have any FPRs remaining, we may also have GPRs remaining.
1876 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1877 // GPRs.
Chris Lattner9f0bc652007-02-25 05:34:32 +00001878 if (isMachoABI) {
1879 if (GPR_idx != NumGPRs)
1880 ++GPR_idx;
1881 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
1882 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
1883 ++GPR_idx;
1884 }
Chris Lattnerabde4602006-05-16 22:56:08 +00001885 }
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001886 } else {
Evan Cheng8b2794a2006-10-13 21:14:26 +00001887 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
Chris Lattner9f0bc652007-02-25 05:34:32 +00001888 inMem = true;
Chris Lattnerabde4602006-05-16 22:56:08 +00001889 }
Chris Lattner9f0bc652007-02-25 05:34:32 +00001890 if (inMem || isMachoABI) {
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001891 // Stack align in ELF
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00001892 if (isELF32_ABI && Expand)
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001893 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
Chris Lattner9f0bc652007-02-25 05:34:32 +00001894 if (isPPC64)
1895 ArgOffset += 8;
1896 else
1897 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1898 }
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001899 break;
1900 case MVT::v4f32:
1901 case MVT::v4i32:
1902 case MVT::v8i16:
1903 case MVT::v16i8:
1904 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
Chris Lattner9a2a4972006-05-17 06:01:33 +00001905 assert(VR_idx != NumVRs &&
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001906 "Don't support passing more than 12 vector args yet!");
Chris Lattner9a2a4972006-05-17 06:01:33 +00001907 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001908 break;
Chris Lattnerabde4602006-05-16 22:56:08 +00001909 }
Chris Lattnerabde4602006-05-16 22:56:08 +00001910 }
Chris Lattner9a2a4972006-05-17 06:01:33 +00001911 if (!MemOpChains.empty())
Chris Lattnere2199452006-08-11 17:38:39 +00001912 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1913 &MemOpChains[0], MemOpChains.size());
Chris Lattnerabde4602006-05-16 22:56:08 +00001914
Chris Lattner9a2a4972006-05-17 06:01:33 +00001915 // Build a sequence of copy-to-reg nodes chained together with token chain
1916 // and flag operands which copy the outgoing args into the appropriate regs.
1917 SDOperand InFlag;
1918 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1919 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1920 InFlag);
1921 InFlag = Chain.getValue(1);
1922 }
Chris Lattner9f0bc652007-02-25 05:34:32 +00001923
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00001924 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
1925 if (isVarArg && isELF32_ABI) {
Chris Lattner9f0bc652007-02-25 05:34:32 +00001926 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0);
1927 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag);
1928 InFlag = Chain.getValue(1);
1929 }
1930
Chris Lattnerc703a8f2006-05-17 19:00:46 +00001931 std::vector<MVT::ValueType> NodeTys;
Chris Lattner4a45abf2006-06-10 01:14:28 +00001932 NodeTys.push_back(MVT::Other); // Returns a chain
1933 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1934
Chris Lattner79e490a2006-08-11 17:18:05 +00001935 SmallVector<SDOperand, 8> Ops;
Nicolas Geoffray63f8fb12007-02-27 13:01:19 +00001936 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
Chris Lattnerc703a8f2006-05-17 19:00:46 +00001937
1938 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1939 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1940 // node so that legalize doesn't hack it.
Nicolas Geoffray5a6c91a2007-12-21 12:22:29 +00001941 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1942 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1943 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
Chris Lattnerc703a8f2006-05-17 19:00:46 +00001944 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1945 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1946 // If this is an absolute destination address, use the munged value.
1947 Callee = SDOperand(Dest, 0);
1948 else {
1949 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1950 // to do the call, we can't use PPCISD::CALL.
Chris Lattner79e490a2006-08-11 17:18:05 +00001951 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1952 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
Chris Lattnerc703a8f2006-05-17 19:00:46 +00001953 InFlag = Chain.getValue(1);
1954
1955 // Copy the callee address into R12 on darwin.
Chris Lattner9f0bc652007-02-25 05:34:32 +00001956 if (isMachoABI) {
1957 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1958 InFlag = Chain.getValue(1);
1959 }
Chris Lattnerc703a8f2006-05-17 19:00:46 +00001960
1961 NodeTys.clear();
1962 NodeTys.push_back(MVT::Other);
1963 NodeTys.push_back(MVT::Flag);
Chris Lattnerc703a8f2006-05-17 19:00:46 +00001964 Ops.push_back(Chain);
Chris Lattner9f0bc652007-02-25 05:34:32 +00001965 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
Chris Lattnerc703a8f2006-05-17 19:00:46 +00001966 Callee.Val = 0;
1967 }
Chris Lattner9a2a4972006-05-17 06:01:33 +00001968
Chris Lattner4a45abf2006-06-10 01:14:28 +00001969 // If this is a direct call, pass the chain and the callee.
Chris Lattnerc703a8f2006-05-17 19:00:46 +00001970 if (Callee.Val) {
Chris Lattnerc703a8f2006-05-17 19:00:46 +00001971 Ops.push_back(Chain);
1972 Ops.push_back(Callee);
Chris Lattnerc703a8f2006-05-17 19:00:46 +00001973 }
Chris Lattnerabde4602006-05-16 22:56:08 +00001974
Chris Lattner4a45abf2006-06-10 01:14:28 +00001975 // Add argument registers to the end of the list so that they are known live
1976 // into the call.
1977 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1978 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1979 RegsToPass[i].second.getValueType()));
1980
1981 if (InFlag.Val)
1982 Ops.push_back(InFlag);
Chris Lattner79e490a2006-08-11 17:18:05 +00001983 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
Chris Lattner4a45abf2006-06-10 01:14:28 +00001984 InFlag = Chain.getValue(1);
1985
Bill Wendling0f8d9c02007-11-13 00:44:25 +00001986 Chain = DAG.getCALLSEQ_END(Chain,
1987 DAG.getConstant(NumBytes, PtrVT),
1988 DAG.getConstant(0, PtrVT),
1989 InFlag);
1990 if (Op.Val->getValueType(0) != MVT::Other)
1991 InFlag = Chain.getValue(1);
1992
Chris Lattner79e490a2006-08-11 17:18:05 +00001993 SDOperand ResultVals[3];
1994 unsigned NumResults = 0;
Chris Lattner9a2a4972006-05-17 06:01:33 +00001995 NodeTys.clear();
1996
1997 // If the call has results, copy the values out of the ret val registers.
1998 switch (Op.Val->getValueType(0)) {
1999 default: assert(0 && "Unexpected ret value!");
2000 case MVT::Other: break;
2001 case MVT::i32:
2002 if (Op.Val->getValueType(1) == MVT::i32) {
Dan Gohman532dc2e2007-07-09 20:59:04 +00002003 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
Chris Lattner79e490a2006-08-11 17:18:05 +00002004 ResultVals[0] = Chain.getValue(0);
Dan Gohman532dc2e2007-07-09 20:59:04 +00002005 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32,
Chris Lattner9a2a4972006-05-17 06:01:33 +00002006 Chain.getValue(2)).getValue(1);
Chris Lattner79e490a2006-08-11 17:18:05 +00002007 ResultVals[1] = Chain.getValue(0);
2008 NumResults = 2;
Chris Lattner9a2a4972006-05-17 06:01:33 +00002009 NodeTys.push_back(MVT::i32);
2010 } else {
2011 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
Chris Lattner79e490a2006-08-11 17:18:05 +00002012 ResultVals[0] = Chain.getValue(0);
2013 NumResults = 1;
Chris Lattner9a2a4972006-05-17 06:01:33 +00002014 }
2015 NodeTys.push_back(MVT::i32);
2016 break;
Chris Lattnerc91a4752006-06-26 22:48:35 +00002017 case MVT::i64:
2018 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
Chris Lattner79e490a2006-08-11 17:18:05 +00002019 ResultVals[0] = Chain.getValue(0);
2020 NumResults = 1;
Chris Lattnerc91a4752006-06-26 22:48:35 +00002021 NodeTys.push_back(MVT::i64);
2022 break;
Chris Lattner9a2a4972006-05-17 06:01:33 +00002023 case MVT::f64:
Dale Johannesen161e8972007-10-05 20:04:43 +00002024 if (Op.Val->getValueType(1) == MVT::f64) {
2025 Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1);
2026 ResultVals[0] = Chain.getValue(0);
2027 Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64,
2028 Chain.getValue(2)).getValue(1);
2029 ResultVals[1] = Chain.getValue(0);
2030 NumResults = 2;
2031 NodeTys.push_back(MVT::f64);
2032 NodeTys.push_back(MVT::f64);
2033 break;
2034 }
2035 // else fall through
2036 case MVT::f32:
Chris Lattner9a2a4972006-05-17 06:01:33 +00002037 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
2038 InFlag).getValue(1);
Chris Lattner79e490a2006-08-11 17:18:05 +00002039 ResultVals[0] = Chain.getValue(0);
2040 NumResults = 1;
Chris Lattner9a2a4972006-05-17 06:01:33 +00002041 NodeTys.push_back(Op.Val->getValueType(0));
2042 break;
2043 case MVT::v4f32:
2044 case MVT::v4i32:
2045 case MVT::v8i16:
2046 case MVT::v16i8:
2047 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
2048 InFlag).getValue(1);
Chris Lattner79e490a2006-08-11 17:18:05 +00002049 ResultVals[0] = Chain.getValue(0);
2050 NumResults = 1;
Chris Lattner9a2a4972006-05-17 06:01:33 +00002051 NodeTys.push_back(Op.Val->getValueType(0));
2052 break;
2053 }
2054
Chris Lattner9a2a4972006-05-17 06:01:33 +00002055 NodeTys.push_back(MVT::Other);
Chris Lattnerabde4602006-05-16 22:56:08 +00002056
Chris Lattnerc703a8f2006-05-17 19:00:46 +00002057 // If the function returns void, just return the chain.
Chris Lattnerf6e190f2006-08-12 07:20:05 +00002058 if (NumResults == 0)
Chris Lattnerc703a8f2006-05-17 19:00:46 +00002059 return Chain;
2060
2061 // Otherwise, merge everything together with a MERGE_VALUES node.
Chris Lattner79e490a2006-08-11 17:18:05 +00002062 ResultVals[NumResults++] = Chain;
2063 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
2064 ResultVals, NumResults);
Chris Lattnerabde4602006-05-16 22:56:08 +00002065 return Res.getValue(Op.ResNo);
2066}
2067
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002068SDOperand PPCTargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG,
2069 TargetMachine &TM) {
Chris Lattnerb9a7bea2007-03-06 00:59:59 +00002070 SmallVector<CCValAssign, 16> RVLocs;
2071 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
Chris Lattner52387be2007-06-19 00:13:10 +00002072 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
2073 CCState CCInfo(CC, isVarArg, TM, RVLocs);
Chris Lattnerb9a7bea2007-03-06 00:59:59 +00002074 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
2075
2076 // If this is the first return lowered for this function, add the regs to the
2077 // liveout set for the function.
Chris Lattner84bc5422007-12-31 04:13:23 +00002078 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
Chris Lattnerb9a7bea2007-03-06 00:59:59 +00002079 for (unsigned i = 0; i != RVLocs.size(); ++i)
Chris Lattner84bc5422007-12-31 04:13:23 +00002080 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
Chris Lattnerb9a7bea2007-03-06 00:59:59 +00002081 }
2082
Chris Lattnercaddd442007-02-26 19:44:02 +00002083 SDOperand Chain = Op.getOperand(0);
Chris Lattnerb9a7bea2007-03-06 00:59:59 +00002084 SDOperand Flag;
2085
2086 // Copy the result values into the output registers.
2087 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2088 CCValAssign &VA = RVLocs[i];
2089 assert(VA.isRegLoc() && "Can only return in registers!");
2090 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
2091 Flag = Chain.getValue(1);
2092 }
2093
2094 if (Flag.Val)
2095 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
2096 else
Chris Lattnercaddd442007-02-26 19:44:02 +00002097 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
Chris Lattner1a635d62006-04-14 06:01:58 +00002098}
2099
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002100SDOperand PPCTargetLowering::LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
Jim Laskeyefc7e522006-12-04 22:04:42 +00002101 const PPCSubtarget &Subtarget) {
2102 // When we pop the dynamic allocation we need to restore the SP link.
2103
2104 // Get the corect type for pointers.
2105 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2106
2107 // Construct the stack pointer operand.
2108 bool IsPPC64 = Subtarget.isPPC64();
2109 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
2110 SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
2111
2112 // Get the operands for the STACKRESTORE.
2113 SDOperand Chain = Op.getOperand(0);
2114 SDOperand SaveSP = Op.getOperand(1);
2115
2116 // Load the old link SP.
2117 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
2118
2119 // Restore the stack pointer.
2120 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
2121
2122 // Store the old link SP.
2123 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
2124}
2125
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002126SDOperand PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
2127 SelectionDAG &DAG,
Jim Laskey2f616bf2006-11-16 22:43:37 +00002128 const PPCSubtarget &Subtarget) {
2129 MachineFunction &MF = DAG.getMachineFunction();
2130 bool IsPPC64 = Subtarget.isPPC64();
Chris Lattner9f0bc652007-02-25 05:34:32 +00002131 bool isMachoABI = Subtarget.isMachoABI();
Jim Laskey2f616bf2006-11-16 22:43:37 +00002132
2133 // Get current frame pointer save index. The users of this index will be
2134 // primarily DYNALLOC instructions.
2135 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2136 int FPSI = FI->getFramePointerSaveIndex();
Chris Lattner9f0bc652007-02-25 05:34:32 +00002137
Jim Laskey2f616bf2006-11-16 22:43:37 +00002138 // If the frame pointer save index hasn't been defined yet.
2139 if (!FPSI) {
2140 // Find out what the fix offset of the frame pointer save area.
Chris Lattner9f0bc652007-02-25 05:34:32 +00002141 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
2142
Jim Laskey2f616bf2006-11-16 22:43:37 +00002143 // Allocate the frame index for frame pointer save area.
Chris Lattner9f0bc652007-02-25 05:34:32 +00002144 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
Jim Laskey2f616bf2006-11-16 22:43:37 +00002145 // Save the result.
2146 FI->setFramePointerSaveIndex(FPSI);
2147 }
2148
2149 // Get the inputs.
2150 SDOperand Chain = Op.getOperand(0);
2151 SDOperand Size = Op.getOperand(1);
2152
2153 // Get the corect type for pointers.
2154 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2155 // Negate the size.
2156 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
2157 DAG.getConstant(0, PtrVT), Size);
2158 // Construct a node for the frame pointer save index.
2159 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT);
2160 // Build a DYNALLOC node.
2161 SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
2162 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
2163 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
2164}
2165
2166
Chris Lattner1a635d62006-04-14 06:01:58 +00002167/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
2168/// possible.
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002169SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner1a635d62006-04-14 06:01:58 +00002170 // Not FP? Not a fsel.
2171 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
2172 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
2173 return SDOperand();
2174
2175 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2176
2177 // Cannot handle SETEQ/SETNE.
2178 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
2179
2180 MVT::ValueType ResVT = Op.getValueType();
2181 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
2182 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2183 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
2184
2185 // If the RHS of the comparison is a 0.0, we don't need to do the
2186 // subtraction at all.
2187 if (isFloatingPointZero(RHS))
2188 switch (CC) {
2189 default: break; // SETUO etc aren't handled by fsel.
2190 case ISD::SETULT:
Chris Lattner57340122006-05-24 00:06:44 +00002191 case ISD::SETOLT:
Chris Lattner1a635d62006-04-14 06:01:58 +00002192 case ISD::SETLT:
2193 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2194 case ISD::SETUGE:
Chris Lattner57340122006-05-24 00:06:44 +00002195 case ISD::SETOGE:
Chris Lattner1a635d62006-04-14 06:01:58 +00002196 case ISD::SETGE:
2197 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2198 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2199 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
2200 case ISD::SETUGT:
Chris Lattner57340122006-05-24 00:06:44 +00002201 case ISD::SETOGT:
Chris Lattner1a635d62006-04-14 06:01:58 +00002202 case ISD::SETGT:
2203 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2204 case ISD::SETULE:
Chris Lattner57340122006-05-24 00:06:44 +00002205 case ISD::SETOLE:
Chris Lattner1a635d62006-04-14 06:01:58 +00002206 case ISD::SETLE:
2207 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2208 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2209 return DAG.getNode(PPCISD::FSEL, ResVT,
2210 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
2211 }
2212
Chris Lattner1de7c1d2007-10-15 20:14:52 +00002213 SDOperand Cmp;
Chris Lattner1a635d62006-04-14 06:01:58 +00002214 switch (CC) {
2215 default: break; // SETUO etc aren't handled by fsel.
2216 case ISD::SETULT:
Chris Lattner57340122006-05-24 00:06:44 +00002217 case ISD::SETOLT:
Chris Lattner1a635d62006-04-14 06:01:58 +00002218 case ISD::SETLT:
2219 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2220 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2221 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2222 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2223 case ISD::SETUGE:
Chris Lattner57340122006-05-24 00:06:44 +00002224 case ISD::SETOGE:
Chris Lattner1a635d62006-04-14 06:01:58 +00002225 case ISD::SETGE:
2226 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2227 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2228 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2229 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2230 case ISD::SETUGT:
Chris Lattner57340122006-05-24 00:06:44 +00002231 case ISD::SETOGT:
Chris Lattner1a635d62006-04-14 06:01:58 +00002232 case ISD::SETGT:
2233 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2234 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2235 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2236 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2237 case ISD::SETULE:
Chris Lattner57340122006-05-24 00:06:44 +00002238 case ISD::SETOLE:
Chris Lattner1a635d62006-04-14 06:01:58 +00002239 case ISD::SETLE:
2240 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2241 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2242 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2243 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2244 }
2245 return SDOperand();
2246}
2247
Chris Lattner1f873002007-11-28 18:44:47 +00002248// FIXME: Split this code up when LegalizeDAGTypes lands.
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002249SDOperand PPCTargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner1a635d62006-04-14 06:01:58 +00002250 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
2251 SDOperand Src = Op.getOperand(0);
2252 if (Src.getValueType() == MVT::f32)
2253 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
2254
2255 SDOperand Tmp;
2256 switch (Op.getValueType()) {
2257 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2258 case MVT::i32:
2259 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
2260 break;
2261 case MVT::i64:
2262 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
2263 break;
2264 }
2265
2266 // Convert the FP value to an int value through memory.
Chris Lattner1de7c1d2007-10-15 20:14:52 +00002267 SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64);
2268
2269 // Emit a store to the stack slot.
2270 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0);
2271
2272 // Result is a load from the stack slot. If loading 4 bytes, make sure to
2273 // add in a bias.
Chris Lattner1a635d62006-04-14 06:01:58 +00002274 if (Op.getValueType() == MVT::i32)
Chris Lattner1de7c1d2007-10-15 20:14:52 +00002275 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr,
2276 DAG.getConstant(4, FIPtr.getValueType()));
2277 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0);
Chris Lattner1a635d62006-04-14 06:01:58 +00002278}
2279
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002280SDOperand PPCTargetLowering::LowerFP_ROUND_INREG(SDOperand Op,
2281 SelectionDAG &DAG) {
Dale Johannesen6eaeff22007-10-10 01:01:31 +00002282 assert(Op.getValueType() == MVT::ppcf128);
2283 SDNode *Node = Op.Val;
2284 assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
Chris Lattner26cb2862007-10-19 04:08:28 +00002285 assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR);
Dale Johannesen6eaeff22007-10-10 01:01:31 +00002286 SDOperand Lo = Node->getOperand(0).Val->getOperand(0);
2287 SDOperand Hi = Node->getOperand(0).Val->getOperand(1);
2288
2289 // This sequence changes FPSCR to do round-to-zero, adds the two halves
2290 // of the long double, and puts FPSCR back the way it was. We do not
2291 // actually model FPSCR.
2292 std::vector<MVT::ValueType> NodeTys;
2293 SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg;
2294
2295 NodeTys.push_back(MVT::f64); // Return register
2296 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
2297 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2298 MFFSreg = Result.getValue(0);
2299 InFlag = Result.getValue(1);
2300
2301 NodeTys.clear();
2302 NodeTys.push_back(MVT::Flag); // Returns a flag
2303 Ops[0] = DAG.getConstant(31, MVT::i32);
2304 Ops[1] = InFlag;
2305 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2);
2306 InFlag = Result.getValue(0);
2307
2308 NodeTys.clear();
2309 NodeTys.push_back(MVT::Flag); // Returns a flag
2310 Ops[0] = DAG.getConstant(30, MVT::i32);
2311 Ops[1] = InFlag;
2312 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2);
2313 InFlag = Result.getValue(0);
2314
2315 NodeTys.clear();
2316 NodeTys.push_back(MVT::f64); // result of add
2317 NodeTys.push_back(MVT::Flag); // Returns a flag
2318 Ops[0] = Lo;
2319 Ops[1] = Hi;
2320 Ops[2] = InFlag;
2321 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3);
2322 FPreg = Result.getValue(0);
2323 InFlag = Result.getValue(1);
2324
2325 NodeTys.clear();
2326 NodeTys.push_back(MVT::f64);
2327 Ops[0] = DAG.getConstant(1, MVT::i32);
2328 Ops[1] = MFFSreg;
2329 Ops[2] = FPreg;
2330 Ops[3] = InFlag;
2331 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4);
2332 FPreg = Result.getValue(0);
2333
2334 // We know the low half is about to be thrown away, so just use something
2335 // convenient.
2336 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg);
2337}
2338
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002339SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner1a635d62006-04-14 06:01:58 +00002340 if (Op.getOperand(0).getValueType() == MVT::i64) {
2341 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
2342 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
2343 if (Op.getValueType() == MVT::f32)
Chris Lattner0bd48932008-01-17 07:00:52 +00002344 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
Chris Lattner1a635d62006-04-14 06:01:58 +00002345 return FP;
2346 }
2347
2348 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2349 "Unhandled SINT_TO_FP type in custom expander!");
2350 // Since we only generate this in 64-bit mode, we can take advantage of
2351 // 64-bit registers. In particular, sign extend the input value into the
2352 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2353 // then lfd it and fcfid it.
2354 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2355 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
Chris Lattner0d72a202006-07-28 16:45:47 +00002356 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2357 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
Chris Lattner1a635d62006-04-14 06:01:58 +00002358
2359 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
2360 Op.getOperand(0));
2361
2362 // STD the extended value into the stack slot.
Dan Gohman3069b872008-02-07 18:41:25 +00002363 MemOperand MO(PseudoSourceValue::getFixedStack(),
Dan Gohman69de1932008-02-06 22:27:42 +00002364 MemOperand::MOStore, FrameIdx, 8, 8);
Chris Lattner1a635d62006-04-14 06:01:58 +00002365 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
2366 DAG.getEntryNode(), Ext64, FIdx,
Dan Gohman69de1932008-02-06 22:27:42 +00002367 DAG.getMemOperand(MO));
Chris Lattner1a635d62006-04-14 06:01:58 +00002368 // Load the value as a double.
Evan Cheng466685d2006-10-09 20:57:25 +00002369 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
Chris Lattner1a635d62006-04-14 06:01:58 +00002370
2371 // FCFID it and return it.
2372 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
2373 if (Op.getValueType() == MVT::f32)
Chris Lattner0bd48932008-01-17 07:00:52 +00002374 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
Chris Lattner1a635d62006-04-14 06:01:58 +00002375 return FP;
2376}
2377
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002378SDOperand PPCTargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
Dale Johannesen5c5eb802008-01-18 19:55:37 +00002379 /*
2380 The rounding mode is in bits 30:31 of FPSR, and has the following
2381 settings:
2382 00 Round to nearest
2383 01 Round to 0
2384 10 Round to +inf
2385 11 Round to -inf
2386
2387 FLT_ROUNDS, on the other hand, expects the following:
2388 -1 Undefined
2389 0 Round to 0
2390 1 Round to nearest
2391 2 Round to +inf
2392 3 Round to -inf
2393
2394 To perform the conversion, we do:
2395 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
2396 */
2397
2398 MachineFunction &MF = DAG.getMachineFunction();
2399 MVT::ValueType VT = Op.getValueType();
2400 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2401 std::vector<MVT::ValueType> NodeTys;
2402 SDOperand MFFSreg, InFlag;
2403
2404 // Save FP Control Word to register
2405 NodeTys.push_back(MVT::f64); // return register
2406 NodeTys.push_back(MVT::Flag); // unused in this context
2407 SDOperand Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2408
2409 // Save FP register to stack slot
2410 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
2411 SDOperand StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
2412 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Chain,
2413 StackSlot, NULL, 0);
2414
2415 // Load FP Control Word from low 32 bits of stack slot.
2416 SDOperand Four = DAG.getConstant(4, PtrVT);
2417 SDOperand Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four);
2418 SDOperand CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0);
2419
2420 // Transform as necessary
2421 SDOperand CWD1 =
2422 DAG.getNode(ISD::AND, MVT::i32,
2423 CWD, DAG.getConstant(3, MVT::i32));
2424 SDOperand CWD2 =
2425 DAG.getNode(ISD::SRL, MVT::i32,
2426 DAG.getNode(ISD::AND, MVT::i32,
2427 DAG.getNode(ISD::XOR, MVT::i32,
2428 CWD, DAG.getConstant(3, MVT::i32)),
2429 DAG.getConstant(3, MVT::i32)),
2430 DAG.getConstant(1, MVT::i8));
2431
2432 SDOperand RetVal =
2433 DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2);
2434
2435 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ?
2436 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
2437}
2438
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002439SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
Dan Gohman9ed06db2008-03-07 20:36:53 +00002440 MVT::ValueType VT = Op.getValueType();
2441 unsigned BitWidth = MVT::getSizeInBits(VT);
2442 assert(Op.getNumOperands() == 3 &&
2443 VT == Op.getOperand(1).getValueType() &&
2444 "Unexpected SHL!");
Chris Lattner1a635d62006-04-14 06:01:58 +00002445
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002446 // Expand into a bunch of logical ops. Note that these ops
Chris Lattner1a635d62006-04-14 06:01:58 +00002447 // depend on the PPC behavior for oversized shift amounts.
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002448 SDOperand Lo = Op.getOperand(0);
2449 SDOperand Hi = Op.getOperand(1);
2450 SDOperand Amt = Op.getOperand(2);
Dan Gohman9ed06db2008-03-07 20:36:53 +00002451 MVT::ValueType AmtVT = Amt.getValueType();
Chris Lattner1a635d62006-04-14 06:01:58 +00002452
Dan Gohman9ed06db2008-03-07 20:36:53 +00002453 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
2454 DAG.getConstant(BitWidth, AmtVT), Amt);
2455 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt);
2456 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1);
2457 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
2458 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
2459 DAG.getConstant(-BitWidth, AmtVT));
2460 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5);
2461 SDOperand OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
2462 SDOperand OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt);
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002463 SDOperand OutOps[] = { OutLo, OutHi };
Dan Gohman9ed06db2008-03-07 20:36:53 +00002464 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002465 OutOps, 2);
Chris Lattner1a635d62006-04-14 06:01:58 +00002466}
2467
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002468SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
Dan Gohman9ed06db2008-03-07 20:36:53 +00002469 MVT::ValueType VT = Op.getValueType();
2470 unsigned BitWidth = MVT::getSizeInBits(VT);
2471 assert(Op.getNumOperands() == 3 &&
2472 VT == Op.getOperand(1).getValueType() &&
2473 "Unexpected SRL!");
Chris Lattner1a635d62006-04-14 06:01:58 +00002474
Dan Gohman9ed06db2008-03-07 20:36:53 +00002475 // Expand into a bunch of logical ops. Note that these ops
Chris Lattner1a635d62006-04-14 06:01:58 +00002476 // depend on the PPC behavior for oversized shift amounts.
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002477 SDOperand Lo = Op.getOperand(0);
2478 SDOperand Hi = Op.getOperand(1);
2479 SDOperand Amt = Op.getOperand(2);
Dan Gohman9ed06db2008-03-07 20:36:53 +00002480 MVT::ValueType AmtVT = Amt.getValueType();
Chris Lattner1a635d62006-04-14 06:01:58 +00002481
Dan Gohman9ed06db2008-03-07 20:36:53 +00002482 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
2483 DAG.getConstant(BitWidth, AmtVT), Amt);
2484 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
2485 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
2486 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
2487 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
2488 DAG.getConstant(-BitWidth, AmtVT));
2489 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5);
2490 SDOperand OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
2491 SDOperand OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt);
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002492 SDOperand OutOps[] = { OutLo, OutHi };
Dan Gohman9ed06db2008-03-07 20:36:53 +00002493 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002494 OutOps, 2);
Chris Lattner1a635d62006-04-14 06:01:58 +00002495}
2496
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002497SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
Dan Gohman9ed06db2008-03-07 20:36:53 +00002498 MVT::ValueType VT = Op.getValueType();
2499 unsigned BitWidth = MVT::getSizeInBits(VT);
2500 assert(Op.getNumOperands() == 3 &&
2501 VT == Op.getOperand(1).getValueType() &&
2502 "Unexpected SRA!");
Chris Lattner1a635d62006-04-14 06:01:58 +00002503
Dan Gohman9ed06db2008-03-07 20:36:53 +00002504 // Expand into a bunch of logical ops, followed by a select_cc.
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002505 SDOperand Lo = Op.getOperand(0);
2506 SDOperand Hi = Op.getOperand(1);
2507 SDOperand Amt = Op.getOperand(2);
Dan Gohman9ed06db2008-03-07 20:36:53 +00002508 MVT::ValueType AmtVT = Amt.getValueType();
Chris Lattner1a635d62006-04-14 06:01:58 +00002509
Dan Gohman9ed06db2008-03-07 20:36:53 +00002510 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
2511 DAG.getConstant(BitWidth, AmtVT), Amt);
2512 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
2513 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
2514 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
2515 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
2516 DAG.getConstant(-BitWidth, AmtVT));
2517 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5);
2518 SDOperand OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt);
2519 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT),
Chris Lattner1a635d62006-04-14 06:01:58 +00002520 Tmp4, Tmp6, ISD::SETLE);
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002521 SDOperand OutOps[] = { OutLo, OutHi };
Dan Gohman9ed06db2008-03-07 20:36:53 +00002522 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002523 OutOps, 2);
Chris Lattner1a635d62006-04-14 06:01:58 +00002524}
2525
2526//===----------------------------------------------------------------------===//
2527// Vector related lowering.
2528//
2529
Chris Lattnerac225ca2006-04-12 19:07:14 +00002530// If this is a vector of constants or undefs, get the bits. A bit in
2531// UndefBits is set if the corresponding element of the vector is an
2532// ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2533// zero. Return true if this is not an array of constants, false if it is.
2534//
Chris Lattnerac225ca2006-04-12 19:07:14 +00002535static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
2536 uint64_t UndefBits[2]) {
2537 // Start with zero'd results.
2538 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
2539
2540 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
2541 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2542 SDOperand OpVal = BV->getOperand(i);
2543
2544 unsigned PartNo = i >= e/2; // In the upper 128 bits?
Chris Lattnerb17f1672006-04-16 01:01:29 +00002545 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
Chris Lattnerac225ca2006-04-12 19:07:14 +00002546
2547 uint64_t EltBits = 0;
2548 if (OpVal.getOpcode() == ISD::UNDEF) {
2549 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
2550 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
2551 continue;
2552 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2553 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
2554 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2555 assert(CN->getValueType(0) == MVT::f32 &&
2556 "Only one legal FP vector type!");
Dale Johanneseneaf08942007-08-31 04:03:46 +00002557 EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
Chris Lattnerac225ca2006-04-12 19:07:14 +00002558 } else {
2559 // Nonconstant element.
2560 return true;
2561 }
2562
2563 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
2564 }
2565
2566 //printf("%llx %llx %llx %llx\n",
2567 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
2568 return false;
2569}
Chris Lattneref819f82006-03-20 06:33:01 +00002570
Chris Lattnerb17f1672006-04-16 01:01:29 +00002571// If this is a splat (repetition) of a value across the whole vector, return
2572// the smallest size that splats it. For example, "0x01010101010101..." is a
2573// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2574// SplatSize = 1 byte.
2575static bool isConstantSplat(const uint64_t Bits128[2],
2576 const uint64_t Undef128[2],
2577 unsigned &SplatBits, unsigned &SplatUndef,
2578 unsigned &SplatSize) {
2579
2580 // Don't let undefs prevent splats from matching. See if the top 64-bits are
2581 // the same as the lower 64-bits, ignoring undefs.
2582 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
2583 return false; // Can't be a splat if two pieces don't match.
2584
2585 uint64_t Bits64 = Bits128[0] | Bits128[1];
2586 uint64_t Undef64 = Undef128[0] & Undef128[1];
2587
2588 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
2589 // undefs.
2590 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
2591 return false; // Can't be a splat if two pieces don't match.
2592
2593 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
2594 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
2595
2596 // If the top 16-bits are different than the lower 16-bits, ignoring
2597 // undefs, we have an i32 splat.
2598 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
2599 SplatBits = Bits32;
2600 SplatUndef = Undef32;
2601 SplatSize = 4;
2602 return true;
2603 }
2604
2605 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
2606 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
2607
2608 // If the top 8-bits are different than the lower 8-bits, ignoring
2609 // undefs, we have an i16 splat.
2610 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
2611 SplatBits = Bits16;
2612 SplatUndef = Undef16;
2613 SplatSize = 2;
2614 return true;
2615 }
2616
2617 // Otherwise, we have an 8-bit splat.
2618 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
2619 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
2620 SplatSize = 1;
2621 return true;
2622}
2623
Chris Lattner4a998b92006-04-17 06:00:21 +00002624/// BuildSplatI - Build a canonical splati of Val with an element size of
2625/// SplatSize. Cast the result to VT.
2626static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
2627 SelectionDAG &DAG) {
2628 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
Chris Lattner70fa4932006-12-01 01:45:39 +00002629
Chris Lattner4a998b92006-04-17 06:00:21 +00002630 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
2631 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
2632 };
Chris Lattner70fa4932006-12-01 01:45:39 +00002633
2634 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
2635
2636 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
2637 if (Val == -1)
2638 SplatSize = 1;
2639
Chris Lattner4a998b92006-04-17 06:00:21 +00002640 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
2641
2642 // Build a canonical splat for this value.
Dan Gohman51eaa862007-06-14 22:58:02 +00002643 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT));
Chris Lattnere2199452006-08-11 17:38:39 +00002644 SmallVector<SDOperand, 8> Ops;
2645 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
2646 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
2647 &Ops[0], Ops.size());
Chris Lattner70fa4932006-12-01 01:45:39 +00002648 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
Chris Lattner4a998b92006-04-17 06:00:21 +00002649}
2650
Chris Lattnere7c768e2006-04-18 03:24:30 +00002651/// BuildIntrinsicOp - Return a binary operator intrinsic node with the
Chris Lattner6876e662006-04-17 06:58:41 +00002652/// specified intrinsic ID.
Chris Lattnere7c768e2006-04-18 03:24:30 +00002653static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
2654 SelectionDAG &DAG,
2655 MVT::ValueType DestVT = MVT::Other) {
2656 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
2657 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
Chris Lattner6876e662006-04-17 06:58:41 +00002658 DAG.getConstant(IID, MVT::i32), LHS, RHS);
2659}
2660
Chris Lattnere7c768e2006-04-18 03:24:30 +00002661/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
2662/// specified intrinsic ID.
2663static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
2664 SDOperand Op2, SelectionDAG &DAG,
2665 MVT::ValueType DestVT = MVT::Other) {
2666 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
2667 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2668 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
2669}
2670
2671
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002672/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
2673/// amount. The result has the specified value type.
2674static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
2675 MVT::ValueType VT, SelectionDAG &DAG) {
2676 // Force LHS/RHS to be the right type.
2677 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
2678 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
2679
Chris Lattnere2199452006-08-11 17:38:39 +00002680 SDOperand Ops[16];
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002681 for (unsigned i = 0; i != 16; ++i)
Chris Lattnere2199452006-08-11 17:38:39 +00002682 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002683 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
Chris Lattnere2199452006-08-11 17:38:39 +00002684 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002685 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
2686}
2687
Chris Lattnerf1b47082006-04-14 05:19:18 +00002688// If this is a case we can't handle, return null and let the default
2689// expansion code take care of it. If we CAN select this case, and if it
2690// selects to a single instruction, return Op. Otherwise, if we can codegen
2691// this case more efficiently than a constant pool load, lower it to the
2692// sequence of ops that should be used.
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002693SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op,
2694 SelectionDAG &DAG) {
Chris Lattnerf1b47082006-04-14 05:19:18 +00002695 // If this is a vector of constants or undefs, get the bits. A bit in
2696 // UndefBits is set if the corresponding element of the vector is an
2697 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2698 // zero.
2699 uint64_t VectorBits[2];
2700 uint64_t UndefBits[2];
2701 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
2702 return SDOperand(); // Not a constant vector.
2703
Chris Lattnerb17f1672006-04-16 01:01:29 +00002704 // If this is a splat (repetition) of a value across the whole vector, return
2705 // the smallest size that splats it. For example, "0x01010101010101..." is a
2706 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2707 // SplatSize = 1 byte.
2708 unsigned SplatBits, SplatUndef, SplatSize;
2709 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
2710 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
2711
2712 // First, handle single instruction cases.
2713
2714 // All zeros?
2715 if (SplatBits == 0) {
2716 // Canonicalize all zero vectors to be v4i32.
2717 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
2718 SDOperand Z = DAG.getConstant(0, MVT::i32);
2719 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
2720 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
2721 }
2722 return Op;
Chris Lattnerf1b47082006-04-14 05:19:18 +00002723 }
Chris Lattnerb17f1672006-04-16 01:01:29 +00002724
2725 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
2726 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
Chris Lattner4a998b92006-04-17 06:00:21 +00002727 if (SextVal >= -16 && SextVal <= 15)
2728 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
Chris Lattnerb17f1672006-04-16 01:01:29 +00002729
Chris Lattnerdbce85d2006-04-17 18:09:22 +00002730
2731 // Two instruction sequences.
2732
Chris Lattner4a998b92006-04-17 06:00:21 +00002733 // If this value is in the range [-32,30] and is even, use:
2734 // tmp = VSPLTI[bhw], result = add tmp, tmp
2735 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
2736 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
2737 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
2738 }
Chris Lattner6876e662006-04-17 06:58:41 +00002739
2740 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
2741 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
2742 // for fneg/fabs.
2743 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
2744 // Make -1 and vspltisw -1:
2745 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
2746
2747 // Make the VSLW intrinsic, computing 0x8000_0000.
Chris Lattnere7c768e2006-04-18 03:24:30 +00002748 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
2749 OnesV, DAG);
Chris Lattner6876e662006-04-17 06:58:41 +00002750
2751 // xor by OnesV to invert it.
2752 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
2753 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2754 }
2755
2756 // Check to see if this is a wide variety of vsplti*, binop self cases.
2757 unsigned SplatBitSize = SplatSize*8;
Lauro Ramos Venancio1baa1972007-03-27 16:33:08 +00002758 static const signed char SplatCsts[] = {
Chris Lattner6876e662006-04-17 06:58:41 +00002759 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
Chris Lattnerdbce85d2006-04-17 18:09:22 +00002760 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
Chris Lattner6876e662006-04-17 06:58:41 +00002761 };
Chris Lattner15eb3292006-11-29 19:58:49 +00002762
Owen Anderson718cb662007-09-07 04:06:50 +00002763 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
Chris Lattner6876e662006-04-17 06:58:41 +00002764 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
2765 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
2766 int i = SplatCsts[idx];
2767
2768 // Figure out what shift amount will be used by altivec if shifted by i in
2769 // this splat size.
2770 unsigned TypeShiftAmt = i & (SplatBitSize-1);
2771
2772 // vsplti + shl self.
2773 if (SextVal == (i << (int)TypeShiftAmt)) {
Chris Lattner15eb3292006-11-29 19:58:49 +00002774 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
Chris Lattner6876e662006-04-17 06:58:41 +00002775 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2776 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
2777 Intrinsic::ppc_altivec_vslw
2778 };
Chris Lattner15eb3292006-11-29 19:58:49 +00002779 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2780 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
Chris Lattner6876e662006-04-17 06:58:41 +00002781 }
2782
2783 // vsplti + srl self.
2784 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
Chris Lattner15eb3292006-11-29 19:58:49 +00002785 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
Chris Lattner6876e662006-04-17 06:58:41 +00002786 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2787 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
2788 Intrinsic::ppc_altivec_vsrw
2789 };
Chris Lattner15eb3292006-11-29 19:58:49 +00002790 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2791 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
Chris Lattner6876e662006-04-17 06:58:41 +00002792 }
2793
2794 // vsplti + sra self.
2795 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
Chris Lattner15eb3292006-11-29 19:58:49 +00002796 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
Chris Lattner6876e662006-04-17 06:58:41 +00002797 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2798 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
2799 Intrinsic::ppc_altivec_vsraw
2800 };
Chris Lattner15eb3292006-11-29 19:58:49 +00002801 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2802 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
Chris Lattner6876e662006-04-17 06:58:41 +00002803 }
2804
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002805 // vsplti + rol self.
2806 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
2807 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
Chris Lattner15eb3292006-11-29 19:58:49 +00002808 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002809 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2810 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
2811 Intrinsic::ppc_altivec_vrlw
2812 };
Chris Lattner15eb3292006-11-29 19:58:49 +00002813 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2814 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002815 }
2816
2817 // t = vsplti c, result = vsldoi t, t, 1
2818 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
2819 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2820 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
2821 }
2822 // t = vsplti c, result = vsldoi t, t, 2
2823 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
2824 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2825 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
2826 }
2827 // t = vsplti c, result = vsldoi t, t, 3
2828 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
2829 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2830 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
2831 }
Chris Lattner6876e662006-04-17 06:58:41 +00002832 }
2833
Chris Lattner6876e662006-04-17 06:58:41 +00002834 // Three instruction sequences.
2835
Chris Lattnerdbce85d2006-04-17 18:09:22 +00002836 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
2837 if (SextVal >= 0 && SextVal <= 31) {
Chris Lattner15eb3292006-11-29 19:58:49 +00002838 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
2839 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
Dale Johannesen296c1762007-10-14 01:58:32 +00002840 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS);
Chris Lattner15eb3292006-11-29 19:58:49 +00002841 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
Chris Lattnerdbce85d2006-04-17 18:09:22 +00002842 }
2843 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
2844 if (SextVal >= -31 && SextVal <= 0) {
Chris Lattner15eb3292006-11-29 19:58:49 +00002845 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
2846 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
Dale Johannesen296c1762007-10-14 01:58:32 +00002847 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
Chris Lattner15eb3292006-11-29 19:58:49 +00002848 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
Chris Lattnerf1b47082006-04-14 05:19:18 +00002849 }
2850 }
Chris Lattnerb17f1672006-04-16 01:01:29 +00002851
Chris Lattnerf1b47082006-04-14 05:19:18 +00002852 return SDOperand();
2853}
2854
Chris Lattner59138102006-04-17 05:28:54 +00002855/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2856/// the specified operations to build the shuffle.
2857static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
2858 SDOperand RHS, SelectionDAG &DAG) {
2859 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2860 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2861 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2862
2863 enum {
Chris Lattner00402c72006-05-16 04:20:24 +00002864 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
Chris Lattner59138102006-04-17 05:28:54 +00002865 OP_VMRGHW,
2866 OP_VMRGLW,
2867 OP_VSPLTISW0,
2868 OP_VSPLTISW1,
2869 OP_VSPLTISW2,
2870 OP_VSPLTISW3,
2871 OP_VSLDOI4,
2872 OP_VSLDOI8,
Chris Lattnerd74ea2b2006-05-24 17:04:05 +00002873 OP_VSLDOI12
Chris Lattner59138102006-04-17 05:28:54 +00002874 };
2875
2876 if (OpNum == OP_COPY) {
2877 if (LHSID == (1*9+2)*9+3) return LHS;
2878 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2879 return RHS;
2880 }
2881
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002882 SDOperand OpLHS, OpRHS;
2883 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
2884 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
2885
Chris Lattner59138102006-04-17 05:28:54 +00002886 unsigned ShufIdxs[16];
2887 switch (OpNum) {
2888 default: assert(0 && "Unknown i32 permute!");
2889 case OP_VMRGHW:
2890 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
2891 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
2892 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
2893 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
2894 break;
2895 case OP_VMRGLW:
2896 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
2897 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
2898 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
2899 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
2900 break;
2901 case OP_VSPLTISW0:
2902 for (unsigned i = 0; i != 16; ++i)
2903 ShufIdxs[i] = (i&3)+0;
2904 break;
2905 case OP_VSPLTISW1:
2906 for (unsigned i = 0; i != 16; ++i)
2907 ShufIdxs[i] = (i&3)+4;
2908 break;
2909 case OP_VSPLTISW2:
2910 for (unsigned i = 0; i != 16; ++i)
2911 ShufIdxs[i] = (i&3)+8;
2912 break;
2913 case OP_VSPLTISW3:
2914 for (unsigned i = 0; i != 16; ++i)
2915 ShufIdxs[i] = (i&3)+12;
2916 break;
2917 case OP_VSLDOI4:
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002918 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
Chris Lattner59138102006-04-17 05:28:54 +00002919 case OP_VSLDOI8:
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002920 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
Chris Lattner59138102006-04-17 05:28:54 +00002921 case OP_VSLDOI12:
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002922 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
Chris Lattner59138102006-04-17 05:28:54 +00002923 }
Chris Lattnere2199452006-08-11 17:38:39 +00002924 SDOperand Ops[16];
Chris Lattner59138102006-04-17 05:28:54 +00002925 for (unsigned i = 0; i != 16; ++i)
Chris Lattnere2199452006-08-11 17:38:39 +00002926 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
Chris Lattner59138102006-04-17 05:28:54 +00002927
2928 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
Chris Lattnere2199452006-08-11 17:38:39 +00002929 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
Chris Lattner59138102006-04-17 05:28:54 +00002930}
2931
Chris Lattnerf1b47082006-04-14 05:19:18 +00002932/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
2933/// is a shuffle we can handle in a single instruction, return it. Otherwise,
2934/// return the code it can be lowered into. Worst case, it can always be
2935/// lowered into a vperm.
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002936SDOperand PPCTargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op,
2937 SelectionDAG &DAG) {
Chris Lattnerf1b47082006-04-14 05:19:18 +00002938 SDOperand V1 = Op.getOperand(0);
2939 SDOperand V2 = Op.getOperand(1);
2940 SDOperand PermMask = Op.getOperand(2);
2941
2942 // Cases that are handled by instructions that take permute immediates
2943 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
2944 // selected by the instruction selector.
2945 if (V2.getOpcode() == ISD::UNDEF) {
2946 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
2947 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
2948 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
2949 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
2950 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
2951 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
2952 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
2953 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
2954 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
2955 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
2956 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
2957 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
2958 return Op;
2959 }
2960 }
2961
2962 // Altivec has a variety of "shuffle immediates" that take two vector inputs
2963 // and produce a fixed permutation. If any of these match, do not lower to
2964 // VPERM.
2965 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
2966 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
2967 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
2968 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
2969 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
2970 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
2971 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
2972 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
2973 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
2974 return Op;
2975
Chris Lattner59138102006-04-17 05:28:54 +00002976 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
2977 // perfect shuffle table to emit an optimal matching sequence.
2978 unsigned PFIndexes[4];
2979 bool isFourElementShuffle = true;
2980 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
2981 unsigned EltNo = 8; // Start out undef.
2982 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
2983 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
2984 continue; // Undef, ignore it.
2985
2986 unsigned ByteSource =
2987 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
2988 if ((ByteSource & 3) != j) {
2989 isFourElementShuffle = false;
2990 break;
2991 }
2992
2993 if (EltNo == 8) {
2994 EltNo = ByteSource/4;
2995 } else if (EltNo != ByteSource/4) {
2996 isFourElementShuffle = false;
2997 break;
2998 }
2999 }
3000 PFIndexes[i] = EltNo;
3001 }
3002
3003 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
3004 // perfect shuffle vector to determine if it is cost effective to do this as
3005 // discrete instructions, or whether we should use a vperm.
3006 if (isFourElementShuffle) {
3007 // Compute the index in the perfect shuffle table.
3008 unsigned PFTableIndex =
3009 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3010
3011 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3012 unsigned Cost = (PFEntry >> 30);
3013
3014 // Determining when to avoid vperm is tricky. Many things affect the cost
3015 // of vperm, particularly how many times the perm mask needs to be computed.
3016 // For example, if the perm mask can be hoisted out of a loop or is already
3017 // used (perhaps because there are multiple permutes with the same shuffle
3018 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
3019 // the loop requires an extra register.
3020 //
3021 // As a compromise, we only emit discrete instructions if the shuffle can be
3022 // generated in 3 or fewer operations. When we have loop information
3023 // available, if this block is within a loop, we should avoid using vperm
3024 // for 3-operation perms and use a constant pool load instead.
3025 if (Cost < 3)
3026 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
3027 }
Chris Lattnerf1b47082006-04-14 05:19:18 +00003028
3029 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
3030 // vector that will get spilled to the constant pool.
3031 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
3032
3033 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
3034 // that it is in input element units, not in bytes. Convert now.
Dan Gohman51eaa862007-06-14 22:58:02 +00003035 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
Chris Lattnerf1b47082006-04-14 05:19:18 +00003036 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
3037
Chris Lattnere2199452006-08-11 17:38:39 +00003038 SmallVector<SDOperand, 16> ResultMask;
Chris Lattnerf1b47082006-04-14 05:19:18 +00003039 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
Chris Lattner730b4562006-04-15 23:48:05 +00003040 unsigned SrcElt;
3041 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
3042 SrcElt = 0;
3043 else
3044 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
Chris Lattnerf1b47082006-04-14 05:19:18 +00003045
3046 for (unsigned j = 0; j != BytesPerElement; ++j)
3047 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
3048 MVT::i8));
3049 }
3050
Chris Lattnere2199452006-08-11 17:38:39 +00003051 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
3052 &ResultMask[0], ResultMask.size());
Chris Lattnerf1b47082006-04-14 05:19:18 +00003053 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
3054}
3055
Chris Lattner90564f22006-04-18 17:59:36 +00003056/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
3057/// altivec comparison. If it is, return true and fill in Opc/isDot with
3058/// information about the intrinsic.
3059static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
3060 bool &isDot) {
3061 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
3062 CompareOpc = -1;
3063 isDot = false;
3064 switch (IntrinsicID) {
3065 default: return false;
3066 // Comparison predicates.
Chris Lattner1a635d62006-04-14 06:01:58 +00003067 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
3068 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
3069 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
3070 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
3071 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
3072 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
3073 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
3074 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
3075 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
3076 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
3077 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
3078 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
3079 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
3080
3081 // Normal Comparisons.
3082 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
3083 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
3084 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
3085 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
3086 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
3087 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
3088 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
3089 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
3090 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
3091 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
3092 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
3093 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
3094 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
3095 }
Chris Lattner90564f22006-04-18 17:59:36 +00003096 return true;
3097}
3098
3099/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
3100/// lower, do it, otherwise return null.
Dale Johannesen5b3b6952008-03-04 23:17:14 +00003101SDOperand PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op,
3102 SelectionDAG &DAG) {
Chris Lattner90564f22006-04-18 17:59:36 +00003103 // If this is a lowered altivec predicate compare, CompareOpc is set to the
3104 // opcode number of the comparison.
3105 int CompareOpc;
3106 bool isDot;
3107 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
3108 return SDOperand(); // Don't custom lower most intrinsics.
Chris Lattner1a635d62006-04-14 06:01:58 +00003109
Chris Lattner90564f22006-04-18 17:59:36 +00003110 // If this is a non-dot comparison, make the VCMP node and we are done.
Chris Lattner1a635d62006-04-14 06:01:58 +00003111 if (!isDot) {
3112 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
3113 Op.getOperand(1), Op.getOperand(2),
3114 DAG.getConstant(CompareOpc, MVT::i32));
3115 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
3116 }
3117
3118 // Create the PPCISD altivec 'dot' comparison node.
Chris Lattner79e490a2006-08-11 17:18:05 +00003119 SDOperand Ops[] = {
3120 Op.getOperand(2), // LHS
3121 Op.getOperand(3), // RHS
3122 DAG.getConstant(CompareOpc, MVT::i32)
3123 };
Chris Lattner1a635d62006-04-14 06:01:58 +00003124 std::vector<MVT::ValueType> VTs;
Chris Lattner1a635d62006-04-14 06:01:58 +00003125 VTs.push_back(Op.getOperand(2).getValueType());
3126 VTs.push_back(MVT::Flag);
Chris Lattner79e490a2006-08-11 17:18:05 +00003127 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
Chris Lattner1a635d62006-04-14 06:01:58 +00003128
3129 // Now that we have the comparison, emit a copy from the CR to a GPR.
3130 // This is flagged to the above dot comparison.
3131 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
3132 DAG.getRegister(PPC::CR6, MVT::i32),
3133 CompNode.getValue(1));
3134
3135 // Unpack the result based on how the target uses it.
3136 unsigned BitNo; // Bit # of CR6.
3137 bool InvertBit; // Invert result?
3138 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
3139 default: // Can't happen, don't crash on invalid number though.
3140 case 0: // Return the value of the EQ bit of CR6.
3141 BitNo = 0; InvertBit = false;
3142 break;
3143 case 1: // Return the inverted value of the EQ bit of CR6.
3144 BitNo = 0; InvertBit = true;
3145 break;
3146 case 2: // Return the value of the LT bit of CR6.
3147 BitNo = 2; InvertBit = false;
3148 break;
3149 case 3: // Return the inverted value of the LT bit of CR6.
3150 BitNo = 2; InvertBit = true;
3151 break;
3152 }
3153
3154 // Shift the bit into the low position.
3155 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
3156 DAG.getConstant(8-(3-BitNo), MVT::i32));
3157 // Isolate the bit.
3158 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
3159 DAG.getConstant(1, MVT::i32));
3160
3161 // If we are supposed to, toggle the bit.
3162 if (InvertBit)
3163 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
3164 DAG.getConstant(1, MVT::i32));
3165 return Flags;
3166}
3167
Dale Johannesen5b3b6952008-03-04 23:17:14 +00003168SDOperand PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op,
3169 SelectionDAG &DAG) {
Chris Lattner1a635d62006-04-14 06:01:58 +00003170 // Create a stack slot that is 16-byte aligned.
3171 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3172 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
Chris Lattner0d72a202006-07-28 16:45:47 +00003173 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3174 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
Chris Lattner1a635d62006-04-14 06:01:58 +00003175
3176 // Store the input value into Value#0 of the stack slot.
Evan Cheng786225a2006-10-05 23:01:46 +00003177 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
Evan Cheng8b2794a2006-10-13 21:14:26 +00003178 Op.getOperand(0), FIdx, NULL, 0);
Chris Lattner1a635d62006-04-14 06:01:58 +00003179 // Load it out.
Evan Cheng466685d2006-10-09 20:57:25 +00003180 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
Chris Lattner1a635d62006-04-14 06:01:58 +00003181}
3182
Dale Johannesen5b3b6952008-03-04 23:17:14 +00003183SDOperand PPCTargetLowering::LowerMUL(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner72dd9bd2006-04-18 03:43:48 +00003184 if (Op.getValueType() == MVT::v4i32) {
3185 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3186
3187 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
3188 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
3189
3190 SDOperand RHSSwap = // = vrlw RHS, 16
3191 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
3192
3193 // Shrinkify inputs to v8i16.
3194 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
3195 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
3196 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
3197
3198 // Low parts multiplied together, generating 32-bit results (we ignore the
3199 // top parts).
3200 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
3201 LHS, RHS, DAG, MVT::v4i32);
3202
3203 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
3204 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
3205 // Shift the high parts up 16 bits.
3206 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
3207 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
3208 } else if (Op.getValueType() == MVT::v8i16) {
3209 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3210
Chris Lattnercea2aa72006-04-18 04:28:57 +00003211 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
Chris Lattner72dd9bd2006-04-18 03:43:48 +00003212
Chris Lattnercea2aa72006-04-18 04:28:57 +00003213 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
3214 LHS, RHS, Zero, DAG);
Chris Lattner19a81522006-04-18 03:57:35 +00003215 } else if (Op.getValueType() == MVT::v16i8) {
3216 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3217
3218 // Multiply the even 8-bit parts, producing 16-bit sums.
3219 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
3220 LHS, RHS, DAG, MVT::v8i16);
3221 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
3222
3223 // Multiply the odd 8-bit parts, producing 16-bit sums.
3224 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
3225 LHS, RHS, DAG, MVT::v8i16);
3226 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
3227
3228 // Merge the results together.
Chris Lattnere2199452006-08-11 17:38:39 +00003229 SDOperand Ops[16];
Chris Lattner19a81522006-04-18 03:57:35 +00003230 for (unsigned i = 0; i != 8; ++i) {
Chris Lattnere2199452006-08-11 17:38:39 +00003231 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
3232 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
Chris Lattner19a81522006-04-18 03:57:35 +00003233 }
Chris Lattner19a81522006-04-18 03:57:35 +00003234 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
Chris Lattnere2199452006-08-11 17:38:39 +00003235 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
Chris Lattner72dd9bd2006-04-18 03:43:48 +00003236 } else {
3237 assert(0 && "Unknown mul to lower!");
3238 abort();
3239 }
Chris Lattnere7c768e2006-04-18 03:24:30 +00003240}
3241
Chris Lattnere4bc9ea2005-08-26 00:52:45 +00003242/// LowerOperation - Provide custom lowering hooks for some operations.
3243///
Nate Begeman21e463b2005-10-16 05:39:50 +00003244SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
Chris Lattnere4bc9ea2005-08-26 00:52:45 +00003245 switch (Op.getOpcode()) {
3246 default: assert(0 && "Wasn't expecting to be able to lower this!");
Chris Lattner1a635d62006-04-14 06:01:58 +00003247 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3248 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
Lauro Ramos Venancio75ce0102007-07-11 17:19:51 +00003249 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
Nate Begeman37efe672006-04-22 18:53:45 +00003250 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
Chris Lattner1a635d62006-04-14 06:01:58 +00003251 case ISD::SETCC: return LowerSETCC(Op, DAG);
Nicolas Geoffray01119992007-04-03 13:59:52 +00003252 case ISD::VASTART:
3253 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3254 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3255
3256 case ISD::VAARG:
3257 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3258 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3259
Chris Lattneref957102006-06-21 00:34:03 +00003260 case ISD::FORMAL_ARGUMENTS:
Nicolas Geoffray01119992007-04-03 13:59:52 +00003261 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
3262 VarArgsStackOffset, VarArgsNumGPR,
3263 VarArgsNumFPR, PPCSubTarget);
3264
Chris Lattner9f0bc652007-02-25 05:34:32 +00003265 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget);
Chris Lattnerb9a7bea2007-03-06 00:59:59 +00003266 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
Jim Laskeyefc7e522006-12-04 22:04:42 +00003267 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
Chris Lattner9f0bc652007-02-25 05:34:32 +00003268 case ISD::DYNAMIC_STACKALLOC:
3269 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
Chris Lattner7c0d6642005-10-02 06:37:13 +00003270
Chris Lattner1a635d62006-04-14 06:01:58 +00003271 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3272 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
3273 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
Dale Johannesen6eaeff22007-10-10 01:01:31 +00003274 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG);
Dan Gohman1a024862008-01-31 00:41:03 +00003275 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
Chris Lattnerecfe55e2006-03-22 05:30:33 +00003276
Chris Lattner1a635d62006-04-14 06:01:58 +00003277 // Lower 64-bit shifts.
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00003278 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
3279 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
3280 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
Chris Lattnerecfe55e2006-03-22 05:30:33 +00003281
Chris Lattner1a635d62006-04-14 06:01:58 +00003282 // Vector-related lowering.
3283 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3284 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3285 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3286 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
Chris Lattnere7c768e2006-04-18 03:24:30 +00003287 case ISD::MUL: return LowerMUL(Op, DAG);
Nate Begemanbcc5f362007-01-29 22:58:52 +00003288
Chris Lattner3fc027d2007-12-08 06:59:59 +00003289 // Frame & Return address.
3290 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
Nicolas Geoffray43c6e7c2007-03-01 13:11:38 +00003291 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Chris Lattnerbc11c342005-08-31 20:23:54 +00003292 }
Chris Lattnere4bc9ea2005-08-26 00:52:45 +00003293 return SDOperand();
3294}
3295
Chris Lattner1f873002007-11-28 18:44:47 +00003296SDNode *PPCTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
3297 switch (N->getOpcode()) {
3298 default: assert(0 && "Wasn't expecting to be able to lower this!");
3299 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(SDOperand(N, 0), DAG).Val;
3300 }
3301}
3302
3303
Chris Lattner1a635d62006-04-14 06:01:58 +00003304//===----------------------------------------------------------------------===//
3305// Other Lowering Code
3306//===----------------------------------------------------------------------===//
3307
Chris Lattner8a2d3ca2005-08-26 21:23:58 +00003308MachineBasicBlock *
Evan Chengff9b3732008-01-30 18:18:23 +00003309PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3310 MachineBasicBlock *BB) {
Evan Chengc0f64ff2006-11-27 23:37:22 +00003311 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
Chris Lattnerc08f9022006-06-27 00:04:13 +00003312 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
3313 MI->getOpcode() == PPC::SELECT_CC_I8 ||
Chris Lattner919c0322005-10-01 01:35:02 +00003314 MI->getOpcode() == PPC::SELECT_CC_F4 ||
Chris Lattner710ff322006-04-08 22:45:08 +00003315 MI->getOpcode() == PPC::SELECT_CC_F8 ||
3316 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
Chris Lattner8a2d3ca2005-08-26 21:23:58 +00003317 "Unexpected instr type to insert");
3318
3319 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
3320 // control-flow pattern. The incoming instruction knows the destination vreg
3321 // to set, the condition code register to branch on, the true/false values to
3322 // select between, and a branch opcode to use.
3323 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3324 ilist<MachineBasicBlock>::iterator It = BB;
3325 ++It;
3326
3327 // thisMBB:
3328 // ...
3329 // TrueVal = ...
3330 // cmpTY ccX, r1, r2
3331 // bCC copy1MBB
3332 // fallthrough --> copy0MBB
3333 MachineBasicBlock *thisMBB = BB;
3334 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
3335 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
Chris Lattnerdf4ed632006-11-17 22:10:59 +00003336 unsigned SelectPred = MI->getOperand(4).getImm();
Evan Chengc0f64ff2006-11-27 23:37:22 +00003337 BuildMI(BB, TII->get(PPC::BCC))
Chris Lattner18258c62006-11-17 22:37:34 +00003338 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
Chris Lattner8a2d3ca2005-08-26 21:23:58 +00003339 MachineFunction *F = BB->getParent();
3340 F->getBasicBlockList().insert(It, copy0MBB);
3341 F->getBasicBlockList().insert(It, sinkMBB);
Nate Begemanf15485a2006-03-27 01:32:24 +00003342 // Update machine-CFG edges by first adding all successors of the current
3343 // block to the new block which will contain the Phi node for the select.
3344 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
3345 e = BB->succ_end(); i != e; ++i)
3346 sinkMBB->addSuccessor(*i);
3347 // Next, remove all successors of the current block, and add the true
3348 // and fallthrough blocks as its successors.
3349 while(!BB->succ_empty())
3350 BB->removeSuccessor(BB->succ_begin());
Chris Lattner8a2d3ca2005-08-26 21:23:58 +00003351 BB->addSuccessor(copy0MBB);
3352 BB->addSuccessor(sinkMBB);
3353
3354 // copy0MBB:
3355 // %FalseValue = ...
3356 // # fallthrough to sinkMBB
3357 BB = copy0MBB;
3358
3359 // Update machine-CFG edges
3360 BB->addSuccessor(sinkMBB);
3361
3362 // sinkMBB:
3363 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3364 // ...
3365 BB = sinkMBB;
Evan Chengc0f64ff2006-11-27 23:37:22 +00003366 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
Chris Lattner8a2d3ca2005-08-26 21:23:58 +00003367 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
3368 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3369
3370 delete MI; // The pseudo instruction is gone now.
3371 return BB;
3372}
3373
Chris Lattner1a635d62006-04-14 06:01:58 +00003374//===----------------------------------------------------------------------===//
3375// Target Optimization Hooks
3376//===----------------------------------------------------------------------===//
3377
Chris Lattner8c13d0a2006-03-01 04:57:39 +00003378SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
3379 DAGCombinerInfo &DCI) const {
3380 TargetMachine &TM = getTargetMachine();
3381 SelectionDAG &DAG = DCI.DAG;
3382 switch (N->getOpcode()) {
3383 default: break;
Chris Lattnercf9d0ac2006-09-19 05:22:59 +00003384 case PPCISD::SHL:
3385 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3386 if (C->getValue() == 0) // 0 << V -> 0.
3387 return N->getOperand(0);
3388 }
3389 break;
3390 case PPCISD::SRL:
3391 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3392 if (C->getValue() == 0) // 0 >>u V -> 0.
3393 return N->getOperand(0);
3394 }
3395 break;
3396 case PPCISD::SRA:
3397 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3398 if (C->getValue() == 0 || // 0 >>s V -> 0.
3399 C->isAllOnesValue()) // -1 >>s V -> -1.
3400 return N->getOperand(0);
3401 }
3402 break;
3403
Chris Lattner8c13d0a2006-03-01 04:57:39 +00003404 case ISD::SINT_TO_FP:
Chris Lattnera7a58542006-06-16 17:34:12 +00003405 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
Chris Lattnerecfe55e2006-03-22 05:30:33 +00003406 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
3407 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
3408 // We allow the src/dst to be either f32/f64, but the intermediate
3409 // type must be i64.
Dale Johannesen79217062007-10-23 23:20:14 +00003410 if (N->getOperand(0).getValueType() == MVT::i64 &&
3411 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
Chris Lattnerecfe55e2006-03-22 05:30:33 +00003412 SDOperand Val = N->getOperand(0).getOperand(0);
3413 if (Val.getValueType() == MVT::f32) {
3414 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3415 DCI.AddToWorklist(Val.Val);
3416 }
3417
3418 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
Chris Lattner8c13d0a2006-03-01 04:57:39 +00003419 DCI.AddToWorklist(Val.Val);
Chris Lattnerecfe55e2006-03-22 05:30:33 +00003420 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
Chris Lattner8c13d0a2006-03-01 04:57:39 +00003421 DCI.AddToWorklist(Val.Val);
Chris Lattnerecfe55e2006-03-22 05:30:33 +00003422 if (N->getValueType(0) == MVT::f32) {
Chris Lattner0bd48932008-01-17 07:00:52 +00003423 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val,
3424 DAG.getIntPtrConstant(0));
Chris Lattnerecfe55e2006-03-22 05:30:33 +00003425 DCI.AddToWorklist(Val.Val);
3426 }
3427 return Val;
3428 } else if (N->getOperand(0).getValueType() == MVT::i32) {
3429 // If the intermediate type is i32, we can avoid the load/store here
3430 // too.
Chris Lattner8c13d0a2006-03-01 04:57:39 +00003431 }
Chris Lattner8c13d0a2006-03-01 04:57:39 +00003432 }
3433 }
3434 break;
Chris Lattner51269842006-03-01 05:50:56 +00003435 case ISD::STORE:
3436 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
3437 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
Chris Lattnera7a02fb2008-01-18 16:54:56 +00003438 !cast<StoreSDNode>(N)->isTruncatingStore() &&
Chris Lattner51269842006-03-01 05:50:56 +00003439 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
Dale Johannesen79217062007-10-23 23:20:14 +00003440 N->getOperand(1).getValueType() == MVT::i32 &&
3441 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
Chris Lattner51269842006-03-01 05:50:56 +00003442 SDOperand Val = N->getOperand(1).getOperand(0);
3443 if (Val.getValueType() == MVT::f32) {
3444 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3445 DCI.AddToWorklist(Val.Val);
3446 }
3447 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
3448 DCI.AddToWorklist(Val.Val);
3449
3450 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
3451 N->getOperand(2), N->getOperand(3));
3452 DCI.AddToWorklist(Val.Val);
3453 return Val;
3454 }
Chris Lattnerd9989382006-07-10 20:56:58 +00003455
3456 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
3457 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
3458 N->getOperand(1).Val->hasOneUse() &&
3459 (N->getOperand(1).getValueType() == MVT::i32 ||
3460 N->getOperand(1).getValueType() == MVT::i16)) {
3461 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
3462 // Do an any-extend to 32-bits if this is a half-word input.
3463 if (BSwapOp.getValueType() == MVT::i16)
3464 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
3465
3466 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
3467 N->getOperand(2), N->getOperand(3),
3468 DAG.getValueType(N->getOperand(1).getValueType()));
3469 }
3470 break;
3471 case ISD::BSWAP:
3472 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
Evan Cheng466685d2006-10-09 20:57:25 +00003473 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
Chris Lattnerd9989382006-07-10 20:56:58 +00003474 N->getOperand(0).hasOneUse() &&
3475 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
3476 SDOperand Load = N->getOperand(0);
Evan Cheng466685d2006-10-09 20:57:25 +00003477 LoadSDNode *LD = cast<LoadSDNode>(Load);
Chris Lattnerd9989382006-07-10 20:56:58 +00003478 // Create the byte-swapping load.
3479 std::vector<MVT::ValueType> VTs;
3480 VTs.push_back(MVT::i32);
3481 VTs.push_back(MVT::Other);
Dan Gohman69de1932008-02-06 22:27:42 +00003482 SDOperand MO = DAG.getMemOperand(LD->getMemOperand());
Chris Lattner79e490a2006-08-11 17:18:05 +00003483 SDOperand Ops[] = {
Evan Cheng466685d2006-10-09 20:57:25 +00003484 LD->getChain(), // Chain
3485 LD->getBasePtr(), // Ptr
Dan Gohman69de1932008-02-06 22:27:42 +00003486 MO, // MemOperand
Chris Lattner79e490a2006-08-11 17:18:05 +00003487 DAG.getValueType(N->getValueType(0)) // VT
3488 };
3489 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
Chris Lattnerd9989382006-07-10 20:56:58 +00003490
3491 // If this is an i16 load, insert the truncate.
3492 SDOperand ResVal = BSLoad;
3493 if (N->getValueType(0) == MVT::i16)
3494 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
3495
3496 // First, combine the bswap away. This makes the value produced by the
3497 // load dead.
3498 DCI.CombineTo(N, ResVal);
3499
3500 // Next, combine the load away, we give it a bogus result value but a real
3501 // chain result. The result value is dead because the bswap is dead.
3502 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
3503
3504 // Return N so it doesn't get rechecked!
3505 return SDOperand(N, 0);
3506 }
3507
Chris Lattner51269842006-03-01 05:50:56 +00003508 break;
Chris Lattner4468c222006-03-31 06:02:07 +00003509 case PPCISD::VCMP: {
3510 // If a VCMPo node already exists with exactly the same operands as this
3511 // node, use its result instead of this node (VCMPo computes both a CR6 and
3512 // a normal output).
3513 //
3514 if (!N->getOperand(0).hasOneUse() &&
3515 !N->getOperand(1).hasOneUse() &&
3516 !N->getOperand(2).hasOneUse()) {
3517
3518 // Scan all of the users of the LHS, looking for VCMPo's that match.
3519 SDNode *VCMPoNode = 0;
3520
3521 SDNode *LHSN = N->getOperand(0).Val;
3522 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
3523 UI != E; ++UI)
3524 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
3525 (*UI)->getOperand(1) == N->getOperand(1) &&
3526 (*UI)->getOperand(2) == N->getOperand(2) &&
3527 (*UI)->getOperand(0) == N->getOperand(0)) {
3528 VCMPoNode = *UI;
3529 break;
3530 }
3531
Chris Lattner00901202006-04-18 18:28:22 +00003532 // If there is no VCMPo node, or if the flag value has a single use, don't
3533 // transform this.
3534 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
3535 break;
3536
3537 // Look at the (necessarily single) use of the flag value. If it has a
3538 // chain, this transformation is more complex. Note that multiple things
3539 // could use the value result, which we should ignore.
3540 SDNode *FlagUser = 0;
3541 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
3542 FlagUser == 0; ++UI) {
3543 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
3544 SDNode *User = *UI;
3545 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
3546 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
3547 FlagUser = User;
3548 break;
3549 }
3550 }
3551 }
3552
3553 // If the user is a MFCR instruction, we know this is safe. Otherwise we
3554 // give up for right now.
3555 if (FlagUser->getOpcode() == PPCISD::MFCR)
Chris Lattner4468c222006-03-31 06:02:07 +00003556 return SDOperand(VCMPoNode, 0);
3557 }
3558 break;
3559 }
Chris Lattner90564f22006-04-18 17:59:36 +00003560 case ISD::BR_CC: {
3561 // If this is a branch on an altivec predicate comparison, lower this so
3562 // that we don't have to do a MFCR: instead, branch directly on CR6. This
3563 // lowering is done pre-legalize, because the legalizer lowers the predicate
3564 // compare down to code that is difficult to reassemble.
3565 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
3566 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
3567 int CompareOpc;
3568 bool isDot;
3569
3570 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
3571 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
3572 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
3573 assert(isDot && "Can't compare against a vector result!");
3574
3575 // If this is a comparison against something other than 0/1, then we know
3576 // that the condition is never/always true.
3577 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
3578 if (Val != 0 && Val != 1) {
3579 if (CC == ISD::SETEQ) // Cond never true, remove branch.
3580 return N->getOperand(0);
3581 // Always !=, turn it into an unconditional branch.
3582 return DAG.getNode(ISD::BR, MVT::Other,
3583 N->getOperand(0), N->getOperand(4));
3584 }
3585
3586 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
3587
3588 // Create the PPCISD altivec 'dot' comparison node.
Chris Lattner90564f22006-04-18 17:59:36 +00003589 std::vector<MVT::ValueType> VTs;
Chris Lattner79e490a2006-08-11 17:18:05 +00003590 SDOperand Ops[] = {
3591 LHS.getOperand(2), // LHS of compare
3592 LHS.getOperand(3), // RHS of compare
3593 DAG.getConstant(CompareOpc, MVT::i32)
3594 };
Chris Lattner90564f22006-04-18 17:59:36 +00003595 VTs.push_back(LHS.getOperand(2).getValueType());
3596 VTs.push_back(MVT::Flag);
Chris Lattner79e490a2006-08-11 17:18:05 +00003597 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
Chris Lattner90564f22006-04-18 17:59:36 +00003598
3599 // Unpack the result based on how the target uses it.
Chris Lattnerdf4ed632006-11-17 22:10:59 +00003600 PPC::Predicate CompOpc;
Chris Lattner90564f22006-04-18 17:59:36 +00003601 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
3602 default: // Can't happen, don't crash on invalid number though.
3603 case 0: // Branch on the value of the EQ bit of CR6.
Chris Lattnerdf4ed632006-11-17 22:10:59 +00003604 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
Chris Lattner90564f22006-04-18 17:59:36 +00003605 break;
3606 case 1: // Branch on the inverted value of the EQ bit of CR6.
Chris Lattnerdf4ed632006-11-17 22:10:59 +00003607 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
Chris Lattner90564f22006-04-18 17:59:36 +00003608 break;
3609 case 2: // Branch on the value of the LT bit of CR6.
Chris Lattnerdf4ed632006-11-17 22:10:59 +00003610 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
Chris Lattner90564f22006-04-18 17:59:36 +00003611 break;
3612 case 3: // Branch on the inverted value of the LT bit of CR6.
Chris Lattnerdf4ed632006-11-17 22:10:59 +00003613 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
Chris Lattner90564f22006-04-18 17:59:36 +00003614 break;
3615 }
3616
3617 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
Chris Lattner90564f22006-04-18 17:59:36 +00003618 DAG.getConstant(CompOpc, MVT::i32),
Chris Lattner18258c62006-11-17 22:37:34 +00003619 DAG.getRegister(PPC::CR6, MVT::i32),
Chris Lattner90564f22006-04-18 17:59:36 +00003620 N->getOperand(4), CompNode.getValue(1));
3621 }
3622 break;
3623 }
Chris Lattner8c13d0a2006-03-01 04:57:39 +00003624 }
3625
3626 return SDOperand();
3627}
3628
Chris Lattner1a635d62006-04-14 06:01:58 +00003629//===----------------------------------------------------------------------===//
3630// Inline Assembly Support
3631//===----------------------------------------------------------------------===//
3632
Chris Lattnerbbe77de2006-04-02 06:26:07 +00003633void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
Dan Gohman977a76f2008-02-13 22:28:48 +00003634 const APInt &Mask,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +00003635 APInt &KnownZero,
3636 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +00003637 const SelectionDAG &DAG,
Chris Lattnerbbe77de2006-04-02 06:26:07 +00003638 unsigned Depth) const {
Dan Gohmanfd29e0e2008-02-13 00:35:47 +00003639 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
Chris Lattnerbbe77de2006-04-02 06:26:07 +00003640 switch (Op.getOpcode()) {
3641 default: break;
Chris Lattnerd9989382006-07-10 20:56:58 +00003642 case PPCISD::LBRX: {
3643 // lhbrx is known to have the top bits cleared out.
3644 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
3645 KnownZero = 0xFFFF0000;
3646 break;
3647 }
Chris Lattnerbbe77de2006-04-02 06:26:07 +00003648 case ISD::INTRINSIC_WO_CHAIN: {
3649 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
3650 default: break;
3651 case Intrinsic::ppc_altivec_vcmpbfp_p:
3652 case Intrinsic::ppc_altivec_vcmpeqfp_p:
3653 case Intrinsic::ppc_altivec_vcmpequb_p:
3654 case Intrinsic::ppc_altivec_vcmpequh_p:
3655 case Intrinsic::ppc_altivec_vcmpequw_p:
3656 case Intrinsic::ppc_altivec_vcmpgefp_p:
3657 case Intrinsic::ppc_altivec_vcmpgtfp_p:
3658 case Intrinsic::ppc_altivec_vcmpgtsb_p:
3659 case Intrinsic::ppc_altivec_vcmpgtsh_p:
3660 case Intrinsic::ppc_altivec_vcmpgtsw_p:
3661 case Intrinsic::ppc_altivec_vcmpgtub_p:
3662 case Intrinsic::ppc_altivec_vcmpgtuh_p:
3663 case Intrinsic::ppc_altivec_vcmpgtuw_p:
3664 KnownZero = ~1U; // All bits but the low one are known to be zero.
3665 break;
3666 }
3667 }
3668 }
3669}
3670
3671
Chris Lattner4234f572007-03-25 02:14:49 +00003672/// getConstraintType - Given a constraint, return the type of
Chris Lattnerad3bc8d2006-02-07 20:16:30 +00003673/// constraint it is for this target.
3674PPCTargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +00003675PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
3676 if (Constraint.size() == 1) {
3677 switch (Constraint[0]) {
3678 default: break;
3679 case 'b':
3680 case 'r':
3681 case 'f':
3682 case 'v':
3683 case 'y':
3684 return C_RegisterClass;
3685 }
3686 }
3687 return TargetLowering::getConstraintType(Constraint);
Chris Lattnerad3bc8d2006-02-07 20:16:30 +00003688}
3689
Chris Lattner331d1bc2006-11-02 01:44:04 +00003690std::pair<unsigned, const TargetRegisterClass*>
3691PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3692 MVT::ValueType VT) const {
Chris Lattnerddc787d2006-01-31 19:20:21 +00003693 if (Constraint.size() == 1) {
Chris Lattner331d1bc2006-11-02 01:44:04 +00003694 // GCC RS6000 Constraint Letters
3695 switch (Constraint[0]) {
3696 case 'b': // R1-R31
3697 case 'r': // R0-R31
3698 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
3699 return std::make_pair(0U, PPC::G8RCRegisterClass);
3700 return std::make_pair(0U, PPC::GPRCRegisterClass);
3701 case 'f':
3702 if (VT == MVT::f32)
3703 return std::make_pair(0U, PPC::F4RCRegisterClass);
3704 else if (VT == MVT::f64)
3705 return std::make_pair(0U, PPC::F8RCRegisterClass);
3706 break;
Chris Lattnerddc787d2006-01-31 19:20:21 +00003707 case 'v':
Chris Lattner331d1bc2006-11-02 01:44:04 +00003708 return std::make_pair(0U, PPC::VRRCRegisterClass);
3709 case 'y': // crrc
3710 return std::make_pair(0U, PPC::CRRCRegisterClass);
Chris Lattnerddc787d2006-01-31 19:20:21 +00003711 }
3712 }
3713
Chris Lattner331d1bc2006-11-02 01:44:04 +00003714 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
Chris Lattnerddc787d2006-01-31 19:20:21 +00003715}
Chris Lattner763317d2006-02-07 00:47:13 +00003716
Chris Lattner331d1bc2006-11-02 01:44:04 +00003717
Chris Lattner48884cd2007-08-25 00:47:38 +00003718/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3719/// vector. If it is invalid, don't add anything to Ops.
3720void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
3721 std::vector<SDOperand>&Ops,
3722 SelectionDAG &DAG) {
3723 SDOperand Result(0,0);
Chris Lattner763317d2006-02-07 00:47:13 +00003724 switch (Letter) {
3725 default: break;
3726 case 'I':
3727 case 'J':
3728 case 'K':
3729 case 'L':
3730 case 'M':
3731 case 'N':
3732 case 'O':
3733 case 'P': {
Chris Lattner9f5d5782007-05-15 01:31:05 +00003734 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
Chris Lattner48884cd2007-08-25 00:47:38 +00003735 if (!CST) return; // Must be an immediate to match.
Chris Lattner9f5d5782007-05-15 01:31:05 +00003736 unsigned Value = CST->getValue();
Chris Lattner763317d2006-02-07 00:47:13 +00003737 switch (Letter) {
3738 default: assert(0 && "Unknown constraint letter!");
3739 case 'I': // "I" is a signed 16-bit constant.
Chris Lattner9f5d5782007-05-15 01:31:05 +00003740 if ((short)Value == (int)Value)
Chris Lattner48884cd2007-08-25 00:47:38 +00003741 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattnerdba1aee2006-10-31 19:40:43 +00003742 break;
Chris Lattner763317d2006-02-07 00:47:13 +00003743 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
3744 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
Chris Lattner9f5d5782007-05-15 01:31:05 +00003745 if ((short)Value == 0)
Chris Lattner48884cd2007-08-25 00:47:38 +00003746 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattnerdba1aee2006-10-31 19:40:43 +00003747 break;
Chris Lattner763317d2006-02-07 00:47:13 +00003748 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
Chris Lattner9f5d5782007-05-15 01:31:05 +00003749 if ((Value >> 16) == 0)
Chris Lattner48884cd2007-08-25 00:47:38 +00003750 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattnerdba1aee2006-10-31 19:40:43 +00003751 break;
Chris Lattner763317d2006-02-07 00:47:13 +00003752 case 'M': // "M" is a constant that is greater than 31.
Chris Lattner9f5d5782007-05-15 01:31:05 +00003753 if (Value > 31)
Chris Lattner48884cd2007-08-25 00:47:38 +00003754 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattnerdba1aee2006-10-31 19:40:43 +00003755 break;
Chris Lattner763317d2006-02-07 00:47:13 +00003756 case 'N': // "N" is a positive constant that is an exact power of two.
Chris Lattner9f5d5782007-05-15 01:31:05 +00003757 if ((int)Value > 0 && isPowerOf2_32(Value))
Chris Lattner48884cd2007-08-25 00:47:38 +00003758 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattnerdba1aee2006-10-31 19:40:43 +00003759 break;
Chris Lattner763317d2006-02-07 00:47:13 +00003760 case 'O': // "O" is the constant zero.
Chris Lattner9f5d5782007-05-15 01:31:05 +00003761 if (Value == 0)
Chris Lattner48884cd2007-08-25 00:47:38 +00003762 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattnerdba1aee2006-10-31 19:40:43 +00003763 break;
Chris Lattner763317d2006-02-07 00:47:13 +00003764 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
Chris Lattner9f5d5782007-05-15 01:31:05 +00003765 if ((short)-Value == (int)-Value)
Chris Lattner48884cd2007-08-25 00:47:38 +00003766 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattnerdba1aee2006-10-31 19:40:43 +00003767 break;
Chris Lattner763317d2006-02-07 00:47:13 +00003768 }
3769 break;
3770 }
3771 }
3772
Chris Lattner48884cd2007-08-25 00:47:38 +00003773 if (Result.Val) {
3774 Ops.push_back(Result);
3775 return;
3776 }
3777
Chris Lattner763317d2006-02-07 00:47:13 +00003778 // Handle standard constraint letters.
Chris Lattner48884cd2007-08-25 00:47:38 +00003779 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
Chris Lattner763317d2006-02-07 00:47:13 +00003780}
Evan Chengc4c62572006-03-13 23:20:37 +00003781
Chris Lattnerc9addb72007-03-30 23:15:24 +00003782// isLegalAddressingMode - Return true if the addressing mode represented
3783// by AM is legal for this target, for a load/store of the specified type.
3784bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3785 const Type *Ty) const {
3786 // FIXME: PPC does not allow r+i addressing modes for vectors!
3787
3788 // PPC allows a sign-extended 16-bit immediate field.
3789 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3790 return false;
3791
3792 // No global is ever allowed as a base.
3793 if (AM.BaseGV)
3794 return false;
3795
3796 // PPC only support r+r,
3797 switch (AM.Scale) {
3798 case 0: // "r+i" or just "i", depending on HasBaseReg.
3799 break;
3800 case 1:
3801 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3802 return false;
3803 // Otherwise we have r+r or r+i.
3804 break;
3805 case 2:
3806 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3807 return false;
3808 // Allow 2*r as r+r.
3809 break;
Chris Lattner7c7ba9d2007-04-09 22:10:05 +00003810 default:
3811 // No other scales are supported.
3812 return false;
Chris Lattnerc9addb72007-03-30 23:15:24 +00003813 }
3814
3815 return true;
3816}
3817
Evan Chengc4c62572006-03-13 23:20:37 +00003818/// isLegalAddressImmediate - Return true if the integer value can be used
Evan Cheng86193912007-03-12 23:29:01 +00003819/// as the offset of the target addressing mode for load / store of the
3820/// given type.
3821bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
Evan Chengc4c62572006-03-13 23:20:37 +00003822 // PPC allows a sign-extended 16-bit immediate field.
3823 return (V > -(1 << 16) && V < (1 << 16)-1);
3824}
Reid Spencer3a9ec242006-08-28 01:02:49 +00003825
3826bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
Chris Lattnerc9addb72007-03-30 23:15:24 +00003827 return false;
Reid Spencer3a9ec242006-08-28 01:02:49 +00003828}
Nicolas Geoffray43c6e7c2007-03-01 13:11:38 +00003829
Chris Lattner3fc027d2007-12-08 06:59:59 +00003830SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
3831 // Depths > 0 not supported yet!
3832 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3833 return SDOperand();
3834
3835 MachineFunction &MF = DAG.getMachineFunction();
3836 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3837 int RAIdx = FuncInfo->getReturnAddrSaveIndex();
3838 if (RAIdx == 0) {
3839 bool isPPC64 = PPCSubTarget.isPPC64();
3840 int Offset =
3841 PPCFrameInfo::getReturnSaveOffset(isPPC64, PPCSubTarget.isMachoABI());
3842
3843 // Set up a frame object for the return address.
3844 RAIdx = MF.getFrameInfo()->CreateFixedObject(isPPC64 ? 8 : 4, Offset);
3845
3846 // Remember it for next time.
3847 FuncInfo->setReturnAddrSaveIndex(RAIdx);
3848
3849 // Make sure the function really does not optimize away the store of the RA
3850 // to the stack.
3851 FuncInfo->setLRStoreRequired();
3852 }
3853
3854 // Just load the return address off the stack.
3855 SDOperand RetAddrFI = DAG.getFrameIndex(RAIdx, getPointerTy());
3856 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
3857}
3858
3859SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
Nicolas Geoffray43c6e7c2007-03-01 13:11:38 +00003860 // Depths > 0 not supported yet!
3861 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3862 return SDOperand();
3863
3864 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3865 bool isPPC64 = PtrVT == MVT::i64;
3866
3867 MachineFunction &MF = DAG.getMachineFunction();
3868 MachineFrameInfo *MFI = MF.getFrameInfo();
3869 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
3870 && MFI->getStackSize();
3871
3872 if (isPPC64)
3873 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
Bill Wendlingb8a80f02007-08-30 00:59:19 +00003874 MVT::i64);
Nicolas Geoffray43c6e7c2007-03-01 13:11:38 +00003875 else
3876 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,
3877 MVT::i32);
3878}