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Jia Liubb481f82012-02-28 07:46:26 +00001//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00007//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00008//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00009//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +000013//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000014
15#define DEBUG_TYPE "mips-lower"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000016#include "MipsISelLowering.h"
Bruno Cardoso Lopesa2b1bb52007-08-28 05:08:16 +000017#include "MipsMachineFunction.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000018#include "MipsTargetMachine.h"
Chris Lattnerb71b9092009-08-13 06:28:06 +000019#include "MipsTargetObjectFile.h"
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000020#include "MipsSubtarget.h"
Craig Topper79aa3412012-03-17 18:46:09 +000021#include "InstPrinter/MipsInstPrinter.h"
22#include "MCTargetDesc/MipsBaseInfo.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000023#include "llvm/DerivedTypes.h"
24#include "llvm/Function.h"
Bruno Cardoso Lopes91fd5322008-07-21 18:52:34 +000025#include "llvm/GlobalVariable.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000026#include "llvm/Intrinsics.h"
27#include "llvm/CallingConv.h"
28#include "llvm/CodeGen/CallingConvLower.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineFunction.h"
31#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000032#include "llvm/CodeGen/MachineRegisterInfo.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000033#include "llvm/CodeGen/SelectionDAGISel.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000034#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/Support/Debug.h"
Torok Edwinc25e7582009-07-11 20:10:48 +000036#include "llvm/Support/ErrorHandling.h"
NAKAMURA Takumi89593932012-04-21 15:31:45 +000037#include "llvm/Support/raw_ostream.h"
38
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000039using namespace llvm;
40
Jia Liubb481f82012-02-28 07:46:26 +000041// If I is a shifted mask, set the size (Size) and the first bit of the
Akira Hatanakadbe9a312011-08-18 20:07:42 +000042// mask (Pos), and return true.
Jia Liubb481f82012-02-28 07:46:26 +000043// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
Akira Hatanaka854a7db2011-08-19 22:59:00 +000044static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
Akira Hatanakad6bc5232011-12-05 21:26:34 +000045 if (!isShiftedMask_64(I))
Akira Hatanaka854a7db2011-08-19 22:59:00 +000046 return false;
Akira Hatanakabb15e112011-08-17 02:05:42 +000047
Akira Hatanakad6bc5232011-12-05 21:26:34 +000048 Size = CountPopulation_64(I);
49 Pos = CountTrailingZeros_64(I);
Akira Hatanakadbe9a312011-08-18 20:07:42 +000050 return true;
Akira Hatanakabb15e112011-08-17 02:05:42 +000051}
52
Akira Hatanaka648f00c2012-02-24 22:34:47 +000053static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) {
54 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
55 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
56}
57
Chris Lattnerf0144122009-07-28 03:13:23 +000058const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
59 switch (Opcode) {
Akira Hatanakabdd2ce92011-05-23 21:13:59 +000060 case MipsISD::JmpLink: return "MipsISD::JmpLink";
61 case MipsISD::Hi: return "MipsISD::Hi";
62 case MipsISD::Lo: return "MipsISD::Lo";
63 case MipsISD::GPRel: return "MipsISD::GPRel";
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +000064 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
Akira Hatanakabdd2ce92011-05-23 21:13:59 +000065 case MipsISD::Ret: return "MipsISD::Ret";
66 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
67 case MipsISD::FPCmp: return "MipsISD::FPCmp";
68 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
69 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
70 case MipsISD::FPRound: return "MipsISD::FPRound";
71 case MipsISD::MAdd: return "MipsISD::MAdd";
72 case MipsISD::MAddu: return "MipsISD::MAddu";
73 case MipsISD::MSub: return "MipsISD::MSub";
74 case MipsISD::MSubu: return "MipsISD::MSubu";
75 case MipsISD::DivRem: return "MipsISD::DivRem";
76 case MipsISD::DivRemU: return "MipsISD::DivRemU";
77 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
78 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
Akira Hatanakabfcb83f2011-12-12 22:38:19 +000079 case MipsISD::Wrapper: return "MipsISD::Wrapper";
Akira Hatanaka21afc632011-06-21 00:40:49 +000080 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
Akira Hatanakadb548262011-07-19 23:30:50 +000081 case MipsISD::Sync: return "MipsISD::Sync";
Akira Hatanakabb15e112011-08-17 02:05:42 +000082 case MipsISD::Ext: return "MipsISD::Ext";
83 case MipsISD::Ins: return "MipsISD::Ins";
Akira Hatanaka0f843822011-06-07 18:58:42 +000084 default: return NULL;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000085 }
86}
87
88MipsTargetLowering::
Chris Lattnerf0144122009-07-28 03:13:23 +000089MipsTargetLowering(MipsTargetMachine &TM)
Akira Hatanaka8b4198d2011-09-26 21:47:02 +000090 : TargetLowering(TM, new MipsTargetObjectFile()),
91 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
Akira Hatanaka2ec69fa2011-10-28 18:47:24 +000092 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
93 IsO32(Subtarget->isABI_O32()) {
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000094
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000095 // Mips does not have i1 type, so use i32 for
Wesley Peckbf17cfa2010-11-23 03:31:01 +000096 // setcc operations results (slt, sgt, ...).
Duncan Sands03228082008-11-23 15:47:28 +000097 setBooleanContents(ZeroOrOneBooleanContent);
Duncan Sands28b77e92011-09-06 19:07:46 +000098 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000099
100 // Set up the register classes
Craig Topper420761a2012-04-20 07:30:17 +0000101 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000102
Akira Hatanaka95934842011-09-24 01:34:44 +0000103 if (HasMips64)
Craig Topper420761a2012-04-20 07:30:17 +0000104 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
Akira Hatanaka95934842011-09-24 01:34:44 +0000105
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000106 if (!TM.Options.UseSoftFloat) {
Craig Topper420761a2012-04-20 07:30:17 +0000107 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000108
109 // When dealing with single precision only, use libcalls
110 if (!Subtarget->isSingleFloat()) {
111 if (HasMips64)
Craig Topper420761a2012-04-20 07:30:17 +0000112 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000113 else
Craig Topper420761a2012-04-20 07:30:17 +0000114 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000115 }
Akira Hatanaka792016b2011-09-23 18:28:39 +0000116 }
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000117
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000118 // Load extented operations for i1 types must be promoted
Owen Anderson825b72b2009-08-11 20:47:22 +0000119 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
120 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
121 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000122
Eli Friedman6055a6a2009-07-17 04:07:24 +0000123 // MIPS doesn't have extending float->double load/store
Owen Anderson825b72b2009-08-11 20:47:22 +0000124 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
125 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
Eli Friedman10a36592009-07-17 02:28:12 +0000126
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000127 // Used by legalize types to correctly generate the setcc result.
128 // Without this, every float setcc comes with a AND/OR with the result,
129 // we don't want this, since the fpcmp result goes to a flag register,
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +0000130 // which is used implicitly by brcond and select operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000131 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +0000132
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000133 // Mips Custom Operations
Owen Anderson825b72b2009-08-11 20:47:22 +0000134 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +0000135 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
Owen Anderson825b72b2009-08-11 20:47:22 +0000136 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
137 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
138 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
139 setOperationAction(ISD::SELECT, MVT::f32, Custom);
140 setOperationAction(ISD::SELECT, MVT::f64, Custom);
141 setOperationAction(ISD::SELECT, MVT::i32, Custom);
Akira Hatanaka0a40c232012-03-09 23:46:03 +0000142 setOperationAction(ISD::SETCC, MVT::f32, Custom);
143 setOperationAction(ISD::SETCC, MVT::f64, Custom);
Owen Anderson825b72b2009-08-11 20:47:22 +0000144 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
145 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000146 setOperationAction(ISD::VASTART, MVT::Other, Custom);
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000147 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
148 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
149 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
150 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
151
Akira Hatanakac12a6e62012-04-11 22:49:04 +0000152 if (!TM.Options.NoNaNsFPMath) {
153 setOperationAction(ISD::FABS, MVT::f32, Custom);
154 setOperationAction(ISD::FABS, MVT::f64, Custom);
155 }
156
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000157 if (HasMips64) {
158 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
159 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
160 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
161 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
162 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
163 setOperationAction(ISD::SELECT, MVT::i64, Custom);
164 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
165 }
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000166
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000167 setOperationAction(ISD::SDIV, MVT::i32, Expand);
168 setOperationAction(ISD::SREM, MVT::i32, Expand);
169 setOperationAction(ISD::UDIV, MVT::i32, Expand);
170 setOperationAction(ISD::UREM, MVT::i32, Expand);
Akira Hatanakadda4a072011-10-03 21:06:13 +0000171 setOperationAction(ISD::SDIV, MVT::i64, Expand);
172 setOperationAction(ISD::SREM, MVT::i64, Expand);
173 setOperationAction(ISD::UDIV, MVT::i64, Expand);
174 setOperationAction(ISD::UREM, MVT::i64, Expand);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000175
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000176 // Operations not directly supported by Mips.
Owen Anderson825b72b2009-08-11 20:47:22 +0000177 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
178 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
179 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
180 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
Akira Hatanakae1bcd6b2011-12-20 23:40:56 +0000181 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000182 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
Akira Hatanakae1bcd6b2011-12-20 23:40:56 +0000183 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000184 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
185 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
Akira Hatanaka7f162742011-12-21 00:14:05 +0000186 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000187 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
Akira Hatanaka7f162742011-12-21 00:14:05 +0000188 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
Chandler Carruth63974b22011-12-13 01:56:10 +0000189 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
190 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
191 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
192 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000193 setOperationAction(ISD::ROTL, MVT::i32, Expand);
Akira Hatanakac7bafe92011-09-30 18:51:46 +0000194 setOperationAction(ISD::ROTL, MVT::i64, Expand);
Bruno Cardoso Lopes908b6dd2010-12-09 17:32:30 +0000195
Akira Hatanaka56633442011-09-20 23:53:09 +0000196 if (!Subtarget->hasMips32r2())
Bruno Cardoso Lopes908b6dd2010-12-09 17:32:30 +0000197 setOperationAction(ISD::ROTR, MVT::i32, Expand);
198
Akira Hatanakac7bafe92011-09-30 18:51:46 +0000199 if (!Subtarget->hasMips64r2())
200 setOperationAction(ISD::ROTR, MVT::i64, Expand);
201
Owen Anderson825b72b2009-08-11 20:47:22 +0000202 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
203 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
204 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000205 setOperationAction(ISD::FSIN, MVT::f32, Expand);
Bruno Cardoso Lopes5d6fb5d2011-03-04 18:54:14 +0000206 setOperationAction(ISD::FSIN, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000207 setOperationAction(ISD::FCOS, MVT::f32, Expand);
Bruno Cardoso Lopes5d6fb5d2011-03-04 18:54:14 +0000208 setOperationAction(ISD::FCOS, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000209 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
210 setOperationAction(ISD::FPOW, MVT::f32, Expand);
Akira Hatanaka46da1362011-05-23 22:23:58 +0000211 setOperationAction(ISD::FPOW, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000212 setOperationAction(ISD::FLOG, MVT::f32, Expand);
213 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
214 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
215 setOperationAction(ISD::FEXP, MVT::f32, Expand);
Cameron Zwarich33390842011-07-08 21:39:21 +0000216 setOperationAction(ISD::FMA, MVT::f32, Expand);
217 setOperationAction(ISD::FMA, MVT::f64, Expand);
Akira Hatanaka21ecc2f2012-03-29 18:43:11 +0000218 setOperationAction(ISD::FREM, MVT::f32, Expand);
219 setOperationAction(ISD::FREM, MVT::f64, Expand);
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000220
Akira Hatanaka1cc63332012-04-11 22:59:08 +0000221 if (!TM.Options.NoNaNsFPMath) {
222 setOperationAction(ISD::FNEG, MVT::f32, Expand);
223 setOperationAction(ISD::FNEG, MVT::f64, Expand);
224 }
225
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000226 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
Akira Hatanaka590baca2012-02-02 03:13:40 +0000227 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000228 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
Akira Hatanaka590baca2012-02-02 03:13:40 +0000229 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
Eric Christopher471e4222011-06-08 23:55:35 +0000230
Bruno Cardoso Lopes954dac02011-03-09 19:22:22 +0000231 setOperationAction(ISD::VAARG, MVT::Other, Expand);
232 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
233 setOperationAction(ISD::VAEND, MVT::Other, Expand);
234
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000235 // Use the default for now
Owen Anderson825b72b2009-08-11 20:47:22 +0000236 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
237 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
Eli Friedman14648462011-07-27 22:21:52 +0000238
Jia Liubb481f82012-02-28 07:46:26 +0000239 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
240 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
241 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
242 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
Eli Friedman4db5aca2011-08-29 18:23:02 +0000243
Eli Friedman26689ac2011-08-03 21:06:02 +0000244 setInsertFencesForAtomic(true);
245
Bruno Cardoso Lopesea9d4d62008-08-04 06:44:31 +0000246 if (Subtarget->isSingleFloat())
Owen Anderson825b72b2009-08-11 20:47:22 +0000247 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000248
Bruno Cardoso Lopes7728f7e2008-07-09 05:32:22 +0000249 if (!Subtarget->hasSEInReg()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000250 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
251 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000252 }
253
Akira Hatanakac79507a2011-12-21 00:20:27 +0000254 if (!Subtarget->hasBitCount()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000255 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
Akira Hatanakac79507a2011-12-21 00:20:27 +0000256 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
257 }
Bruno Cardoso Lopes65ad4522008-08-08 06:16:31 +0000258
Akira Hatanakac0ea0432011-12-20 23:56:43 +0000259 if (!Subtarget->hasSwap()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000260 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
Akira Hatanakac0ea0432011-12-20 23:56:43 +0000261 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
262 }
Bruno Cardoso Lopes739e4412008-08-13 07:13:40 +0000263
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000264 setTargetDAGCombine(ISD::ADDE);
265 setTargetDAGCombine(ISD::SUBE);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000266 setTargetDAGCombine(ISD::SDIVREM);
267 setTargetDAGCombine(ISD::UDIVREM);
Akira Hatanakaee8c3b02012-03-08 03:26:37 +0000268 setTargetDAGCombine(ISD::SELECT);
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000269 setTargetDAGCombine(ISD::AND);
270 setTargetDAGCombine(ISD::OR);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000271
Akira Hatanaka5fdf5002012-03-08 01:59:33 +0000272 setMinFunctionAlignment(HasMips64 ? 3 : 2);
Eli Friedmanfc5d3052011-05-06 20:34:06 +0000273
Akira Hatanaka3f5b1072012-02-02 03:17:04 +0000274 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000275 computeRegisterProperties();
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000276
Akira Hatanaka590baca2012-02-02 03:13:40 +0000277 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
278 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000279}
280
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +0000281bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
Akira Hatanaka511961a2011-08-17 18:49:18 +0000282 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
Jia Liubb481f82012-02-28 07:46:26 +0000283
Akira Hatanaka44b6c712012-02-28 02:55:02 +0000284 switch (SVT) {
285 case MVT::i64:
286 case MVT::i32:
287 case MVT::i16:
288 return true;
289 case MVT::f32:
Akira Hatanaka44b6c712012-02-28 02:55:02 +0000290 return Subtarget->hasMips32r2Or64();
291 default:
292 return false;
293 }
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +0000294}
295
Duncan Sands28b77e92011-09-06 19:07:46 +0000296EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
Owen Anderson825b72b2009-08-11 20:47:22 +0000297 return MVT::i32;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000298}
299
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000300// SelectMadd -
301// Transforms a subgraph in CurDAG if the following pattern is found:
302// (addc multLo, Lo0), (adde multHi, Hi0),
303// where,
304// multHi/Lo: product of multiplication
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000305// Lo0: initial value of Lo register
306// Hi0: initial value of Hi register
Akira Hatanaka81bd78b2011-03-30 21:15:35 +0000307// Return true if pattern matching was successful.
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000308static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000309 // ADDENode's second operand must be a flag output of an ADDC node in order
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000310 // for the matching to be successful.
311 SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
312
313 if (ADDCNode->getOpcode() != ISD::ADDC)
314 return false;
315
316 SDValue MultHi = ADDENode->getOperand(0);
317 SDValue MultLo = ADDCNode->getOperand(0);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000318 SDNode* MultNode = MultHi.getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000319 unsigned MultOpc = MultHi.getOpcode();
320
321 // MultHi and MultLo must be generated by the same node,
322 if (MultLo.getNode() != MultNode)
323 return false;
324
325 // and it must be a multiplication.
326 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
327 return false;
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000328
329 // MultLo amd MultHi must be the first and second output of MultNode
330 // respectively.
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000331 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
332 return false;
333
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000334 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000335 // of the values of MultNode, in which case MultNode will be removed in later
336 // phases.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000337 // If there exist users other than ADDENode or ADDCNode, this function returns
338 // here, which will result in MultNode being mapped to a single MULT
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000339 // instruction node rather than a pair of MULT and MADD instructions being
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000340 // produced.
341 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
342 return false;
343
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000344 SDValue Chain = CurDAG->getEntryNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000345 DebugLoc dl = ADDENode->getDebugLoc();
346
347 // create MipsMAdd(u) node
348 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000349
Akira Hatanaka82099682011-12-19 19:52:25 +0000350 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000351 MultNode->getOperand(0),// Factor 0
352 MultNode->getOperand(1),// Factor 1
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000353 ADDCNode->getOperand(1),// Lo0
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000354 ADDENode->getOperand(1));// Hi0
355
356 // create CopyFromReg nodes
357 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
358 MAdd);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000359 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000360 Mips::HI, MVT::i32,
361 CopyFromLo.getValue(2));
362
363 // replace uses of adde and addc here
364 if (!SDValue(ADDCNode, 0).use_empty())
365 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
366
367 if (!SDValue(ADDENode, 0).use_empty())
368 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
369
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000370 return true;
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000371}
372
373// SelectMsub -
374// Transforms a subgraph in CurDAG if the following pattern is found:
375// (addc Lo0, multLo), (sube Hi0, multHi),
376// where,
377// multHi/Lo: product of multiplication
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000378// Lo0: initial value of Lo register
379// Hi0: initial value of Hi register
Akira Hatanaka81bd78b2011-03-30 21:15:35 +0000380// Return true if pattern matching was successful.
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000381static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000382 // SUBENode's second operand must be a flag output of an SUBC node in order
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000383 // for the matching to be successful.
384 SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
385
386 if (SUBCNode->getOpcode() != ISD::SUBC)
387 return false;
388
389 SDValue MultHi = SUBENode->getOperand(1);
390 SDValue MultLo = SUBCNode->getOperand(1);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000391 SDNode* MultNode = MultHi.getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000392 unsigned MultOpc = MultHi.getOpcode();
393
394 // MultHi and MultLo must be generated by the same node,
395 if (MultLo.getNode() != MultNode)
396 return false;
397
398 // and it must be a multiplication.
399 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
400 return false;
401
402 // MultLo amd MultHi must be the first and second output of MultNode
403 // respectively.
404 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
405 return false;
406
407 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
408 // of the values of MultNode, in which case MultNode will be removed in later
409 // phases.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000410 // If there exist users other than SUBENode or SUBCNode, this function returns
411 // here, which will result in MultNode being mapped to a single MULT
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000412 // instruction node rather than a pair of MULT and MSUB instructions being
413 // produced.
414 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
415 return false;
416
417 SDValue Chain = CurDAG->getEntryNode();
418 DebugLoc dl = SUBENode->getDebugLoc();
419
420 // create MipsSub(u) node
421 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
422
Akira Hatanaka82099682011-12-19 19:52:25 +0000423 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000424 MultNode->getOperand(0),// Factor 0
425 MultNode->getOperand(1),// Factor 1
426 SUBCNode->getOperand(0),// Lo0
427 SUBENode->getOperand(0));// Hi0
428
429 // create CopyFromReg nodes
430 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
431 MSub);
432 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
433 Mips::HI, MVT::i32,
434 CopyFromLo.getValue(2));
435
436 // replace uses of sube and subc here
437 if (!SDValue(SUBCNode, 0).use_empty())
438 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
439
440 if (!SDValue(SUBENode, 0).use_empty())
441 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
442
443 return true;
444}
445
446static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
447 TargetLowering::DAGCombinerInfo &DCI,
448 const MipsSubtarget* Subtarget) {
449 if (DCI.isBeforeLegalize())
450 return SDValue();
451
Akira Hatanakae184fec2011-11-11 04:18:21 +0000452 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
453 SelectMadd(N, &DAG))
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000454 return SDValue(N, 0);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000455
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000456 return SDValue();
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000457}
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000458
459static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
460 TargetLowering::DAGCombinerInfo &DCI,
461 const MipsSubtarget* Subtarget) {
462 if (DCI.isBeforeLegalize())
463 return SDValue();
464
Akira Hatanakae184fec2011-11-11 04:18:21 +0000465 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
466 SelectMsub(N, &DAG))
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000467 return SDValue(N, 0);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000468
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000469 return SDValue();
470}
471
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000472static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
473 TargetLowering::DAGCombinerInfo &DCI,
474 const MipsSubtarget* Subtarget) {
475 if (DCI.isBeforeLegalizeOps())
476 return SDValue();
477
Akira Hatanakadda4a072011-10-03 21:06:13 +0000478 EVT Ty = N->getValueType(0);
Jia Liubb481f82012-02-28 07:46:26 +0000479 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
480 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000481 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
482 MipsISD::DivRemU;
483 DebugLoc dl = N->getDebugLoc();
484
485 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
486 N->getOperand(0), N->getOperand(1));
487 SDValue InChain = DAG.getEntryNode();
488 SDValue InGlue = DivRem;
489
490 // insert MFLO
491 if (N->hasAnyUseOfValue(0)) {
Akira Hatanakadda4a072011-10-03 21:06:13 +0000492 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000493 InGlue);
494 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
495 InChain = CopyFromLo.getValue(1);
496 InGlue = CopyFromLo.getValue(2);
497 }
498
499 // insert MFHI
500 if (N->hasAnyUseOfValue(1)) {
501 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
Akira Hatanakadda4a072011-10-03 21:06:13 +0000502 HI, Ty, InGlue);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000503 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
504 }
505
506 return SDValue();
507}
508
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000509static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
510 switch (CC) {
511 default: llvm_unreachable("Unknown fp condition code!");
512 case ISD::SETEQ:
513 case ISD::SETOEQ: return Mips::FCOND_OEQ;
514 case ISD::SETUNE: return Mips::FCOND_UNE;
515 case ISD::SETLT:
516 case ISD::SETOLT: return Mips::FCOND_OLT;
517 case ISD::SETGT:
518 case ISD::SETOGT: return Mips::FCOND_OGT;
519 case ISD::SETLE:
520 case ISD::SETOLE: return Mips::FCOND_OLE;
521 case ISD::SETGE:
522 case ISD::SETOGE: return Mips::FCOND_OGE;
523 case ISD::SETULT: return Mips::FCOND_ULT;
524 case ISD::SETULE: return Mips::FCOND_ULE;
525 case ISD::SETUGT: return Mips::FCOND_UGT;
526 case ISD::SETUGE: return Mips::FCOND_UGE;
527 case ISD::SETUO: return Mips::FCOND_UN;
528 case ISD::SETO: return Mips::FCOND_OR;
529 case ISD::SETNE:
530 case ISD::SETONE: return Mips::FCOND_ONE;
531 case ISD::SETUEQ: return Mips::FCOND_UEQ;
532 }
533}
534
535
536// Returns true if condition code has to be inverted.
537static bool InvertFPCondCode(Mips::CondCode CC) {
538 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
539 return false;
540
Akira Hatanaka82099682011-12-19 19:52:25 +0000541 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
542 "Illegal Condition Code");
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000543
Akira Hatanaka82099682011-12-19 19:52:25 +0000544 return true;
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000545}
546
547// Creates and returns an FPCmp node from a setcc node.
548// Returns Op if setcc is not a floating point comparison.
549static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
550 // must be a SETCC node
551 if (Op.getOpcode() != ISD::SETCC)
552 return Op;
553
554 SDValue LHS = Op.getOperand(0);
555
556 if (!LHS.getValueType().isFloatingPoint())
557 return Op;
558
559 SDValue RHS = Op.getOperand(1);
560 DebugLoc dl = Op.getDebugLoc();
561
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +0000562 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
563 // node if necessary.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000564 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
565
566 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
567 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
568}
569
570// Creates and returns a CMovFPT/F node.
571static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True,
572 SDValue False, DebugLoc DL) {
573 bool invert = InvertFPCondCode((Mips::CondCode)
574 cast<ConstantSDNode>(Cond.getOperand(2))
575 ->getSExtValue());
576
577 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
578 True.getValueType(), True, False, Cond);
579}
580
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000581static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG& DAG,
582 TargetLowering::DAGCombinerInfo &DCI,
583 const MipsSubtarget* Subtarget) {
584 if (DCI.isBeforeLegalizeOps())
585 return SDValue();
586
587 SDValue SetCC = N->getOperand(0);
588
589 if ((SetCC.getOpcode() != ISD::SETCC) ||
590 !SetCC.getOperand(0).getValueType().isInteger())
591 return SDValue();
592
593 SDValue False = N->getOperand(2);
594 EVT FalseTy = False.getValueType();
595
596 if (!FalseTy.isInteger())
597 return SDValue();
598
599 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
600
601 if (!CN || CN->getZExtValue())
602 return SDValue();
603
604 const DebugLoc DL = N->getDebugLoc();
605 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
606 SDValue True = N->getOperand(1);
607
608 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
609 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
610
611 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
612}
613
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000614static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG,
615 TargetLowering::DAGCombinerInfo &DCI,
616 const MipsSubtarget* Subtarget) {
617 // Pattern match EXT.
618 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
619 // => ext $dst, $src, size, pos
Akira Hatanaka56633442011-09-20 23:53:09 +0000620 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000621 return SDValue();
622
623 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000624 unsigned ShiftRightOpc = ShiftRight.getOpcode();
625
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000626 // Op's first operand must be a shift right.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000627 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000628 return SDValue();
629
630 // The second operand of the shift must be an immediate.
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000631 ConstantSDNode *CN;
632 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
633 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000634
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000635 uint64_t Pos = CN->getZExtValue();
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000636 uint64_t SMPos, SMSize;
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000637
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000638 // Op's second operand must be a shifted mask.
639 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000640 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000641 return SDValue();
642
643 // Return if the shifted mask does not start at bit 0 or the sum of its size
644 // and Pos exceeds the word's size.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000645 EVT ValTy = N->getValueType(0);
646 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000647 return SDValue();
648
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000649 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy,
Akira Hatanaka82099682011-12-19 19:52:25 +0000650 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
Akira Hatanaka667645f2011-08-17 22:59:46 +0000651 DAG.getConstant(SMSize, MVT::i32));
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000652}
Jia Liubb481f82012-02-28 07:46:26 +0000653
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000654static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
655 TargetLowering::DAGCombinerInfo &DCI,
656 const MipsSubtarget* Subtarget) {
657 // Pattern match INS.
658 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
Jia Liubb481f82012-02-28 07:46:26 +0000659 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000660 // => ins $dst, $src, size, pos, $src1
Akira Hatanaka56633442011-09-20 23:53:09 +0000661 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000662 return SDValue();
663
664 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
665 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
666 ConstantSDNode *CN;
667
668 // See if Op's first operand matches (and $src1 , mask0).
669 if (And0.getOpcode() != ISD::AND)
670 return SDValue();
671
672 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000673 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000674 return SDValue();
675
676 // See if Op's second operand matches (and (shl $src, pos), mask1).
677 if (And1.getOpcode() != ISD::AND)
678 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000679
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000680 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000681 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000682 return SDValue();
683
684 // The shift masks must have the same position and size.
685 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
686 return SDValue();
687
688 SDValue Shl = And1.getOperand(0);
689 if (Shl.getOpcode() != ISD::SHL)
690 return SDValue();
691
692 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
693 return SDValue();
694
695 unsigned Shamt = CN->getZExtValue();
696
697 // Return if the shift amount and the first bit position of mask are not the
Jia Liubb481f82012-02-28 07:46:26 +0000698 // same.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000699 EVT ValTy = N->getValueType(0);
700 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000701 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000702
Akira Hatanaka82099682011-12-19 19:52:25 +0000703 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0),
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000704 DAG.getConstant(SMPos0, MVT::i32),
Akira Hatanaka82099682011-12-19 19:52:25 +0000705 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000706}
Jia Liubb481f82012-02-28 07:46:26 +0000707
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000708SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000709 const {
710 SelectionDAG &DAG = DCI.DAG;
711 unsigned opc = N->getOpcode();
712
713 switch (opc) {
714 default: break;
715 case ISD::ADDE:
716 return PerformADDECombine(N, DAG, DCI, Subtarget);
717 case ISD::SUBE:
718 return PerformSUBECombine(N, DAG, DCI, Subtarget);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000719 case ISD::SDIVREM:
720 case ISD::UDIVREM:
721 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000722 case ISD::SELECT:
723 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000724 case ISD::AND:
725 return PerformANDCombine(N, DAG, DCI, Subtarget);
726 case ISD::OR:
727 return PerformORCombine(N, DAG, DCI, Subtarget);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000728 }
729
730 return SDValue();
731}
732
Dan Gohman475871a2008-07-27 21:46:04 +0000733SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +0000734LowerOperation(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000735{
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000736 switch (Op.getOpcode())
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000737 {
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000738 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000739 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
740 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000741 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +0000742 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000743 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
744 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000745 case ISD::SELECT: return LowerSELECT(Op, DAG);
Akira Hatanaka0a40c232012-03-09 23:46:03 +0000746 case ISD::SETCC: return LowerSETCC(Op, DAG);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000747 case ISD::VASTART: return LowerVASTART(Op, DAG);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +0000748 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
Akira Hatanakac12a6e62012-04-11 22:49:04 +0000749 case ISD::FABS: return LowerFABS(Op, DAG);
Akira Hatanaka2e591472011-06-02 00:24:44 +0000750 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Akira Hatanakadb548262011-07-19 23:30:50 +0000751 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
Eli Friedman14648462011-07-27 22:21:52 +0000752 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000753 }
Dan Gohman475871a2008-07-27 21:46:04 +0000754 return SDValue();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000755}
756
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000757//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000758// Lower helper functions
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000759//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000760
761// AddLiveIn - This helper function adds the specified physical register to the
762// MachineFunction as a live in value. It also creates a corresponding
763// virtual register for it.
764static unsigned
Craig Topper44d23822012-02-22 05:59:10 +0000765AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000766{
767 assert(RC->contains(PReg) && "Not the correct regclass!");
Chris Lattner84bc5422007-12-31 04:13:23 +0000768 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
769 MF.getRegInfo().addLiveIn(PReg, VReg);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000770 return VReg;
771}
772
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000773// Get fp branch code (not opcode) from condition code.
774static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
775 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
776 return Mips::BRANCH_T;
777
Akira Hatanaka82099682011-12-19 19:52:25 +0000778 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
779 "Invalid CondCode.");
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000780
Akira Hatanaka82099682011-12-19 19:52:25 +0000781 return Mips::BRANCH_F;
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000782}
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000783
Akira Hatanaka8ae330a2011-10-17 18:53:29 +0000784/*
Akira Hatanaka14487d42011-06-07 19:28:39 +0000785static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
786 DebugLoc dl,
787 const MipsSubtarget* Subtarget,
788 const TargetInstrInfo *TII,
789 bool isFPCmp, unsigned Opc) {
790 // There is no need to expand CMov instructions if target has
791 // conditional moves.
792 if (Subtarget->hasCondMov())
793 return BB;
794
795 // To "insert" a SELECT_CC instruction, we actually have to insert the
796 // diamond control-flow pattern. The incoming instruction knows the
797 // destination vreg to set, the condition code register to branch on, the
798 // true/false values to select between, and a branch opcode to use.
799 const BasicBlock *LLVM_BB = BB->getBasicBlock();
800 MachineFunction::iterator It = BB;
801 ++It;
802
803 // thisMBB:
804 // ...
805 // TrueVal = ...
806 // setcc r1, r2, r3
807 // bNE r1, r0, copy1MBB
808 // fallthrough --> copy0MBB
809 MachineBasicBlock *thisMBB = BB;
810 MachineFunction *F = BB->getParent();
811 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
812 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
813 F->insert(It, copy0MBB);
814 F->insert(It, sinkMBB);
815
816 // Transfer the remainder of BB and its successor edges to sinkMBB.
817 sinkMBB->splice(sinkMBB->begin(), BB,
818 llvm::next(MachineBasicBlock::iterator(MI)),
819 BB->end());
820 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
821
822 // Next, add the true and fallthrough blocks as its successors.
823 BB->addSuccessor(copy0MBB);
824 BB->addSuccessor(sinkMBB);
825
826 // Emit the right instruction according to the type of the operands compared
827 if (isFPCmp)
828 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
829 else
830 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
831 .addReg(Mips::ZERO).addMBB(sinkMBB);
832
833 // copy0MBB:
834 // %FalseValue = ...
835 // # fallthrough to sinkMBB
836 BB = copy0MBB;
837
838 // Update machine-CFG edges
839 BB->addSuccessor(sinkMBB);
840
841 // sinkMBB:
842 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
843 // ...
844 BB = sinkMBB;
845
846 if (isFPCmp)
847 BuildMI(*BB, BB->begin(), dl,
848 TII->get(Mips::PHI), MI->getOperand(0).getReg())
849 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
850 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
851 else
852 BuildMI(*BB, BB->begin(), dl,
853 TII->get(Mips::PHI), MI->getOperand(0).getReg())
854 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
855 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
856
857 MI->eraseFromParent(); // The pseudo instruction is gone now.
858 return BB;
859}
Akira Hatanaka8ae330a2011-10-17 18:53:29 +0000860*/
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000861MachineBasicBlock *
862MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
Dan Gohmanaf1d8ca2010-05-01 00:01:06 +0000863 MachineBasicBlock *BB) const {
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000864 switch (MI->getOpcode()) {
Craig Topperbc219812012-02-07 02:50:20 +0000865 default: llvm_unreachable("Unexpected instr type to insert");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000866 case Mips::ATOMIC_LOAD_ADD_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000867 case Mips::ATOMIC_LOAD_ADD_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000868 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
869 case Mips::ATOMIC_LOAD_ADD_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000870 case Mips::ATOMIC_LOAD_ADD_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000871 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
872 case Mips::ATOMIC_LOAD_ADD_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000873 case Mips::ATOMIC_LOAD_ADD_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000874 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
Akira Hatanaka59068062011-11-11 04:14:30 +0000875 case Mips::ATOMIC_LOAD_ADD_I64:
876 case Mips::ATOMIC_LOAD_ADD_I64_P8:
877 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000878
879 case Mips::ATOMIC_LOAD_AND_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000880 case Mips::ATOMIC_LOAD_AND_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000881 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
882 case Mips::ATOMIC_LOAD_AND_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000883 case Mips::ATOMIC_LOAD_AND_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000884 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
885 case Mips::ATOMIC_LOAD_AND_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000886 case Mips::ATOMIC_LOAD_AND_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000887 return EmitAtomicBinary(MI, BB, 4, Mips::AND);
Akira Hatanaka59068062011-11-11 04:14:30 +0000888 case Mips::ATOMIC_LOAD_AND_I64:
889 case Mips::ATOMIC_LOAD_AND_I64_P8:
Akira Hatanaka73866122011-11-12 02:38:12 +0000890 return EmitAtomicBinary(MI, BB, 8, Mips::AND64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000891
892 case Mips::ATOMIC_LOAD_OR_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000893 case Mips::ATOMIC_LOAD_OR_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000894 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
895 case Mips::ATOMIC_LOAD_OR_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000896 case Mips::ATOMIC_LOAD_OR_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000897 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
898 case Mips::ATOMIC_LOAD_OR_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000899 case Mips::ATOMIC_LOAD_OR_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000900 return EmitAtomicBinary(MI, BB, 4, Mips::OR);
Akira Hatanaka59068062011-11-11 04:14:30 +0000901 case Mips::ATOMIC_LOAD_OR_I64:
902 case Mips::ATOMIC_LOAD_OR_I64_P8:
903 return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000904
905 case Mips::ATOMIC_LOAD_XOR_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000906 case Mips::ATOMIC_LOAD_XOR_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000907 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
908 case Mips::ATOMIC_LOAD_XOR_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000909 case Mips::ATOMIC_LOAD_XOR_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000910 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
911 case Mips::ATOMIC_LOAD_XOR_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000912 case Mips::ATOMIC_LOAD_XOR_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000913 return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
Akira Hatanaka59068062011-11-11 04:14:30 +0000914 case Mips::ATOMIC_LOAD_XOR_I64:
915 case Mips::ATOMIC_LOAD_XOR_I64_P8:
916 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000917
918 case Mips::ATOMIC_LOAD_NAND_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000919 case Mips::ATOMIC_LOAD_NAND_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000920 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
921 case Mips::ATOMIC_LOAD_NAND_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000922 case Mips::ATOMIC_LOAD_NAND_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000923 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
924 case Mips::ATOMIC_LOAD_NAND_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000925 case Mips::ATOMIC_LOAD_NAND_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000926 return EmitAtomicBinary(MI, BB, 4, 0, true);
Akira Hatanaka59068062011-11-11 04:14:30 +0000927 case Mips::ATOMIC_LOAD_NAND_I64:
928 case Mips::ATOMIC_LOAD_NAND_I64_P8:
929 return EmitAtomicBinary(MI, BB, 8, 0, true);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000930
931 case Mips::ATOMIC_LOAD_SUB_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000932 case Mips::ATOMIC_LOAD_SUB_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000933 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
934 case Mips::ATOMIC_LOAD_SUB_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000935 case Mips::ATOMIC_LOAD_SUB_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000936 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
937 case Mips::ATOMIC_LOAD_SUB_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000938 case Mips::ATOMIC_LOAD_SUB_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000939 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
Akira Hatanaka59068062011-11-11 04:14:30 +0000940 case Mips::ATOMIC_LOAD_SUB_I64:
941 case Mips::ATOMIC_LOAD_SUB_I64_P8:
942 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000943
944 case Mips::ATOMIC_SWAP_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000945 case Mips::ATOMIC_SWAP_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000946 return EmitAtomicBinaryPartword(MI, BB, 1, 0);
947 case Mips::ATOMIC_SWAP_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000948 case Mips::ATOMIC_SWAP_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000949 return EmitAtomicBinaryPartword(MI, BB, 2, 0);
950 case Mips::ATOMIC_SWAP_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000951 case Mips::ATOMIC_SWAP_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000952 return EmitAtomicBinary(MI, BB, 4, 0);
Akira Hatanaka59068062011-11-11 04:14:30 +0000953 case Mips::ATOMIC_SWAP_I64:
954 case Mips::ATOMIC_SWAP_I64_P8:
955 return EmitAtomicBinary(MI, BB, 8, 0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000956
957 case Mips::ATOMIC_CMP_SWAP_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000958 case Mips::ATOMIC_CMP_SWAP_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000959 return EmitAtomicCmpSwapPartword(MI, BB, 1);
960 case Mips::ATOMIC_CMP_SWAP_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000961 case Mips::ATOMIC_CMP_SWAP_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000962 return EmitAtomicCmpSwapPartword(MI, BB, 2);
963 case Mips::ATOMIC_CMP_SWAP_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000964 case Mips::ATOMIC_CMP_SWAP_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000965 return EmitAtomicCmpSwap(MI, BB, 4);
Akira Hatanaka59068062011-11-11 04:14:30 +0000966 case Mips::ATOMIC_CMP_SWAP_I64:
967 case Mips::ATOMIC_CMP_SWAP_I64_P8:
968 return EmitAtomicCmpSwap(MI, BB, 8);
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000969 }
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000970}
971
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000972// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
973// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
974MachineBasicBlock *
975MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
Eric Christopher471e4222011-06-08 23:55:35 +0000976 unsigned Size, unsigned BinOpcode,
Akira Hatanaka0f843822011-06-07 18:58:42 +0000977 bool Nand) const {
Akira Hatanaka59068062011-11-11 04:14:30 +0000978 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000979
980 MachineFunction *MF = BB->getParent();
981 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Akira Hatanaka59068062011-11-11 04:14:30 +0000982 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000983 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
984 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +0000985 unsigned LL, SC, AND, NOR, ZERO, BEQ;
986
987 if (Size == 4) {
988 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
989 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
990 AND = Mips::AND;
991 NOR = Mips::NOR;
992 ZERO = Mips::ZERO;
993 BEQ = Mips::BEQ;
994 }
995 else {
996 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
997 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
998 AND = Mips::AND64;
999 NOR = Mips::NOR64;
1000 ZERO = Mips::ZERO_64;
1001 BEQ = Mips::BEQ64;
1002 }
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001003
Akira Hatanaka4061da12011-07-19 20:11:17 +00001004 unsigned OldVal = MI->getOperand(0).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001005 unsigned Ptr = MI->getOperand(1).getReg();
1006 unsigned Incr = MI->getOperand(2).getReg();
1007
Akira Hatanaka4061da12011-07-19 20:11:17 +00001008 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1009 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1010 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001011
1012 // insert new blocks after the current block
1013 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1014 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1015 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1016 MachineFunction::iterator It = BB;
1017 ++It;
1018 MF->insert(It, loopMBB);
1019 MF->insert(It, exitMBB);
1020
1021 // Transfer the remainder of BB and its successor edges to exitMBB.
1022 exitMBB->splice(exitMBB->begin(), BB,
1023 llvm::next(MachineBasicBlock::iterator(MI)),
1024 BB->end());
1025 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1026
1027 // thisMBB:
1028 // ...
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001029 // fallthrough --> loopMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001030 BB->addSuccessor(loopMBB);
Akira Hatanaka81b44112011-07-19 17:09:53 +00001031 loopMBB->addSuccessor(loopMBB);
1032 loopMBB->addSuccessor(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001033
1034 // loopMBB:
1035 // ll oldval, 0(ptr)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001036 // <binop> storeval, oldval, incr
1037 // sc success, storeval, 0(ptr)
1038 // beq success, $0, loopMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001039 BB = loopMBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001040 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001041 if (Nand) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001042 // and andres, oldval, incr
1043 // nor storeval, $0, andres
Akira Hatanaka59068062011-11-11 04:14:30 +00001044 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1045 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001046 } else if (BinOpcode) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001047 // <binop> storeval, oldval, incr
1048 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001049 } else {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001050 StoreVal = Incr;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001051 }
Akira Hatanaka59068062011-11-11 04:14:30 +00001052 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1053 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001054
1055 MI->eraseFromParent(); // The instruction is gone now.
1056
Akira Hatanaka939ece12011-07-19 03:42:13 +00001057 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001058}
1059
1060MachineBasicBlock *
1061MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001062 MachineBasicBlock *BB,
1063 unsigned Size, unsigned BinOpcode,
1064 bool Nand) const {
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001065 assert((Size == 1 || Size == 2) &&
1066 "Unsupported size for EmitAtomicBinaryPartial.");
1067
1068 MachineFunction *MF = BB->getParent();
1069 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1070 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1071 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1072 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001073 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1074 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001075
1076 unsigned Dest = MI->getOperand(0).getReg();
1077 unsigned Ptr = MI->getOperand(1).getReg();
1078 unsigned Incr = MI->getOperand(2).getReg();
1079
Akira Hatanaka4061da12011-07-19 20:11:17 +00001080 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1081 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001082 unsigned Mask = RegInfo.createVirtualRegister(RC);
1083 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001084 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1085 unsigned OldVal = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001086 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001087 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1088 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1089 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1090 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1091 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001092 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001093 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1094 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1095 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1096 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1097 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001098
1099 // insert new blocks after the current block
1100 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1101 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001102 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001103 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1104 MachineFunction::iterator It = BB;
1105 ++It;
1106 MF->insert(It, loopMBB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001107 MF->insert(It, sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001108 MF->insert(It, exitMBB);
1109
1110 // Transfer the remainder of BB and its successor edges to exitMBB.
1111 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001112 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001113 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1114
Akira Hatanaka81b44112011-07-19 17:09:53 +00001115 BB->addSuccessor(loopMBB);
1116 loopMBB->addSuccessor(loopMBB);
1117 loopMBB->addSuccessor(sinkMBB);
1118 sinkMBB->addSuccessor(exitMBB);
1119
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001120 // thisMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001121 // addiu masklsb2,$0,-4 # 0xfffffffc
1122 // and alignedaddr,ptr,masklsb2
1123 // andi ptrlsb2,ptr,3
1124 // sll shiftamt,ptrlsb2,3
1125 // ori maskupper,$0,255 # 0xff
1126 // sll mask,maskupper,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001127 // nor mask2,$0,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001128 // sll incr2,incr,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001129
1130 int64_t MaskImm = (Size == 1) ? 255 : 65535;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001131 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1132 .addReg(Mips::ZERO).addImm(-4);
1133 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1134 .addReg(Ptr).addReg(MaskLSB2);
1135 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1136 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1137 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1138 .addReg(Mips::ZERO).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001139 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1140 .addReg(ShiftAmt).addReg(MaskUpper);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001141 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001142 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
Bruno Cardoso Lopescada2d02011-05-31 20:25:26 +00001143
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001144 // atomic.load.binop
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001145 // loopMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001146 // ll oldval,0(alignedaddr)
1147 // binop binopres,oldval,incr2
1148 // and newval,binopres,mask
1149 // and maskedoldval0,oldval,mask2
1150 // or storeval,maskedoldval0,newval
1151 // sc success,storeval,0(alignedaddr)
1152 // beq success,$0,loopMBB
1153
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001154 // atomic.swap
1155 // loopMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001156 // ll oldval,0(alignedaddr)
Akira Hatanaka70564a92011-07-19 18:14:26 +00001157 // and newval,incr2,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001158 // and maskedoldval0,oldval,mask2
1159 // or storeval,maskedoldval0,newval
1160 // sc success,storeval,0(alignedaddr)
1161 // beq success,$0,loopMBB
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001162
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001163 BB = loopMBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001164 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001165 if (Nand) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001166 // and andres, oldval, incr2
1167 // nor binopres, $0, andres
1168 // and newval, binopres, mask
1169 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1170 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
1171 .addReg(Mips::ZERO).addReg(AndRes);
1172 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001173 } else if (BinOpcode) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001174 // <binop> binopres, oldval, incr2
1175 // and newval, binopres, mask
1176 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1177 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
Akira Hatanaka70564a92011-07-19 18:14:26 +00001178 } else {// atomic.swap
Akira Hatanaka4061da12011-07-19 20:11:17 +00001179 // and newval, incr2, mask
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001180 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
Akira Hatanaka70564a92011-07-19 18:14:26 +00001181 }
Jia Liubb481f82012-02-28 07:46:26 +00001182
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001183 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001184 .addReg(OldVal).addReg(Mask2);
1185 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001186 .addReg(MaskedOldVal0).addReg(NewVal);
Akira Hatanaka59068062011-11-11 04:14:30 +00001187 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001188 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001189 BuildMI(BB, dl, TII->get(Mips::BEQ))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001190 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001191
Akira Hatanaka939ece12011-07-19 03:42:13 +00001192 // sinkMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001193 // and maskedoldval1,oldval,mask
1194 // srl srlres,maskedoldval1,shiftamt
1195 // sll sllres,srlres,24
1196 // sra dest,sllres,24
Akira Hatanaka939ece12011-07-19 03:42:13 +00001197 BB = sinkMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001198 int64_t ShiftImm = (Size == 1) ? 24 : 16;
Akira Hatanakaa308c672011-07-19 03:14:58 +00001199
Akira Hatanaka4061da12011-07-19 20:11:17 +00001200 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1201 .addReg(OldVal).addReg(Mask);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001202 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1203 .addReg(ShiftAmt).addReg(MaskedOldVal1);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001204 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1205 .addReg(SrlRes).addImm(ShiftImm);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001206 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001207 .addReg(SllRes).addImm(ShiftImm);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001208
1209 MI->eraseFromParent(); // The instruction is gone now.
1210
Akira Hatanaka939ece12011-07-19 03:42:13 +00001211 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001212}
1213
1214MachineBasicBlock *
1215MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001216 MachineBasicBlock *BB,
1217 unsigned Size) const {
Akira Hatanaka59068062011-11-11 04:14:30 +00001218 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001219
1220 MachineFunction *MF = BB->getParent();
1221 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Akira Hatanaka59068062011-11-11 04:14:30 +00001222 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001223 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1224 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001225 unsigned LL, SC, ZERO, BNE, BEQ;
1226
1227 if (Size == 4) {
1228 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1229 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1230 ZERO = Mips::ZERO;
1231 BNE = Mips::BNE;
1232 BEQ = Mips::BEQ;
1233 }
1234 else {
1235 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1236 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1237 ZERO = Mips::ZERO_64;
1238 BNE = Mips::BNE64;
1239 BEQ = Mips::BEQ64;
1240 }
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001241
1242 unsigned Dest = MI->getOperand(0).getReg();
1243 unsigned Ptr = MI->getOperand(1).getReg();
Akira Hatanaka4061da12011-07-19 20:11:17 +00001244 unsigned OldVal = MI->getOperand(2).getReg();
1245 unsigned NewVal = MI->getOperand(3).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001246
Akira Hatanaka4061da12011-07-19 20:11:17 +00001247 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001248
1249 // insert new blocks after the current block
1250 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1251 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1252 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1253 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1254 MachineFunction::iterator It = BB;
1255 ++It;
1256 MF->insert(It, loop1MBB);
1257 MF->insert(It, loop2MBB);
1258 MF->insert(It, exitMBB);
1259
1260 // Transfer the remainder of BB and its successor edges to exitMBB.
1261 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001262 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001263 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1264
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001265 // thisMBB:
1266 // ...
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001267 // fallthrough --> loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001268 BB->addSuccessor(loop1MBB);
Akira Hatanaka81b44112011-07-19 17:09:53 +00001269 loop1MBB->addSuccessor(exitMBB);
1270 loop1MBB->addSuccessor(loop2MBB);
1271 loop2MBB->addSuccessor(loop1MBB);
1272 loop2MBB->addSuccessor(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001273
1274 // loop1MBB:
1275 // ll dest, 0(ptr)
1276 // bne dest, oldval, exitMBB
1277 BB = loop1MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001278 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1279 BuildMI(BB, dl, TII->get(BNE))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001280 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001281
1282 // loop2MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001283 // sc success, newval, 0(ptr)
1284 // beq success, $0, loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001285 BB = loop2MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001286 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001287 .addReg(NewVal).addReg(Ptr).addImm(0);
Akira Hatanaka59068062011-11-11 04:14:30 +00001288 BuildMI(BB, dl, TII->get(BEQ))
1289 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001290
1291 MI->eraseFromParent(); // The instruction is gone now.
1292
Akira Hatanaka939ece12011-07-19 03:42:13 +00001293 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001294}
1295
1296MachineBasicBlock *
1297MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001298 MachineBasicBlock *BB,
1299 unsigned Size) const {
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001300 assert((Size == 1 || Size == 2) &&
1301 "Unsupported size for EmitAtomicCmpSwapPartial.");
1302
1303 MachineFunction *MF = BB->getParent();
1304 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1305 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1306 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1307 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001308 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1309 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001310
1311 unsigned Dest = MI->getOperand(0).getReg();
1312 unsigned Ptr = MI->getOperand(1).getReg();
Akira Hatanaka4061da12011-07-19 20:11:17 +00001313 unsigned CmpVal = MI->getOperand(2).getReg();
1314 unsigned NewVal = MI->getOperand(3).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001315
Akira Hatanaka4061da12011-07-19 20:11:17 +00001316 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1317 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001318 unsigned Mask = RegInfo.createVirtualRegister(RC);
1319 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001320 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1321 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1322 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1323 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1324 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1325 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1326 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1327 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1328 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1329 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1330 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1331 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1332 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1333 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001334
1335 // insert new blocks after the current block
1336 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1337 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1338 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001339 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001340 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1341 MachineFunction::iterator It = BB;
1342 ++It;
1343 MF->insert(It, loop1MBB);
1344 MF->insert(It, loop2MBB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001345 MF->insert(It, sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001346 MF->insert(It, exitMBB);
1347
1348 // Transfer the remainder of BB and its successor edges to exitMBB.
1349 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001350 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001351 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1352
Akira Hatanaka81b44112011-07-19 17:09:53 +00001353 BB->addSuccessor(loop1MBB);
1354 loop1MBB->addSuccessor(sinkMBB);
1355 loop1MBB->addSuccessor(loop2MBB);
1356 loop2MBB->addSuccessor(loop1MBB);
1357 loop2MBB->addSuccessor(sinkMBB);
1358 sinkMBB->addSuccessor(exitMBB);
1359
Akira Hatanaka70564a92011-07-19 18:14:26 +00001360 // FIXME: computation of newval2 can be moved to loop2MBB.
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001361 // thisMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001362 // addiu masklsb2,$0,-4 # 0xfffffffc
1363 // and alignedaddr,ptr,masklsb2
1364 // andi ptrlsb2,ptr,3
1365 // sll shiftamt,ptrlsb2,3
1366 // ori maskupper,$0,255 # 0xff
1367 // sll mask,maskupper,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001368 // nor mask2,$0,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001369 // andi maskedcmpval,cmpval,255
1370 // sll shiftedcmpval,maskedcmpval,shiftamt
1371 // andi maskednewval,newval,255
1372 // sll shiftednewval,maskednewval,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001373 int64_t MaskImm = (Size == 1) ? 255 : 65535;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001374 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1375 .addReg(Mips::ZERO).addImm(-4);
1376 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1377 .addReg(Ptr).addReg(MaskLSB2);
1378 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1379 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1380 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1381 .addReg(Mips::ZERO).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001382 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1383 .addReg(ShiftAmt).addReg(MaskUpper);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001384 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001385 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
1386 .addReg(CmpVal).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001387 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
1388 .addReg(ShiftAmt).addReg(MaskedCmpVal);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001389 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
1390 .addReg(NewVal).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001391 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
1392 .addReg(ShiftAmt).addReg(MaskedNewVal);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001393
1394 // loop1MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001395 // ll oldval,0(alginedaddr)
1396 // and maskedoldval0,oldval,mask
1397 // bne maskedoldval0,shiftedcmpval,sinkMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001398 BB = loop1MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001399 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001400 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1401 .addReg(OldVal).addReg(Mask);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001402 BuildMI(BB, dl, TII->get(Mips::BNE))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001403 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001404
1405 // loop2MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001406 // and maskedoldval1,oldval,mask2
1407 // or storeval,maskedoldval1,shiftednewval
1408 // sc success,storeval,0(alignedaddr)
1409 // beq success,$0,loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001410 BB = loop2MBB;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001411 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1412 .addReg(OldVal).addReg(Mask2);
1413 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1414 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
Akira Hatanaka59068062011-11-11 04:14:30 +00001415 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001416 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001417 BuildMI(BB, dl, TII->get(Mips::BEQ))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001418 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001419
Akira Hatanaka939ece12011-07-19 03:42:13 +00001420 // sinkMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001421 // srl srlres,maskedoldval0,shiftamt
1422 // sll sllres,srlres,24
1423 // sra dest,sllres,24
Akira Hatanaka939ece12011-07-19 03:42:13 +00001424 BB = sinkMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001425 int64_t ShiftImm = (Size == 1) ? 24 : 16;
Akira Hatanakaa308c672011-07-19 03:14:58 +00001426
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001427 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1428 .addReg(ShiftAmt).addReg(MaskedOldVal0);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001429 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1430 .addReg(SrlRes).addImm(ShiftImm);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001431 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001432 .addReg(SllRes).addImm(ShiftImm);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001433
1434 MI->eraseFromParent(); // The instruction is gone now.
1435
Akira Hatanaka939ece12011-07-19 03:42:13 +00001436 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001437}
1438
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001439//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001440// Misc Lower Operation implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001441//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesd3bdf192009-05-27 17:23:44 +00001442SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001443LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001444{
Akira Hatanaka21afc632011-06-21 00:40:49 +00001445 MachineFunction &MF = DAG.getMachineFunction();
1446 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001447 unsigned SP = IsN64 ? Mips::SP_64 : Mips::SP;
Akira Hatanaka21afc632011-06-21 00:40:49 +00001448
1449 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >=
Akira Hatanaka053546c2011-05-25 02:20:00 +00001450 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() &&
1451 "Cannot lower if the alignment of the allocated space is larger than \
1452 that of the stack.");
1453
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001454 SDValue Chain = Op.getOperand(0);
1455 SDValue Size = Op.getOperand(1);
Dale Johannesena05dca42009-02-04 23:02:30 +00001456 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001457
1458 // Get a reference from Mips stack pointer
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001459 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SP, getPointerTy());
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001460
1461 // Subtract the dynamic size from the actual stack size to
1462 // obtain the new stack size.
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001463 SDValue Sub = DAG.getNode(ISD::SUB, dl, getPointerTy(), StackPointer, Size);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001464
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001465 // The Sub result contains the new stack start address, so it
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001466 // must be placed in the stack pointer register.
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001467 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, SP, Sub, SDValue());
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001468
1469 // This node always has two return values: a new stack pointer
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001470 // value and a chain
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001471 SDVTList VTLs = DAG.getVTList(getPointerTy(), MVT::Other);
Akira Hatanaka21afc632011-06-21 00:40:49 +00001472 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy());
1473 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) };
1474
1475 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001476}
1477
1478SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001479LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001480{
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001481 // The first operand is the chain, the second is the condition, the third is
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001482 // the block to branch to if the condition is true.
1483 SDValue Chain = Op.getOperand(0);
1484 SDValue Dest = Op.getOperand(2);
Dale Johannesende064702009-02-06 21:50:26 +00001485 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001486
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001487 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
1488
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001489 // Return if flag is not set by a floating point comparison.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001490 if (CondRes.getOpcode() != MipsISD::FPCmp)
Bruno Cardoso Lopes4b877ca2008-07-30 17:06:13 +00001491 return Op;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001492
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +00001493 SDValue CCNode = CondRes.getOperand(2);
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001494 Mips::CondCode CC =
1495 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001496 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001497
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001498 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001499 Dest, CondRes);
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001500}
1501
1502SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001503LowerSELECT(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001504{
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001505 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001506
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001507 // Return if flag is not set by a floating point comparison.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001508 if (Cond.getOpcode() != MipsISD::FPCmp)
1509 return Op;
Bruno Cardoso Lopes739e4412008-08-13 07:13:40 +00001510
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001511 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1512 Op.getDebugLoc());
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001513}
1514
Akira Hatanaka0a40c232012-03-09 23:46:03 +00001515SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1516 SDValue Cond = CreateFPCmp(DAG, Op);
1517
1518 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1519 "Floating point operand expected.");
1520
1521 SDValue True = DAG.getConstant(1, MVT::i32);
1522 SDValue False = DAG.getConstant(0, MVT::i32);
1523
1524 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc());
1525}
1526
Dan Gohmand858e902010-04-17 15:26:15 +00001527SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
1528 SelectionDAG &DAG) const {
Dale Johannesende064702009-02-06 21:50:26 +00001529 // FIXME there isn't actually debug info here
Dale Johannesen33c960f2009-02-04 20:06:27 +00001530 DebugLoc dl = Op.getDebugLoc();
Jia Liubb481f82012-02-28 07:46:26 +00001531 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001532
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001533 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Chris Lattnere3736f82009-08-13 05:41:27 +00001534 SDVTList VTs = DAG.getVTList(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001535
Chris Lattnerb71b9092009-08-13 06:28:06 +00001536 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001537
Chris Lattnere3736f82009-08-13 05:41:27 +00001538 // %gp_rel relocation
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001539 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1540 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00001541 MipsII::MO_GPREL);
Chris Lattnere3736f82009-08-13 05:41:27 +00001542 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
1543 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001544 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
Chris Lattnere3736f82009-08-13 05:41:27 +00001545 }
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001546 // %hi/%lo relocation
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001547 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1548 MipsII::MO_ABS_HI);
1549 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1550 MipsII::MO_ABS_LO);
1551 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
1552 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
Owen Anderson825b72b2009-08-11 20:47:22 +00001553 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001554 }
1555
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001556 EVT ValTy = Op.getValueType();
1557 bool HasGotOfst = (GV->hasInternalLinkage() ||
1558 (GV->hasLocalLinkage() && !isa<Function>(GV)));
Akira Hatanaka56ce6b32012-04-04 22:16:36 +00001559 unsigned GotFlag = HasMips64 ?
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001560 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) :
Bruno Cardoso Lopese3d35722011-12-07 00:28:57 +00001561 (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16);
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001562 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001563 GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), GA);
Akira Hatanaka82099682011-12-19 19:52:25 +00001564 SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA,
1565 MachinePointerInfo(), false, false, false, 0);
Akira Hatanaka0f843822011-06-07 18:58:42 +00001566 // On functions and global targets not internal linked only
1567 // a load from got/GP is necessary for PIC to work.
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001568 if (!HasGotOfst)
Akira Hatanaka0f843822011-06-07 18:58:42 +00001569 return ResNode;
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001570 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0,
Akira Hatanaka56ce6b32012-04-04 22:16:36 +00001571 HasMips64 ? MipsII::MO_GOT_OFST :
1572 MipsII::MO_ABS_LO);
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001573 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo);
1574 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001575}
1576
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001577SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
1578 SelectionDAG &DAG) const {
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001579 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1580 // FIXME there isn't actually debug info here
1581 DebugLoc dl = Op.getDebugLoc();
1582
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001583 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001584 // %hi/%lo relocation
Akira Hatanaka82099682011-12-19 19:52:25 +00001585 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_HI);
1586 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_LO);
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001587 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
1588 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
1589 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001590 }
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001591
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001592 EVT ValTy = Op.getValueType();
Akira Hatanaka03d830e2012-04-04 18:22:53 +00001593 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1594 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001595 SDValue BAGOTOffset = DAG.getBlockAddress(BA, ValTy, true, GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001596 BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy,
1597 GetGlobalReg(DAG, ValTy), BAGOTOffset);
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001598 SDValue BALOOffset = DAG.getBlockAddress(BA, ValTy, true, OFSTFlag);
Akira Hatanaka82099682011-12-19 19:52:25 +00001599 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset,
Pete Cooperd752e0f2011-11-08 18:42:53 +00001600 MachinePointerInfo(), false, false, false, 0);
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001601 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset);
1602 return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001603}
1604
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001605SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001606LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001607{
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001608 // If the relocation model is PIC, use the General Dynamic TLS Model or
1609 // Local Dynamic TLS model, otherwise use the Initial Exec or
1610 // Local Exec TLS Model.
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001611
1612 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1613 DebugLoc dl = GA->getDebugLoc();
1614 const GlobalValue *GV = GA->getGlobal();
1615 EVT PtrVT = getPointerTy();
1616
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001617 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1618
1619 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001620 // General Dynamic TLS Model
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001621 bool LocalDynamic = GV->hasInternalLinkage();
1622 unsigned Flag = LocalDynamic ? MipsII::MO_TLSLDM :MipsII::MO_TLSGD;
1623 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001624 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT,
1625 GetGlobalReg(DAG, PtrVT), TGA);
Akira Hatanaka7a7194b2011-12-08 21:05:38 +00001626 unsigned PtrSize = PtrVT.getSizeInBits();
1627 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1628
Benjamin Kramer5eccf672011-12-11 12:21:34 +00001629 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001630
1631 ArgListTy Args;
1632 ArgListEntry Entry;
1633 Entry.Node = Argument;
Akira Hatanakaca074792011-12-08 20:34:32 +00001634 Entry.Ty = PtrTy;
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001635 Args.push_back(Entry);
Jia Liubb481f82012-02-28 07:46:26 +00001636
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001637 std::pair<SDValue, SDValue> CallResult =
Akira Hatanakaca074792011-12-08 20:34:32 +00001638 LowerCallTo(DAG.getEntryNode(), PtrTy,
Evan Cheng4bfcd4a2012-02-28 18:51:51 +00001639 false, false, false, false, 0, CallingConv::C,
1640 /*isTailCall=*/false, /*doesNotRet=*/false,
1641 /*isReturnValueUsed=*/true,
Akira Hatanaka7a7194b2011-12-08 21:05:38 +00001642 TlsGetAddr, Args, DAG, dl);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001643
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001644 SDValue Ret = CallResult.first;
1645
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001646 if (model != TLSModel::LocalDynamic)
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001647 return Ret;
1648
1649 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1650 MipsII::MO_DTPREL_HI);
1651 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1652 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1653 MipsII::MO_DTPREL_LO);
1654 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1655 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret);
1656 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001657 }
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001658
1659 SDValue Offset;
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001660 if (model == TLSModel::InitialExec) {
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001661 // Initial Exec TLS Model
Akira Hatanakaca074792011-12-08 20:34:32 +00001662 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001663 MipsII::MO_GOTTPREL);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001664 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1665 TGA);
Akira Hatanakaca074792011-12-08 20:34:32 +00001666 Offset = DAG.getLoad(PtrVT, dl,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001667 DAG.getEntryNode(), TGA, MachinePointerInfo(),
Pete Cooperd752e0f2011-11-08 18:42:53 +00001668 false, false, false, 0);
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001669 } else {
1670 // Local Exec TLS Model
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001671 assert(model == TLSModel::LocalExec);
Akira Hatanakaca074792011-12-08 20:34:32 +00001672 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001673 MipsII::MO_TPREL_HI);
Akira Hatanakaca074792011-12-08 20:34:32 +00001674 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001675 MipsII::MO_TPREL_LO);
Akira Hatanakaca074792011-12-08 20:34:32 +00001676 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1677 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1678 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001679 }
1680
1681 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
1682 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001683}
1684
1685SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001686LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001687{
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001688 SDValue HiPart, JTI, JTILo;
Dale Johannesende064702009-02-06 21:50:26 +00001689 // FIXME there isn't actually debug info here
Dale Johannesen33c960f2009-02-04 20:06:27 +00001690 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00001691 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Owen Andersone50ed302009-08-10 22:56:29 +00001692 EVT PtrVT = Op.getValueType();
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001693 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001694
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001695 if (!IsPIC && !IsN64) {
1696 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI);
1697 HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI);
1698 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO);
Akira Hatanaka342837d2011-05-28 01:07:07 +00001699 } else {// Emit Load from Global Pointer
Akira Hatanakac75ceb72012-04-04 18:31:32 +00001700 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1701 unsigned OfstFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001702 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001703 JTI = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1704 JTI);
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001705 HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI,
1706 MachinePointerInfo(), false, false, false, 0);
1707 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag);
Akira Hatanaka342837d2011-05-28 01:07:07 +00001708 }
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001709
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001710 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo);
1711 return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo);
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001712}
1713
Dan Gohman475871a2008-07-27 21:46:04 +00001714SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001715LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +00001716{
Dan Gohman475871a2008-07-27 21:46:04 +00001717 SDValue ResNode;
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001718 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
Dan Gohman46510a72010-04-15 01:51:59 +00001719 const Constant *C = N->getConstVal();
Dale Johannesende064702009-02-06 21:50:26 +00001720 // FIXME there isn't actually debug info here
1721 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001722
1723 // gp_rel relocation
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001724 // FIXME: we should reference the constant pool using small data sections,
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001725 // but the asm printer currently doesn't support this feature without
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001726 // hacking it. This feature should come soon so we can uncomment the
Bruno Cardoso Lopesf33bc432008-07-28 19:26:25 +00001727 // stuff below.
Eli Friedmane2c74082009-08-03 02:22:28 +00001728 //if (IsInSmallSection(C->getType())) {
Owen Anderson825b72b2009-08-11 20:47:22 +00001729 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1730 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001731 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001732
Akira Hatanaka13daee32012-03-27 02:55:31 +00001733 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001734 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001735 N->getOffset(), MipsII::MO_ABS_HI);
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001736 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001737 N->getOffset(), MipsII::MO_ABS_LO);
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001738 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
1739 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
Owen Anderson825b72b2009-08-11 20:47:22 +00001740 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001741 } else {
Akira Hatanaka620db892011-11-16 22:44:38 +00001742 EVT ValTy = Op.getValueType();
Akira Hatanaka86a27332012-04-04 18:26:12 +00001743 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1744 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Akira Hatanaka620db892011-11-16 22:44:38 +00001745 SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1746 N->getOffset(), GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001747 CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), CP);
Akira Hatanaka82099682011-12-19 19:52:25 +00001748 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP,
1749 MachinePointerInfo::getConstantPool(), false,
1750 false, false, 0);
Akira Hatanaka620db892011-11-16 22:44:38 +00001751 SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1752 N->getOffset(), OFSTFlag);
1753 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo);
1754 ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001755 }
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001756
1757 return ResNode;
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +00001758}
1759
Dan Gohmand858e902010-04-17 15:26:15 +00001760SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
Dan Gohman1e93df62010-04-17 14:41:14 +00001761 MachineFunction &MF = DAG.getMachineFunction();
1762 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1763
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001764 DebugLoc dl = Op.getDebugLoc();
Dan Gohman1e93df62010-04-17 14:41:14 +00001765 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1766 getPointerTy());
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001767
1768 // vastart just stores the address of the VarArgsFrameIndex slot into the
1769 // memory location argument.
1770 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Chris Lattner8026a9d2010-09-21 17:50:43 +00001771 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
Akira Hatanaka82099682011-12-19 19:52:25 +00001772 MachinePointerInfo(SV), false, false, 0);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001773}
Jia Liubb481f82012-02-28 07:46:26 +00001774
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001775static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1776 EVT TyX = Op.getOperand(0).getValueType();
1777 EVT TyY = Op.getOperand(1).getValueType();
1778 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1779 SDValue Const31 = DAG.getConstant(31, MVT::i32);
1780 DebugLoc DL = Op.getDebugLoc();
1781 SDValue Res;
1782
1783 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1784 // to i32.
1785 SDValue X = (TyX == MVT::f32) ?
1786 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1787 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1788 Const1);
1789 SDValue Y = (TyY == MVT::f32) ?
1790 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1791 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1792 Const1);
1793
1794 if (HasR2) {
1795 // ext E, Y, 31, 1 ; extract bit31 of Y
1796 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1797 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1798 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1799 } else {
1800 // sll SllX, X, 1
1801 // srl SrlX, SllX, 1
1802 // srl SrlY, Y, 31
1803 // sll SllY, SrlX, 31
1804 // or Or, SrlX, SllY
1805 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1806 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1807 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1808 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1809 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1810 }
1811
1812 if (TyX == MVT::f32)
1813 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1814
1815 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1816 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1817 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001818}
1819
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001820static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1821 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1822 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1823 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1824 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1825 DebugLoc DL = Op.getDebugLoc();
Eric Christopher471e4222011-06-08 23:55:35 +00001826
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001827 // Bitcast to integer nodes.
1828 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1829 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001830
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001831 if (HasR2) {
1832 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1833 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1834 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1835 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001836
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001837 if (WidthX > WidthY)
1838 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1839 else if (WidthY > WidthX)
1840 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001841
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001842 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1843 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
1844 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1845 }
1846
1847 // (d)sll SllX, X, 1
1848 // (d)srl SrlX, SllX, 1
1849 // (d)srl SrlY, Y, width(Y)-1
1850 // (d)sll SllY, SrlX, width(Y)-1
1851 // or Or, SrlX, SllY
1852 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1853 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1854 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1855 DAG.getConstant(WidthY - 1, MVT::i32));
1856
1857 if (WidthX > WidthY)
1858 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1859 else if (WidthY > WidthX)
1860 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1861
1862 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1863 DAG.getConstant(WidthX - 1, MVT::i32));
1864 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1865 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001866}
1867
Akira Hatanaka82099682011-12-19 19:52:25 +00001868SDValue
1869MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001870 if (Subtarget->hasMips64())
1871 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001872
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001873 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001874}
1875
Akira Hatanakac12a6e62012-04-11 22:49:04 +00001876static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1877 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1878 DebugLoc DL = Op.getDebugLoc();
1879
1880 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1881 // to i32.
1882 SDValue X = (Op.getValueType() == MVT::f32) ?
1883 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1884 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1885 Const1);
1886
1887 // Clear MSB.
1888 if (HasR2)
1889 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
1890 DAG.getRegister(Mips::ZERO, MVT::i32),
1891 DAG.getConstant(31, MVT::i32), Const1, X);
1892 else {
1893 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1894 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1895 }
1896
1897 if (Op.getValueType() == MVT::f32)
1898 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
1899
1900 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1901 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1902 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1903}
1904
1905static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1906 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1907 DebugLoc DL = Op.getDebugLoc();
1908
1909 // Bitcast to integer node.
1910 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
1911
1912 // Clear MSB.
1913 if (HasR2)
1914 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
1915 DAG.getRegister(Mips::ZERO_64, MVT::i64),
1916 DAG.getConstant(63, MVT::i32), Const1, X);
1917 else {
1918 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
1919 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
1920 }
1921
1922 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
1923}
1924
1925SDValue
1926MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
1927 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
1928 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2());
1929
1930 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2());
1931}
1932
Akira Hatanaka2e591472011-06-02 00:24:44 +00001933SDValue MipsTargetLowering::
1934LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
Bruno Cardoso Lopese0b5cfc2011-06-16 00:40:02 +00001935 // check the depth
1936 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
Akira Hatanaka0f843822011-06-07 18:58:42 +00001937 "Frame address can only be determined for current frame.");
Akira Hatanaka2e591472011-06-02 00:24:44 +00001938
1939 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1940 MFI->setFrameAddressIsTaken(true);
1941 EVT VT = Op.getValueType();
1942 DebugLoc dl = Op.getDebugLoc();
Akira Hatanaka46ac4392011-11-11 04:11:56 +00001943 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1944 IsN64 ? Mips::FP_64 : Mips::FP, VT);
Akira Hatanaka2e591472011-06-02 00:24:44 +00001945 return FrameAddr;
1946}
1947
Akira Hatanakadb548262011-07-19 23:30:50 +00001948// TODO: set SType according to the desired memory barrier behavior.
Akira Hatanaka82099682011-12-19 19:52:25 +00001949SDValue
1950MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const {
Akira Hatanakadb548262011-07-19 23:30:50 +00001951 unsigned SType = 0;
1952 DebugLoc dl = Op.getDebugLoc();
1953 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
1954 DAG.getConstant(SType, MVT::i32));
1955}
1956
Eli Friedman14648462011-07-27 22:21:52 +00001957SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
1958 SelectionDAG& DAG) const {
1959 // FIXME: Need pseudo-fence for 'singlethread' fences
1960 // FIXME: Set SType for weaker fences where supported/appropriate.
1961 unsigned SType = 0;
1962 DebugLoc dl = Op.getDebugLoc();
1963 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
1964 DAG.getConstant(SType, MVT::i32));
1965}
1966
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001967//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001968// Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001969//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001970
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001971//===----------------------------------------------------------------------===//
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001972// TODO: Implement a generic logic using tblgen that can support this.
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001973// Mips O32 ABI rules:
1974// ---
1975// i32 - Passed in A0, A1, A2, A3 and stack
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001976// f32 - Only passed in f32 registers if no int reg has been used yet to hold
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001977// an argument. Otherwise, passed in A1, A2, A3 and stack.
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001978// f64 - Only passed in two aliased f32 registers if no int reg has been used
1979// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001980// not used, it must be shadowed. If only A3 is avaiable, shadow it and
1981// go to stack.
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00001982//
1983// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001984//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001985
Duncan Sands1e96bab2010-11-04 10:49:57 +00001986static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
Duncan Sands1440e8b2010-11-03 11:35:31 +00001987 MVT LocVT, CCValAssign::LocInfo LocInfo,
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001988 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1989
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001990 static const unsigned IntRegsSize=4, FloatRegsSize=2;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001991
Craig Topperc5eaae42012-03-11 07:57:25 +00001992 static const uint16_t IntRegs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001993 Mips::A0, Mips::A1, Mips::A2, Mips::A3
1994 };
Craig Topperc5eaae42012-03-11 07:57:25 +00001995 static const uint16_t F32Regs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001996 Mips::F12, Mips::F14
1997 };
Craig Topperc5eaae42012-03-11 07:57:25 +00001998 static const uint16_t F64Regs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00001999 Mips::D6, Mips::D7
2000 };
2001
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002002 // ByVal Args
2003 if (ArgFlags.isByVal()) {
2004 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo,
2005 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags);
2006 unsigned NextReg = (State.getNextStackOffset() + 3) / 4;
2007 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize);
2008 r < std::min(IntRegsSize, NextReg); ++r)
2009 State.AllocateReg(IntRegs[r]);
2010 return false;
2011 }
2012
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002013 // Promote i8 and i16
2014 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2015 LocVT = MVT::i32;
2016 if (ArgFlags.isSExt())
2017 LocInfo = CCValAssign::SExt;
2018 else if (ArgFlags.isZExt())
2019 LocInfo = CCValAssign::ZExt;
2020 else
2021 LocInfo = CCValAssign::AExt;
2022 }
2023
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002024 unsigned Reg;
2025
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002026 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2027 // is true: function is vararg, argument is 3rd or higher, there is previous
2028 // argument which is not f32 or f64.
2029 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
2030 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
Akira Hatanakaa1a7ba82011-05-19 20:29:48 +00002031 unsigned OrigAlign = ArgFlags.getOrigAlign();
2032 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002033
2034 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002035 Reg = State.AllocateReg(IntRegs, IntRegsSize);
Akira Hatanakaa1a7ba82011-05-19 20:29:48 +00002036 // If this is the first part of an i64 arg,
2037 // the allocated register must be either A0 or A2.
2038 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2039 Reg = State.AllocateReg(IntRegs, IntRegsSize);
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002040 LocVT = MVT::i32;
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002041 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2042 // Allocate int register and shadow next int register. If first
2043 // available register is Mips::A1 or Mips::A3, shadow it too.
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002044 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2045 if (Reg == Mips::A1 || Reg == Mips::A3)
2046 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2047 State.AllocateReg(IntRegs, IntRegsSize);
2048 LocVT = MVT::i32;
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002049 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2050 // we are guaranteed to find an available float register
2051 if (ValVT == MVT::f32) {
2052 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2053 // Shadow int register
2054 State.AllocateReg(IntRegs, IntRegsSize);
2055 } else {
2056 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2057 // Shadow int registers
2058 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2059 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2060 State.AllocateReg(IntRegs, IntRegsSize);
2061 State.AllocateReg(IntRegs, IntRegsSize);
2062 }
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002063 } else
2064 llvm_unreachable("Cannot handle this ValVT.");
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002065
Akira Hatanakad37776d2011-05-20 21:39:54 +00002066 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
2067 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign);
2068
2069 if (!Reg)
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002070 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
Akira Hatanakad37776d2011-05-20 21:39:54 +00002071 else
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002072 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002073
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002074 return false; // CC must always match
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002075}
2076
Craig Topperc5eaae42012-03-11 07:57:25 +00002077static const uint16_t Mips64IntRegs[8] =
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002078 {Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
2079 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
Craig Topperc5eaae42012-03-11 07:57:25 +00002080static const uint16_t Mips64DPRegs[8] =
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002081 {Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
2082 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64};
2083
2084static bool CC_Mips64Byval(unsigned ValNo, MVT ValVT, MVT LocVT,
2085 CCValAssign::LocInfo LocInfo,
2086 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2087 unsigned Align = std::max(ArgFlags.getByValAlign(), (unsigned)8);
2088 unsigned Size = (ArgFlags.getByValSize() + 7) / 8 * 8;
2089 unsigned FirstIdx = State.getFirstUnallocated(Mips64IntRegs, 8);
2090
2091 assert(Align <= 16 && "Cannot handle alignments larger than 16.");
2092
Jia Liubb481f82012-02-28 07:46:26 +00002093 // If byval is 16-byte aligned, the first arg register must be even.
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002094 if ((Align == 16) && (FirstIdx % 2)) {
2095 State.AllocateReg(Mips64IntRegs[FirstIdx], Mips64DPRegs[FirstIdx]);
2096 ++FirstIdx;
2097 }
2098
2099 // Mark the registers allocated.
2100 for (unsigned I = FirstIdx; Size && (I < 8); Size -= 8, ++I)
2101 State.AllocateReg(Mips64IntRegs[I], Mips64DPRegs[I]);
2102
2103 // Allocate space on caller's stack.
2104 unsigned Offset = State.AllocateStack(Size, Align);
Jia Liubb481f82012-02-28 07:46:26 +00002105
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002106 if (FirstIdx < 8)
2107 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Mips64IntRegs[FirstIdx],
Jia Liubb481f82012-02-28 07:46:26 +00002108 LocVT, LocInfo));
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002109 else
2110 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2111
2112 return true;
2113}
2114
2115#include "MipsGenCallingConv.inc"
2116
Akira Hatanaka49617092011-11-14 19:02:54 +00002117static void
Akira Hatanaka08067b22012-01-24 22:07:36 +00002118AnalyzeMips64CallOperands(CCState &CCInfo,
Akira Hatanaka49617092011-11-14 19:02:54 +00002119 const SmallVectorImpl<ISD::OutputArg> &Outs) {
2120 unsigned NumOps = Outs.size();
2121 for (unsigned i = 0; i != NumOps; ++i) {
2122 MVT ArgVT = Outs[i].VT;
2123 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2124 bool R;
2125
2126 if (Outs[i].IsFixed)
2127 R = CC_MipsN(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2128 else
2129 R = CC_MipsN_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
Jia Liubb481f82012-02-28 07:46:26 +00002130
Akira Hatanaka49617092011-11-14 19:02:54 +00002131 if (R) {
Benjamin Kramer6296ee32011-11-14 19:51:48 +00002132#ifndef NDEBUG
Akira Hatanaka49617092011-11-14 19:02:54 +00002133 dbgs() << "Call operand #" << i << " has unhandled type "
2134 << EVT(ArgVT).getEVTString();
2135#endif
2136 llvm_unreachable(0);
2137 }
2138 }
2139}
2140
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002141//===----------------------------------------------------------------------===//
Dan Gohman98ca4f22009-08-05 01:29:28 +00002142// Call Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002143//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002144
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002145static const unsigned O32IntRegsSize = 4;
2146
Craig Topperc5eaae42012-03-11 07:57:25 +00002147static const uint16_t O32IntRegs[] = {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002148 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2149};
2150
Akira Hatanaka373e3a42011-09-23 00:58:33 +00002151// Return next O32 integer argument register.
2152static unsigned getNextIntArgReg(unsigned Reg) {
2153 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2154 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2155}
2156
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002157// Write ByVal Arg to arg registers and stack.
2158static void
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002159WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl,
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002160 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass,
2161 SmallVector<SDValue, 8>& MemOpChains, int& LastFI,
2162 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
Akira Hatanakaedacba82011-05-25 17:32:06 +00002163 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002164 MVT PtrType, bool isLittle) {
2165 unsigned LocMemOffset = VA.getLocMemOffset();
2166 unsigned Offset = 0;
2167 uint32_t RemainingSize = Flags.getByValSize();
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +00002168 unsigned ByValAlign = Flags.getByValAlign();
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002169
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002170 // Copy the first 4 words of byval arg to registers A0 - A3.
2171 // FIXME: Use a stricter alignment if it enables better optimization in passes
2172 // run later.
2173 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4;
2174 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002175 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002176 DAG.getConstant(Offset, MVT::i32));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002177 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
Akira Hatanaka82099682011-12-19 19:52:25 +00002178 MachinePointerInfo(), false, false, false,
2179 std::min(ByValAlign, (unsigned )4));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002180 MemOpChains.push_back(LoadVal.getValue(1));
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002181 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002182 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
2183 }
2184
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002185 if (RemainingSize == 0)
2186 return;
2187
2188 // If there still is a register available for argument passing, write the
2189 // remaining part of the structure to it using subword loads and shifts.
2190 if (LocMemOffset < 4 * 4) {
2191 assert(RemainingSize <= 3 && RemainingSize >= 1 &&
2192 "There must be one to three bytes remaining.");
2193 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize);
2194 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2195 DAG.getConstant(Offset, MVT::i32));
2196 unsigned Alignment = std::min(ByValAlign, (unsigned )4);
2197 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
2198 LoadPtr, MachinePointerInfo(),
2199 MVT::getIntegerVT(LoadSize * 8), false,
2200 false, Alignment);
2201 MemOpChains.push_back(LoadVal.getValue(1));
2202
2203 // If target is big endian, shift it to the most significant half-word or
2204 // byte.
2205 if (!isLittle)
2206 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal,
2207 DAG.getConstant(32 - LoadSize * 8, MVT::i32));
2208
2209 Offset += LoadSize;
2210 RemainingSize -= LoadSize;
2211
2212 // Read second subword if necessary.
2213 if (RemainingSize != 0) {
2214 assert(RemainingSize == 1 && "There must be one byte remaining.");
Jia Liubb481f82012-02-28 07:46:26 +00002215 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002216 DAG.getConstant(Offset, MVT::i32));
2217 unsigned Alignment = std::min(ByValAlign, (unsigned )2);
2218 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
2219 LoadPtr, MachinePointerInfo(),
2220 MVT::i8, false, false, Alignment);
2221 MemOpChains.push_back(Subword.getValue(1));
2222 // Insert the loaded byte to LoadVal.
2223 // FIXME: Use INS if supported by target.
2224 unsigned ShiftAmt = isLittle ? 16 : 8;
2225 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword,
2226 DAG.getConstant(ShiftAmt, MVT::i32));
2227 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift);
2228 }
2229
2230 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
2231 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
2232 return;
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002233 }
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002234
2235 // Create a fixed object on stack at offset LocMemOffset and copy
2236 // remaining part of byval arg to it using memcpy.
2237 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2238 DAG.getConstant(Offset, MVT::i32));
2239 LastFI = MFI->CreateFixedObject(RemainingSize, LocMemOffset, true);
2240 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType);
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002241 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src,
2242 DAG.getConstant(RemainingSize, MVT::i32),
2243 std::min(ByValAlign, (unsigned)4),
2244 /*isVolatile=*/false, /*AlwaysInline=*/false,
2245 MachinePointerInfo(0), MachinePointerInfo(0));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002246}
2247
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002248// Copy Mips64 byVal arg to registers and stack.
2249void static
2250PassByValArg64(SDValue& ByValChain, SDValue Chain, DebugLoc dl,
2251 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass,
2252 SmallVector<SDValue, 8>& MemOpChains, int& LastFI,
2253 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
2254 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
2255 EVT PtrTy, bool isLittle) {
2256 unsigned ByValSize = Flags.getByValSize();
2257 unsigned Alignment = std::min(Flags.getByValAlign(), (unsigned)8);
2258 bool IsRegLoc = VA.isRegLoc();
2259 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
2260 unsigned LocMemOffset = 0;
Akira Hatanaka16040852011-11-15 18:42:25 +00002261 unsigned MemCpySize = ByValSize;
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002262
2263 if (!IsRegLoc)
2264 LocMemOffset = VA.getLocMemOffset();
2265 else {
Craig Topperc5eaae42012-03-11 07:57:25 +00002266 const uint16_t *Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8,
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002267 VA.getLocReg());
Craig Topperc5eaae42012-03-11 07:57:25 +00002268 const uint16_t *RegEnd = Mips64IntRegs + 8;
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002269
2270 // Copy double words to registers.
2271 for (; (Reg != RegEnd) && (ByValSize >= Offset + 8); ++Reg, Offset += 8) {
2272 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2273 DAG.getConstant(Offset, PtrTy));
2274 SDValue LoadVal = DAG.getLoad(MVT::i64, dl, Chain, LoadPtr,
2275 MachinePointerInfo(), false, false, false,
2276 Alignment);
2277 MemOpChains.push_back(LoadVal.getValue(1));
2278 RegsToPass.push_back(std::make_pair(*Reg, LoadVal));
2279 }
2280
Jia Liubb481f82012-02-28 07:46:26 +00002281 // Return if the struct has been fully copied.
Akira Hatanaka16040852011-11-15 18:42:25 +00002282 if (!(MemCpySize = ByValSize - Offset))
2283 return;
2284
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002285 // If there is an argument register available, copy the remainder of the
2286 // byval argument with sub-doubleword loads and shifts.
Akira Hatanaka16040852011-11-15 18:42:25 +00002287 if (Reg != RegEnd) {
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002288 assert((ByValSize < Offset + 8) &&
2289 "Size of the remainder should be smaller than 8-byte.");
2290 SDValue Val;
2291 for (unsigned LoadSize = 4; Offset < ByValSize; LoadSize /= 2) {
2292 unsigned RemSize = ByValSize - Offset;
2293
2294 if (RemSize < LoadSize)
2295 continue;
Jia Liubb481f82012-02-28 07:46:26 +00002296
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002297 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2298 DAG.getConstant(Offset, PtrTy));
Jia Liubb481f82012-02-28 07:46:26 +00002299 SDValue LoadVal =
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002300 DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i64, Chain, LoadPtr,
2301 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
2302 false, false, Alignment);
2303 MemOpChains.push_back(LoadVal.getValue(1));
2304
2305 // Offset in number of bits from double word boundary.
2306 unsigned OffsetDW = (Offset % 8) * 8;
2307 unsigned Shamt = isLittle ? OffsetDW : 64 - (OffsetDW + LoadSize * 8);
2308 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i64, LoadVal,
2309 DAG.getConstant(Shamt, MVT::i32));
Jia Liubb481f82012-02-28 07:46:26 +00002310
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002311 Val = Val.getNode() ? DAG.getNode(ISD::OR, dl, MVT::i64, Val, Shift) :
2312 Shift;
2313 Offset += LoadSize;
2314 Alignment = std::min(Alignment, LoadSize);
2315 }
Jia Liubb481f82012-02-28 07:46:26 +00002316
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002317 RegsToPass.push_back(std::make_pair(*Reg, Val));
2318 return;
2319 }
2320 }
2321
Akira Hatanaka16040852011-11-15 18:42:25 +00002322 assert(MemCpySize && "MemCpySize must not be zero.");
2323
2324 // Create a fixed object on stack at offset LocMemOffset and copy
2325 // remainder of byval arg to it with memcpy.
2326 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2327 DAG.getConstant(Offset, PtrTy));
2328 LastFI = MFI->CreateFixedObject(MemCpySize, LocMemOffset, true);
2329 SDValue Dst = DAG.getFrameIndex(LastFI, PtrTy);
2330 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src,
2331 DAG.getConstant(MemCpySize, PtrTy), Alignment,
2332 /*isVolatile=*/false, /*AlwaysInline=*/false,
2333 MachinePointerInfo(0), MachinePointerInfo(0));
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002334}
2335
Dan Gohman98ca4f22009-08-05 01:29:28 +00002336/// LowerCall - functions arguments are copied from virtual regs to
Nate Begeman5bf4b752009-01-26 03:15:54 +00002337/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002338/// TODO: isTailCall.
Dan Gohman98ca4f22009-08-05 01:29:28 +00002339SDValue
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002340MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00002341 CallingConv::ID CallConv, bool isVarArg,
Evan Cheng4bfcd4a2012-02-28 18:51:51 +00002342 bool doesNotRet, bool &isTailCall,
Dan Gohman98ca4f22009-08-05 01:29:28 +00002343 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +00002344 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohman98ca4f22009-08-05 01:29:28 +00002345 const SmallVectorImpl<ISD::InputArg> &Ins,
2346 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +00002347 SmallVectorImpl<SDValue> &InVals) const {
Evan Cheng0c439eb2010-01-27 00:07:07 +00002348 // MIPs target does not yet support tail call optimization.
2349 isTailCall = false;
Dan Gohman98ca4f22009-08-05 01:29:28 +00002350
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002351 MachineFunction &MF = DAG.getMachineFunction();
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002352 MachineFrameInfo *MFI = MF.getFrameInfo();
Akira Hatanakad37776d2011-05-20 21:39:54 +00002353 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00002354 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Akira Hatanaka17a1e872011-05-20 18:39:33 +00002355 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002356
2357 // Analyze operands of the call, assigning locations to each operand.
2358 SmallVector<CCValAssign, 16> ArgLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00002359 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka82099682011-12-19 19:52:25 +00002360 getTargetMachine(), ArgLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002361
Akira Hatanaka2ec69fa2011-10-28 18:47:24 +00002362 if (IsO32)
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002363 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
Akira Hatanaka49617092011-11-14 19:02:54 +00002364 else if (HasMips64)
2365 AnalyzeMips64CallOperands(CCInfo, Outs);
Akira Hatanakabdd2ce92011-05-23 21:13:59 +00002366 else
Dan Gohman98ca4f22009-08-05 01:29:28 +00002367 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002368
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002369 // Get a count of how many bytes are to be pushed on the stack.
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002370 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2371
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002372 // Chain is the output chain of the last Load/Store or CopyToReg node.
2373 // ByValChain is the output chain of the last Memcpy node created for copying
2374 // byval arguments to the stack.
2375 SDValue Chain, CallSeqStart, ByValChain;
2376 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2377 Chain = CallSeqStart = DAG.getCALLSEQ_START(InChain, NextStackOffsetVal);
2378 ByValChain = InChain;
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002379
2380 // If this is the first call, create a stack frame object that points to
2381 // a location to which .cprestore saves $gp.
Akira Hatanaka648f00c2012-02-24 22:34:47 +00002382 if (IsO32 && IsPIC && MipsFI->globalBaseRegFixed() && !MipsFI->getGPFI())
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002383 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true));
2384
Akira Hatanaka21afc632011-06-21 00:40:49 +00002385 // Get the frame index of the stack frame object that points to the location
2386 // of dynamically allocated area on the stack.
2387 int DynAllocFI = MipsFI->getDynAllocFI();
2388
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002389 // Update size of the maximum argument space.
2390 // For O32, a minimum of four words (16 bytes) of argument space is
2391 // allocated.
Akira Hatanaka2ec69fa2011-10-28 18:47:24 +00002392 if (IsO32)
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002393 NextStackOffset = std::max(NextStackOffset, (unsigned)16);
2394
2395 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize();
2396
2397 if (MaxCallFrameSize < NextStackOffset) {
2398 MipsFI->setMaxCallFrameSize(NextStackOffset);
2399
Akira Hatanaka21afc632011-06-21 00:40:49 +00002400 // Set the offsets relative to $sp of the $gp restore slot and dynamically
2401 // allocated stack space. These offsets must be aligned to a boundary
2402 // determined by the stack alignment of the ABI.
2403 unsigned StackAlignment = TFL->getStackAlignment();
2404 NextStackOffset = (NextStackOffset + StackAlignment - 1) /
2405 StackAlignment * StackAlignment;
2406
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002407 if (MipsFI->needGPSaveRestore())
Akira Hatanaka21afc632011-06-21 00:40:49 +00002408 MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset);
2409
2410 MFI->setObjectOffset(DynAllocFI, NextStackOffset);
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002411 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002412
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002413 // With EABI is it possible to have 16 args on registers.
Dan Gohman475871a2008-07-27 21:46:04 +00002414 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
2415 SmallVector<SDValue, 8> MemOpChains;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002416
Eric Christopher471e4222011-06-08 23:55:35 +00002417 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0;
Akira Hatanaka43299772011-05-20 23:22:14 +00002418
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002419 // Walk the register/memloc assignments, inserting copies/loads.
2420 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
Dan Gohmanc9403652010-07-07 15:54:55 +00002421 SDValue Arg = OutVals[i];
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002422 CCValAssign &VA = ArgLocs[i];
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002423 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002424 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2425
2426 // ByVal Arg.
2427 if (Flags.isByVal()) {
2428 assert(Flags.getByValSize() &&
2429 "ByVal args of size 0 should have been ignored by front-end.");
2430 if (IsO32)
2431 WriteByValArg(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI,
2432 MFI, DAG, Arg, VA, Flags, getPointerTy(),
2433 Subtarget->isLittle());
2434 else
2435 PassByValArg64(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI,
Jia Liubb481f82012-02-28 07:46:26 +00002436 MFI, DAG, Arg, VA, Flags, getPointerTy(),
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002437 Subtarget->isLittle());
2438 continue;
2439 }
Jia Liubb481f82012-02-28 07:46:26 +00002440
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002441 // Promote the value if needed.
2442 switch (VA.getLocInfo()) {
Torok Edwinc23197a2009-07-14 16:55:14 +00002443 default: llvm_unreachable("Unknown loc info!");
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002444 case CCValAssign::Full:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002445 if (VA.isRegLoc()) {
2446 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2447 (ValVT == MVT::f64 && LocVT == MVT::i64))
2448 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
2449 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002450 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2451 Arg, DAG.getConstant(0, MVT::i32));
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00002452 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2453 Arg, DAG.getConstant(1, MVT::i32));
Akira Hatanaka99a2e982011-04-15 19:52:08 +00002454 if (!Subtarget->isLittle())
2455 std::swap(Lo, Hi);
Jia Liubb481f82012-02-28 07:46:26 +00002456 unsigned LocRegLo = VA.getLocReg();
Akira Hatanaka373e3a42011-09-23 00:58:33 +00002457 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2458 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2459 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002460 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002461 }
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002462 }
2463 break;
Chris Lattnere0b12152008-03-17 06:57:02 +00002464 case CCValAssign::SExt:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002465 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002466 break;
2467 case CCValAssign::ZExt:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002468 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002469 break;
2470 case CCValAssign::AExt:
Akira Hatanaka38bdc572012-02-17 02:20:26 +00002471 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002472 break;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002473 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002474
2475 // Arguments that can be passed on register must be kept at
Bruno Cardoso Lopesc7db5612007-11-05 03:02:32 +00002476 // RegsToPass vector
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002477 if (VA.isRegLoc()) {
2478 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
Chris Lattnere0b12152008-03-17 06:57:02 +00002479 continue;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002480 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002481
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002482 // Register can't get to this point...
Chris Lattnere0b12152008-03-17 06:57:02 +00002483 assert(VA.isMemLoc());
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002484
Chris Lattnere0b12152008-03-17 06:57:02 +00002485 // Create the frame index object for this incoming parameter
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002486 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002487 VA.getLocMemOffset(), true);
Akira Hatanaka43299772011-05-20 23:22:14 +00002488 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
Chris Lattnere0b12152008-03-17 06:57:02 +00002489
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002490 // emit ISD::STORE whichs stores the
Chris Lattnere0b12152008-03-17 06:57:02 +00002491 // parameter value to a stack Location
Chris Lattner8026a9d2010-09-21 17:50:43 +00002492 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
Akira Hatanaka82099682011-12-19 19:52:25 +00002493 MachinePointerInfo(), false, false, 0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002494 }
2495
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002496 // Extend range of indices of frame objects for outgoing arguments that were
2497 // created during this function call. Skip this step if no such objects were
2498 // created.
2499 if (LastFI)
2500 MipsFI->extendOutArgFIRange(FirstFI, LastFI);
2501
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002502 // If a memcpy has been created to copy a byval arg to a stack, replace the
2503 // chain input of CallSeqStart with ByValChain.
2504 if (InChain != ByValChain)
2505 DAG.UpdateNodeOperands(CallSeqStart.getNode(), ByValChain,
2506 NextStackOffsetVal);
2507
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002508 // Transform all store nodes into one single node because all store
2509 // nodes are independent of each other.
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002510 if (!MemOpChains.empty())
2511 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002512 &MemOpChains[0], MemOpChains.size());
2513
Bill Wendling056292f2008-09-16 21:48:12 +00002514 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002515 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2516 // node so that legalize doesn't hack it.
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002517 unsigned char OpFlag;
2518 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002519 bool GlobalOrExternal = false;
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002520 SDValue CalleeLo;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002521
2522 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002523 if (IsPICCall && G->getGlobal()->hasInternalLinkage()) {
2524 OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE;
2525 unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST;
2526 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
2527 OpFlag);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002528 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002529 0, LoFlag);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002530 } else {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002531 OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002532 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2533 getPointerTy(), 0, OpFlag);
2534 }
2535
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002536 GlobalOrExternal = true;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002537 }
2538 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002539 if (IsN64 || (!IsO32 && IsPIC))
2540 OpFlag = MipsII::MO_GOT_DISP;
2541 else if (!IsPIC) // !N64 && static
2542 OpFlag = MipsII::MO_NO_FLAG;
2543 else // O32 & PIC
2544 OpFlag = MipsII::MO_GOT_CALL;
Akira Hatanaka82099682011-12-19 19:52:25 +00002545 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2546 OpFlag);
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002547 GlobalOrExternal = true;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002548 }
2549
Akira Hatanakacd0f90f2011-05-20 02:30:51 +00002550 SDValue InFlag;
2551
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002552 // Create nodes that load address of callee and copy it to T9
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002553 if (IsPICCall) {
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002554 if (GlobalOrExternal) {
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002555 // Load callee address
Akira Hatanaka648f00c2012-02-24 22:34:47 +00002556 Callee = DAG.getNode(MipsISD::Wrapper, dl, getPointerTy(),
2557 GetGlobalReg(DAG, getPointerTy()), Callee);
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002558 SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
2559 Callee, MachinePointerInfo::getGOT(),
Pete Cooperd752e0f2011-11-08 18:42:53 +00002560 false, false, false, 0);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002561
2562 // Use GOT+LO if callee has internal linkage.
2563 if (CalleeLo.getNode()) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002564 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo);
2565 Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002566 } else
2567 Callee = LoadValue;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002568 }
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002569 }
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002570
Jia Liubb481f82012-02-28 07:46:26 +00002571 // T9 should contain the address of the callee function if
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002572 // -reloction-model=pic or it is an indirect call.
2573 if (IsPICCall || !GlobalOrExternal) {
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002574 // copy to T9
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002575 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
2576 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0));
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002577 InFlag = Chain.getValue(1);
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002578 Callee = DAG.getRegister(T9Reg, getPointerTy());
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002579 }
Bill Wendling056292f2008-09-16 21:48:12 +00002580
Akira Hatanakacd0f90f2011-05-20 02:30:51 +00002581 // Build a sequence of copy-to-reg nodes chained together with token
2582 // chain and flag operands which copy the outgoing args into registers.
2583 // The InFlag in necessary since all emitted instructions must be
2584 // stuck together.
2585 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2586 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2587 RegsToPass[i].second, InFlag);
2588 InFlag = Chain.getValue(1);
2589 }
2590
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002591 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002592 // = Chain, Callee, Reg#1, Reg#2, ...
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002593 //
2594 // Returns a chain & a flag for retval copy to use.
Chris Lattnerf1b4eaf2010-12-21 02:38:05 +00002595 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
Dan Gohman475871a2008-07-27 21:46:04 +00002596 SmallVector<SDValue, 8> Ops;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002597 Ops.push_back(Chain);
2598 Ops.push_back(Callee);
2599
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002600 // Add argument registers to the end of the list so that they are
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002601 // known live into the call.
2602 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2603 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2604 RegsToPass[i].second.getValueType()));
2605
Akira Hatanakab2930b92012-03-01 22:27:29 +00002606 // Add a register mask operand representing the call-preserved registers.
2607 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2608 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2609 assert(Mask && "Missing call preserved mask for calling convention");
2610 Ops.push_back(DAG.getRegisterMask(Mask));
2611
Gabor Greifba36cb52008-08-28 21:40:38 +00002612 if (InFlag.getNode())
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002613 Ops.push_back(InFlag);
2614
Dale Johannesen33c960f2009-02-04 20:06:27 +00002615 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002616 InFlag = Chain.getValue(1);
2617
Bruno Cardoso Lopes3ed6f872010-01-30 18:32:07 +00002618 // Create the CALLSEQ_END node.
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00002619 Chain = DAG.getCALLSEQ_END(Chain,
2620 DAG.getIntPtrConstant(NextStackOffset, true),
Bruno Cardoso Lopes3ed6f872010-01-30 18:32:07 +00002621 DAG.getIntPtrConstant(0, true), InFlag);
2622 InFlag = Chain.getValue(1);
2623
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002624 // Handle result values, copying them out of physregs into vregs that we
2625 // return.
Dan Gohman98ca4f22009-08-05 01:29:28 +00002626 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2627 Ins, dl, DAG, InVals);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002628}
2629
Dan Gohman98ca4f22009-08-05 01:29:28 +00002630/// LowerCallResult - Lower the result values of a call into the
2631/// appropriate copies out of appropriate physical registers.
2632SDValue
2633MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00002634 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +00002635 const SmallVectorImpl<ISD::InputArg> &Ins,
2636 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +00002637 SmallVectorImpl<SDValue> &InVals) const {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002638 // Assign locations to each value returned by this call.
2639 SmallVector<CCValAssign, 16> RVLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00002640 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2641 getTargetMachine(), RVLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002642
Dan Gohman98ca4f22009-08-05 01:29:28 +00002643 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002644
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002645 // Copy all of the result registers out of their specified physreg.
2646 for (unsigned i = 0; i != RVLocs.size(); ++i) {
Dale Johannesen33c960f2009-02-04 20:06:27 +00002647 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
Dan Gohman98ca4f22009-08-05 01:29:28 +00002648 RVLocs[i].getValVT(), InFlag).getValue(1);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002649 InFlag = Chain.getValue(2);
Dan Gohman98ca4f22009-08-05 01:29:28 +00002650 InVals.push_back(Chain.getValue(0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002651 }
Bruno Cardoso Lopesc7db5612007-11-05 03:02:32 +00002652
Dan Gohman98ca4f22009-08-05 01:29:28 +00002653 return Chain;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002654}
2655
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002656//===----------------------------------------------------------------------===//
Dan Gohman98ca4f22009-08-05 01:29:28 +00002657// Formal Arguments Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002658//===----------------------------------------------------------------------===//
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002659static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl,
2660 std::vector<SDValue>& OutChains,
2661 SelectionDAG &DAG, unsigned NumWords, SDValue FIN,
Akira Hatanakab4549e12012-03-27 03:13:56 +00002662 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
2663 const Argument *FuncArg) {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002664 unsigned LocMem = VA.getLocMemOffset();
2665 unsigned FirstWord = LocMem / 4;
2666
2667 // copy register A0 - A3 to frame object
2668 for (unsigned i = 0; i < NumWords; ++i) {
2669 unsigned CurWord = FirstWord + i;
2670 if (CurWord >= O32IntRegsSize)
2671 break;
2672
2673 unsigned SrcReg = O32IntRegs[CurWord];
Craig Topper420761a2012-04-20 07:30:17 +00002674 unsigned Reg = AddLiveIn(MF, SrcReg, &Mips::CPURegsRegClass);
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002675 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
2676 DAG.getConstant(i * 4, MVT::i32));
2677 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32),
Akira Hatanakab4549e12012-03-27 03:13:56 +00002678 StorePtr, MachinePointerInfo(FuncArg, i * 4),
2679 false, false, 0);
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002680 OutChains.push_back(Store);
2681 }
2682}
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002683
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002684// Create frame object on stack and copy registers used for byval passing to it.
2685static unsigned
2686CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl,
2687 std::vector<SDValue>& OutChains, SelectionDAG &DAG,
2688 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
2689 MachineFrameInfo *MFI, bool IsRegLoc,
2690 SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI,
Akira Hatanakab4549e12012-03-27 03:13:56 +00002691 EVT PtrTy, const Argument *FuncArg) {
Craig Topperc5eaae42012-03-11 07:57:25 +00002692 const uint16_t *Reg = Mips64IntRegs + 8;
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002693 int FOOffset; // Frame object offset from virtual frame pointer.
2694
2695 if (IsRegLoc) {
2696 Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, VA.getLocReg());
2697 FOOffset = (Reg - Mips64IntRegs) * 8 - 8 * 8;
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002698 }
2699 else
2700 FOOffset = VA.getLocMemOffset();
2701
2702 // Create frame object.
2703 unsigned NumRegs = (Flags.getByValSize() + 7) / 8;
2704 unsigned LastFI = MFI->CreateFixedObject(NumRegs * 8, FOOffset, true);
2705 SDValue FIN = DAG.getFrameIndex(LastFI, PtrTy);
2706 InVals.push_back(FIN);
2707
2708 // Copy arg registers.
2709 for (unsigned I = 0; (Reg != Mips64IntRegs + 8) && (I < NumRegs);
2710 ++Reg, ++I) {
Craig Topper420761a2012-04-20 07:30:17 +00002711 unsigned VReg = AddLiveIn(MF, *Reg, &Mips::CPU64RegsRegClass);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002712 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, PtrTy, FIN,
2713 DAG.getConstant(I * 8, PtrTy));
2714 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64),
Akira Hatanakab4549e12012-03-27 03:13:56 +00002715 StorePtr, MachinePointerInfo(FuncArg, I * 8),
2716 false, false, 0);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002717 OutChains.push_back(Store);
2718 }
Jia Liubb481f82012-02-28 07:46:26 +00002719
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002720 return LastFI;
2721}
2722
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002723/// LowerFormalArguments - transform physical registers into virtual registers
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002724/// and generate load operations for arguments places on the stack.
Dan Gohman98ca4f22009-08-05 01:29:28 +00002725SDValue
2726MipsTargetLowering::LowerFormalArguments(SDValue Chain,
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00002727 CallingConv::ID CallConv,
2728 bool isVarArg,
Akira Hatanaka82099682011-12-19 19:52:25 +00002729 const SmallVectorImpl<ISD::InputArg> &Ins,
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00002730 DebugLoc dl, SelectionDAG &DAG,
2731 SmallVectorImpl<SDValue> &InVals)
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002732 const {
Bruno Cardoso Lopesf7f3b502008-08-04 07:12:52 +00002733 MachineFunction &MF = DAG.getMachineFunction();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002734 MachineFrameInfo *MFI = MF.getFrameInfo();
Bruno Cardoso Lopesa2b1bb52007-08-28 05:08:16 +00002735 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002736
Dan Gohman1e93df62010-04-17 14:41:14 +00002737 MipsFI->setVarArgsFrameIndex(0);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002738
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002739 // Used with vargs to acumulate store chains.
2740 std::vector<SDValue> OutChains;
2741
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002742 // Assign locations to all of the incoming arguments.
2743 SmallVector<CCValAssign, 16> ArgLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00002744 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka82099682011-12-19 19:52:25 +00002745 getTargetMachine(), ArgLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002746
Akira Hatanaka2ec69fa2011-10-28 18:47:24 +00002747 if (IsO32)
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002748 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002749 else
Dan Gohman98ca4f22009-08-05 01:29:28 +00002750 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002751
Akira Hatanakab4549e12012-03-27 03:13:56 +00002752 Function::const_arg_iterator FuncArg =
2753 DAG.getMachineFunction().getFunction()->arg_begin();
Akira Hatanaka43299772011-05-20 23:22:14 +00002754 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function.
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002755
Akira Hatanakab4549e12012-03-27 03:13:56 +00002756 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++FuncArg) {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002757 CCValAssign &VA = ArgLocs[i];
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00002758 EVT ValVT = VA.getValVT();
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002759 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2760 bool IsRegLoc = VA.isRegLoc();
2761
2762 if (Flags.isByVal()) {
2763 assert(Flags.getByValSize() &&
2764 "ByVal args of size 0 should have been ignored by front-end.");
2765 if (IsO32) {
2766 unsigned NumWords = (Flags.getByValSize() + 3) / 4;
2767 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(),
2768 true);
2769 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
2770 InVals.push_back(FIN);
Akira Hatanakab4549e12012-03-27 03:13:56 +00002771 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags,
2772 &*FuncArg);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002773 } else // N32/64
2774 LastFI = CopyMips64ByValRegs(MF, Chain, dl, OutChains, DAG, VA, Flags,
2775 MFI, IsRegLoc, InVals, MipsFI,
Akira Hatanakab4549e12012-03-27 03:13:56 +00002776 getPointerTy(), &*FuncArg);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002777 continue;
2778 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002779
2780 // Arguments stored on registers
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002781 if (IsRegLoc) {
Owen Andersone50ed302009-08-10 22:56:29 +00002782 EVT RegVT = VA.getLocVT();
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002783 unsigned ArgReg = VA.getLocReg();
Craig Topper44d23822012-02-22 05:59:10 +00002784 const TargetRegisterClass *RC;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002785
Owen Anderson825b72b2009-08-11 20:47:22 +00002786 if (RegVT == MVT::i32)
Craig Topper420761a2012-04-20 07:30:17 +00002787 RC = &Mips::CPURegsRegClass;
Akira Hatanaka95934842011-09-24 01:34:44 +00002788 else if (RegVT == MVT::i64)
Craig Topper420761a2012-04-20 07:30:17 +00002789 RC = &Mips::CPU64RegsRegClass;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002790 else if (RegVT == MVT::f32)
Craig Topper420761a2012-04-20 07:30:17 +00002791 RC = &Mips::FGR32RegClass;
Akira Hatanaka09dd60f2011-09-26 21:37:50 +00002792 else if (RegVT == MVT::f64)
Craig Topper420761a2012-04-20 07:30:17 +00002793 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
Akira Hatanaka09dd60f2011-09-26 21:37:50 +00002794 else
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002795 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002796
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002797 // Transform the arguments stored on
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002798 // physical registers into virtual ones
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002799 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
Dan Gohman98ca4f22009-08-05 01:29:28 +00002800 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002801
2802 // If this is an 8 or 16-bit value, it has been passed promoted
2803 // to 32 bits. Insert an assert[sz]ext to capture this, then
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002804 // truncate to the right size.
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002805 if (VA.getLocInfo() != CCValAssign::Full) {
Chris Lattnerd4015072009-03-26 05:28:14 +00002806 unsigned Opcode = 0;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002807 if (VA.getLocInfo() == CCValAssign::SExt)
2808 Opcode = ISD::AssertSext;
2809 else if (VA.getLocInfo() == CCValAssign::ZExt)
2810 Opcode = ISD::AssertZext;
Chris Lattnerd4015072009-03-26 05:28:14 +00002811 if (Opcode)
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002812 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00002813 DAG.getValueType(ValVT));
2814 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002815 }
2816
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00002817 // Handle floating point arguments passed in integer registers.
2818 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
2819 (RegVT == MVT::i64 && ValVT == MVT::f64))
2820 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
2821 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
2822 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
2823 getNextIntArgReg(ArgReg), RC);
2824 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
2825 if (!Subtarget->isLittle())
2826 std::swap(ArgValue, ArgValue2);
2827 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
2828 ArgValue, ArgValue2);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002829 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002830
Dan Gohman98ca4f22009-08-05 01:29:28 +00002831 InVals.push_back(ArgValue);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002832 } else { // VA.isRegLoc()
2833
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002834 // sanity check
2835 assert(VA.isMemLoc());
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002836
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002837 // The stack pointer offset is relative to the caller stack frame.
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00002838 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002839 VA.getLocMemOffset(), true);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002840
2841 // Create load nodes to retrieve arguments from the stack
Akira Hatanaka43299772011-05-20 23:22:14 +00002842 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00002843 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
Akira Hatanaka43299772011-05-20 23:22:14 +00002844 MachinePointerInfo::getFixedStack(LastFI),
Pete Cooperd752e0f2011-11-08 18:42:53 +00002845 false, false, false, 0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002846 }
2847 }
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002848
2849 // The mips ABIs for returning structs by value requires that we copy
2850 // the sret argument into $v0 for the return. Save the argument into
2851 // a virtual register so that we can access it from the return points.
2852 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2853 unsigned Reg = MipsFI->getSRetReturnReg();
2854 if (!Reg) {
Owen Anderson825b72b2009-08-11 20:47:22 +00002855 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002856 MipsFI->setSRetReturnReg(Reg);
2857 }
Dan Gohman98ca4f22009-08-05 01:29:28 +00002858 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
Owen Anderson825b72b2009-08-11 20:47:22 +00002859 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002860 }
2861
Akira Hatanakabad53f42011-11-14 19:01:09 +00002862 if (isVarArg) {
2863 unsigned NumOfRegs = IsO32 ? 4 : 8;
Craig Topperc5eaae42012-03-11 07:57:25 +00002864 const uint16_t *ArgRegs = IsO32 ? O32IntRegs : Mips64IntRegs;
Akira Hatanakabad53f42011-11-14 19:01:09 +00002865 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumOfRegs);
2866 int FirstRegSlotOffset = IsO32 ? 0 : -64 ; // offset of $a0's slot.
Craig Topper420761a2012-04-20 07:30:17 +00002867 const TargetRegisterClass *RC = IsO32 ?
2868 (const TargetRegisterClass*)&Mips::CPURegsRegClass :
2869 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
Akira Hatanakabad53f42011-11-14 19:01:09 +00002870 unsigned RegSize = RC->getSize();
2871 int RegSlotOffset = FirstRegSlotOffset + Idx * RegSize;
2872
2873 // Offset of the first variable argument from stack pointer.
2874 int FirstVaArgOffset;
2875
2876 if (IsO32 || (Idx == NumOfRegs)) {
2877 FirstVaArgOffset =
2878 (CCInfo.getNextStackOffset() + RegSize - 1) / RegSize * RegSize;
2879 } else
2880 FirstVaArgOffset = RegSlotOffset;
2881
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002882 // Record the frame index of the first variable argument
Eric Christopher471e4222011-06-08 23:55:35 +00002883 // which is a value necessary to VASTART.
Akira Hatanakabad53f42011-11-14 19:01:09 +00002884 LastFI = MFI->CreateFixedObject(RegSize, FirstVaArgOffset, true);
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002885 MipsFI->setVarArgsFrameIndex(LastFI);
Akira Hatanakaedacba82011-05-25 17:32:06 +00002886
Akira Hatanakabad53f42011-11-14 19:01:09 +00002887 // Copy the integer registers that have not been used for argument passing
2888 // to the argument register save area. For O32, the save area is allocated
2889 // in the caller's stack frame, while for N32/64, it is allocated in the
2890 // callee's stack frame.
2891 for (int StackOffset = RegSlotOffset;
2892 Idx < NumOfRegs; ++Idx, StackOffset += RegSize) {
2893 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegs[Idx], RC);
2894 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2895 MVT::getIntegerVT(RegSize * 8));
2896 LastFI = MFI->CreateFixedObject(RegSize, StackOffset, true);
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002897 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
2898 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
Akira Hatanaka82099682011-12-19 19:52:25 +00002899 MachinePointerInfo(), false, false, 0));
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002900 }
2901 }
2902
Akira Hatanaka43299772011-05-20 23:22:14 +00002903 MipsFI->setLastInArgFI(LastFI);
2904
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002905 // All stores are grouped in one node to allow the matching between
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002906 // the size of Ins and InVals. This only happens when on varg functions
2907 if (!OutChains.empty()) {
2908 OutChains.push_back(Chain);
2909 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2910 &OutChains[0], OutChains.size());
2911 }
2912
Dan Gohman98ca4f22009-08-05 01:29:28 +00002913 return Chain;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002914}
2915
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002916//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002917// Return Value Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002918//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002919
Dan Gohman98ca4f22009-08-05 01:29:28 +00002920SDValue
2921MipsTargetLowering::LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00002922 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +00002923 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +00002924 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmand858e902010-04-17 15:26:15 +00002925 DebugLoc dl, SelectionDAG &DAG) const {
Dan Gohman98ca4f22009-08-05 01:29:28 +00002926
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002927 // CCValAssign - represent the assignment of
2928 // the return value to a location
2929 SmallVector<CCValAssign, 16> RVLocs;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002930
2931 // CCState - Info about the registers and stack slot.
Eric Christopher471e4222011-06-08 23:55:35 +00002932 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2933 getTargetMachine(), RVLocs, *DAG.getContext());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002934
Dan Gohman98ca4f22009-08-05 01:29:28 +00002935 // Analize return values.
2936 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002937
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002938 // If this is the first return lowered for this function, add
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002939 // the regs to the liveout set for the function.
Chris Lattner84bc5422007-12-31 04:13:23 +00002940 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002941 for (unsigned i = 0; i != RVLocs.size(); ++i)
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002942 if (RVLocs[i].isRegLoc())
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002943 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002944 }
2945
Dan Gohman475871a2008-07-27 21:46:04 +00002946 SDValue Flag;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002947
2948 // Copy the result values into the output registers.
2949 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2950 CCValAssign &VA = RVLocs[i];
2951 assert(VA.isRegLoc() && "Can only return in registers!");
2952
Akira Hatanaka82099682011-12-19 19:52:25 +00002953 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002954
2955 // guarantee that all emitted copies are
2956 // stuck together, avoiding something bad
2957 Flag = Chain.getValue(1);
2958 }
2959
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002960 // The mips ABIs for returning structs by value requires that we copy
2961 // the sret argument into $v0 for the return. We saved the argument into
2962 // a virtual register in the entry block, so now we copy the value out
2963 // and into $v0.
2964 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2965 MachineFunction &MF = DAG.getMachineFunction();
2966 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2967 unsigned Reg = MipsFI->getSRetReturnReg();
2968
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002969 if (!Reg)
Torok Edwinc23197a2009-07-14 16:55:14 +00002970 llvm_unreachable("sret virtual register not created in the entry block");
Dale Johannesena05dca42009-02-04 23:02:30 +00002971 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002972
Dale Johannesena05dca42009-02-04 23:02:30 +00002973 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002974 Flag = Chain.getValue(1);
2975 }
2976
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002977 // Return on Mips is always a "jr $ra"
Gabor Greifba36cb52008-08-28 21:40:38 +00002978 if (Flag.getNode())
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002979 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
Owen Anderson825b72b2009-08-11 20:47:22 +00002980 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002981 else // Return Void
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002982 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
Owen Anderson825b72b2009-08-11 20:47:22 +00002983 Chain, DAG.getRegister(Mips::RA, MVT::i32));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002984}
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002985
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002986//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002987// Mips Inline Assembly Support
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002988//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002989
2990/// getConstraintType - Given a constraint letter, return the type of
2991/// constraint it is for this target.
2992MipsTargetLowering::ConstraintType MipsTargetLowering::
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002993getConstraintType(const std::string &Constraint) const
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00002994{
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002995 // Mips specific constrainy
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002996 // GCC config/mips/constraints.md
2997 //
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002998 // 'd' : An address register. Equivalent to r
2999 // unless generating MIPS16 code.
3000 // 'y' : Equivalent to r; retained for
3001 // backwards compatibility.
3002 // 'f' : Floating Point registers.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003003 if (Constraint.size() == 1) {
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003004 switch (Constraint[0]) {
3005 default : break;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003006 case 'd':
3007 case 'y':
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003008 case 'f':
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003009 return C_RegisterClass;
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003010 }
3011 }
3012 return TargetLowering::getConstraintType(Constraint);
3013}
3014
John Thompson44ab89e2010-10-29 17:29:13 +00003015/// Examine constraint type and operand type and determine a weight value.
3016/// This object must already have been set up with the operand type
3017/// and the current alternative constraint selected.
3018TargetLowering::ConstraintWeight
3019MipsTargetLowering::getSingleConstraintMatchWeight(
3020 AsmOperandInfo &info, const char *constraint) const {
3021 ConstraintWeight weight = CW_Invalid;
3022 Value *CallOperandVal = info.CallOperandVal;
3023 // If we don't have a value, we can't do a match,
3024 // but allow it at the lowest weight.
3025 if (CallOperandVal == NULL)
3026 return CW_Default;
Chris Lattnerdb125cf2011-07-18 04:54:35 +00003027 Type *type = CallOperandVal->getType();
John Thompson44ab89e2010-10-29 17:29:13 +00003028 // Look at the constraint type.
3029 switch (*constraint) {
3030 default:
3031 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3032 break;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003033 case 'd':
3034 case 'y':
John Thompson44ab89e2010-10-29 17:29:13 +00003035 if (type->isIntegerTy())
3036 weight = CW_Register;
3037 break;
3038 case 'f':
3039 if (type->isFloatTy())
3040 weight = CW_Register;
3041 break;
Eric Christopher50ab0392012-05-07 03:13:32 +00003042 case 'I': // signed 16 bit immediate
Eric Christophere5076d42012-05-07 03:13:42 +00003043 case 'J': // integer zero
Eric Christopherf49f8462012-05-07 05:46:29 +00003044 case 'K': // unsigned 16 bit immediate
Eric Christopher5ac47bb2012-05-07 05:46:37 +00003045 case 'L': // signed 32 bit immediate where lower 16 bits are 0
Eric Christopher60cfc792012-05-07 05:46:43 +00003046 case 'N': // immediate in the range of -65535 to -1 (inclusive)
Eric Christopher50ab0392012-05-07 03:13:32 +00003047 if (isa<ConstantInt>(CallOperandVal))
3048 weight = CW_Constant;
3049 break;
John Thompson44ab89e2010-10-29 17:29:13 +00003050 }
3051 return weight;
3052}
3053
Eric Christopher38d64262011-06-29 19:33:04 +00003054/// Given a register class constraint, like 'r', if this corresponds directly
3055/// to an LLVM register class, return a register of 0 and the register class
3056/// pointer.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003057std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
Owen Andersone50ed302009-08-10 22:56:29 +00003058getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003059{
3060 if (Constraint.size() == 1) {
3061 switch (Constraint[0]) {
Eric Christopher314aff12011-06-29 19:04:31 +00003062 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3063 case 'y': // Same as 'r'. Exists for compatibility.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003064 case 'r':
Eric Christopher3ccbd472012-05-07 03:13:16 +00003065 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
Craig Topper420761a2012-04-20 07:30:17 +00003066 return std::make_pair(0U, &Mips::CPURegsRegClass);
Eric Christopher0ed1f762012-05-07 03:13:22 +00003067 if (VT == MVT::i64 && HasMips64)
3068 return std::make_pair(0U, &Mips::CPU64RegsRegClass);
3069 // This will generate an error message
3070 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003071 case 'f':
Owen Anderson825b72b2009-08-11 20:47:22 +00003072 if (VT == MVT::f32)
Craig Topper420761a2012-04-20 07:30:17 +00003073 return std::make_pair(0U, &Mips::FGR32RegClass);
Akira Hatanakacb9dd722012-01-04 02:45:01 +00003074 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
3075 if (Subtarget->isFP64bit())
Craig Topper420761a2012-04-20 07:30:17 +00003076 return std::make_pair(0U, &Mips::FGR64RegClass);
3077 return std::make_pair(0U, &Mips::AFGR64RegClass);
Akira Hatanakacb9dd722012-01-04 02:45:01 +00003078 }
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003079 }
3080 }
3081 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3082}
3083
Eric Christopher50ab0392012-05-07 03:13:32 +00003084/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3085/// vector. If it is invalid, don't add anything to Ops.
3086void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3087 std::string &Constraint,
3088 std::vector<SDValue>&Ops,
3089 SelectionDAG &DAG) const {
3090 SDValue Result(0, 0);
3091
3092 // Only support length 1 constraints for now.
3093 if (Constraint.length() > 1) return;
3094
3095 char ConstraintLetter = Constraint[0];
3096 switch (ConstraintLetter) {
3097 default: break; // This will fall through to the generic implementation
3098 case 'I': // Signed 16 bit constant
3099 // If this fails, the parent routine will give an error
3100 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3101 EVT Type = Op.getValueType();
3102 int64_t Val = C->getSExtValue();
3103 if (isInt<16>(Val)) {
3104 Result = DAG.getTargetConstant(Val, Type);
3105 break;
3106 }
3107 }
3108 return;
Eric Christophere5076d42012-05-07 03:13:42 +00003109 case 'J': // integer zero
3110 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3111 EVT Type = Op.getValueType();
3112 int64_t Val = C->getZExtValue();
3113 if (Val == 0) {
3114 Result = DAG.getTargetConstant(0, Type);
3115 break;
3116 }
3117 }
3118 return;
Eric Christopherf49f8462012-05-07 05:46:29 +00003119 case 'K': // unsigned 16 bit immediate
3120 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3121 EVT Type = Op.getValueType();
3122 uint64_t Val = (uint64_t)C->getZExtValue();
3123 if (isUInt<16>(Val)) {
3124 Result = DAG.getTargetConstant(Val, Type);
3125 break;
3126 }
3127 }
3128 return;
Eric Christopher5ac47bb2012-05-07 05:46:37 +00003129 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3130 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3131 EVT Type = Op.getValueType();
3132 int64_t Val = C->getSExtValue();
3133 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3134 Result = DAG.getTargetConstant(Val, Type);
3135 break;
3136 }
3137 }
3138 return;
Eric Christopher60cfc792012-05-07 05:46:43 +00003139 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3140 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3141 EVT Type = Op.getValueType();
3142 int64_t Val = C->getSExtValue();
3143 if ((Val >= -65535) && (Val <= -1)) {
3144 Result = DAG.getTargetConstant(Val, Type);
3145 break;
3146 }
3147 }
3148 return;
Eric Christopher50ab0392012-05-07 03:13:32 +00003149 }
3150
3151 if (Result.getNode()) {
3152 Ops.push_back(Result);
3153 return;
3154 }
3155
3156 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3157}
3158
Dan Gohman6520e202008-10-18 02:06:02 +00003159bool
3160MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3161 // The Mips target isn't yet aware of offsets.
3162 return false;
3163}
Evan Chengeb2f9692009-10-27 19:56:55 +00003164
Evan Chenga1eaa3c2009-10-28 01:43:28 +00003165bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3166 if (VT != MVT::f32 && VT != MVT::f64)
3167 return false;
Bruno Cardoso Lopes6b902822011-01-18 19:41:41 +00003168 if (Imm.isNegZero())
3169 return false;
Evan Chengeb2f9692009-10-27 19:56:55 +00003170 return Imm.isZero();
3171}
Akira Hatanaka6c2cf8b2012-02-03 04:33:00 +00003172
3173unsigned MipsTargetLowering::getJumpTableEncoding() const {
3174 if (IsN64)
3175 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
Jia Liubb481f82012-02-28 07:46:26 +00003176
Akira Hatanaka6c2cf8b2012-02-03 04:33:00 +00003177 return TargetLowering::getJumpTableEncoding();
3178}