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Evan Chenga8e29892007-01-19 07:51:42 +00001//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00006// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the ARM instructions in TableGen format.
11//
12//===----------------------------------------------------------------------===//
13
Evan Chenga8e29892007-01-19 07:51:42 +000014//===----------------------------------------------------------------------===//
15// ARM specific DAG Nodes.
16//
Rafael Espindola7cca7c52006-09-11 17:25:40 +000017
Evan Chenga8e29892007-01-19 07:51:42 +000018// Type profiles.
Bill Wendlingc69107c2007-11-13 09:19:02 +000019def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
Rafael Espindola6e8c6492006-11-08 17:07:32 +000021
Evan Chenga8e29892007-01-19 07:51:42 +000022def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
Rafael Espindola32bd5f42006-10-17 18:04:53 +000023
Evan Chenga8e29892007-01-19 07:51:42 +000024def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
Rafael Espindola7cca7c52006-09-11 17:25:40 +000025
Evan Chenga8e29892007-01-19 07:51:42 +000026def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
28 SDTCisVT<3, i32>]>;
Rafael Espindola6e8c6492006-11-08 17:07:32 +000029
Evan Chenga8e29892007-01-19 07:51:42 +000030def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
32
33def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
35 SDTCisVT<2, i32>]>;
36
37def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
38
39def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
41
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +000042def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
Jim Grosbachf9570122009-05-14 00:46:35 +000043def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +000044
Evan Chenga8e29892007-01-19 07:51:42 +000045// Node definitions.
46def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
Evan Chenga8e29892007-01-19 07:51:42 +000047def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
48
Bill Wendlingc69107c2007-11-13 09:19:02 +000049def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
Bill Wendling6ef781f2008-02-27 06:33:05 +000050 [SDNPHasChain, SDNPOutFlag]>;
Bill Wendlingc69107c2007-11-13 09:19:02 +000051def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
Bill Wendling6ef781f2008-02-27 06:33:05 +000052 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Evan Chenga8e29892007-01-19 07:51:42 +000053
54def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
55 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Evan Cheng277f0742007-06-19 21:05:09 +000056def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
57 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Evan Chenga8e29892007-01-19 07:51:42 +000058def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60
Chris Lattner48be23c2008-01-15 22:02:54 +000061def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
Evan Chenga8e29892007-01-19 07:51:42 +000062 [SDNPHasChain, SDNPOptInFlag]>;
63
64def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
65 [SDNPInFlag]>;
66def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
67 [SDNPInFlag]>;
68
69def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
70 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
71
72def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
73 [SDNPHasChain]>;
74
75def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
76 [SDNPOutFlag]>;
77
Lauro Ramos Venancio99966632007-04-02 01:30:03 +000078def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
79 [SDNPOutFlag]>;
80
Evan Chenga8e29892007-01-19 07:51:42 +000081def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
82
83def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
84def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
85def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
Rafael Espindola32bd5f42006-10-17 18:04:53 +000086
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +000087def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
Jim Grosbachf9570122009-05-14 00:46:35 +000088def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +000089
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000090//===----------------------------------------------------------------------===//
Evan Chenga8e29892007-01-19 07:51:42 +000091// ARM Instruction Predicate Definitions.
92//
Anton Korobeynikovbb629622009-06-15 21:46:20 +000093def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
94def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
95def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
Bob Wilson5bafff32009-06-22 23:27:02 +000096def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
97def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
98def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
99def HasNEON : Predicate<"Subtarget->hasNEON()">;
Anton Korobeynikovbb629622009-06-15 21:46:20 +0000100def IsThumb : Predicate<"Subtarget->isThumb()">;
Evan Chengf49810c2009-06-23 17:48:47 +0000101def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
Anton Korobeynikovbb629622009-06-15 21:46:20 +0000102def HasThumb2 : Predicate<"Subtarget->hasThumb2()">;
103def IsARM : Predicate<"!Subtarget->isThumb()">;
Bob Wilson54fc1242009-06-22 21:01:46 +0000104def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
105def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
Evan Chenga8e29892007-01-19 07:51:42 +0000106
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000107//===----------------------------------------------------------------------===//
Evan Chenga8e29892007-01-19 07:51:42 +0000108// ARM Flag Definitions.
109
110class RegConstraint<string C> {
111 string Constraints = C;
112}
113
114//===----------------------------------------------------------------------===//
115// ARM specific transformation functions and pattern fragments.
116//
117
118// so_imm_XFORM - Return a so_imm value packed into the format described for
119// so_imm def below.
120def so_imm_XFORM : SDNodeXForm<imm, [{
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000121 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getZExtValue()),
Evan Chenga8e29892007-01-19 07:51:42 +0000122 MVT::i32);
123}]>;
124
125// so_imm_neg_XFORM - Return a so_imm value packed into the format described for
126// so_imm_neg def below.
127def so_imm_neg_XFORM : SDNodeXForm<imm, [{
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000128 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getZExtValue()),
Evan Chenga8e29892007-01-19 07:51:42 +0000129 MVT::i32);
130}]>;
131
132// so_imm_not_XFORM - Return a so_imm value packed into the format described for
133// so_imm_not def below.
134def so_imm_not_XFORM : SDNodeXForm<imm, [{
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000135 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getZExtValue()),
Evan Chenga8e29892007-01-19 07:51:42 +0000136 MVT::i32);
137}]>;
138
139// rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
140def rot_imm : PatLeaf<(i32 imm), [{
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000141 int32_t v = (int32_t)N->getZExtValue();
Evan Chenga8e29892007-01-19 07:51:42 +0000142 return v == 8 || v == 16 || v == 24;
143}]>;
144
145/// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
146def imm1_15 : PatLeaf<(i32 imm), [{
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000147 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
Evan Chenga8e29892007-01-19 07:51:42 +0000148}]>;
149
150/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
151def imm16_31 : PatLeaf<(i32 imm), [{
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000152 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
Evan Chenga8e29892007-01-19 07:51:42 +0000153}]>;
154
155def so_imm_neg :
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000156 PatLeaf<(imm), [{
157 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
158 }], so_imm_neg_XFORM>;
Evan Chenga8e29892007-01-19 07:51:42 +0000159
Evan Chenga2515702007-03-19 07:09:02 +0000160def so_imm_not :
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000161 PatLeaf<(imm), [{
162 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
163 }], so_imm_not_XFORM>;
Evan Chenga8e29892007-01-19 07:51:42 +0000164
165// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
166def sext_16_node : PatLeaf<(i32 GPR:$a), [{
Dan Gohman475871a2008-07-27 21:46:04 +0000167 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
Evan Chenga8e29892007-01-19 07:51:42 +0000168}]>;
169
Evan Cheng37f25d92008-08-28 23:39:26 +0000170class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
171class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
Evan Chenga8e29892007-01-19 07:51:42 +0000172
173//===----------------------------------------------------------------------===//
174// Operand Definitions.
175//
176
177// Branch target.
178def brtarget : Operand<OtherVT>;
179
Evan Chenga8e29892007-01-19 07:51:42 +0000180// A list of registers separated by comma. Used by load/store multiple.
181def reglist : Operand<i32> {
182 let PrintMethod = "printRegisterList";
183}
184
185// An operand for the CONSTPOOL_ENTRY pseudo-instruction.
186def cpinst_operand : Operand<i32> {
187 let PrintMethod = "printCPInstOperand";
188}
189
190def jtblock_operand : Operand<i32> {
191 let PrintMethod = "printJTBlockOperand";
192}
193
194// Local PC labels.
195def pclabel : Operand<i32> {
196 let PrintMethod = "printPCLabel";
197}
198
199// shifter_operand operands: so_reg and so_imm.
200def so_reg : Operand<i32>, // reg reg imm
201 ComplexPattern<i32, 3, "SelectShifterOperandReg",
202 [shl,srl,sra,rotr]> {
203 let PrintMethod = "printSORegOperand";
204 let MIOperandInfo = (ops GPR, GPR, i32imm);
205}
206
207// so_imm - Match a 32-bit shifter_operand immediate operand, which is an
208// 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
209// represented in the imm field in the same 12-bit form that they are encoded
210// into so_imm instructions: the 8-bit immediate is the least significant bits
211// [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
212def so_imm : Operand<i32>,
213 PatLeaf<(imm),
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000214 [{ return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; }],
Evan Chenga8e29892007-01-19 07:51:42 +0000215 so_imm_XFORM> {
216 let PrintMethod = "printSOImmOperand";
217}
218
Evan Chengc70d1842007-03-20 08:11:30 +0000219// Break so_imm's up into two pieces. This handles immediates with up to 16
220// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
221// get the first/second pieces.
222def so_imm2part : Operand<i32>,
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000223 PatLeaf<(imm), [{
224 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
225 }]> {
Evan Chengc70d1842007-03-20 08:11:30 +0000226 let PrintMethod = "printSOImm2PartOperand";
227}
228
229def so_imm2part_1 : SDNodeXForm<imm, [{
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000230 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
Evan Chengc70d1842007-03-20 08:11:30 +0000231 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
232}]>;
233
234def so_imm2part_2 : SDNodeXForm<imm, [{
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000235 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
Evan Chengc70d1842007-03-20 08:11:30 +0000236 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
237}]>;
238
Evan Chenga8e29892007-01-19 07:51:42 +0000239
240// Define ARM specific addressing modes.
241
242// addrmode2 := reg +/- reg shop imm
243// addrmode2 := reg +/- imm12
244//
245def addrmode2 : Operand<i32>,
246 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
247 let PrintMethod = "printAddrMode2Operand";
248 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
249}
250
251def am2offset : Operand<i32>,
252 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
253 let PrintMethod = "printAddrMode2OffsetOperand";
254 let MIOperandInfo = (ops GPR, i32imm);
255}
256
257// addrmode3 := reg +/- reg
258// addrmode3 := reg +/- imm8
259//
260def addrmode3 : Operand<i32>,
261 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
262 let PrintMethod = "printAddrMode3Operand";
263 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
264}
265
266def am3offset : Operand<i32>,
267 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
268 let PrintMethod = "printAddrMode3OffsetOperand";
269 let MIOperandInfo = (ops GPR, i32imm);
270}
271
272// addrmode4 := reg, <mode|W>
273//
274def addrmode4 : Operand<i32>,
275 ComplexPattern<i32, 2, "", []> {
276 let PrintMethod = "printAddrMode4Operand";
277 let MIOperandInfo = (ops GPR, i32imm);
278}
279
280// addrmode5 := reg +/- imm8*4
281//
282def addrmode5 : Operand<i32>,
283 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
284 let PrintMethod = "printAddrMode5Operand";
285 let MIOperandInfo = (ops GPR, i32imm);
286}
287
288// addrmodepc := pc + reg
289//
290def addrmodepc : Operand<i32>,
291 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
292 let PrintMethod = "printAddrModePCOperand";
293 let MIOperandInfo = (ops GPR, i32imm);
294}
295
Evan Chengc85e8322007-07-05 07:13:32 +0000296// ARM Predicate operand. Default to 14 = always (AL). Second part is CC
297// register whose default is 0 (no register).
298def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
299 (ops (i32 14), (i32 zero_reg))> {
Evan Cheng42d712b2007-05-08 21:08:43 +0000300 let PrintMethod = "printPredicateOperand";
301}
302
Evan Cheng04c813d2007-07-06 01:00:49 +0000303// Conditional code result for instructions whose 's' bit is set, e.g. subs.
Evan Chengc85e8322007-07-05 07:13:32 +0000304//
Evan Cheng04c813d2007-07-06 01:00:49 +0000305def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
306 let PrintMethod = "printSBitModifierOperand";
Evan Cheng42d712b2007-05-08 21:08:43 +0000307}
308
Evan Chenga8e29892007-01-19 07:51:42 +0000309//===----------------------------------------------------------------------===//
310// ARM Instruction flags. These need to match ARMInstrInfo.h.
311//
312
313// Addressing mode.
314class AddrMode<bits<4> val> {
315 bits<4> Value = val;
316}
317def AddrModeNone : AddrMode<0>;
318def AddrMode1 : AddrMode<1>;
319def AddrMode2 : AddrMode<2>;
320def AddrMode3 : AddrMode<3>;
321def AddrMode4 : AddrMode<4>;
322def AddrMode5 : AddrMode<5>;
Evan Chengedda31c2008-11-05 18:35:52 +0000323def AddrModeT1 : AddrMode<6>;
324def AddrModeT2 : AddrMode<7>;
325def AddrModeT4 : AddrMode<8>;
326def AddrModeTs : AddrMode<9>;
Evan Chenga8e29892007-01-19 07:51:42 +0000327
328// Instruction size.
329class SizeFlagVal<bits<3> val> {
330 bits<3> Value = val;
331}
332def SizeInvalid : SizeFlagVal<0>; // Unset.
333def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
334def Size8Bytes : SizeFlagVal<2>;
335def Size4Bytes : SizeFlagVal<3>;
336def Size2Bytes : SizeFlagVal<4>;
337
338// Load / store index mode.
339class IndexMode<bits<2> val> {
340 bits<2> Value = val;
341}
342def IndexModeNone : IndexMode<0>;
343def IndexModePre : IndexMode<1>;
344def IndexModePost : IndexMode<2>;
345
346//===----------------------------------------------------------------------===//
Evan Cheng0ff94f72007-08-07 01:37:15 +0000347
Evan Cheng37f25d92008-08-28 23:39:26 +0000348include "ARMInstrFormats.td"
Evan Cheng0ff94f72007-08-07 01:37:15 +0000349
350//===----------------------------------------------------------------------===//
Evan Cheng37f25d92008-08-28 23:39:26 +0000351// Multiclass helpers...
Evan Chenga8e29892007-01-19 07:51:42 +0000352//
353
Evan Cheng3924f782008-08-29 07:36:24 +0000354/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
Evan Chenga8e29892007-01-19 07:51:42 +0000355/// binop that produces a value.
Evan Cheng0ff94f72007-08-07 01:37:15 +0000356multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
Evan Chengedda31c2008-11-05 18:35:52 +0000357 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
Evan Chengc85e8322007-07-05 07:13:32 +0000358 opc, " $dst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000359 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
Evan Chengedda31c2008-11-05 18:35:52 +0000360 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
Evan Chengc85e8322007-07-05 07:13:32 +0000361 opc, " $dst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000362 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
Evan Chengedda31c2008-11-05 18:35:52 +0000363 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
Evan Chengc85e8322007-07-05 07:13:32 +0000364 opc, " $dst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +0000365 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
366}
367
Evan Cheng1e249e32009-06-25 20:59:23 +0000368/// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
Evan Chengc85e8322007-07-05 07:13:32 +0000369/// instruction modifies the CSPR register.
Evan Cheng071a2792007-09-11 19:55:27 +0000370let Defs = [CPSR] in {
Evan Cheng1e249e32009-06-25 20:59:23 +0000371multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
Evan Chengedda31c2008-11-05 18:35:52 +0000372 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
Evan Chengc85e8322007-07-05 07:13:32 +0000373 opc, "s $dst, $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000374 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
Evan Chengedda31c2008-11-05 18:35:52 +0000375 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
Evan Chengc85e8322007-07-05 07:13:32 +0000376 opc, "s $dst, $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000377 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
Evan Chengedda31c2008-11-05 18:35:52 +0000378 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
Evan Chengc85e8322007-07-05 07:13:32 +0000379 opc, "s $dst, $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000380 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
381}
Evan Chengc85e8322007-07-05 07:13:32 +0000382}
383
384/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
Evan Cheng13ab0202007-07-10 18:08:01 +0000385/// patterns. Similar to AsI1_bin_irs except the instruction does not produce
Evan Chengc85e8322007-07-05 07:13:32 +0000386/// a explicit result, only implicitly set CPSR.
Evan Cheng071a2792007-09-11 19:55:27 +0000387let Defs = [CPSR] in {
Evan Cheng0ff94f72007-08-07 01:37:15 +0000388multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
Evan Chengedda31c2008-11-05 18:35:52 +0000389 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm,
Evan Cheng44bec522007-05-15 01:29:07 +0000390 opc, " $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000391 [(opnode GPR:$a, so_imm:$b)]>;
Evan Chengedda31c2008-11-05 18:35:52 +0000392 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm,
Evan Cheng44bec522007-05-15 01:29:07 +0000393 opc, " $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000394 [(opnode GPR:$a, GPR:$b)]>;
Evan Chengedda31c2008-11-05 18:35:52 +0000395 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
Evan Cheng44bec522007-05-15 01:29:07 +0000396 opc, " $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000397 [(opnode GPR:$a, so_reg:$b)]>;
398}
Evan Chenga8e29892007-01-19 07:51:42 +0000399}
400
Evan Chenga8e29892007-01-19 07:51:42 +0000401/// AI_unary_rrot - A unary operation with two forms: one whose operand is a
402/// register and one whose operand is a register rotated by 8/16/24.
Evan Cheng97f48c32008-11-06 22:15:19 +0000403/// FIXME: Remove the 'r' variant. Its rot_imm is zero.
404multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
405 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src),
Evan Cheng44bec522007-05-15 01:29:07 +0000406 opc, " $dst, $Src",
Evan Cheng97f48c32008-11-06 22:15:19 +0000407 [(set GPR:$dst, (opnode GPR:$Src))]>,
408 Requires<[IsARM, HasV6]> {
409 let Inst{19-16} = 0b1111;
410 }
411 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
Evan Cheng44bec522007-05-15 01:29:07 +0000412 opc, " $dst, $Src, ror $rot",
Evan Chenga8e29892007-01-19 07:51:42 +0000413 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
Evan Cheng97f48c32008-11-06 22:15:19 +0000414 Requires<[IsARM, HasV6]> {
415 let Inst{19-16} = 0b1111;
416 }
Evan Chenga8e29892007-01-19 07:51:42 +0000417}
418
419/// AI_bin_rrot - A binary operation with two forms: one whose operand is a
420/// register and one whose operand is a register rotated by 8/16/24.
Evan Cheng97f48c32008-11-06 22:15:19 +0000421multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
422 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
423 opc, " $dst, $LHS, $RHS",
Evan Chenga8e29892007-01-19 07:51:42 +0000424 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
425 Requires<[IsARM, HasV6]>;
Evan Cheng97f48c32008-11-06 22:15:19 +0000426 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
427 opc, " $dst, $LHS, $RHS, ror $rot",
Evan Chenga8e29892007-01-19 07:51:42 +0000428 [(set GPR:$dst, (opnode GPR:$LHS,
429 (rotr GPR:$RHS, rot_imm:$rot)))]>,
430 Requires<[IsARM, HasV6]>;
431}
432
Evan Cheng1e249e32009-06-25 20:59:23 +0000433/// AI1_bin_cs_irs - A binary operation that both uses and defines CPSR. It's
434/// currently not predicable.
435let Defs = [CPSR], Uses = [CPSR] in {
436multiclass AI1_bin_cs_irs<bits<4> opcod, string opc, PatFrag opnode> {
437 def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
438 DPFrm, !strconcat(opc, "s $dst, $a, $b"),
Evan Cheng071a2792007-09-11 19:55:27 +0000439 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
Evan Cheng1e249e32009-06-25 20:59:23 +0000440 def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
441 DPFrm, !strconcat(opc, "s $dst, $a, $b"),
Evan Cheng071a2792007-09-11 19:55:27 +0000442 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
Evan Cheng1e249e32009-06-25 20:59:23 +0000443 def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
444 DPSoRegFrm, !strconcat(opc, "s $dst, $a, $b"),
Evan Cheng071a2792007-09-11 19:55:27 +0000445 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
446}
Evan Chengc85e8322007-07-05 07:13:32 +0000447}
448
Rafael Espindola15a6c3e2006-10-16 17:57:20 +0000449//===----------------------------------------------------------------------===//
450// Instructions
451//===----------------------------------------------------------------------===//
452
Evan Chenga8e29892007-01-19 07:51:42 +0000453//===----------------------------------------------------------------------===//
454// Miscellaneous Instructions.
455//
Rafael Espindola6f602de2006-08-24 16:13:15 +0000456
Evan Chenga8e29892007-01-19 07:51:42 +0000457/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
458/// the function. The first operand is the ID# for this instruction, the second
459/// is the index into the MachineConstantPool that this is, the third is the
460/// size in bytes of this constant pool entry.
Evan Chengcd799b92009-06-12 20:46:18 +0000461let neverHasSideEffects = 1, isNotDuplicable = 1 in
Evan Chenga8e29892007-01-19 07:51:42 +0000462def CONSTPOOL_ENTRY :
Evan Cheng64d80e32007-07-19 01:14:50 +0000463PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
Evan Cheng12c3a532008-11-06 17:48:05 +0000464 i32imm:$size),
Evan Chenga8e29892007-01-19 07:51:42 +0000465 "${instid:label} ${cpidx:cpentry}", []>;
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000466
Evan Cheng071a2792007-09-11 19:55:27 +0000467let Defs = [SP], Uses = [SP] in {
Evan Chenga8e29892007-01-19 07:51:42 +0000468def ADJCALLSTACKUP :
Bill Wendling0f8d9c02007-11-13 00:44:25 +0000469PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p),
470 "@ ADJCALLSTACKUP $amt1",
Chris Lattnere563bbc2008-10-11 22:08:30 +0000471 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
Rafael Espindolacdda88c2006-08-24 17:19:08 +0000472
Evan Chenga8e29892007-01-19 07:51:42 +0000473def ADJCALLSTACKDOWN :
Evan Cheng64d80e32007-07-19 01:14:50 +0000474PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
Evan Chenga8e29892007-01-19 07:51:42 +0000475 "@ ADJCALLSTACKDOWN $amt",
Chris Lattnere563bbc2008-10-11 22:08:30 +0000476 [(ARMcallseq_start timm:$amt)]>;
Evan Cheng071a2792007-09-11 19:55:27 +0000477}
Rafael Espindola3c000bf2006-08-21 22:00:32 +0000478
Evan Chenga8e29892007-01-19 07:51:42 +0000479def DWARF_LOC :
Evan Cheng64d80e32007-07-19 01:14:50 +0000480PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
Evan Chenga8e29892007-01-19 07:51:42 +0000481 ".loc $file, $line, $col",
482 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
Rafael Espindola4b20fbc2006-10-10 12:56:00 +0000483
Evan Cheng12c3a532008-11-06 17:48:05 +0000484
485// Address computation and loads and stores in PIC mode.
Evan Chengeaa91b02007-06-19 01:26:51 +0000486let isNotDuplicable = 1 in {
Evan Chengc0729662008-10-31 19:11:09 +0000487def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000488 Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
Evan Cheng44bec522007-05-15 01:29:07 +0000489 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
Dale Johannesen86d40692007-05-21 22:14:33 +0000490
Evan Cheng325474e2008-01-07 23:56:57 +0000491let AddedComplexity = 10 in {
Dan Gohman15511cf2008-12-03 18:15:48 +0000492let canFoldAsLoad = 1 in
Evan Chengd87293c2008-11-06 08:47:38 +0000493def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000494 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000495 [(set GPR:$dst, (load addrmodepc:$addr))]>;
Rafael Espindola84b19be2006-07-16 01:02:57 +0000496
Evan Chengd87293c2008-11-06 08:47:38 +0000497def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000498 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
Dale Johannesen86d40692007-05-21 22:14:33 +0000499 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
500
Evan Chengd87293c2008-11-06 08:47:38 +0000501def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000502 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
Dale Johannesen86d40692007-05-21 22:14:33 +0000503 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
504
Evan Chengd87293c2008-11-06 08:47:38 +0000505def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000506 Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
Dale Johannesen86d40692007-05-21 22:14:33 +0000507 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
508
Evan Chengd87293c2008-11-06 08:47:38 +0000509def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000510 Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
Dale Johannesen86d40692007-05-21 22:14:33 +0000511 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
512}
Chris Lattner13c63102008-01-06 05:55:01 +0000513let AddedComplexity = 10 in {
Evan Chengd87293c2008-11-06 08:47:38 +0000514def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000515 Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
Dale Johannesen86d40692007-05-21 22:14:33 +0000516 [(store GPR:$src, addrmodepc:$addr)]>;
517
Evan Chengd87293c2008-11-06 08:47:38 +0000518def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000519 Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
Dale Johannesen86d40692007-05-21 22:14:33 +0000520 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
521
Evan Chengd87293c2008-11-06 08:47:38 +0000522def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000523 Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
Dale Johannesen86d40692007-05-21 22:14:33 +0000524 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
525}
Evan Cheng12c3a532008-11-06 17:48:05 +0000526} // isNotDuplicable = 1
Dale Johannesen86d40692007-05-21 22:14:33 +0000527
Evan Chenge07715c2009-06-23 05:25:29 +0000528
529// LEApcrel - Load a pc-relative address into a register without offending the
530// assembler.
531def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo,
532 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
533 "${:private}PCRELL${:uid}+8))\n"),
534 !strconcat("${:private}PCRELL${:uid}:\n\t",
535 "add$p $dst, pc, #PCRELV${:uid}")),
536 []>;
537
Evan Cheng023dd3f2009-06-24 23:14:45 +0000538def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
539 (ins i32imm:$label, i32imm:$id, pred:$p),
Evan Chenge07715c2009-06-23 05:25:29 +0000540 Pseudo,
541 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
542 "${:private}PCRELL${:uid}+8))\n"),
543 !strconcat("${:private}PCRELL${:uid}:\n\t",
544 "add$p $dst, pc, #PCRELV${:uid}")),
545 []>;
546
Evan Chenga8e29892007-01-19 07:51:42 +0000547//===----------------------------------------------------------------------===//
548// Control Flow Instructions.
549//
Rafael Espindola9e071f02006-10-02 19:30:56 +0000550
Evan Chenga8e29892007-01-19 07:51:42 +0000551let isReturn = 1, isTerminator = 1 in
Evan Cheng12c3a532008-11-06 17:48:05 +0000552 def BX_RET : AI<(outs), (ins), BrMiscFrm, "bx", " lr", [(ARMretflag)]> {
Jim Grosbach26421962008-10-14 20:36:24 +0000553 let Inst{7-4} = 0b0001;
554 let Inst{19-8} = 0b111111111111;
555 let Inst{27-20} = 0b00010010;
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000556}
Rafael Espindola27185192006-09-29 21:20:16 +0000557
Evan Chenga8e29892007-01-19 07:51:42 +0000558// FIXME: remove when we have a way to marking a MI with these properties.
Evan Cheng64d80e32007-07-19 01:14:50 +0000559// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
560// operand list.
Evan Cheng12c3a532008-11-06 17:48:05 +0000561// FIXME: Should pc be an implicit operand like PICADD, etc?
Evan Cheng325474e2008-01-07 23:56:57 +0000562let isReturn = 1, isTerminator = 1 in
Evan Cheng12c3a532008-11-06 17:48:05 +0000563 def LDM_RET : AXI4ld<(outs),
Evan Cheng64d80e32007-07-19 01:14:50 +0000564 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
Evan Cheng3c4a4ff2008-11-12 07:18:38 +0000565 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
Evan Chenga8e29892007-01-19 07:51:42 +0000566 []>;
Rafael Espindolaa2845842006-10-05 16:48:49 +0000567
Bob Wilson54fc1242009-06-22 21:01:46 +0000568// On non-Darwin platforms R9 is callee-saved.
Evan Cheng8557c2b2009-06-19 01:51:50 +0000569let isCall = 1, Itinerary = IIC_Br,
Evan Chenga8e29892007-01-19 07:51:42 +0000570 Defs = [R0, R1, R2, R3, R12, LR,
Evan Chengc85e8322007-07-05 07:13:32 +0000571 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
Evan Cheng12c3a532008-11-06 17:48:05 +0000572 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
Evan Chengdcc50a42007-05-18 01:53:54 +0000573 "bl ${func:call}",
Bob Wilson54fc1242009-06-22 21:01:46 +0000574 [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
Evan Cheng277f0742007-06-19 21:05:09 +0000575
Evan Cheng12c3a532008-11-06 17:48:05 +0000576 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
Evan Cheng3aac7882008-09-01 08:25:56 +0000577 "bl", " ${func:call}",
Bob Wilson54fc1242009-06-22 21:01:46 +0000578 [(ARMcall_pred tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
Evan Cheng277f0742007-06-19 21:05:09 +0000579
Evan Chenga8e29892007-01-19 07:51:42 +0000580 // ARMv5T and above
Evan Cheng12c3a532008-11-06 17:48:05 +0000581 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
Evan Cheng64d80e32007-07-19 01:14:50 +0000582 "blx $func",
Bob Wilson54fc1242009-06-22 21:01:46 +0000583 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsNotDarwin]> {
Jim Grosbach26421962008-10-14 20:36:24 +0000584 let Inst{7-4} = 0b0011;
585 let Inst{19-8} = 0b111111111111;
586 let Inst{27-20} = 0b00010010;
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000587 }
588
Lauro Ramos Venancio64c88d72007-03-20 17:57:23 +0000589 let Uses = [LR] in {
590 // ARMv4T
Evan Cheng12c3a532008-11-06 17:48:05 +0000591 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
592 "mov lr, pc\n\tbx $func",
Bob Wilson54fc1242009-06-22 21:01:46 +0000593 [(ARMcall_nolink GPR:$func)]>, Requires<[IsNotDarwin]>;
594 }
595}
596
597// On Darwin R9 is call-clobbered.
598let isCall = 1, Itinerary = IIC_Br,
599 Defs = [R0, R1, R2, R3, R9, R12, LR,
600 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
601 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
602 "bl ${func:call}",
603 [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>;
604
605 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
606 "bl", " ${func:call}",
607 [(ARMcall_pred tglobaladdr:$func)]>, Requires<[IsDarwin]>;
608
609 // ARMv5T and above
610 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
611 "blx $func",
612 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
613 let Inst{7-4} = 0b0011;
614 let Inst{19-8} = 0b111111111111;
615 let Inst{27-20} = 0b00010010;
616 }
617
618 let Uses = [LR] in {
619 // ARMv4T
620 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
621 "mov lr, pc\n\tbx $func",
622 [(ARMcall_nolink GPR:$func)]>, Requires<[IsDarwin]>;
Lauro Ramos Venancio64c88d72007-03-20 17:57:23 +0000623 }
Rafael Espindola35574632006-07-18 17:00:30 +0000624}
Rafael Espindoladc124a22006-05-18 21:45:49 +0000625
Evan Cheng8557c2b2009-06-19 01:51:50 +0000626let isBranch = 1, isTerminator = 1, Itinerary = IIC_Br in {
Evan Cheng5ada1992007-05-16 20:50:01 +0000627 // B is "predicable" since it can be xformed into a Bcc.
Evan Chengaeafca02007-05-16 07:45:54 +0000628 let isBarrier = 1 in {
Evan Cheng5ada1992007-05-16 20:50:01 +0000629 let isPredicable = 1 in
Evan Cheng12c3a532008-11-06 17:48:05 +0000630 def B : ABXI<0b1010, (outs), (ins brtarget:$target), "b $target",
Evan Cheng64d80e32007-07-19 01:14:50 +0000631 [(br bb:$target)]>;
Evan Cheng44bec522007-05-15 01:29:07 +0000632
Owen Anderson20ab2902007-11-12 07:39:39 +0000633 let isNotDuplicable = 1, isIndirectBranch = 1 in {
Evan Cheng4df60f52008-11-07 09:06:08 +0000634 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
Evan Cheng64d80e32007-07-19 01:14:50 +0000635 "mov pc, $target \n$jt",
Evan Cheng4df60f52008-11-07 09:06:08 +0000636 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
637 let Inst{20} = 0; // S Bit
638 let Inst{24-21} = 0b1101;
639 let Inst{27-26} = {0,0};
Evan Chengaeafca02007-05-16 07:45:54 +0000640 }
Evan Cheng4df60f52008-11-07 09:06:08 +0000641 def BR_JTm : JTI<(outs),
642 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
643 "ldr pc, $target \n$jt",
644 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
645 imm:$id)]> {
646 let Inst{20} = 1; // L bit
647 let Inst{21} = 0; // W bit
648 let Inst{22} = 0; // B bit
649 let Inst{24} = 1; // P bit
650 let Inst{27-26} = {0,1};
Evan Chengeaa91b02007-06-19 01:26:51 +0000651 }
Evan Cheng4df60f52008-11-07 09:06:08 +0000652 def BR_JTadd : JTI<(outs),
653 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
654 "add pc, $target, $idx \n$jt",
655 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
656 imm:$id)]> {
657 let Inst{20} = 0; // S bit
658 let Inst{24-21} = 0b0100;
659 let Inst{27-26} = {0,0};
660 }
661 } // isNotDuplicable = 1, isIndirectBranch = 1
662 } // isBarrier = 1
Evan Chengaeafca02007-05-16 07:45:54 +0000663
Evan Chengc85e8322007-07-05 07:13:32 +0000664 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
665 // a two-value operand where a dag node expects two operands. :(
Evan Cheng12c3a532008-11-06 17:48:05 +0000666 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
Evan Cheng0ff94f72007-08-07 01:37:15 +0000667 "b", " $target",
668 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
Rafael Espindola1ed3af12006-08-01 18:53:10 +0000669}
Rafael Espindola84b19be2006-07-16 01:02:57 +0000670
Evan Chenga8e29892007-01-19 07:51:42 +0000671//===----------------------------------------------------------------------===//
672// Load / store Instructions.
673//
Rafael Espindola82c678b2006-10-16 17:17:22 +0000674
Evan Chenga8e29892007-01-19 07:51:42 +0000675// Load
Dan Gohman15511cf2008-12-03 18:15:48 +0000676let canFoldAsLoad = 1 in
Evan Cheng148cad82008-11-13 07:34:59 +0000677def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
Evan Cheng44bec522007-05-15 01:29:07 +0000678 "ldr", " $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000679 [(set GPR:$dst, (load addrmode2:$addr))]>;
Rafael Espindola82c678b2006-10-16 17:17:22 +0000680
Evan Chengfa775d02007-03-19 07:20:03 +0000681// Special LDR for loads from non-pc-relative constpools.
Dan Gohman15511cf2008-12-03 18:15:48 +0000682let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
Evan Cheng148cad82008-11-13 07:34:59 +0000683def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
Evan Cheng44bec522007-05-15 01:29:07 +0000684 "ldr", " $dst, $addr", []>;
Evan Chengfa775d02007-03-19 07:20:03 +0000685
Evan Chenga8e29892007-01-19 07:51:42 +0000686// Loads with zero extension
Evan Cheng148cad82008-11-13 07:34:59 +0000687def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000688 "ldr", "h $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000689 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
Rafael Espindola82c678b2006-10-16 17:17:22 +0000690
Evan Cheng148cad82008-11-13 07:34:59 +0000691def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000692 "ldr", "b $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000693 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
Rafael Espindola82c678b2006-10-16 17:17:22 +0000694
Evan Chenga8e29892007-01-19 07:51:42 +0000695// Loads with sign extension
Evan Cheng148cad82008-11-13 07:34:59 +0000696def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000697 "ldr", "sh $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000698 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000699
Evan Cheng148cad82008-11-13 07:34:59 +0000700def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000701 "ldr", "sb $dst, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000702 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
Rafael Espindolac391d162006-10-23 20:34:27 +0000703
Chris Lattner9b37aaf2008-01-10 05:12:37 +0000704let mayLoad = 1 in {
Evan Chenga8e29892007-01-19 07:51:42 +0000705// Load doubleword
Evan Cheng358dec52009-06-15 08:28:29 +0000706def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
707 "ldr", "d $dst1, $addr", []>, Requires<[IsARM, HasV5T]>;
Rafael Espindolac391d162006-10-23 20:34:27 +0000708
Evan Chenga8e29892007-01-19 07:51:42 +0000709// Indexed loads
Evan Chengd87293c2008-11-06 08:47:38 +0000710def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000711 (ins addrmode2:$addr), LdFrm,
Evan Cheng0ff94f72007-08-07 01:37:15 +0000712 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
Rafael Espindoladc124a22006-05-18 21:45:49 +0000713
Evan Chengd87293c2008-11-06 08:47:38 +0000714def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000715 (ins GPR:$base, am2offset:$offset), LdFrm,
Evan Cheng0ff94f72007-08-07 01:37:15 +0000716 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
Rafael Espindola450856d2006-12-12 00:37:38 +0000717
Evan Chengd87293c2008-11-06 08:47:38 +0000718def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000719 (ins addrmode3:$addr), LdMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000720 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
Rafael Espindola4e307642006-09-08 16:59:47 +0000721
Evan Chengd87293c2008-11-06 08:47:38 +0000722def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000723 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000724 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
Lauro Ramos Venancio301009a2006-12-28 13:11:14 +0000725
Evan Chengd87293c2008-11-06 08:47:38 +0000726def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000727 (ins addrmode2:$addr), LdFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000728 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
Lauro Ramos Venancio301009a2006-12-28 13:11:14 +0000729
Evan Chengd87293c2008-11-06 08:47:38 +0000730def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000731 (ins GPR:$base,am2offset:$offset), LdFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000732 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000733
Evan Chengd87293c2008-11-06 08:47:38 +0000734def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000735 (ins addrmode3:$addr), LdMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000736 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000737
Evan Chengd87293c2008-11-06 08:47:38 +0000738def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000739 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
740 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000741
Evan Chengd87293c2008-11-06 08:47:38 +0000742def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000743 (ins addrmode3:$addr), LdMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000744 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000745
Evan Chengd87293c2008-11-06 08:47:38 +0000746def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000747 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000748 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
Chris Lattner9b37aaf2008-01-10 05:12:37 +0000749}
Evan Chenga8e29892007-01-19 07:51:42 +0000750
751// Store
Evan Cheng148cad82008-11-13 07:34:59 +0000752def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
Evan Cheng44bec522007-05-15 01:29:07 +0000753 "str", " $src, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000754 [(store GPR:$src, addrmode2:$addr)]>;
755
756// Stores with truncate
Evan Cheng148cad82008-11-13 07:34:59 +0000757def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000758 "str", "h $src, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000759 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
760
Evan Cheng148cad82008-11-13 07:34:59 +0000761def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000762 "str", "b $src, $addr",
Evan Chenga8e29892007-01-19 07:51:42 +0000763 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
764
765// Store doubleword
Chris Lattner2e48a702008-01-06 08:36:04 +0000766let mayStore = 1 in
Evan Cheng358dec52009-06-15 08:28:29 +0000767def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),StMiscFrm,
768 "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5T]>;
Evan Chenga8e29892007-01-19 07:51:42 +0000769
770// Indexed stores
Evan Chengd87293c2008-11-06 08:47:38 +0000771def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000772 (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
Evan Cheng44bec522007-05-15 01:29:07 +0000773 "str", " $src, [$base, $offset]!", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000774 [(set GPR:$base_wb,
775 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
776
Evan Chengd87293c2008-11-06 08:47:38 +0000777def STR_POST : AI2stwpo<(outs GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000778 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
Evan Cheng44bec522007-05-15 01:29:07 +0000779 "str", " $src, [$base], $offset", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000780 [(set GPR:$base_wb,
781 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
782
Evan Chengd87293c2008-11-06 08:47:38 +0000783def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000784 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000785 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000786 [(set GPR:$base_wb,
787 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
788
Evan Chengd87293c2008-11-06 08:47:38 +0000789def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000790 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000791 "str", "h $src, [$base], $offset", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000792 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
793 GPR:$base, am3offset:$offset))]>;
794
Evan Chengd87293c2008-11-06 08:47:38 +0000795def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000796 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000797 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000798 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
799 GPR:$base, am2offset:$offset))]>;
800
Evan Chengd87293c2008-11-06 08:47:38 +0000801def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
Evan Cheng148cad82008-11-13 07:34:59 +0000802 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
Evan Chengfd488ed2007-05-29 23:32:06 +0000803 "str", "b $src, [$base], $offset", "$base = $base_wb",
Evan Chenga8e29892007-01-19 07:51:42 +0000804 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
805 GPR:$base, am2offset:$offset))]>;
Evan Chenga8e29892007-01-19 07:51:42 +0000806
807//===----------------------------------------------------------------------===//
808// Load / store multiple Instructions.
809//
810
Evan Cheng64d80e32007-07-19 01:14:50 +0000811// FIXME: $dst1 should be a def.
Chris Lattner9b37aaf2008-01-10 05:12:37 +0000812let mayLoad = 1 in
Evan Chengd87293c2008-11-06 08:47:38 +0000813def LDM : AXI4ld<(outs),
Evan Cheng64d80e32007-07-19 01:14:50 +0000814 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
Evan Cheng3c4a4ff2008-11-12 07:18:38 +0000815 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
Evan Cheng44bec522007-05-15 01:29:07 +0000816 []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000817
Chris Lattner2e48a702008-01-06 08:36:04 +0000818let mayStore = 1 in
Evan Chengd87293c2008-11-06 08:47:38 +0000819def STM : AXI4st<(outs),
Evan Cheng64d80e32007-07-19 01:14:50 +0000820 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
Evan Cheng3c4a4ff2008-11-12 07:18:38 +0000821 LdStMulFrm, "stm${p}${addr:submode} $addr, $src1",
Evan Cheng44bec522007-05-15 01:29:07 +0000822 []>;
Evan Chenga8e29892007-01-19 07:51:42 +0000823
824//===----------------------------------------------------------------------===//
825// Move Instructions.
826//
827
Evan Chengcd799b92009-06-12 20:46:18 +0000828let neverHasSideEffects = 1 in
Evan Chengedda31c2008-11-05 18:35:52 +0000829def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm,
830 "mov", " $dst, $src", []>, UnaryDP;
831def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
832 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP;
Evan Chenga2515702007-03-19 07:09:02 +0000833
Evan Chengb3379fb2009-02-05 08:42:55 +0000834let isReMaterializable = 1, isAsCheapAsAMove = 1 in
Evan Chengedda31c2008-11-05 18:35:52 +0000835def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm,
836 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP;
Evan Cheng13ab0202007-07-10 18:08:01 +0000837
Evan Chenga9562552008-11-14 20:09:11 +0000838def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
Evan Cheng64d80e32007-07-19 01:14:50 +0000839 "mov", " $dst, $src, rrx",
Evan Chengedda31c2008-11-05 18:35:52 +0000840 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
Evan Chenga8e29892007-01-19 07:51:42 +0000841
842// These aren't really mov instructions, but we have to define them this way
843// due to flag operands.
844
Evan Cheng071a2792007-09-11 19:55:27 +0000845let Defs = [CPSR] in {
Evan Chenga9562552008-11-14 20:09:11 +0000846def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
Evan Chengfd488ed2007-05-29 23:32:06 +0000847 "mov", "s $dst, $src, lsr #1",
Evan Chengedda31c2008-11-05 18:35:52 +0000848 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
Evan Chenga9562552008-11-14 20:09:11 +0000849def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
Evan Chengfd488ed2007-05-29 23:32:06 +0000850 "mov", "s $dst, $src, asr #1",
Evan Chengedda31c2008-11-05 18:35:52 +0000851 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
Evan Cheng071a2792007-09-11 19:55:27 +0000852}
Evan Chenga8e29892007-01-19 07:51:42 +0000853
Evan Chenga8e29892007-01-19 07:51:42 +0000854//===----------------------------------------------------------------------===//
855// Extend Instructions.
856//
857
858// Sign extenders
859
Evan Cheng97f48c32008-11-06 22:15:19 +0000860defm SXTB : AI_unary_rrot<0b01101010,
861 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
862defm SXTH : AI_unary_rrot<0b01101011,
863 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
Evan Chenga8e29892007-01-19 07:51:42 +0000864
Evan Cheng97f48c32008-11-06 22:15:19 +0000865defm SXTAB : AI_bin_rrot<0b01101010,
866 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
867defm SXTAH : AI_bin_rrot<0b01101011,
868 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
Evan Chenga8e29892007-01-19 07:51:42 +0000869
870// TODO: SXT(A){B|H}16
871
872// Zero extenders
873
874let AddedComplexity = 16 in {
Evan Cheng97f48c32008-11-06 22:15:19 +0000875defm UXTB : AI_unary_rrot<0b01101110,
876 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
877defm UXTH : AI_unary_rrot<0b01101111,
878 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
879defm UXTB16 : AI_unary_rrot<0b01101100,
880 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
Evan Chenga8e29892007-01-19 07:51:42 +0000881
Bob Wilson1c76d0e2009-06-22 22:08:29 +0000882def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
Evan Chenga8e29892007-01-19 07:51:42 +0000883 (UXTB16r_rot GPR:$Src, 24)>;
Bob Wilson1c76d0e2009-06-22 22:08:29 +0000884def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
Evan Chenga8e29892007-01-19 07:51:42 +0000885 (UXTB16r_rot GPR:$Src, 8)>;
886
Evan Cheng97f48c32008-11-06 22:15:19 +0000887defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
Evan Chenga8e29892007-01-19 07:51:42 +0000888 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
Evan Cheng97f48c32008-11-06 22:15:19 +0000889defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
Evan Chenga8e29892007-01-19 07:51:42 +0000890 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
Rafael Espindola3c000bf2006-08-21 22:00:32 +0000891}
892
Evan Chenga8e29892007-01-19 07:51:42 +0000893// This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
894//defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
Rafael Espindola817e7fd2006-09-11 19:24:19 +0000895
Evan Chenga8e29892007-01-19 07:51:42 +0000896// TODO: UXT(A){B|H}16
897
898//===----------------------------------------------------------------------===//
899// Arithmetic Instructions.
900//
901
Jim Grosbach26421962008-10-14 20:36:24 +0000902defm ADD : AsI1_bin_irs<0b0100, "add",
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000903 BinOpFrag<(add node:$LHS, node:$RHS)>>;
Jim Grosbach26421962008-10-14 20:36:24 +0000904defm SUB : AsI1_bin_irs<0b0010, "sub",
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000905 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
Evan Chenga8e29892007-01-19 07:51:42 +0000906
Evan Chengc85e8322007-07-05 07:13:32 +0000907// ADD and SUB with 's' bit set.
Evan Cheng1e249e32009-06-25 20:59:23 +0000908defm ADDS : AI1_bin_s_irs<0b0100, "add",
909 BinOpFrag<(addc node:$LHS, node:$RHS)>>;
910defm SUBS : AI1_bin_s_irs<0b0010, "sub",
911 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
Evan Cheng2c614c52007-06-06 10:17:05 +0000912
Evan Cheng1e249e32009-06-25 20:59:23 +0000913// FIXME: Do not allow ADCS / SBCS to be predicated for now.
914defm ADCS : AI1_bin_cs_irs<0b0101, "adc",
915 BinOpFrag<(adde node:$LHS, node:$RHS)>>;
916defm SBCS : AI1_bin_cs_irs<0b0110, "sbc",
917 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
Evan Chenga8e29892007-01-19 07:51:42 +0000918
Evan Chengc85e8322007-07-05 07:13:32 +0000919// These don't define reg/reg forms, because they are handled above.
Evan Chengedda31c2008-11-05 18:35:52 +0000920def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
Evan Cheng13ab0202007-07-10 18:08:01 +0000921 "rsb", " $dst, $a, $b",
922 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
923
Evan Chengedda31c2008-11-05 18:35:52 +0000924def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
Evan Cheng13ab0202007-07-10 18:08:01 +0000925 "rsb", " $dst, $a, $b",
926 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
Evan Chengc85e8322007-07-05 07:13:32 +0000927
928// RSB with 's' bit set.
Evan Cheng071a2792007-09-11 19:55:27 +0000929let Defs = [CPSR] in {
Evan Chengedda31c2008-11-05 18:35:52 +0000930def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
Evan Chengc85e8322007-07-05 07:13:32 +0000931 "rsb", "s $dst, $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000932 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
Evan Chengedda31c2008-11-05 18:35:52 +0000933def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
Evan Chengc85e8322007-07-05 07:13:32 +0000934 "rsb", "s $dst, $a, $b",
Evan Cheng071a2792007-09-11 19:55:27 +0000935 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
936}
Evan Chengc85e8322007-07-05 07:13:32 +0000937
Evan Cheng1e249e32009-06-25 20:59:23 +0000938// FIXME: Do not allow RSC to be predicated for now.
939let Defs = [CPSR], Uses = [CPSR] in {
940def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
941 DPFrm, "rscs $dst, $a, $b",
942 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
943def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
944 DPSoRegFrm, "rscs $dst, $a, $b",
945 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
Evan Cheng071a2792007-09-11 19:55:27 +0000946}
Evan Cheng2c614c52007-06-06 10:17:05 +0000947
Evan Chenga8e29892007-01-19 07:51:42 +0000948// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
949def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
950 (SUBri GPR:$src, so_imm_neg:$imm)>;
951
952//def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
953// (SUBSri GPR:$src, so_imm_neg:$imm)>;
954//def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
955// (SBCri GPR:$src, so_imm_neg:$imm)>;
956
957// Note: These are implemented in C++ code, because they have to generate
958// ADD/SUBrs instructions, which use a complex pattern that a xform function
959// cannot produce.
960// (mul X, 2^n+1) -> (add (X << n), X)
961// (mul X, 2^n-1) -> (rsb X, (X << n))
962
963
964//===----------------------------------------------------------------------===//
965// Bitwise Instructions.
966//
967
Jim Grosbach26421962008-10-14 20:36:24 +0000968defm AND : AsI1_bin_irs<0b0000, "and",
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000969 BinOpFrag<(and node:$LHS, node:$RHS)>>;
Jim Grosbach26421962008-10-14 20:36:24 +0000970defm ORR : AsI1_bin_irs<0b1100, "orr",
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000971 BinOpFrag<(or node:$LHS, node:$RHS)>>;
Jim Grosbach26421962008-10-14 20:36:24 +0000972defm EOR : AsI1_bin_irs<0b0001, "eor",
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000973 BinOpFrag<(xor node:$LHS, node:$RHS)>>;
Jim Grosbach26421962008-10-14 20:36:24 +0000974defm BIC : AsI1_bin_irs<0b1110, "bic",
Evan Cheng7fd7ca42008-09-17 07:53:38 +0000975 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
Evan Chenga8e29892007-01-19 07:51:42 +0000976
Evan Chengedda31c2008-11-05 18:35:52 +0000977def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm,
978 "mvn", " $dst, $src",
979 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP;
980def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
981 "mvn", " $dst, $src",
982 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
Evan Chengb3379fb2009-02-05 08:42:55 +0000983let isReMaterializable = 1, isAsCheapAsAMove = 1 in
Evan Chengedda31c2008-11-05 18:35:52 +0000984def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
985 "mvn", " $dst, $imm",
986 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP;
Evan Chenga8e29892007-01-19 07:51:42 +0000987
988def : ARMPat<(and GPR:$src, so_imm_not:$imm),
989 (BICri GPR:$src, so_imm_not:$imm)>;
990
991//===----------------------------------------------------------------------===//
992// Multiply Instructions.
993//
994
Evan Chengfbc9d412008-11-06 01:21:28 +0000995def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
Evan Cheng12c3a532008-11-06 17:48:05 +0000996 "mul", " $dst, $a, $b",
997 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
Evan Chenga8e29892007-01-19 07:51:42 +0000998
Evan Chengfbc9d412008-11-06 01:21:28 +0000999def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
Evan Cheng12c3a532008-11-06 17:48:05 +00001000 "mla", " $dst, $a, $b, $c",
1001 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
Evan Chenga8e29892007-01-19 07:51:42 +00001002
1003// Extra precision multiplies with low / high results
Evan Chengcd799b92009-06-12 20:46:18 +00001004let neverHasSideEffects = 1 in {
Evan Chengfbc9d412008-11-06 01:21:28 +00001005def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1006 (ins GPR:$a, GPR:$b),
1007 "smull", " $ldst, $hdst, $a, $b", []>;
Evan Chenga8e29892007-01-19 07:51:42 +00001008
Evan Chengfbc9d412008-11-06 01:21:28 +00001009def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1010 (ins GPR:$a, GPR:$b),
1011 "umull", " $ldst, $hdst, $a, $b", []>;
Evan Chenga8e29892007-01-19 07:51:42 +00001012
1013// Multiply + accumulate
Evan Chengfbc9d412008-11-06 01:21:28 +00001014def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1015 (ins GPR:$a, GPR:$b),
1016 "smlal", " $ldst, $hdst, $a, $b", []>;
Evan Chenga8e29892007-01-19 07:51:42 +00001017
Evan Chengfbc9d412008-11-06 01:21:28 +00001018def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1019 (ins GPR:$a, GPR:$b),
1020 "umlal", " $ldst, $hdst, $a, $b", []>;
Evan Chenga8e29892007-01-19 07:51:42 +00001021
Evan Chengfbc9d412008-11-06 01:21:28 +00001022def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1023 (ins GPR:$a, GPR:$b),
1024 "umaal", " $ldst, $hdst, $a, $b", []>,
1025 Requires<[IsARM, HasV6]>;
Evan Chengcd799b92009-06-12 20:46:18 +00001026} // neverHasSideEffects
Evan Chenga8e29892007-01-19 07:51:42 +00001027
1028// Most significant word multiply
Evan Chengfbc9d412008-11-06 01:21:28 +00001029def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
Evan Cheng13ab0202007-07-10 18:08:01 +00001030 "smmul", " $dst, $a, $b",
1031 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
Evan Chengfbc9d412008-11-06 01:21:28 +00001032 Requires<[IsARM, HasV6]> {
1033 let Inst{7-4} = 0b0001;
1034 let Inst{15-12} = 0b1111;
1035}
Evan Cheng13ab0202007-07-10 18:08:01 +00001036
Evan Chengfbc9d412008-11-06 01:21:28 +00001037def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
Evan Cheng13ab0202007-07-10 18:08:01 +00001038 "smmla", " $dst, $a, $b, $c",
1039 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
Evan Chengfbc9d412008-11-06 01:21:28 +00001040 Requires<[IsARM, HasV6]> {
1041 let Inst{7-4} = 0b0001;
1042}
Evan Chenga8e29892007-01-19 07:51:42 +00001043
1044
Evan Chengfbc9d412008-11-06 01:21:28 +00001045def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
Evan Cheng44bec522007-05-15 01:29:07 +00001046 "smmls", " $dst, $a, $b, $c",
Evan Chenga8e29892007-01-19 07:51:42 +00001047 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
Evan Chengfbc9d412008-11-06 01:21:28 +00001048 Requires<[IsARM, HasV6]> {
1049 let Inst{7-4} = 0b1101;
1050}
Evan Chenga8e29892007-01-19 07:51:42 +00001051
Raul Herbster37fb5b12007-08-30 23:25:47 +00001052multiclass AI_smul<string opc, PatFrag opnode> {
Evan Chengeb4f52e2008-11-06 03:35:07 +00001053 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +00001054 !strconcat(opc, "bb"), " $dst, $a, $b",
Evan Cheng34b12d22007-01-19 20:27:35 +00001055 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1056 (sext_inreg GPR:$b, i16)))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001057 Requires<[IsARM, HasV5TE]> {
1058 let Inst{5} = 0;
1059 let Inst{6} = 0;
1060 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001061
Evan Chengeb4f52e2008-11-06 03:35:07 +00001062 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +00001063 !strconcat(opc, "bt"), " $dst, $a, $b",
Evan Cheng34b12d22007-01-19 20:27:35 +00001064 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001065 (sra GPR:$b, (i32 16))))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001066 Requires<[IsARM, HasV5TE]> {
1067 let Inst{5} = 0;
1068 let Inst{6} = 1;
1069 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001070
Evan Chengeb4f52e2008-11-06 03:35:07 +00001071 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +00001072 !strconcat(opc, "tb"), " $dst, $a, $b",
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001073 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
Evan Cheng34b12d22007-01-19 20:27:35 +00001074 (sext_inreg GPR:$b, i16)))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001075 Requires<[IsARM, HasV5TE]> {
1076 let Inst{5} = 1;
1077 let Inst{6} = 0;
1078 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001079
Evan Chengeb4f52e2008-11-06 03:35:07 +00001080 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +00001081 !strconcat(opc, "tt"), " $dst, $a, $b",
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001082 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1083 (sra GPR:$b, (i32 16))))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001084 Requires<[IsARM, HasV5TE]> {
1085 let Inst{5} = 1;
1086 let Inst{6} = 1;
1087 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001088
Evan Chengeb4f52e2008-11-06 03:35:07 +00001089 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +00001090 !strconcat(opc, "wb"), " $dst, $a, $b",
Evan Cheng34b12d22007-01-19 20:27:35 +00001091 [(set GPR:$dst, (sra (opnode GPR:$a,
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001092 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001093 Requires<[IsARM, HasV5TE]> {
1094 let Inst{5} = 1;
1095 let Inst{6} = 0;
1096 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001097
Evan Chengeb4f52e2008-11-06 03:35:07 +00001098 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
Evan Cheng44bec522007-05-15 01:29:07 +00001099 !strconcat(opc, "wt"), " $dst, $a, $b",
Evan Chenga8e29892007-01-19 07:51:42 +00001100 [(set GPR:$dst, (sra (opnode GPR:$a,
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001101 (sra GPR:$b, (i32 16))), (i32 16)))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001102 Requires<[IsARM, HasV5TE]> {
1103 let Inst{5} = 1;
1104 let Inst{6} = 1;
1105 }
Rafael Espindolabec2e382006-10-16 16:33:29 +00001106}
1107
Raul Herbster37fb5b12007-08-30 23:25:47 +00001108
1109multiclass AI_smla<string opc, PatFrag opnode> {
Evan Chengeb4f52e2008-11-06 03:35:07 +00001110 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +00001111 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
Evan Cheng34b12d22007-01-19 20:27:35 +00001112 [(set GPR:$dst, (add GPR:$acc,
1113 (opnode (sext_inreg GPR:$a, i16),
1114 (sext_inreg GPR:$b, i16))))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001115 Requires<[IsARM, HasV5TE]> {
1116 let Inst{5} = 0;
1117 let Inst{6} = 0;
1118 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001119
Evan Chengeb4f52e2008-11-06 03:35:07 +00001120 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +00001121 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
Evan Cheng34b12d22007-01-19 20:27:35 +00001122 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001123 (sra GPR:$b, (i32 16)))))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001124 Requires<[IsARM, HasV5TE]> {
1125 let Inst{5} = 0;
1126 let Inst{6} = 1;
1127 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001128
Evan Chengeb4f52e2008-11-06 03:35:07 +00001129 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +00001130 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001131 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
Evan Cheng34b12d22007-01-19 20:27:35 +00001132 (sext_inreg GPR:$b, i16))))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001133 Requires<[IsARM, HasV5TE]> {
1134 let Inst{5} = 1;
1135 let Inst{6} = 0;
1136 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001137
Evan Chengeb4f52e2008-11-06 03:35:07 +00001138 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +00001139 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001140 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1141 (sra GPR:$b, (i32 16)))))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001142 Requires<[IsARM, HasV5TE]> {
1143 let Inst{5} = 1;
1144 let Inst{6} = 1;
1145 }
Evan Chenga8e29892007-01-19 07:51:42 +00001146
Evan Chengeb4f52e2008-11-06 03:35:07 +00001147 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +00001148 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
Evan Cheng34b12d22007-01-19 20:27:35 +00001149 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001150 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001151 Requires<[IsARM, HasV5TE]> {
1152 let Inst{5} = 0;
1153 let Inst{6} = 0;
1154 }
Raul Herbster37fb5b12007-08-30 23:25:47 +00001155
Evan Chengeb4f52e2008-11-06 03:35:07 +00001156 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
Evan Cheng44bec522007-05-15 01:29:07 +00001157 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
Evan Chenga8e29892007-01-19 07:51:42 +00001158 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001159 (sra GPR:$b, (i32 16))), (i32 16))))]>,
Evan Chengeb4f52e2008-11-06 03:35:07 +00001160 Requires<[IsARM, HasV5TE]> {
1161 let Inst{5} = 0;
1162 let Inst{6} = 1;
1163 }
Rafael Espindola70673a12006-10-18 16:20:57 +00001164}
Rafael Espindola5c2aa0a2006-09-08 12:47:03 +00001165
Raul Herbster37fb5b12007-08-30 23:25:47 +00001166defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1167defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
Rafael Espindola27185192006-09-29 21:20:16 +00001168
Evan Chenga8e29892007-01-19 07:51:42 +00001169// TODO: Halfword multiple accumulate long: SMLAL<x><y>
1170// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
Rafael Espindola42b62f32006-10-13 13:14:59 +00001171
Evan Chenga8e29892007-01-19 07:51:42 +00001172//===----------------------------------------------------------------------===//
1173// Misc. Arithmetic Instructions.
1174//
Rafael Espindola0d9fe762006-10-10 16:33:47 +00001175
Evan Cheng8b59db32008-11-07 01:41:35 +00001176def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src),
Evan Cheng44bec522007-05-15 01:29:07 +00001177 "clz", " $dst, $src",
Evan Cheng8b59db32008-11-07 01:41:35 +00001178 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1179 let Inst{7-4} = 0b0001;
1180 let Inst{11-8} = 0b1111;
1181 let Inst{19-16} = 0b1111;
1182}
Rafael Espindola199dd672006-10-17 13:13:23 +00001183
Evan Cheng8b59db32008-11-07 01:41:35 +00001184def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
Evan Cheng44bec522007-05-15 01:29:07 +00001185 "rev", " $dst, $src",
Evan Cheng8b59db32008-11-07 01:41:35 +00001186 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1187 let Inst{7-4} = 0b0011;
1188 let Inst{11-8} = 0b1111;
1189 let Inst{19-16} = 0b1111;
1190}
Rafael Espindola199dd672006-10-17 13:13:23 +00001191
Evan Cheng8b59db32008-11-07 01:41:35 +00001192def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
Evan Cheng44bec522007-05-15 01:29:07 +00001193 "rev16", " $dst, $src",
Evan Chenga8e29892007-01-19 07:51:42 +00001194 [(set GPR:$dst,
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001195 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1196 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1197 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1198 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
Evan Cheng8b59db32008-11-07 01:41:35 +00001199 Requires<[IsARM, HasV6]> {
1200 let Inst{7-4} = 0b1011;
1201 let Inst{11-8} = 0b1111;
1202 let Inst{19-16} = 0b1111;
1203}
Rafael Espindola27185192006-09-29 21:20:16 +00001204
Evan Cheng8b59db32008-11-07 01:41:35 +00001205def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src),
Evan Cheng44bec522007-05-15 01:29:07 +00001206 "revsh", " $dst, $src",
Evan Chenga8e29892007-01-19 07:51:42 +00001207 [(set GPR:$dst,
1208 (sext_inreg
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001209 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1210 (shl GPR:$src, (i32 8))), i16))]>,
Evan Cheng8b59db32008-11-07 01:41:35 +00001211 Requires<[IsARM, HasV6]> {
1212 let Inst{7-4} = 0b1011;
1213 let Inst{11-8} = 0b1111;
1214 let Inst{19-16} = 0b1111;
1215}
Rafael Espindola27185192006-09-29 21:20:16 +00001216
Evan Cheng8b59db32008-11-07 01:41:35 +00001217def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1218 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1219 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
Evan Chenga8e29892007-01-19 07:51:42 +00001220 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1221 (and (shl GPR:$src2, (i32 imm:$shamt)),
1222 0xFFFF0000)))]>,
Evan Cheng8b59db32008-11-07 01:41:35 +00001223 Requires<[IsARM, HasV6]> {
1224 let Inst{6-4} = 0b001;
1225}
Rafael Espindola27185192006-09-29 21:20:16 +00001226
Evan Chenga8e29892007-01-19 07:51:42 +00001227// Alternate cases for PKHBT where identities eliminate some nodes.
1228def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1229 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1230def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1231 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
Rafael Espindola9e071f02006-10-02 19:30:56 +00001232
Rafael Espindolaa2845842006-10-05 16:48:49 +00001233
Evan Cheng8b59db32008-11-07 01:41:35 +00001234def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1235 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1236 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
Evan Chenga8e29892007-01-19 07:51:42 +00001237 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1238 (and (sra GPR:$src2, imm16_31:$shamt),
Evan Cheng8b59db32008-11-07 01:41:35 +00001239 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1240 let Inst{6-4} = 0b101;
1241}
Rafael Espindola9e071f02006-10-02 19:30:56 +00001242
Evan Chenga8e29892007-01-19 07:51:42 +00001243// Alternate cases for PKHTB where identities eliminate some nodes. Note that
1244// a shift amount of 0 is *not legal* here, it is PKHBT instead.
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001245def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
Evan Chenga8e29892007-01-19 07:51:42 +00001246 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1247def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1248 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1249 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
Rafael Espindolab47e1d02006-10-10 18:55:14 +00001250
Evan Chenga8e29892007-01-19 07:51:42 +00001251//===----------------------------------------------------------------------===//
1252// Comparison Instructions...
1253//
Rafael Espindolab47e1d02006-10-10 18:55:14 +00001254
Jim Grosbach26421962008-10-14 20:36:24 +00001255defm CMP : AI1_cmp_irs<0b1010, "cmp",
Evan Cheng0ff94f72007-08-07 01:37:15 +00001256 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
Jim Grosbach26421962008-10-14 20:36:24 +00001257defm CMN : AI1_cmp_irs<0b1011, "cmn",
Evan Cheng0ff94f72007-08-07 01:37:15 +00001258 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
Rafael Espindolae5bbd6d2006-10-07 14:24:52 +00001259
Evan Chenga8e29892007-01-19 07:51:42 +00001260// Note that TST/TEQ don't set all the same flags that CMP does!
Evan Chengd87293c2008-11-06 08:47:38 +00001261defm TST : AI1_cmp_irs<0b1000, "tst",
Evan Cheng0ff94f72007-08-07 01:37:15 +00001262 BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
Evan Chengd87293c2008-11-06 08:47:38 +00001263defm TEQ : AI1_cmp_irs<0b1001, "teq",
Evan Cheng0ff94f72007-08-07 01:37:15 +00001264 BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
Lauro Ramos Venancio99966632007-04-02 01:30:03 +00001265
Jim Grosbach26421962008-10-14 20:36:24 +00001266defm CMPnz : AI1_cmp_irs<0b1010, "cmp",
Evan Cheng0ff94f72007-08-07 01:37:15 +00001267 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
Jim Grosbach26421962008-10-14 20:36:24 +00001268defm CMNnz : AI1_cmp_irs<0b1011, "cmn",
Evan Cheng0ff94f72007-08-07 01:37:15 +00001269 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
Evan Cheng2c614c52007-06-06 10:17:05 +00001270
1271def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1272 (CMNri GPR:$src, so_imm_neg:$imm)>;
Lauro Ramos Venancio99966632007-04-02 01:30:03 +00001273
1274def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1275 (CMNri GPR:$src, so_imm_neg:$imm)>;
1276
Rafael Espindolae5bbd6d2006-10-07 14:24:52 +00001277
Evan Chenga8e29892007-01-19 07:51:42 +00001278// Conditional moves
Evan Chengc85e8322007-07-05 07:13:32 +00001279// FIXME: should be able to write a pattern for ARMcmov, but can't use
1280// a two-value operand where a dag node expects two operands. :(
Evan Chengd87293c2008-11-06 08:47:38 +00001281def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
Evan Chengedda31c2008-11-05 18:35:52 +00001282 "mov", " $dst, $true",
Evan Chengc85e8322007-07-05 07:13:32 +00001283 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
Evan Chengd87293c2008-11-06 08:47:38 +00001284 RegConstraint<"$false = $dst">, UnaryDP;
Rafael Espindola493a7fc2006-10-10 20:38:57 +00001285
Evan Chengd87293c2008-11-06 08:47:38 +00001286def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1287 (ins GPR:$false, so_reg:$true), DPSoRegFrm,
Evan Chengedda31c2008-11-05 18:35:52 +00001288 "mov", " $dst, $true",
Evan Chengc85e8322007-07-05 07:13:32 +00001289 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
Evan Chengedda31c2008-11-05 18:35:52 +00001290 RegConstraint<"$false = $dst">, UnaryDP;
Rafael Espindola2dc0f2b2006-10-09 17:50:29 +00001291
Evan Chengd87293c2008-11-06 08:47:38 +00001292def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1293 (ins GPR:$false, so_imm:$true), DPFrm,
Evan Chengedda31c2008-11-05 18:35:52 +00001294 "mov", " $dst, $true",
Evan Chengc85e8322007-07-05 07:13:32 +00001295 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
Evan Chengedda31c2008-11-05 18:35:52 +00001296 RegConstraint<"$false = $dst">, UnaryDP;
Rafael Espindolad9ae7782006-10-07 13:46:42 +00001297
Rafael Espindola4b20fbc2006-10-10 12:56:00 +00001298
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001299//===----------------------------------------------------------------------===//
1300// TLS Instructions
1301//
1302
1303// __aeabi_read_tp preserves the registers r1-r3.
Evan Cheng13ab0202007-07-10 18:08:01 +00001304let isCall = 1,
1305 Defs = [R0, R12, LR, CPSR] in {
Evan Cheng12c3a532008-11-06 17:48:05 +00001306 def TPsoft : ABXI<0b1011, (outs), (ins),
Evan Chengdcc50a42007-05-18 01:53:54 +00001307 "bl __aeabi_read_tp",
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001308 [(set R0, ARMthread_pointer)]>;
1309}
Rafael Espindolac01c87c2006-10-17 20:33:13 +00001310
Evan Chenga8e29892007-01-19 07:51:42 +00001311//===----------------------------------------------------------------------===//
Jim Grosbach0e0da732009-05-12 23:59:14 +00001312// SJLJ Exception handling intrinsics
Jim Grosbachf9570122009-05-14 00:46:35 +00001313// eh_sjlj_setjmp() is a three instruction sequence to store the return
1314// address and save #0 in R0 for the non-longjmp case.
Jim Grosbach0e0da732009-05-12 23:59:14 +00001315// Since by its nature we may be coming from some other function to get
1316// here, and we're using the stack frame for the containing function to
1317// save/restore registers, we can't keep anything live in regs across
Jim Grosbachf9570122009-05-14 00:46:35 +00001318// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
Jim Grosbach0e0da732009-05-12 23:59:14 +00001319// when we get here from a longjmp(). We force everthing out of registers
Jim Grosbachf9570122009-05-14 00:46:35 +00001320// except for our own input by listing the relevant registers in Defs. By
1321// doing so, we also cause the prologue/epilogue code to actively preserve
1322// all of the callee-saved resgisters, which is exactly what we want.
Jim Grosbach0e0da732009-05-12 23:59:14 +00001323let Defs =
1324 [ R0, R1, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR,
1325 D0, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 ] in {
Jim Grosbachf9570122009-05-14 00:46:35 +00001326 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
Jim Grosbach0e0da732009-05-12 23:59:14 +00001327 AddrModeNone, SizeSpecial, IndexModeNone, Pseudo,
1328 "add r0, pc, #4\n\t"
1329 "str r0, [$src, #+4]\n\t"
Jim Grosbachf9570122009-05-14 00:46:35 +00001330 "mov r0, #0 @ eh_setjmp", "",
1331 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
Jim Grosbach0e0da732009-05-12 23:59:14 +00001332}
1333
1334//===----------------------------------------------------------------------===//
Evan Chenga8e29892007-01-19 07:51:42 +00001335// Non-Instruction Patterns
1336//
Rafael Espindola5aca9272006-10-07 14:03:39 +00001337
Evan Chenga8e29892007-01-19 07:51:42 +00001338// ConstantPool, GlobalAddress, and JumpTable
1339def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1340def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1341def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
Evan Chengc70d1842007-03-20 08:11:30 +00001342 (LEApcrelJT tjumptable:$dst, imm:$id)>;
Rafael Espindola5aca9272006-10-07 14:03:39 +00001343
Evan Chenga8e29892007-01-19 07:51:42 +00001344// Large immediate handling.
Rafael Espindola0505be02006-10-16 21:10:32 +00001345
Evan Chenga8e29892007-01-19 07:51:42 +00001346// Two piece so_imms.
Dan Gohmand45eddd2007-06-26 00:48:07 +00001347let isReMaterializable = 1 in
Evan Chengd87293c2008-11-06 08:47:38 +00001348def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), Pseudo,
Evan Cheng44bec522007-05-15 01:29:07 +00001349 "mov", " $dst, $src",
Evan Cheng90922132008-11-06 02:25:39 +00001350 [(set GPR:$dst, so_imm2part:$src)]>;
Rafael Espindolaf621abc2006-10-17 13:36:07 +00001351
Evan Chenga8e29892007-01-19 07:51:42 +00001352def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1353 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1354 (so_imm2part_2 imm:$RHS))>;
1355def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1356 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1357 (so_imm2part_2 imm:$RHS))>;
Rafael Espindolaf621abc2006-10-17 13:36:07 +00001358
Evan Chenga8e29892007-01-19 07:51:42 +00001359// TODO: add,sub,and, 3-instr forms?
Rafael Espindola0505be02006-10-16 21:10:32 +00001360
Rafael Espindola24357862006-10-19 17:05:03 +00001361
Evan Chenga8e29892007-01-19 07:51:42 +00001362// Direct calls
Bob Wilson54fc1242009-06-22 21:01:46 +00001363def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1364 Requires<[IsNotDarwin]>;
1365def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1366 Requires<[IsDarwin]>;
Rafael Espindola9dca7ad2006-11-01 14:13:27 +00001367
Evan Chenga8e29892007-01-19 07:51:42 +00001368// zextload i1 -> zextload i8
1369def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
Lauro Ramos Venancioa8f9f4a2006-12-26 19:30:42 +00001370
Evan Chenga8e29892007-01-19 07:51:42 +00001371// extload -> zextload
1372def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1373def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1374def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
Rafael Espindola9dca7ad2006-11-01 14:13:27 +00001375
Evan Cheng83b5cf02008-11-05 23:22:34 +00001376def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1377def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1378
Evan Cheng34b12d22007-01-19 20:27:35 +00001379// smul* and smla*
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001380def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1381 (sra (shl GPR:$b, (i32 16)), (i32 16))),
Evan Cheng34b12d22007-01-19 20:27:35 +00001382 (SMULBB GPR:$a, GPR:$b)>;
1383def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1384 (SMULBB GPR:$a, GPR:$b)>;
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001385def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1386 (sra GPR:$b, (i32 16))),
Evan Cheng34b12d22007-01-19 20:27:35 +00001387 (SMULBT GPR:$a, GPR:$b)>;
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001388def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
Evan Cheng34b12d22007-01-19 20:27:35 +00001389 (SMULBT GPR:$a, GPR:$b)>;
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001390def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1391 (sra (shl GPR:$b, (i32 16)), (i32 16))),
Evan Cheng34b12d22007-01-19 20:27:35 +00001392 (SMULTB GPR:$a, GPR:$b)>;
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001393def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
Evan Cheng34b12d22007-01-19 20:27:35 +00001394 (SMULTB GPR:$a, GPR:$b)>;
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001395def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1396 (i32 16)),
Evan Cheng34b12d22007-01-19 20:27:35 +00001397 (SMULWB GPR:$a, GPR:$b)>;
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001398def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
Evan Cheng34b12d22007-01-19 20:27:35 +00001399 (SMULWB GPR:$a, GPR:$b)>;
1400
1401def : ARMV5TEPat<(add GPR:$acc,
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001402 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1403 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
Evan Cheng34b12d22007-01-19 20:27:35 +00001404 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1405def : ARMV5TEPat<(add GPR:$acc,
1406 (mul sext_16_node:$a, sext_16_node:$b)),
1407 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1408def : ARMV5TEPat<(add GPR:$acc,
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001409 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1410 (sra GPR:$b, (i32 16)))),
Evan Cheng34b12d22007-01-19 20:27:35 +00001411 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1412def : ARMV5TEPat<(add GPR:$acc,
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001413 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
Evan Cheng34b12d22007-01-19 20:27:35 +00001414 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1415def : ARMV5TEPat<(add GPR:$acc,
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001416 (mul (sra GPR:$a, (i32 16)),
1417 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
Evan Cheng34b12d22007-01-19 20:27:35 +00001418 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1419def : ARMV5TEPat<(add GPR:$acc,
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001420 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
Evan Cheng34b12d22007-01-19 20:27:35 +00001421 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1422def : ARMV5TEPat<(add GPR:$acc,
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001423 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1424 (i32 16))),
Evan Cheng34b12d22007-01-19 20:27:35 +00001425 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1426def : ARMV5TEPat<(add GPR:$acc,
Bob Wilson1c76d0e2009-06-22 22:08:29 +00001427 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
Evan Cheng34b12d22007-01-19 20:27:35 +00001428 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1429
Evan Chenga8e29892007-01-19 07:51:42 +00001430//===----------------------------------------------------------------------===//
1431// Thumb Support
1432//
1433
1434include "ARMInstrThumb.td"
1435
1436//===----------------------------------------------------------------------===//
Anton Korobeynikov52237112009-06-17 18:13:58 +00001437// Thumb2 Support
1438//
1439
1440include "ARMInstrThumb2.td"
1441
1442//===----------------------------------------------------------------------===//
Evan Chenga8e29892007-01-19 07:51:42 +00001443// Floating Point Support
1444//
1445
1446include "ARMInstrVFP.td"
Bob Wilson5bafff32009-06-22 23:27:02 +00001447
1448//===----------------------------------------------------------------------===//
1449// Advanced SIMD (NEON) Support
1450//
1451
1452include "ARMInstrNEON.td"