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Chris Lattnera3b8b5c2004-07-23 17:56:30 +00001//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LiveInterval analysis pass which is used
11// by the Linear Scan Register allocator. This pass linearizes the
12// basic blocks of the function in DFS order and uses the
13// LiveVariables pass to conservatively compute live intervals for
14// each virtual and physical register.
15//
16//===----------------------------------------------------------------------===//
17
Jakob Stoklund Olesen4281e202012-01-07 07:39:47 +000018#define DEBUG_TYPE "regalloc"
Chris Lattner3c3fe462005-09-21 04:19:09 +000019#include "llvm/CodeGen/LiveIntervalAnalysis.h"
Chris Lattner015959e2004-05-01 21:24:39 +000020#include "llvm/Value.h"
Dan Gohman6d69ba82008-07-25 00:02:30 +000021#include "llvm/Analysis/AliasAnalysis.h"
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000022#include "llvm/CodeGen/LiveVariables.h"
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000023#include "llvm/CodeGen/MachineInstr.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000024#include "llvm/CodeGen/MachineRegisterInfo.h"
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000025#include "llvm/CodeGen/Passes.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +000026#include "llvm/Target/TargetRegisterInfo.h"
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000027#include "llvm/Target/TargetInstrInfo.h"
28#include "llvm/Target/TargetMachine.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000029#include "llvm/Support/CommandLine.h"
30#include "llvm/Support/Debug.h"
Torok Edwin7d696d82009-07-11 13:10:19 +000031#include "llvm/Support/ErrorHandling.h"
32#include "llvm/Support/raw_ostream.h"
Andrew Trickd35576b2012-02-13 20:44:42 +000033#include "llvm/ADT/DenseSet.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000034#include "llvm/ADT/Statistic.h"
35#include "llvm/ADT/STLExtras.h"
Alkis Evlogimenos20aa4742004-09-03 18:19:51 +000036#include <algorithm>
Lang Hamesf41538d2009-06-02 16:53:25 +000037#include <limits>
Jeff Cohen97af7512006-12-02 02:22:01 +000038#include <cmath>
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000039using namespace llvm;
40
Dan Gohman844731a2008-05-13 00:00:25 +000041// Hidden options for help debugging.
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +000042static cl::opt<bool> DisableReMat("disable-rematerialization",
Dan Gohman844731a2008-05-13 00:00:25 +000043 cl::init(false), cl::Hidden);
Evan Cheng81a03822007-11-17 00:40:40 +000044
Evan Cheng752195e2009-09-14 21:33:42 +000045STATISTIC(numIntervals , "Number of original intervals");
Chris Lattnercd3245a2006-12-19 22:41:21 +000046
Devang Patel19974732007-05-03 01:11:54 +000047char LiveIntervals::ID = 0;
Owen Anderson2ab36d32010-10-12 19:48:12 +000048INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
49 "Live Interval Analysis", false, false)
Andrew Trick8dd26252012-02-10 04:10:36 +000050INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
Owen Anderson2ab36d32010-10-12 19:48:12 +000051INITIALIZE_PASS_DEPENDENCY(LiveVariables)
Andrew Trick8dd26252012-02-10 04:10:36 +000052INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
Owen Anderson2ab36d32010-10-12 19:48:12 +000053INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
Owen Anderson2ab36d32010-10-12 19:48:12 +000054INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
Owen Andersonce665bd2010-10-07 22:25:06 +000055 "Live Interval Analysis", false, false)
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000056
Chris Lattnerf7da2c72006-08-24 22:43:55 +000057void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
Dan Gohman845012e2009-07-31 23:37:33 +000058 AU.setPreservesCFG();
Dan Gohman6d69ba82008-07-25 00:02:30 +000059 AU.addRequired<AliasAnalysis>();
60 AU.addPreserved<AliasAnalysis>();
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +000061 AU.addRequired<LiveVariables>();
Evan Cheng148341c2010-08-17 21:00:37 +000062 AU.addPreserved<LiveVariables>();
Andrew Trickd35576b2012-02-13 20:44:42 +000063 AU.addPreservedID(MachineLoopInfoID);
Bill Wendling67d65bb2008-01-04 20:54:55 +000064 AU.addPreservedID(MachineDominatorsID);
Lang Hames233a60e2009-11-03 23:52:08 +000065 AU.addPreserved<SlotIndexes>();
66 AU.addRequiredTransitive<SlotIndexes>();
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +000067 MachineFunctionPass::getAnalysisUsage(AU);
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000068}
69
Chris Lattnerf7da2c72006-08-24 22:43:55 +000070void LiveIntervals::releaseMemory() {
Owen Anderson03857b22008-08-13 21:49:13 +000071 // Free the live intervals themselves.
Owen Anderson20e28392008-08-13 22:08:30 +000072 for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
Bob Wilsond6a6b3b2010-03-24 20:25:25 +000073 E = r2iMap_.end(); I != E; ++I)
Owen Anderson03857b22008-08-13 21:49:13 +000074 delete I->second;
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +000075
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +000076 r2iMap_.clear();
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +000077 RegMaskSlots.clear();
78 RegMaskBits.clear();
Jakob Stoklund Olesen34e85d02012-02-10 01:26:29 +000079 RegMaskBlocks.clear();
Lang Hamesffd13262009-07-09 03:57:02 +000080
Benjamin Kramerce9a20b2010-06-26 11:30:59 +000081 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
82 VNInfoAllocator.Reset();
Alkis Evlogimenos08cec002004-01-31 19:59:32 +000083}
84
Owen Anderson80b3ce62008-05-28 20:54:50 +000085/// runOnMachineFunction - Register allocate the whole function
86///
87bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
88 mf_ = &fn;
89 mri_ = &mf_->getRegInfo();
90 tm_ = &fn.getTarget();
91 tri_ = tm_->getRegisterInfo();
92 tii_ = tm_->getInstrInfo();
Dan Gohman6d69ba82008-07-25 00:02:30 +000093 aa_ = &getAnalysis<AliasAnalysis>();
Owen Anderson80b3ce62008-05-28 20:54:50 +000094 lv_ = &getAnalysis<LiveVariables>();
Lang Hames233a60e2009-11-03 23:52:08 +000095 indexes_ = &getAnalysis<SlotIndexes>();
Owen Anderson80b3ce62008-05-28 20:54:50 +000096 allocatableRegs_ = tri_->getAllocatableSet(fn);
Lang Hames342c64c2012-02-14 18:51:53 +000097 reservedRegs_ = tri_->getReservedRegs(fn);
Owen Anderson80b3ce62008-05-28 20:54:50 +000098
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +000099 computeIntervals();
Alkis Evlogimenos843b1602004-02-15 10:24:21 +0000100
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000101 numIntervals += getNumIntervals();
102
Chris Lattner70ca3582004-09-30 15:59:17 +0000103 DEBUG(dump());
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000104 return true;
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000105}
106
Chris Lattner70ca3582004-09-30 15:59:17 +0000107/// print - Implement the dump method.
Chris Lattner45cfe542009-08-23 06:03:38 +0000108void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
Chris Lattner705e07f2009-08-23 03:41:05 +0000109 OS << "********** INTERVALS **********\n";
Jakob Stoklund Olesenf658af52012-02-14 23:46:21 +0000110
111 // Dump the physregs.
112 for (unsigned Reg = 1, RegE = tri_->getNumRegs(); Reg != RegE; ++Reg)
113 if (const LiveInterval *LI = r2iMap_.lookup(Reg)) {
114 LI->print(OS, tri_);
115 OS << '\n';
116 }
117
118 // Dump the virtregs.
119 for (unsigned Reg = 0, RegE = mri_->getNumVirtRegs(); Reg != RegE; ++Reg)
120 if (const LiveInterval *LI =
121 r2iMap_.lookup(TargetRegisterInfo::index2VirtReg(Reg))) {
122 LI->print(OS, tri_);
123 OS << '\n';
124 }
Chris Lattner70ca3582004-09-30 15:59:17 +0000125
Evan Cheng752195e2009-09-14 21:33:42 +0000126 printInstrs(OS);
127}
128
129void LiveIntervals::printInstrs(raw_ostream &OS) const {
Chris Lattner705e07f2009-08-23 03:41:05 +0000130 OS << "********** MACHINEINSTRS **********\n";
Jakob Stoklund Olesenf4a1e1a2010-10-26 20:21:46 +0000131 mf_->print(OS, indexes_);
Chris Lattner70ca3582004-09-30 15:59:17 +0000132}
133
Evan Cheng752195e2009-09-14 21:33:42 +0000134void LiveIntervals::dumpInstrs() const {
David Greene8a342292010-01-04 22:49:02 +0000135 printInstrs(dbgs());
Evan Cheng752195e2009-09-14 21:33:42 +0000136}
137
Evan Chengafff40a2010-05-04 20:26:52 +0000138static
Evan Cheng37499432010-05-05 18:27:40 +0000139bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
Evan Chengafff40a2010-05-04 20:26:52 +0000140 unsigned Reg = MI.getOperand(MOIdx).getReg();
141 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
142 const MachineOperand &MO = MI.getOperand(i);
143 if (!MO.isReg())
144 continue;
145 if (MO.getReg() == Reg && MO.isDef()) {
146 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
147 MI.getOperand(MOIdx).getSubReg() &&
Jakob Stoklund Olesened2185e2010-07-06 23:26:25 +0000148 (MO.getSubReg() || MO.isImplicit()));
Evan Chengafff40a2010-05-04 20:26:52 +0000149 return true;
150 }
151 }
152 return false;
153}
154
Evan Cheng37499432010-05-05 18:27:40 +0000155/// isPartialRedef - Return true if the specified def at the specific index is
156/// partially re-defining the specified live interval. A common case of this is
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000157/// a definition of the sub-register.
Evan Cheng37499432010-05-05 18:27:40 +0000158bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
159 LiveInterval &interval) {
160 if (!MO.getSubReg() || MO.isEarlyClobber())
161 return false;
162
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000163 SlotIndex RedefIndex = MIIdx.getRegSlot();
Evan Cheng37499432010-05-05 18:27:40 +0000164 const LiveRange *OldLR =
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000165 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
Lang Hames6e2968c2010-09-25 12:04:16 +0000166 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
167 if (DefMI != 0) {
Evan Cheng37499432010-05-05 18:27:40 +0000168 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
169 }
170 return false;
171}
172
Chris Lattnerbe4f88a2006-08-22 18:19:46 +0000173void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000174 MachineBasicBlock::iterator mi,
Lang Hames233a60e2009-11-03 23:52:08 +0000175 SlotIndex MIIdx,
Lang Hames86511252009-09-04 20:41:11 +0000176 MachineOperand& MO,
Evan Chengef0732d2008-07-10 07:35:43 +0000177 unsigned MOIdx,
Chris Lattnerbe4f88a2006-08-22 18:19:46 +0000178 LiveInterval &interval) {
Jakob Stoklund Olesen43142682011-01-09 03:05:53 +0000179 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
Evan Cheng419852c2008-04-03 16:39:43 +0000180
Alkis Evlogimenos70651572004-08-04 09:46:56 +0000181 // Virtual registers may be defined multiple times (due to phi
182 // elimination and 2-addr elimination). Much of what we do only has to be
183 // done once for the vreg. We use an empty interval to detect the first
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000184 // time we see a vreg.
Evan Chengd129d732009-07-17 19:43:40 +0000185 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000186 if (interval.empty()) {
187 // Get the Idx of the defining instructions.
Jakob Stoklund Olesend14614e2011-11-13 22:05:42 +0000188 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
Jakob Stoklund Olesen63e6a482010-05-21 16:32:16 +0000189
190 // Make sure the first definition is not a partial redefinition. Add an
191 // <imp-def> of the full register.
Jakob Stoklund Olesenb0e1bc72011-10-05 16:51:21 +0000192 // FIXME: LiveIntervals shouldn't modify the code like this. Whoever
193 // created the machine instruction should annotate it with <undef> flags
194 // as needed. Then we can simply assert here. The REG_SEQUENCE lowering
195 // is the main suspect.
Jakob Stoklund Olesen7016cf62011-10-04 21:49:33 +0000196 if (MO.getSubReg()) {
Jakob Stoklund Olesen63e6a482010-05-21 16:32:16 +0000197 mi->addRegisterDefined(interval.reg);
Jakob Stoklund Olesen7016cf62011-10-04 21:49:33 +0000198 // Mark all defs of interval.reg on this instruction as reading <undef>.
199 for (unsigned i = MOIdx, e = mi->getNumOperands(); i != e; ++i) {
200 MachineOperand &MO2 = mi->getOperand(i);
201 if (MO2.isReg() && MO2.getReg() == interval.reg && MO2.getSubReg())
202 MO2.setIsUndef();
203 }
204 }
Jakob Stoklund Olesen63e6a482010-05-21 16:32:16 +0000205
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000206 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
Evan Cheng7ecb38b2007-08-29 20:45:00 +0000207 assert(ValNo->id == 0 && "First value in interval is not 0?");
Chris Lattner7ac2d312004-07-24 02:59:07 +0000208
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000209 // Loop over all of the blocks that the vreg is defined in. There are
210 // two cases we have to handle here. The most common case is a vreg
211 // whose lifetime is contained within a basic block. In this case there
212 // will be a single kill, in MBB, which comes after the definition.
213 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
214 // FIXME: what about dead vars?
Lang Hames233a60e2009-11-03 23:52:08 +0000215 SlotIndex killIdx;
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000216 if (vi.Kills[0] != mi)
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000217 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000218 else
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000219 killIdx = defIndex.getDeadSlot();
Chris Lattner6097d132004-07-19 02:15:56 +0000220
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000221 // If the kill happens after the definition, we have an intra-block
222 // live range.
223 if (killIdx > defIndex) {
Jeffrey Yasskin493a3d02009-05-26 18:27:15 +0000224 assert(vi.AliveBlocks.empty() &&
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000225 "Shouldn't be alive across any blocks!");
Evan Cheng7ecb38b2007-08-29 20:45:00 +0000226 LiveRange LR(defIndex, killIdx, ValNo);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000227 interval.addRange(LR);
David Greene8a342292010-01-04 22:49:02 +0000228 DEBUG(dbgs() << " +" << LR << "\n");
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000229 return;
230 }
Alkis Evlogimenosdd2cc652003-12-18 08:48:48 +0000231 }
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000232
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000233 // The other case we handle is when a virtual register lives to the end
234 // of the defining block, potentially live across some blocks, then is
235 // live into some number of blocks, but gets killed. Start by adding a
236 // range that goes from this definition to the end of the defining block.
Lang Hames74ab5ee2009-12-22 00:11:50 +0000237 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
David Greene8a342292010-01-04 22:49:02 +0000238 DEBUG(dbgs() << " +" << NewLR);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000239 interval.addRange(NewLR);
240
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000241 bool PHIJoin = lv_->isPHIJoin(interval.reg);
242
243 if (PHIJoin) {
244 // A phi join register is killed at the end of the MBB and revived as a new
245 // valno in the killing blocks.
246 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
247 DEBUG(dbgs() << " phi-join");
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000248 ValNo->setHasPHIKill(true);
249 } else {
250 // Iterate over all of the blocks that the variable is completely
251 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
252 // live interval.
253 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
254 E = vi.AliveBlocks.end(); I != E; ++I) {
255 MachineBasicBlock *aliveBlock = mf_->getBlockNumbered(*I);
256 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo);
257 interval.addRange(LR);
258 DEBUG(dbgs() << " +" << LR);
259 }
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000260 }
261
262 // Finally, this virtual register is live from the start of any killing
263 // block to the 'use' slot of the killing instruction.
264 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
265 MachineInstr *Kill = vi.Kills[i];
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000266 SlotIndex Start = getMBBStartIdx(Kill->getParent());
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000267 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000268
269 // Create interval with one of a NEW value number. Note that this value
270 // number isn't actually defined by an instruction, weird huh? :)
271 if (PHIJoin) {
Lang Hames6e2968c2010-09-25 12:04:16 +0000272 assert(getInstructionFromIndex(Start) == 0 &&
273 "PHI def index points at actual instruction.");
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000274 ValNo = interval.getNextValue(Start, VNInfoAllocator);
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000275 ValNo->setIsPHIDef(true);
276 }
277 LiveRange LR(Start, killIdx, ValNo);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000278 interval.addRange(LR);
David Greene8a342292010-01-04 22:49:02 +0000279 DEBUG(dbgs() << " +" << LR);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000280 }
281
282 } else {
Evan Cheng37499432010-05-05 18:27:40 +0000283 if (MultipleDefsBySameMI(*mi, MOIdx))
Nick Lewycky761fd4c2010-05-20 03:30:09 +0000284 // Multiple defs of the same virtual register by the same instruction.
285 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
Evan Chengafff40a2010-05-04 20:26:52 +0000286 // This is likely due to elimination of REG_SEQUENCE instructions. Return
287 // here since there is nothing to do.
288 return;
289
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000290 // If this is the second time we see a virtual register definition, it
291 // must be due to phi elimination or two addr elimination. If this is
Evan Chengbf105c82006-11-03 03:04:46 +0000292 // the result of two address elimination, then the vreg is one of the
293 // def-and-use register operand.
Evan Cheng37499432010-05-05 18:27:40 +0000294
295 // It may also be partial redef like this:
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000296 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
297 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
Evan Cheng37499432010-05-05 18:27:40 +0000298 bool PartReDef = isPartialRedef(MIIdx, MO, interval);
299 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000300 // If this is a two-address definition, then we have already processed
301 // the live range. The only problem is that we didn't realize there
302 // are actually two values in the live interval. Because of this we
303 // need to take the LiveRegion that defines this register and split it
304 // into two values.
Jakob Stoklund Olesend14614e2011-11-13 22:05:42 +0000305 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000306
Lang Hames35f291d2009-09-12 03:34:03 +0000307 const LiveRange *OldLR =
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000308 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
Evan Cheng7ecb38b2007-08-29 20:45:00 +0000309 VNInfo *OldValNo = OldLR->valno;
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000310 SlotIndex DefIndex = OldValNo->def.getRegSlot();
Evan Cheng4f8ff162007-08-11 00:59:19 +0000311
Jakob Stoklund Olesenc66d0f22010-06-16 21:29:40 +0000312 // Delete the previous value, which should be short and continuous,
Chris Lattnerbe4f88a2006-08-22 18:19:46 +0000313 // because the 2-addr copy must be in the same MBB as the redef.
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000314 interval.removeRange(DefIndex, RedefIndex);
Alkis Evlogimenos70651572004-08-04 09:46:56 +0000315
Chris Lattner91725b72006-08-31 05:54:43 +0000316 // The new value number (#1) is defined by the instruction we claimed
317 // defined value #0.
Lang Hames6e2968c2010-09-25 12:04:16 +0000318 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
Lang Hames857c4e02009-06-17 21:01:20 +0000319
Chris Lattner91725b72006-08-31 05:54:43 +0000320 // Value#0 is now defined by the 2-addr instruction.
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000321 OldValNo->def = RedefIndex;
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000322
Chris Lattnerbe4f88a2006-08-22 18:19:46 +0000323 // Add the new live interval which replaces the range for the input copy.
324 LiveRange LR(DefIndex, RedefIndex, ValNo);
David Greene8a342292010-01-04 22:49:02 +0000325 DEBUG(dbgs() << " replace range with " << LR);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000326 interval.addRange(LR);
327
328 // If this redefinition is dead, we need to add a dummy unit live
329 // range covering the def slot.
Owen Anderson6b098de2008-06-25 23:39:39 +0000330 if (MO.isDead())
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000331 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
Lang Hames233a60e2009-11-03 23:52:08 +0000332 OldValNo));
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000333
Bill Wendling8e6179f2009-08-22 20:18:03 +0000334 DEBUG({
David Greene8a342292010-01-04 22:49:02 +0000335 dbgs() << " RESULT: ";
336 interval.print(dbgs(), tri_);
Bill Wendling8e6179f2009-08-22 20:18:03 +0000337 });
Evan Cheng37499432010-05-05 18:27:40 +0000338 } else if (lv_->isPHIJoin(interval.reg)) {
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000339 // In the case of PHI elimination, each variable definition is only
340 // live until the end of the block. We've already taken care of the
341 // rest of the live range.
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000342
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000343 SlotIndex defIndex = MIIdx.getRegSlot();
Evan Chengfb112882009-03-23 08:01:15 +0000344 if (MO.isEarlyClobber())
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000345 defIndex = MIIdx.getRegSlot(true);
Evan Cheng752195e2009-09-14 21:33:42 +0000346
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000347 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000348
Lang Hames74ab5ee2009-12-22 00:11:50 +0000349 SlotIndex killIndex = getMBBEndIdx(mbb);
Evan Cheng7ecb38b2007-08-29 20:45:00 +0000350 LiveRange LR(defIndex, killIndex, ValNo);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000351 interval.addRange(LR);
Lang Hames857c4e02009-06-17 21:01:20 +0000352 ValNo->setHasPHIKill(true);
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000353 DEBUG(dbgs() << " phi-join +" << LR);
Evan Cheng37499432010-05-05 18:27:40 +0000354 } else {
355 llvm_unreachable("Multiply defined register");
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000356 }
357 }
358
David Greene8a342292010-01-04 22:49:02 +0000359 DEBUG(dbgs() << '\n');
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000360}
361
Lang Hamesaf8b34d2012-02-17 00:18:18 +0000362static bool isRegLiveIntoSuccessor(const MachineBasicBlock *MBB, unsigned Reg) {
Lang Hames342c64c2012-02-14 18:51:53 +0000363 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
364 SE = MBB->succ_end();
365 SI != SE; ++SI) {
366 const MachineBasicBlock* succ = *SI;
367 if (succ->isLiveIn(Reg))
368 return true;
369 }
370 return false;
371}
Lang Hames342c64c2012-02-14 18:51:53 +0000372
Chris Lattnerf35fef72004-07-23 21:24:19 +0000373void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000374 MachineBasicBlock::iterator mi,
Lang Hames233a60e2009-11-03 23:52:08 +0000375 SlotIndex MIIdx,
Owen Anderson6b098de2008-06-25 23:39:39 +0000376 MachineOperand& MO,
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000377 LiveInterval &interval) {
Jakob Stoklund Olesen43142682011-01-09 03:05:53 +0000378 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
Alkis Evlogimenos02ba13c2004-01-31 23:13:30 +0000379
Lang Hames233a60e2009-11-03 23:52:08 +0000380 SlotIndex baseIndex = MIIdx;
Jakob Stoklund Olesend14614e2011-11-13 22:05:42 +0000381 SlotIndex start = baseIndex.getRegSlot(MO.isEarlyClobber());
Lang Hames233a60e2009-11-03 23:52:08 +0000382 SlotIndex end = start;
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000383
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000384 // If it is not used after definition, it is considered dead at
385 // the instruction defining it. Hence its interval is:
386 // [defSlot(def), defSlot(def)+1)
Dale Johannesen39faac22009-09-20 00:36:41 +0000387 // For earlyclobbers, the defSlot was pushed back one; the extra
388 // advance below compensates.
Owen Anderson6b098de2008-06-25 23:39:39 +0000389 if (MO.isDead()) {
David Greene8a342292010-01-04 22:49:02 +0000390 DEBUG(dbgs() << " dead");
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000391 end = start.getDeadSlot();
Chris Lattnerab4b66d2005-08-23 22:51:41 +0000392 goto exit;
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000393 }
394
395 // If it is not dead on definition, it must be killed by a
396 // subsequent instruction. Hence its interval is:
397 // [defSlot(def), useSlot(kill)+1)
Lang Hames233a60e2009-11-03 23:52:08 +0000398 baseIndex = baseIndex.getNextIndex();
Chris Lattner5ab6f5f2005-09-02 00:20:32 +0000399 while (++mi != MBB->end()) {
Lang Hames233a60e2009-11-03 23:52:08 +0000400
Dale Johannesenbd635202010-02-10 00:55:42 +0000401 if (mi->isDebugValue())
402 continue;
Lang Hames233a60e2009-11-03 23:52:08 +0000403 if (getInstructionFromIndex(baseIndex) == 0)
404 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
405
Evan Cheng6130f662008-03-05 00:59:57 +0000406 if (mi->killsRegister(interval.reg, tri_)) {
David Greene8a342292010-01-04 22:49:02 +0000407 DEBUG(dbgs() << " killed");
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000408 end = baseIndex.getRegSlot();
Chris Lattnerab4b66d2005-08-23 22:51:41 +0000409 goto exit;
Evan Chengc45288e2009-04-27 20:42:46 +0000410 } else {
Evan Cheng1015ba72010-05-21 20:53:24 +0000411 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_);
Evan Chengc45288e2009-04-27 20:42:46 +0000412 if (DefIdx != -1) {
413 if (mi->isRegTiedToUseOperand(DefIdx)) {
414 // Two-address instruction.
Jakob Stoklund Olesen7e899cb2012-02-04 05:41:20 +0000415 end = baseIndex.getRegSlot(mi->getOperand(DefIdx).isEarlyClobber());
Evan Chengc45288e2009-04-27 20:42:46 +0000416 } else {
417 // Another instruction redefines the register before it is ever read.
Dale Johannesenbd635202010-02-10 00:55:42 +0000418 // Then the register is essentially dead at the instruction that
419 // defines it. Hence its interval is:
Evan Chengc45288e2009-04-27 20:42:46 +0000420 // [defSlot(def), defSlot(def)+1)
David Greene8a342292010-01-04 22:49:02 +0000421 DEBUG(dbgs() << " dead");
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000422 end = start.getDeadSlot();
Evan Chengc45288e2009-04-27 20:42:46 +0000423 }
424 goto exit;
425 }
Alkis Evlogimenosaf254732004-01-13 22:26:14 +0000426 }
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000427
Lang Hames233a60e2009-11-03 23:52:08 +0000428 baseIndex = baseIndex.getNextIndex();
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000429 }
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000430
Lang Hames342c64c2012-02-14 18:51:53 +0000431 // If we get here the register *should* be live out.
432 assert(!isAllocatable(interval.reg) && "Physregs shouldn't be live out!");
Alkis Evlogimenos02ba13c2004-01-31 23:13:30 +0000433
Lang Hames342c64c2012-02-14 18:51:53 +0000434 // FIXME: We need saner rules for reserved regs.
435 if (isReserved(interval.reg)) {
Lang Hames342c64c2012-02-14 18:51:53 +0000436 end = start.getDeadSlot();
437 } else {
438 // Unreserved, unallocable registers like EFLAGS can be live across basic
439 // block boundaries.
Lang Hamesaf8b34d2012-02-17 00:18:18 +0000440 assert(isRegLiveIntoSuccessor(MBB, interval.reg) &&
441 "Unreserved reg not live-out?");
Lang Hames342c64c2012-02-14 18:51:53 +0000442 end = getMBBEndIdx(MBB);
443 }
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000444exit:
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000445 assert(start < end && "did not find end of interval?");
Chris Lattnerf768bba2005-03-09 23:05:19 +0000446
Evan Cheng24a3cc42007-04-25 07:30:23 +0000447 // Already exists? Extend old live interval.
Jakob Stoklund Olesen31cc3ec2010-10-11 21:45:03 +0000448 VNInfo *ValNo = interval.getVNInfoAt(start);
449 bool Extend = ValNo != 0;
450 if (!Extend)
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000451 ValNo = interval.getNextValue(start, VNInfoAllocator);
Evan Cheng7ecb38b2007-08-29 20:45:00 +0000452 LiveRange LR(start, end, ValNo);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000453 interval.addRange(LR);
David Greene8a342292010-01-04 22:49:02 +0000454 DEBUG(dbgs() << " +" << LR << '\n');
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000455}
456
Chris Lattnerf35fef72004-07-23 21:24:19 +0000457void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
458 MachineBasicBlock::iterator MI,
Lang Hames233a60e2009-11-03 23:52:08 +0000459 SlotIndex MIIdx,
Evan Chengef0732d2008-07-10 07:35:43 +0000460 MachineOperand& MO,
461 unsigned MOIdx) {
Owen Anderson6b098de2008-06-25 23:39:39 +0000462 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
Evan Chengef0732d2008-07-10 07:35:43 +0000463 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
Owen Anderson6b098de2008-06-25 23:39:39 +0000464 getOrCreateInterval(MO.getReg()));
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000465 else
Evan Chengc45288e2009-04-27 20:42:46 +0000466 handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000467 getOrCreateInterval(MO.getReg()));
Alkis Evlogimenos4d46e1e2004-01-31 14:37:41 +0000468}
469
Evan Chengb371f452007-02-19 21:49:54 +0000470void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
Lang Hames233a60e2009-11-03 23:52:08 +0000471 SlotIndex MIIdx,
Lang Hames4465b6f2012-02-10 03:19:36 +0000472 LiveInterval &interval) {
Lang Hames342c64c2012-02-14 18:51:53 +0000473 assert(TargetRegisterInfo::isPhysicalRegister(interval.reg) &&
474 "Only physical registers can be live in.");
475 assert((!isAllocatable(interval.reg) || MBB->getParent()->begin() ||
476 MBB->isLandingPad()) &&
477 "Allocatable live-ins only valid for entry blocks and landing pads.");
478
Jakob Stoklund Olesen43142682011-01-09 03:05:53 +0000479 DEBUG(dbgs() << "\t\tlivein register: " << PrintReg(interval.reg, tri_));
Evan Chengb371f452007-02-19 21:49:54 +0000480
481 // Look for kills, if it reaches a def before it's killed, then it shouldn't
482 // be considered a livein.
483 MachineBasicBlock::iterator mi = MBB->begin();
Evan Cheng4507f082010-03-16 21:51:27 +0000484 MachineBasicBlock::iterator E = MBB->end();
485 // Skip over DBG_VALUE at the start of the MBB.
486 if (mi != E && mi->isDebugValue()) {
487 while (++mi != E && mi->isDebugValue())
488 ;
489 if (mi == E)
490 // MBB is empty except for DBG_VALUE's.
491 return;
492 }
493
Lang Hames233a60e2009-11-03 23:52:08 +0000494 SlotIndex baseIndex = MIIdx;
495 SlotIndex start = baseIndex;
496 if (getInstructionFromIndex(baseIndex) == 0)
497 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
498
499 SlotIndex end = baseIndex;
Evan Cheng0076c612009-03-05 03:34:26 +0000500 bool SeenDefUse = false;
Evan Chengb371f452007-02-19 21:49:54 +0000501
Dale Johannesenbd635202010-02-10 00:55:42 +0000502 while (mi != E) {
Dale Johannesen1d0aeab2010-02-10 01:31:26 +0000503 if (mi->killsRegister(interval.reg, tri_)) {
504 DEBUG(dbgs() << " killed");
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000505 end = baseIndex.getRegSlot();
Dale Johannesen1d0aeab2010-02-10 01:31:26 +0000506 SeenDefUse = true;
507 break;
Jakob Stoklund Olesen6b791382012-02-14 23:46:24 +0000508 } else if (mi->modifiesRegister(interval.reg, tri_)) {
Dale Johannesen1d0aeab2010-02-10 01:31:26 +0000509 // Another instruction redefines the register before it is ever read.
510 // Then the register is essentially dead at the instruction that defines
511 // it. Hence its interval is:
512 // [defSlot(def), defSlot(def)+1)
513 DEBUG(dbgs() << " dead");
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000514 end = start.getDeadSlot();
Dale Johannesen1d0aeab2010-02-10 01:31:26 +0000515 SeenDefUse = true;
516 break;
517 }
518
Evan Cheng4507f082010-03-16 21:51:27 +0000519 while (++mi != E && mi->isDebugValue())
520 // Skip over DBG_VALUE.
521 ;
522 if (mi != E)
Lang Hames233a60e2009-11-03 23:52:08 +0000523 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
Evan Chengb371f452007-02-19 21:49:54 +0000524 }
525
Evan Cheng75611fb2007-06-27 01:16:36 +0000526 // Live-in register might not be used at all.
Evan Cheng0076c612009-03-05 03:34:26 +0000527 if (!SeenDefUse) {
Lang Hamesaf8b34d2012-02-17 00:18:18 +0000528 if (isAllocatable(interval.reg) ||
529 !isRegLiveIntoSuccessor(MBB, interval.reg)) {
530 // Allocatable registers are never live through.
531 // Non-allocatable registers that aren't live into any successors also
532 // aren't live through.
Lang Hames342c64c2012-02-14 18:51:53 +0000533 DEBUG(dbgs() << " dead");
Lang Hamesf58e37f2012-02-15 01:31:10 +0000534 return;
Lang Hames342c64c2012-02-14 18:51:53 +0000535 } else {
Lang Hamesaf8b34d2012-02-17 00:18:18 +0000536 // If we get here the register is non-allocatable and live into some
537 // successor. We'll conservatively assume it's live-through.
Lang Hames342c64c2012-02-14 18:51:53 +0000538 DEBUG(dbgs() << " live through");
539 end = getMBBEndIdx(MBB);
540 }
Evan Cheng24a3cc42007-04-25 07:30:23 +0000541 }
542
Lang Hames6e2968c2010-09-25 12:04:16 +0000543 SlotIndex defIdx = getMBBStartIdx(MBB);
544 assert(getInstructionFromIndex(defIdx) == 0 &&
545 "PHI def index points at actual instruction.");
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000546 VNInfo *vni = interval.getNextValue(defIdx, VNInfoAllocator);
Lang Hamesd21c3162009-06-18 22:01:47 +0000547 vni->setIsPHIDef(true);
548 LiveRange LR(start, end, vni);
Jakob Stoklund Olesen3de23e62009-11-07 01:58:40 +0000549
Jim Laskey9b25b8c2007-02-21 22:41:17 +0000550 interval.addRange(LR);
David Greene8a342292010-01-04 22:49:02 +0000551 DEBUG(dbgs() << " +" << LR << '\n');
Evan Chengb371f452007-02-19 21:49:54 +0000552}
553
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000554/// computeIntervals - computes the live intervals for virtual
Alkis Evlogimenos4d46e1e2004-01-31 14:37:41 +0000555/// registers. for some ordering of the machine instructions [1,N] a
Alkis Evlogimenos08cec002004-01-31 19:59:32 +0000556/// live interval is an interval [i, j) where 1 <= i <= j < N for
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000557/// which a variable is live
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000558void LiveIntervals::computeIntervals() {
David Greene8a342292010-01-04 22:49:02 +0000559 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
Bill Wendling8e6179f2009-08-22 20:18:03 +0000560 << "********** Function: "
561 << ((Value*)mf_->getFunction())->getName() << '\n');
Evan Chengd129d732009-07-17 19:43:40 +0000562
Jakob Stoklund Olesen34e85d02012-02-10 01:26:29 +0000563 RegMaskBlocks.resize(mf_->getNumBlockIDs());
564
Evan Chengd129d732009-07-17 19:43:40 +0000565 SmallVector<unsigned, 8> UndefUses;
Chris Lattner428b92e2006-09-15 03:57:23 +0000566 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
567 MBBI != E; ++MBBI) {
568 MachineBasicBlock *MBB = MBBI;
Jakob Stoklund Olesen34e85d02012-02-10 01:26:29 +0000569 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
570
Evan Cheng00a99a32010-02-06 09:07:11 +0000571 if (MBB->empty())
572 continue;
573
Owen Anderson134eb732008-09-21 20:43:24 +0000574 // Track the index of the current machine instr.
Lang Hames233a60e2009-11-03 23:52:08 +0000575 SlotIndex MIIndex = getMBBStartIdx(MBB);
Bob Wilsonad98f792010-05-03 21:38:11 +0000576 DEBUG(dbgs() << "BB#" << MBB->getNumber()
577 << ":\t\t# derived from " << MBB->getName() << "\n");
Alkis Evlogimenos6b4edba2003-12-21 20:19:10 +0000578
Dan Gohmancb406c22007-10-03 19:26:29 +0000579 // Create intervals for live-ins to this BB first.
Dan Gohman81bf03e2010-04-13 16:57:55 +0000580 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
Dan Gohmancb406c22007-10-03 19:26:29 +0000581 LE = MBB->livein_end(); LI != LE; ++LI) {
582 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
Chris Lattnerdffb2e82006-09-04 18:27:40 +0000583 }
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000584
Owen Anderson99500ae2008-09-15 22:00:38 +0000585 // Skip over empty initial indices.
Lang Hames233a60e2009-11-03 23:52:08 +0000586 if (getInstructionFromIndex(MIIndex) == 0)
587 MIIndex = indexes_->getNextNonNullIndex(MIIndex);
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000588
Dale Johannesen1caedd02010-01-22 22:38:21 +0000589 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
590 MI != miEnd; ++MI) {
David Greene8a342292010-01-04 22:49:02 +0000591 DEBUG(dbgs() << MIIndex << "\t" << *MI);
Chris Lattner518bb532010-02-09 19:54:29 +0000592 if (MI->isDebugValue())
Dale Johannesen1caedd02010-01-22 22:38:21 +0000593 continue;
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +0000594 assert(indexes_->getInstructionFromIndex(MIIndex) == MI &&
595 "Lost SlotIndex synchronization");
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000596
Evan Cheng438f7bc2006-11-10 08:43:01 +0000597 // Handle defs.
Chris Lattner428b92e2006-09-15 03:57:23 +0000598 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
599 MachineOperand &MO = MI->getOperand(i);
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +0000600
601 // Collect register masks.
602 if (MO.isRegMask()) {
603 RegMaskSlots.push_back(MIIndex.getRegSlot());
604 RegMaskBits.push_back(MO.getRegMask());
605 continue;
606 }
607
Evan Chengd129d732009-07-17 19:43:40 +0000608 if (!MO.isReg() || !MO.getReg())
609 continue;
610
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000611 // handle register defs - build intervals
Evan Chengd129d732009-07-17 19:43:40 +0000612 if (MO.isDef())
Evan Chengef0732d2008-07-10 07:35:43 +0000613 handleRegisterDef(MBB, MI, MIIndex, MO, i);
Evan Chengd129d732009-07-17 19:43:40 +0000614 else if (MO.isUndef())
615 UndefUses.push_back(MO.getReg());
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000616 }
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000617
Lang Hames233a60e2009-11-03 23:52:08 +0000618 // Move to the next instr slot.
619 MIIndex = indexes_->getNextNonNullIndex(MIIndex);
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000620 }
Jakob Stoklund Olesen34e85d02012-02-10 01:26:29 +0000621
622 // Compute the number of register mask instructions in this block.
623 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
624 RMB.second = RegMaskSlots.size() - RMB.first;;
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000625 }
Evan Chengd129d732009-07-17 19:43:40 +0000626
627 // Create empty intervals for registers defined by implicit_def's (except
628 // for those implicit_def that define values which are liveout of their
629 // blocks.
630 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
631 unsigned UndefReg = UndefUses[i];
632 (void)getOrCreateInterval(UndefReg);
633 }
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000634}
Alkis Evlogimenosb27ef242003-12-05 10:38:28 +0000635
Owen Anderson03857b22008-08-13 21:49:13 +0000636LiveInterval* LiveIntervals::createInterval(unsigned reg) {
Evan Cheng0a1fcce2009-02-08 11:04:35 +0000637 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
Owen Anderson03857b22008-08-13 21:49:13 +0000638 return new LiveInterval(reg, Weight);
Alkis Evlogimenos9a8b4902004-04-09 18:07:57 +0000639}
Evan Chengf2fbca62007-11-12 06:35:08 +0000640
Evan Cheng0a1fcce2009-02-08 11:04:35 +0000641/// dupInterval - Duplicate a live interval. The caller is responsible for
642/// managing the allocated memory.
643LiveInterval* LiveIntervals::dupInterval(LiveInterval *li) {
644 LiveInterval *NewLI = createInterval(li->reg);
Evan Cheng90f95f82009-06-14 20:22:55 +0000645 NewLI->Copy(*li, mri_, getVNInfoAllocator());
Evan Cheng0a1fcce2009-02-08 11:04:35 +0000646 return NewLI;
647}
648
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000649/// shrinkToUses - After removing some uses of a register, shrink its live
650/// range to just the remaining uses. This method does not compute reaching
651/// defs for new uses, and it doesn't remove dead defs.
Jakob Stoklund Olesen6a3dbd32011-03-17 20:37:07 +0000652bool LiveIntervals::shrinkToUses(LiveInterval *li,
Jakob Stoklund Olesen0d8ccaa2011-03-07 23:29:10 +0000653 SmallVectorImpl<MachineInstr*> *dead) {
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000654 DEBUG(dbgs() << "Shrink: " << *li << '\n');
655 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
Lang Hames567cdba2012-01-03 20:05:57 +0000656 && "Can only shrink virtual registers");
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000657 // Find all the values used, including PHI kills.
658 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
659
Jakob Stoklund Olesen031432f2011-09-15 15:24:16 +0000660 // Blocks that have already been added to WorkList as live-out.
661 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
662
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000663 // Visit all instructions reading li->reg.
664 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(li->reg);
665 MachineInstr *UseMI = I.skipInstruction();) {
666 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
667 continue;
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000668 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
Jakob Stoklund Olesenf054e192011-11-14 18:45:38 +0000669 // Note: This intentionally picks up the wrong VNI in case of an EC redef.
670 // See below.
671 VNInfo *VNI = li->getVNInfoBefore(Idx);
Jakob Stoklund Olesen9ef931e2011-03-18 03:06:04 +0000672 if (!VNI) {
673 // This shouldn't happen: readsVirtualRegister returns true, but there is
674 // no live value. It is likely caused by a target getting <undef> flags
675 // wrong.
676 DEBUG(dbgs() << Idx << '\t' << *UseMI
677 << "Warning: Instr claims to read non-existent value in "
678 << *li << '\n');
679 continue;
680 }
Jakob Stoklund Olesenf054e192011-11-14 18:45:38 +0000681 // Special case: An early-clobber tied operand reads and writes the
682 // register one slot early. The getVNInfoBefore call above would have
683 // picked up the value defined by UseMI. Adjust the kill slot and value.
684 if (SlotIndex::isSameInstr(VNI->def, Idx)) {
685 Idx = VNI->def;
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000686 VNI = li->getVNInfoBefore(Idx);
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000687 assert(VNI && "Early-clobber tied value not available");
688 }
689 WorkList.push_back(std::make_pair(Idx, VNI));
690 }
691
692 // Create a new live interval with only minimal live segments per def.
693 LiveInterval NewLI(li->reg, 0);
694 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
695 I != E; ++I) {
696 VNInfo *VNI = *I;
697 if (VNI->isUnused())
698 continue;
Jakob Stoklund Olesen1f81e312011-11-13 22:42:13 +0000699 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000700 }
701
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000702 // Keep track of the PHIs that are in use.
703 SmallPtrSet<VNInfo*, 8> UsedPHIs;
704
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000705 // Extend intervals to reach all uses in WorkList.
706 while (!WorkList.empty()) {
707 SlotIndex Idx = WorkList.back().first;
708 VNInfo *VNI = WorkList.back().second;
709 WorkList.pop_back();
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000710 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000711 SlotIndex BlockStart = getMBBStartIdx(MBB);
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000712
713 // Extend the live range for VNI to be live at Idx.
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000714 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
Nick Lewycky4b11a702011-03-02 01:43:30 +0000715 (void)ExtVNI;
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000716 assert(ExtVNI == VNI && "Unexpected existing value number");
717 // Is this a PHIDef we haven't seen before?
Jakob Stoklund Olesenc29d9b32011-03-03 00:20:51 +0000718 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000719 continue;
720 // The PHI is live, make sure the predecessors are live-out.
721 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
722 PE = MBB->pred_end(); PI != PE; ++PI) {
Jakob Stoklund Olesen031432f2011-09-15 15:24:16 +0000723 if (!LiveOut.insert(*PI))
724 continue;
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000725 SlotIndex Stop = getMBBEndIdx(*PI);
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000726 // A predecessor is not required to have a live-out value for a PHI.
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000727 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000728 WorkList.push_back(std::make_pair(Stop, PVNI));
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000729 }
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000730 continue;
731 }
732
733 // VNI is live-in to MBB.
734 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000735 NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000736
737 // Make sure VNI is live-out from the predecessors.
738 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
739 PE = MBB->pred_end(); PI != PE; ++PI) {
Jakob Stoklund Olesen031432f2011-09-15 15:24:16 +0000740 if (!LiveOut.insert(*PI))
741 continue;
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000742 SlotIndex Stop = getMBBEndIdx(*PI);
743 assert(li->getVNInfoBefore(Stop) == VNI &&
744 "Wrong value out of predecessor");
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000745 WorkList.push_back(std::make_pair(Stop, VNI));
746 }
747 }
748
749 // Handle dead values.
Jakob Stoklund Olesen6a3dbd32011-03-17 20:37:07 +0000750 bool CanSeparate = false;
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000751 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
752 I != E; ++I) {
753 VNInfo *VNI = *I;
754 if (VNI->isUnused())
755 continue;
756 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
757 assert(LII != NewLI.end() && "Missing live range for PHI");
Jakob Stoklund Olesen1f81e312011-11-13 22:42:13 +0000758 if (LII->end != VNI->def.getDeadSlot())
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000759 continue;
Jakob Stoklund Olesena4d34732011-03-02 00:33:01 +0000760 if (VNI->isPHIDef()) {
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000761 // This is a dead PHI. Remove it.
762 VNI->setIsUnused(true);
763 NewLI.removeRange(*LII);
Jakob Stoklund Olesen6a3dbd32011-03-17 20:37:07 +0000764 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
765 CanSeparate = true;
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000766 } else {
767 // This is a dead def. Make sure the instruction knows.
768 MachineInstr *MI = getInstructionFromIndex(VNI->def);
769 assert(MI && "No instruction defining live value");
770 MI->addRegisterDead(li->reg, tri_);
Jakob Stoklund Olesen0d8ccaa2011-03-07 23:29:10 +0000771 if (dead && MI->allDefsAreDead()) {
Jakob Stoklund Olesenc46570d2011-03-16 22:56:08 +0000772 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
Jakob Stoklund Olesen0d8ccaa2011-03-07 23:29:10 +0000773 dead->push_back(MI);
774 }
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000775 }
776 }
777
778 // Move the trimmed ranges back.
779 li->ranges.swap(NewLI.ranges);
Jakob Stoklund Olesenc46570d2011-03-16 22:56:08 +0000780 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
Jakob Stoklund Olesen6a3dbd32011-03-17 20:37:07 +0000781 return CanSeparate;
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000782}
783
784
Evan Chengf2fbca62007-11-12 06:35:08 +0000785//===----------------------------------------------------------------------===//
786// Register allocator hooks.
787//
788
Jakob Stoklund Olesen8a61da82011-02-08 21:13:03 +0000789void LiveIntervals::addKillFlags() {
790 for (iterator I = begin(), E = end(); I != E; ++I) {
791 unsigned Reg = I->first;
792 if (TargetRegisterInfo::isPhysicalRegister(Reg))
793 continue;
794 if (mri_->reg_nodbg_empty(Reg))
795 continue;
796 LiveInterval *LI = I->second;
797
798 // Every instruction that kills Reg corresponds to a live range end point.
799 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
800 ++RI) {
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000801 // A block index indicates an MBB edge.
802 if (RI->end.isBlock())
Jakob Stoklund Olesen8a61da82011-02-08 21:13:03 +0000803 continue;
804 MachineInstr *MI = getInstructionFromIndex(RI->end);
805 if (!MI)
806 continue;
807 MI->addRegisterKilled(Reg, NULL);
808 }
809 }
810}
811
Evan Chengd70dbb52008-02-22 09:24:50 +0000812/// getReMatImplicitUse - If the remat definition MI has one (for now, we only
813/// allow one) virtual register operand, then its uses are implicitly using
814/// the register. Returns the virtual register.
815unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li,
816 MachineInstr *MI) const {
817 unsigned RegOp = 0;
818 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
819 MachineOperand &MO = MI->getOperand(i);
Dan Gohmand735b802008-10-03 15:45:36 +0000820 if (!MO.isReg() || !MO.isUse())
Evan Chengd70dbb52008-02-22 09:24:50 +0000821 continue;
822 unsigned Reg = MO.getReg();
823 if (Reg == 0 || Reg == li.reg)
824 continue;
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000825
Lang Hamescd339b72012-02-14 03:04:29 +0000826 if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isAllocatable(Reg))
Chris Lattner1873d0c2009-06-27 04:06:41 +0000827 continue;
Evan Chengd70dbb52008-02-22 09:24:50 +0000828 RegOp = MO.getReg();
Lang Hames6c76e802012-01-25 21:53:23 +0000829 break; // Found vreg operand - leave the loop.
Evan Chengd70dbb52008-02-22 09:24:50 +0000830 }
831 return RegOp;
832}
833
834/// isValNoAvailableAt - Return true if the val# of the specified interval
835/// which reaches the given instruction also reaches the specified use index.
836bool LiveIntervals::isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
Lang Hames233a60e2009-11-03 23:52:08 +0000837 SlotIndex UseIdx) const {
Jakob Stoklund Olesen31cc3ec2010-10-11 21:45:03 +0000838 VNInfo *UValNo = li.getVNInfoAt(UseIdx);
839 return UValNo && UValNo == li.getVNInfoAt(getInstructionIndex(MI));
Evan Chengd70dbb52008-02-22 09:24:50 +0000840}
841
Evan Chengf2fbca62007-11-12 06:35:08 +0000842/// isReMaterializable - Returns true if the definition MI of the specified
843/// val# of the specified interval is re-materializable.
Andrew Trickf4baeaf2010-11-10 19:18:47 +0000844bool
845LiveIntervals::isReMaterializable(const LiveInterval &li,
846 const VNInfo *ValNo, MachineInstr *MI,
Jakob Stoklund Olesen38f6bd02011-03-10 01:21:58 +0000847 const SmallVectorImpl<LiveInterval*> *SpillIs,
Andrew Trickf4baeaf2010-11-10 19:18:47 +0000848 bool &isLoad) {
Evan Chengf2fbca62007-11-12 06:35:08 +0000849 if (DisableReMat)
850 return false;
851
Dan Gohmana70dca12009-10-09 23:27:56 +0000852 if (!tii_->isTriviallyReMaterializable(MI, aa_))
853 return false;
Evan Chengdd3465e2008-02-23 01:44:27 +0000854
Dan Gohmana70dca12009-10-09 23:27:56 +0000855 // Target-specific code can mark an instruction as being rematerializable
856 // if it has one virtual reg use, though it had better be something like
857 // a PIC base register which is likely to be live everywhere.
Dan Gohman6d69ba82008-07-25 00:02:30 +0000858 unsigned ImpUse = getReMatImplicitUse(li, MI);
859 if (ImpUse) {
860 const LiveInterval &ImpLi = getInterval(ImpUse);
Evan Cheng28a1e482010-03-30 05:49:07 +0000861 for (MachineRegisterInfo::use_nodbg_iterator
862 ri = mri_->use_nodbg_begin(li.reg), re = mri_->use_nodbg_end();
863 ri != re; ++ri) {
Dan Gohman6d69ba82008-07-25 00:02:30 +0000864 MachineInstr *UseMI = &*ri;
Lang Hames233a60e2009-11-03 23:52:08 +0000865 SlotIndex UseIdx = getInstructionIndex(UseMI);
Jakob Stoklund Olesen31cc3ec2010-10-11 21:45:03 +0000866 if (li.getVNInfoAt(UseIdx) != ValNo)
Dan Gohman6d69ba82008-07-25 00:02:30 +0000867 continue;
868 if (!isValNoAvailableAt(ImpLi, MI, UseIdx))
869 return false;
870 }
Evan Chengdc377862008-09-30 15:44:16 +0000871
872 // If a register operand of the re-materialized instruction is going to
873 // be spilled next, then it's not legal to re-materialize this instruction.
Jakob Stoklund Olesen38f6bd02011-03-10 01:21:58 +0000874 if (SpillIs)
875 for (unsigned i = 0, e = SpillIs->size(); i != e; ++i)
876 if (ImpUse == (*SpillIs)[i]->reg)
877 return false;
Dan Gohman6d69ba82008-07-25 00:02:30 +0000878 }
879 return true;
Evan Cheng5ef3a042007-12-06 00:01:56 +0000880}
881
882/// isReMaterializable - Returns true if every definition of MI of every
883/// val# of the specified interval is re-materializable.
Andrew Trickf4baeaf2010-11-10 19:18:47 +0000884bool
885LiveIntervals::isReMaterializable(const LiveInterval &li,
Jakob Stoklund Olesen38f6bd02011-03-10 01:21:58 +0000886 const SmallVectorImpl<LiveInterval*> *SpillIs,
Andrew Trickf4baeaf2010-11-10 19:18:47 +0000887 bool &isLoad) {
Evan Cheng5ef3a042007-12-06 00:01:56 +0000888 isLoad = false;
889 for (LiveInterval::const_vni_iterator i = li.vni_begin(), e = li.vni_end();
890 i != e; ++i) {
891 const VNInfo *VNI = *i;
Lang Hames857c4e02009-06-17 21:01:20 +0000892 if (VNI->isUnused())
Evan Cheng5ef3a042007-12-06 00:01:56 +0000893 continue; // Dead val#.
894 // Is the def for the val# rematerializable?
Lang Hames857c4e02009-06-17 21:01:20 +0000895 MachineInstr *ReMatDefMI = getInstructionFromIndex(VNI->def);
Lang Hames6e2968c2010-09-25 12:04:16 +0000896 if (!ReMatDefMI)
897 return false;
Evan Cheng5ef3a042007-12-06 00:01:56 +0000898 bool DefIsLoad = false;
Evan Chengd70dbb52008-02-22 09:24:50 +0000899 if (!ReMatDefMI ||
Evan Chengdc377862008-09-30 15:44:16 +0000900 !isReMaterializable(li, VNI, ReMatDefMI, SpillIs, DefIsLoad))
Evan Cheng5ef3a042007-12-06 00:01:56 +0000901 return false;
902 isLoad |= DefIsLoad;
Evan Chengf2fbca62007-11-12 06:35:08 +0000903 }
904 return true;
905}
906
Jakob Stoklund Olesenebf27502012-02-10 01:23:55 +0000907MachineBasicBlock*
908LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
909 // A local live range must be fully contained inside the block, meaning it is
910 // defined and killed at instructions, not at block boundaries. It is not
911 // live in or or out of any block.
912 //
913 // It is technically possible to have a PHI-defined live range identical to a
914 // single block, but we are going to return false in that case.
Lang Hames233a60e2009-11-03 23:52:08 +0000915
Jakob Stoklund Olesenebf27502012-02-10 01:23:55 +0000916 SlotIndex Start = LI.beginIndex();
917 if (Start.isBlock())
918 return NULL;
Lang Hames233a60e2009-11-03 23:52:08 +0000919
Jakob Stoklund Olesenebf27502012-02-10 01:23:55 +0000920 SlotIndex Stop = LI.endIndex();
921 if (Stop.isBlock())
922 return NULL;
Lang Hames233a60e2009-11-03 23:52:08 +0000923
Jakob Stoklund Olesenebf27502012-02-10 01:23:55 +0000924 // getMBBFromIndex doesn't need to search the MBB table when both indexes
925 // belong to proper instructions.
926 MachineBasicBlock *MBB1 = indexes_->getMBBFromIndex(Start);
927 MachineBasicBlock *MBB2 = indexes_->getMBBFromIndex(Stop);
928 return MBB1 == MBB2 ? MBB1 : NULL;
Evan Cheng81a03822007-11-17 00:40:40 +0000929}
930
Jakob Stoklund Olesene5d90412010-03-01 20:59:38 +0000931float
932LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
933 // Limit the loop depth ridiculousness.
934 if (loopDepth > 200)
935 loopDepth = 200;
936
937 // The loop depth is used to roughly estimate the number of times the
938 // instruction is executed. Something like 10^d is simple, but will quickly
939 // overflow a float. This expression behaves like 10^d for small d, but is
940 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
941 // headroom before overflow.
NAKAMURA Takumidc5198b2011-03-31 12:11:33 +0000942 // By the way, powf() might be unavailable here. For consistency,
943 // We may take pow(double,double).
944 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
Jakob Stoklund Olesene5d90412010-03-01 20:59:38 +0000945
946 return (isDef + isUse) * lc;
947}
948
Owen Andersonc4dc1322008-06-05 17:15:43 +0000949LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
Lang Hamesffd13262009-07-09 03:57:02 +0000950 MachineInstr* startInst) {
Owen Andersonc4dc1322008-06-05 17:15:43 +0000951 LiveInterval& Interval = getOrCreateInterval(reg);
952 VNInfo* VN = Interval.getNextValue(
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000953 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000954 getVNInfoAllocator());
Lang Hames857c4e02009-06-17 21:01:20 +0000955 VN->setHasPHIKill(true);
Lang Hames86511252009-09-04 20:41:11 +0000956 LiveRange LR(
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000957 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
Lang Hames74ab5ee2009-12-22 00:11:50 +0000958 getMBBEndIdx(startInst->getParent()), VN);
Owen Andersonc4dc1322008-06-05 17:15:43 +0000959 Interval.addRange(LR);
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000960
Owen Andersonc4dc1322008-06-05 17:15:43 +0000961 return LR;
962}
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +0000963
964
965//===----------------------------------------------------------------------===//
966// Register mask functions
967//===----------------------------------------------------------------------===//
968
969bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
970 BitVector &UsableRegs) {
971 if (LI.empty())
972 return false;
Jakob Stoklund Olesen9f10ac62012-02-10 01:31:31 +0000973 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
974
975 // Use a smaller arrays for local live ranges.
976 ArrayRef<SlotIndex> Slots;
977 ArrayRef<const uint32_t*> Bits;
978 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
979 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
980 Bits = getRegMaskBitsInBlock(MBB->getNumber());
981 } else {
982 Slots = getRegMaskSlots();
983 Bits = getRegMaskBits();
984 }
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +0000985
986 // We are going to enumerate all the register mask slots contained in LI.
987 // Start with a binary search of RegMaskSlots to find a starting point.
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +0000988 ArrayRef<SlotIndex>::iterator SlotI =
989 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
990 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
991
992 // No slots in range, LI begins after the last call.
993 if (SlotI == SlotE)
994 return false;
995
996 bool Found = false;
997 for (;;) {
998 assert(*SlotI >= LiveI->start);
999 // Loop over all slots overlapping this segment.
1000 while (*SlotI < LiveI->end) {
1001 // *SlotI overlaps LI. Collect mask bits.
1002 if (!Found) {
1003 // This is the first overlap. Initialize UsableRegs to all ones.
1004 UsableRegs.clear();
1005 UsableRegs.resize(tri_->getNumRegs(), true);
1006 Found = true;
1007 }
1008 // Remove usable registers clobbered by this mask.
Jakob Stoklund Olesen9f10ac62012-02-10 01:31:31 +00001009 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +00001010 if (++SlotI == SlotE)
1011 return Found;
1012 }
1013 // *SlotI is beyond the current LI segment.
1014 LiveI = LI.advanceTo(LiveI, *SlotI);
1015 if (LiveI == LiveE)
1016 return Found;
1017 // Advance SlotI until it overlaps.
1018 while (*SlotI < LiveI->start)
1019 if (++SlotI == SlotE)
1020 return Found;
1021 }
1022}
Lang Hames3dc7c512012-02-17 18:44:18 +00001023
1024//===----------------------------------------------------------------------===//
1025// IntervalUpdate class.
1026//===----------------------------------------------------------------------===//
1027
1028/// HMEditor is a toolkit used by handleMove to trim or extend live intervals.
1029class LiveIntervals::HMEditor {
1030private:
Lang Hamesecb50622012-02-17 23:43:40 +00001031 LiveIntervals& LIS;
1032 const MachineRegisterInfo& MRI;
1033 const TargetRegisterInfo& TRI;
1034 SlotIndex NewIdx;
Lang Hames3dc7c512012-02-17 18:44:18 +00001035
Lang Hames55fed622012-02-19 03:00:30 +00001036 typedef std::pair<LiveInterval*, LiveRange*> IntRangePair;
1037 typedef DenseSet<IntRangePair> RangeSet;
1038
Lang Hames3dc7c512012-02-17 18:44:18 +00001039public:
Lang Hamesecb50622012-02-17 23:43:40 +00001040 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
1041 const TargetRegisterInfo& TRI, SlotIndex NewIdx)
1042 : LIS(LIS), MRI(MRI), TRI(TRI), NewIdx(NewIdx) {}
Lang Hames3dc7c512012-02-17 18:44:18 +00001043
Lang Hames55fed622012-02-19 03:00:30 +00001044 // Update intervals for all operands of MI from OldIdx to NewIdx.
1045 // This assumes that MI used to be at OldIdx, and now resides at
1046 // NewIdx.
1047 void moveAllOperandsFrom(MachineInstr* MI, SlotIndex OldIdx) {
1048 // Collect the operands.
1049 RangeSet Entering, Internal, Exiting;
Lang Hamesac027142012-02-19 03:09:55 +00001050 bool hasRegMaskOp = false;
1051 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
Lang Hames55fed622012-02-19 03:00:30 +00001052
1053 moveAllEnteringFrom(OldIdx, Entering);
1054 moveAllInternalFrom(OldIdx, Internal);
1055 moveAllExitingFrom(OldIdx, Exiting);
1056
Lang Hamesac027142012-02-19 03:09:55 +00001057 if (hasRegMaskOp)
1058 updateRegMaskSlots(OldIdx);
1059
Lang Hames55fed622012-02-19 03:00:30 +00001060#ifndef NDEBUG
1061 LIValidator validator;
1062 std::for_each(Entering.begin(), Entering.end(), validator);
1063 std::for_each(Internal.begin(), Internal.end(), validator);
1064 std::for_each(Exiting.begin(), Exiting.end(), validator);
1065 assert(validator.rangesOk() && "moveOperandsFrom broke liveness.");
1066#endif
1067
Lang Hames3dc7c512012-02-17 18:44:18 +00001068 }
1069
Lang Hames55fed622012-02-19 03:00:30 +00001070private:
Lang Hames3dc7c512012-02-17 18:44:18 +00001071
Lang Hames55fed622012-02-19 03:00:30 +00001072#ifndef NDEBUG
1073 class LIValidator {
1074 private:
1075 DenseSet<const LiveInterval*> Checked, Bogus;
1076 public:
1077 void operator()(const IntRangePair& P) {
1078 const LiveInterval* LI = P.first;
1079 if (Checked.count(LI))
1080 return;
1081 Checked.insert(LI);
1082 if (LI->empty())
1083 return;
1084 SlotIndex LastEnd = LI->begin()->start;
1085 for (LiveInterval::const_iterator LRI = LI->begin(), LRE = LI->end();
1086 LRI != LRE; ++LRI) {
1087 const LiveRange& LR = *LRI;
1088 if (LastEnd > LR.start || LR.start >= LR.end)
1089 Bogus.insert(LI);
1090 LastEnd = LR.end;
Lang Hames3dc7c512012-02-17 18:44:18 +00001091 }
1092 }
Lang Hames3dc7c512012-02-17 18:44:18 +00001093
Lang Hames55fed622012-02-19 03:00:30 +00001094 bool rangesOk() const {
1095 return Bogus.empty();
Lang Hames3dc7c512012-02-17 18:44:18 +00001096 }
Lang Hames55fed622012-02-19 03:00:30 +00001097 };
1098#endif
Lang Hames3dc7c512012-02-17 18:44:18 +00001099
Lang Hames55fed622012-02-19 03:00:30 +00001100 // Collect IntRangePairs for all operands of MI that may need fixing.
1101 // Treat's MI's index as OldIdx (regardless of what it is in SlotIndexes'
1102 // maps).
1103 void collectRanges(MachineInstr* MI, RangeSet& Entering, RangeSet& Internal,
Lang Hamesac027142012-02-19 03:09:55 +00001104 RangeSet& Exiting, bool& hasRegMaskOp, SlotIndex OldIdx) {
1105 hasRegMaskOp = false;
Lang Hamesecb50622012-02-17 23:43:40 +00001106 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
1107 MOE = MI->operands_end();
1108 MOI != MOE; ++MOI) {
1109 const MachineOperand& MO = *MOI;
Lang Hamesac027142012-02-19 03:09:55 +00001110
1111 if (MO.isRegMask()) {
1112 hasRegMaskOp = true;
1113 continue;
1114 }
1115
Lang Hamesecb50622012-02-17 23:43:40 +00001116 if (!MO.isReg() || MO.getReg() == 0)
Lang Hames3dc7c512012-02-17 18:44:18 +00001117 continue;
1118
Lang Hamesecb50622012-02-17 23:43:40 +00001119 unsigned Reg = MO.getReg();
Lang Hames3dc7c512012-02-17 18:44:18 +00001120
1121 // TODO: Currently we're skipping uses that are reserved or have no
1122 // interval, but we're not updating their kills. This should be
1123 // fixed.
Lang Hamesecb50622012-02-17 23:43:40 +00001124 if (!LIS.hasInterval(Reg) ||
1125 (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg)))
Lang Hames3dc7c512012-02-17 18:44:18 +00001126 continue;
1127
Lang Hames55fed622012-02-19 03:00:30 +00001128 LiveInterval* LI = &LIS.getInterval(Reg);
1129
1130 if (MO.readsReg()) {
1131 LiveRange* LR = LI->getLiveRangeContaining(OldIdx);
1132 if (LR != 0)
1133 Entering.insert(std::make_pair(LI, LR));
Lang Hames3dc7c512012-02-17 18:44:18 +00001134 }
Lang Hamesecb50622012-02-17 23:43:40 +00001135 if (MO.isDef()) {
Lang Hames55fed622012-02-19 03:00:30 +00001136 if (MO.isEarlyClobber()) {
1137 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot(true));
1138 assert(LR != 0 && "No EC range?");
1139 if (LR->end > OldIdx.getDeadSlot())
1140 Exiting.insert(std::make_pair(LI, LR));
1141 else
Lang Hamesac027142012-02-19 03:09:55 +00001142 Internal.insert(std::make_pair(LI, LR));
Lang Hames55fed622012-02-19 03:00:30 +00001143 } else if (MO.isDead()) {
1144 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot());
1145 assert(LR != 0 && "No dead-def range?");
1146 Internal.insert(std::make_pair(LI, LR));
Lang Hames3dc7c512012-02-17 18:44:18 +00001147 } else {
Lang Hames55fed622012-02-19 03:00:30 +00001148 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getDeadSlot());
1149 assert(LR && LR->end > OldIdx.getDeadSlot() &&
1150 "Non-dead-def should have live range exiting.");
1151 Exiting.insert(std::make_pair(LI, LR));
Lang Hames3dc7c512012-02-17 18:44:18 +00001152 }
1153 }
1154 }
Lang Hames3dc7c512012-02-17 18:44:18 +00001155 }
1156
Lang Hamesecb50622012-02-17 23:43:40 +00001157 void moveKillFlags(unsigned reg, SlotIndex OldIdx, SlotIndex newKillIdx) {
1158 MachineInstr* OldKillMI = LIS.getInstructionFromIndex(OldIdx);
1159 if (!OldKillMI->killsRegister(reg))
Lang Hames3dc7c512012-02-17 18:44:18 +00001160 return; // Bail out if we don't have kill flags on the old register.
Lang Hamesecb50622012-02-17 23:43:40 +00001161 MachineInstr* NewKillMI = LIS.getInstructionFromIndex(newKillIdx);
1162 assert(OldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
1163 assert(!NewKillMI->killsRegister(reg) && "New kill instr is already a kill.");
1164 OldKillMI->clearRegisterKills(reg, &TRI);
1165 NewKillMI->addRegisterKilled(reg, &TRI);
Lang Hames3dc7c512012-02-17 18:44:18 +00001166 }
1167
Lang Hamesecb50622012-02-17 23:43:40 +00001168 void updateRegMaskSlots(SlotIndex OldIdx) {
1169 SmallVectorImpl<SlotIndex>::iterator RI =
1170 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1171 OldIdx);
1172 assert(*RI == OldIdx && "No RegMask at OldIdx.");
1173 *RI = NewIdx;
1174 assert(*prior(RI) < *RI && *RI < *next(RI) &&
Lang Hamesfbc8dd32012-02-17 21:29:41 +00001175 "RegSlots out of order. Did you move one call across another?");
1176 }
Lang Hames55fed622012-02-19 03:00:30 +00001177
1178 // Return the last use of reg between NewIdx and OldIdx.
1179 SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {
1180 SlotIndex LastUse = NewIdx;
1181 for (MachineRegisterInfo::use_nodbg_iterator
1182 UI = MRI.use_nodbg_begin(Reg),
1183 UE = MRI.use_nodbg_end();
Lang Hames038d2d52012-02-19 04:38:25 +00001184 UI != UE; UI.skipInstruction()) {
Lang Hames55fed622012-02-19 03:00:30 +00001185 const MachineInstr* MI = &*UI;
1186 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1187 if (InstSlot > LastUse && InstSlot < OldIdx)
1188 LastUse = InstSlot;
1189 }
1190 return LastUse;
1191 }
1192
1193 void moveEnteringUpFrom(SlotIndex OldIdx, IntRangePair& P) {
1194 LiveInterval* LI = P.first;
1195 LiveRange* LR = P.second;
1196 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1197 if (LiveThrough)
1198 return;
1199 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1200 if (LastUse != NewIdx)
1201 moveKillFlags(LI->reg, NewIdx, LastUse);
1202 LR->end = LastUse.getRegSlot(LR->end.isEarlyClobber());
1203 }
1204
1205 void moveEnteringDownFrom(SlotIndex OldIdx, IntRangePair& P) {
1206 LiveInterval* LI = P.first;
1207 LiveRange* LR = P.second;
Lang Hames4a0b2d62012-02-19 06:13:56 +00001208 if (NewIdx > LR->end) {
1209 moveKillFlags(LI->reg, LR->end, NewIdx);
1210 LR->end = NewIdx.getRegSlot();
Lang Hames55fed622012-02-19 03:00:30 +00001211 }
1212 }
1213
1214 void moveAllEnteringFrom(SlotIndex OldIdx, RangeSet& Entering) {
1215 bool GoingUp = NewIdx < OldIdx;
1216
1217 if (GoingUp) {
1218 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1219 EI != EE; ++EI)
1220 moveEnteringUpFrom(OldIdx, *EI);
1221 } else {
1222 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1223 EI != EE; ++EI)
1224 moveEnteringDownFrom(OldIdx, *EI);
1225 }
1226 }
1227
1228 void moveInternalFrom(SlotIndex OldIdx, IntRangePair& P) {
1229 LiveInterval* LI = P.first;
1230 LiveRange* LR = P.second;
1231 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1232 LR->end <= OldIdx.getDeadSlot() &&
1233 "Range should be internal to OldIdx.");
1234 LiveRange Tmp(*LR);
1235 Tmp.start = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1236 Tmp.valno->def = Tmp.start;
1237 Tmp.end = LR->end.isDead() ? NewIdx.getDeadSlot() : NewIdx.getRegSlot();
1238 LI->removeRange(*LR);
1239 LI->addRange(Tmp);
1240 }
1241
1242 void moveAllInternalFrom(SlotIndex OldIdx, RangeSet& Internal) {
1243 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1244 II != IE; ++II)
1245 moveInternalFrom(OldIdx, *II);
1246 }
1247
1248 void moveExitingFrom(SlotIndex OldIdx, IntRangePair& P) {
1249 LiveRange* LR = P.second;
1250 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1251 "Range should start in OldIdx.");
1252 assert(LR->end > OldIdx.getDeadSlot() && "Range should exit OldIdx.");
1253 SlotIndex NewStart = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1254 LR->start = NewStart;
1255 LR->valno->def = NewStart;
1256 }
1257
1258 void moveAllExitingFrom(SlotIndex OldIdx, RangeSet& Exiting) {
1259 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1260 EI != EE; ++EI)
1261 moveExitingFrom(OldIdx, *EI);
1262 }
1263
Lang Hames3dc7c512012-02-17 18:44:18 +00001264};
1265
Lang Hamesecb50622012-02-17 23:43:40 +00001266void LiveIntervals::handleMove(MachineInstr* MI) {
1267 SlotIndex OldIndex = indexes_->getInstructionIndex(MI);
1268 indexes_->removeMachineInstrFromMaps(MI);
1269 SlotIndex NewIndex = MI->isInsideBundle() ?
1270 indexes_->getInstructionIndex(MI->getBundleStart()) :
1271 indexes_->insertMachineInstrInMaps(MI);
1272 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1273 OldIndex < getMBBEndIdx(MI->getParent()) &&
Lang Hames3dc7c512012-02-17 18:44:18 +00001274 "Cannot handle moves across basic block boundaries.");
Lang Hamesecb50622012-02-17 23:43:40 +00001275 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
Lang Hames3dc7c512012-02-17 18:44:18 +00001276
Lang Hamesecb50622012-02-17 23:43:40 +00001277 HMEditor HME(*this, *mri_, *tri_, NewIndex);
1278 HME.moveAllOperandsFrom(MI, OldIndex);
Lang Hames3dc7c512012-02-17 18:44:18 +00001279}