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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 6ea706e40e841c148bc47bcac4dcca5e0f0245eb / . / lib / Target / Hexagon / HexagonInstrInfo.h
blob: 03a8a77a33ad3d2dd8ce099a388a3b1b14b50ccf [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef HexagonINSTRUCTIONINFO_H
15#define HexagonINSTRUCTIONINFO_H
16
Craig Topper79aa3412012-03-17 18:46:09 +0000[diff] [blame]17#include "HexagonRegisterInfo.h"
Brendon Cahoonc635ebd2012-02-08 18:25:47 +0000[diff] [blame]18#include "MCTargetDesc/HexagonBaseInfo.h"
Jyotsna Verma6ea706e2013-05-01 21:37:34 +0000[diff] [blame^]19#include "llvm/Target/TargetInstrInfo.h"
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]20#include "llvm/Target/TargetFrameLowering.h"
Chandler Carrutha1514e22012-12-04 07:12:27 +0000[diff] [blame]21#include "llvm/Target/TargetInstrInfo.h"
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]22
23
24#define GET_INSTRINFO_HEADER
25#include "HexagonGenInstrInfo.inc"
26
27namespace llvm {
28
29class HexagonInstrInfo : public HexagonGenInstrInfo {
30 const HexagonRegisterInfo RI;
31 const HexagonSubtarget& Subtarget;
Jyotsna Verma6ea706e2013-05-01 21:37:34 +0000[diff] [blame^]32 typedef unsigned Opcode_t;
33
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]34public:
35 explicit HexagonInstrInfo(HexagonSubtarget &ST);
36
37 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
38 /// such, whenever a client has an instance of instruction info, it should
39 /// always be able to get register info as well (through this method).
40 ///
41 virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
42
43 /// isLoadFromStackSlot - If the specified machine instruction is a direct
44 /// load from a stack slot, return the virtual or physical register number of
45 /// the destination along with the FrameIndex of the loaded stack slot. If
46 /// not, return 0. This predicate must return 0 if the instruction has
47 /// any side effects other than loading from the stack slot.
48 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
49 int &FrameIndex) const;
50
51 /// isStoreToStackSlot - If the specified machine instruction is a direct
52 /// store to a stack slot, return the virtual or physical register number of
53 /// the source reg along with the FrameIndex of the loaded stack slot. If
54 /// not, return 0. This predicate must return 0 if the instruction has
55 /// any side effects other than storing to the stack slot.
56 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
57 int &FrameIndex) const;
58
59
60 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
61 MachineBasicBlock *&FBB,
62 SmallVectorImpl<MachineOperand> &Cond,
63 bool AllowModify) const;
64
65 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
66
67 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
68 MachineBasicBlock *FBB,
69 const SmallVectorImpl<MachineOperand> &Cond,
70 DebugLoc DL) const;
71
Krzysztof Parzyszekce55d912013-02-11 20:04:29 +0000[diff] [blame]72 virtual bool analyzeCompare(const MachineInstr *MI,
73 unsigned &SrcReg, unsigned &SrcReg2,
74 int &Mask, int &Value) const;
75
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]76 virtual void copyPhysReg(MachineBasicBlock &MBB,
77 MachineBasicBlock::iterator I, DebugLoc DL,
78 unsigned DestReg, unsigned SrcReg,
79 bool KillSrc) const;
80
81 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator MBBI,
83 unsigned SrcReg, bool isKill, int FrameIndex,
84 const TargetRegisterClass *RC,
85 const TargetRegisterInfo *TRI) const;
86
87 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
88 SmallVectorImpl<MachineOperand> &Addr,
89 const TargetRegisterClass *RC,
90 SmallVectorImpl<MachineInstr*> &NewMIs) const;
91
92 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
93 MachineBasicBlock::iterator MBBI,
94 unsigned DestReg, int FrameIndex,
95 const TargetRegisterClass *RC,
96 const TargetRegisterInfo *TRI) const;
97
98 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
99 SmallVectorImpl<MachineOperand> &Addr,
100 const TargetRegisterClass *RC,
101 SmallVectorImpl<MachineInstr*> &NewMIs) const;
102
103 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
104 MachineInstr* MI,
105 const SmallVectorImpl<unsigned> &Ops,
106 int FrameIndex) const;
107
108 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
109 MachineInstr* MI,
110 const SmallVectorImpl<unsigned> &Ops,
111 MachineInstr* LoadMI) const {
112 return 0;
113 }
114
115 unsigned createVR(MachineFunction* MF, MVT VT) const;
116
117 virtual bool isPredicable(MachineInstr *MI) const;
118 virtual bool
119 PredicateInstruction(MachineInstr *MI,
120 const SmallVectorImpl<MachineOperand> &Cond) const;
121
Kay Tiong Khoo575e90e2012-06-13 15:53:04 +0000[diff] [blame]122 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]123 unsigned ExtraPredCycles,
124 const BranchProbability &Probability) const;
125
126 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
127 unsigned NumTCycles, unsigned ExtraTCycles,
128 MachineBasicBlock &FMBB,
129 unsigned NumFCycles, unsigned ExtraFCycles,
130 const BranchProbability &Probability) const;
131
132 virtual bool isPredicated(const MachineInstr *MI) const;
Jyotsna Verma810848d2013-03-28 19:44:04 +0000[diff] [blame]133 virtual bool isPredicatedNew(const MachineInstr *MI) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]134 virtual bool DefinesPredicate(MachineInstr *MI,
135 std::vector<MachineOperand> &Pred) const;
136 virtual bool
137 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
138 const SmallVectorImpl<MachineOperand> &Pred2) const;
139
140 virtual bool
141 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
142
143 virtual bool
144 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles,
145 const BranchProbability &Probability) const;
146
Jyotsna Verma2a885552013-03-29 21:09:53 +0000[diff] [blame]147 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
148 int FrameIx,
149 uint64_t Offset,
150 const MDNode *MDPtr,
151 DebugLoc DL) const;
Andrew Trickee498d32012-02-01 22:13:57 +0000[diff] [blame]152 virtual DFAPacketizer*
153 CreateTargetScheduleState(const TargetMachine *TM,
154 const ScheduleDAG *DAG) const;
155
156 virtual bool isSchedulingBoundary(const MachineInstr *MI,
157 const MachineBasicBlock *MBB,
158 const MachineFunction &MF) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]159 bool isValidOffset(const int Opcode, const int Offset) const;
160 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
161 bool isMemOp(const MachineInstr *MI) const;
162 bool isSpillPredRegOp(const MachineInstr *MI) const;
163 bool isU6_3Immediate(const int value) const;
164 bool isU6_2Immediate(const int value) const;
165 bool isU6_1Immediate(const int value) const;
166 bool isU6_0Immediate(const int value) const;
167 bool isS4_3Immediate(const int value) const;
168 bool isS4_2Immediate(const int value) const;
169 bool isS4_1Immediate(const int value) const;
170 bool isS4_0Immediate(const int value) const;
171 bool isS12_Immediate(const int value) const;
172 bool isU6_Immediate(const int value) const;
173 bool isS8_Immediate(const int value) const;
174 bool isS6_Immediate(const int value) const;
175
Sirish Pande26f61a12012-05-03 21:52:53 +0000[diff] [blame]176 bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
177 bool isConditionalTransfer(const MachineInstr* MI) const;
Chandler Carruthd410eab2012-04-23 18:25:57 +0000[diff] [blame]178 bool isConditionalALU32 (const MachineInstr* MI) const;
179 bool isConditionalLoad (const MachineInstr* MI) const;
Sirish Pande26f61a12012-05-03 21:52:53 +0000[diff] [blame]180 bool isConditionalStore(const MachineInstr* MI) const;
Jyotsna Verma9feabc22013-03-05 18:51:42 +0000[diff] [blame]181 bool isNewValueInst(const MachineInstr* MI) const;
Jyotsna Verma810848d2013-03-28 19:44:04 +0000[diff] [blame]182 bool isDotNewInst(const MachineInstr* MI) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]183 bool isDeallocRet(const MachineInstr *MI) const;
Chandler Carruthd410eab2012-04-23 18:25:57 +0000[diff] [blame]184 unsigned getInvertedPredicatedOpcode(const int Opc) const;
Sirish Pande26f61a12012-05-03 21:52:53 +0000[diff] [blame]185 bool isExtendable(const MachineInstr* MI) const;
186 bool isExtended(const MachineInstr* MI) const;
187 bool isPostIncrement(const MachineInstr* MI) const;
188 bool isNewValueStore(const MachineInstr* MI) const;
189 bool isNewValueJump(const MachineInstr* MI) const;
Sirish Pandeb3385702012-05-12 05:10:30 +0000[diff] [blame]190 bool isNewValueJumpCandidate(const MachineInstr *MI) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]191
Jyotsna Vermaef94c6c2013-03-01 17:37:13 +0000[diff] [blame]192
193 void immediateExtend(MachineInstr *MI) const;
194 bool isConstExtended(MachineInstr *MI) const;
195 unsigned getAddrMode(const MachineInstr* MI) const;
196 bool isOperandExtended(const MachineInstr *MI,
197 unsigned short OperandNum) const;
198 unsigned short getCExtOpNum(const MachineInstr *MI) const;
199 int getMinValue(const MachineInstr *MI) const;
200 int getMaxValue(const MachineInstr *MI) const;
201 bool NonExtEquivalentExists (const MachineInstr *MI) const;
202 short getNonExtOpcode(const MachineInstr *MI) const;
Jyotsna Verma6ea706e2013-05-01 21:37:34 +0000[diff] [blame^]203 bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
204 bool PredOpcodeHasNot(Opcode_t Opcode) const;
205
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]206private:
207 int getMatchingCondBranchOpcode(int Opc, bool sense) const;
208
209};
210
211}
212
213#endif