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Jia Liubb481f82012-02-28 07:46:26 +00001//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00007//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00008//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00009//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +000013//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000014
15#define DEBUG_TYPE "mips-lower"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000016#include "MipsISelLowering.h"
Bruno Cardoso Lopesa2b1bb52007-08-28 05:08:16 +000017#include "MipsMachineFunction.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000018#include "MipsTargetMachine.h"
Chris Lattnerb71b9092009-08-13 06:28:06 +000019#include "MipsTargetObjectFile.h"
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000020#include "MipsSubtarget.h"
Craig Topper79aa3412012-03-17 18:46:09 +000021#include "InstPrinter/MipsInstPrinter.h"
22#include "MCTargetDesc/MipsBaseInfo.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000023#include "llvm/DerivedTypes.h"
24#include "llvm/Function.h"
Bruno Cardoso Lopes91fd5322008-07-21 18:52:34 +000025#include "llvm/GlobalVariable.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000026#include "llvm/Intrinsics.h"
27#include "llvm/CallingConv.h"
28#include "llvm/CodeGen/CallingConvLower.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineFunction.h"
31#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000032#include "llvm/CodeGen/MachineRegisterInfo.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000033#include "llvm/CodeGen/SelectionDAGISel.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000034#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/Support/Debug.h"
Torok Edwinc25e7582009-07-11 20:10:48 +000036#include "llvm/Support/ErrorHandling.h"
NAKAMURA Takumi89593932012-04-21 15:31:45 +000037#include "llvm/Support/raw_ostream.h"
38
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000039using namespace llvm;
40
Jia Liubb481f82012-02-28 07:46:26 +000041// If I is a shifted mask, set the size (Size) and the first bit of the
Akira Hatanakadbe9a312011-08-18 20:07:42 +000042// mask (Pos), and return true.
Jia Liubb481f82012-02-28 07:46:26 +000043// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
Akira Hatanaka854a7db2011-08-19 22:59:00 +000044static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
Akira Hatanakad6bc5232011-12-05 21:26:34 +000045 if (!isShiftedMask_64(I))
Akira Hatanaka854a7db2011-08-19 22:59:00 +000046 return false;
Akira Hatanakabb15e112011-08-17 02:05:42 +000047
Akira Hatanakad6bc5232011-12-05 21:26:34 +000048 Size = CountPopulation_64(I);
49 Pos = CountTrailingZeros_64(I);
Akira Hatanakadbe9a312011-08-18 20:07:42 +000050 return true;
Akira Hatanakabb15e112011-08-17 02:05:42 +000051}
52
Akira Hatanaka648f00c2012-02-24 22:34:47 +000053static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) {
54 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
55 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
56}
57
Chris Lattnerf0144122009-07-28 03:13:23 +000058const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
59 switch (Opcode) {
Akira Hatanakabdd2ce92011-05-23 21:13:59 +000060 case MipsISD::JmpLink: return "MipsISD::JmpLink";
61 case MipsISD::Hi: return "MipsISD::Hi";
62 case MipsISD::Lo: return "MipsISD::Lo";
63 case MipsISD::GPRel: return "MipsISD::GPRel";
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +000064 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
Akira Hatanakabdd2ce92011-05-23 21:13:59 +000065 case MipsISD::Ret: return "MipsISD::Ret";
66 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
67 case MipsISD::FPCmp: return "MipsISD::FPCmp";
68 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
69 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
70 case MipsISD::FPRound: return "MipsISD::FPRound";
71 case MipsISD::MAdd: return "MipsISD::MAdd";
72 case MipsISD::MAddu: return "MipsISD::MAddu";
73 case MipsISD::MSub: return "MipsISD::MSub";
74 case MipsISD::MSubu: return "MipsISD::MSubu";
75 case MipsISD::DivRem: return "MipsISD::DivRem";
76 case MipsISD::DivRemU: return "MipsISD::DivRemU";
77 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
78 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
Akira Hatanakabfcb83f2011-12-12 22:38:19 +000079 case MipsISD::Wrapper: return "MipsISD::Wrapper";
Akira Hatanaka21afc632011-06-21 00:40:49 +000080 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
Akira Hatanakadb548262011-07-19 23:30:50 +000081 case MipsISD::Sync: return "MipsISD::Sync";
Akira Hatanakabb15e112011-08-17 02:05:42 +000082 case MipsISD::Ext: return "MipsISD::Ext";
83 case MipsISD::Ins: return "MipsISD::Ins";
Akira Hatanakab6f1dc22012-06-02 00:03:12 +000084 case MipsISD::LWL: return "MipsISD::LWL";
85 case MipsISD::LWR: return "MipsISD::LWR";
86 case MipsISD::SWL: return "MipsISD::SWL";
87 case MipsISD::SWR: return "MipsISD::SWR";
88 case MipsISD::LDL: return "MipsISD::LDL";
89 case MipsISD::LDR: return "MipsISD::LDR";
90 case MipsISD::SDL: return "MipsISD::SDL";
91 case MipsISD::SDR: return "MipsISD::SDR";
Akira Hatanaka6fad5e72012-09-21 23:52:47 +000092 case MipsISD::EXTP: return "MipsISD::EXTP";
93 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
94 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
95 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
96 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
97 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
98 case MipsISD::SHILO: return "MipsISD::SHILO";
99 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
100 case MipsISD::MULT: return "MipsISD::MULT";
101 case MipsISD::MULTU: return "MipsISD::MULTU";
102 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSPDSP";
103 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
104 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
105 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
Akira Hatanaka0f843822011-06-07 18:58:42 +0000106 default: return NULL;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000107 }
108}
109
110MipsTargetLowering::
Chris Lattnerf0144122009-07-28 03:13:23 +0000111MipsTargetLowering(MipsTargetMachine &TM)
Akira Hatanaka8b4198d2011-09-26 21:47:02 +0000112 : TargetLowering(TM, new MipsTargetObjectFile()),
113 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
Akira Hatanaka2ec69fa2011-10-28 18:47:24 +0000114 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
115 IsO32(Subtarget->isABI_O32()) {
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000116
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000117 // Mips does not have i1 type, so use i32 for
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000118 // setcc operations results (slt, sgt, ...).
Duncan Sands03228082008-11-23 15:47:28 +0000119 setBooleanContents(ZeroOrOneBooleanContent);
Duncan Sands28b77e92011-09-06 19:07:46 +0000120 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000121
122 // Set up the register classes
Craig Topper420761a2012-04-20 07:30:17 +0000123 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000124
Akira Hatanaka95934842011-09-24 01:34:44 +0000125 if (HasMips64)
Craig Topper420761a2012-04-20 07:30:17 +0000126 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
Akira Hatanaka95934842011-09-24 01:34:44 +0000127
Akira Hatanaka28ee4fd2012-05-31 02:59:44 +0000128 if (Subtarget->inMips16Mode()) {
129 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
Akira Hatanaka28ee4fd2012-05-31 02:59:44 +0000130 }
131
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000132 if (!TM.Options.UseSoftFloat) {
Craig Topper420761a2012-04-20 07:30:17 +0000133 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000134
135 // When dealing with single precision only, use libcalls
136 if (!Subtarget->isSingleFloat()) {
137 if (HasMips64)
Craig Topper420761a2012-04-20 07:30:17 +0000138 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000139 else
Craig Topper420761a2012-04-20 07:30:17 +0000140 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000141 }
Akira Hatanaka792016b2011-09-23 18:28:39 +0000142 }
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000143
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000144 // Load extented operations for i1 types must be promoted
Owen Anderson825b72b2009-08-11 20:47:22 +0000145 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
146 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
147 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000148
Eli Friedman6055a6a2009-07-17 04:07:24 +0000149 // MIPS doesn't have extending float->double load/store
Owen Anderson825b72b2009-08-11 20:47:22 +0000150 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
151 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
Eli Friedman10a36592009-07-17 02:28:12 +0000152
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000153 // Used by legalize types to correctly generate the setcc result.
154 // Without this, every float setcc comes with a AND/OR with the result,
155 // we don't want this, since the fpcmp result goes to a flag register,
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +0000156 // which is used implicitly by brcond and select operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000157 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +0000158
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000159 // Mips Custom Operations
Owen Anderson825b72b2009-08-11 20:47:22 +0000160 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +0000161 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
Owen Anderson825b72b2009-08-11 20:47:22 +0000162 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
163 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
164 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
165 setOperationAction(ISD::SELECT, MVT::f32, Custom);
166 setOperationAction(ISD::SELECT, MVT::f64, Custom);
167 setOperationAction(ISD::SELECT, MVT::i32, Custom);
Akira Hatanaka3fef29d2012-07-11 19:32:27 +0000168 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
169 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
Akira Hatanaka0a40c232012-03-09 23:46:03 +0000170 setOperationAction(ISD::SETCC, MVT::f32, Custom);
171 setOperationAction(ISD::SETCC, MVT::f64, Custom);
Owen Anderson825b72b2009-08-11 20:47:22 +0000172 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000173 setOperationAction(ISD::VASTART, MVT::Other, Custom);
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000174 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
175 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
176 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
177 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
Akira Hatanakaf934d152012-09-15 01:02:03 +0000178 if (!Subtarget->inMips16Mode()) {
179 setOperationAction(ISD::LOAD, MVT::i32, Custom);
180 setOperationAction(ISD::STORE, MVT::i32, Custom);
181 }
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000182
Akira Hatanakac12a6e62012-04-11 22:49:04 +0000183 if (!TM.Options.NoNaNsFPMath) {
184 setOperationAction(ISD::FABS, MVT::f32, Custom);
185 setOperationAction(ISD::FABS, MVT::f64, Custom);
186 }
187
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000188 if (HasMips64) {
189 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
190 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
191 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
192 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
193 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
194 setOperationAction(ISD::SELECT, MVT::i64, Custom);
Akira Hatanaka7664f052012-06-02 00:04:42 +0000195 setOperationAction(ISD::LOAD, MVT::i64, Custom);
196 setOperationAction(ISD::STORE, MVT::i64, Custom);
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000197 }
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000198
Akira Hatanakaa284acb2012-05-09 00:55:21 +0000199 if (!HasMips64) {
200 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
201 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
202 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
203 }
204
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000205 setOperationAction(ISD::SDIV, MVT::i32, Expand);
206 setOperationAction(ISD::SREM, MVT::i32, Expand);
207 setOperationAction(ISD::UDIV, MVT::i32, Expand);
208 setOperationAction(ISD::UREM, MVT::i32, Expand);
Akira Hatanakadda4a072011-10-03 21:06:13 +0000209 setOperationAction(ISD::SDIV, MVT::i64, Expand);
210 setOperationAction(ISD::SREM, MVT::i64, Expand);
211 setOperationAction(ISD::UDIV, MVT::i64, Expand);
212 setOperationAction(ISD::UREM, MVT::i64, Expand);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000213
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000214 // Operations not directly supported by Mips.
Owen Anderson825b72b2009-08-11 20:47:22 +0000215 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
216 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
217 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
218 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
Akira Hatanakae1bcd6b2011-12-20 23:40:56 +0000219 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000220 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
Akira Hatanakae1bcd6b2011-12-20 23:40:56 +0000221 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000222 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
223 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
Akira Hatanaka7f162742011-12-21 00:14:05 +0000224 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000225 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
Akira Hatanaka7f162742011-12-21 00:14:05 +0000226 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
Chandler Carruth63974b22011-12-13 01:56:10 +0000227 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
228 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
229 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
230 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000231 setOperationAction(ISD::ROTL, MVT::i32, Expand);
Akira Hatanakac7bafe92011-09-30 18:51:46 +0000232 setOperationAction(ISD::ROTL, MVT::i64, Expand);
Akira Hatanaka1d165f12012-07-31 20:54:48 +0000233 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
234 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
Bruno Cardoso Lopes908b6dd2010-12-09 17:32:30 +0000235
Akira Hatanaka56633442011-09-20 23:53:09 +0000236 if (!Subtarget->hasMips32r2())
Bruno Cardoso Lopes908b6dd2010-12-09 17:32:30 +0000237 setOperationAction(ISD::ROTR, MVT::i32, Expand);
238
Akira Hatanakac7bafe92011-09-30 18:51:46 +0000239 if (!Subtarget->hasMips64r2())
240 setOperationAction(ISD::ROTR, MVT::i64, Expand);
241
Owen Anderson825b72b2009-08-11 20:47:22 +0000242 setOperationAction(ISD::FSIN, MVT::f32, Expand);
Bruno Cardoso Lopes5d6fb5d2011-03-04 18:54:14 +0000243 setOperationAction(ISD::FSIN, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000244 setOperationAction(ISD::FCOS, MVT::f32, Expand);
Bruno Cardoso Lopes5d6fb5d2011-03-04 18:54:14 +0000245 setOperationAction(ISD::FCOS, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000246 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
247 setOperationAction(ISD::FPOW, MVT::f32, Expand);
Akira Hatanaka46da1362011-05-23 22:23:58 +0000248 setOperationAction(ISD::FPOW, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000249 setOperationAction(ISD::FLOG, MVT::f32, Expand);
250 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
251 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
252 setOperationAction(ISD::FEXP, MVT::f32, Expand);
Cameron Zwarich33390842011-07-08 21:39:21 +0000253 setOperationAction(ISD::FMA, MVT::f32, Expand);
254 setOperationAction(ISD::FMA, MVT::f64, Expand);
Akira Hatanaka21ecc2f2012-03-29 18:43:11 +0000255 setOperationAction(ISD::FREM, MVT::f32, Expand);
256 setOperationAction(ISD::FREM, MVT::f64, Expand);
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000257
Akira Hatanaka1cc63332012-04-11 22:59:08 +0000258 if (!TM.Options.NoNaNsFPMath) {
259 setOperationAction(ISD::FNEG, MVT::f32, Expand);
260 setOperationAction(ISD::FNEG, MVT::f64, Expand);
261 }
262
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000263 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
Akira Hatanaka590baca2012-02-02 03:13:40 +0000264 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000265 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
Akira Hatanaka590baca2012-02-02 03:13:40 +0000266 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
Eric Christopher471e4222011-06-08 23:55:35 +0000267
Bruno Cardoso Lopes954dac02011-03-09 19:22:22 +0000268 setOperationAction(ISD::VAARG, MVT::Other, Expand);
269 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
270 setOperationAction(ISD::VAEND, MVT::Other, Expand);
271
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000272 // Use the default for now
Owen Anderson825b72b2009-08-11 20:47:22 +0000273 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
274 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
Eli Friedman14648462011-07-27 22:21:52 +0000275
Jia Liubb481f82012-02-28 07:46:26 +0000276 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
277 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
278 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
279 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
Eli Friedman4db5aca2011-08-29 18:23:02 +0000280
Eli Friedman26689ac2011-08-03 21:06:02 +0000281 setInsertFencesForAtomic(true);
282
Bruno Cardoso Lopes7728f7e2008-07-09 05:32:22 +0000283 if (!Subtarget->hasSEInReg()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000284 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
285 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000286 }
287
Akira Hatanakac79507a2011-12-21 00:20:27 +0000288 if (!Subtarget->hasBitCount()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000289 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
Akira Hatanakac79507a2011-12-21 00:20:27 +0000290 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
291 }
Bruno Cardoso Lopes65ad4522008-08-08 06:16:31 +0000292
Akira Hatanakac0ea0432011-12-20 23:56:43 +0000293 if (!Subtarget->hasSwap()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000294 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
Akira Hatanakac0ea0432011-12-20 23:56:43 +0000295 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
296 }
Bruno Cardoso Lopes739e4412008-08-13 07:13:40 +0000297
Akira Hatanaka7664f052012-06-02 00:04:42 +0000298 if (HasMips64) {
299 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
300 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
301 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
302 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
303 }
304
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000305 setTargetDAGCombine(ISD::ADDE);
306 setTargetDAGCombine(ISD::SUBE);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000307 setTargetDAGCombine(ISD::SDIVREM);
308 setTargetDAGCombine(ISD::UDIVREM);
Akira Hatanakaee8c3b02012-03-08 03:26:37 +0000309 setTargetDAGCombine(ISD::SELECT);
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000310 setTargetDAGCombine(ISD::AND);
311 setTargetDAGCombine(ISD::OR);
Akira Hatanaka87827072012-06-13 20:33:18 +0000312 setTargetDAGCombine(ISD::ADD);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000313
Akira Hatanaka5fdf5002012-03-08 01:59:33 +0000314 setMinFunctionAlignment(HasMips64 ? 3 : 2);
Eli Friedmanfc5d3052011-05-06 20:34:06 +0000315
Akira Hatanaka3f5b1072012-02-02 03:17:04 +0000316 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000317 computeRegisterProperties();
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000318
Akira Hatanaka590baca2012-02-02 03:13:40 +0000319 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
320 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
Akira Hatanakae193b322012-06-13 19:33:32 +0000321
322 maxStoresPerMemcpy = 16;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000323}
324
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +0000325bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
Akira Hatanaka511961a2011-08-17 18:49:18 +0000326 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
Jia Liubb481f82012-02-28 07:46:26 +0000327
Akira Hatanakaf934d152012-09-15 01:02:03 +0000328 if (Subtarget->inMips16Mode())
329 return false;
330
Akira Hatanaka44b6c712012-02-28 02:55:02 +0000331 switch (SVT) {
332 case MVT::i64:
333 case MVT::i32:
Akira Hatanaka44b6c712012-02-28 02:55:02 +0000334 return true;
Akira Hatanaka44b6c712012-02-28 02:55:02 +0000335 default:
336 return false;
337 }
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +0000338}
339
Duncan Sands28b77e92011-09-06 19:07:46 +0000340EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
Owen Anderson825b72b2009-08-11 20:47:22 +0000341 return MVT::i32;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000342}
343
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000344// SelectMadd -
345// Transforms a subgraph in CurDAG if the following pattern is found:
346// (addc multLo, Lo0), (adde multHi, Hi0),
347// where,
348// multHi/Lo: product of multiplication
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000349// Lo0: initial value of Lo register
350// Hi0: initial value of Hi register
Akira Hatanaka81bd78b2011-03-30 21:15:35 +0000351// Return true if pattern matching was successful.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000352static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) {
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000353 // ADDENode's second operand must be a flag output of an ADDC node in order
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000354 // for the matching to be successful.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000355 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000356
357 if (ADDCNode->getOpcode() != ISD::ADDC)
358 return false;
359
360 SDValue MultHi = ADDENode->getOperand(0);
361 SDValue MultLo = ADDCNode->getOperand(0);
Akira Hatanaka864f6602012-06-14 21:10:56 +0000362 SDNode *MultNode = MultHi.getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000363 unsigned MultOpc = MultHi.getOpcode();
364
365 // MultHi and MultLo must be generated by the same node,
366 if (MultLo.getNode() != MultNode)
367 return false;
368
369 // and it must be a multiplication.
370 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
371 return false;
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000372
373 // MultLo amd MultHi must be the first and second output of MultNode
374 // respectively.
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000375 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
376 return false;
377
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000378 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000379 // of the values of MultNode, in which case MultNode will be removed in later
380 // phases.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000381 // If there exist users other than ADDENode or ADDCNode, this function returns
382 // here, which will result in MultNode being mapped to a single MULT
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000383 // instruction node rather than a pair of MULT and MADD instructions being
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000384 // produced.
385 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
386 return false;
387
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000388 SDValue Chain = CurDAG->getEntryNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000389 DebugLoc dl = ADDENode->getDebugLoc();
390
391 // create MipsMAdd(u) node
392 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000393
Akira Hatanaka82099682011-12-19 19:52:25 +0000394 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000395 MultNode->getOperand(0),// Factor 0
396 MultNode->getOperand(1),// Factor 1
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000397 ADDCNode->getOperand(1),// Lo0
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000398 ADDENode->getOperand(1));// Hi0
399
400 // create CopyFromReg nodes
401 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
402 MAdd);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000403 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000404 Mips::HI, MVT::i32,
405 CopyFromLo.getValue(2));
406
407 // replace uses of adde and addc here
408 if (!SDValue(ADDCNode, 0).use_empty())
409 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
410
411 if (!SDValue(ADDENode, 0).use_empty())
412 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
413
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000414 return true;
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000415}
416
417// SelectMsub -
418// Transforms a subgraph in CurDAG if the following pattern is found:
419// (addc Lo0, multLo), (sube Hi0, multHi),
420// where,
421// multHi/Lo: product of multiplication
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000422// Lo0: initial value of Lo register
423// Hi0: initial value of Hi register
Akira Hatanaka81bd78b2011-03-30 21:15:35 +0000424// Return true if pattern matching was successful.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000425static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) {
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000426 // SUBENode's second operand must be a flag output of an SUBC node in order
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000427 // for the matching to be successful.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000428 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000429
430 if (SUBCNode->getOpcode() != ISD::SUBC)
431 return false;
432
433 SDValue MultHi = SUBENode->getOperand(1);
434 SDValue MultLo = SUBCNode->getOperand(1);
Akira Hatanaka864f6602012-06-14 21:10:56 +0000435 SDNode *MultNode = MultHi.getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000436 unsigned MultOpc = MultHi.getOpcode();
437
438 // MultHi and MultLo must be generated by the same node,
439 if (MultLo.getNode() != MultNode)
440 return false;
441
442 // and it must be a multiplication.
443 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
444 return false;
445
446 // MultLo amd MultHi must be the first and second output of MultNode
447 // respectively.
448 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
449 return false;
450
451 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
452 // of the values of MultNode, in which case MultNode will be removed in later
453 // phases.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000454 // If there exist users other than SUBENode or SUBCNode, this function returns
455 // here, which will result in MultNode being mapped to a single MULT
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000456 // instruction node rather than a pair of MULT and MSUB instructions being
457 // produced.
458 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
459 return false;
460
461 SDValue Chain = CurDAG->getEntryNode();
462 DebugLoc dl = SUBENode->getDebugLoc();
463
464 // create MipsSub(u) node
465 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
466
Akira Hatanaka82099682011-12-19 19:52:25 +0000467 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000468 MultNode->getOperand(0),// Factor 0
469 MultNode->getOperand(1),// Factor 1
470 SUBCNode->getOperand(0),// Lo0
471 SUBENode->getOperand(0));// Hi0
472
473 // create CopyFromReg nodes
474 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
475 MSub);
476 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
477 Mips::HI, MVT::i32,
478 CopyFromLo.getValue(2));
479
480 // replace uses of sube and subc here
481 if (!SDValue(SUBCNode, 0).use_empty())
482 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
483
484 if (!SDValue(SUBENode, 0).use_empty())
485 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
486
487 return true;
488}
489
Akira Hatanaka864f6602012-06-14 21:10:56 +0000490static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000491 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000492 const MipsSubtarget *Subtarget) {
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000493 if (DCI.isBeforeLegalize())
494 return SDValue();
495
Akira Hatanakae184fec2011-11-11 04:18:21 +0000496 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
497 SelectMadd(N, &DAG))
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000498 return SDValue(N, 0);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000499
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000500 return SDValue();
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000501}
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000502
Akira Hatanaka864f6602012-06-14 21:10:56 +0000503static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000504 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000505 const MipsSubtarget *Subtarget) {
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000506 if (DCI.isBeforeLegalize())
507 return SDValue();
508
Akira Hatanakae184fec2011-11-11 04:18:21 +0000509 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
510 SelectMsub(N, &DAG))
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000511 return SDValue(N, 0);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000512
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000513 return SDValue();
514}
515
Akira Hatanaka864f6602012-06-14 21:10:56 +0000516static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG,
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000517 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000518 const MipsSubtarget *Subtarget) {
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000519 if (DCI.isBeforeLegalizeOps())
520 return SDValue();
521
Akira Hatanakadda4a072011-10-03 21:06:13 +0000522 EVT Ty = N->getValueType(0);
Jia Liubb481f82012-02-28 07:46:26 +0000523 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
524 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000525 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
526 MipsISD::DivRemU;
527 DebugLoc dl = N->getDebugLoc();
528
529 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
530 N->getOperand(0), N->getOperand(1));
531 SDValue InChain = DAG.getEntryNode();
532 SDValue InGlue = DivRem;
533
534 // insert MFLO
535 if (N->hasAnyUseOfValue(0)) {
Akira Hatanakadda4a072011-10-03 21:06:13 +0000536 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000537 InGlue);
538 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
539 InChain = CopyFromLo.getValue(1);
540 InGlue = CopyFromLo.getValue(2);
541 }
542
543 // insert MFHI
544 if (N->hasAnyUseOfValue(1)) {
545 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
Akira Hatanakadda4a072011-10-03 21:06:13 +0000546 HI, Ty, InGlue);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000547 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
548 }
549
550 return SDValue();
551}
552
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000553static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
554 switch (CC) {
555 default: llvm_unreachable("Unknown fp condition code!");
556 case ISD::SETEQ:
557 case ISD::SETOEQ: return Mips::FCOND_OEQ;
558 case ISD::SETUNE: return Mips::FCOND_UNE;
559 case ISD::SETLT:
560 case ISD::SETOLT: return Mips::FCOND_OLT;
561 case ISD::SETGT:
562 case ISD::SETOGT: return Mips::FCOND_OGT;
563 case ISD::SETLE:
564 case ISD::SETOLE: return Mips::FCOND_OLE;
565 case ISD::SETGE:
566 case ISD::SETOGE: return Mips::FCOND_OGE;
567 case ISD::SETULT: return Mips::FCOND_ULT;
568 case ISD::SETULE: return Mips::FCOND_ULE;
569 case ISD::SETUGT: return Mips::FCOND_UGT;
570 case ISD::SETUGE: return Mips::FCOND_UGE;
571 case ISD::SETUO: return Mips::FCOND_UN;
572 case ISD::SETO: return Mips::FCOND_OR;
573 case ISD::SETNE:
574 case ISD::SETONE: return Mips::FCOND_ONE;
575 case ISD::SETUEQ: return Mips::FCOND_UEQ;
576 }
577}
578
579
580// Returns true if condition code has to be inverted.
581static bool InvertFPCondCode(Mips::CondCode CC) {
582 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
583 return false;
584
Akira Hatanaka82099682011-12-19 19:52:25 +0000585 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
586 "Illegal Condition Code");
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000587
Akira Hatanaka82099682011-12-19 19:52:25 +0000588 return true;
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000589}
590
591// Creates and returns an FPCmp node from a setcc node.
592// Returns Op if setcc is not a floating point comparison.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000593static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) {
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000594 // must be a SETCC node
595 if (Op.getOpcode() != ISD::SETCC)
596 return Op;
597
598 SDValue LHS = Op.getOperand(0);
599
600 if (!LHS.getValueType().isFloatingPoint())
601 return Op;
602
603 SDValue RHS = Op.getOperand(1);
604 DebugLoc dl = Op.getDebugLoc();
605
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +0000606 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
607 // node if necessary.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000608 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
609
610 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
611 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
612}
613
614// Creates and returns a CMovFPT/F node.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000615static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000616 SDValue False, DebugLoc DL) {
617 bool invert = InvertFPCondCode((Mips::CondCode)
618 cast<ConstantSDNode>(Cond.getOperand(2))
619 ->getSExtValue());
620
621 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
622 True.getValueType(), True, False, Cond);
623}
624
Akira Hatanaka864f6602012-06-14 21:10:56 +0000625static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000626 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000627 const MipsSubtarget *Subtarget) {
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000628 if (DCI.isBeforeLegalizeOps())
629 return SDValue();
630
631 SDValue SetCC = N->getOperand(0);
632
633 if ((SetCC.getOpcode() != ISD::SETCC) ||
634 !SetCC.getOperand(0).getValueType().isInteger())
635 return SDValue();
636
637 SDValue False = N->getOperand(2);
638 EVT FalseTy = False.getValueType();
639
640 if (!FalseTy.isInteger())
641 return SDValue();
642
643 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
644
645 if (!CN || CN->getZExtValue())
646 return SDValue();
647
648 const DebugLoc DL = N->getDebugLoc();
649 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
650 SDValue True = N->getOperand(1);
Akira Hatanaka864f6602012-06-14 21:10:56 +0000651
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000652 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
653 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
Akira Hatanaka864f6602012-06-14 21:10:56 +0000654
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000655 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
656}
657
Akira Hatanaka864f6602012-06-14 21:10:56 +0000658static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG,
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000659 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000660 const MipsSubtarget *Subtarget) {
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000661 // Pattern match EXT.
662 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
663 // => ext $dst, $src, size, pos
Akira Hatanaka56633442011-09-20 23:53:09 +0000664 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000665 return SDValue();
666
667 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000668 unsigned ShiftRightOpc = ShiftRight.getOpcode();
669
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000670 // Op's first operand must be a shift right.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000671 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000672 return SDValue();
673
674 // The second operand of the shift must be an immediate.
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000675 ConstantSDNode *CN;
676 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
677 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000678
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000679 uint64_t Pos = CN->getZExtValue();
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000680 uint64_t SMPos, SMSize;
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000681
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000682 // Op's second operand must be a shifted mask.
683 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000684 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000685 return SDValue();
686
687 // Return if the shifted mask does not start at bit 0 or the sum of its size
688 // and Pos exceeds the word's size.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000689 EVT ValTy = N->getValueType(0);
690 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000691 return SDValue();
692
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000693 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy,
Akira Hatanaka82099682011-12-19 19:52:25 +0000694 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
Akira Hatanaka667645f2011-08-17 22:59:46 +0000695 DAG.getConstant(SMSize, MVT::i32));
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000696}
Jia Liubb481f82012-02-28 07:46:26 +0000697
Akira Hatanaka864f6602012-06-14 21:10:56 +0000698static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG,
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000699 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000700 const MipsSubtarget *Subtarget) {
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000701 // Pattern match INS.
702 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
Jia Liubb481f82012-02-28 07:46:26 +0000703 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000704 // => ins $dst, $src, size, pos, $src1
Akira Hatanaka56633442011-09-20 23:53:09 +0000705 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000706 return SDValue();
707
708 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
709 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
710 ConstantSDNode *CN;
711
712 // See if Op's first operand matches (and $src1 , mask0).
713 if (And0.getOpcode() != ISD::AND)
714 return SDValue();
715
716 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000717 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000718 return SDValue();
719
720 // See if Op's second operand matches (and (shl $src, pos), mask1).
721 if (And1.getOpcode() != ISD::AND)
722 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000723
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000724 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000725 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000726 return SDValue();
727
728 // The shift masks must have the same position and size.
729 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
730 return SDValue();
731
732 SDValue Shl = And1.getOperand(0);
733 if (Shl.getOpcode() != ISD::SHL)
734 return SDValue();
735
736 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
737 return SDValue();
738
739 unsigned Shamt = CN->getZExtValue();
740
741 // Return if the shift amount and the first bit position of mask are not the
Jia Liubb481f82012-02-28 07:46:26 +0000742 // same.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000743 EVT ValTy = N->getValueType(0);
744 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000745 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000746
Akira Hatanaka82099682011-12-19 19:52:25 +0000747 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0),
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000748 DAG.getConstant(SMPos0, MVT::i32),
Akira Hatanaka82099682011-12-19 19:52:25 +0000749 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000750}
Jia Liubb481f82012-02-28 07:46:26 +0000751
Akira Hatanaka864f6602012-06-14 21:10:56 +0000752static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG,
Akira Hatanaka87827072012-06-13 20:33:18 +0000753 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000754 const MipsSubtarget *Subtarget) {
Akira Hatanaka87827072012-06-13 20:33:18 +0000755 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
756
757 if (DCI.isBeforeLegalizeOps())
758 return SDValue();
759
760 SDValue Add = N->getOperand(1);
761
762 if (Add.getOpcode() != ISD::ADD)
763 return SDValue();
764
765 SDValue Lo = Add.getOperand(1);
766
767 if ((Lo.getOpcode() != MipsISD::Lo) ||
768 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
769 return SDValue();
770
771 EVT ValTy = N->getValueType(0);
772 DebugLoc DL = N->getDebugLoc();
773
774 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
775 Add.getOperand(0));
776 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
777}
778
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000779SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000780 const {
781 SelectionDAG &DAG = DCI.DAG;
782 unsigned opc = N->getOpcode();
783
784 switch (opc) {
785 default: break;
786 case ISD::ADDE:
787 return PerformADDECombine(N, DAG, DCI, Subtarget);
788 case ISD::SUBE:
789 return PerformSUBECombine(N, DAG, DCI, Subtarget);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000790 case ISD::SDIVREM:
791 case ISD::UDIVREM:
792 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000793 case ISD::SELECT:
Akira Hatanaka864f6602012-06-14 21:10:56 +0000794 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000795 case ISD::AND:
796 return PerformANDCombine(N, DAG, DCI, Subtarget);
797 case ISD::OR:
798 return PerformORCombine(N, DAG, DCI, Subtarget);
Akira Hatanaka87827072012-06-13 20:33:18 +0000799 case ISD::ADD:
800 return PerformADDCombine(N, DAG, DCI, Subtarget);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000801 }
802
803 return SDValue();
804}
805
Dan Gohman475871a2008-07-27 21:46:04 +0000806SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +0000807LowerOperation(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000808{
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000809 switch (Op.getOpcode())
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000810 {
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000811 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000812 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000813 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +0000814 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000815 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
816 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000817 case ISD::SELECT: return LowerSELECT(Op, DAG);
Akira Hatanaka3fef29d2012-07-11 19:32:27 +0000818 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
Akira Hatanaka0a40c232012-03-09 23:46:03 +0000819 case ISD::SETCC: return LowerSETCC(Op, DAG);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000820 case ISD::VASTART: return LowerVASTART(Op, DAG);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +0000821 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
Akira Hatanakac12a6e62012-04-11 22:49:04 +0000822 case ISD::FABS: return LowerFABS(Op, DAG);
Akira Hatanaka2e591472011-06-02 00:24:44 +0000823 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Akira Hatanakaba584fe2012-07-11 00:53:32 +0000824 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
Akira Hatanakadb548262011-07-19 23:30:50 +0000825 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
Eli Friedman14648462011-07-27 22:21:52 +0000826 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
Akira Hatanakaa284acb2012-05-09 00:55:21 +0000827 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
828 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, true);
829 case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false);
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +0000830 case ISD::LOAD: return LowerLOAD(Op, DAG);
831 case ISD::STORE: return LowerSTORE(Op, DAG);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000832 }
Dan Gohman475871a2008-07-27 21:46:04 +0000833 return SDValue();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000834}
835
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000836//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000837// Lower helper functions
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000838//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000839
840// AddLiveIn - This helper function adds the specified physical register to the
841// MachineFunction as a live in value. It also creates a corresponding
842// virtual register for it.
843static unsigned
Craig Topper44d23822012-02-22 05:59:10 +0000844AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000845{
846 assert(RC->contains(PReg) && "Not the correct regclass!");
Chris Lattner84bc5422007-12-31 04:13:23 +0000847 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
848 MF.getRegInfo().addLiveIn(PReg, VReg);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000849 return VReg;
850}
851
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000852// Get fp branch code (not opcode) from condition code.
853static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
854 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
855 return Mips::BRANCH_T;
856
Akira Hatanaka82099682011-12-19 19:52:25 +0000857 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
858 "Invalid CondCode.");
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000859
Akira Hatanaka82099682011-12-19 19:52:25 +0000860 return Mips::BRANCH_F;
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000861}
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000862
Akira Hatanaka8ae330a2011-10-17 18:53:29 +0000863/*
Akira Hatanaka14487d42011-06-07 19:28:39 +0000864static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
865 DebugLoc dl,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000866 const MipsSubtarget *Subtarget,
Akira Hatanaka14487d42011-06-07 19:28:39 +0000867 const TargetInstrInfo *TII,
868 bool isFPCmp, unsigned Opc) {
869 // There is no need to expand CMov instructions if target has
870 // conditional moves.
871 if (Subtarget->hasCondMov())
872 return BB;
873
874 // To "insert" a SELECT_CC instruction, we actually have to insert the
875 // diamond control-flow pattern. The incoming instruction knows the
876 // destination vreg to set, the condition code register to branch on, the
877 // true/false values to select between, and a branch opcode to use.
878 const BasicBlock *LLVM_BB = BB->getBasicBlock();
879 MachineFunction::iterator It = BB;
880 ++It;
881
882 // thisMBB:
883 // ...
884 // TrueVal = ...
885 // setcc r1, r2, r3
886 // bNE r1, r0, copy1MBB
887 // fallthrough --> copy0MBB
888 MachineBasicBlock *thisMBB = BB;
889 MachineFunction *F = BB->getParent();
890 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
891 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
892 F->insert(It, copy0MBB);
893 F->insert(It, sinkMBB);
894
895 // Transfer the remainder of BB and its successor edges to sinkMBB.
896 sinkMBB->splice(sinkMBB->begin(), BB,
897 llvm::next(MachineBasicBlock::iterator(MI)),
898 BB->end());
899 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
900
901 // Next, add the true and fallthrough blocks as its successors.
902 BB->addSuccessor(copy0MBB);
903 BB->addSuccessor(sinkMBB);
904
905 // Emit the right instruction according to the type of the operands compared
906 if (isFPCmp)
907 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
908 else
909 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
910 .addReg(Mips::ZERO).addMBB(sinkMBB);
911
912 // copy0MBB:
913 // %FalseValue = ...
914 // # fallthrough to sinkMBB
915 BB = copy0MBB;
916
917 // Update machine-CFG edges
918 BB->addSuccessor(sinkMBB);
919
920 // sinkMBB:
921 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
922 // ...
923 BB = sinkMBB;
924
925 if (isFPCmp)
926 BuildMI(*BB, BB->begin(), dl,
927 TII->get(Mips::PHI), MI->getOperand(0).getReg())
928 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
929 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
930 else
931 BuildMI(*BB, BB->begin(), dl,
932 TII->get(Mips::PHI), MI->getOperand(0).getReg())
933 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
934 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
935
936 MI->eraseFromParent(); // The pseudo instruction is gone now.
937 return BB;
938}
Akira Hatanaka8ae330a2011-10-17 18:53:29 +0000939*/
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000940MachineBasicBlock *
941MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
Dan Gohmanaf1d8ca2010-05-01 00:01:06 +0000942 MachineBasicBlock *BB) const {
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000943 switch (MI->getOpcode()) {
Craig Topperbc219812012-02-07 02:50:20 +0000944 default: llvm_unreachable("Unexpected instr type to insert");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000945 case Mips::ATOMIC_LOAD_ADD_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000946 case Mips::ATOMIC_LOAD_ADD_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000947 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
948 case Mips::ATOMIC_LOAD_ADD_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000949 case Mips::ATOMIC_LOAD_ADD_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000950 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
951 case Mips::ATOMIC_LOAD_ADD_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000952 case Mips::ATOMIC_LOAD_ADD_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000953 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
Akira Hatanaka59068062011-11-11 04:14:30 +0000954 case Mips::ATOMIC_LOAD_ADD_I64:
955 case Mips::ATOMIC_LOAD_ADD_I64_P8:
956 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000957
958 case Mips::ATOMIC_LOAD_AND_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000959 case Mips::ATOMIC_LOAD_AND_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000960 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
961 case Mips::ATOMIC_LOAD_AND_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000962 case Mips::ATOMIC_LOAD_AND_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000963 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
964 case Mips::ATOMIC_LOAD_AND_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000965 case Mips::ATOMIC_LOAD_AND_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000966 return EmitAtomicBinary(MI, BB, 4, Mips::AND);
Akira Hatanaka59068062011-11-11 04:14:30 +0000967 case Mips::ATOMIC_LOAD_AND_I64:
968 case Mips::ATOMIC_LOAD_AND_I64_P8:
Akira Hatanaka73866122011-11-12 02:38:12 +0000969 return EmitAtomicBinary(MI, BB, 8, Mips::AND64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000970
971 case Mips::ATOMIC_LOAD_OR_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000972 case Mips::ATOMIC_LOAD_OR_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000973 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
974 case Mips::ATOMIC_LOAD_OR_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000975 case Mips::ATOMIC_LOAD_OR_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000976 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
977 case Mips::ATOMIC_LOAD_OR_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000978 case Mips::ATOMIC_LOAD_OR_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000979 return EmitAtomicBinary(MI, BB, 4, Mips::OR);
Akira Hatanaka59068062011-11-11 04:14:30 +0000980 case Mips::ATOMIC_LOAD_OR_I64:
981 case Mips::ATOMIC_LOAD_OR_I64_P8:
982 return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000983
984 case Mips::ATOMIC_LOAD_XOR_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000985 case Mips::ATOMIC_LOAD_XOR_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000986 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
987 case Mips::ATOMIC_LOAD_XOR_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000988 case Mips::ATOMIC_LOAD_XOR_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000989 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
990 case Mips::ATOMIC_LOAD_XOR_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000991 case Mips::ATOMIC_LOAD_XOR_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000992 return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
Akira Hatanaka59068062011-11-11 04:14:30 +0000993 case Mips::ATOMIC_LOAD_XOR_I64:
994 case Mips::ATOMIC_LOAD_XOR_I64_P8:
995 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000996
997 case Mips::ATOMIC_LOAD_NAND_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000998 case Mips::ATOMIC_LOAD_NAND_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000999 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
1000 case Mips::ATOMIC_LOAD_NAND_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +00001001 case Mips::ATOMIC_LOAD_NAND_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001002 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
1003 case Mips::ATOMIC_LOAD_NAND_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +00001004 case Mips::ATOMIC_LOAD_NAND_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001005 return EmitAtomicBinary(MI, BB, 4, 0, true);
Akira Hatanaka59068062011-11-11 04:14:30 +00001006 case Mips::ATOMIC_LOAD_NAND_I64:
1007 case Mips::ATOMIC_LOAD_NAND_I64_P8:
1008 return EmitAtomicBinary(MI, BB, 8, 0, true);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001009
1010 case Mips::ATOMIC_LOAD_SUB_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +00001011 case Mips::ATOMIC_LOAD_SUB_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001012 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1013 case Mips::ATOMIC_LOAD_SUB_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +00001014 case Mips::ATOMIC_LOAD_SUB_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001015 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1016 case Mips::ATOMIC_LOAD_SUB_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +00001017 case Mips::ATOMIC_LOAD_SUB_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001018 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
Akira Hatanaka59068062011-11-11 04:14:30 +00001019 case Mips::ATOMIC_LOAD_SUB_I64:
1020 case Mips::ATOMIC_LOAD_SUB_I64_P8:
1021 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001022
1023 case Mips::ATOMIC_SWAP_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +00001024 case Mips::ATOMIC_SWAP_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001025 return EmitAtomicBinaryPartword(MI, BB, 1, 0);
1026 case Mips::ATOMIC_SWAP_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +00001027 case Mips::ATOMIC_SWAP_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001028 return EmitAtomicBinaryPartword(MI, BB, 2, 0);
1029 case Mips::ATOMIC_SWAP_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +00001030 case Mips::ATOMIC_SWAP_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001031 return EmitAtomicBinary(MI, BB, 4, 0);
Akira Hatanaka59068062011-11-11 04:14:30 +00001032 case Mips::ATOMIC_SWAP_I64:
1033 case Mips::ATOMIC_SWAP_I64_P8:
1034 return EmitAtomicBinary(MI, BB, 8, 0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001035
1036 case Mips::ATOMIC_CMP_SWAP_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +00001037 case Mips::ATOMIC_CMP_SWAP_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001038 return EmitAtomicCmpSwapPartword(MI, BB, 1);
1039 case Mips::ATOMIC_CMP_SWAP_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +00001040 case Mips::ATOMIC_CMP_SWAP_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001041 return EmitAtomicCmpSwapPartword(MI, BB, 2);
1042 case Mips::ATOMIC_CMP_SWAP_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +00001043 case Mips::ATOMIC_CMP_SWAP_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001044 return EmitAtomicCmpSwap(MI, BB, 4);
Akira Hatanaka59068062011-11-11 04:14:30 +00001045 case Mips::ATOMIC_CMP_SWAP_I64:
1046 case Mips::ATOMIC_CMP_SWAP_I64_P8:
1047 return EmitAtomicCmpSwap(MI, BB, 8);
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001048 }
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001049}
1050
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001051// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1052// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1053MachineBasicBlock *
1054MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
Eric Christopher471e4222011-06-08 23:55:35 +00001055 unsigned Size, unsigned BinOpcode,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001056 bool Nand) const {
Akira Hatanaka59068062011-11-11 04:14:30 +00001057 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001058
1059 MachineFunction *MF = BB->getParent();
1060 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Akira Hatanaka59068062011-11-11 04:14:30 +00001061 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001062 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1063 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001064 unsigned LL, SC, AND, NOR, ZERO, BEQ;
1065
1066 if (Size == 4) {
1067 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1068 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1069 AND = Mips::AND;
1070 NOR = Mips::NOR;
1071 ZERO = Mips::ZERO;
1072 BEQ = Mips::BEQ;
1073 }
1074 else {
1075 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1076 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1077 AND = Mips::AND64;
1078 NOR = Mips::NOR64;
1079 ZERO = Mips::ZERO_64;
1080 BEQ = Mips::BEQ64;
1081 }
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001082
Akira Hatanaka4061da12011-07-19 20:11:17 +00001083 unsigned OldVal = MI->getOperand(0).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001084 unsigned Ptr = MI->getOperand(1).getReg();
1085 unsigned Incr = MI->getOperand(2).getReg();
1086
Akira Hatanaka4061da12011-07-19 20:11:17 +00001087 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1088 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1089 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001090
1091 // insert new blocks after the current block
1092 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1093 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1094 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1095 MachineFunction::iterator It = BB;
1096 ++It;
1097 MF->insert(It, loopMBB);
1098 MF->insert(It, exitMBB);
1099
1100 // Transfer the remainder of BB and its successor edges to exitMBB.
1101 exitMBB->splice(exitMBB->begin(), BB,
1102 llvm::next(MachineBasicBlock::iterator(MI)),
1103 BB->end());
1104 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1105
1106 // thisMBB:
1107 // ...
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001108 // fallthrough --> loopMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001109 BB->addSuccessor(loopMBB);
Akira Hatanaka81b44112011-07-19 17:09:53 +00001110 loopMBB->addSuccessor(loopMBB);
1111 loopMBB->addSuccessor(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001112
1113 // loopMBB:
1114 // ll oldval, 0(ptr)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001115 // <binop> storeval, oldval, incr
1116 // sc success, storeval, 0(ptr)
1117 // beq success, $0, loopMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001118 BB = loopMBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001119 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001120 if (Nand) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001121 // and andres, oldval, incr
1122 // nor storeval, $0, andres
Akira Hatanaka59068062011-11-11 04:14:30 +00001123 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1124 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001125 } else if (BinOpcode) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001126 // <binop> storeval, oldval, incr
1127 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001128 } else {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001129 StoreVal = Incr;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001130 }
Akira Hatanaka59068062011-11-11 04:14:30 +00001131 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1132 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001133
1134 MI->eraseFromParent(); // The instruction is gone now.
1135
Akira Hatanaka939ece12011-07-19 03:42:13 +00001136 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001137}
1138
1139MachineBasicBlock *
1140MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001141 MachineBasicBlock *BB,
1142 unsigned Size, unsigned BinOpcode,
1143 bool Nand) const {
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001144 assert((Size == 1 || Size == 2) &&
1145 "Unsupported size for EmitAtomicBinaryPartial.");
1146
1147 MachineFunction *MF = BB->getParent();
1148 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1149 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1150 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1151 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001152 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1153 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001154
1155 unsigned Dest = MI->getOperand(0).getReg();
1156 unsigned Ptr = MI->getOperand(1).getReg();
1157 unsigned Incr = MI->getOperand(2).getReg();
1158
Akira Hatanaka4061da12011-07-19 20:11:17 +00001159 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1160 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001161 unsigned Mask = RegInfo.createVirtualRegister(RC);
1162 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001163 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1164 unsigned OldVal = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001165 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001166 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1167 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1168 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1169 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1170 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001171 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001172 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1173 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1174 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1175 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1176 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001177
1178 // insert new blocks after the current block
1179 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1180 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001181 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001182 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1183 MachineFunction::iterator It = BB;
1184 ++It;
1185 MF->insert(It, loopMBB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001186 MF->insert(It, sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001187 MF->insert(It, exitMBB);
1188
1189 // Transfer the remainder of BB and its successor edges to exitMBB.
1190 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001191 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001192 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1193
Akira Hatanaka81b44112011-07-19 17:09:53 +00001194 BB->addSuccessor(loopMBB);
1195 loopMBB->addSuccessor(loopMBB);
1196 loopMBB->addSuccessor(sinkMBB);
1197 sinkMBB->addSuccessor(exitMBB);
1198
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001199 // thisMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001200 // addiu masklsb2,$0,-4 # 0xfffffffc
1201 // and alignedaddr,ptr,masklsb2
1202 // andi ptrlsb2,ptr,3
1203 // sll shiftamt,ptrlsb2,3
1204 // ori maskupper,$0,255 # 0xff
1205 // sll mask,maskupper,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001206 // nor mask2,$0,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001207 // sll incr2,incr,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001208
1209 int64_t MaskImm = (Size == 1) ? 255 : 65535;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001210 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1211 .addReg(Mips::ZERO).addImm(-4);
1212 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1213 .addReg(Ptr).addReg(MaskLSB2);
1214 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1215 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1216 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1217 .addReg(Mips::ZERO).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001218 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1219 .addReg(ShiftAmt).addReg(MaskUpper);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001220 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001221 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
Bruno Cardoso Lopescada2d02011-05-31 20:25:26 +00001222
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001223 // atomic.load.binop
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001224 // loopMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001225 // ll oldval,0(alignedaddr)
1226 // binop binopres,oldval,incr2
1227 // and newval,binopres,mask
1228 // and maskedoldval0,oldval,mask2
1229 // or storeval,maskedoldval0,newval
1230 // sc success,storeval,0(alignedaddr)
1231 // beq success,$0,loopMBB
1232
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001233 // atomic.swap
1234 // loopMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001235 // ll oldval,0(alignedaddr)
Akira Hatanaka70564a92011-07-19 18:14:26 +00001236 // and newval,incr2,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001237 // and maskedoldval0,oldval,mask2
1238 // or storeval,maskedoldval0,newval
1239 // sc success,storeval,0(alignedaddr)
1240 // beq success,$0,loopMBB
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001241
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001242 BB = loopMBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001243 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001244 if (Nand) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001245 // and andres, oldval, incr2
1246 // nor binopres, $0, andres
1247 // and newval, binopres, mask
1248 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1249 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
1250 .addReg(Mips::ZERO).addReg(AndRes);
1251 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001252 } else if (BinOpcode) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001253 // <binop> binopres, oldval, incr2
1254 // and newval, binopres, mask
1255 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1256 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
Akira Hatanaka70564a92011-07-19 18:14:26 +00001257 } else {// atomic.swap
Akira Hatanaka4061da12011-07-19 20:11:17 +00001258 // and newval, incr2, mask
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001259 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
Akira Hatanaka70564a92011-07-19 18:14:26 +00001260 }
Jia Liubb481f82012-02-28 07:46:26 +00001261
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001262 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001263 .addReg(OldVal).addReg(Mask2);
1264 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001265 .addReg(MaskedOldVal0).addReg(NewVal);
Akira Hatanaka59068062011-11-11 04:14:30 +00001266 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001267 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001268 BuildMI(BB, dl, TII->get(Mips::BEQ))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001269 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001270
Akira Hatanaka939ece12011-07-19 03:42:13 +00001271 // sinkMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001272 // and maskedoldval1,oldval,mask
1273 // srl srlres,maskedoldval1,shiftamt
1274 // sll sllres,srlres,24
1275 // sra dest,sllres,24
Akira Hatanaka939ece12011-07-19 03:42:13 +00001276 BB = sinkMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001277 int64_t ShiftImm = (Size == 1) ? 24 : 16;
Akira Hatanakaa308c672011-07-19 03:14:58 +00001278
Akira Hatanaka4061da12011-07-19 20:11:17 +00001279 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1280 .addReg(OldVal).addReg(Mask);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001281 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1282 .addReg(ShiftAmt).addReg(MaskedOldVal1);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001283 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1284 .addReg(SrlRes).addImm(ShiftImm);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001285 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001286 .addReg(SllRes).addImm(ShiftImm);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001287
1288 MI->eraseFromParent(); // The instruction is gone now.
1289
Akira Hatanaka939ece12011-07-19 03:42:13 +00001290 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001291}
1292
1293MachineBasicBlock *
1294MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001295 MachineBasicBlock *BB,
1296 unsigned Size) const {
Akira Hatanaka59068062011-11-11 04:14:30 +00001297 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001298
1299 MachineFunction *MF = BB->getParent();
1300 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Akira Hatanaka59068062011-11-11 04:14:30 +00001301 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001302 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1303 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001304 unsigned LL, SC, ZERO, BNE, BEQ;
1305
1306 if (Size == 4) {
1307 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1308 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1309 ZERO = Mips::ZERO;
1310 BNE = Mips::BNE;
1311 BEQ = Mips::BEQ;
1312 }
1313 else {
1314 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1315 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1316 ZERO = Mips::ZERO_64;
1317 BNE = Mips::BNE64;
1318 BEQ = Mips::BEQ64;
1319 }
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001320
1321 unsigned Dest = MI->getOperand(0).getReg();
1322 unsigned Ptr = MI->getOperand(1).getReg();
Akira Hatanaka4061da12011-07-19 20:11:17 +00001323 unsigned OldVal = MI->getOperand(2).getReg();
1324 unsigned NewVal = MI->getOperand(3).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001325
Akira Hatanaka4061da12011-07-19 20:11:17 +00001326 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001327
1328 // insert new blocks after the current block
1329 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1330 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1331 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1332 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1333 MachineFunction::iterator It = BB;
1334 ++It;
1335 MF->insert(It, loop1MBB);
1336 MF->insert(It, loop2MBB);
1337 MF->insert(It, exitMBB);
1338
1339 // Transfer the remainder of BB and its successor edges to exitMBB.
1340 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001341 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001342 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1343
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001344 // thisMBB:
1345 // ...
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001346 // fallthrough --> loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001347 BB->addSuccessor(loop1MBB);
Akira Hatanaka81b44112011-07-19 17:09:53 +00001348 loop1MBB->addSuccessor(exitMBB);
1349 loop1MBB->addSuccessor(loop2MBB);
1350 loop2MBB->addSuccessor(loop1MBB);
1351 loop2MBB->addSuccessor(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001352
1353 // loop1MBB:
1354 // ll dest, 0(ptr)
1355 // bne dest, oldval, exitMBB
1356 BB = loop1MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001357 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1358 BuildMI(BB, dl, TII->get(BNE))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001359 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001360
1361 // loop2MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001362 // sc success, newval, 0(ptr)
1363 // beq success, $0, loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001364 BB = loop2MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001365 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001366 .addReg(NewVal).addReg(Ptr).addImm(0);
Akira Hatanaka59068062011-11-11 04:14:30 +00001367 BuildMI(BB, dl, TII->get(BEQ))
1368 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001369
1370 MI->eraseFromParent(); // The instruction is gone now.
1371
Akira Hatanaka939ece12011-07-19 03:42:13 +00001372 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001373}
1374
1375MachineBasicBlock *
1376MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001377 MachineBasicBlock *BB,
1378 unsigned Size) const {
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001379 assert((Size == 1 || Size == 2) &&
1380 "Unsupported size for EmitAtomicCmpSwapPartial.");
1381
1382 MachineFunction *MF = BB->getParent();
1383 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1384 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1385 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1386 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001387 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1388 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001389
1390 unsigned Dest = MI->getOperand(0).getReg();
1391 unsigned Ptr = MI->getOperand(1).getReg();
Akira Hatanaka4061da12011-07-19 20:11:17 +00001392 unsigned CmpVal = MI->getOperand(2).getReg();
1393 unsigned NewVal = MI->getOperand(3).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001394
Akira Hatanaka4061da12011-07-19 20:11:17 +00001395 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1396 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001397 unsigned Mask = RegInfo.createVirtualRegister(RC);
1398 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001399 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1400 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1401 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1402 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1403 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1404 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1405 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1406 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1407 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1408 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1409 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1410 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1411 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1412 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001413
1414 // insert new blocks after the current block
1415 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1416 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1417 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001418 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001419 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1420 MachineFunction::iterator It = BB;
1421 ++It;
1422 MF->insert(It, loop1MBB);
1423 MF->insert(It, loop2MBB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001424 MF->insert(It, sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001425 MF->insert(It, exitMBB);
1426
1427 // Transfer the remainder of BB and its successor edges to exitMBB.
1428 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001429 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001430 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1431
Akira Hatanaka81b44112011-07-19 17:09:53 +00001432 BB->addSuccessor(loop1MBB);
1433 loop1MBB->addSuccessor(sinkMBB);
1434 loop1MBB->addSuccessor(loop2MBB);
1435 loop2MBB->addSuccessor(loop1MBB);
1436 loop2MBB->addSuccessor(sinkMBB);
1437 sinkMBB->addSuccessor(exitMBB);
1438
Akira Hatanaka70564a92011-07-19 18:14:26 +00001439 // FIXME: computation of newval2 can be moved to loop2MBB.
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001440 // thisMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001441 // addiu masklsb2,$0,-4 # 0xfffffffc
1442 // and alignedaddr,ptr,masklsb2
1443 // andi ptrlsb2,ptr,3
1444 // sll shiftamt,ptrlsb2,3
1445 // ori maskupper,$0,255 # 0xff
1446 // sll mask,maskupper,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001447 // nor mask2,$0,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001448 // andi maskedcmpval,cmpval,255
1449 // sll shiftedcmpval,maskedcmpval,shiftamt
1450 // andi maskednewval,newval,255
1451 // sll shiftednewval,maskednewval,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001452 int64_t MaskImm = (Size == 1) ? 255 : 65535;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001453 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1454 .addReg(Mips::ZERO).addImm(-4);
1455 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1456 .addReg(Ptr).addReg(MaskLSB2);
1457 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1458 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1459 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1460 .addReg(Mips::ZERO).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001461 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1462 .addReg(ShiftAmt).addReg(MaskUpper);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001463 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001464 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
1465 .addReg(CmpVal).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001466 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
1467 .addReg(ShiftAmt).addReg(MaskedCmpVal);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001468 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
1469 .addReg(NewVal).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001470 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
1471 .addReg(ShiftAmt).addReg(MaskedNewVal);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001472
1473 // loop1MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001474 // ll oldval,0(alginedaddr)
1475 // and maskedoldval0,oldval,mask
1476 // bne maskedoldval0,shiftedcmpval,sinkMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001477 BB = loop1MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001478 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001479 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1480 .addReg(OldVal).addReg(Mask);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001481 BuildMI(BB, dl, TII->get(Mips::BNE))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001482 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001483
1484 // loop2MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001485 // and maskedoldval1,oldval,mask2
1486 // or storeval,maskedoldval1,shiftednewval
1487 // sc success,storeval,0(alignedaddr)
1488 // beq success,$0,loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001489 BB = loop2MBB;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001490 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1491 .addReg(OldVal).addReg(Mask2);
1492 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1493 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
Akira Hatanaka59068062011-11-11 04:14:30 +00001494 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001495 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001496 BuildMI(BB, dl, TII->get(Mips::BEQ))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001497 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001498
Akira Hatanaka939ece12011-07-19 03:42:13 +00001499 // sinkMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001500 // srl srlres,maskedoldval0,shiftamt
1501 // sll sllres,srlres,24
1502 // sra dest,sllres,24
Akira Hatanaka939ece12011-07-19 03:42:13 +00001503 BB = sinkMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001504 int64_t ShiftImm = (Size == 1) ? 24 : 16;
Akira Hatanakaa308c672011-07-19 03:14:58 +00001505
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001506 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1507 .addReg(ShiftAmt).addReg(MaskedOldVal0);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001508 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1509 .addReg(SrlRes).addImm(ShiftImm);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001510 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001511 .addReg(SllRes).addImm(ShiftImm);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001512
1513 MI->eraseFromParent(); // The instruction is gone now.
1514
Akira Hatanaka939ece12011-07-19 03:42:13 +00001515 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001516}
1517
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001518//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001519// Misc Lower Operation implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001520//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesd3bdf192009-05-27 17:23:44 +00001521SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001522LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001523{
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001524 // The first operand is the chain, the second is the condition, the third is
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001525 // the block to branch to if the condition is true.
1526 SDValue Chain = Op.getOperand(0);
1527 SDValue Dest = Op.getOperand(2);
Dale Johannesende064702009-02-06 21:50:26 +00001528 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001529
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001530 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
1531
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001532 // Return if flag is not set by a floating point comparison.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001533 if (CondRes.getOpcode() != MipsISD::FPCmp)
Bruno Cardoso Lopes4b877ca2008-07-30 17:06:13 +00001534 return Op;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001535
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +00001536 SDValue CCNode = CondRes.getOperand(2);
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001537 Mips::CondCode CC =
1538 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001539 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001540
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001541 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001542 Dest, CondRes);
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001543}
1544
1545SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001546LowerSELECT(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001547{
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001548 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001549
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001550 // Return if flag is not set by a floating point comparison.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001551 if (Cond.getOpcode() != MipsISD::FPCmp)
1552 return Op;
Bruno Cardoso Lopes739e4412008-08-13 07:13:40 +00001553
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001554 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1555 Op.getDebugLoc());
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001556}
1557
Akira Hatanaka3fef29d2012-07-11 19:32:27 +00001558SDValue MipsTargetLowering::
1559LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1560{
1561 DebugLoc DL = Op.getDebugLoc();
1562 EVT Ty = Op.getOperand(0).getValueType();
1563 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty),
1564 Op.getOperand(0), Op.getOperand(1),
1565 Op.getOperand(4));
1566
1567 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1568 Op.getOperand(3));
1569}
1570
Akira Hatanaka0a40c232012-03-09 23:46:03 +00001571SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1572 SDValue Cond = CreateFPCmp(DAG, Op);
1573
1574 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1575 "Floating point operand expected.");
1576
1577 SDValue True = DAG.getConstant(1, MVT::i32);
1578 SDValue False = DAG.getConstant(0, MVT::i32);
1579
1580 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc());
1581}
1582
Dan Gohmand858e902010-04-17 15:26:15 +00001583SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
1584 SelectionDAG &DAG) const {
Dale Johannesende064702009-02-06 21:50:26 +00001585 // FIXME there isn't actually debug info here
Dale Johannesen33c960f2009-02-04 20:06:27 +00001586 DebugLoc dl = Op.getDebugLoc();
Jia Liubb481f82012-02-28 07:46:26 +00001587 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001588
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001589 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Chris Lattnere3736f82009-08-13 05:41:27 +00001590 SDVTList VTs = DAG.getVTList(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001591
Akira Hatanakaafc945b2012-09-12 23:27:55 +00001592 const MipsTargetObjectFile &TLOF =
1593 (const MipsTargetObjectFile&)getObjFileLowering();
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001594
Chris Lattnere3736f82009-08-13 05:41:27 +00001595 // %gp_rel relocation
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001596 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1597 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00001598 MipsII::MO_GPREL);
Chris Lattnere3736f82009-08-13 05:41:27 +00001599 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
Akira Hatanakae7338cd2012-08-22 03:18:13 +00001600 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
1601 return DAG.getNode(ISD::ADD, dl, MVT::i32, GPReg, GPRelNode);
Chris Lattnere3736f82009-08-13 05:41:27 +00001602 }
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001603 // %hi/%lo relocation
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001604 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1605 MipsII::MO_ABS_HI);
1606 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1607 MipsII::MO_ABS_LO);
1608 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
1609 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
Owen Anderson825b72b2009-08-11 20:47:22 +00001610 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001611 }
1612
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001613 EVT ValTy = Op.getValueType();
1614 bool HasGotOfst = (GV->hasInternalLinkage() ||
1615 (GV->hasLocalLinkage() && !isa<Function>(GV)));
Akira Hatanaka56ce6b32012-04-04 22:16:36 +00001616 unsigned GotFlag = HasMips64 ?
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001617 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) :
Bruno Cardoso Lopese3d35722011-12-07 00:28:57 +00001618 (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16);
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001619 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001620 GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), GA);
Akira Hatanaka82099682011-12-19 19:52:25 +00001621 SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA,
1622 MachinePointerInfo(), false, false, false, 0);
Akira Hatanaka0f843822011-06-07 18:58:42 +00001623 // On functions and global targets not internal linked only
1624 // a load from got/GP is necessary for PIC to work.
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001625 if (!HasGotOfst)
Akira Hatanaka0f843822011-06-07 18:58:42 +00001626 return ResNode;
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001627 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0,
Akira Hatanaka56ce6b32012-04-04 22:16:36 +00001628 HasMips64 ? MipsII::MO_GOT_OFST :
1629 MipsII::MO_ABS_LO);
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001630 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo);
1631 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001632}
1633
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001634SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
1635 SelectionDAG &DAG) const {
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001636 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1637 // FIXME there isn't actually debug info here
1638 DebugLoc dl = Op.getDebugLoc();
1639
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001640 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001641 // %hi/%lo relocation
Michael Liao6c7ccaa2012-09-12 21:43:09 +00001642 SDValue BAHi = DAG.getTargetBlockAddress(BA, MVT::i32, 0, MipsII::MO_ABS_HI);
1643 SDValue BALo = DAG.getTargetBlockAddress(BA, MVT::i32, 0, MipsII::MO_ABS_LO);
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001644 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
1645 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
1646 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001647 }
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001648
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001649 EVT ValTy = Op.getValueType();
Akira Hatanaka03d830e2012-04-04 18:22:53 +00001650 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1651 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Michael Liao6c7ccaa2012-09-12 21:43:09 +00001652 SDValue BAGOTOffset = DAG.getTargetBlockAddress(BA, ValTy, 0, GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001653 BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy,
1654 GetGlobalReg(DAG, ValTy), BAGOTOffset);
Michael Liao6c7ccaa2012-09-12 21:43:09 +00001655 SDValue BALOOffset = DAG.getTargetBlockAddress(BA, ValTy, 0, OFSTFlag);
Akira Hatanaka82099682011-12-19 19:52:25 +00001656 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset,
Pete Cooperd752e0f2011-11-08 18:42:53 +00001657 MachinePointerInfo(), false, false, false, 0);
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001658 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset);
1659 return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001660}
1661
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001662SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001663LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001664{
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001665 // If the relocation model is PIC, use the General Dynamic TLS Model or
1666 // Local Dynamic TLS model, otherwise use the Initial Exec or
1667 // Local Exec TLS Model.
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001668
1669 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1670 DebugLoc dl = GA->getDebugLoc();
1671 const GlobalValue *GV = GA->getGlobal();
1672 EVT PtrVT = getPointerTy();
1673
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001674 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1675
1676 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
Hans Wennborg70a07c72012-06-04 14:02:08 +00001677 // General Dynamic and Local Dynamic TLS Model.
1678 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1679 : MipsII::MO_TLSGD;
1680
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001681 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001682 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT,
1683 GetGlobalReg(DAG, PtrVT), TGA);
Akira Hatanaka7a7194b2011-12-08 21:05:38 +00001684 unsigned PtrSize = PtrVT.getSizeInBits();
1685 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1686
Benjamin Kramer5eccf672011-12-11 12:21:34 +00001687 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001688
1689 ArgListTy Args;
1690 ArgListEntry Entry;
1691 Entry.Node = Argument;
Akira Hatanakaca074792011-12-08 20:34:32 +00001692 Entry.Ty = PtrTy;
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001693 Args.push_back(Entry);
Jia Liubb481f82012-02-28 07:46:26 +00001694
Justin Holewinskid2ea0e12012-05-25 16:35:28 +00001695 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
Evan Cheng4bfcd4a2012-02-28 18:51:51 +00001696 false, false, false, false, 0, CallingConv::C,
1697 /*isTailCall=*/false, /*doesNotRet=*/false,
1698 /*isReturnValueUsed=*/true,
Akira Hatanaka7a7194b2011-12-08 21:05:38 +00001699 TlsGetAddr, Args, DAG, dl);
Justin Holewinskid2ea0e12012-05-25 16:35:28 +00001700 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001701
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001702 SDValue Ret = CallResult.first;
1703
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001704 if (model != TLSModel::LocalDynamic)
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001705 return Ret;
1706
1707 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1708 MipsII::MO_DTPREL_HI);
1709 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1710 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1711 MipsII::MO_DTPREL_LO);
1712 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1713 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret);
1714 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001715 }
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001716
1717 SDValue Offset;
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001718 if (model == TLSModel::InitialExec) {
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001719 // Initial Exec TLS Model
Akira Hatanakaca074792011-12-08 20:34:32 +00001720 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001721 MipsII::MO_GOTTPREL);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001722 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1723 TGA);
Akira Hatanakaca074792011-12-08 20:34:32 +00001724 Offset = DAG.getLoad(PtrVT, dl,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001725 DAG.getEntryNode(), TGA, MachinePointerInfo(),
Pete Cooperd752e0f2011-11-08 18:42:53 +00001726 false, false, false, 0);
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001727 } else {
1728 // Local Exec TLS Model
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001729 assert(model == TLSModel::LocalExec);
Akira Hatanakaca074792011-12-08 20:34:32 +00001730 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001731 MipsII::MO_TPREL_HI);
Akira Hatanakaca074792011-12-08 20:34:32 +00001732 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001733 MipsII::MO_TPREL_LO);
Akira Hatanakaca074792011-12-08 20:34:32 +00001734 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1735 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1736 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001737 }
1738
1739 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
1740 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001741}
1742
1743SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001744LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001745{
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001746 SDValue HiPart, JTI, JTILo;
Dale Johannesende064702009-02-06 21:50:26 +00001747 // FIXME there isn't actually debug info here
Dale Johannesen33c960f2009-02-04 20:06:27 +00001748 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00001749 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Owen Andersone50ed302009-08-10 22:56:29 +00001750 EVT PtrVT = Op.getValueType();
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001751 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001752
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001753 if (!IsPIC && !IsN64) {
1754 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI);
1755 HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI);
1756 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO);
Akira Hatanaka342837d2011-05-28 01:07:07 +00001757 } else {// Emit Load from Global Pointer
Akira Hatanakac75ceb72012-04-04 18:31:32 +00001758 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1759 unsigned OfstFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001760 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001761 JTI = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1762 JTI);
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001763 HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI,
1764 MachinePointerInfo(), false, false, false, 0);
1765 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag);
Akira Hatanaka342837d2011-05-28 01:07:07 +00001766 }
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001767
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001768 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo);
1769 return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo);
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001770}
1771
Dan Gohman475871a2008-07-27 21:46:04 +00001772SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001773LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +00001774{
Dan Gohman475871a2008-07-27 21:46:04 +00001775 SDValue ResNode;
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001776 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
Dan Gohman46510a72010-04-15 01:51:59 +00001777 const Constant *C = N->getConstVal();
Dale Johannesende064702009-02-06 21:50:26 +00001778 // FIXME there isn't actually debug info here
1779 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001780
1781 // gp_rel relocation
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001782 // FIXME: we should reference the constant pool using small data sections,
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001783 // but the asm printer currently doesn't support this feature without
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001784 // hacking it. This feature should come soon so we can uncomment the
Bruno Cardoso Lopesf33bc432008-07-28 19:26:25 +00001785 // stuff below.
Eli Friedmane2c74082009-08-03 02:22:28 +00001786 //if (IsInSmallSection(C->getType())) {
Owen Anderson825b72b2009-08-11 20:47:22 +00001787 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1788 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001789 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001790
Akira Hatanaka13daee32012-03-27 02:55:31 +00001791 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001792 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001793 N->getOffset(), MipsII::MO_ABS_HI);
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001794 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001795 N->getOffset(), MipsII::MO_ABS_LO);
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001796 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
1797 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
Owen Anderson825b72b2009-08-11 20:47:22 +00001798 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001799 } else {
Akira Hatanaka620db892011-11-16 22:44:38 +00001800 EVT ValTy = Op.getValueType();
Akira Hatanaka86a27332012-04-04 18:26:12 +00001801 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1802 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Akira Hatanaka620db892011-11-16 22:44:38 +00001803 SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1804 N->getOffset(), GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001805 CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), CP);
Akira Hatanaka82099682011-12-19 19:52:25 +00001806 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP,
1807 MachinePointerInfo::getConstantPool(), false,
1808 false, false, 0);
Akira Hatanaka620db892011-11-16 22:44:38 +00001809 SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1810 N->getOffset(), OFSTFlag);
1811 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo);
1812 ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001813 }
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001814
1815 return ResNode;
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +00001816}
1817
Dan Gohmand858e902010-04-17 15:26:15 +00001818SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
Dan Gohman1e93df62010-04-17 14:41:14 +00001819 MachineFunction &MF = DAG.getMachineFunction();
1820 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1821
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001822 DebugLoc dl = Op.getDebugLoc();
Dan Gohman1e93df62010-04-17 14:41:14 +00001823 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1824 getPointerTy());
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001825
1826 // vastart just stores the address of the VarArgsFrameIndex slot into the
1827 // memory location argument.
1828 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Chris Lattner8026a9d2010-09-21 17:50:43 +00001829 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
Akira Hatanaka82099682011-12-19 19:52:25 +00001830 MachinePointerInfo(SV), false, false, 0);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001831}
Jia Liubb481f82012-02-28 07:46:26 +00001832
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001833static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1834 EVT TyX = Op.getOperand(0).getValueType();
1835 EVT TyY = Op.getOperand(1).getValueType();
1836 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1837 SDValue Const31 = DAG.getConstant(31, MVT::i32);
1838 DebugLoc DL = Op.getDebugLoc();
1839 SDValue Res;
1840
1841 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1842 // to i32.
1843 SDValue X = (TyX == MVT::f32) ?
1844 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1845 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1846 Const1);
1847 SDValue Y = (TyY == MVT::f32) ?
1848 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1849 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1850 Const1);
1851
1852 if (HasR2) {
1853 // ext E, Y, 31, 1 ; extract bit31 of Y
1854 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1855 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1856 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1857 } else {
1858 // sll SllX, X, 1
1859 // srl SrlX, SllX, 1
1860 // srl SrlY, Y, 31
1861 // sll SllY, SrlX, 31
1862 // or Or, SrlX, SllY
1863 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1864 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1865 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1866 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1867 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1868 }
1869
1870 if (TyX == MVT::f32)
1871 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1872
1873 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1874 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1875 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001876}
1877
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001878static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1879 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1880 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1881 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1882 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1883 DebugLoc DL = Op.getDebugLoc();
Eric Christopher471e4222011-06-08 23:55:35 +00001884
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001885 // Bitcast to integer nodes.
1886 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1887 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001888
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001889 if (HasR2) {
1890 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1891 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1892 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1893 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001894
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001895 if (WidthX > WidthY)
1896 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1897 else if (WidthY > WidthX)
1898 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001899
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001900 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1901 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
1902 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1903 }
1904
1905 // (d)sll SllX, X, 1
1906 // (d)srl SrlX, SllX, 1
1907 // (d)srl SrlY, Y, width(Y)-1
1908 // (d)sll SllY, SrlX, width(Y)-1
1909 // or Or, SrlX, SllY
1910 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1911 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1912 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1913 DAG.getConstant(WidthY - 1, MVT::i32));
1914
1915 if (WidthX > WidthY)
1916 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1917 else if (WidthY > WidthX)
1918 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1919
1920 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1921 DAG.getConstant(WidthX - 1, MVT::i32));
1922 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1923 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001924}
1925
Akira Hatanaka82099682011-12-19 19:52:25 +00001926SDValue
1927MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001928 if (Subtarget->hasMips64())
1929 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001930
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001931 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001932}
1933
Akira Hatanakac12a6e62012-04-11 22:49:04 +00001934static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1935 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1936 DebugLoc DL = Op.getDebugLoc();
1937
1938 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1939 // to i32.
1940 SDValue X = (Op.getValueType() == MVT::f32) ?
1941 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1942 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1943 Const1);
1944
1945 // Clear MSB.
1946 if (HasR2)
1947 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
1948 DAG.getRegister(Mips::ZERO, MVT::i32),
1949 DAG.getConstant(31, MVT::i32), Const1, X);
1950 else {
1951 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1952 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1953 }
1954
1955 if (Op.getValueType() == MVT::f32)
1956 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
1957
1958 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1959 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1960 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1961}
1962
1963static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1964 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1965 DebugLoc DL = Op.getDebugLoc();
1966
1967 // Bitcast to integer node.
1968 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
1969
1970 // Clear MSB.
1971 if (HasR2)
1972 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
1973 DAG.getRegister(Mips::ZERO_64, MVT::i64),
1974 DAG.getConstant(63, MVT::i32), Const1, X);
1975 else {
1976 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
1977 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
1978 }
1979
1980 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
1981}
1982
1983SDValue
1984MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
1985 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
1986 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2());
1987
1988 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2());
1989}
1990
Akira Hatanaka2e591472011-06-02 00:24:44 +00001991SDValue MipsTargetLowering::
1992LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
Bruno Cardoso Lopese0b5cfc2011-06-16 00:40:02 +00001993 // check the depth
1994 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
Akira Hatanaka0f843822011-06-07 18:58:42 +00001995 "Frame address can only be determined for current frame.");
Akira Hatanaka2e591472011-06-02 00:24:44 +00001996
1997 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1998 MFI->setFrameAddressIsTaken(true);
1999 EVT VT = Op.getValueType();
2000 DebugLoc dl = Op.getDebugLoc();
Akira Hatanaka46ac4392011-11-11 04:11:56 +00002001 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2002 IsN64 ? Mips::FP_64 : Mips::FP, VT);
Akira Hatanaka2e591472011-06-02 00:24:44 +00002003 return FrameAddr;
2004}
2005
Akira Hatanakaba584fe2012-07-11 00:53:32 +00002006SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op,
2007 SelectionDAG &DAG) const {
2008 // check the depth
2009 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2010 "Return address can be determined only for current frame.");
2011
2012 MachineFunction &MF = DAG.getMachineFunction();
2013 MachineFrameInfo *MFI = MF.getFrameInfo();
2014 EVT VT = Op.getValueType();
2015 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
2016 MFI->setReturnAddressIsTaken(true);
2017
2018 // Return RA, which contains the return address. Mark it an implicit live-in.
2019 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2020 return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT);
2021}
2022
Akira Hatanakadb548262011-07-19 23:30:50 +00002023// TODO: set SType according to the desired memory barrier behavior.
Akira Hatanaka82099682011-12-19 19:52:25 +00002024SDValue
Akira Hatanaka864f6602012-06-14 21:10:56 +00002025MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const {
Akira Hatanakadb548262011-07-19 23:30:50 +00002026 unsigned SType = 0;
2027 DebugLoc dl = Op.getDebugLoc();
2028 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2029 DAG.getConstant(SType, MVT::i32));
2030}
2031
Eli Friedman14648462011-07-27 22:21:52 +00002032SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002033 SelectionDAG &DAG) const {
Eli Friedman14648462011-07-27 22:21:52 +00002034 // FIXME: Need pseudo-fence for 'singlethread' fences
2035 // FIXME: Set SType for weaker fences where supported/appropriate.
2036 unsigned SType = 0;
2037 DebugLoc dl = Op.getDebugLoc();
2038 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2039 DAG.getConstant(SType, MVT::i32));
2040}
2041
Akira Hatanakaa284acb2012-05-09 00:55:21 +00002042SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002043 SelectionDAG &DAG) const {
Akira Hatanakaa284acb2012-05-09 00:55:21 +00002044 DebugLoc DL = Op.getDebugLoc();
2045 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2046 SDValue Shamt = Op.getOperand(2);
2047
2048 // if shamt < 32:
2049 // lo = (shl lo, shamt)
2050 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2051 // else:
2052 // lo = 0
2053 // hi = (shl lo, shamt[4:0])
2054 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2055 DAG.getConstant(-1, MVT::i32));
2056 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
2057 DAG.getConstant(1, MVT::i32));
2058 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
2059 Not);
2060 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
2061 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2062 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
2063 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2064 DAG.getConstant(0x20, MVT::i32));
Akira Hatanaka864f6602012-06-14 21:10:56 +00002065 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2066 DAG.getConstant(0, MVT::i32), ShiftLeftLo);
Akira Hatanakaa284acb2012-05-09 00:55:21 +00002067 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
2068
2069 SDValue Ops[2] = {Lo, Hi};
2070 return DAG.getMergeValues(Ops, 2, DL);
2071}
2072
Akira Hatanaka864f6602012-06-14 21:10:56 +00002073SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
Akira Hatanakaa284acb2012-05-09 00:55:21 +00002074 bool IsSRA) const {
2075 DebugLoc DL = Op.getDebugLoc();
2076 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2077 SDValue Shamt = Op.getOperand(2);
2078
2079 // if shamt < 32:
2080 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2081 // if isSRA:
2082 // hi = (sra hi, shamt)
2083 // else:
2084 // hi = (srl hi, shamt)
2085 // else:
2086 // if isSRA:
2087 // lo = (sra hi, shamt[4:0])
2088 // hi = (sra hi, 31)
2089 // else:
2090 // lo = (srl hi, shamt[4:0])
2091 // hi = 0
2092 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2093 DAG.getConstant(-1, MVT::i32));
2094 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
2095 DAG.getConstant(1, MVT::i32));
2096 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
2097 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
2098 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2099 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2100 Hi, Shamt);
2101 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2102 DAG.getConstant(0x20, MVT::i32));
2103 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
2104 DAG.getConstant(31, MVT::i32));
2105 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
2106 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2107 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
2108 ShiftRightHi);
2109
2110 SDValue Ops[2] = {Lo, Hi};
2111 return DAG.getMergeValues(Ops, 2, DL);
2112}
2113
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002114static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2115 SDValue Chain, SDValue Src, unsigned Offset) {
Akira Hatanaka2bd7e532012-06-13 19:06:08 +00002116 SDValue Ptr = LD->getBasePtr();
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002117 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
Akira Hatanaka2bd7e532012-06-13 19:06:08 +00002118 EVT BasePtrVT = Ptr.getValueType();
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002119 DebugLoc DL = LD->getDebugLoc();
2120 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2121
2122 if (Offset)
Akira Hatanaka2bd7e532012-06-13 19:06:08 +00002123 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002124 DAG.getConstant(Offset, BasePtrVT));
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002125
2126 SDValue Ops[] = { Chain, Ptr, Src };
2127 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2128 LD->getMemOperand());
2129}
2130
2131// Expand an unaligned 32 or 64-bit integer load node.
2132SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2133 LoadSDNode *LD = cast<LoadSDNode>(Op);
2134 EVT MemVT = LD->getMemoryVT();
2135
2136 // Return if load is aligned or if MemVT is neither i32 nor i64.
2137 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2138 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2139 return SDValue();
2140
2141 bool IsLittle = Subtarget->isLittle();
2142 EVT VT = Op.getValueType();
2143 ISD::LoadExtType ExtType = LD->getExtensionType();
2144 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2145
2146 assert((VT == MVT::i32) || (VT == MVT::i64));
2147
2148 // Expand
2149 // (set dst, (i64 (load baseptr)))
2150 // to
2151 // (set tmp, (ldl (add baseptr, 7), undef))
2152 // (set dst, (ldr baseptr, tmp))
2153 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2154 SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2155 IsLittle ? 7 : 0);
2156 return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2157 IsLittle ? 0 : 7);
2158 }
2159
2160 SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2161 IsLittle ? 3 : 0);
2162 SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2163 IsLittle ? 0 : 3);
2164
2165 // Expand
2166 // (set dst, (i32 (load baseptr))) or
2167 // (set dst, (i64 (sextload baseptr))) or
2168 // (set dst, (i64 (extload baseptr)))
2169 // to
2170 // (set tmp, (lwl (add baseptr, 3), undef))
2171 // (set dst, (lwr baseptr, tmp))
2172 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2173 (ExtType == ISD::EXTLOAD))
2174 return LWR;
2175
2176 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2177
2178 // Expand
2179 // (set dst, (i64 (zextload baseptr)))
2180 // to
2181 // (set tmp0, (lwl (add baseptr, 3), undef))
2182 // (set tmp1, (lwr baseptr, tmp0))
2183 // (set tmp2, (shl tmp1, 32))
2184 // (set dst, (srl tmp2, 32))
2185 DebugLoc DL = LD->getDebugLoc();
2186 SDValue Const32 = DAG.getConstant(32, MVT::i32);
2187 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
Akira Hatanaka94ccee22012-06-04 17:46:29 +00002188 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2189 SDValue Ops[] = { SRL, LWR.getValue(1) };
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002190 return DAG.getMergeValues(Ops, 2, DL);
2191}
2192
2193static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2194 SDValue Chain, unsigned Offset) {
Akira Hatanaka2bd7e532012-06-13 19:06:08 +00002195 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2196 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002197 DebugLoc DL = SD->getDebugLoc();
2198 SDVTList VTList = DAG.getVTList(MVT::Other);
2199
2200 if (Offset)
Akira Hatanaka2bd7e532012-06-13 19:06:08 +00002201 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002202 DAG.getConstant(Offset, BasePtrVT));
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002203
2204 SDValue Ops[] = { Chain, Value, Ptr };
2205 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2206 SD->getMemOperand());
2207}
2208
2209// Expand an unaligned 32 or 64-bit integer store node.
2210SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2211 StoreSDNode *SD = cast<StoreSDNode>(Op);
2212 EVT MemVT = SD->getMemoryVT();
2213
2214 // Return if store is aligned or if MemVT is neither i32 nor i64.
2215 if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2216 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2217 return SDValue();
2218
2219 bool IsLittle = Subtarget->isLittle();
2220 SDValue Value = SD->getValue(), Chain = SD->getChain();
2221 EVT VT = Value.getValueType();
2222
2223 // Expand
2224 // (store val, baseptr) or
2225 // (truncstore val, baseptr)
2226 // to
2227 // (swl val, (add baseptr, 3))
2228 // (swr val, baseptr)
2229 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2230 SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain,
2231 IsLittle ? 3 : 0);
2232 return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2233 }
2234
2235 assert(VT == MVT::i64);
2236
2237 // Expand
2238 // (store val, baseptr)
2239 // to
2240 // (sdl val, (add baseptr, 7))
2241 // (sdr val, baseptr)
2242 SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2243 return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2244}
2245
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002246//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002247// Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002248//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002249
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002250//===----------------------------------------------------------------------===//
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002251// TODO: Implement a generic logic using tblgen that can support this.
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002252// Mips O32 ABI rules:
2253// ---
2254// i32 - Passed in A0, A1, A2, A3 and stack
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002255// f32 - Only passed in f32 registers if no int reg has been used yet to hold
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002256// an argument. Otherwise, passed in A1, A2, A3 and stack.
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002257// f64 - Only passed in two aliased f32 registers if no int reg has been used
2258// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002259// not used, it must be shadowed. If only A3 is avaiable, shadow it and
2260// go to stack.
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002261//
2262// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002263//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002264
Duncan Sands1e96bab2010-11-04 10:49:57 +00002265static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
Duncan Sands1440e8b2010-11-03 11:35:31 +00002266 MVT LocVT, CCValAssign::LocInfo LocInfo,
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002267 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2268
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002269 static const unsigned IntRegsSize=4, FloatRegsSize=2;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002270
Craig Topperc5eaae42012-03-11 07:57:25 +00002271 static const uint16_t IntRegs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002272 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2273 };
Craig Topperc5eaae42012-03-11 07:57:25 +00002274 static const uint16_t F32Regs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002275 Mips::F12, Mips::F14
2276 };
Craig Topperc5eaae42012-03-11 07:57:25 +00002277 static const uint16_t F64Regs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002278 Mips::D6, Mips::D7
2279 };
2280
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002281 // ByVal Args
2282 if (ArgFlags.isByVal()) {
2283 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo,
2284 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags);
2285 unsigned NextReg = (State.getNextStackOffset() + 3) / 4;
2286 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize);
2287 r < std::min(IntRegsSize, NextReg); ++r)
2288 State.AllocateReg(IntRegs[r]);
2289 return false;
2290 }
2291
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002292 // Promote i8 and i16
2293 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2294 LocVT = MVT::i32;
2295 if (ArgFlags.isSExt())
2296 LocInfo = CCValAssign::SExt;
2297 else if (ArgFlags.isZExt())
2298 LocInfo = CCValAssign::ZExt;
2299 else
2300 LocInfo = CCValAssign::AExt;
2301 }
2302
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002303 unsigned Reg;
2304
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002305 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2306 // is true: function is vararg, argument is 3rd or higher, there is previous
2307 // argument which is not f32 or f64.
2308 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
2309 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
Akira Hatanakaa1a7ba82011-05-19 20:29:48 +00002310 unsigned OrigAlign = ArgFlags.getOrigAlign();
2311 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002312
2313 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002314 Reg = State.AllocateReg(IntRegs, IntRegsSize);
Akira Hatanakaa1a7ba82011-05-19 20:29:48 +00002315 // If this is the first part of an i64 arg,
2316 // the allocated register must be either A0 or A2.
2317 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2318 Reg = State.AllocateReg(IntRegs, IntRegsSize);
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002319 LocVT = MVT::i32;
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002320 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2321 // Allocate int register and shadow next int register. If first
2322 // available register is Mips::A1 or Mips::A3, shadow it too.
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002323 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2324 if (Reg == Mips::A1 || Reg == Mips::A3)
2325 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2326 State.AllocateReg(IntRegs, IntRegsSize);
2327 LocVT = MVT::i32;
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002328 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2329 // we are guaranteed to find an available float register
2330 if (ValVT == MVT::f32) {
2331 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2332 // Shadow int register
2333 State.AllocateReg(IntRegs, IntRegsSize);
2334 } else {
2335 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2336 // Shadow int registers
2337 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2338 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2339 State.AllocateReg(IntRegs, IntRegsSize);
2340 State.AllocateReg(IntRegs, IntRegsSize);
2341 }
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002342 } else
2343 llvm_unreachable("Cannot handle this ValVT.");
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002344
Akira Hatanakad37776d2011-05-20 21:39:54 +00002345 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
2346 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign);
2347
2348 if (!Reg)
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002349 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
Akira Hatanakad37776d2011-05-20 21:39:54 +00002350 else
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002351 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002352
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002353 return false; // CC must always match
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002354}
2355
Craig Topperc5eaae42012-03-11 07:57:25 +00002356static const uint16_t Mips64IntRegs[8] =
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002357 {Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
2358 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
Craig Topperc5eaae42012-03-11 07:57:25 +00002359static const uint16_t Mips64DPRegs[8] =
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002360 {Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
2361 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64};
2362
2363static bool CC_Mips64Byval(unsigned ValNo, MVT ValVT, MVT LocVT,
2364 CCValAssign::LocInfo LocInfo,
2365 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2366 unsigned Align = std::max(ArgFlags.getByValAlign(), (unsigned)8);
2367 unsigned Size = (ArgFlags.getByValSize() + 7) / 8 * 8;
2368 unsigned FirstIdx = State.getFirstUnallocated(Mips64IntRegs, 8);
2369
2370 assert(Align <= 16 && "Cannot handle alignments larger than 16.");
2371
Jia Liubb481f82012-02-28 07:46:26 +00002372 // If byval is 16-byte aligned, the first arg register must be even.
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002373 if ((Align == 16) && (FirstIdx % 2)) {
2374 State.AllocateReg(Mips64IntRegs[FirstIdx], Mips64DPRegs[FirstIdx]);
2375 ++FirstIdx;
2376 }
2377
2378 // Mark the registers allocated.
2379 for (unsigned I = FirstIdx; Size && (I < 8); Size -= 8, ++I)
2380 State.AllocateReg(Mips64IntRegs[I], Mips64DPRegs[I]);
2381
2382 // Allocate space on caller's stack.
2383 unsigned Offset = State.AllocateStack(Size, Align);
Jia Liubb481f82012-02-28 07:46:26 +00002384
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002385 if (FirstIdx < 8)
2386 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Mips64IntRegs[FirstIdx],
Jia Liubb481f82012-02-28 07:46:26 +00002387 LocVT, LocInfo));
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002388 else
2389 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2390
2391 return true;
2392}
2393
2394#include "MipsGenCallingConv.inc"
2395
Akira Hatanaka49617092011-11-14 19:02:54 +00002396static void
Akira Hatanaka08067b22012-01-24 22:07:36 +00002397AnalyzeMips64CallOperands(CCState &CCInfo,
Akira Hatanaka49617092011-11-14 19:02:54 +00002398 const SmallVectorImpl<ISD::OutputArg> &Outs) {
2399 unsigned NumOps = Outs.size();
2400 for (unsigned i = 0; i != NumOps; ++i) {
2401 MVT ArgVT = Outs[i].VT;
2402 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2403 bool R;
2404
2405 if (Outs[i].IsFixed)
2406 R = CC_MipsN(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2407 else
2408 R = CC_MipsN_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
Jia Liubb481f82012-02-28 07:46:26 +00002409
Akira Hatanaka49617092011-11-14 19:02:54 +00002410 if (R) {
Benjamin Kramer6296ee32011-11-14 19:51:48 +00002411#ifndef NDEBUG
Akira Hatanaka49617092011-11-14 19:02:54 +00002412 dbgs() << "Call operand #" << i << " has unhandled type "
2413 << EVT(ArgVT).getEVTString();
2414#endif
2415 llvm_unreachable(0);
2416 }
2417 }
2418}
2419
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002420//===----------------------------------------------------------------------===//
Dan Gohman98ca4f22009-08-05 01:29:28 +00002421// Call Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002422//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002423
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002424static const unsigned O32IntRegsSize = 4;
2425
Craig Topperc5eaae42012-03-11 07:57:25 +00002426static const uint16_t O32IntRegs[] = {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002427 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2428};
2429
Akira Hatanaka373e3a42011-09-23 00:58:33 +00002430// Return next O32 integer argument register.
2431static unsigned getNextIntArgReg(unsigned Reg) {
2432 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2433 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2434}
2435
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002436// Write ByVal Arg to arg registers and stack.
2437static void
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002438WriteByValArg(SDValue Chain, DebugLoc dl,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002439 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass,
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002440 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002441 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002442 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002443 MVT PtrType, bool isLittle) {
2444 unsigned LocMemOffset = VA.getLocMemOffset();
2445 unsigned Offset = 0;
2446 uint32_t RemainingSize = Flags.getByValSize();
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +00002447 unsigned ByValAlign = Flags.getByValAlign();
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002448
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002449 // Copy the first 4 words of byval arg to registers A0 - A3.
2450 // FIXME: Use a stricter alignment if it enables better optimization in passes
2451 // run later.
2452 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4;
2453 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002454 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002455 DAG.getConstant(Offset, MVT::i32));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002456 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
Akira Hatanaka82099682011-12-19 19:52:25 +00002457 MachinePointerInfo(), false, false, false,
2458 std::min(ByValAlign, (unsigned )4));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002459 MemOpChains.push_back(LoadVal.getValue(1));
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002460 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002461 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
2462 }
2463
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002464 if (RemainingSize == 0)
2465 return;
2466
2467 // If there still is a register available for argument passing, write the
2468 // remaining part of the structure to it using subword loads and shifts.
2469 if (LocMemOffset < 4 * 4) {
2470 assert(RemainingSize <= 3 && RemainingSize >= 1 &&
2471 "There must be one to three bytes remaining.");
2472 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize);
2473 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2474 DAG.getConstant(Offset, MVT::i32));
2475 unsigned Alignment = std::min(ByValAlign, (unsigned )4);
2476 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
2477 LoadPtr, MachinePointerInfo(),
2478 MVT::getIntegerVT(LoadSize * 8), false,
2479 false, Alignment);
2480 MemOpChains.push_back(LoadVal.getValue(1));
2481
2482 // If target is big endian, shift it to the most significant half-word or
2483 // byte.
2484 if (!isLittle)
2485 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal,
2486 DAG.getConstant(32 - LoadSize * 8, MVT::i32));
2487
2488 Offset += LoadSize;
2489 RemainingSize -= LoadSize;
2490
2491 // Read second subword if necessary.
2492 if (RemainingSize != 0) {
2493 assert(RemainingSize == 1 && "There must be one byte remaining.");
Jia Liubb481f82012-02-28 07:46:26 +00002494 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002495 DAG.getConstant(Offset, MVT::i32));
2496 unsigned Alignment = std::min(ByValAlign, (unsigned )2);
2497 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
2498 LoadPtr, MachinePointerInfo(),
2499 MVT::i8, false, false, Alignment);
2500 MemOpChains.push_back(Subword.getValue(1));
2501 // Insert the loaded byte to LoadVal.
2502 // FIXME: Use INS if supported by target.
2503 unsigned ShiftAmt = isLittle ? 16 : 8;
2504 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword,
2505 DAG.getConstant(ShiftAmt, MVT::i32));
2506 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift);
2507 }
2508
2509 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
2510 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
2511 return;
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002512 }
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002513
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002514 // Copy remaining part of byval arg using memcpy.
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002515 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2516 DAG.getConstant(Offset, MVT::i32));
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002517 SDValue Dst = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr,
2518 DAG.getIntPtrConstant(LocMemOffset));
2519 Chain = DAG.getMemcpy(Chain, dl, Dst, Src,
2520 DAG.getConstant(RemainingSize, MVT::i32),
2521 std::min(ByValAlign, (unsigned)4),
2522 /*isVolatile=*/false, /*AlwaysInline=*/false,
2523 MachinePointerInfo(0), MachinePointerInfo(0));
2524 MemOpChains.push_back(Chain);
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002525}
2526
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002527// Copy Mips64 byVal arg to registers and stack.
2528void static
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002529PassByValArg64(SDValue Chain, DebugLoc dl,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002530 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass,
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002531 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002532 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002533 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002534 EVT PtrTy, bool isLittle) {
2535 unsigned ByValSize = Flags.getByValSize();
2536 unsigned Alignment = std::min(Flags.getByValAlign(), (unsigned)8);
2537 bool IsRegLoc = VA.isRegLoc();
2538 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
2539 unsigned LocMemOffset = 0;
Akira Hatanaka16040852011-11-15 18:42:25 +00002540 unsigned MemCpySize = ByValSize;
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002541
2542 if (!IsRegLoc)
2543 LocMemOffset = VA.getLocMemOffset();
2544 else {
Craig Topperc5eaae42012-03-11 07:57:25 +00002545 const uint16_t *Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8,
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002546 VA.getLocReg());
Craig Topperc5eaae42012-03-11 07:57:25 +00002547 const uint16_t *RegEnd = Mips64IntRegs + 8;
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002548
2549 // Copy double words to registers.
2550 for (; (Reg != RegEnd) && (ByValSize >= Offset + 8); ++Reg, Offset += 8) {
2551 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2552 DAG.getConstant(Offset, PtrTy));
2553 SDValue LoadVal = DAG.getLoad(MVT::i64, dl, Chain, LoadPtr,
2554 MachinePointerInfo(), false, false, false,
2555 Alignment);
2556 MemOpChains.push_back(LoadVal.getValue(1));
2557 RegsToPass.push_back(std::make_pair(*Reg, LoadVal));
2558 }
2559
Jia Liubb481f82012-02-28 07:46:26 +00002560 // Return if the struct has been fully copied.
Akira Hatanaka16040852011-11-15 18:42:25 +00002561 if (!(MemCpySize = ByValSize - Offset))
2562 return;
2563
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002564 // If there is an argument register available, copy the remainder of the
2565 // byval argument with sub-doubleword loads and shifts.
Akira Hatanaka16040852011-11-15 18:42:25 +00002566 if (Reg != RegEnd) {
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002567 assert((ByValSize < Offset + 8) &&
2568 "Size of the remainder should be smaller than 8-byte.");
2569 SDValue Val;
2570 for (unsigned LoadSize = 4; Offset < ByValSize; LoadSize /= 2) {
2571 unsigned RemSize = ByValSize - Offset;
2572
2573 if (RemSize < LoadSize)
2574 continue;
Jia Liubb481f82012-02-28 07:46:26 +00002575
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002576 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2577 DAG.getConstant(Offset, PtrTy));
Jia Liubb481f82012-02-28 07:46:26 +00002578 SDValue LoadVal =
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002579 DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i64, Chain, LoadPtr,
2580 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
2581 false, false, Alignment);
2582 MemOpChains.push_back(LoadVal.getValue(1));
2583
2584 // Offset in number of bits from double word boundary.
2585 unsigned OffsetDW = (Offset % 8) * 8;
2586 unsigned Shamt = isLittle ? OffsetDW : 64 - (OffsetDW + LoadSize * 8);
2587 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i64, LoadVal,
2588 DAG.getConstant(Shamt, MVT::i32));
Jia Liubb481f82012-02-28 07:46:26 +00002589
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002590 Val = Val.getNode() ? DAG.getNode(ISD::OR, dl, MVT::i64, Val, Shift) :
2591 Shift;
2592 Offset += LoadSize;
2593 Alignment = std::min(Alignment, LoadSize);
2594 }
Jia Liubb481f82012-02-28 07:46:26 +00002595
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002596 RegsToPass.push_back(std::make_pair(*Reg, Val));
2597 return;
2598 }
2599 }
2600
Akira Hatanaka16040852011-11-15 18:42:25 +00002601 assert(MemCpySize && "MemCpySize must not be zero.");
2602
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002603 // Copy remainder of byval arg to it with memcpy.
Akira Hatanaka16040852011-11-15 18:42:25 +00002604 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2605 DAG.getConstant(Offset, PtrTy));
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002606 SDValue Dst = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr,
2607 DAG.getIntPtrConstant(LocMemOffset));
2608 Chain = DAG.getMemcpy(Chain, dl, Dst, Src,
2609 DAG.getConstant(MemCpySize, PtrTy), Alignment,
2610 /*isVolatile=*/false, /*AlwaysInline=*/false,
2611 MachinePointerInfo(0), MachinePointerInfo(0));
2612 MemOpChains.push_back(Chain);
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002613}
2614
Dan Gohman98ca4f22009-08-05 01:29:28 +00002615/// LowerCall - functions arguments are copied from virtual regs to
Nate Begeman5bf4b752009-01-26 03:15:54 +00002616/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002617/// TODO: isTailCall.
Dan Gohman98ca4f22009-08-05 01:29:28 +00002618SDValue
Justin Holewinskid2ea0e12012-05-25 16:35:28 +00002619MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
Dan Gohmand858e902010-04-17 15:26:15 +00002620 SmallVectorImpl<SDValue> &InVals) const {
Justin Holewinskid2ea0e12012-05-25 16:35:28 +00002621 SelectionDAG &DAG = CLI.DAG;
2622 DebugLoc &dl = CLI.DL;
2623 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2624 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2625 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002626 SDValue Chain = CLI.Chain;
Justin Holewinskid2ea0e12012-05-25 16:35:28 +00002627 SDValue Callee = CLI.Callee;
2628 bool &isTailCall = CLI.IsTailCall;
2629 CallingConv::ID CallConv = CLI.CallConv;
2630 bool isVarArg = CLI.IsVarArg;
2631
Evan Cheng0c439eb2010-01-27 00:07:07 +00002632 // MIPs target does not yet support tail call optimization.
2633 isTailCall = false;
Dan Gohman98ca4f22009-08-05 01:29:28 +00002634
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002635 MachineFunction &MF = DAG.getMachineFunction();
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002636 MachineFrameInfo *MFI = MF.getFrameInfo();
Akira Hatanakad37776d2011-05-20 21:39:54 +00002637 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00002638 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Akira Hatanaka17a1e872011-05-20 18:39:33 +00002639 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002640
2641 // Analyze operands of the call, assigning locations to each operand.
2642 SmallVector<CCValAssign, 16> ArgLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00002643 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka82099682011-12-19 19:52:25 +00002644 getTargetMachine(), ArgLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002645
Akira Hatanaka777a1202012-06-13 18:06:00 +00002646 if (CallConv == CallingConv::Fast)
2647 CCInfo.AnalyzeCallOperands(Outs, CC_Mips_FastCC);
2648 else if (IsO32)
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002649 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
Akira Hatanaka49617092011-11-14 19:02:54 +00002650 else if (HasMips64)
2651 AnalyzeMips64CallOperands(CCInfo, Outs);
Akira Hatanakabdd2ce92011-05-23 21:13:59 +00002652 else
Dan Gohman98ca4f22009-08-05 01:29:28 +00002653 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002654
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002655 // Get a count of how many bytes are to be pushed on the stack.
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002656 unsigned NextStackOffset = CCInfo.getNextStackOffset();
Akira Hatanaka480eeb52012-07-26 23:27:01 +00002657 unsigned StackAlignment = TFL->getStackAlignment();
2658 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2659
2660 // Update size of the maximum argument space.
2661 // For O32, a minimum of four words (16 bytes) of argument space is
2662 // allocated.
2663 if (IsO32 && (CallConv != CallingConv::Fast))
2664 NextStackOffset = std::max(NextStackOffset, (unsigned)16);
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002665
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002666 // Chain is the output chain of the last Load/Store or CopyToReg node.
2667 // ByValChain is the output chain of the last Memcpy node created for copying
2668 // byval arguments to the stack.
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002669 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002670 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal);
2671
2672 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl,
2673 IsN64 ? Mips::SP_64 : Mips::SP,
2674 getPointerTy());
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002675
Akira Hatanaka1d165f12012-07-31 20:54:48 +00002676 if (MipsFI->getMaxCallFrameSize() < NextStackOffset)
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002677 MipsFI->setMaxCallFrameSize(NextStackOffset);
2678
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002679 // With EABI is it possible to have 16 args on registers.
Dan Gohman475871a2008-07-27 21:46:04 +00002680 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
2681 SmallVector<SDValue, 8> MemOpChains;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002682
2683 // Walk the register/memloc assignments, inserting copies/loads.
2684 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
Dan Gohmanc9403652010-07-07 15:54:55 +00002685 SDValue Arg = OutVals[i];
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002686 CCValAssign &VA = ArgLocs[i];
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002687 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002688 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2689
2690 // ByVal Arg.
2691 if (Flags.isByVal()) {
2692 assert(Flags.getByValSize() &&
2693 "ByVal args of size 0 should have been ignored by front-end.");
2694 if (IsO32)
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002695 WriteByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr,
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002696 MFI, DAG, Arg, VA, Flags, getPointerTy(),
2697 Subtarget->isLittle());
2698 else
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002699 PassByValArg64(Chain, dl, RegsToPass, MemOpChains, StackPtr,
Jia Liubb481f82012-02-28 07:46:26 +00002700 MFI, DAG, Arg, VA, Flags, getPointerTy(),
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002701 Subtarget->isLittle());
2702 continue;
2703 }
Jia Liubb481f82012-02-28 07:46:26 +00002704
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002705 // Promote the value if needed.
2706 switch (VA.getLocInfo()) {
Torok Edwinc23197a2009-07-14 16:55:14 +00002707 default: llvm_unreachable("Unknown loc info!");
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002708 case CCValAssign::Full:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002709 if (VA.isRegLoc()) {
2710 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2711 (ValVT == MVT::f64 && LocVT == MVT::i64))
2712 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
2713 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002714 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2715 Arg, DAG.getConstant(0, MVT::i32));
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00002716 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2717 Arg, DAG.getConstant(1, MVT::i32));
Akira Hatanaka99a2e982011-04-15 19:52:08 +00002718 if (!Subtarget->isLittle())
2719 std::swap(Lo, Hi);
Jia Liubb481f82012-02-28 07:46:26 +00002720 unsigned LocRegLo = VA.getLocReg();
Akira Hatanaka373e3a42011-09-23 00:58:33 +00002721 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2722 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2723 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002724 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002725 }
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002726 }
2727 break;
Chris Lattnere0b12152008-03-17 06:57:02 +00002728 case CCValAssign::SExt:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002729 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002730 break;
2731 case CCValAssign::ZExt:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002732 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002733 break;
2734 case CCValAssign::AExt:
Akira Hatanaka38bdc572012-02-17 02:20:26 +00002735 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002736 break;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002737 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002738
2739 // Arguments that can be passed on register must be kept at
Bruno Cardoso Lopesc7db5612007-11-05 03:02:32 +00002740 // RegsToPass vector
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002741 if (VA.isRegLoc()) {
2742 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
Chris Lattnere0b12152008-03-17 06:57:02 +00002743 continue;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002744 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002745
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002746 // Register can't get to this point...
Chris Lattnere0b12152008-03-17 06:57:02 +00002747 assert(VA.isMemLoc());
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002748
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002749 // emit ISD::STORE whichs stores the
Chris Lattnere0b12152008-03-17 06:57:02 +00002750 // parameter value to a stack Location
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002751 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
2752 DAG.getIntPtrConstant(VA.getLocMemOffset()));
Chris Lattner8026a9d2010-09-21 17:50:43 +00002753 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
Akira Hatanaka82099682011-12-19 19:52:25 +00002754 MachinePointerInfo(), false, false, 0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002755 }
2756
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002757 // Transform all store nodes into one single node because all store
2758 // nodes are independent of each other.
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002759 if (!MemOpChains.empty())
2760 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002761 &MemOpChains[0], MemOpChains.size());
2762
Bill Wendling056292f2008-09-16 21:48:12 +00002763 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002764 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2765 // node so that legalize doesn't hack it.
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002766 unsigned char OpFlag;
2767 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002768 bool GlobalOrExternal = false;
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002769 SDValue CalleeLo;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002770
2771 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002772 if (IsPICCall && G->getGlobal()->hasInternalLinkage()) {
2773 OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE;
2774 unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST;
2775 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
2776 OpFlag);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002777 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002778 0, LoFlag);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002779 } else {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002780 OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002781 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2782 getPointerTy(), 0, OpFlag);
2783 }
2784
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002785 GlobalOrExternal = true;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002786 }
2787 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002788 if (IsN64 || (!IsO32 && IsPIC))
2789 OpFlag = MipsII::MO_GOT_DISP;
2790 else if (!IsPIC) // !N64 && static
2791 OpFlag = MipsII::MO_NO_FLAG;
2792 else // O32 & PIC
2793 OpFlag = MipsII::MO_GOT_CALL;
Akira Hatanaka82099682011-12-19 19:52:25 +00002794 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2795 OpFlag);
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002796 GlobalOrExternal = true;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002797 }
2798
Akira Hatanakacd0f90f2011-05-20 02:30:51 +00002799 SDValue InFlag;
2800
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002801 // Create nodes that load address of callee and copy it to T9
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002802 if (IsPICCall) {
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002803 if (GlobalOrExternal) {
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002804 // Load callee address
Akira Hatanaka648f00c2012-02-24 22:34:47 +00002805 Callee = DAG.getNode(MipsISD::Wrapper, dl, getPointerTy(),
2806 GetGlobalReg(DAG, getPointerTy()), Callee);
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002807 SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
2808 Callee, MachinePointerInfo::getGOT(),
Pete Cooperd752e0f2011-11-08 18:42:53 +00002809 false, false, false, 0);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002810
2811 // Use GOT+LO if callee has internal linkage.
2812 if (CalleeLo.getNode()) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002813 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo);
2814 Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002815 } else
2816 Callee = LoadValue;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002817 }
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002818 }
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002819
Akira Hatanakae11246c2012-07-26 02:24:43 +00002820 // T9 register operand.
2821 SDValue T9;
2822
Jia Liubb481f82012-02-28 07:46:26 +00002823 // T9 should contain the address of the callee function if
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002824 // -reloction-model=pic or it is an indirect call.
2825 if (IsPICCall || !GlobalOrExternal) {
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002826 // copy to T9
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002827 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
2828 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0));
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002829 InFlag = Chain.getValue(1);
Akira Hatanakae11246c2012-07-26 02:24:43 +00002830
2831 if (Subtarget->inMips16Mode())
2832 T9 = DAG.getRegister(T9Reg, getPointerTy());
2833 else
2834 Callee = DAG.getRegister(T9Reg, getPointerTy());
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002835 }
Bill Wendling056292f2008-09-16 21:48:12 +00002836
Akira Hatanaka92d4aec2012-05-12 03:19:04 +00002837 // Insert node "GP copy globalreg" before call to function.
2838 // Lazy-binding stubs require GP to point to the GOT.
2839 if (IsPICCall) {
2840 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
2841 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
2842 RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty)));
2843 }
2844
Akira Hatanakacd0f90f2011-05-20 02:30:51 +00002845 // Build a sequence of copy-to-reg nodes chained together with token
2846 // chain and flag operands which copy the outgoing args into registers.
2847 // The InFlag in necessary since all emitted instructions must be
2848 // stuck together.
2849 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2850 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2851 RegsToPass[i].second, InFlag);
2852 InFlag = Chain.getValue(1);
2853 }
2854
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002855 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002856 // = Chain, Callee, Reg#1, Reg#2, ...
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002857 //
2858 // Returns a chain & a flag for retval copy to use.
Chris Lattnerf1b4eaf2010-12-21 02:38:05 +00002859 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
Dan Gohman475871a2008-07-27 21:46:04 +00002860 SmallVector<SDValue, 8> Ops;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002861 Ops.push_back(Chain);
Akira Hatanakae11246c2012-07-26 02:24:43 +00002862 Ops.push_back(Callee);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002863
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002864 // Add argument registers to the end of the list so that they are
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002865 // known live into the call.
2866 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2867 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2868 RegsToPass[i].second.getValueType()));
2869
Akira Hatanakae11246c2012-07-26 02:24:43 +00002870 // Add T9 register operand.
2871 if (T9.getNode())
2872 Ops.push_back(T9);
2873
Akira Hatanakab2930b92012-03-01 22:27:29 +00002874 // Add a register mask operand representing the call-preserved registers.
2875 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2876 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2877 assert(Mask && "Missing call preserved mask for calling convention");
2878 Ops.push_back(DAG.getRegisterMask(Mask));
2879
Gabor Greifba36cb52008-08-28 21:40:38 +00002880 if (InFlag.getNode())
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002881 Ops.push_back(InFlag);
2882
Dale Johannesen33c960f2009-02-04 20:06:27 +00002883 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002884 InFlag = Chain.getValue(1);
2885
Bruno Cardoso Lopes3ed6f872010-01-30 18:32:07 +00002886 // Create the CALLSEQ_END node.
Akira Hatanaka480eeb52012-07-26 23:27:01 +00002887 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
Bruno Cardoso Lopes3ed6f872010-01-30 18:32:07 +00002888 DAG.getIntPtrConstant(0, true), InFlag);
2889 InFlag = Chain.getValue(1);
2890
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002891 // Handle result values, copying them out of physregs into vregs that we
2892 // return.
Dan Gohman98ca4f22009-08-05 01:29:28 +00002893 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2894 Ins, dl, DAG, InVals);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002895}
2896
Dan Gohman98ca4f22009-08-05 01:29:28 +00002897/// LowerCallResult - Lower the result values of a call into the
2898/// appropriate copies out of appropriate physical registers.
2899SDValue
2900MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00002901 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +00002902 const SmallVectorImpl<ISD::InputArg> &Ins,
2903 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +00002904 SmallVectorImpl<SDValue> &InVals) const {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002905 // Assign locations to each value returned by this call.
2906 SmallVector<CCValAssign, 16> RVLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00002907 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka864f6602012-06-14 21:10:56 +00002908 getTargetMachine(), RVLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002909
Dan Gohman98ca4f22009-08-05 01:29:28 +00002910 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002911
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002912 // Copy all of the result registers out of their specified physreg.
2913 for (unsigned i = 0; i != RVLocs.size(); ++i) {
Dale Johannesen33c960f2009-02-04 20:06:27 +00002914 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
Dan Gohman98ca4f22009-08-05 01:29:28 +00002915 RVLocs[i].getValVT(), InFlag).getValue(1);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002916 InFlag = Chain.getValue(2);
Dan Gohman98ca4f22009-08-05 01:29:28 +00002917 InVals.push_back(Chain.getValue(0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002918 }
Bruno Cardoso Lopesc7db5612007-11-05 03:02:32 +00002919
Dan Gohman98ca4f22009-08-05 01:29:28 +00002920 return Chain;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002921}
2922
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002923//===----------------------------------------------------------------------===//
Dan Gohman98ca4f22009-08-05 01:29:28 +00002924// Formal Arguments Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002925//===----------------------------------------------------------------------===//
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002926static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002927 std::vector<SDValue> &OutChains,
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002928 SelectionDAG &DAG, unsigned NumWords, SDValue FIN,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002929 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
Akira Hatanakab4549e12012-03-27 03:13:56 +00002930 const Argument *FuncArg) {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002931 unsigned LocMem = VA.getLocMemOffset();
2932 unsigned FirstWord = LocMem / 4;
2933
2934 // copy register A0 - A3 to frame object
2935 for (unsigned i = 0; i < NumWords; ++i) {
2936 unsigned CurWord = FirstWord + i;
2937 if (CurWord >= O32IntRegsSize)
2938 break;
2939
2940 unsigned SrcReg = O32IntRegs[CurWord];
Craig Topper420761a2012-04-20 07:30:17 +00002941 unsigned Reg = AddLiveIn(MF, SrcReg, &Mips::CPURegsRegClass);
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002942 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
2943 DAG.getConstant(i * 4, MVT::i32));
2944 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32),
Akira Hatanakab4549e12012-03-27 03:13:56 +00002945 StorePtr, MachinePointerInfo(FuncArg, i * 4),
2946 false, false, 0);
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002947 OutChains.push_back(Store);
2948 }
2949}
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002950
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002951// Create frame object on stack and copy registers used for byval passing to it.
2952static unsigned
2953CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002954 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
2955 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002956 MachineFrameInfo *MFI, bool IsRegLoc,
2957 SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI,
Akira Hatanakab4549e12012-03-27 03:13:56 +00002958 EVT PtrTy, const Argument *FuncArg) {
Craig Topperc5eaae42012-03-11 07:57:25 +00002959 const uint16_t *Reg = Mips64IntRegs + 8;
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002960 int FOOffset; // Frame object offset from virtual frame pointer.
2961
2962 if (IsRegLoc) {
2963 Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, VA.getLocReg());
2964 FOOffset = (Reg - Mips64IntRegs) * 8 - 8 * 8;
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002965 }
2966 else
2967 FOOffset = VA.getLocMemOffset();
2968
2969 // Create frame object.
2970 unsigned NumRegs = (Flags.getByValSize() + 7) / 8;
2971 unsigned LastFI = MFI->CreateFixedObject(NumRegs * 8, FOOffset, true);
2972 SDValue FIN = DAG.getFrameIndex(LastFI, PtrTy);
2973 InVals.push_back(FIN);
2974
2975 // Copy arg registers.
2976 for (unsigned I = 0; (Reg != Mips64IntRegs + 8) && (I < NumRegs);
2977 ++Reg, ++I) {
Craig Topper420761a2012-04-20 07:30:17 +00002978 unsigned VReg = AddLiveIn(MF, *Reg, &Mips::CPU64RegsRegClass);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002979 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, PtrTy, FIN,
2980 DAG.getConstant(I * 8, PtrTy));
2981 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64),
Akira Hatanakab4549e12012-03-27 03:13:56 +00002982 StorePtr, MachinePointerInfo(FuncArg, I * 8),
2983 false, false, 0);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002984 OutChains.push_back(Store);
2985 }
Jia Liubb481f82012-02-28 07:46:26 +00002986
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002987 return LastFI;
2988}
2989
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002990/// LowerFormalArguments - transform physical registers into virtual registers
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002991/// and generate load operations for arguments places on the stack.
Dan Gohman98ca4f22009-08-05 01:29:28 +00002992SDValue
2993MipsTargetLowering::LowerFormalArguments(SDValue Chain,
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00002994 CallingConv::ID CallConv,
2995 bool isVarArg,
Akira Hatanaka82099682011-12-19 19:52:25 +00002996 const SmallVectorImpl<ISD::InputArg> &Ins,
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00002997 DebugLoc dl, SelectionDAG &DAG,
2998 SmallVectorImpl<SDValue> &InVals)
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002999 const {
Bruno Cardoso Lopesf7f3b502008-08-04 07:12:52 +00003000 MachineFunction &MF = DAG.getMachineFunction();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003001 MachineFrameInfo *MFI = MF.getFrameInfo();
Bruno Cardoso Lopesa2b1bb52007-08-28 05:08:16 +00003002 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00003003
Dan Gohman1e93df62010-04-17 14:41:14 +00003004 MipsFI->setVarArgsFrameIndex(0);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003005
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00003006 // Used with vargs to acumulate store chains.
3007 std::vector<SDValue> OutChains;
3008
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003009 // Assign locations to all of the incoming arguments.
3010 SmallVector<CCValAssign, 16> ArgLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00003011 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka82099682011-12-19 19:52:25 +00003012 getTargetMachine(), ArgLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00003013
Akira Hatanaka777a1202012-06-13 18:06:00 +00003014 if (CallConv == CallingConv::Fast)
3015 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FastCC);
3016 else if (IsO32)
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00003017 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003018 else
Dan Gohman98ca4f22009-08-05 01:29:28 +00003019 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003020
Akira Hatanakab4549e12012-03-27 03:13:56 +00003021 Function::const_arg_iterator FuncArg =
3022 DAG.getMachineFunction().getFunction()->arg_begin();
Akira Hatanaka43299772011-05-20 23:22:14 +00003023 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function.
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003024
Akira Hatanakab4549e12012-03-27 03:13:56 +00003025 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++FuncArg) {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003026 CCValAssign &VA = ArgLocs[i];
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00003027 EVT ValVT = VA.getValVT();
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003028 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3029 bool IsRegLoc = VA.isRegLoc();
3030
3031 if (Flags.isByVal()) {
3032 assert(Flags.getByValSize() &&
3033 "ByVal args of size 0 should have been ignored by front-end.");
3034 if (IsO32) {
3035 unsigned NumWords = (Flags.getByValSize() + 3) / 4;
3036 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(),
3037 true);
3038 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
3039 InVals.push_back(FIN);
Akira Hatanakab4549e12012-03-27 03:13:56 +00003040 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags,
3041 &*FuncArg);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003042 } else // N32/64
3043 LastFI = CopyMips64ByValRegs(MF, Chain, dl, OutChains, DAG, VA, Flags,
3044 MFI, IsRegLoc, InVals, MipsFI,
Akira Hatanakab4549e12012-03-27 03:13:56 +00003045 getPointerTy(), &*FuncArg);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003046 continue;
3047 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003048
3049 // Arguments stored on registers
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003050 if (IsRegLoc) {
Owen Andersone50ed302009-08-10 22:56:29 +00003051 EVT RegVT = VA.getLocVT();
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003052 unsigned ArgReg = VA.getLocReg();
Craig Topper44d23822012-02-22 05:59:10 +00003053 const TargetRegisterClass *RC;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003054
Owen Anderson825b72b2009-08-11 20:47:22 +00003055 if (RegVT == MVT::i32)
Craig Topper420761a2012-04-20 07:30:17 +00003056 RC = &Mips::CPURegsRegClass;
Akira Hatanaka95934842011-09-24 01:34:44 +00003057 else if (RegVT == MVT::i64)
Craig Topper420761a2012-04-20 07:30:17 +00003058 RC = &Mips::CPU64RegsRegClass;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003059 else if (RegVT == MVT::f32)
Craig Topper420761a2012-04-20 07:30:17 +00003060 RC = &Mips::FGR32RegClass;
Akira Hatanaka09dd60f2011-09-26 21:37:50 +00003061 else if (RegVT == MVT::f64)
Craig Topper420761a2012-04-20 07:30:17 +00003062 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
Akira Hatanaka09dd60f2011-09-26 21:37:50 +00003063 else
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00003064 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003065
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003066 // Transform the arguments stored on
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003067 // physical registers into virtual ones
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003068 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
Dan Gohman98ca4f22009-08-05 01:29:28 +00003069 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003070
3071 // If this is an 8 or 16-bit value, it has been passed promoted
3072 // to 32 bits. Insert an assert[sz]ext to capture this, then
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003073 // truncate to the right size.
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003074 if (VA.getLocInfo() != CCValAssign::Full) {
Chris Lattnerd4015072009-03-26 05:28:14 +00003075 unsigned Opcode = 0;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003076 if (VA.getLocInfo() == CCValAssign::SExt)
3077 Opcode = ISD::AssertSext;
3078 else if (VA.getLocInfo() == CCValAssign::ZExt)
3079 Opcode = ISD::AssertZext;
Chris Lattnerd4015072009-03-26 05:28:14 +00003080 if (Opcode)
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003081 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00003082 DAG.getValueType(ValVT));
3083 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003084 }
3085
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00003086 // Handle floating point arguments passed in integer registers.
3087 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3088 (RegVT == MVT::i64 && ValVT == MVT::f64))
3089 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
3090 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
3091 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
3092 getNextIntArgReg(ArgReg), RC);
3093 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
3094 if (!Subtarget->isLittle())
3095 std::swap(ArgValue, ArgValue2);
3096 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
3097 ArgValue, ArgValue2);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003098 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003099
Dan Gohman98ca4f22009-08-05 01:29:28 +00003100 InVals.push_back(ArgValue);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003101 } else { // VA.isRegLoc()
3102
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003103 // sanity check
3104 assert(VA.isMemLoc());
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00003105
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003106 // The stack pointer offset is relative to the caller stack frame.
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00003107 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003108 VA.getLocMemOffset(), true);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003109
3110 // Create load nodes to retrieve arguments from the stack
Akira Hatanaka43299772011-05-20 23:22:14 +00003111 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00003112 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
Akira Hatanaka43299772011-05-20 23:22:14 +00003113 MachinePointerInfo::getFixedStack(LastFI),
Pete Cooperd752e0f2011-11-08 18:42:53 +00003114 false, false, false, 0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003115 }
3116 }
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003117
3118 // The mips ABIs for returning structs by value requires that we copy
3119 // the sret argument into $v0 for the return. Save the argument into
3120 // a virtual register so that we can access it from the return points.
3121 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3122 unsigned Reg = MipsFI->getSRetReturnReg();
3123 if (!Reg) {
Owen Anderson825b72b2009-08-11 20:47:22 +00003124 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003125 MipsFI->setSRetReturnReg(Reg);
3126 }
Dan Gohman98ca4f22009-08-05 01:29:28 +00003127 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
Owen Anderson825b72b2009-08-11 20:47:22 +00003128 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003129 }
3130
Akira Hatanakabad53f42011-11-14 19:01:09 +00003131 if (isVarArg) {
3132 unsigned NumOfRegs = IsO32 ? 4 : 8;
Craig Topperc5eaae42012-03-11 07:57:25 +00003133 const uint16_t *ArgRegs = IsO32 ? O32IntRegs : Mips64IntRegs;
Akira Hatanakabad53f42011-11-14 19:01:09 +00003134 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumOfRegs);
3135 int FirstRegSlotOffset = IsO32 ? 0 : -64 ; // offset of $a0's slot.
Craig Topper420761a2012-04-20 07:30:17 +00003136 const TargetRegisterClass *RC = IsO32 ?
3137 (const TargetRegisterClass*)&Mips::CPURegsRegClass :
3138 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
Akira Hatanakabad53f42011-11-14 19:01:09 +00003139 unsigned RegSize = RC->getSize();
3140 int RegSlotOffset = FirstRegSlotOffset + Idx * RegSize;
3141
3142 // Offset of the first variable argument from stack pointer.
3143 int FirstVaArgOffset;
3144
3145 if (IsO32 || (Idx == NumOfRegs)) {
3146 FirstVaArgOffset =
3147 (CCInfo.getNextStackOffset() + RegSize - 1) / RegSize * RegSize;
3148 } else
3149 FirstVaArgOffset = RegSlotOffset;
3150
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003151 // Record the frame index of the first variable argument
Eric Christopher471e4222011-06-08 23:55:35 +00003152 // which is a value necessary to VASTART.
Akira Hatanakabad53f42011-11-14 19:01:09 +00003153 LastFI = MFI->CreateFixedObject(RegSize, FirstVaArgOffset, true);
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003154 MipsFI->setVarArgsFrameIndex(LastFI);
Akira Hatanakaedacba82011-05-25 17:32:06 +00003155
Akira Hatanakabad53f42011-11-14 19:01:09 +00003156 // Copy the integer registers that have not been used for argument passing
3157 // to the argument register save area. For O32, the save area is allocated
3158 // in the caller's stack frame, while for N32/64, it is allocated in the
3159 // callee's stack frame.
3160 for (int StackOffset = RegSlotOffset;
3161 Idx < NumOfRegs; ++Idx, StackOffset += RegSize) {
3162 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegs[Idx], RC);
3163 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
3164 MVT::getIntegerVT(RegSize * 8));
3165 LastFI = MFI->CreateFixedObject(RegSize, StackOffset, true);
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003166 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
3167 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
Akira Hatanaka82099682011-12-19 19:52:25 +00003168 MachinePointerInfo(), false, false, 0));
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00003169 }
3170 }
3171
Akira Hatanaka43299772011-05-20 23:22:14 +00003172 MipsFI->setLastInArgFI(LastFI);
3173
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003174 // All stores are grouped in one node to allow the matching between
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00003175 // the size of Ins and InVals. This only happens when on varg functions
3176 if (!OutChains.empty()) {
3177 OutChains.push_back(Chain);
3178 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3179 &OutChains[0], OutChains.size());
3180 }
3181
Dan Gohman98ca4f22009-08-05 01:29:28 +00003182 return Chain;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003183}
3184
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003185//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003186// Return Value Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003187//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003188
Dan Gohman98ca4f22009-08-05 01:29:28 +00003189SDValue
3190MipsTargetLowering::LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00003191 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +00003192 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +00003193 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmand858e902010-04-17 15:26:15 +00003194 DebugLoc dl, SelectionDAG &DAG) const {
Dan Gohman98ca4f22009-08-05 01:29:28 +00003195
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003196 // CCValAssign - represent the assignment of
3197 // the return value to a location
3198 SmallVector<CCValAssign, 16> RVLocs;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003199
3200 // CCState - Info about the registers and stack slot.
Eric Christopher471e4222011-06-08 23:55:35 +00003201 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka864f6602012-06-14 21:10:56 +00003202 getTargetMachine(), RVLocs, *DAG.getContext());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003203
Dan Gohman98ca4f22009-08-05 01:29:28 +00003204 // Analize return values.
3205 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003206
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003207 // If this is the first return lowered for this function, add
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003208 // the regs to the liveout set for the function.
Chris Lattner84bc5422007-12-31 04:13:23 +00003209 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003210 for (unsigned i = 0; i != RVLocs.size(); ++i)
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00003211 if (RVLocs[i].isRegLoc())
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003212 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003213 }
3214
Dan Gohman475871a2008-07-27 21:46:04 +00003215 SDValue Flag;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003216
3217 // Copy the result values into the output registers.
3218 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3219 CCValAssign &VA = RVLocs[i];
3220 assert(VA.isRegLoc() && "Can only return in registers!");
3221
Akira Hatanaka82099682011-12-19 19:52:25 +00003222 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003223
3224 // guarantee that all emitted copies are
3225 // stuck together, avoiding something bad
3226 Flag = Chain.getValue(1);
3227 }
3228
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003229 // The mips ABIs for returning structs by value requires that we copy
3230 // the sret argument into $v0 for the return. We saved the argument into
3231 // a virtual register in the entry block, so now we copy the value out
3232 // and into $v0.
3233 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3234 MachineFunction &MF = DAG.getMachineFunction();
3235 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3236 unsigned Reg = MipsFI->getSRetReturnReg();
3237
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003238 if (!Reg)
Torok Edwinc23197a2009-07-14 16:55:14 +00003239 llvm_unreachable("sret virtual register not created in the entry block");
Dale Johannesena05dca42009-02-04 23:02:30 +00003240 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003241
Dale Johannesena05dca42009-02-04 23:02:30 +00003242 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003243 Flag = Chain.getValue(1);
3244 }
3245
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003246 // Return on Mips is always a "jr $ra"
Gabor Greifba36cb52008-08-28 21:40:38 +00003247 if (Flag.getNode())
Akira Hatanaka182ef6f2012-07-10 00:19:06 +00003248 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain, Flag);
3249
3250 // Return Void
3251 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003252}
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003253
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003254//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003255// Mips Inline Assembly Support
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003256//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003257
3258/// getConstraintType - Given a constraint letter, return the type of
3259/// constraint it is for this target.
3260MipsTargetLowering::ConstraintType MipsTargetLowering::
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003261getConstraintType(const std::string &Constraint) const
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003262{
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003263 // Mips specific constrainy
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003264 // GCC config/mips/constraints.md
3265 //
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003266 // 'd' : An address register. Equivalent to r
3267 // unless generating MIPS16 code.
3268 // 'y' : Equivalent to r; retained for
3269 // backwards compatibility.
Eric Christopher1d5a3922012-05-07 06:25:10 +00003270 // 'c' : A register suitable for use in an indirect
3271 // jump. This will always be $25 for -mabicalls.
Eric Christopheraf97f732012-05-07 06:25:19 +00003272 // 'l' : The lo register. 1 word storage.
3273 // 'x' : The hilo register pair. Double word storage.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003274 if (Constraint.size() == 1) {
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003275 switch (Constraint[0]) {
3276 default : break;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003277 case 'd':
3278 case 'y':
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003279 case 'f':
Eric Christopher1d5a3922012-05-07 06:25:10 +00003280 case 'c':
Eric Christopher4adbefe2012-05-07 06:25:15 +00003281 case 'l':
Eric Christopheraf97f732012-05-07 06:25:19 +00003282 case 'x':
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003283 return C_RegisterClass;
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003284 }
3285 }
3286 return TargetLowering::getConstraintType(Constraint);
3287}
3288
John Thompson44ab89e2010-10-29 17:29:13 +00003289/// Examine constraint type and operand type and determine a weight value.
3290/// This object must already have been set up with the operand type
3291/// and the current alternative constraint selected.
3292TargetLowering::ConstraintWeight
3293MipsTargetLowering::getSingleConstraintMatchWeight(
3294 AsmOperandInfo &info, const char *constraint) const {
3295 ConstraintWeight weight = CW_Invalid;
3296 Value *CallOperandVal = info.CallOperandVal;
3297 // If we don't have a value, we can't do a match,
3298 // but allow it at the lowest weight.
3299 if (CallOperandVal == NULL)
3300 return CW_Default;
Chris Lattnerdb125cf2011-07-18 04:54:35 +00003301 Type *type = CallOperandVal->getType();
John Thompson44ab89e2010-10-29 17:29:13 +00003302 // Look at the constraint type.
3303 switch (*constraint) {
3304 default:
3305 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3306 break;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003307 case 'd':
3308 case 'y':
John Thompson44ab89e2010-10-29 17:29:13 +00003309 if (type->isIntegerTy())
3310 weight = CW_Register;
3311 break;
3312 case 'f':
3313 if (type->isFloatTy())
3314 weight = CW_Register;
3315 break;
Eric Christopher1d5a3922012-05-07 06:25:10 +00003316 case 'c': // $25 for indirect jumps
Eric Christopher4adbefe2012-05-07 06:25:15 +00003317 case 'l': // lo register
Eric Christopheraf97f732012-05-07 06:25:19 +00003318 case 'x': // hilo register pair
Eric Christopher1d5a3922012-05-07 06:25:10 +00003319 if (type->isIntegerTy())
3320 weight = CW_SpecificReg;
3321 break;
Eric Christopher50ab0392012-05-07 03:13:32 +00003322 case 'I': // signed 16 bit immediate
Eric Christophere5076d42012-05-07 03:13:42 +00003323 case 'J': // integer zero
Eric Christopherf49f8462012-05-07 05:46:29 +00003324 case 'K': // unsigned 16 bit immediate
Eric Christopher5ac47bb2012-05-07 05:46:37 +00003325 case 'L': // signed 32 bit immediate where lower 16 bits are 0
Eric Christopher60cfc792012-05-07 05:46:43 +00003326 case 'N': // immediate in the range of -65535 to -1 (inclusive)
Eric Christopher1ce20342012-05-07 05:46:48 +00003327 case 'O': // signed 15 bit immediate (+- 16383)
Eric Christopher54412a72012-05-07 06:25:02 +00003328 case 'P': // immediate in the range of 65535 to 1 (inclusive)
Eric Christopher50ab0392012-05-07 03:13:32 +00003329 if (isa<ConstantInt>(CallOperandVal))
3330 weight = CW_Constant;
3331 break;
John Thompson44ab89e2010-10-29 17:29:13 +00003332 }
3333 return weight;
3334}
3335
Eric Christopher38d64262011-06-29 19:33:04 +00003336/// Given a register class constraint, like 'r', if this corresponds directly
3337/// to an LLVM register class, return a register of 0 and the register class
3338/// pointer.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003339std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
Owen Andersone50ed302009-08-10 22:56:29 +00003340getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003341{
3342 if (Constraint.size() == 1) {
3343 switch (Constraint[0]) {
Eric Christopher314aff12011-06-29 19:04:31 +00003344 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3345 case 'y': // Same as 'r'. Exists for compatibility.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003346 case 'r':
Akira Hatanakaafc945b2012-09-12 23:27:55 +00003347 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3348 if (Subtarget->inMips16Mode())
3349 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
Craig Topper420761a2012-04-20 07:30:17 +00003350 return std::make_pair(0U, &Mips::CPURegsRegClass);
Akira Hatanakaafc945b2012-09-12 23:27:55 +00003351 }
Jack Carter10de0252012-07-02 23:35:23 +00003352 if (VT == MVT::i64 && !HasMips64)
3353 return std::make_pair(0U, &Mips::CPURegsRegClass);
Eric Christopher0ed1f762012-05-07 03:13:22 +00003354 if (VT == MVT::i64 && HasMips64)
3355 return std::make_pair(0U, &Mips::CPU64RegsRegClass);
3356 // This will generate an error message
3357 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003358 case 'f':
Owen Anderson825b72b2009-08-11 20:47:22 +00003359 if (VT == MVT::f32)
Craig Topper420761a2012-04-20 07:30:17 +00003360 return std::make_pair(0U, &Mips::FGR32RegClass);
Akira Hatanakacb9dd722012-01-04 02:45:01 +00003361 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
3362 if (Subtarget->isFP64bit())
Craig Topper420761a2012-04-20 07:30:17 +00003363 return std::make_pair(0U, &Mips::FGR64RegClass);
3364 return std::make_pair(0U, &Mips::AFGR64RegClass);
Akira Hatanakacb9dd722012-01-04 02:45:01 +00003365 }
Eric Christopher1d5a3922012-05-07 06:25:10 +00003366 break;
3367 case 'c': // register suitable for indirect jump
3368 if (VT == MVT::i32)
3369 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
3370 assert(VT == MVT::i64 && "Unexpected type.");
3371 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
Eric Christopher4adbefe2012-05-07 06:25:15 +00003372 case 'l': // register suitable for indirect jump
3373 if (VT == MVT::i32)
3374 return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass);
3375 return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass);
Eric Christopheraf97f732012-05-07 06:25:19 +00003376 case 'x': // register suitable for indirect jump
3377 // Fixme: Not triggering the use of both hi and low
3378 // This will generate an error message
3379 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003380 }
3381 }
3382 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3383}
3384
Eric Christopher50ab0392012-05-07 03:13:32 +00003385/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3386/// vector. If it is invalid, don't add anything to Ops.
3387void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3388 std::string &Constraint,
3389 std::vector<SDValue>&Ops,
3390 SelectionDAG &DAG) const {
3391 SDValue Result(0, 0);
3392
3393 // Only support length 1 constraints for now.
3394 if (Constraint.length() > 1) return;
3395
3396 char ConstraintLetter = Constraint[0];
3397 switch (ConstraintLetter) {
3398 default: break; // This will fall through to the generic implementation
3399 case 'I': // Signed 16 bit constant
3400 // If this fails, the parent routine will give an error
3401 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3402 EVT Type = Op.getValueType();
3403 int64_t Val = C->getSExtValue();
3404 if (isInt<16>(Val)) {
3405 Result = DAG.getTargetConstant(Val, Type);
3406 break;
3407 }
3408 }
3409 return;
Eric Christophere5076d42012-05-07 03:13:42 +00003410 case 'J': // integer zero
3411 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3412 EVT Type = Op.getValueType();
3413 int64_t Val = C->getZExtValue();
3414 if (Val == 0) {
3415 Result = DAG.getTargetConstant(0, Type);
3416 break;
3417 }
3418 }
3419 return;
Eric Christopherf49f8462012-05-07 05:46:29 +00003420 case 'K': // unsigned 16 bit immediate
3421 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3422 EVT Type = Op.getValueType();
3423 uint64_t Val = (uint64_t)C->getZExtValue();
3424 if (isUInt<16>(Val)) {
3425 Result = DAG.getTargetConstant(Val, Type);
3426 break;
3427 }
3428 }
3429 return;
Eric Christopher5ac47bb2012-05-07 05:46:37 +00003430 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3431 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3432 EVT Type = Op.getValueType();
3433 int64_t Val = C->getSExtValue();
3434 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3435 Result = DAG.getTargetConstant(Val, Type);
3436 break;
3437 }
3438 }
3439 return;
Eric Christopher60cfc792012-05-07 05:46:43 +00003440 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3441 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3442 EVT Type = Op.getValueType();
3443 int64_t Val = C->getSExtValue();
3444 if ((Val >= -65535) && (Val <= -1)) {
3445 Result = DAG.getTargetConstant(Val, Type);
3446 break;
3447 }
3448 }
3449 return;
Eric Christopher1ce20342012-05-07 05:46:48 +00003450 case 'O': // signed 15 bit immediate
3451 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3452 EVT Type = Op.getValueType();
3453 int64_t Val = C->getSExtValue();
3454 if ((isInt<15>(Val))) {
3455 Result = DAG.getTargetConstant(Val, Type);
3456 break;
3457 }
3458 }
3459 return;
Eric Christopher54412a72012-05-07 06:25:02 +00003460 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3461 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3462 EVT Type = Op.getValueType();
3463 int64_t Val = C->getSExtValue();
3464 if ((Val <= 65535) && (Val >= 1)) {
3465 Result = DAG.getTargetConstant(Val, Type);
3466 break;
3467 }
3468 }
3469 return;
Eric Christopher50ab0392012-05-07 03:13:32 +00003470 }
3471
3472 if (Result.getNode()) {
3473 Ops.push_back(Result);
3474 return;
3475 }
3476
3477 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3478}
3479
Dan Gohman6520e202008-10-18 02:06:02 +00003480bool
3481MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3482 // The Mips target isn't yet aware of offsets.
3483 return false;
3484}
Evan Chengeb2f9692009-10-27 19:56:55 +00003485
Akira Hatanakae193b322012-06-13 19:33:32 +00003486EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3487 unsigned SrcAlign, bool IsZeroVal,
3488 bool MemcpyStrSrc,
3489 MachineFunction &MF) const {
3490 if (Subtarget->hasMips64())
3491 return MVT::i64;
3492
3493 return MVT::i32;
3494}
3495
Evan Chenga1eaa3c2009-10-28 01:43:28 +00003496bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3497 if (VT != MVT::f32 && VT != MVT::f64)
3498 return false;
Bruno Cardoso Lopes6b902822011-01-18 19:41:41 +00003499 if (Imm.isNegZero())
3500 return false;
Evan Chengeb2f9692009-10-27 19:56:55 +00003501 return Imm.isZero();
3502}
Akira Hatanaka6c2cf8b2012-02-03 04:33:00 +00003503
3504unsigned MipsTargetLowering::getJumpTableEncoding() const {
3505 if (IsN64)
3506 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
Jia Liubb481f82012-02-28 07:46:26 +00003507
Akira Hatanaka6c2cf8b2012-02-03 04:33:00 +00003508 return TargetLowering::getJumpTableEncoding();
3509}