Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1 | //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by Chris Lattner and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines the interfaces that X86 uses to lower LLVM code into a |
| 11 | // selection DAG. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #include "X86.h" |
| 16 | #include "X86ISelLowering.h" |
| 17 | #include "X86TargetMachine.h" |
| 18 | #include "llvm/CallingConv.h" |
| 19 | #include "llvm/Function.h" |
| 20 | #include "llvm/CodeGen/MachineFunction.h" |
| 21 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 22 | #include "llvm/CodeGen/SelectionDAG.h" |
| 23 | #include "llvm/CodeGen/SSARegMap.h" |
| 24 | #include "llvm/Target/TargetOptions.h" |
| 25 | using namespace llvm; |
| 26 | |
| 27 | // FIXME: temporary. |
| 28 | #include "llvm/Support/CommandLine.h" |
| 29 | static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden, |
| 30 | cl::desc("Enable fastcc on X86")); |
| 31 | |
| 32 | X86TargetLowering::X86TargetLowering(TargetMachine &TM) |
| 33 | : TargetLowering(TM) { |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 34 | // Set up the TargetLowering object. |
| 35 | |
| 36 | // X86 is weird, it always uses i8 for shift amounts and setcc results. |
| 37 | setShiftAmountType(MVT::i8); |
| 38 | setSetCCResultType(MVT::i8); |
| 39 | setSetCCResultContents(ZeroOrOneSetCCResult); |
| 40 | setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 |
| 41 | |
| 42 | // Set up the register classes. |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 43 | addRegisterClass(MVT::i8, X86::R8RegisterClass); |
| 44 | addRegisterClass(MVT::i16, X86::R16RegisterClass); |
| 45 | addRegisterClass(MVT::i32, X86::R32RegisterClass); |
| 46 | |
| 47 | // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this |
| 48 | // operation. |
| 49 | setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); |
| 50 | setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); |
| 51 | setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); |
| 52 | setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); |
| 53 | |
| 54 | // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have |
| 55 | // this operation. |
| 56 | setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); |
| 57 | setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); |
| 58 | |
| 59 | if (!X86ScalarSSE) { |
| 60 | // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64 |
| 61 | // isn't legal. |
| 62 | setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); |
| 63 | setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); |
| 64 | setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); |
| 65 | setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); |
| 66 | } |
| 67 | |
| 68 | // Handle FP_TO_UINT by promoting the destination to a larger signed |
| 69 | // conversion. |
| 70 | setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); |
| 71 | setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); |
| 72 | setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); |
| 73 | |
| 74 | if (!X86ScalarSSE) |
| 75 | setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); |
| 76 | |
| 77 | // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have |
| 78 | // this operation. |
| 79 | setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); |
| 80 | setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); |
| 81 | setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); |
| 82 | |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 83 | if (X86DAGIsel) { |
| 84 | setOperationAction(ISD::BRCOND , MVT::Other, Custom); |
| 85 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 86 | setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand); |
| 87 | setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand); |
| 88 | setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); |
| 89 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); |
Chris Lattner | e80242a | 2005-12-07 17:59:14 +0000 | [diff] [blame] | 90 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 91 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); |
| 92 | setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); |
| 93 | setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand); |
| 94 | setOperationAction(ISD::FREM , MVT::f64 , Expand); |
| 95 | setOperationAction(ISD::CTPOP , MVT::i8 , Expand); |
| 96 | setOperationAction(ISD::CTTZ , MVT::i8 , Expand); |
| 97 | setOperationAction(ISD::CTLZ , MVT::i8 , Expand); |
| 98 | setOperationAction(ISD::CTPOP , MVT::i16 , Expand); |
| 99 | setOperationAction(ISD::CTTZ , MVT::i16 , Expand); |
| 100 | setOperationAction(ISD::CTLZ , MVT::i16 , Expand); |
| 101 | setOperationAction(ISD::CTPOP , MVT::i32 , Expand); |
| 102 | setOperationAction(ISD::CTTZ , MVT::i32 , Expand); |
| 103 | setOperationAction(ISD::CTLZ , MVT::i32 , Expand); |
Andrew Lenharth | b873ff3 | 2005-11-20 21:41:10 +0000 | [diff] [blame] | 104 | setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 105 | |
| 106 | setOperationAction(ISD::READIO , MVT::i1 , Expand); |
| 107 | setOperationAction(ISD::READIO , MVT::i8 , Expand); |
| 108 | setOperationAction(ISD::READIO , MVT::i16 , Expand); |
| 109 | setOperationAction(ISD::READIO , MVT::i32 , Expand); |
| 110 | setOperationAction(ISD::WRITEIO , MVT::i1 , Expand); |
| 111 | setOperationAction(ISD::WRITEIO , MVT::i8 , Expand); |
| 112 | setOperationAction(ISD::WRITEIO , MVT::i16 , Expand); |
| 113 | setOperationAction(ISD::WRITEIO , MVT::i32 , Expand); |
| 114 | |
| 115 | // These should be promoted to a larger select which is supported. |
| 116 | setOperationAction(ISD::SELECT , MVT::i1 , Promote); |
| 117 | setOperationAction(ISD::SELECT , MVT::i8 , Promote); |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 118 | // X86 wants to expand cmov itself. |
| 119 | if (X86DAGIsel) { |
| 120 | setOperationAction(ISD::SELECT , MVT::i16 , Custom); |
| 121 | setOperationAction(ISD::SELECT , MVT::i32 , Custom); |
| 122 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 123 | |
Chris Lattner | f73bae1 | 2005-11-29 06:16:21 +0000 | [diff] [blame] | 124 | // We don't have line number support yet. |
| 125 | setOperationAction(ISD::LOCATION, MVT::Other, Expand); |
| 126 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 127 | if (X86ScalarSSE) { |
| 128 | // Set up the FP register classes. |
| 129 | addRegisterClass(MVT::f32, X86::V4F4RegisterClass); |
| 130 | addRegisterClass(MVT::f64, X86::V2F8RegisterClass); |
| 131 | |
| 132 | // SSE has no load+extend ops |
| 133 | setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); |
| 134 | setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand); |
| 135 | |
| 136 | // SSE has no i16 to fp conversion, only i32 |
| 137 | setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); |
| 138 | setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); |
| 139 | |
| 140 | // Expand FP_TO_UINT into a select. |
| 141 | // FIXME: We would like to use a Custom expander here eventually to do |
| 142 | // the optimal thing for SSE vs. the default expansion in the legalizer. |
| 143 | setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); |
| 144 | |
| 145 | // We don't support sin/cos/sqrt/fmod |
| 146 | setOperationAction(ISD::FSIN , MVT::f64, Expand); |
| 147 | setOperationAction(ISD::FCOS , MVT::f64, Expand); |
| 148 | setOperationAction(ISD::FABS , MVT::f64, Expand); |
| 149 | setOperationAction(ISD::FNEG , MVT::f64, Expand); |
| 150 | setOperationAction(ISD::FREM , MVT::f64, Expand); |
| 151 | setOperationAction(ISD::FSIN , MVT::f32, Expand); |
| 152 | setOperationAction(ISD::FCOS , MVT::f32, Expand); |
| 153 | setOperationAction(ISD::FABS , MVT::f32, Expand); |
| 154 | setOperationAction(ISD::FNEG , MVT::f32, Expand); |
| 155 | setOperationAction(ISD::FREM , MVT::f32, Expand); |
| 156 | |
| 157 | addLegalFPImmediate(+0.0); // xorps / xorpd |
| 158 | } else { |
| 159 | // Set up the FP register classes. |
| 160 | addRegisterClass(MVT::f64, X86::RFPRegisterClass); |
| 161 | |
| 162 | if (!UnsafeFPMath) { |
| 163 | setOperationAction(ISD::FSIN , MVT::f64 , Expand); |
| 164 | setOperationAction(ISD::FCOS , MVT::f64 , Expand); |
| 165 | } |
| 166 | |
| 167 | addLegalFPImmediate(+0.0); // FLD0 |
| 168 | addLegalFPImmediate(+1.0); // FLD1 |
| 169 | addLegalFPImmediate(-0.0); // FLD0/FCHS |
| 170 | addLegalFPImmediate(-1.0); // FLD1/FCHS |
| 171 | } |
| 172 | computeRegisterProperties(); |
| 173 | |
| 174 | maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores |
| 175 | maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores |
| 176 | maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores |
| 177 | allowUnalignedMemoryAccesses = true; // x86 supports it! |
| 178 | } |
| 179 | |
| 180 | std::vector<SDOperand> |
| 181 | X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { |
| 182 | if (F.getCallingConv() == CallingConv::Fast && EnableFastCC) |
| 183 | return LowerFastCCArguments(F, DAG); |
| 184 | return LowerCCCArguments(F, DAG); |
| 185 | } |
| 186 | |
| 187 | std::pair<SDOperand, SDOperand> |
| 188 | X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, |
| 189 | bool isVarArg, unsigned CallingConv, |
| 190 | bool isTailCall, |
| 191 | SDOperand Callee, ArgListTy &Args, |
| 192 | SelectionDAG &DAG) { |
| 193 | assert((!isVarArg || CallingConv == CallingConv::C) && |
| 194 | "Only C takes varargs!"); |
| 195 | if (CallingConv == CallingConv::Fast && EnableFastCC) |
| 196 | return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG); |
| 197 | return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG); |
| 198 | } |
| 199 | |
| 200 | //===----------------------------------------------------------------------===// |
| 201 | // C Calling Convention implementation |
| 202 | //===----------------------------------------------------------------------===// |
| 203 | |
| 204 | std::vector<SDOperand> |
| 205 | X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) { |
| 206 | std::vector<SDOperand> ArgValues; |
| 207 | |
| 208 | MachineFunction &MF = DAG.getMachineFunction(); |
| 209 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 210 | |
| 211 | // Add DAG nodes to load the arguments... On entry to a function on the X86, |
| 212 | // the stack frame looks like this: |
| 213 | // |
| 214 | // [ESP] -- return address |
| 215 | // [ESP + 4] -- first argument (leftmost lexically) |
| 216 | // [ESP + 8] -- second argument, if first argument is four bytes in size |
| 217 | // ... |
| 218 | // |
| 219 | unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot |
| 220 | for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { |
| 221 | MVT::ValueType ObjectVT = getValueType(I->getType()); |
| 222 | unsigned ArgIncrement = 4; |
| 223 | unsigned ObjSize; |
| 224 | switch (ObjectVT) { |
| 225 | default: assert(0 && "Unhandled argument type!"); |
| 226 | case MVT::i1: |
| 227 | case MVT::i8: ObjSize = 1; break; |
| 228 | case MVT::i16: ObjSize = 2; break; |
| 229 | case MVT::i32: ObjSize = 4; break; |
| 230 | case MVT::i64: ObjSize = ArgIncrement = 8; break; |
| 231 | case MVT::f32: ObjSize = 4; break; |
| 232 | case MVT::f64: ObjSize = ArgIncrement = 8; break; |
| 233 | } |
| 234 | // Create the frame index object for this incoming parameter... |
| 235 | int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); |
| 236 | |
| 237 | // Create the SelectionDAG nodes corresponding to a load from this parameter |
| 238 | SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); |
| 239 | |
| 240 | // Don't codegen dead arguments. FIXME: remove this check when we can nuke |
| 241 | // dead loads. |
| 242 | SDOperand ArgValue; |
| 243 | if (!I->use_empty()) |
| 244 | ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, |
| 245 | DAG.getSrcValue(NULL)); |
| 246 | else { |
| 247 | if (MVT::isInteger(ObjectVT)) |
| 248 | ArgValue = DAG.getConstant(0, ObjectVT); |
| 249 | else |
| 250 | ArgValue = DAG.getConstantFP(0, ObjectVT); |
| 251 | } |
| 252 | ArgValues.push_back(ArgValue); |
| 253 | |
| 254 | ArgOffset += ArgIncrement; // Move on to the next argument... |
| 255 | } |
| 256 | |
| 257 | // If the function takes variable number of arguments, make a frame index for |
| 258 | // the start of the first vararg value... for expansion of llvm.va_start. |
| 259 | if (F.isVarArg()) |
| 260 | VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset); |
| 261 | ReturnAddrIndex = 0; // No return address slot generated yet. |
| 262 | BytesToPopOnReturn = 0; // Callee pops nothing. |
| 263 | BytesCallerReserves = ArgOffset; |
| 264 | |
| 265 | // Finally, inform the code generator which regs we return values in. |
| 266 | switch (getValueType(F.getReturnType())) { |
| 267 | default: assert(0 && "Unknown type!"); |
| 268 | case MVT::isVoid: break; |
| 269 | case MVT::i1: |
| 270 | case MVT::i8: |
| 271 | case MVT::i16: |
| 272 | case MVT::i32: |
| 273 | MF.addLiveOut(X86::EAX); |
| 274 | break; |
| 275 | case MVT::i64: |
| 276 | MF.addLiveOut(X86::EAX); |
| 277 | MF.addLiveOut(X86::EDX); |
| 278 | break; |
| 279 | case MVT::f32: |
| 280 | case MVT::f64: |
| 281 | MF.addLiveOut(X86::ST0); |
| 282 | break; |
| 283 | } |
| 284 | return ArgValues; |
| 285 | } |
| 286 | |
| 287 | std::pair<SDOperand, SDOperand> |
| 288 | X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy, |
| 289 | bool isVarArg, bool isTailCall, |
| 290 | SDOperand Callee, ArgListTy &Args, |
| 291 | SelectionDAG &DAG) { |
| 292 | // Count how many bytes are to be pushed on the stack. |
| 293 | unsigned NumBytes = 0; |
| 294 | |
| 295 | if (Args.empty()) { |
| 296 | // Save zero bytes. |
| 297 | Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, |
| 298 | DAG.getConstant(0, getPointerTy())); |
| 299 | } else { |
| 300 | for (unsigned i = 0, e = Args.size(); i != e; ++i) |
| 301 | switch (getValueType(Args[i].second)) { |
| 302 | default: assert(0 && "Unknown value type!"); |
| 303 | case MVT::i1: |
| 304 | case MVT::i8: |
| 305 | case MVT::i16: |
| 306 | case MVT::i32: |
| 307 | case MVT::f32: |
| 308 | NumBytes += 4; |
| 309 | break; |
| 310 | case MVT::i64: |
| 311 | case MVT::f64: |
| 312 | NumBytes += 8; |
| 313 | break; |
| 314 | } |
| 315 | |
| 316 | Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, |
| 317 | DAG.getConstant(NumBytes, getPointerTy())); |
| 318 | |
| 319 | // Arguments go on the stack in reverse order, as specified by the ABI. |
| 320 | unsigned ArgOffset = 0; |
| 321 | SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), |
| 322 | X86::ESP, MVT::i32); |
| 323 | std::vector<SDOperand> Stores; |
| 324 | |
| 325 | for (unsigned i = 0, e = Args.size(); i != e; ++i) { |
| 326 | SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); |
| 327 | PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); |
| 328 | |
| 329 | switch (getValueType(Args[i].second)) { |
| 330 | default: assert(0 && "Unexpected ValueType for argument!"); |
| 331 | case MVT::i1: |
| 332 | case MVT::i8: |
| 333 | case MVT::i16: |
| 334 | // Promote the integer to 32 bits. If the input type is signed use a |
| 335 | // sign extend, otherwise use a zero extend. |
| 336 | if (Args[i].second->isSigned()) |
| 337 | Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first); |
| 338 | else |
| 339 | Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first); |
| 340 | |
| 341 | // FALL THROUGH |
| 342 | case MVT::i32: |
| 343 | case MVT::f32: |
| 344 | Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, |
| 345 | Args[i].first, PtrOff, |
| 346 | DAG.getSrcValue(NULL))); |
| 347 | ArgOffset += 4; |
| 348 | break; |
| 349 | case MVT::i64: |
| 350 | case MVT::f64: |
| 351 | Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, |
| 352 | Args[i].first, PtrOff, |
| 353 | DAG.getSrcValue(NULL))); |
| 354 | ArgOffset += 8; |
| 355 | break; |
| 356 | } |
| 357 | } |
| 358 | Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); |
| 359 | } |
| 360 | |
| 361 | std::vector<MVT::ValueType> RetVals; |
| 362 | MVT::ValueType RetTyVT = getValueType(RetTy); |
| 363 | RetVals.push_back(MVT::Other); |
| 364 | |
| 365 | // The result values produced have to be legal. Promote the result. |
| 366 | switch (RetTyVT) { |
| 367 | case MVT::isVoid: break; |
| 368 | default: |
| 369 | RetVals.push_back(RetTyVT); |
| 370 | break; |
| 371 | case MVT::i1: |
| 372 | case MVT::i8: |
| 373 | case MVT::i16: |
| 374 | RetVals.push_back(MVT::i32); |
| 375 | break; |
| 376 | case MVT::f32: |
| 377 | if (X86ScalarSSE) |
| 378 | RetVals.push_back(MVT::f32); |
| 379 | else |
| 380 | RetVals.push_back(MVT::f64); |
| 381 | break; |
| 382 | case MVT::i64: |
| 383 | RetVals.push_back(MVT::i32); |
| 384 | RetVals.push_back(MVT::i32); |
| 385 | break; |
| 386 | } |
| 387 | std::vector<SDOperand> Ops; |
| 388 | Ops.push_back(Chain); |
| 389 | Ops.push_back(Callee); |
| 390 | Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); |
| 391 | Ops.push_back(DAG.getConstant(0, getPointerTy())); |
| 392 | SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, |
| 393 | RetVals, Ops); |
| 394 | Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall); |
| 395 | |
| 396 | SDOperand ResultVal; |
| 397 | switch (RetTyVT) { |
| 398 | case MVT::isVoid: break; |
| 399 | default: |
| 400 | ResultVal = TheCall.getValue(1); |
| 401 | break; |
| 402 | case MVT::i1: |
| 403 | case MVT::i8: |
| 404 | case MVT::i16: |
| 405 | ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1)); |
| 406 | break; |
| 407 | case MVT::f32: |
| 408 | // FIXME: we would really like to remember that this FP_ROUND operation is |
| 409 | // okay to eliminate if we allow excess FP precision. |
| 410 | ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1)); |
| 411 | break; |
| 412 | case MVT::i64: |
| 413 | ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1), |
| 414 | TheCall.getValue(2)); |
| 415 | break; |
| 416 | } |
| 417 | |
| 418 | return std::make_pair(ResultVal, Chain); |
| 419 | } |
| 420 | |
| 421 | SDOperand |
| 422 | X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP, |
| 423 | Value *VAListV, SelectionDAG &DAG) { |
| 424 | // vastart just stores the address of the VarArgsFrameIndex slot. |
| 425 | SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); |
| 426 | return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP, |
| 427 | DAG.getSrcValue(VAListV)); |
| 428 | } |
| 429 | |
| 430 | |
| 431 | std::pair<SDOperand,SDOperand> |
| 432 | X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP, |
| 433 | Value *VAListV, const Type *ArgTy, |
| 434 | SelectionDAG &DAG) { |
| 435 | MVT::ValueType ArgVT = getValueType(ArgTy); |
| 436 | SDOperand Val = DAG.getLoad(MVT::i32, Chain, |
| 437 | VAListP, DAG.getSrcValue(VAListV)); |
| 438 | SDOperand Result = DAG.getLoad(ArgVT, Chain, Val, |
| 439 | DAG.getSrcValue(NULL)); |
| 440 | unsigned Amt; |
| 441 | if (ArgVT == MVT::i32) |
| 442 | Amt = 4; |
| 443 | else { |
| 444 | assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) && |
| 445 | "Other types should have been promoted for varargs!"); |
| 446 | Amt = 8; |
| 447 | } |
| 448 | Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val, |
| 449 | DAG.getConstant(Amt, Val.getValueType())); |
| 450 | Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, |
| 451 | Val, VAListP, DAG.getSrcValue(VAListV)); |
| 452 | return std::make_pair(Result, Chain); |
| 453 | } |
| 454 | |
| 455 | //===----------------------------------------------------------------------===// |
| 456 | // Fast Calling Convention implementation |
| 457 | //===----------------------------------------------------------------------===// |
| 458 | // |
| 459 | // The X86 'fast' calling convention passes up to two integer arguments in |
| 460 | // registers (an appropriate portion of EAX/EDX), passes arguments in C order, |
| 461 | // and requires that the callee pop its arguments off the stack (allowing proper |
| 462 | // tail calls), and has the same return value conventions as C calling convs. |
| 463 | // |
| 464 | // This calling convention always arranges for the callee pop value to be 8n+4 |
| 465 | // bytes, which is needed for tail recursion elimination and stack alignment |
| 466 | // reasons. |
| 467 | // |
| 468 | // Note that this can be enhanced in the future to pass fp vals in registers |
| 469 | // (when we have a global fp allocator) and do other tricks. |
| 470 | // |
| 471 | |
| 472 | /// AddLiveIn - This helper function adds the specified physical register to the |
| 473 | /// MachineFunction as a live in value. It also creates a corresponding virtual |
| 474 | /// register for it. |
| 475 | static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, |
| 476 | TargetRegisterClass *RC) { |
| 477 | assert(RC->contains(PReg) && "Not the correct regclass!"); |
| 478 | unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); |
| 479 | MF.addLiveIn(PReg, VReg); |
| 480 | return VReg; |
| 481 | } |
| 482 | |
| 483 | |
| 484 | std::vector<SDOperand> |
| 485 | X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) { |
| 486 | std::vector<SDOperand> ArgValues; |
| 487 | |
| 488 | MachineFunction &MF = DAG.getMachineFunction(); |
| 489 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 490 | |
| 491 | // Add DAG nodes to load the arguments... On entry to a function the stack |
| 492 | // frame looks like this: |
| 493 | // |
| 494 | // [ESP] -- return address |
| 495 | // [ESP + 4] -- first nonreg argument (leftmost lexically) |
| 496 | // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size |
| 497 | // ... |
| 498 | unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot |
| 499 | |
| 500 | // Keep track of the number of integer regs passed so far. This can be either |
| 501 | // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both |
| 502 | // used). |
| 503 | unsigned NumIntRegs = 0; |
| 504 | |
| 505 | for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { |
| 506 | MVT::ValueType ObjectVT = getValueType(I->getType()); |
| 507 | unsigned ArgIncrement = 4; |
| 508 | unsigned ObjSize = 0; |
| 509 | SDOperand ArgValue; |
| 510 | |
| 511 | switch (ObjectVT) { |
| 512 | default: assert(0 && "Unhandled argument type!"); |
| 513 | case MVT::i1: |
| 514 | case MVT::i8: |
| 515 | if (NumIntRegs < 2) { |
| 516 | if (!I->use_empty()) { |
| 517 | unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL, |
| 518 | X86::R8RegisterClass); |
| 519 | ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8); |
| 520 | DAG.setRoot(ArgValue.getValue(1)); |
| 521 | } |
| 522 | ++NumIntRegs; |
| 523 | break; |
| 524 | } |
| 525 | |
| 526 | ObjSize = 1; |
| 527 | break; |
| 528 | case MVT::i16: |
| 529 | if (NumIntRegs < 2) { |
| 530 | if (!I->use_empty()) { |
| 531 | unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX, |
| 532 | X86::R16RegisterClass); |
| 533 | ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16); |
| 534 | DAG.setRoot(ArgValue.getValue(1)); |
| 535 | } |
| 536 | ++NumIntRegs; |
| 537 | break; |
| 538 | } |
| 539 | ObjSize = 2; |
| 540 | break; |
| 541 | case MVT::i32: |
| 542 | if (NumIntRegs < 2) { |
| 543 | if (!I->use_empty()) { |
| 544 | unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX, |
| 545 | X86::R32RegisterClass); |
| 546 | ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); |
| 547 | DAG.setRoot(ArgValue.getValue(1)); |
| 548 | } |
| 549 | ++NumIntRegs; |
| 550 | break; |
| 551 | } |
| 552 | ObjSize = 4; |
| 553 | break; |
| 554 | case MVT::i64: |
| 555 | if (NumIntRegs == 0) { |
| 556 | if (!I->use_empty()) { |
| 557 | unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass); |
| 558 | unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass); |
| 559 | |
| 560 | SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32); |
| 561 | SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32); |
| 562 | DAG.setRoot(Hi.getValue(1)); |
| 563 | |
| 564 | ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi); |
| 565 | } |
| 566 | NumIntRegs = 2; |
| 567 | break; |
| 568 | } else if (NumIntRegs == 1) { |
| 569 | if (!I->use_empty()) { |
| 570 | unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass); |
| 571 | SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32); |
| 572 | DAG.setRoot(Low.getValue(1)); |
| 573 | |
| 574 | // Load the high part from memory. |
| 575 | // Create the frame index object for this incoming parameter... |
| 576 | int FI = MFI->CreateFixedObject(4, ArgOffset); |
| 577 | SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); |
| 578 | SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, |
| 579 | DAG.getSrcValue(NULL)); |
| 580 | ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi); |
| 581 | } |
| 582 | ArgOffset += 4; |
| 583 | NumIntRegs = 2; |
| 584 | break; |
| 585 | } |
| 586 | ObjSize = ArgIncrement = 8; |
| 587 | break; |
| 588 | case MVT::f32: ObjSize = 4; break; |
| 589 | case MVT::f64: ObjSize = ArgIncrement = 8; break; |
| 590 | } |
| 591 | |
| 592 | // Don't codegen dead arguments. FIXME: remove this check when we can nuke |
| 593 | // dead loads. |
| 594 | if (ObjSize && !I->use_empty()) { |
| 595 | // Create the frame index object for this incoming parameter... |
| 596 | int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); |
| 597 | |
| 598 | // Create the SelectionDAG nodes corresponding to a load from this |
| 599 | // parameter. |
| 600 | SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); |
| 601 | |
| 602 | ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, |
| 603 | DAG.getSrcValue(NULL)); |
| 604 | } else if (ArgValue.Val == 0) { |
| 605 | if (MVT::isInteger(ObjectVT)) |
| 606 | ArgValue = DAG.getConstant(0, ObjectVT); |
| 607 | else |
| 608 | ArgValue = DAG.getConstantFP(0, ObjectVT); |
| 609 | } |
| 610 | ArgValues.push_back(ArgValue); |
| 611 | |
| 612 | if (ObjSize) |
| 613 | ArgOffset += ArgIncrement; // Move on to the next argument. |
| 614 | } |
| 615 | |
| 616 | // Make sure the instruction takes 8n+4 bytes to make sure the start of the |
| 617 | // arguments and the arguments after the retaddr has been pushed are aligned. |
| 618 | if ((ArgOffset & 7) == 0) |
| 619 | ArgOffset += 4; |
| 620 | |
| 621 | VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. |
| 622 | ReturnAddrIndex = 0; // No return address slot generated yet. |
| 623 | BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments. |
| 624 | BytesCallerReserves = 0; |
| 625 | |
| 626 | // Finally, inform the code generator which regs we return values in. |
| 627 | switch (getValueType(F.getReturnType())) { |
| 628 | default: assert(0 && "Unknown type!"); |
| 629 | case MVT::isVoid: break; |
| 630 | case MVT::i1: |
| 631 | case MVT::i8: |
| 632 | case MVT::i16: |
| 633 | case MVT::i32: |
| 634 | MF.addLiveOut(X86::EAX); |
| 635 | break; |
| 636 | case MVT::i64: |
| 637 | MF.addLiveOut(X86::EAX); |
| 638 | MF.addLiveOut(X86::EDX); |
| 639 | break; |
| 640 | case MVT::f32: |
| 641 | case MVT::f64: |
| 642 | MF.addLiveOut(X86::ST0); |
| 643 | break; |
| 644 | } |
| 645 | return ArgValues; |
| 646 | } |
| 647 | |
| 648 | std::pair<SDOperand, SDOperand> |
| 649 | X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy, |
| 650 | bool isTailCall, SDOperand Callee, |
| 651 | ArgListTy &Args, SelectionDAG &DAG) { |
| 652 | // Count how many bytes are to be pushed on the stack. |
| 653 | unsigned NumBytes = 0; |
| 654 | |
| 655 | // Keep track of the number of integer regs passed so far. This can be either |
| 656 | // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both |
| 657 | // used). |
| 658 | unsigned NumIntRegs = 0; |
| 659 | |
| 660 | for (unsigned i = 0, e = Args.size(); i != e; ++i) |
| 661 | switch (getValueType(Args[i].second)) { |
| 662 | default: assert(0 && "Unknown value type!"); |
| 663 | case MVT::i1: |
| 664 | case MVT::i8: |
| 665 | case MVT::i16: |
| 666 | case MVT::i32: |
| 667 | if (NumIntRegs < 2) { |
| 668 | ++NumIntRegs; |
| 669 | break; |
| 670 | } |
| 671 | // fall through |
| 672 | case MVT::f32: |
| 673 | NumBytes += 4; |
| 674 | break; |
| 675 | case MVT::i64: |
| 676 | if (NumIntRegs == 0) { |
| 677 | NumIntRegs = 2; |
| 678 | break; |
| 679 | } else if (NumIntRegs == 1) { |
| 680 | NumIntRegs = 2; |
| 681 | NumBytes += 4; |
| 682 | break; |
| 683 | } |
| 684 | |
| 685 | // fall through |
| 686 | case MVT::f64: |
| 687 | NumBytes += 8; |
| 688 | break; |
| 689 | } |
| 690 | |
| 691 | // Make sure the instruction takes 8n+4 bytes to make sure the start of the |
| 692 | // arguments and the arguments after the retaddr has been pushed are aligned. |
| 693 | if ((NumBytes & 7) == 0) |
| 694 | NumBytes += 4; |
| 695 | |
| 696 | Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, |
| 697 | DAG.getConstant(NumBytes, getPointerTy())); |
| 698 | |
| 699 | // Arguments go on the stack in reverse order, as specified by the ABI. |
| 700 | unsigned ArgOffset = 0; |
| 701 | SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), |
| 702 | X86::ESP, MVT::i32); |
| 703 | NumIntRegs = 0; |
| 704 | std::vector<SDOperand> Stores; |
| 705 | std::vector<SDOperand> RegValuesToPass; |
| 706 | for (unsigned i = 0, e = Args.size(); i != e; ++i) { |
| 707 | switch (getValueType(Args[i].second)) { |
| 708 | default: assert(0 && "Unexpected ValueType for argument!"); |
| 709 | case MVT::i1: |
| 710 | case MVT::i8: |
| 711 | case MVT::i16: |
| 712 | case MVT::i32: |
| 713 | if (NumIntRegs < 2) { |
| 714 | RegValuesToPass.push_back(Args[i].first); |
| 715 | ++NumIntRegs; |
| 716 | break; |
| 717 | } |
| 718 | // Fall through |
| 719 | case MVT::f32: { |
| 720 | SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); |
| 721 | PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); |
| 722 | Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, |
| 723 | Args[i].first, PtrOff, |
| 724 | DAG.getSrcValue(NULL))); |
| 725 | ArgOffset += 4; |
| 726 | break; |
| 727 | } |
| 728 | case MVT::i64: |
| 729 | if (NumIntRegs < 2) { // Can pass part of it in regs? |
| 730 | SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, |
| 731 | Args[i].first, DAG.getConstant(1, MVT::i32)); |
| 732 | SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, |
| 733 | Args[i].first, DAG.getConstant(0, MVT::i32)); |
| 734 | RegValuesToPass.push_back(Lo); |
| 735 | ++NumIntRegs; |
| 736 | if (NumIntRegs < 2) { // Pass both parts in regs? |
| 737 | RegValuesToPass.push_back(Hi); |
| 738 | ++NumIntRegs; |
| 739 | } else { |
| 740 | // Pass the high part in memory. |
| 741 | SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); |
| 742 | PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); |
| 743 | Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, |
| 744 | Hi, PtrOff, DAG.getSrcValue(NULL))); |
| 745 | ArgOffset += 4; |
| 746 | } |
| 747 | break; |
| 748 | } |
| 749 | // Fall through |
| 750 | case MVT::f64: |
| 751 | SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); |
| 752 | PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); |
| 753 | Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, |
| 754 | Args[i].first, PtrOff, |
| 755 | DAG.getSrcValue(NULL))); |
| 756 | ArgOffset += 8; |
| 757 | break; |
| 758 | } |
| 759 | } |
| 760 | if (!Stores.empty()) |
| 761 | Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); |
| 762 | |
| 763 | // Make sure the instruction takes 8n+4 bytes to make sure the start of the |
| 764 | // arguments and the arguments after the retaddr has been pushed are aligned. |
| 765 | if ((ArgOffset & 7) == 0) |
| 766 | ArgOffset += 4; |
| 767 | |
| 768 | std::vector<MVT::ValueType> RetVals; |
| 769 | MVT::ValueType RetTyVT = getValueType(RetTy); |
| 770 | |
| 771 | RetVals.push_back(MVT::Other); |
| 772 | |
| 773 | // The result values produced have to be legal. Promote the result. |
| 774 | switch (RetTyVT) { |
| 775 | case MVT::isVoid: break; |
| 776 | default: |
| 777 | RetVals.push_back(RetTyVT); |
| 778 | break; |
| 779 | case MVT::i1: |
| 780 | case MVT::i8: |
| 781 | case MVT::i16: |
| 782 | RetVals.push_back(MVT::i32); |
| 783 | break; |
| 784 | case MVT::f32: |
| 785 | if (X86ScalarSSE) |
| 786 | RetVals.push_back(MVT::f32); |
| 787 | else |
| 788 | RetVals.push_back(MVT::f64); |
| 789 | break; |
| 790 | case MVT::i64: |
| 791 | RetVals.push_back(MVT::i32); |
| 792 | RetVals.push_back(MVT::i32); |
| 793 | break; |
| 794 | } |
| 795 | |
| 796 | std::vector<SDOperand> Ops; |
| 797 | Ops.push_back(Chain); |
| 798 | Ops.push_back(Callee); |
| 799 | Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy())); |
| 800 | // Callee pops all arg values on the stack. |
| 801 | Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy())); |
| 802 | |
| 803 | // Pass register arguments as needed. |
| 804 | Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end()); |
| 805 | |
| 806 | SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, |
| 807 | RetVals, Ops); |
| 808 | Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall); |
| 809 | |
| 810 | SDOperand ResultVal; |
| 811 | switch (RetTyVT) { |
| 812 | case MVT::isVoid: break; |
| 813 | default: |
| 814 | ResultVal = TheCall.getValue(1); |
| 815 | break; |
| 816 | case MVT::i1: |
| 817 | case MVT::i8: |
| 818 | case MVT::i16: |
| 819 | ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1)); |
| 820 | break; |
| 821 | case MVT::f32: |
| 822 | // FIXME: we would really like to remember that this FP_ROUND operation is |
| 823 | // okay to eliminate if we allow excess FP precision. |
| 824 | ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1)); |
| 825 | break; |
| 826 | case MVT::i64: |
| 827 | ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1), |
| 828 | TheCall.getValue(2)); |
| 829 | break; |
| 830 | } |
| 831 | |
| 832 | return std::make_pair(ResultVal, Chain); |
| 833 | } |
| 834 | |
| 835 | SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { |
| 836 | if (ReturnAddrIndex == 0) { |
| 837 | // Set up a frame object for the return address. |
| 838 | MachineFunction &MF = DAG.getMachineFunction(); |
| 839 | ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4); |
| 840 | } |
| 841 | |
| 842 | return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32); |
| 843 | } |
| 844 | |
| 845 | |
| 846 | |
| 847 | std::pair<SDOperand, SDOperand> X86TargetLowering:: |
| 848 | LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth, |
| 849 | SelectionDAG &DAG) { |
| 850 | SDOperand Result; |
| 851 | if (Depth) // Depths > 0 not supported yet! |
| 852 | Result = DAG.getConstant(0, getPointerTy()); |
| 853 | else { |
| 854 | SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG); |
| 855 | if (!isFrameAddress) |
| 856 | // Just load the return address |
| 857 | Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI, |
| 858 | DAG.getSrcValue(NULL)); |
| 859 | else |
| 860 | Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI, |
| 861 | DAG.getConstant(4, MVT::i32)); |
| 862 | } |
| 863 | return std::make_pair(Result, Chain); |
| 864 | } |
| 865 | |
| 866 | //===----------------------------------------------------------------------===// |
| 867 | // X86 Custom Lowering Hooks |
| 868 | //===----------------------------------------------------------------------===// |
| 869 | |
| 870 | /// LowerOperation - Provide custom lowering hooks for some operations. |
| 871 | /// |
| 872 | SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { |
| 873 | switch (Op.getOpcode()) { |
| 874 | default: assert(0 && "Should not custom lower this!"); |
| 875 | case ISD::SINT_TO_FP: { |
| 876 | assert(Op.getValueType() == MVT::f64 && |
| 877 | Op.getOperand(0).getValueType() == MVT::i64 && |
| 878 | "Unknown SINT_TO_FP to lower!"); |
| 879 | // We lower sint64->FP into a store to a temporary stack slot, followed by a |
| 880 | // FILD64m node. |
| 881 | MachineFunction &MF = DAG.getMachineFunction(); |
| 882 | int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); |
| 883 | SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
| 884 | SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), |
| 885 | Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL)); |
| 886 | std::vector<MVT::ValueType> RTs; |
| 887 | RTs.push_back(MVT::f64); |
| 888 | RTs.push_back(MVT::Other); |
| 889 | std::vector<SDOperand> Ops; |
| 890 | Ops.push_back(Store); |
| 891 | Ops.push_back(StackSlot); |
| 892 | return DAG.getNode(X86ISD::FILD64m, RTs, Ops); |
| 893 | } |
| 894 | case ISD::FP_TO_SINT: { |
| 895 | assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 && |
| 896 | Op.getOperand(0).getValueType() == MVT::f64 && |
| 897 | "Unknown FP_TO_SINT to lower!"); |
| 898 | // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary |
| 899 | // stack slot. |
| 900 | MachineFunction &MF = DAG.getMachineFunction(); |
| 901 | unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8; |
| 902 | int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); |
| 903 | SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
| 904 | |
| 905 | unsigned Opc; |
| 906 | switch (Op.getValueType()) { |
| 907 | default: assert(0 && "Invalid FP_TO_SINT to lower!"); |
| 908 | case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; |
| 909 | case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; |
| 910 | case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; |
| 911 | } |
| 912 | |
| 913 | // Build the FP_TO_INT*_IN_MEM |
| 914 | std::vector<SDOperand> Ops; |
| 915 | Ops.push_back(DAG.getEntryNode()); |
| 916 | Ops.push_back(Op.getOperand(0)); |
| 917 | Ops.push_back(StackSlot); |
| 918 | SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops); |
| 919 | |
| 920 | // Load the result. |
| 921 | return DAG.getLoad(Op.getValueType(), FIST, StackSlot, |
| 922 | DAG.getSrcValue(NULL)); |
| 923 | } |
Andrew Lenharth | b873ff3 | 2005-11-20 21:41:10 +0000 | [diff] [blame] | 924 | case ISD::READCYCLECOUNTER: { |
Chris Lattner | 81363c3 | 2005-11-20 22:01:40 +0000 | [diff] [blame] | 925 | std::vector<MVT::ValueType> Tys; |
| 926 | Tys.push_back(MVT::Other); |
| 927 | Tys.push_back(MVT::Flag); |
| 928 | std::vector<SDOperand> Ops; |
| 929 | Ops.push_back(Op.getOperand(0)); |
| 930 | SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops); |
Chris Lattner | 81f803d | 2005-11-20 22:57:19 +0000 | [diff] [blame] | 931 | Ops.clear(); |
| 932 | Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1))); |
| 933 | Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX, |
| 934 | MVT::i32, Ops[0].getValue(2))); |
| 935 | Ops.push_back(Ops[1].getValue(1)); |
| 936 | Tys[0] = Tys[1] = MVT::i32; |
| 937 | Tys.push_back(MVT::Other); |
| 938 | return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); |
Andrew Lenharth | b873ff3 | 2005-11-20 21:41:10 +0000 | [diff] [blame] | 939 | } |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 940 | case ISD::SELECT: { |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 941 | SDOperand Cond = Op.getOperand(0); |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 942 | SDOperand CC; |
| 943 | if (Cond.getOpcode() == ISD::SETCC) { |
| 944 | CC = Cond.getOperand(2); |
| 945 | Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, |
| 946 | Cond.getOperand(0), Cond.getOperand(1)); |
| 947 | } else { |
| 948 | CC = DAG.getCondCode(ISD::SETEQ); |
| 949 | Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond); |
| 950 | } |
| 951 | return DAG.getNode(X86ISD::CMOV, Op.getValueType(), |
| 952 | Op.getOperand(1), Op.getOperand(2), CC, Cond); |
| 953 | } |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 954 | case ISD::BRCOND: { |
| 955 | SDOperand Chain = Op.getOperand(0); |
| 956 | SDOperand Cond = Op.getOperand(1); |
| 957 | SDOperand Dest = Op.getOperand(2); |
| 958 | SDOperand CC; |
| 959 | // TODO: handle Cond == OR / AND / XOR |
| 960 | if (Cond.getOpcode() == ISD::SETCC) { |
| 961 | CC = Cond.getOperand(2); |
| 962 | Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, |
| 963 | Cond.getOperand(0), Cond.getOperand(1)); |
| 964 | } else { |
| 965 | CC = DAG.getCondCode(ISD::SETNE); |
| 966 | Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond); |
| 967 | } |
| 968 | return DAG.getNode(X86ISD::BRCOND, Op.getValueType(), |
| 969 | Op.getOperand(0), Op.getOperand(2), CC, Cond); |
| 970 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 971 | } |
| 972 | } |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame^] | 973 | |
| 974 | const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { |
| 975 | switch (Opcode) { |
| 976 | default: return NULL; |
| 977 | case X86ISD::FILD64m: return "X86ISD::FILD64m"; |
| 978 | case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; |
| 979 | case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; |
| 980 | case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; |
| 981 | case X86ISD::CALL: return "X86ISD::CALL"; |
| 982 | case X86ISD::TAILCALL: return "X86ISD::TAILCALL"; |
| 983 | case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; |
| 984 | case X86ISD::CMP: return "X86ISD::CMP"; |
| 985 | case X86ISD::TEST: return "X86ISD::TEST"; |
| 986 | case X86ISD::CMOV: return "X86ISD::CMOV"; |
| 987 | case X86ISD::BRCOND: return "X86ISD::BRCOND"; |
| 988 | } |
| 989 | } |