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Chris Lattner1c08c712005-01-07 07:47:53 +00001//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
Misha Brukmanedf128a2005-04-21 22:36:52 +00002//
Chris Lattner1c08c712005-01-07 07:47:53 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanedf128a2005-04-21 22:36:52 +00007//
Chris Lattner1c08c712005-01-07 07:47:53 +00008//===----------------------------------------------------------------------===//
9//
10// This implements the SelectionDAGISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "isel"
Anton Korobeynikov5502bf62007-04-04 21:14:49 +000015#include "llvm/ADT/BitVector.h"
Jim Laskeyc7c3f112006-10-16 20:52:31 +000016#include "llvm/Analysis/AliasAnalysis.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000017#include "llvm/CodeGen/SelectionDAGISel.h"
Evan Chenga9c20912006-01-21 02:32:06 +000018#include "llvm/CodeGen/ScheduleDAG.h"
Anton Korobeynikov5502bf62007-04-04 21:14:49 +000019#include "llvm/Constants.h"
Chris Lattneradf6a962005-05-13 18:50:42 +000020#include "llvm/CallingConv.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000021#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
Chris Lattner36ce6912005-11-29 06:21:05 +000023#include "llvm/GlobalVariable.h"
Chris Lattnerce7518c2006-01-26 22:24:51 +000024#include "llvm/InlineAsm.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000025#include "llvm/Instructions.h"
26#include "llvm/Intrinsics.h"
Jim Laskey43970fe2006-03-23 18:06:46 +000027#include "llvm/IntrinsicInst.h"
Reid Spencer5694b6e2007-04-09 06:17:21 +000028#include "llvm/ParameterAttributes.h"
Gordon Henriksence224772008-01-07 01:30:38 +000029#include "llvm/CodeGen/Collector.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000030#include "llvm/CodeGen/MachineFunction.h"
31#include "llvm/CodeGen/MachineFrameInfo.h"
32#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000033#include "llvm/CodeGen/MachineJumpTableInfo.h"
34#include "llvm/CodeGen/MachineModuleInfo.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
Jim Laskeyeb577ba2006-08-02 12:30:23 +000036#include "llvm/CodeGen/SchedulerRegistry.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000037#include "llvm/CodeGen/SelectionDAG.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +000038#include "llvm/Target/TargetRegisterInfo.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000039#include "llvm/Target/TargetData.h"
40#include "llvm/Target/TargetFrameInfo.h"
41#include "llvm/Target/TargetInstrInfo.h"
42#include "llvm/Target/TargetLowering.h"
43#include "llvm/Target/TargetMachine.h"
Vladimir Prus12472912006-05-23 13:43:15 +000044#include "llvm/Target/TargetOptions.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000045#include "llvm/Support/Compiler.h"
Evan Chengdb8d56b2008-06-30 20:45:06 +000046#include "llvm/Support/Debug.h"
47#include "llvm/Support/MathExtras.h"
48#include "llvm/Support/Timer.h"
Jeff Cohen7e881032006-02-24 02:52:40 +000049#include <algorithm>
Chris Lattner1c08c712005-01-07 07:47:53 +000050using namespace llvm;
51
Chris Lattneread0d882008-06-17 06:09:18 +000052static cl::opt<bool>
Chris Lattner70587ea2008-07-10 23:37:50 +000053EnableValueProp("enable-value-prop", cl::Hidden);
54static cl::opt<bool>
Duncan Sandsf00e74f2008-07-17 17:06:03 +000055EnableLegalizeTypes("enable-legalize-types", cl::Hidden);
Chris Lattneread0d882008-06-17 06:09:18 +000056
57
Chris Lattnerda8abb02005-09-01 18:44:10 +000058#ifndef NDEBUG
Chris Lattner7944d9d2005-01-12 03:41:21 +000059static cl::opt<bool>
Dan Gohman462dc7f2008-07-21 20:00:07 +000060ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
61 cl::desc("Pop up a window to show dags before the first "
62 "dag combine pass"));
63static cl::opt<bool>
64ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
65 cl::desc("Pop up a window to show dags before legalize types"));
66static cl::opt<bool>
67ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
68 cl::desc("Pop up a window to show dags before legalize"));
69static cl::opt<bool>
70ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
71 cl::desc("Pop up a window to show dags before the second "
72 "dag combine pass"));
73static cl::opt<bool>
Evan Chenga9c20912006-01-21 02:32:06 +000074ViewISelDAGs("view-isel-dags", cl::Hidden,
75 cl::desc("Pop up a window to show isel dags as they are selected"));
76static cl::opt<bool>
77ViewSchedDAGs("view-sched-dags", cl::Hidden,
78 cl::desc("Pop up a window to show sched dags as they are processed"));
Dan Gohman3e1a7ae2007-08-28 20:32:58 +000079static cl::opt<bool>
80ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
Chris Lattner5bab7852008-01-25 17:24:52 +000081 cl::desc("Pop up a window to show SUnit dags after they are processed"));
Chris Lattner7944d9d2005-01-12 03:41:21 +000082#else
Dan Gohman462dc7f2008-07-21 20:00:07 +000083static const bool ViewDAGCombine1 = false,
84 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
85 ViewDAGCombine2 = false,
86 ViewISelDAGs = false, ViewSchedDAGs = false,
87 ViewSUnitDAGs = false;
Chris Lattner7944d9d2005-01-12 03:41:21 +000088#endif
89
Jim Laskeyeb577ba2006-08-02 12:30:23 +000090//===---------------------------------------------------------------------===//
91///
92/// RegisterScheduler class - Track the registration of instruction schedulers.
93///
94//===---------------------------------------------------------------------===//
95MachinePassRegistry RegisterScheduler::Registry;
96
97//===---------------------------------------------------------------------===//
98///
99/// ISHeuristic command line option for instruction schedulers.
100///
101//===---------------------------------------------------------------------===//
Dan Gohman844731a2008-05-13 00:00:25 +0000102static cl::opt<RegisterScheduler::FunctionPassCtor, false,
103 RegisterPassParser<RegisterScheduler> >
104ISHeuristic("pre-RA-sched",
105 cl::init(&createDefaultScheduler),
106 cl::desc("Instruction schedulers available (before register"
107 " allocation):"));
Jim Laskey13ec7022006-08-01 14:21:23 +0000108
Dan Gohman844731a2008-05-13 00:00:25 +0000109static RegisterScheduler
110defaultListDAGScheduler("default", " Best scheduler for the target",
111 createDefaultScheduler);
Evan Cheng4ef10862006-01-23 07:01:07 +0000112
Evan Cheng5c807602008-02-26 02:33:44 +0000113namespace { struct SDISelAsmOperandInfo; }
Chris Lattnerbf996f12007-04-30 17:29:31 +0000114
Dan Gohman1d685a42008-06-07 02:02:36 +0000115/// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
116/// insertvalue or extractvalue indices that identify a member, return
117/// the linearized index of the start of the member.
118///
119static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
120 const unsigned *Indices,
121 const unsigned *IndicesEnd,
122 unsigned CurIndex = 0) {
123 // Base case: We're done.
Dan Gohman8f36f6d2008-06-20 00:53:00 +0000124 if (Indices && Indices == IndicesEnd)
Dan Gohman1d685a42008-06-07 02:02:36 +0000125 return CurIndex;
126
Chris Lattnerf899fce2008-04-27 23:48:12 +0000127 // Given a struct type, recursively traverse the elements.
128 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
Dan Gohman8f36f6d2008-06-20 00:53:00 +0000129 for (StructType::element_iterator EB = STy->element_begin(),
130 EI = EB,
Dan Gohman1d685a42008-06-07 02:02:36 +0000131 EE = STy->element_end();
132 EI != EE; ++EI) {
Dan Gohman8f36f6d2008-06-20 00:53:00 +0000133 if (Indices && *Indices == unsigned(EI - EB))
134 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
135 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
Dan Gohman1d685a42008-06-07 02:02:36 +0000136 }
137 }
138 // Given an array type, recursively traverse the elements.
139 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
140 const Type *EltTy = ATy->getElementType();
141 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
Dan Gohman8f36f6d2008-06-20 00:53:00 +0000142 if (Indices && *Indices == i)
143 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
144 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
Dan Gohman1d685a42008-06-07 02:02:36 +0000145 }
146 }
147 // We haven't found the type we're looking for, so keep searching.
Dan Gohman8f36f6d2008-06-20 00:53:00 +0000148 return CurIndex + 1;
Dan Gohman1d685a42008-06-07 02:02:36 +0000149}
150
151/// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
152/// MVTs that represent all the individual underlying
153/// non-aggregate types that comprise it.
154///
155/// If Offsets is non-null, it points to a vector to be filled in
156/// with the in-memory offsets of each of the individual values.
157///
158static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
159 SmallVectorImpl<MVT> &ValueVTs,
160 SmallVectorImpl<uint64_t> *Offsets = 0,
161 uint64_t StartingOffset = 0) {
162 // Given a struct type, recursively traverse the elements.
163 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
164 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
165 for (StructType::element_iterator EB = STy->element_begin(),
166 EI = EB,
167 EE = STy->element_end();
168 EI != EE; ++EI)
169 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
170 StartingOffset + SL->getElementOffset(EI - EB));
Chris Lattnerf899fce2008-04-27 23:48:12 +0000171 return;
Dan Gohman23ce5022008-04-25 18:27:55 +0000172 }
Chris Lattnerf899fce2008-04-27 23:48:12 +0000173 // Given an array type, recursively traverse the elements.
174 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
175 const Type *EltTy = ATy->getElementType();
Dan Gohman1d685a42008-06-07 02:02:36 +0000176 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
Chris Lattnerf899fce2008-04-27 23:48:12 +0000177 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
Dan Gohman1d685a42008-06-07 02:02:36 +0000178 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
179 StartingOffset + i * EltSize);
Chris Lattnerf899fce2008-04-27 23:48:12 +0000180 return;
181 }
Duncan Sands83ec4b62008-06-06 12:08:01 +0000182 // Base case: we can get an MVT for this LLVM IR type.
Chris Lattnerf899fce2008-04-27 23:48:12 +0000183 ValueVTs.push_back(TLI.getValueType(Ty));
Dan Gohman1d685a42008-06-07 02:02:36 +0000184 if (Offsets)
185 Offsets->push_back(StartingOffset);
Chris Lattnerf899fce2008-04-27 23:48:12 +0000186}
Dan Gohman23ce5022008-04-25 18:27:55 +0000187
Chris Lattnerf899fce2008-04-27 23:48:12 +0000188namespace {
Dan Gohman0fe00902008-04-28 18:10:39 +0000189 /// RegsForValue - This struct represents the registers (physical or virtual)
190 /// that a particular set of values is assigned, and the type information about
191 /// the value. The most common situation is to represent one value at a time,
192 /// but struct or array values are handled element-wise as multiple values.
193 /// The splitting of aggregates is performed recursively, so that we never
194 /// have aggregate-typed registers. The values at this point do not necessarily
195 /// have legal types, so each value may require one or more registers of some
196 /// legal type.
197 ///
Chris Lattner95255282006-06-28 23:17:24 +0000198 struct VISIBILITY_HIDDEN RegsForValue {
Dan Gohman23ce5022008-04-25 18:27:55 +0000199 /// TLI - The TargetLowering object.
Dan Gohman0fe00902008-04-28 18:10:39 +0000200 ///
Dan Gohman23ce5022008-04-25 18:27:55 +0000201 const TargetLowering *TLI;
202
Dan Gohman0fe00902008-04-28 18:10:39 +0000203 /// ValueVTs - The value types of the values, which may not be legal, and
204 /// may need be promoted or synthesized from one or more registers.
205 ///
Duncan Sands83ec4b62008-06-06 12:08:01 +0000206 SmallVector<MVT, 4> ValueVTs;
Chris Lattner864635a2006-02-22 22:37:12 +0000207
Dan Gohman0fe00902008-04-28 18:10:39 +0000208 /// RegVTs - The value types of the registers. This is the same size as
209 /// ValueVTs and it records, for each value, what the type of the assigned
210 /// register or registers are. (Individual values are never synthesized
211 /// from more than one type of register.)
212 ///
213 /// With virtual registers, the contents of RegVTs is redundant with TLI's
214 /// getRegisterType member function, however when with physical registers
215 /// it is necessary to have a separate record of the types.
Chris Lattner864635a2006-02-22 22:37:12 +0000216 ///
Duncan Sands83ec4b62008-06-06 12:08:01 +0000217 SmallVector<MVT, 4> RegVTs;
Chris Lattner864635a2006-02-22 22:37:12 +0000218
Dan Gohman0fe00902008-04-28 18:10:39 +0000219 /// Regs - This list holds the registers assigned to the values.
220 /// Each legal or promoted value requires one register, and each
221 /// expanded value requires multiple registers.
222 ///
223 SmallVector<unsigned, 4> Regs;
Chris Lattner864635a2006-02-22 22:37:12 +0000224
Dan Gohman23ce5022008-04-25 18:27:55 +0000225 RegsForValue() : TLI(0) {}
Chris Lattner864635a2006-02-22 22:37:12 +0000226
Dan Gohman23ce5022008-04-25 18:27:55 +0000227 RegsForValue(const TargetLowering &tli,
Chris Lattnerb606dba2008-04-28 06:44:42 +0000228 const SmallVector<unsigned, 4> &regs,
Duncan Sands83ec4b62008-06-06 12:08:01 +0000229 MVT regvt, MVT valuevt)
Dan Gohman0fe00902008-04-28 18:10:39 +0000230 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
Dan Gohman23ce5022008-04-25 18:27:55 +0000231 RegsForValue(const TargetLowering &tli,
Chris Lattnerb606dba2008-04-28 06:44:42 +0000232 const SmallVector<unsigned, 4> &regs,
Duncan Sands83ec4b62008-06-06 12:08:01 +0000233 const SmallVector<MVT, 4> &regvts,
234 const SmallVector<MVT, 4> &valuevts)
Dan Gohman0fe00902008-04-28 18:10:39 +0000235 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
Dan Gohman23ce5022008-04-25 18:27:55 +0000236 RegsForValue(const TargetLowering &tli,
237 unsigned Reg, const Type *Ty) : TLI(&tli) {
238 ComputeValueVTs(tli, Ty, ValueVTs);
239
Dan Gohmanb20d4f82008-04-28 17:42:03 +0000240 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000241 MVT ValueVT = ValueVTs[Value];
Dan Gohman23ce5022008-04-25 18:27:55 +0000242 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
Duncan Sands83ec4b62008-06-06 12:08:01 +0000243 MVT RegisterVT = TLI->getRegisterType(ValueVT);
Dan Gohman23ce5022008-04-25 18:27:55 +0000244 for (unsigned i = 0; i != NumRegs; ++i)
245 Regs.push_back(Reg + i);
246 RegVTs.push_back(RegisterVT);
247 Reg += NumRegs;
248 }
Chris Lattner864635a2006-02-22 22:37:12 +0000249 }
250
Chris Lattner41f62592008-04-29 04:29:54 +0000251 /// append - Add the specified values to this one.
252 void append(const RegsForValue &RHS) {
253 TLI = RHS.TLI;
254 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
255 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
256 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
257 }
258
259
Chris Lattner864635a2006-02-22 22:37:12 +0000260 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
Dan Gohman23ce5022008-04-25 18:27:55 +0000261 /// this value and returns the result as a ValueVTs value. This uses
Chris Lattner864635a2006-02-22 22:37:12 +0000262 /// Chain/Flag as the input and updates them for the output Chain/Flag.
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000263 /// If the Flag pointer is NULL, no flag is used.
Dan Gohman475871a2008-07-27 21:46:04 +0000264 SDValue getCopyFromRegs(SelectionDAG &DAG,
265 SDValue &Chain, SDValue *Flag) const;
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +0000266
267 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
268 /// specified value into the registers specified by this object. This uses
269 /// Chain/Flag as the input and updates them for the output Chain/Flag.
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000270 /// If the Flag pointer is NULL, no flag is used.
Dan Gohman475871a2008-07-27 21:46:04 +0000271 void getCopyToRegs(SDValue Val, SelectionDAG &DAG,
272 SDValue &Chain, SDValue *Flag) const;
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +0000273
274 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
275 /// operand list. This adds the code marker and includes the number of
276 /// values added into it.
277 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
Dan Gohman475871a2008-07-27 21:46:04 +0000278 std::vector<SDValue> &Ops) const;
Chris Lattner864635a2006-02-22 22:37:12 +0000279 };
280}
Evan Cheng4ef10862006-01-23 07:01:07 +0000281
Chris Lattner1c08c712005-01-07 07:47:53 +0000282namespace llvm {
283 //===--------------------------------------------------------------------===//
Jim Laskey9373beb2006-08-01 19:14:14 +0000284 /// createDefaultScheduler - This creates an instruction scheduler appropriate
285 /// for the target.
286 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
287 SelectionDAG *DAG,
Evan Cheng4576f6d2008-07-01 18:05:03 +0000288 MachineBasicBlock *BB,
289 bool Fast) {
Jim Laskey9373beb2006-08-01 19:14:14 +0000290 TargetLowering &TLI = IS->getTargetLowering();
291
292 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
Evan Cheng4576f6d2008-07-01 18:05:03 +0000293 return createTDListDAGScheduler(IS, DAG, BB, Fast);
Jim Laskey9373beb2006-08-01 19:14:14 +0000294 } else {
295 assert(TLI.getSchedulingPreference() ==
296 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
Evan Cheng4576f6d2008-07-01 18:05:03 +0000297 return createBURRListDAGScheduler(IS, DAG, BB, Fast);
Jim Laskey9373beb2006-08-01 19:14:14 +0000298 }
299 }
300
301
302 //===--------------------------------------------------------------------===//
Chris Lattner1c08c712005-01-07 07:47:53 +0000303 /// FunctionLoweringInfo - This contains information that is global to a
304 /// function that is used when lowering a region of the function.
Chris Lattnerf26bc8e2005-01-08 19:52:31 +0000305 class FunctionLoweringInfo {
306 public:
Chris Lattner1c08c712005-01-07 07:47:53 +0000307 TargetLowering &TLI;
308 Function &Fn;
309 MachineFunction &MF;
Chris Lattner84bc5422007-12-31 04:13:23 +0000310 MachineRegisterInfo &RegInfo;
Chris Lattner1c08c712005-01-07 07:47:53 +0000311
312 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
313
314 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
315 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
316
317 /// ValueMap - Since we emit code for the function a basic block at a time,
318 /// we must remember which virtual registers hold the values for
319 /// cross-basic-block values.
Chris Lattner9f24ad72007-02-04 01:35:11 +0000320 DenseMap<const Value*, unsigned> ValueMap;
Chris Lattner1c08c712005-01-07 07:47:53 +0000321
322 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
323 /// the entry block. This allows the allocas to be efficiently referenced
324 /// anywhere in the function.
325 std::map<const AllocaInst*, int> StaticAllocaMap;
326
Duncan Sandsf4070822007-06-15 19:04:19 +0000327#ifndef NDEBUG
328 SmallSet<Instruction*, 8> CatchInfoLost;
329 SmallSet<Instruction*, 8> CatchInfoFound;
330#endif
331
Duncan Sands83ec4b62008-06-06 12:08:01 +0000332 unsigned MakeReg(MVT VT) {
Chris Lattner84bc5422007-12-31 04:13:23 +0000333 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
Chris Lattner1c08c712005-01-07 07:47:53 +0000334 }
Chris Lattner571e4342006-10-27 21:36:01 +0000335
336 /// isExportedInst - Return true if the specified value is an instruction
337 /// exported from its block.
338 bool isExportedInst(const Value *V) {
339 return ValueMap.count(V);
340 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000341
Chris Lattner3c384492006-03-16 19:51:18 +0000342 unsigned CreateRegForValue(const Value *V);
343
Chris Lattner1c08c712005-01-07 07:47:53 +0000344 unsigned InitializeRegForValue(const Value *V) {
345 unsigned &R = ValueMap[V];
346 assert(R == 0 && "Already initialized this value register!");
347 return R = CreateRegForValue(V);
348 }
Chris Lattneread0d882008-06-17 06:09:18 +0000349
350 struct LiveOutInfo {
351 unsigned NumSignBits;
352 APInt KnownOne, KnownZero;
353 LiveOutInfo() : NumSignBits(0) {}
354 };
355
356 /// LiveOutRegInfo - Information about live out vregs, indexed by their
357 /// register number offset by 'FirstVirtualRegister'.
358 std::vector<LiveOutInfo> LiveOutRegInfo;
Chris Lattner1c08c712005-01-07 07:47:53 +0000359 };
360}
361
Duncan Sandscf26d7c2007-07-04 20:52:51 +0000362/// isSelector - Return true if this instruction is a call to the
363/// eh.selector intrinsic.
364static bool isSelector(Instruction *I) {
Duncan Sandsf4070822007-06-15 19:04:19 +0000365 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +0000366 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
367 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
Duncan Sandsf4070822007-06-15 19:04:19 +0000368 return false;
369}
370
Chris Lattner1c08c712005-01-07 07:47:53 +0000371/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
Nate Begemanf15485a2006-03-27 01:32:24 +0000372/// PHI nodes or outside of the basic block that defines it, or used by a
Andrew Lenharthab0b9492008-02-21 06:45:13 +0000373/// switch or atomic instruction, which may expand to multiple basic blocks.
Chris Lattner1c08c712005-01-07 07:47:53 +0000374static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
375 if (isa<PHINode>(I)) return true;
376 BasicBlock *BB = I->getParent();
377 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
Nate Begemanf15485a2006-03-27 01:32:24 +0000378 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
Chris Lattner571e4342006-10-27 21:36:01 +0000379 // FIXME: Remove switchinst special case.
Nate Begemanf15485a2006-03-27 01:32:24 +0000380 isa<SwitchInst>(*UI))
Chris Lattner1c08c712005-01-07 07:47:53 +0000381 return true;
382 return false;
383}
384
Chris Lattnerbf209482005-10-30 19:42:35 +0000385/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
Nate Begemanf15485a2006-03-27 01:32:24 +0000386/// entry block, return true. This includes arguments used by switches, since
387/// the switch may expand into multiple basic blocks.
Chris Lattnerbf209482005-10-30 19:42:35 +0000388static bool isOnlyUsedInEntryBlock(Argument *A) {
389 BasicBlock *Entry = A->getParent()->begin();
390 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
Nate Begemanf15485a2006-03-27 01:32:24 +0000391 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
Chris Lattnerbf209482005-10-30 19:42:35 +0000392 return false; // Use not in entry block.
393 return true;
394}
395
Chris Lattner1c08c712005-01-07 07:47:53 +0000396FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
Misha Brukmanedf128a2005-04-21 22:36:52 +0000397 Function &fn, MachineFunction &mf)
Chris Lattner84bc5422007-12-31 04:13:23 +0000398 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
Chris Lattner1c08c712005-01-07 07:47:53 +0000399
Chris Lattnerbf209482005-10-30 19:42:35 +0000400 // Create a vreg for each argument register that is not dead and is used
401 // outside of the entry block for the function.
402 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
403 AI != E; ++AI)
404 if (!isOnlyUsedInEntryBlock(AI))
405 InitializeRegForValue(AI);
406
Chris Lattner1c08c712005-01-07 07:47:53 +0000407 // Initialize the mapping of values to registers. This is only set up for
408 // instruction values that are used outside of the block that defines
409 // them.
Jeff Cohen2aeaf4e2005-10-01 03:57:14 +0000410 Function::iterator BB = Fn.begin(), EB = Fn.end();
Chris Lattner1c08c712005-01-07 07:47:53 +0000411 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
412 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
Reid Spencerb83eb642006-10-20 07:07:24 +0000413 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
Chris Lattner1c08c712005-01-07 07:47:53 +0000414 const Type *Ty = AI->getAllocatedType();
Duncan Sands514ab342007-11-01 20:53:16 +0000415 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
Nate Begemanae232e72005-11-06 09:00:38 +0000416 unsigned Align =
Chris Lattnerd2b7cec2007-02-14 05:52:17 +0000417 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
Nate Begemanae232e72005-11-06 09:00:38 +0000418 AI->getAlignment());
Chris Lattnera8217e32005-05-13 23:14:17 +0000419
Reid Spencerb83eb642006-10-20 07:07:24 +0000420 TySize *= CUI->getZExtValue(); // Get total allocated size.
Chris Lattnerd222f6a2005-10-18 22:14:06 +0000421 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
Chris Lattner1c08c712005-01-07 07:47:53 +0000422 StaticAllocaMap[AI] =
Chris Lattner6266c182007-04-25 04:08:28 +0000423 MF.getFrameInfo()->CreateStackObject(TySize, Align);
Chris Lattner1c08c712005-01-07 07:47:53 +0000424 }
425
Jeff Cohen2aeaf4e2005-10-01 03:57:14 +0000426 for (; BB != EB; ++BB)
427 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
Chris Lattner1c08c712005-01-07 07:47:53 +0000428 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
429 if (!isa<AllocaInst>(I) ||
430 !StaticAllocaMap.count(cast<AllocaInst>(I)))
431 InitializeRegForValue(I);
432
433 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
434 // also creates the initial PHI MachineInstrs, though none of the input
435 // operands are populated.
Jeff Cohen2aeaf4e2005-10-01 03:57:14 +0000436 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
Dan Gohman0e5f1302008-07-07 23:02:41 +0000437 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
Chris Lattner1c08c712005-01-07 07:47:53 +0000438 MBBMap[BB] = MBB;
Dan Gohman0e5f1302008-07-07 23:02:41 +0000439 MF.push_back(MBB);
Chris Lattner1c08c712005-01-07 07:47:53 +0000440
441 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
442 // appropriate.
443 PHINode *PN;
Chris Lattner8c494ab2006-10-27 23:50:33 +0000444 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
445 if (PN->use_empty()) continue;
446
Duncan Sands83ec4b62008-06-06 12:08:01 +0000447 MVT VT = TLI.getValueType(PN->getType());
Dan Gohman7f321562007-06-25 16:23:39 +0000448 unsigned NumRegisters = TLI.getNumRegisters(VT);
Chris Lattner8c494ab2006-10-27 23:50:33 +0000449 unsigned PHIReg = ValueMap[PN];
450 assert(PHIReg && "PHI node does not have an assigned virtual register!");
Evan Chengc0f64ff2006-11-27 23:37:22 +0000451 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
Dan Gohmanb9f10192007-06-21 14:42:22 +0000452 for (unsigned i = 0; i != NumRegisters; ++i)
Evan Chengc0f64ff2006-11-27 23:37:22 +0000453 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
Chris Lattner8c494ab2006-10-27 23:50:33 +0000454 }
Chris Lattner1c08c712005-01-07 07:47:53 +0000455 }
456}
457
Chris Lattner3c384492006-03-16 19:51:18 +0000458/// CreateRegForValue - Allocate the appropriate number of virtual registers of
459/// the correctly promoted or expanded types. Assign these registers
460/// consecutive vreg numbers and return the first assigned number.
Dan Gohman10a6b7a2008-04-28 18:19:43 +0000461///
462/// In the case that the given value has struct or array type, this function
463/// will assign registers for each member or element.
464///
Chris Lattner3c384492006-03-16 19:51:18 +0000465unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000466 SmallVector<MVT, 4> ValueVTs;
Chris Lattnerb606dba2008-04-28 06:44:42 +0000467 ComputeValueVTs(TLI, V->getType(), ValueVTs);
Bill Wendling95b39552007-04-24 21:13:23 +0000468
Dan Gohman23ce5022008-04-25 18:27:55 +0000469 unsigned FirstReg = 0;
Dan Gohmanb20d4f82008-04-28 17:42:03 +0000470 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000471 MVT ValueVT = ValueVTs[Value];
472 MVT RegisterVT = TLI.getRegisterType(ValueVT);
Dan Gohman8c8c5fc2007-06-27 14:34:07 +0000473
Chris Lattnerb606dba2008-04-28 06:44:42 +0000474 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
Dan Gohman23ce5022008-04-25 18:27:55 +0000475 for (unsigned i = 0; i != NumRegs; ++i) {
476 unsigned R = MakeReg(RegisterVT);
477 if (!FirstReg) FirstReg = R;
478 }
479 }
480 return FirstReg;
Chris Lattner3c384492006-03-16 19:51:18 +0000481}
Chris Lattner1c08c712005-01-07 07:47:53 +0000482
483//===----------------------------------------------------------------------===//
484/// SelectionDAGLowering - This is the common target-independent lowering
485/// implementation that is parameterized by a TargetLowering object.
486/// Also, targets can overload any lowering method.
487///
488namespace llvm {
489class SelectionDAGLowering {
490 MachineBasicBlock *CurMBB;
491
Dan Gohman475871a2008-07-27 21:46:04 +0000492 DenseMap<const Value*, SDValue> NodeMap;
Chris Lattner1c08c712005-01-07 07:47:53 +0000493
Chris Lattnerd3948112005-01-17 22:19:26 +0000494 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
495 /// them up and then emit token factor nodes when possible. This allows us to
496 /// get simple disambiguation between loads without worrying about alias
497 /// analysis.
Dan Gohman475871a2008-07-27 21:46:04 +0000498 SmallVector<SDValue, 8> PendingLoads;
Chris Lattnerd3948112005-01-17 22:19:26 +0000499
Dan Gohman86e1ebf2008-03-27 19:56:19 +0000500 /// PendingExports - CopyToReg nodes that copy values to virtual registers
501 /// for export to other blocks need to be emitted before any terminator
502 /// instruction, but they have no other ordering requirements. We bunch them
503 /// up and the emit a single tokenfactor for them just before terminator
504 /// instructions.
Dan Gohman475871a2008-07-27 21:46:04 +0000505 std::vector<SDValue> PendingExports;
Dan Gohman86e1ebf2008-03-27 19:56:19 +0000506
Anton Korobeynikov5502bf62007-04-04 21:14:49 +0000507 /// Case - A struct to record the Value for a switch case, and the
508 /// case's target basic block.
509 struct Case {
510 Constant* Low;
511 Constant* High;
512 MachineBasicBlock* BB;
513
514 Case() : Low(0), High(0), BB(0) { }
515 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
516 Low(low), High(high), BB(bb) { }
517 uint64_t size() const {
518 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
519 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
520 return (rHigh - rLow + 1ULL);
521 }
522 };
523
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000524 struct CaseBits {
525 uint64_t Mask;
526 MachineBasicBlock* BB;
527 unsigned Bits;
528
529 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
530 Mask(mask), BB(bb), Bits(bits) { }
531 };
532
Anton Korobeynikov5502bf62007-04-04 21:14:49 +0000533 typedef std::vector<Case> CaseVector;
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000534 typedef std::vector<CaseBits> CaseBitsVector;
Anton Korobeynikov5502bf62007-04-04 21:14:49 +0000535 typedef CaseVector::iterator CaseItr;
536 typedef std::pair<CaseItr, CaseItr> CaseRange;
Nate Begemanf15485a2006-03-27 01:32:24 +0000537
538 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
539 /// of conditional branches.
540 struct CaseRec {
541 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
542 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
543
544 /// CaseBB - The MBB in which to emit the compare and branch
545 MachineBasicBlock *CaseBB;
546 /// LT, GE - If nonzero, we know the current case value must be less-than or
547 /// greater-than-or-equal-to these Constants.
548 Constant *LT;
549 Constant *GE;
550 /// Range - A pair of iterators representing the range of case values to be
551 /// processed at this point in the binary search tree.
552 CaseRange Range;
553 };
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +0000554
555 typedef std::vector<CaseRec> CaseRecVector;
Anton Korobeynikov5502bf62007-04-04 21:14:49 +0000556
557 /// The comparison function for sorting the switch case values in the vector.
558 /// WARNING: Case ranges should be disjoint!
Nate Begemanf15485a2006-03-27 01:32:24 +0000559 struct CaseCmp {
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000560 bool operator () (const Case& C1, const Case& C2) {
Anton Korobeynikov5502bf62007-04-04 21:14:49 +0000561 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
562 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
563 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
564 return CI1->getValue().slt(CI2->getValue());
Nate Begemanf15485a2006-03-27 01:32:24 +0000565 }
566 };
Anton Korobeynikov5502bf62007-04-04 21:14:49 +0000567
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000568 struct CaseBitsCmp {
569 bool operator () (const CaseBits& C1, const CaseBits& C2) {
570 return C1.Bits > C2.Bits;
571 }
572 };
573
Anton Korobeynikov5502bf62007-04-04 21:14:49 +0000574 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
Nate Begemanf15485a2006-03-27 01:32:24 +0000575
Chris Lattner1c08c712005-01-07 07:47:53 +0000576public:
577 // TLI - This is information that describes the available target features we
578 // need for lowering. This indicates when operations are unavailable,
579 // implemented with a libcall, etc.
580 TargetLowering &TLI;
581 SelectionDAG &DAG;
Owen Andersona69571c2006-05-03 01:29:57 +0000582 const TargetData *TD;
Dan Gohman5f43f922007-08-27 16:26:13 +0000583 AliasAnalysis &AA;
Chris Lattner1c08c712005-01-07 07:47:53 +0000584
Nate Begemanf15485a2006-03-27 01:32:24 +0000585 /// SwitchCases - Vector of CaseBlock structures used to communicate
586 /// SwitchInst code generation information.
587 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +0000588 /// JTCases - Vector of JumpTable structures used to communicate
589 /// SwitchInst code generation information.
590 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000591 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
Nate Begemanf15485a2006-03-27 01:32:24 +0000592
Chris Lattner1c08c712005-01-07 07:47:53 +0000593 /// FuncInfo - Information about the function as a whole.
594 ///
595 FunctionLoweringInfo &FuncInfo;
Gordon Henriksence224772008-01-07 01:30:38 +0000596
597 /// GCI - Garbage collection metadata for the function.
598 CollectorMetadata *GCI;
Chris Lattner1c08c712005-01-07 07:47:53 +0000599
600 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
Dan Gohman5f43f922007-08-27 16:26:13 +0000601 AliasAnalysis &aa,
Gordon Henriksence224772008-01-07 01:30:38 +0000602 FunctionLoweringInfo &funcinfo,
603 CollectorMetadata *gci)
Dan Gohman5f43f922007-08-27 16:26:13 +0000604 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
Gordon Henriksence224772008-01-07 01:30:38 +0000605 FuncInfo(funcinfo), GCI(gci) {
Chris Lattner1c08c712005-01-07 07:47:53 +0000606 }
607
Dan Gohman86e1ebf2008-03-27 19:56:19 +0000608 /// getRoot - Return the current virtual root of the Selection DAG,
609 /// flushing any PendingLoad items. This must be done before emitting
610 /// a store or any other node that may need to be ordered after any
611 /// prior load instructions.
Chris Lattnera651cf62005-01-17 19:43:36 +0000612 ///
Dan Gohman475871a2008-07-27 21:46:04 +0000613 SDValue getRoot() {
Chris Lattnerd3948112005-01-17 22:19:26 +0000614 if (PendingLoads.empty())
615 return DAG.getRoot();
Misha Brukmanedf128a2005-04-21 22:36:52 +0000616
Chris Lattnerd3948112005-01-17 22:19:26 +0000617 if (PendingLoads.size() == 1) {
Dan Gohman475871a2008-07-27 21:46:04 +0000618 SDValue Root = PendingLoads[0];
Chris Lattnerd3948112005-01-17 22:19:26 +0000619 DAG.setRoot(Root);
620 PendingLoads.clear();
621 return Root;
622 }
623
624 // Otherwise, we have to make a token factor node.
Dan Gohman475871a2008-07-27 21:46:04 +0000625 SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
Chris Lattnerbd564bf2006-08-08 02:23:42 +0000626 &PendingLoads[0], PendingLoads.size());
Chris Lattnerd3948112005-01-17 22:19:26 +0000627 PendingLoads.clear();
628 DAG.setRoot(Root);
629 return Root;
Chris Lattnera651cf62005-01-17 19:43:36 +0000630 }
631
Dan Gohman86e1ebf2008-03-27 19:56:19 +0000632 /// getControlRoot - Similar to getRoot, but instead of flushing all the
633 /// PendingLoad items, flush all the PendingExports items. It is necessary
634 /// to do this before emitting a terminator instruction.
635 ///
Dan Gohman475871a2008-07-27 21:46:04 +0000636 SDValue getControlRoot() {
637 SDValue Root = DAG.getRoot();
Dan Gohman86e1ebf2008-03-27 19:56:19 +0000638
639 if (PendingExports.empty())
640 return Root;
641
642 // Turn all of the CopyToReg chains into one factored node.
643 if (Root.getOpcode() != ISD::EntryToken) {
644 unsigned i = 0, e = PendingExports.size();
645 for (; i != e; ++i) {
646 assert(PendingExports[i].Val->getNumOperands() > 1);
647 if (PendingExports[i].Val->getOperand(0) == Root)
648 break; // Don't add the root if we already indirectly depend on it.
649 }
650
651 if (i == e)
652 PendingExports.push_back(Root);
653 }
654
655 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
656 &PendingExports[0],
657 PendingExports.size());
658 PendingExports.clear();
659 DAG.setRoot(Root);
660 return Root;
661 }
662
663 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
Chris Lattner571e4342006-10-27 21:36:01 +0000664
Chris Lattner1c08c712005-01-07 07:47:53 +0000665 void visit(Instruction &I) { visit(I.getOpcode(), I); }
666
667 void visit(unsigned Opcode, User &I) {
Chris Lattner1e7aa5c2006-11-10 04:41:34 +0000668 // Note: this doesn't use InstVisitor, because it has to work with
669 // ConstantExpr's in addition to instructions.
Chris Lattner1c08c712005-01-07 07:47:53 +0000670 switch (Opcode) {
671 default: assert(0 && "Unknown instruction type encountered!");
672 abort();
673 // Build the switch statement using the Instruction.def file.
674#define HANDLE_INST(NUM, OPCODE, CLASS) \
675 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
676#include "llvm/Instruction.def"
677 }
678 }
679
680 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
681
Dan Gohman475871a2008-07-27 21:46:04 +0000682 SDValue getValue(const Value *V);
Chris Lattner1c08c712005-01-07 07:47:53 +0000683
Dan Gohman475871a2008-07-27 21:46:04 +0000684 void setValue(const Value *V, SDValue NewN) {
685 SDValue &N = NodeMap[V];
Chris Lattner1c08c712005-01-07 07:47:53 +0000686 assert(N.Val == 0 && "Already set a value for this node!");
Chris Lattner0da331f2007-02-04 01:31:47 +0000687 N = NewN;
Chris Lattner1c08c712005-01-07 07:47:53 +0000688 }
Chris Lattner4e4b5762006-02-01 18:59:47 +0000689
Evan Cheng5c807602008-02-26 02:33:44 +0000690 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
Chris Lattnere7cf56a2007-04-30 21:11:17 +0000691 std::set<unsigned> &OutputRegs,
692 std::set<unsigned> &InputRegs);
Nate Begemanf15485a2006-03-27 01:32:24 +0000693
Chris Lattner571e4342006-10-27 21:36:01 +0000694 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
695 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
696 unsigned Opc);
Chris Lattner8c494ab2006-10-27 23:50:33 +0000697 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
Chris Lattner571e4342006-10-27 21:36:01 +0000698 void ExportFromCurrentBlock(Value *V);
Dan Gohman475871a2008-07-27 21:46:04 +0000699 void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall,
Anton Korobeynikov070280e2007-05-23 11:08:31 +0000700 MachineBasicBlock *LandingPad = NULL);
Duncan Sandsdc024672007-11-27 13:23:08 +0000701
Chris Lattner1c08c712005-01-07 07:47:53 +0000702 // Terminator instructions.
703 void visitRet(ReturnInst &I);
704 void visitBr(BranchInst &I);
Nate Begemanf15485a2006-03-27 01:32:24 +0000705 void visitSwitch(SwitchInst &I);
Chris Lattner1c08c712005-01-07 07:47:53 +0000706 void visitUnreachable(UnreachableInst &I) { /* noop */ }
707
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +0000708 // Helpers for visitSwitch
Anton Korobeynikovdd433212007-03-27 12:05:48 +0000709 bool handleSmallSwitchRange(CaseRec& CR,
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +0000710 CaseRecVector& WorkList,
711 Value* SV,
712 MachineBasicBlock* Default);
Anton Korobeynikovdd433212007-03-27 12:05:48 +0000713 bool handleJTSwitchCase(CaseRec& CR,
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +0000714 CaseRecVector& WorkList,
715 Value* SV,
716 MachineBasicBlock* Default);
Anton Korobeynikovdd433212007-03-27 12:05:48 +0000717 bool handleBTSplitSwitchCase(CaseRec& CR,
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +0000718 CaseRecVector& WorkList,
719 Value* SV,
720 MachineBasicBlock* Default);
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000721 bool handleBitTestsSwitchCase(CaseRec& CR,
722 CaseRecVector& WorkList,
723 Value* SV,
724 MachineBasicBlock* Default);
Nate Begemanf15485a2006-03-27 01:32:24 +0000725 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000726 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
727 void visitBitTestCase(MachineBasicBlock* NextMBB,
728 unsigned Reg,
729 SelectionDAGISel::BitTestCase &B);
Nate Begeman37efe672006-04-22 18:53:45 +0000730 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +0000731 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
732 SelectionDAGISel::JumpTableHeader &JTH);
Nate Begemanf15485a2006-03-27 01:32:24 +0000733
Chris Lattner1c08c712005-01-07 07:47:53 +0000734 // These all get lowered before this pass.
Jim Laskeyb180aa12007-02-21 22:53:45 +0000735 void visitInvoke(InvokeInst &I);
736 void visitUnwind(UnwindInst &I);
Chris Lattner1c08c712005-01-07 07:47:53 +0000737
Dan Gohman7f321562007-06-25 16:23:39 +0000738 void visitBinary(User &I, unsigned OpCode);
Nate Begemane21ea612005-11-18 07:42:56 +0000739 void visitShift(User &I, unsigned Opcode);
Nate Begeman5fbb5d22005-11-19 00:36:38 +0000740 void visitAdd(User &I) {
Dan Gohman7f321562007-06-25 16:23:39 +0000741 if (I.getType()->isFPOrFPVector())
742 visitBinary(I, ISD::FADD);
Reid Spencer1628cec2006-10-26 06:15:43 +0000743 else
Dan Gohman7f321562007-06-25 16:23:39 +0000744 visitBinary(I, ISD::ADD);
Chris Lattner01b3d732005-09-28 22:28:18 +0000745 }
Chris Lattnerb9fccc42005-04-02 05:04:50 +0000746 void visitSub(User &I);
Reid Spencer1628cec2006-10-26 06:15:43 +0000747 void visitMul(User &I) {
Dan Gohman7f321562007-06-25 16:23:39 +0000748 if (I.getType()->isFPOrFPVector())
749 visitBinary(I, ISD::FMUL);
Reid Spencer1628cec2006-10-26 06:15:43 +0000750 else
Dan Gohman7f321562007-06-25 16:23:39 +0000751 visitBinary(I, ISD::MUL);
Chris Lattner01b3d732005-09-28 22:28:18 +0000752 }
Dan Gohman7f321562007-06-25 16:23:39 +0000753 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
754 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
755 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
756 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
757 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
758 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
759 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
760 void visitOr (User &I) { visitBinary(I, ISD::OR); }
761 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
Reid Spencer24d6da52007-01-21 00:29:26 +0000762 void visitShl (User &I) { visitShift(I, ISD::SHL); }
Reid Spencer3822ff52006-11-08 06:47:33 +0000763 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
764 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
Reid Spencer45fb3f32006-11-20 01:22:35 +0000765 void visitICmp(User &I);
766 void visitFCmp(User &I);
Nate Begemanb43e9c12008-05-12 19:40:03 +0000767 void visitVICmp(User &I);
768 void visitVFCmp(User &I);
Reid Spencer3da59db2006-11-27 01:05:10 +0000769 // Visit the conversion instructions
770 void visitTrunc(User &I);
771 void visitZExt(User &I);
772 void visitSExt(User &I);
773 void visitFPTrunc(User &I);
774 void visitFPExt(User &I);
775 void visitFPToUI(User &I);
776 void visitFPToSI(User &I);
777 void visitUIToFP(User &I);
778 void visitSIToFP(User &I);
779 void visitPtrToInt(User &I);
780 void visitIntToPtr(User &I);
781 void visitBitCast(User &I);
Chris Lattner1c08c712005-01-07 07:47:53 +0000782
Chris Lattner2bbd8102006-03-29 00:11:43 +0000783 void visitExtractElement(User &I);
784 void visitInsertElement(User &I);
Chris Lattner3e104b12006-04-08 04:15:24 +0000785 void visitShuffleVector(User &I);
Chris Lattnerc7029802006-03-18 01:44:44 +0000786
Dan Gohman1d685a42008-06-07 02:02:36 +0000787 void visitExtractValue(ExtractValueInst &I);
788 void visitInsertValue(InsertValueInst &I);
Dan Gohman041e2eb2008-05-15 19:50:34 +0000789
Chris Lattner1c08c712005-01-07 07:47:53 +0000790 void visitGetElementPtr(User &I);
Chris Lattner1c08c712005-01-07 07:47:53 +0000791 void visitSelect(User &I);
Chris Lattner1c08c712005-01-07 07:47:53 +0000792
793 void visitMalloc(MallocInst &I);
794 void visitFree(FreeInst &I);
795 void visitAlloca(AllocaInst &I);
796 void visitLoad(LoadInst &I);
797 void visitStore(StoreInst &I);
798 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
799 void visitCall(CallInst &I);
Duncan Sandsfd7b3262007-12-17 18:08:19 +0000800 void visitInlineAsm(CallSite CS);
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +0000801 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
Chris Lattner0eade312006-03-24 02:22:33 +0000802 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
Chris Lattner1c08c712005-01-07 07:47:53 +0000803
Chris Lattner1c08c712005-01-07 07:47:53 +0000804 void visitVAStart(CallInst &I);
Chris Lattner1c08c712005-01-07 07:47:53 +0000805 void visitVAArg(VAArgInst &I);
806 void visitVAEnd(CallInst &I);
807 void visitVACopy(CallInst &I);
Chris Lattner1c08c712005-01-07 07:47:53 +0000808
Chris Lattner1c08c712005-01-07 07:47:53 +0000809 void visitUserOp1(Instruction &I) {
810 assert(0 && "UserOp1 should not exist at instruction selection time!");
811 abort();
812 }
813 void visitUserOp2(Instruction &I) {
814 assert(0 && "UserOp2 should not exist at instruction selection time!");
815 abort();
816 }
Mon P Wang63307c32008-05-05 19:05:59 +0000817
818private:
819 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
820
Chris Lattner1c08c712005-01-07 07:47:53 +0000821};
822} // end namespace llvm
823
Dan Gohman6183f782007-07-05 20:12:34 +0000824
Duncan Sandsb988bac2008-02-11 20:58:28 +0000825/// getCopyFromParts - Create a value that contains the specified legal parts
826/// combined into the value they represent. If the parts combine to a type
827/// larger then ValueVT then AssertOp can be used to specify whether the extra
828/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
Chris Lattner4468c1f2008-03-09 09:38:46 +0000829/// (ISD::AssertSext).
Dan Gohman475871a2008-07-27 21:46:04 +0000830static SDValue getCopyFromParts(SelectionDAG &DAG,
831 const SDValue *Parts,
Dan Gohman6183f782007-07-05 20:12:34 +0000832 unsigned NumParts,
Duncan Sands83ec4b62008-06-06 12:08:01 +0000833 MVT PartVT,
834 MVT ValueVT,
Chris Lattner4468c1f2008-03-09 09:38:46 +0000835 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
Duncan Sands014e04a2008-02-12 20:46:31 +0000836 assert(NumParts > 0 && "No parts to assemble!");
837 TargetLowering &TLI = DAG.getTargetLoweringInfo();
Dan Gohman475871a2008-07-27 21:46:04 +0000838 SDValue Val = Parts[0];
Dan Gohman6183f782007-07-05 20:12:34 +0000839
Duncan Sands014e04a2008-02-12 20:46:31 +0000840 if (NumParts > 1) {
841 // Assemble the value from multiple parts.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000842 if (!ValueVT.isVector()) {
843 unsigned PartBits = PartVT.getSizeInBits();
844 unsigned ValueBits = ValueVT.getSizeInBits();
Dan Gohman6183f782007-07-05 20:12:34 +0000845
Duncan Sands014e04a2008-02-12 20:46:31 +0000846 // Assemble the power of 2 part.
847 unsigned RoundParts = NumParts & (NumParts - 1) ?
848 1 << Log2_32(NumParts) : NumParts;
849 unsigned RoundBits = PartBits * RoundParts;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000850 MVT RoundVT = RoundBits == ValueBits ?
851 ValueVT : MVT::getIntegerVT(RoundBits);
Dan Gohman475871a2008-07-27 21:46:04 +0000852 SDValue Lo, Hi;
Duncan Sands014e04a2008-02-12 20:46:31 +0000853
854 if (RoundParts > 2) {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000855 MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
Duncan Sands014e04a2008-02-12 20:46:31 +0000856 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
857 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
858 PartVT, HalfVT);
Dan Gohman6183f782007-07-05 20:12:34 +0000859 } else {
Duncan Sands014e04a2008-02-12 20:46:31 +0000860 Lo = Parts[0];
861 Hi = Parts[1];
Dan Gohman6183f782007-07-05 20:12:34 +0000862 }
Duncan Sands014e04a2008-02-12 20:46:31 +0000863 if (TLI.isBigEndian())
864 std::swap(Lo, Hi);
865 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
866
867 if (RoundParts < NumParts) {
868 // Assemble the trailing non-power-of-2 part.
869 unsigned OddParts = NumParts - RoundParts;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000870 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
Duncan Sands014e04a2008-02-12 20:46:31 +0000871 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
872
873 // Combine the round and odd parts.
874 Lo = Val;
875 if (TLI.isBigEndian())
876 std::swap(Lo, Hi);
Duncan Sands83ec4b62008-06-06 12:08:01 +0000877 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
Duncan Sands014e04a2008-02-12 20:46:31 +0000878 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
879 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
Duncan Sands83ec4b62008-06-06 12:08:01 +0000880 DAG.getConstant(Lo.getValueType().getSizeInBits(),
Duncan Sands014e04a2008-02-12 20:46:31 +0000881 TLI.getShiftAmountTy()));
882 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
883 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
884 }
885 } else {
886 // Handle a multi-element vector.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000887 MVT IntermediateVT, RegisterVT;
Duncan Sands014e04a2008-02-12 20:46:31 +0000888 unsigned NumIntermediates;
889 unsigned NumRegs =
890 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
891 RegisterVT);
Duncan Sands014e04a2008-02-12 20:46:31 +0000892 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
Evan Cheng35213342008-05-14 20:29:30 +0000893 NumParts = NumRegs; // Silence a compiler warning.
Duncan Sands014e04a2008-02-12 20:46:31 +0000894 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
895 assert(RegisterVT == Parts[0].getValueType() &&
896 "Part type doesn't match part!");
897
898 // Assemble the parts into intermediate operands.
Dan Gohman475871a2008-07-27 21:46:04 +0000899 SmallVector<SDValue, 8> Ops(NumIntermediates);
Duncan Sands014e04a2008-02-12 20:46:31 +0000900 if (NumIntermediates == NumParts) {
901 // If the register was not expanded, truncate or copy the value,
902 // as appropriate.
903 for (unsigned i = 0; i != NumParts; ++i)
904 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
905 PartVT, IntermediateVT);
906 } else if (NumParts > 0) {
907 // If the intermediate type was expanded, build the intermediate operands
908 // from the parts.
909 assert(NumParts % NumIntermediates == 0 &&
910 "Must expand into a divisible number of parts!");
911 unsigned Factor = NumParts / NumIntermediates;
912 for (unsigned i = 0; i != NumIntermediates; ++i)
913 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
914 PartVT, IntermediateVT);
915 }
916
917 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
918 // operands.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000919 Val = DAG.getNode(IntermediateVT.isVector() ?
Duncan Sands014e04a2008-02-12 20:46:31 +0000920 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
921 ValueVT, &Ops[0], NumIntermediates);
Dan Gohman6183f782007-07-05 20:12:34 +0000922 }
Dan Gohman6183f782007-07-05 20:12:34 +0000923 }
924
Duncan Sands014e04a2008-02-12 20:46:31 +0000925 // There is now one part, held in Val. Correct it to match ValueVT.
926 PartVT = Val.getValueType();
Dan Gohman6183f782007-07-05 20:12:34 +0000927
Duncan Sands014e04a2008-02-12 20:46:31 +0000928 if (PartVT == ValueVT)
929 return Val;
Dan Gohman6183f782007-07-05 20:12:34 +0000930
Duncan Sands83ec4b62008-06-06 12:08:01 +0000931 if (PartVT.isVector()) {
932 assert(ValueVT.isVector() && "Unknown vector conversion!");
Duncan Sands014e04a2008-02-12 20:46:31 +0000933 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
Dan Gohman6183f782007-07-05 20:12:34 +0000934 }
Duncan Sands014e04a2008-02-12 20:46:31 +0000935
Duncan Sands83ec4b62008-06-06 12:08:01 +0000936 if (ValueVT.isVector()) {
937 assert(ValueVT.getVectorElementType() == PartVT &&
938 ValueVT.getVectorNumElements() == 1 &&
Duncan Sands014e04a2008-02-12 20:46:31 +0000939 "Only trivial scalar-to-vector conversions should get here!");
940 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
941 }
942
Duncan Sands83ec4b62008-06-06 12:08:01 +0000943 if (PartVT.isInteger() &&
944 ValueVT.isInteger()) {
Duncan Sands8e4eb092008-06-08 20:54:56 +0000945 if (ValueVT.bitsLT(PartVT)) {
Duncan Sands014e04a2008-02-12 20:46:31 +0000946 // For a truncate, see if we have any information to
947 // indicate whether the truncated bits will always be
948 // zero or sign-extension.
949 if (AssertOp != ISD::DELETED_NODE)
950 Val = DAG.getNode(AssertOp, PartVT, Val,
951 DAG.getValueType(ValueVT));
952 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
953 } else {
954 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
955 }
956 }
957
Duncan Sands83ec4b62008-06-06 12:08:01 +0000958 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
Duncan Sands8e4eb092008-06-08 20:54:56 +0000959 if (ValueVT.bitsLT(Val.getValueType()))
Chris Lattner4468c1f2008-03-09 09:38:46 +0000960 // FP_ROUND's are always exact here.
Chris Lattnerd43d85c2008-03-09 07:47:22 +0000961 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
Chris Lattner4468c1f2008-03-09 09:38:46 +0000962 DAG.getIntPtrConstant(1));
Chris Lattnerd43d85c2008-03-09 07:47:22 +0000963 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
964 }
Duncan Sands014e04a2008-02-12 20:46:31 +0000965
Duncan Sands83ec4b62008-06-06 12:08:01 +0000966 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
Duncan Sands014e04a2008-02-12 20:46:31 +0000967 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
968
969 assert(0 && "Unknown mismatch!");
Dan Gohman475871a2008-07-27 21:46:04 +0000970 return SDValue();
Dan Gohman6183f782007-07-05 20:12:34 +0000971}
972
Duncan Sandsb988bac2008-02-11 20:58:28 +0000973/// getCopyToParts - Create a series of nodes that contain the specified value
974/// split into legal parts. If the parts contain more bits than Val, then, for
975/// integers, ExtendKind can be used to specify how to generate the extra bits.
Dan Gohman6183f782007-07-05 20:12:34 +0000976static void getCopyToParts(SelectionDAG &DAG,
Dan Gohman475871a2008-07-27 21:46:04 +0000977 SDValue Val,
978 SDValue *Parts,
Dan Gohman6183f782007-07-05 20:12:34 +0000979 unsigned NumParts,
Duncan Sands83ec4b62008-06-06 12:08:01 +0000980 MVT PartVT,
Duncan Sandsb988bac2008-02-11 20:58:28 +0000981 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
Dan Gohman25ac7e82007-08-10 14:59:38 +0000982 TargetLowering &TLI = DAG.getTargetLoweringInfo();
Duncan Sands83ec4b62008-06-06 12:08:01 +0000983 MVT PtrVT = TLI.getPointerTy();
984 MVT ValueVT = Val.getValueType();
985 unsigned PartBits = PartVT.getSizeInBits();
Duncan Sands014e04a2008-02-12 20:46:31 +0000986 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
Dan Gohman6183f782007-07-05 20:12:34 +0000987
Duncan Sands014e04a2008-02-12 20:46:31 +0000988 if (!NumParts)
989 return;
990
Duncan Sands83ec4b62008-06-06 12:08:01 +0000991 if (!ValueVT.isVector()) {
Duncan Sands014e04a2008-02-12 20:46:31 +0000992 if (PartVT == ValueVT) {
993 assert(NumParts == 1 && "No-op copy with multiple parts!");
994 Parts[0] = Val;
Dan Gohman6183f782007-07-05 20:12:34 +0000995 return;
996 }
997
Duncan Sands83ec4b62008-06-06 12:08:01 +0000998 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
Duncan Sands014e04a2008-02-12 20:46:31 +0000999 // If the parts cover more bits than the value has, promote the value.
Duncan Sands83ec4b62008-06-06 12:08:01 +00001000 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
Duncan Sands014e04a2008-02-12 20:46:31 +00001001 assert(NumParts == 1 && "Do not know what to promote to!");
Dan Gohman6183f782007-07-05 20:12:34 +00001002 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
Duncan Sands83ec4b62008-06-06 12:08:01 +00001003 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
1004 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
Duncan Sands014e04a2008-02-12 20:46:31 +00001005 Val = DAG.getNode(ExtendKind, ValueVT, Val);
1006 } else {
1007 assert(0 && "Unknown mismatch!");
1008 }
Duncan Sands83ec4b62008-06-06 12:08:01 +00001009 } else if (PartBits == ValueVT.getSizeInBits()) {
Duncan Sands014e04a2008-02-12 20:46:31 +00001010 // Different types of the same size.
1011 assert(NumParts == 1 && PartVT != ValueVT);
1012 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
Duncan Sands83ec4b62008-06-06 12:08:01 +00001013 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
Duncan Sands014e04a2008-02-12 20:46:31 +00001014 // If the parts cover less bits than value has, truncate the value.
Duncan Sands83ec4b62008-06-06 12:08:01 +00001015 if (PartVT.isInteger() && ValueVT.isInteger()) {
1016 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
Duncan Sands014e04a2008-02-12 20:46:31 +00001017 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
Dan Gohman6183f782007-07-05 20:12:34 +00001018 } else {
1019 assert(0 && "Unknown mismatch!");
1020 }
1021 }
Duncan Sands014e04a2008-02-12 20:46:31 +00001022
1023 // The value may have changed - recompute ValueVT.
1024 ValueVT = Val.getValueType();
Duncan Sands83ec4b62008-06-06 12:08:01 +00001025 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
Duncan Sands014e04a2008-02-12 20:46:31 +00001026 "Failed to tile the value with PartVT!");
1027
1028 if (NumParts == 1) {
1029 assert(PartVT == ValueVT && "Type conversion failed!");
1030 Parts[0] = Val;
1031 return;
1032 }
1033
1034 // Expand the value into multiple parts.
1035 if (NumParts & (NumParts - 1)) {
1036 // The number of parts is not a power of 2. Split off and copy the tail.
Duncan Sands83ec4b62008-06-06 12:08:01 +00001037 assert(PartVT.isInteger() && ValueVT.isInteger() &&
Duncan Sands014e04a2008-02-12 20:46:31 +00001038 "Do not know what to expand to!");
1039 unsigned RoundParts = 1 << Log2_32(NumParts);
1040 unsigned RoundBits = RoundParts * PartBits;
1041 unsigned OddParts = NumParts - RoundParts;
Dan Gohman475871a2008-07-27 21:46:04 +00001042 SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
Duncan Sands014e04a2008-02-12 20:46:31 +00001043 DAG.getConstant(RoundBits,
1044 TLI.getShiftAmountTy()));
1045 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
1046 if (TLI.isBigEndian())
1047 // The odd parts were reversed by getCopyToParts - unreverse them.
1048 std::reverse(Parts + RoundParts, Parts + NumParts);
1049 NumParts = RoundParts;
Duncan Sands83ec4b62008-06-06 12:08:01 +00001050 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
Duncan Sands014e04a2008-02-12 20:46:31 +00001051 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1052 }
1053
1054 // The number of parts is a power of 2. Repeatedly bisect the value using
1055 // EXTRACT_ELEMENT.
Duncan Sands25eb0432008-03-12 20:30:08 +00001056 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
Duncan Sands83ec4b62008-06-06 12:08:01 +00001057 MVT::getIntegerVT(ValueVT.getSizeInBits()),
Duncan Sands25eb0432008-03-12 20:30:08 +00001058 Val);
Duncan Sands014e04a2008-02-12 20:46:31 +00001059 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
1060 for (unsigned i = 0; i < NumParts; i += StepSize) {
1061 unsigned ThisBits = StepSize * PartBits / 2;
Duncan Sands83ec4b62008-06-06 12:08:01 +00001062 MVT ThisVT = MVT::getIntegerVT (ThisBits);
Dan Gohman475871a2008-07-27 21:46:04 +00001063 SDValue &Part0 = Parts[i];
1064 SDValue &Part1 = Parts[i+StepSize/2];
Duncan Sands014e04a2008-02-12 20:46:31 +00001065
Duncan Sands25eb0432008-03-12 20:30:08 +00001066 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1067 DAG.getConstant(1, PtrVT));
1068 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1069 DAG.getConstant(0, PtrVT));
1070
1071 if (ThisBits == PartBits && ThisVT != PartVT) {
1072 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
1073 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
1074 }
Duncan Sands014e04a2008-02-12 20:46:31 +00001075 }
1076 }
1077
1078 if (TLI.isBigEndian())
1079 std::reverse(Parts, Parts + NumParts);
1080
1081 return;
1082 }
1083
1084 // Vector ValueVT.
1085 if (NumParts == 1) {
1086 if (PartVT != ValueVT) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00001087 if (PartVT.isVector()) {
Duncan Sands014e04a2008-02-12 20:46:31 +00001088 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1089 } else {
Duncan Sands83ec4b62008-06-06 12:08:01 +00001090 assert(ValueVT.getVectorElementType() == PartVT &&
1091 ValueVT.getVectorNumElements() == 1 &&
Duncan Sands014e04a2008-02-12 20:46:31 +00001092 "Only trivial vector-to-scalar conversions should get here!");
1093 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
1094 DAG.getConstant(0, PtrVT));
1095 }
1096 }
1097
Dan Gohman6183f782007-07-05 20:12:34 +00001098 Parts[0] = Val;
1099 return;
1100 }
1101
1102 // Handle a multi-element vector.
Duncan Sands83ec4b62008-06-06 12:08:01 +00001103 MVT IntermediateVT, RegisterVT;
Dan Gohman6183f782007-07-05 20:12:34 +00001104 unsigned NumIntermediates;
1105 unsigned NumRegs =
1106 DAG.getTargetLoweringInfo()
1107 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
1108 RegisterVT);
Duncan Sands83ec4b62008-06-06 12:08:01 +00001109 unsigned NumElements = ValueVT.getVectorNumElements();
Dan Gohman6183f782007-07-05 20:12:34 +00001110
1111 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
Evan Cheng35213342008-05-14 20:29:30 +00001112 NumParts = NumRegs; // Silence a compiler warning.
Dan Gohman6183f782007-07-05 20:12:34 +00001113 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
1114
1115 // Split the vector into intermediate operands.
Dan Gohman475871a2008-07-27 21:46:04 +00001116 SmallVector<SDValue, 8> Ops(NumIntermediates);
Dan Gohman6183f782007-07-05 20:12:34 +00001117 for (unsigned i = 0; i != NumIntermediates; ++i)
Duncan Sands83ec4b62008-06-06 12:08:01 +00001118 if (IntermediateVT.isVector())
Dan Gohman6183f782007-07-05 20:12:34 +00001119 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
1120 IntermediateVT, Val,
1121 DAG.getConstant(i * (NumElements / NumIntermediates),
Dan Gohman25ac7e82007-08-10 14:59:38 +00001122 PtrVT));
Dan Gohman6183f782007-07-05 20:12:34 +00001123 else
1124 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
1125 IntermediateVT, Val,
Dan Gohman25ac7e82007-08-10 14:59:38 +00001126 DAG.getConstant(i, PtrVT));
Dan Gohman6183f782007-07-05 20:12:34 +00001127
1128 // Split the intermediate operands into legal parts.
1129 if (NumParts == NumIntermediates) {
1130 // If the register was not expanded, promote or copy the value,
1131 // as appropriate.
1132 for (unsigned i = 0; i != NumParts; ++i)
Dan Gohman532dc2e2007-07-09 20:59:04 +00001133 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
Dan Gohman6183f782007-07-05 20:12:34 +00001134 } else if (NumParts > 0) {
1135 // If the intermediate type was expanded, split each the value into
1136 // legal parts.
1137 assert(NumParts % NumIntermediates == 0 &&
1138 "Must expand into a divisible number of parts!");
1139 unsigned Factor = NumParts / NumIntermediates;
1140 for (unsigned i = 0; i != NumIntermediates; ++i)
Dan Gohman532dc2e2007-07-09 20:59:04 +00001141 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
Dan Gohman6183f782007-07-05 20:12:34 +00001142 }
1143}
1144
1145
Dan Gohman475871a2008-07-27 21:46:04 +00001146SDValue SelectionDAGLowering::getValue(const Value *V) {
1147 SDValue &N = NodeMap[V];
Chris Lattner199862b2006-03-16 19:57:50 +00001148 if (N.Val) return N;
1149
Chris Lattner199862b2006-03-16 19:57:50 +00001150 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00001151 MVT VT = TLI.getValueType(V->getType(), true);
Chris Lattnerb606dba2008-04-28 06:44:42 +00001152
1153 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
1154 return N = DAG.getConstant(CI->getValue(), VT);
1155
1156 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
Chris Lattner199862b2006-03-16 19:57:50 +00001157 return N = DAG.getGlobalAddress(GV, VT);
Chris Lattnerb606dba2008-04-28 06:44:42 +00001158
1159 if (isa<ConstantPointerNull>(C))
Chris Lattner199862b2006-03-16 19:57:50 +00001160 return N = DAG.getConstant(0, TLI.getPointerTy());
Chris Lattnerb606dba2008-04-28 06:44:42 +00001161
1162 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1163 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
1164
Dan Gohman1d685a42008-06-07 02:02:36 +00001165 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
1166 !V->getType()->isAggregateType())
Chris Lattner6833b062008-04-28 07:16:35 +00001167 return N = DAG.getNode(ISD::UNDEF, VT);
Chris Lattnerb606dba2008-04-28 06:44:42 +00001168
1169 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1170 visit(CE->getOpcode(), *CE);
Dan Gohman475871a2008-07-27 21:46:04 +00001171 SDValue N1 = NodeMap[V];
Chris Lattnerb606dba2008-04-28 06:44:42 +00001172 assert(N1.Val && "visit didn't populate the ValueMap!");
1173 return N1;
1174 }
1175
Dan Gohman1d685a42008-06-07 02:02:36 +00001176 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
Dan Gohman475871a2008-07-27 21:46:04 +00001177 SmallVector<SDValue, 4> Constants;
Dan Gohman1d685a42008-06-07 02:02:36 +00001178 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1179 OI != OE; ++OI) {
1180 SDNode *Val = getValue(*OI).Val;
Duncan Sands4bdcb612008-07-02 17:40:58 +00001181 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
Dan Gohman475871a2008-07-27 21:46:04 +00001182 Constants.push_back(SDValue(Val, i));
Dan Gohman1d685a42008-06-07 02:02:36 +00001183 }
Duncan Sands4bdcb612008-07-02 17:40:58 +00001184 return DAG.getMergeValues(&Constants[0], Constants.size());
Dan Gohman1d685a42008-06-07 02:02:36 +00001185 }
1186
1187 if (const ArrayType *ATy = dyn_cast<ArrayType>(C->getType())) {
1188 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1189 "Unknown array constant!");
1190 unsigned NumElts = ATy->getNumElements();
Dan Gohman8a6ccb52008-06-09 15:21:47 +00001191 if (NumElts == 0)
Dan Gohman475871a2008-07-27 21:46:04 +00001192 return SDValue(); // empty array
Dan Gohman1d685a42008-06-07 02:02:36 +00001193 MVT EltVT = TLI.getValueType(ATy->getElementType());
Dan Gohman475871a2008-07-27 21:46:04 +00001194 SmallVector<SDValue, 4> Constants(NumElts);
Dan Gohman1d685a42008-06-07 02:02:36 +00001195 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1196 if (isa<UndefValue>(C))
1197 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1198 else if (EltVT.isFloatingPoint())
1199 Constants[i] = DAG.getConstantFP(0, EltVT);
1200 else
1201 Constants[i] = DAG.getConstant(0, EltVT);
1202 }
Duncan Sands4bdcb612008-07-02 17:40:58 +00001203 return DAG.getMergeValues(&Constants[0], Constants.size());
Dan Gohman1d685a42008-06-07 02:02:36 +00001204 }
1205
1206 if (const StructType *STy = dyn_cast<StructType>(C->getType())) {
1207 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1208 "Unknown struct constant!");
1209 unsigned NumElts = STy->getNumElements();
Dan Gohman8a6ccb52008-06-09 15:21:47 +00001210 if (NumElts == 0)
Dan Gohman475871a2008-07-27 21:46:04 +00001211 return SDValue(); // empty struct
1212 SmallVector<SDValue, 4> Constants(NumElts);
Dan Gohman1d685a42008-06-07 02:02:36 +00001213 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1214 MVT EltVT = TLI.getValueType(STy->getElementType(i));
Dan Gohman1d685a42008-06-07 02:02:36 +00001215 if (isa<UndefValue>(C))
1216 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1217 else if (EltVT.isFloatingPoint())
1218 Constants[i] = DAG.getConstantFP(0, EltVT);
1219 else
1220 Constants[i] = DAG.getConstant(0, EltVT);
1221 }
Duncan Sands4bdcb612008-07-02 17:40:58 +00001222 return DAG.getMergeValues(&Constants[0], Constants.size());
Dan Gohman1d685a42008-06-07 02:02:36 +00001223 }
1224
Chris Lattner6833b062008-04-28 07:16:35 +00001225 const VectorType *VecTy = cast<VectorType>(V->getType());
Chris Lattnerb606dba2008-04-28 06:44:42 +00001226 unsigned NumElements = VecTy->getNumElements();
Chris Lattnerb606dba2008-04-28 06:44:42 +00001227
Chris Lattner6833b062008-04-28 07:16:35 +00001228 // Now that we know the number and type of the elements, get that number of
1229 // elements into the Ops array based on what kind of constant it is.
Dan Gohman475871a2008-07-27 21:46:04 +00001230 SmallVector<SDValue, 16> Ops;
Chris Lattnerb606dba2008-04-28 06:44:42 +00001231 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1232 for (unsigned i = 0; i != NumElements; ++i)
1233 Ops.push_back(getValue(CP->getOperand(i)));
1234 } else {
Chris Lattner6833b062008-04-28 07:16:35 +00001235 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1236 "Unknown vector constant!");
Duncan Sands83ec4b62008-06-06 12:08:01 +00001237 MVT EltVT = TLI.getValueType(VecTy->getElementType());
Chris Lattner6833b062008-04-28 07:16:35 +00001238
Dan Gohman475871a2008-07-27 21:46:04 +00001239 SDValue Op;
Chris Lattner6833b062008-04-28 07:16:35 +00001240 if (isa<UndefValue>(C))
1241 Op = DAG.getNode(ISD::UNDEF, EltVT);
Duncan Sands83ec4b62008-06-06 12:08:01 +00001242 else if (EltVT.isFloatingPoint())
Chris Lattner6833b062008-04-28 07:16:35 +00001243 Op = DAG.getConstantFP(0, EltVT);
Chris Lattnerb606dba2008-04-28 06:44:42 +00001244 else
Chris Lattner6833b062008-04-28 07:16:35 +00001245 Op = DAG.getConstant(0, EltVT);
Chris Lattnerb606dba2008-04-28 06:44:42 +00001246 Ops.assign(NumElements, Op);
1247 }
1248
1249 // Create a BUILD_VECTOR node.
1250 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
Chris Lattner199862b2006-03-16 19:57:50 +00001251 }
1252
Chris Lattnerb606dba2008-04-28 06:44:42 +00001253 // If this is a static alloca, generate it as the frameindex instead of
1254 // computation.
Chris Lattner199862b2006-03-16 19:57:50 +00001255 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1256 std::map<const AllocaInst*, int>::iterator SI =
Chris Lattnerb606dba2008-04-28 06:44:42 +00001257 FuncInfo.StaticAllocaMap.find(AI);
Chris Lattner199862b2006-03-16 19:57:50 +00001258 if (SI != FuncInfo.StaticAllocaMap.end())
1259 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1260 }
1261
Chris Lattner251db182007-02-25 18:40:32 +00001262 unsigned InReg = FuncInfo.ValueMap[V];
1263 assert(InReg && "Value not in map!");
Chris Lattner199862b2006-03-16 19:57:50 +00001264
Chris Lattner6833b062008-04-28 07:16:35 +00001265 RegsForValue RFV(TLI, InReg, V->getType());
Dan Gohman475871a2008-07-27 21:46:04 +00001266 SDValue Chain = DAG.getEntryNode();
Dan Gohmanb6f5b002007-06-28 23:29:44 +00001267 return RFV.getCopyFromRegs(DAG, Chain, NULL);
Chris Lattner199862b2006-03-16 19:57:50 +00001268}
1269
1270
Chris Lattner1c08c712005-01-07 07:47:53 +00001271void SelectionDAGLowering::visitRet(ReturnInst &I) {
1272 if (I.getNumOperands() == 0) {
Dan Gohman86e1ebf2008-03-27 19:56:19 +00001273 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
Chris Lattner1c08c712005-01-07 07:47:53 +00001274 return;
1275 }
Chris Lattnerb606dba2008-04-28 06:44:42 +00001276
Dan Gohman475871a2008-07-27 21:46:04 +00001277 SmallVector<SDValue, 8> NewValues;
Dan Gohman86e1ebf2008-03-27 19:56:19 +00001278 NewValues.push_back(getControlRoot());
1279 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00001280 SDValue RetOp = getValue(I.getOperand(i));
Duncan Sandsb988bac2008-02-11 20:58:28 +00001281
Dan Gohmanab8ec0a2008-06-20 01:29:26 +00001282 SmallVector<MVT, 4> ValueVTs;
1283 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
1284 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) {
1285 MVT VT = ValueVTs[j];
Duncan Sandsb988bac2008-02-11 20:58:28 +00001286
Dan Gohmanab8ec0a2008-06-20 01:29:26 +00001287 // FIXME: C calling convention requires the return type to be promoted to
1288 // at least 32-bit. But this is not necessary for non-C calling conventions.
1289 if (VT.isInteger()) {
1290 MVT MinVT = TLI.getRegisterType(MVT::i32);
1291 if (VT.bitsLT(MinVT))
1292 VT = MinVT;
1293 }
Duncan Sandsb988bac2008-02-11 20:58:28 +00001294
Dan Gohmanab8ec0a2008-06-20 01:29:26 +00001295 unsigned NumParts = TLI.getNumRegisters(VT);
1296 MVT PartVT = TLI.getRegisterType(VT);
Dan Gohman475871a2008-07-27 21:46:04 +00001297 SmallVector<SDValue, 4> Parts(NumParts);
Dan Gohmanab8ec0a2008-06-20 01:29:26 +00001298 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1299
1300 const Function *F = I.getParent()->getParent();
1301 if (F->paramHasAttr(0, ParamAttr::SExt))
1302 ExtendKind = ISD::SIGN_EXTEND;
1303 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1304 ExtendKind = ISD::ZERO_EXTEND;
Duncan Sandsb988bac2008-02-11 20:58:28 +00001305
Dan Gohman475871a2008-07-27 21:46:04 +00001306 getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.ResNo + j),
Dan Gohmanab8ec0a2008-06-20 01:29:26 +00001307 &Parts[0], NumParts, PartVT, ExtendKind);
Duncan Sandsb988bac2008-02-11 20:58:28 +00001308
Dan Gohmanab8ec0a2008-06-20 01:29:26 +00001309 for (unsigned i = 0; i < NumParts; ++i) {
1310 NewValues.push_back(Parts[i]);
1311 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
1312 }
Nate Begemanee625572006-01-27 21:09:22 +00001313 }
Chris Lattner1c08c712005-01-07 07:47:53 +00001314 }
Chris Lattnerbd564bf2006-08-08 02:23:42 +00001315 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1316 &NewValues[0], NewValues.size()));
Chris Lattner1c08c712005-01-07 07:47:53 +00001317}
1318
Chris Lattner571e4342006-10-27 21:36:01 +00001319/// ExportFromCurrentBlock - If this condition isn't known to be exported from
1320/// the current basic block, add it to ValueMap now so that we'll get a
1321/// CopyTo/FromReg.
1322void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1323 // No need to export constants.
1324 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1325
1326 // Already exported?
1327 if (FuncInfo.isExportedInst(V)) return;
1328
1329 unsigned Reg = FuncInfo.InitializeRegForValue(V);
Dan Gohman86e1ebf2008-03-27 19:56:19 +00001330 CopyValueToVirtualRegister(V, Reg);
Chris Lattner571e4342006-10-27 21:36:01 +00001331}
1332
Chris Lattner8c494ab2006-10-27 23:50:33 +00001333bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1334 const BasicBlock *FromBB) {
1335 // The operands of the setcc have to be in this block. We don't know
1336 // how to export them from some other block.
1337 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1338 // Can export from current BB.
1339 if (VI->getParent() == FromBB)
1340 return true;
1341
1342 // Is already exported, noop.
1343 return FuncInfo.isExportedInst(V);
1344 }
1345
1346 // If this is an argument, we can export it if the BB is the entry block or
1347 // if it is already exported.
1348 if (isa<Argument>(V)) {
1349 if (FromBB == &FromBB->getParent()->getEntryBlock())
1350 return true;
1351
1352 // Otherwise, can only export this if it is already exported.
1353 return FuncInfo.isExportedInst(V);
1354 }
1355
1356 // Otherwise, constants can always be exported.
1357 return true;
1358}
1359
Chris Lattner6a586c82006-10-29 21:01:20 +00001360static bool InBlock(const Value *V, const BasicBlock *BB) {
1361 if (const Instruction *I = dyn_cast<Instruction>(V))
1362 return I->getParent() == BB;
1363 return true;
1364}
1365
Chris Lattner571e4342006-10-27 21:36:01 +00001366/// FindMergedConditions - If Cond is an expression like
1367void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1368 MachineBasicBlock *TBB,
1369 MachineBasicBlock *FBB,
1370 MachineBasicBlock *CurBB,
1371 unsigned Opc) {
Chris Lattner571e4342006-10-27 21:36:01 +00001372 // If this node is not part of the or/and tree, emit it as a branch.
Reid Spencere4d87aa2006-12-23 06:05:41 +00001373 Instruction *BOp = dyn_cast<Instruction>(Cond);
Chris Lattner571e4342006-10-27 21:36:01 +00001374
Reid Spencere4d87aa2006-12-23 06:05:41 +00001375 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1376 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
Chris Lattner6a586c82006-10-29 21:01:20 +00001377 BOp->getParent() != CurBB->getBasicBlock() ||
1378 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1379 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
Chris Lattner571e4342006-10-27 21:36:01 +00001380 const BasicBlock *BB = CurBB->getBasicBlock();
1381
Reid Spencere4d87aa2006-12-23 06:05:41 +00001382 // If the leaf of the tree is a comparison, merge the condition into
1383 // the caseblock.
1384 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1385 // The operands of the cmp have to be in this block. We don't know
Chris Lattner5a145f02006-10-29 18:23:37 +00001386 // how to export them from some other block. If this is the first block
1387 // of the sequence, no exporting is needed.
1388 (CurBB == CurMBB ||
1389 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1390 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
Reid Spencere4d87aa2006-12-23 06:05:41 +00001391 BOp = cast<Instruction>(Cond);
1392 ISD::CondCode Condition;
1393 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1394 switch (IC->getPredicate()) {
1395 default: assert(0 && "Unknown icmp predicate opcode!");
1396 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1397 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1398 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1399 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1400 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1401 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1402 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1403 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1404 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1405 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1406 }
1407 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1408 ISD::CondCode FPC, FOC;
1409 switch (FC->getPredicate()) {
1410 default: assert(0 && "Unknown fcmp predicate opcode!");
1411 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1412 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1413 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1414 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1415 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1416 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1417 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
Chris Lattner6bf30ab2008-05-01 07:26:11 +00001418 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1419 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
Reid Spencere4d87aa2006-12-23 06:05:41 +00001420 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1421 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1422 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1423 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1424 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1425 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1426 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1427 }
1428 if (FiniteOnlyFPMath())
1429 Condition = FOC;
1430 else
1431 Condition = FPC;
1432 } else {
Chris Lattner0da331f2007-02-04 01:31:47 +00001433 Condition = ISD::SETEQ; // silence warning.
Reid Spencere4d87aa2006-12-23 06:05:41 +00001434 assert(0 && "Unknown compare instruction");
Chris Lattner571e4342006-10-27 21:36:01 +00001435 }
1436
Chris Lattner571e4342006-10-27 21:36:01 +00001437 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001438 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
Chris Lattner571e4342006-10-27 21:36:01 +00001439 SwitchCases.push_back(CB);
1440 return;
1441 }
1442
1443 // Create a CaseBlock record representing this branch.
Zhou Sheng6b6b6ef2007-01-11 12:24:14 +00001444 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001445 NULL, TBB, FBB, CurBB);
Chris Lattner571e4342006-10-27 21:36:01 +00001446 SwitchCases.push_back(CB);
Chris Lattner571e4342006-10-27 21:36:01 +00001447 return;
1448 }
1449
Chris Lattnerd2f9ee92006-10-27 21:54:23 +00001450
1451 // Create TmpBB after CurBB.
Chris Lattner571e4342006-10-27 21:36:01 +00001452 MachineFunction::iterator BBI = CurBB;
Dan Gohman0e5f1302008-07-07 23:02:41 +00001453 MachineFunction &MF = DAG.getMachineFunction();
1454 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1455 CurBB->getParent()->insert(++BBI, TmpBB);
Chris Lattner571e4342006-10-27 21:36:01 +00001456
Chris Lattnerd2f9ee92006-10-27 21:54:23 +00001457 if (Opc == Instruction::Or) {
1458 // Codegen X | Y as:
1459 // jmp_if_X TBB
1460 // jmp TmpBB
1461 // TmpBB:
1462 // jmp_if_Y TBB
1463 // jmp FBB
1464 //
Chris Lattner571e4342006-10-27 21:36:01 +00001465
Chris Lattnerd2f9ee92006-10-27 21:54:23 +00001466 // Emit the LHS condition.
1467 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1468
1469 // Emit the RHS condition into TmpBB.
1470 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1471 } else {
1472 assert(Opc == Instruction::And && "Unknown merge op!");
1473 // Codegen X & Y as:
1474 // jmp_if_X TmpBB
1475 // jmp FBB
1476 // TmpBB:
1477 // jmp_if_Y TBB
1478 // jmp FBB
1479 //
1480 // This requires creation of TmpBB after CurBB.
1481
1482 // Emit the LHS condition.
1483 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1484
1485 // Emit the RHS condition into TmpBB.
1486 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1487 }
Chris Lattner571e4342006-10-27 21:36:01 +00001488}
1489
Chris Lattnerdf19f272006-10-31 22:37:42 +00001490/// If the set of cases should be emitted as a series of branches, return true.
1491/// If we should emit this as a bunch of and/or'd together conditions, return
1492/// false.
1493static bool
1494ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1495 if (Cases.size() != 2) return true;
1496
Chris Lattner0ccb5002006-10-31 23:06:00 +00001497 // If this is two comparisons of the same values or'd or and'd together, they
1498 // will get folded into a single comparison, so don't emit two blocks.
1499 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1500 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1501 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1502 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1503 return false;
1504 }
1505
Chris Lattnerdf19f272006-10-31 22:37:42 +00001506 return true;
1507}
1508
Chris Lattner1c08c712005-01-07 07:47:53 +00001509void SelectionDAGLowering::visitBr(BranchInst &I) {
1510 // Update machine-CFG edges.
1511 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
Chris Lattner1c08c712005-01-07 07:47:53 +00001512
1513 // Figure out which block is immediately after the current one.
1514 MachineBasicBlock *NextBlock = 0;
1515 MachineFunction::iterator BBI = CurMBB;
1516 if (++BBI != CurMBB->getParent()->end())
1517 NextBlock = BBI;
1518
1519 if (I.isUnconditional()) {
Owen Anderson2d389e82008-06-07 00:00:23 +00001520 // Update machine-CFG edges.
1521 CurMBB->addSuccessor(Succ0MBB);
1522
Chris Lattner1c08c712005-01-07 07:47:53 +00001523 // If this is not a fall-through branch, emit the branch.
1524 if (Succ0MBB != NextBlock)
Dan Gohman86e1ebf2008-03-27 19:56:19 +00001525 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
Misha Brukmandedf2bd2005-04-22 04:01:18 +00001526 DAG.getBasicBlock(Succ0MBB)));
Chris Lattner57ab6592006-10-24 17:57:59 +00001527 return;
1528 }
1529
1530 // If this condition is one of the special cases we handle, do special stuff
1531 // now.
1532 Value *CondVal = I.getCondition();
Chris Lattner57ab6592006-10-24 17:57:59 +00001533 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
Chris Lattner571e4342006-10-27 21:36:01 +00001534
1535 // If this is a series of conditions that are or'd or and'd together, emit
1536 // this as a sequence of branches instead of setcc's with and/or operations.
1537 // For example, instead of something like:
1538 // cmp A, B
1539 // C = seteq
1540 // cmp D, E
1541 // F = setle
1542 // or C, F
1543 // jnz foo
1544 // Emit:
1545 // cmp A, B
1546 // je foo
1547 // cmp D, E
1548 // jle foo
1549 //
1550 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1551 if (BOp->hasOneUse() &&
Chris Lattnerd2f9ee92006-10-27 21:54:23 +00001552 (BOp->getOpcode() == Instruction::And ||
Chris Lattner571e4342006-10-27 21:36:01 +00001553 BOp->getOpcode() == Instruction::Or)) {
1554 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
Chris Lattner0ccb5002006-10-31 23:06:00 +00001555 // If the compares in later blocks need to use values not currently
1556 // exported from this block, export them now. This block should always
1557 // be the first entry.
1558 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1559
Chris Lattnerdf19f272006-10-31 22:37:42 +00001560 // Allow some cases to be rejected.
1561 if (ShouldEmitAsBranches(SwitchCases)) {
Chris Lattnerdf19f272006-10-31 22:37:42 +00001562 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1563 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1564 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1565 }
1566
1567 // Emit the branch for this block.
1568 visitSwitchCase(SwitchCases[0]);
1569 SwitchCases.erase(SwitchCases.begin());
1570 return;
Chris Lattner5a145f02006-10-29 18:23:37 +00001571 }
1572
Chris Lattner0ccb5002006-10-31 23:06:00 +00001573 // Okay, we decided not to do this, remove any inserted MBB's and clear
1574 // SwitchCases.
1575 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
Dan Gohman0e5f1302008-07-07 23:02:41 +00001576 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
Chris Lattner0ccb5002006-10-31 23:06:00 +00001577
Chris Lattnerdf19f272006-10-31 22:37:42 +00001578 SwitchCases.clear();
Chris Lattner571e4342006-10-27 21:36:01 +00001579 }
1580 }
Chris Lattner24525952006-10-24 18:07:37 +00001581
1582 // Create a CaseBlock record representing this branch.
Zhou Sheng6b6b6ef2007-01-11 12:24:14 +00001583 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001584 NULL, Succ0MBB, Succ1MBB, CurMBB);
Chris Lattner24525952006-10-24 18:07:37 +00001585 // Use visitSwitchCase to actually insert the fast branch sequence for this
1586 // cond branch.
1587 visitSwitchCase(CB);
Chris Lattner1c08c712005-01-07 07:47:53 +00001588}
1589
Nate Begemanf15485a2006-03-27 01:32:24 +00001590/// visitSwitchCase - Emits the necessary code to represent a single node in
1591/// the binary search tree resulting from lowering a switch instruction.
1592void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
Dan Gohman475871a2008-07-27 21:46:04 +00001593 SDValue Cond;
1594 SDValue CondLHS = getValue(CB.CmpLHS);
Chris Lattner57ab6592006-10-24 17:57:59 +00001595
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001596 // Build the setcc now.
1597 if (CB.CmpMHS == NULL) {
1598 // Fold "(X == true)" to X and "(X == false)" to !X to
1599 // handle common cases produced by branch lowering.
1600 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1601 Cond = CondLHS;
1602 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
Dan Gohman475871a2008-07-27 21:46:04 +00001603 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001604 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1605 } else
1606 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1607 } else {
1608 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001609
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001610 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1611 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1612
Dan Gohman475871a2008-07-27 21:46:04 +00001613 SDValue CmpOp = getValue(CB.CmpMHS);
Duncan Sands83ec4b62008-06-06 12:08:01 +00001614 MVT VT = CmpOp.getValueType();
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001615
1616 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1617 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1618 } else {
Dan Gohman475871a2008-07-27 21:46:04 +00001619 SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001620 Cond = DAG.getSetCC(MVT::i1, SUB,
1621 DAG.getConstant(High-Low, VT), ISD::SETULE);
1622 }
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001623 }
1624
Owen Anderson2d389e82008-06-07 00:00:23 +00001625 // Update successor info
1626 CurMBB->addSuccessor(CB.TrueBB);
1627 CurMBB->addSuccessor(CB.FalseBB);
1628
Nate Begemanf15485a2006-03-27 01:32:24 +00001629 // Set NextBlock to be the MBB immediately after the current one, if any.
1630 // This is used to avoid emitting unnecessary branches to the next block.
1631 MachineBasicBlock *NextBlock = 0;
1632 MachineFunction::iterator BBI = CurMBB;
1633 if (++BBI != CurMBB->getParent()->end())
1634 NextBlock = BBI;
1635
1636 // If the lhs block is the next block, invert the condition so that we can
1637 // fall through to the lhs instead of the rhs block.
Chris Lattner57ab6592006-10-24 17:57:59 +00001638 if (CB.TrueBB == NextBlock) {
1639 std::swap(CB.TrueBB, CB.FalseBB);
Dan Gohman475871a2008-07-27 21:46:04 +00001640 SDValue True = DAG.getConstant(1, Cond.getValueType());
Nate Begemanf15485a2006-03-27 01:32:24 +00001641 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1642 }
Dan Gohman475871a2008-07-27 21:46:04 +00001643 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
Chris Lattner57ab6592006-10-24 17:57:59 +00001644 DAG.getBasicBlock(CB.TrueBB));
1645 if (CB.FalseBB == NextBlock)
Nate Begemanf15485a2006-03-27 01:32:24 +00001646 DAG.setRoot(BrCond);
1647 else
1648 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
Chris Lattner57ab6592006-10-24 17:57:59 +00001649 DAG.getBasicBlock(CB.FalseBB)));
Nate Begemanf15485a2006-03-27 01:32:24 +00001650}
1651
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001652/// visitJumpTable - Emit JumpTable node in the current MBB
Nate Begeman37efe672006-04-22 18:53:45 +00001653void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
Nate Begeman37efe672006-04-22 18:53:45 +00001654 // Emit the code for the jump table
Scott Michelf147a8d2007-04-24 01:24:20 +00001655 assert(JT.Reg != -1U && "Should lower JT Header first!");
Duncan Sands83ec4b62008-06-06 12:08:01 +00001656 MVT PTy = TLI.getPointerTy();
Dan Gohman475871a2008-07-27 21:46:04 +00001657 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1658 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
Evan Cheng3d4ce112006-10-30 08:00:44 +00001659 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1660 Table, Index));
1661 return;
Nate Begeman37efe672006-04-22 18:53:45 +00001662}
1663
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001664/// visitJumpTableHeader - This function emits necessary code to produce index
1665/// in the JumpTable from switch case.
1666void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1667 SelectionDAGISel::JumpTableHeader &JTH) {
1668 // Subtract the lowest switch case value from the value being switched on
1669 // and conditional branch to default mbb if the result is greater than the
1670 // difference between smallest and largest cases.
Dan Gohman475871a2008-07-27 21:46:04 +00001671 SDValue SwitchOp = getValue(JTH.SValue);
Duncan Sands83ec4b62008-06-06 12:08:01 +00001672 MVT VT = SwitchOp.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +00001673 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001674 DAG.getConstant(JTH.First, VT));
1675
1676 // The SDNode we just created, which holds the value being switched on
1677 // minus the the smallest case value, needs to be copied to a virtual
1678 // register so it can be used as an index into the jump table in a
1679 // subsequent basic block. This value may be smaller or larger than the
1680 // target's pointer type, and therefore require extension or truncating.
Duncan Sands8e4eb092008-06-08 20:54:56 +00001681 if (VT.bitsGT(TLI.getPointerTy()))
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001682 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1683 else
1684 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1685
1686 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
Dan Gohman475871a2008-07-27 21:46:04 +00001687 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001688 JT.Reg = JumpTableReg;
1689
1690 // Emit the range check for the jump table, and branch to the default
1691 // block for the switch statement if the value being switched on exceeds
1692 // the largest case in the switch.
Dan Gohman475871a2008-07-27 21:46:04 +00001693 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001694 DAG.getConstant(JTH.Last-JTH.First,VT),
1695 ISD::SETUGT);
1696
1697 // Set NextBlock to be the MBB immediately after the current one, if any.
1698 // This is used to avoid emitting unnecessary branches to the next block.
1699 MachineBasicBlock *NextBlock = 0;
1700 MachineFunction::iterator BBI = CurMBB;
1701 if (++BBI != CurMBB->getParent()->end())
1702 NextBlock = BBI;
1703
Dan Gohman475871a2008-07-27 21:46:04 +00001704 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001705 DAG.getBasicBlock(JT.Default));
1706
1707 if (JT.MBB == NextBlock)
1708 DAG.setRoot(BrCond);
1709 else
1710 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001711 DAG.getBasicBlock(JT.MBB)));
1712
1713 return;
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001714}
1715
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001716/// visitBitTestHeader - This function emits necessary code to produce value
1717/// suitable for "bit tests"
1718void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1719 // Subtract the minimum value
Dan Gohman475871a2008-07-27 21:46:04 +00001720 SDValue SwitchOp = getValue(B.SValue);
Duncan Sands83ec4b62008-06-06 12:08:01 +00001721 MVT VT = SwitchOp.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +00001722 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001723 DAG.getConstant(B.First, VT));
1724
1725 // Check range
Dan Gohman475871a2008-07-27 21:46:04 +00001726 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001727 DAG.getConstant(B.Range, VT),
1728 ISD::SETUGT);
1729
Dan Gohman475871a2008-07-27 21:46:04 +00001730 SDValue ShiftOp;
Duncan Sands8e4eb092008-06-08 20:54:56 +00001731 if (VT.bitsGT(TLI.getShiftAmountTy()))
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001732 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1733 else
1734 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1735
1736 // Make desired shift
Dan Gohman475871a2008-07-27 21:46:04 +00001737 SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001738 DAG.getConstant(1, TLI.getPointerTy()),
1739 ShiftOp);
1740
1741 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
Dan Gohman475871a2008-07-27 21:46:04 +00001742 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001743 B.Reg = SwitchReg;
1744
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001745 // Set NextBlock to be the MBB immediately after the current one, if any.
1746 // This is used to avoid emitting unnecessary branches to the next block.
1747 MachineBasicBlock *NextBlock = 0;
1748 MachineFunction::iterator BBI = CurMBB;
1749 if (++BBI != CurMBB->getParent()->end())
1750 NextBlock = BBI;
1751
1752 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
Owen Anderson2d389e82008-06-07 00:00:23 +00001753
1754 CurMBB->addSuccessor(B.Default);
1755 CurMBB->addSuccessor(MBB);
1756
Dan Gohman475871a2008-07-27 21:46:04 +00001757 SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
Owen Anderson2d389e82008-06-07 00:00:23 +00001758 DAG.getBasicBlock(B.Default));
1759
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001760 if (MBB == NextBlock)
1761 DAG.setRoot(BrRange);
1762 else
1763 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1764 DAG.getBasicBlock(MBB)));
1765
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001766 return;
1767}
1768
1769/// visitBitTestCase - this function produces one "bit test"
1770void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1771 unsigned Reg,
1772 SelectionDAGISel::BitTestCase &B) {
1773 // Emit bit tests and jumps
Dan Gohman475871a2008-07-27 21:46:04 +00001774 SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
Chris Lattneread0d882008-06-17 06:09:18 +00001775 TLI.getPointerTy());
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001776
Dan Gohman475871a2008-07-27 21:46:04 +00001777 SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
Chris Lattneread0d882008-06-17 06:09:18 +00001778 DAG.getConstant(B.Mask, TLI.getPointerTy()));
Dan Gohman475871a2008-07-27 21:46:04 +00001779 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001780 DAG.getConstant(0, TLI.getPointerTy()),
1781 ISD::SETNE);
Owen Anderson2d389e82008-06-07 00:00:23 +00001782
1783 CurMBB->addSuccessor(B.TargetBB);
1784 CurMBB->addSuccessor(NextMBB);
1785
Dan Gohman475871a2008-07-27 21:46:04 +00001786 SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001787 AndCmp, DAG.getBasicBlock(B.TargetBB));
1788
1789 // Set NextBlock to be the MBB immediately after the current one, if any.
1790 // This is used to avoid emitting unnecessary branches to the next block.
1791 MachineBasicBlock *NextBlock = 0;
1792 MachineFunction::iterator BBI = CurMBB;
1793 if (++BBI != CurMBB->getParent()->end())
1794 NextBlock = BBI;
1795
1796 if (NextMBB == NextBlock)
1797 DAG.setRoot(BrAnd);
1798 else
1799 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1800 DAG.getBasicBlock(NextMBB)));
1801
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001802 return;
1803}
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001804
Jim Laskeyb180aa12007-02-21 22:53:45 +00001805void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1806 // Retrieve successors.
1807 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
Duncan Sandsf19f6bb2007-06-13 05:51:31 +00001808 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
Duncan Sands9fac0b52007-06-06 10:05:18 +00001809
Duncan Sandsfd7b3262007-12-17 18:08:19 +00001810 if (isa<InlineAsm>(I.getCalledValue()))
1811 visitInlineAsm(&I);
1812 else
Duncan Sands6f74b482007-12-19 09:48:52 +00001813 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
Duncan Sands9fac0b52007-06-06 10:05:18 +00001814
Duncan Sandsf19f6bb2007-06-13 05:51:31 +00001815 // If the value of the invoke is used outside of its defining block, make it
1816 // available as a virtual register.
1817 if (!I.use_empty()) {
1818 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1819 if (VMI != FuncInfo.ValueMap.end())
Dan Gohman86e1ebf2008-03-27 19:56:19 +00001820 CopyValueToVirtualRegister(&I, VMI->second);
Jim Laskey183f47f2007-02-25 21:43:59 +00001821 }
Duncan Sandsf19f6bb2007-06-13 05:51:31 +00001822
Duncan Sandsf19f6bb2007-06-13 05:51:31 +00001823 // Update successor info
1824 CurMBB->addSuccessor(Return);
1825 CurMBB->addSuccessor(LandingPad);
Owen Anderson2d389e82008-06-07 00:00:23 +00001826
1827 // Drop into normal successor.
1828 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1829 DAG.getBasicBlock(Return)));
Jim Laskeyb180aa12007-02-21 22:53:45 +00001830}
1831
1832void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1833}
1834
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001835/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001836/// small case ranges).
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001837bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001838 CaseRecVector& WorkList,
1839 Value* SV,
1840 MachineBasicBlock* Default) {
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001841 Case& BackCase = *(CR.Range.second-1);
1842
1843 // Size is the number of Cases represented by this range.
1844 unsigned Size = CR.Range.second - CR.Range.first;
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001845 if (Size > 3)
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001846 return false;
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001847
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001848 // Get the MachineFunction which holds the current MBB. This is used when
1849 // inserting any additional MBBs necessary to represent the switch.
1850 MachineFunction *CurMF = CurMBB->getParent();
1851
1852 // Figure out which block is immediately after the current one.
1853 MachineBasicBlock *NextBlock = 0;
1854 MachineFunction::iterator BBI = CR.CaseBB;
1855
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001856 if (++BBI != CurMBB->getParent()->end())
1857 NextBlock = BBI;
1858
1859 // TODO: If any two of the cases has the same destination, and if one value
1860 // is the same as the other, but has one bit unset that the other has set,
1861 // use bit manipulation to do two compares at once. For example:
1862 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1863
1864 // Rearrange the case blocks so that the last one falls through if possible.
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001865 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001866 // The last case block won't fall through into 'NextBlock' if we emit the
1867 // branches in this order. See if rearranging a case value would help.
1868 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001869 if (I->BB == NextBlock) {
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001870 std::swap(*I, BackCase);
1871 break;
1872 }
1873 }
1874 }
1875
1876 // Create a CaseBlock record representing a conditional branch to
1877 // the Case's target mbb if the value being switched on SV is equal
1878 // to C.
1879 MachineBasicBlock *CurBlock = CR.CaseBB;
1880 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1881 MachineBasicBlock *FallThrough;
1882 if (I != E-1) {
Dan Gohman0e5f1302008-07-07 23:02:41 +00001883 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1884 CurMF->insert(BBI, FallThrough);
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001885 } else {
1886 // If the last case doesn't match, go to the default block.
1887 FallThrough = Default;
1888 }
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001889
1890 Value *RHS, *LHS, *MHS;
1891 ISD::CondCode CC;
1892 if (I->High == I->Low) {
1893 // This is just small small case range :) containing exactly 1 case
1894 CC = ISD::SETEQ;
1895 LHS = SV; RHS = I->High; MHS = NULL;
1896 } else {
1897 CC = ISD::SETLE;
1898 LHS = I->Low; MHS = SV; RHS = I->High;
1899 }
1900 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1901 I->BB, FallThrough, CurBlock);
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001902
1903 // If emitting the first comparison, just call visitSwitchCase to emit the
1904 // code into the current block. Otherwise, push the CaseBlock onto the
1905 // vector to be later processed by SDISel, and insert the node's MBB
1906 // before the next MBB.
1907 if (CurBlock == CurMBB)
1908 visitSwitchCase(CB);
1909 else
1910 SwitchCases.push_back(CB);
1911
1912 CurBlock = FallThrough;
1913 }
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001914
1915 return true;
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001916}
1917
Anton Korobeynikov7294b582007-05-09 20:07:08 +00001918static inline bool areJTsAllowed(const TargetLowering &TLI) {
1919 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1920 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1921}
1922
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001923/// handleJTSwitchCase - Emit jumptable for current switch case range
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001924bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001925 CaseRecVector& WorkList,
1926 Value* SV,
1927 MachineBasicBlock* Default) {
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001928 Case& FrontCase = *CR.Range.first;
1929 Case& BackCase = *(CR.Range.second-1);
1930
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001931 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1932 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1933
1934 uint64_t TSize = 0;
1935 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1936 I!=E; ++I)
1937 TSize += I->size();
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001938
Anton Korobeynikov7294b582007-05-09 20:07:08 +00001939 if (!areJTsAllowed(TLI) || TSize <= 3)
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001940 return false;
1941
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001942 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1943 if (Density < 0.4)
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001944 return false;
1945
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001946 DOUT << "Lowering jump table\n"
1947 << "First entry: " << First << ". Last entry: " << Last << "\n"
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001948 << "Size: " << TSize << ". Density: " << Density << "\n\n";
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001949
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001950 // Get the MachineFunction which holds the current MBB. This is used when
1951 // inserting any additional MBBs necessary to represent the switch.
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001952 MachineFunction *CurMF = CurMBB->getParent();
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001953
1954 // Figure out which block is immediately after the current one.
1955 MachineBasicBlock *NextBlock = 0;
1956 MachineFunction::iterator BBI = CR.CaseBB;
1957
1958 if (++BBI != CurMBB->getParent()->end())
1959 NextBlock = BBI;
1960
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001961 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1962
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001963 // Create a new basic block to hold the code for loading the address
1964 // of the jump table, and jumping to it. Update successor information;
1965 // we will either branch to the default case for the switch, or the jump
1966 // table.
Dan Gohman0e5f1302008-07-07 23:02:41 +00001967 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1968 CurMF->insert(BBI, JumpTableBB);
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001969 CR.CaseBB->addSuccessor(Default);
1970 CR.CaseBB->addSuccessor(JumpTableBB);
1971
1972 // Build a vector of destination BBs, corresponding to each target
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001973 // of the jump table. If the value of the jump table slot corresponds to
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001974 // a case statement, push the case's BB onto the vector, otherwise, push
1975 // the default BB.
1976 std::vector<MachineBasicBlock*> DestBBs;
1977 int64_t TEI = First;
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001978 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1979 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1980 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1981
1982 if ((Low <= TEI) && (TEI <= High)) {
1983 DestBBs.push_back(I->BB);
1984 if (TEI==High)
1985 ++I;
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001986 } else {
1987 DestBBs.push_back(Default);
1988 }
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001989 }
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001990
1991 // Update successor info. Add one edge to each unique successor.
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001992 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001993 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1994 E = DestBBs.end(); I != E; ++I) {
1995 if (!SuccsHandled[(*I)->getNumber()]) {
1996 SuccsHandled[(*I)->getNumber()] = true;
1997 JumpTableBB->addSuccessor(*I);
1998 }
1999 }
2000
2001 // Create a jump table index for this jump table, or return an existing
2002 // one.
2003 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
2004
2005 // Set the jump table information so that we can codegen it as a second
2006 // MachineBasicBlock
Scott Michelf147a8d2007-04-24 01:24:20 +00002007 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002008 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
2009 (CR.CaseBB == CurMBB));
2010 if (CR.CaseBB == CurMBB)
2011 visitJumpTableHeader(JT, JTH);
2012
2013 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002014
Anton Korobeynikovdd433212007-03-27 12:05:48 +00002015 return true;
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002016}
2017
2018/// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2019/// 2 subtrees.
Anton Korobeynikovdd433212007-03-27 12:05:48 +00002020bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002021 CaseRecVector& WorkList,
2022 Value* SV,
2023 MachineBasicBlock* Default) {
2024 // Get the MachineFunction which holds the current MBB. This is used when
2025 // inserting any additional MBBs necessary to represent the switch.
2026 MachineFunction *CurMF = CurMBB->getParent();
2027
2028 // Figure out which block is immediately after the current one.
2029 MachineBasicBlock *NextBlock = 0;
2030 MachineFunction::iterator BBI = CR.CaseBB;
2031
2032 if (++BBI != CurMBB->getParent()->end())
2033 NextBlock = BBI;
2034
2035 Case& FrontCase = *CR.Range.first;
2036 Case& BackCase = *(CR.Range.second-1);
2037 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2038
2039 // Size is the number of Cases represented by this range.
2040 unsigned Size = CR.Range.second - CR.Range.first;
2041
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00002042 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
2043 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
Anton Korobeynikov4198c582007-04-09 12:31:58 +00002044 double FMetric = 0;
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00002045 CaseItr Pivot = CR.Range.first + Size/2;
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002046
2047 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2048 // (heuristically) allow us to emit JumpTable's later.
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00002049 uint64_t TSize = 0;
2050 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2051 I!=E; ++I)
2052 TSize += I->size();
2053
2054 uint64_t LSize = FrontCase.size();
2055 uint64_t RSize = TSize-LSize;
Anton Korobeynikov4198c582007-04-09 12:31:58 +00002056 DOUT << "Selecting best pivot: \n"
2057 << "First: " << First << ", Last: " << Last <<"\n"
2058 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002059 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00002060 J!=E; ++I, ++J) {
2061 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
2062 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
Anton Korobeynikov4198c582007-04-09 12:31:58 +00002063 assert((RBegin-LEnd>=1) && "Invalid case distance");
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002064 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
2065 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
Anton Korobeynikov54e2b142007-04-09 21:57:03 +00002066 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
Anton Korobeynikov4198c582007-04-09 12:31:58 +00002067 // Should always split in some non-trivial place
2068 DOUT <<"=>Step\n"
2069 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
2070 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
2071 << "Metric: " << Metric << "\n";
2072 if (FMetric < Metric) {
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002073 Pivot = J;
Anton Korobeynikov4198c582007-04-09 12:31:58 +00002074 FMetric = Metric;
2075 DOUT << "Current metric set to: " << FMetric << "\n";
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002076 }
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00002077
2078 LSize += J->size();
2079 RSize -= J->size();
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002080 }
Anton Korobeynikov7294b582007-05-09 20:07:08 +00002081 if (areJTsAllowed(TLI)) {
2082 // If our case is dense we *really* should handle it earlier!
2083 assert((FMetric > 0) && "Should handle dense range earlier!");
2084 } else {
2085 Pivot = CR.Range.first + Size/2;
2086 }
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002087
2088 CaseRange LHSR(CR.Range.first, Pivot);
2089 CaseRange RHSR(Pivot, CR.Range.second);
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00002090 Constant *C = Pivot->Low;
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002091 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2092
2093 // We know that we branch to the LHS if the Value being switched on is
2094 // less than the Pivot value, C. We use this to optimize our binary
2095 // tree a bit, by recognizing that if SV is greater than or equal to the
2096 // LHS's Case Value, and that Case Value is exactly one less than the
2097 // Pivot's Value, then we can branch directly to the LHS's Target,
2098 // rather than creating a leaf node for it.
2099 if ((LHSR.second - LHSR.first) == 1 &&
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00002100 LHSR.first->High == CR.GE &&
2101 cast<ConstantInt>(C)->getSExtValue() ==
2102 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
2103 TrueBB = LHSR.first->BB;
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002104 } else {
Dan Gohman0e5f1302008-07-07 23:02:41 +00002105 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2106 CurMF->insert(BBI, TrueBB);
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002107 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2108 }
2109
2110 // Similar to the optimization above, if the Value being switched on is
2111 // known to be less than the Constant CR.LT, and the current Case Value
2112 // is CR.LT - 1, then we can branch directly to the target block for
2113 // the current Case Value, rather than emitting a RHS leaf node for it.
2114 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00002115 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
2116 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
2117 FalseBB = RHSR.first->BB;
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002118 } else {
Dan Gohman0e5f1302008-07-07 23:02:41 +00002119 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2120 CurMF->insert(BBI, FalseBB);
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002121 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2122 }
2123
2124 // Create a CaseBlock record representing a conditional branch to
2125 // the LHS node if the value being switched on SV is less than C.
2126 // Otherwise, branch to LHS.
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00002127 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
2128 TrueBB, FalseBB, CR.CaseBB);
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002129
2130 if (CR.CaseBB == CurMBB)
2131 visitSwitchCase(CB);
2132 else
2133 SwitchCases.push_back(CB);
Anton Korobeynikovdd433212007-03-27 12:05:48 +00002134
2135 return true;
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002136}
2137
Anton Korobeynikov4198c582007-04-09 12:31:58 +00002138/// handleBitTestsSwitchCase - if current case range has few destination and
2139/// range span less, than machine word bitwidth, encode case range into series
2140/// of masks and emit bit tests with these masks.
2141bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
2142 CaseRecVector& WorkList,
2143 Value* SV,
Chris Lattner3ff98172007-04-14 02:26:56 +00002144 MachineBasicBlock* Default){
Duncan Sands83ec4b62008-06-06 12:08:01 +00002145 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
Anton Korobeynikov4198c582007-04-09 12:31:58 +00002146
2147 Case& FrontCase = *CR.Range.first;
2148 Case& BackCase = *(CR.Range.second-1);
2149
2150 // Get the MachineFunction which holds the current MBB. This is used when
2151 // inserting any additional MBBs necessary to represent the switch.
2152 MachineFunction *CurMF = CurMBB->getParent();
2153
2154 unsigned numCmps = 0;
2155 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2156 I!=E; ++I) {
2157 // Single case counts one, case range - two.
2158 if (I->Low == I->High)
2159 numCmps +=1;
2160 else
2161 numCmps +=2;
2162 }
2163
2164 // Count unique destinations
2165 SmallSet<MachineBasicBlock*, 4> Dests;
2166 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2167 Dests.insert(I->BB);
2168 if (Dests.size() > 3)
2169 // Don't bother the code below, if there are too much unique destinations
2170 return false;
2171 }
2172 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
2173 << "Total number of comparisons: " << numCmps << "\n";
2174
2175 // Compute span of values.
2176 Constant* minValue = FrontCase.Low;
2177 Constant* maxValue = BackCase.High;
2178 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
2179 cast<ConstantInt>(minValue)->getSExtValue();
2180 DOUT << "Compare range: " << range << "\n"
2181 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
2182 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
2183
Anton Korobeynikovab8fd402007-04-26 20:44:04 +00002184 if (range>=IntPtrBits ||
Anton Korobeynikov4198c582007-04-09 12:31:58 +00002185 (!(Dests.size() == 1 && numCmps >= 3) &&
2186 !(Dests.size() == 2 && numCmps >= 5) &&
2187 !(Dests.size() >= 3 && numCmps >= 6)))
2188 return false;
2189
2190 DOUT << "Emitting bit tests\n";
2191 int64_t lowBound = 0;
2192
2193 // Optimize the case where all the case values fit in a
2194 // word without having to subtract minValue. In this case,
2195 // we can optimize away the subtraction.
2196 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
Anton Korobeynikove01017b2007-04-14 13:25:55 +00002197 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
Anton Korobeynikov4198c582007-04-09 12:31:58 +00002198 range = cast<ConstantInt>(maxValue)->getSExtValue();
2199 } else {
2200 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
2201 }
2202
2203 CaseBitsVector CasesBits;
2204 unsigned i, count = 0;
2205
2206 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2207 MachineBasicBlock* Dest = I->BB;
2208 for (i = 0; i < count; ++i)
2209 if (Dest == CasesBits[i].BB)
2210 break;
2211
2212 if (i == count) {
2213 assert((count < 3) && "Too much destinations to test!");
2214 CasesBits.push_back(CaseBits(0, Dest, 0));
2215 count++;
2216 }
2217
2218 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
2219 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
2220
2221 for (uint64_t j = lo; j <= hi; j++) {
Anton Korobeynikove01017b2007-04-14 13:25:55 +00002222 CasesBits[i].Mask |= 1ULL << j;
Anton Korobeynikov4198c582007-04-09 12:31:58 +00002223 CasesBits[i].Bits++;
2224 }
2225
2226 }
2227 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2228
2229 SelectionDAGISel::BitTestInfo BTC;
2230
2231 // Figure out which block is immediately after the current one.
2232 MachineFunction::iterator BBI = CR.CaseBB;
2233 ++BBI;
2234
2235 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2236
2237 DOUT << "Cases:\n";
2238 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2239 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
2240 << ", BB: " << CasesBits[i].BB << "\n";
2241
Dan Gohman0e5f1302008-07-07 23:02:41 +00002242 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2243 CurMF->insert(BBI, CaseBB);
Anton Korobeynikov4198c582007-04-09 12:31:58 +00002244 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
2245 CaseBB,
2246 CasesBits[i].BB));
2247 }
2248
2249 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
Jeff Cohenefc36622007-04-09 14:32:59 +00002250 -1U, (CR.CaseBB == CurMBB),
Anton Korobeynikov4198c582007-04-09 12:31:58 +00002251 CR.CaseBB, Default, BTC);
2252
2253 if (CR.CaseBB == CurMBB)
2254 visitBitTestHeader(BTB);
2255
2256 BitTestCases.push_back(BTB);
2257
2258 return true;
2259}
2260
2261
Dan Gohman86e1ebf2008-03-27 19:56:19 +00002262/// Clusterify - Transform simple list of Cases into list of CaseRange's
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00002263unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2264 const SwitchInst& SI) {
2265 unsigned numCmps = 0;
2266
2267 // Start with "simple" cases
2268 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2269 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2270 Cases.push_back(Case(SI.getSuccessorValue(i),
2271 SI.getSuccessorValue(i),
2272 SMBB));
2273 }
Chris Lattnerb3d9cdb2007-11-27 06:14:32 +00002274 std::sort(Cases.begin(), Cases.end(), CaseCmp());
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00002275
2276 // Merge case into clusters
2277 if (Cases.size()>=2)
David Greenea2a48852007-06-29 03:42:23 +00002278 // Must recompute end() each iteration because it may be
2279 // invalidated by erase if we hold on to it
Chris Lattner27a6c732007-11-24 07:07:01 +00002280 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00002281 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2282 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2283 MachineBasicBlock* nextBB = J->BB;
2284 MachineBasicBlock* currentBB = I->BB;
2285
2286 // If the two neighboring cases go to the same destination, merge them
2287 // into a single case.
2288 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2289 I->High = J->High;
2290 J = Cases.erase(J);
2291 } else {
2292 I = J++;
2293 }
2294 }
2295
2296 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2297 if (I->Low != I->High)
2298 // A range counts double, since it requires two compares.
2299 ++numCmps;
2300 }
2301
2302 return numCmps;
2303}
2304
2305void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
Nate Begemanf15485a2006-03-27 01:32:24 +00002306 // Figure out which block is immediately after the current one.
2307 MachineBasicBlock *NextBlock = 0;
2308 MachineFunction::iterator BBI = CurMBB;
Bill Wendlingc70ddad2006-10-19 21:46:38 +00002309
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00002310 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
Chris Lattnerd2c1d222006-10-22 21:36:53 +00002311
Nate Begemanf15485a2006-03-27 01:32:24 +00002312 // If there is only the default destination, branch to it if it is not the
2313 // next basic block. Otherwise, just fall through.
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00002314 if (SI.getNumOperands() == 2) {
Nate Begemanf15485a2006-03-27 01:32:24 +00002315 // Update machine-CFG edges.
Bill Wendlingc70ddad2006-10-19 21:46:38 +00002316
Nate Begemanf15485a2006-03-27 01:32:24 +00002317 // If this is not a fall-through branch, emit the branch.
Owen Anderson2d389e82008-06-07 00:00:23 +00002318 CurMBB->addSuccessor(Default);
Chris Lattnerd2c1d222006-10-22 21:36:53 +00002319 if (Default != NextBlock)
Dan Gohman86e1ebf2008-03-27 19:56:19 +00002320 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
Chris Lattnerd2c1d222006-10-22 21:36:53 +00002321 DAG.getBasicBlock(Default)));
Owen Anderson2d389e82008-06-07 00:00:23 +00002322
Nate Begemanf15485a2006-03-27 01:32:24 +00002323 return;
2324 }
2325
2326 // If there are any non-default case statements, create a vector of Cases
2327 // representing each one, and sort the vector so that we can efficiently
2328 // create a binary search tree from them.
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00002329 CaseVector Cases;
2330 unsigned numCmps = Clusterify(Cases, SI);
2331 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2332 << ". Total compares: " << numCmps << "\n";
Bill Wendlingc70ddad2006-10-19 21:46:38 +00002333
Nate Begemanf15485a2006-03-27 01:32:24 +00002334 // Get the Value to be switched on and default basic blocks, which will be
2335 // inserted into CaseBlock records, representing basic blocks in the binary
2336 // search tree.
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00002337 Value *SV = SI.getOperand(0);
Nate Begeman37efe672006-04-22 18:53:45 +00002338
Nate Begemanf15485a2006-03-27 01:32:24 +00002339 // Push the initial CaseRec onto the worklist
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00002340 CaseRecVector WorkList;
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00002341 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2342
2343 while (!WorkList.empty()) {
Nate Begemanf15485a2006-03-27 01:32:24 +00002344 // Grab a record representing a case range to process off the worklist
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00002345 CaseRec CR = WorkList.back();
2346 WorkList.pop_back();
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00002347
Anton Korobeynikov4198c582007-04-09 12:31:58 +00002348 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2349 continue;
2350
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00002351 // If the range has few cases (two or less) emit a series of specific
2352 // tests.
Anton Korobeynikovdd433212007-03-27 12:05:48 +00002353 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2354 continue;
2355
Anton Korobeynikov4198c582007-04-09 12:31:58 +00002356 // If the switch has more than 5 blocks, and at least 40% dense, and the
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00002357 // target supports indirect branches, then emit a jump table rather than
2358 // lowering the switch to a binary tree of conditional branches.
Anton Korobeynikovdd433212007-03-27 12:05:48 +00002359 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2360 continue;
2361
2362 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2363 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2364 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
Nate Begemanf15485a2006-03-27 01:32:24 +00002365 }
2366}
2367
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00002368
Chris Lattnerb9fccc42005-04-02 05:04:50 +00002369void SelectionDAGLowering::visitSub(User &I) {
2370 // -0.0 - X --> fneg
Reid Spencer24d6da52007-01-21 00:29:26 +00002371 const Type *Ty = I.getType();
Reid Spencer9d6565a2007-02-15 02:26:10 +00002372 if (isa<VectorType>(Ty)) {
Dan Gohman7f321562007-06-25 16:23:39 +00002373 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2374 const VectorType *DestTy = cast<VectorType>(I.getType());
2375 const Type *ElTy = DestTy->getElementType();
Evan Chengc45453f2007-06-29 21:44:35 +00002376 if (ElTy->isFloatingPoint()) {
2377 unsigned VL = DestTy->getNumElements();
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00002378 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
Evan Chengc45453f2007-06-29 21:44:35 +00002379 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2380 if (CV == CNZ) {
Dan Gohman475871a2008-07-27 21:46:04 +00002381 SDValue Op2 = getValue(I.getOperand(1));
Evan Chengc45453f2007-06-29 21:44:35 +00002382 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2383 return;
2384 }
Dan Gohman7f321562007-06-25 16:23:39 +00002385 }
2386 }
2387 }
2388 if (Ty->isFloatingPoint()) {
Chris Lattner01b3d732005-09-28 22:28:18 +00002389 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00002390 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
Dan Gohman475871a2008-07-27 21:46:04 +00002391 SDValue Op2 = getValue(I.getOperand(1));
Chris Lattner01b3d732005-09-28 22:28:18 +00002392 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2393 return;
2394 }
Dan Gohman7f321562007-06-25 16:23:39 +00002395 }
2396
2397 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
Chris Lattnerb9fccc42005-04-02 05:04:50 +00002398}
2399
Dan Gohman7f321562007-06-25 16:23:39 +00002400void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
Dan Gohman475871a2008-07-27 21:46:04 +00002401 SDValue Op1 = getValue(I.getOperand(0));
2402 SDValue Op2 = getValue(I.getOperand(1));
Reid Spencer24d6da52007-01-21 00:29:26 +00002403
2404 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
Reid Spencer1628cec2006-10-26 06:15:43 +00002405}
2406
Nate Begemane21ea612005-11-18 07:42:56 +00002407void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
Dan Gohman475871a2008-07-27 21:46:04 +00002408 SDValue Op1 = getValue(I.getOperand(0));
2409 SDValue Op2 = getValue(I.getOperand(1));
Nate Begeman5bc1ea02008-07-29 15:49:41 +00002410 if (!isa<VectorType>(I.getType())) {
2411 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
2412 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2413 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2414 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2415 }
Nate Begemane21ea612005-11-18 07:42:56 +00002416
Chris Lattner1c08c712005-01-07 07:47:53 +00002417 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2418}
2419
Reid Spencer45fb3f32006-11-20 01:22:35 +00002420void SelectionDAGLowering::visitICmp(User &I) {
Reid Spencere4d87aa2006-12-23 06:05:41 +00002421 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2422 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2423 predicate = IC->getPredicate();
2424 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2425 predicate = ICmpInst::Predicate(IC->getPredicate());
Dan Gohman475871a2008-07-27 21:46:04 +00002426 SDValue Op1 = getValue(I.getOperand(0));
2427 SDValue Op2 = getValue(I.getOperand(1));
Reid Spencer45fb3f32006-11-20 01:22:35 +00002428 ISD::CondCode Opcode;
Reid Spencere4d87aa2006-12-23 06:05:41 +00002429 switch (predicate) {
Reid Spencer45fb3f32006-11-20 01:22:35 +00002430 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2431 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2432 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2433 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2434 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2435 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2436 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2437 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2438 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2439 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2440 default:
2441 assert(!"Invalid ICmp predicate value");
2442 Opcode = ISD::SETEQ;
2443 break;
2444 }
2445 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2446}
2447
2448void SelectionDAGLowering::visitFCmp(User &I) {
Reid Spencere4d87aa2006-12-23 06:05:41 +00002449 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2450 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2451 predicate = FC->getPredicate();
2452 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2453 predicate = FCmpInst::Predicate(FC->getPredicate());
Dan Gohman475871a2008-07-27 21:46:04 +00002454 SDValue Op1 = getValue(I.getOperand(0));
2455 SDValue Op2 = getValue(I.getOperand(1));
Reid Spencere4d87aa2006-12-23 06:05:41 +00002456 ISD::CondCode Condition, FOC, FPC;
2457 switch (predicate) {
2458 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2459 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2460 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2461 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2462 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2463 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2464 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
Dan Gohmancba3b442008-05-01 23:40:44 +00002465 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2466 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
Reid Spencere4d87aa2006-12-23 06:05:41 +00002467 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2468 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2469 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2470 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2471 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2472 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2473 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2474 default:
2475 assert(!"Invalid FCmp predicate value");
2476 FOC = FPC = ISD::SETFALSE;
2477 break;
2478 }
2479 if (FiniteOnlyFPMath())
2480 Condition = FOC;
2481 else
2482 Condition = FPC;
2483 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
Chris Lattner1c08c712005-01-07 07:47:53 +00002484}
2485
Nate Begemanb43e9c12008-05-12 19:40:03 +00002486void SelectionDAGLowering::visitVICmp(User &I) {
2487 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2488 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2489 predicate = IC->getPredicate();
2490 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2491 predicate = ICmpInst::Predicate(IC->getPredicate());
Dan Gohman475871a2008-07-27 21:46:04 +00002492 SDValue Op1 = getValue(I.getOperand(0));
2493 SDValue Op2 = getValue(I.getOperand(1));
Nate Begemanb43e9c12008-05-12 19:40:03 +00002494 ISD::CondCode Opcode;
2495 switch (predicate) {
2496 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2497 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2498 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2499 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2500 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2501 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2502 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2503 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2504 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2505 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2506 default:
2507 assert(!"Invalid ICmp predicate value");
2508 Opcode = ISD::SETEQ;
2509 break;
2510 }
2511 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2512}
2513
2514void SelectionDAGLowering::visitVFCmp(User &I) {
2515 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2516 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2517 predicate = FC->getPredicate();
2518 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2519 predicate = FCmpInst::Predicate(FC->getPredicate());
Dan Gohman475871a2008-07-27 21:46:04 +00002520 SDValue Op1 = getValue(I.getOperand(0));
2521 SDValue Op2 = getValue(I.getOperand(1));
Nate Begemanb43e9c12008-05-12 19:40:03 +00002522 ISD::CondCode Condition, FOC, FPC;
2523 switch (predicate) {
2524 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2525 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2526 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2527 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2528 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2529 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2530 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2531 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2532 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2533 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2534 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2535 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2536 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2537 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2538 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2539 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2540 default:
2541 assert(!"Invalid VFCmp predicate value");
2542 FOC = FPC = ISD::SETFALSE;
2543 break;
2544 }
2545 if (FiniteOnlyFPMath())
2546 Condition = FOC;
2547 else
2548 Condition = FPC;
2549
Duncan Sands83ec4b62008-06-06 12:08:01 +00002550 MVT DestVT = TLI.getValueType(I.getType());
Nate Begemanb43e9c12008-05-12 19:40:03 +00002551
2552 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2553}
2554
Chris Lattner1c08c712005-01-07 07:47:53 +00002555void SelectionDAGLowering::visitSelect(User &I) {
Dan Gohman475871a2008-07-27 21:46:04 +00002556 SDValue Cond = getValue(I.getOperand(0));
2557 SDValue TrueVal = getValue(I.getOperand(1));
2558 SDValue FalseVal = getValue(I.getOperand(2));
Dan Gohman7f321562007-06-25 16:23:39 +00002559 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2560 TrueVal, FalseVal));
Chris Lattner1c08c712005-01-07 07:47:53 +00002561}
2562
Reid Spencer3da59db2006-11-27 01:05:10 +00002563
2564void SelectionDAGLowering::visitTrunc(User &I) {
2565 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
Dan Gohman475871a2008-07-27 21:46:04 +00002566 SDValue N = getValue(I.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +00002567 MVT DestVT = TLI.getValueType(I.getType());
Reid Spencer3da59db2006-11-27 01:05:10 +00002568 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2569}
2570
2571void SelectionDAGLowering::visitZExt(User &I) {
2572 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2573 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
Dan Gohman475871a2008-07-27 21:46:04 +00002574 SDValue N = getValue(I.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +00002575 MVT DestVT = TLI.getValueType(I.getType());
Reid Spencer3da59db2006-11-27 01:05:10 +00002576 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2577}
2578
2579void SelectionDAGLowering::visitSExt(User &I) {
2580 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2581 // SExt also can't be a cast to bool for same reason. So, nothing much to do
Dan Gohman475871a2008-07-27 21:46:04 +00002582 SDValue N = getValue(I.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +00002583 MVT DestVT = TLI.getValueType(I.getType());
Reid Spencer3da59db2006-11-27 01:05:10 +00002584 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2585}
2586
2587void SelectionDAGLowering::visitFPTrunc(User &I) {
2588 // FPTrunc is never a no-op cast, no need to check
Dan Gohman475871a2008-07-27 21:46:04 +00002589 SDValue N = getValue(I.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +00002590 MVT DestVT = TLI.getValueType(I.getType());
Chris Lattner0bd48932008-01-17 07:00:52 +00002591 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
Reid Spencer3da59db2006-11-27 01:05:10 +00002592}
2593
2594void SelectionDAGLowering::visitFPExt(User &I){
2595 // FPTrunc is never a no-op cast, no need to check
Dan Gohman475871a2008-07-27 21:46:04 +00002596 SDValue N = getValue(I.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +00002597 MVT DestVT = TLI.getValueType(I.getType());
Reid Spencer3da59db2006-11-27 01:05:10 +00002598 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2599}
2600
2601void SelectionDAGLowering::visitFPToUI(User &I) {
2602 // FPToUI is never a no-op cast, no need to check
Dan Gohman475871a2008-07-27 21:46:04 +00002603 SDValue N = getValue(I.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +00002604 MVT DestVT = TLI.getValueType(I.getType());
Reid Spencer3da59db2006-11-27 01:05:10 +00002605 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2606}
2607
2608void SelectionDAGLowering::visitFPToSI(User &I) {
2609 // FPToSI is never a no-op cast, no need to check
Dan Gohman475871a2008-07-27 21:46:04 +00002610 SDValue N = getValue(I.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +00002611 MVT DestVT = TLI.getValueType(I.getType());
Reid Spencer3da59db2006-11-27 01:05:10 +00002612 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2613}
2614
2615void SelectionDAGLowering::visitUIToFP(User &I) {
2616 // UIToFP is never a no-op cast, no need to check
Dan Gohman475871a2008-07-27 21:46:04 +00002617 SDValue N = getValue(I.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +00002618 MVT DestVT = TLI.getValueType(I.getType());
Reid Spencer3da59db2006-11-27 01:05:10 +00002619 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2620}
2621
2622void SelectionDAGLowering::visitSIToFP(User &I){
2623 // UIToFP is never a no-op cast, no need to check
Dan Gohman475871a2008-07-27 21:46:04 +00002624 SDValue N = getValue(I.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +00002625 MVT DestVT = TLI.getValueType(I.getType());
Reid Spencer3da59db2006-11-27 01:05:10 +00002626 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2627}
2628
2629void SelectionDAGLowering::visitPtrToInt(User &I) {
2630 // What to do depends on the size of the integer and the size of the pointer.
2631 // We can either truncate, zero extend, or no-op, accordingly.
Dan Gohman475871a2008-07-27 21:46:04 +00002632 SDValue N = getValue(I.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +00002633 MVT SrcVT = N.getValueType();
2634 MVT DestVT = TLI.getValueType(I.getType());
Dan Gohman475871a2008-07-27 21:46:04 +00002635 SDValue Result;
Duncan Sands8e4eb092008-06-08 20:54:56 +00002636 if (DestVT.bitsLT(SrcVT))
Reid Spencer3da59db2006-11-27 01:05:10 +00002637 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2638 else
2639 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2640 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2641 setValue(&I, Result);
2642}
Chris Lattner1c08c712005-01-07 07:47:53 +00002643
Reid Spencer3da59db2006-11-27 01:05:10 +00002644void SelectionDAGLowering::visitIntToPtr(User &I) {
2645 // What to do depends on the size of the integer and the size of the pointer.
2646 // We can either truncate, zero extend, or no-op, accordingly.
Dan Gohman475871a2008-07-27 21:46:04 +00002647 SDValue N = getValue(I.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +00002648 MVT SrcVT = N.getValueType();
2649 MVT DestVT = TLI.getValueType(I.getType());
Duncan Sands8e4eb092008-06-08 20:54:56 +00002650 if (DestVT.bitsLT(SrcVT))
Reid Spencer3da59db2006-11-27 01:05:10 +00002651 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2652 else
2653 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2654 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2655}
2656
2657void SelectionDAGLowering::visitBitCast(User &I) {
Dan Gohman475871a2008-07-27 21:46:04 +00002658 SDValue N = getValue(I.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +00002659 MVT DestVT = TLI.getValueType(I.getType());
Reid Spencer3da59db2006-11-27 01:05:10 +00002660
2661 // BitCast assures us that source and destination are the same size so this
2662 // is either a BIT_CONVERT or a no-op.
2663 if (DestVT != N.getValueType())
2664 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2665 else
2666 setValue(&I, N); // noop cast.
Chris Lattner1c08c712005-01-07 07:47:53 +00002667}
2668
Chris Lattner2bbd8102006-03-29 00:11:43 +00002669void SelectionDAGLowering::visitInsertElement(User &I) {
Dan Gohman475871a2008-07-27 21:46:04 +00002670 SDValue InVec = getValue(I.getOperand(0));
2671 SDValue InVal = getValue(I.getOperand(1));
2672 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
Chris Lattnerc7029802006-03-18 01:44:44 +00002673 getValue(I.getOperand(2)));
2674
Dan Gohman7f321562007-06-25 16:23:39 +00002675 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2676 TLI.getValueType(I.getType()),
2677 InVec, InVal, InIdx));
Chris Lattnerc7029802006-03-18 01:44:44 +00002678}
2679
Chris Lattner2bbd8102006-03-29 00:11:43 +00002680void SelectionDAGLowering::visitExtractElement(User &I) {
Dan Gohman475871a2008-07-27 21:46:04 +00002681 SDValue InVec = getValue(I.getOperand(0));
2682 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
Chris Lattner384504c2006-03-21 20:44:12 +00002683 getValue(I.getOperand(1)));
Dan Gohman7f321562007-06-25 16:23:39 +00002684 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
Chris Lattner384504c2006-03-21 20:44:12 +00002685 TLI.getValueType(I.getType()), InVec, InIdx));
2686}
Chris Lattnerc7029802006-03-18 01:44:44 +00002687
Chris Lattner3e104b12006-04-08 04:15:24 +00002688void SelectionDAGLowering::visitShuffleVector(User &I) {
Dan Gohman475871a2008-07-27 21:46:04 +00002689 SDValue V1 = getValue(I.getOperand(0));
2690 SDValue V2 = getValue(I.getOperand(1));
2691 SDValue Mask = getValue(I.getOperand(2));
Chris Lattner3e104b12006-04-08 04:15:24 +00002692
Dan Gohman7f321562007-06-25 16:23:39 +00002693 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2694 TLI.getValueType(I.getType()),
2695 V1, V2, Mask));
Chris Lattner3e104b12006-04-08 04:15:24 +00002696}
2697
Dan Gohman1d685a42008-06-07 02:02:36 +00002698void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2699 const Value *Op0 = I.getOperand(0);
2700 const Value *Op1 = I.getOperand(1);
2701 const Type *AggTy = I.getType();
2702 const Type *ValTy = Op1->getType();
2703 bool IntoUndef = isa<UndefValue>(Op0);
2704 bool FromUndef = isa<UndefValue>(Op1);
2705
2706 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2707 I.idx_begin(), I.idx_end());
2708
2709 SmallVector<MVT, 4> AggValueVTs;
2710 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2711 SmallVector<MVT, 4> ValValueVTs;
2712 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2713
2714 unsigned NumAggValues = AggValueVTs.size();
2715 unsigned NumValValues = ValValueVTs.size();
Dan Gohman475871a2008-07-27 21:46:04 +00002716 SmallVector<SDValue, 4> Values(NumAggValues);
Dan Gohman1d685a42008-06-07 02:02:36 +00002717
Dan Gohman475871a2008-07-27 21:46:04 +00002718 SDValue Agg = getValue(Op0);
2719 SDValue Val = getValue(Op1);
Dan Gohman1d685a42008-06-07 02:02:36 +00002720 unsigned i = 0;
2721 // Copy the beginning value(s) from the original aggregate.
2722 for (; i != LinearIndex; ++i)
2723 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
Dan Gohman475871a2008-07-27 21:46:04 +00002724 SDValue(Agg.Val, Agg.ResNo + i);
Dan Gohman1d685a42008-06-07 02:02:36 +00002725 // Copy values from the inserted value(s).
2726 for (; i != LinearIndex + NumValValues; ++i)
2727 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
Dan Gohman475871a2008-07-27 21:46:04 +00002728 SDValue(Val.Val, Val.ResNo + i - LinearIndex);
Dan Gohman1d685a42008-06-07 02:02:36 +00002729 // Copy remaining value(s) from the original aggregate.
2730 for (; i != NumAggValues; ++i)
2731 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
Dan Gohman475871a2008-07-27 21:46:04 +00002732 SDValue(Agg.Val, Agg.ResNo + i);
Dan Gohman1d685a42008-06-07 02:02:36 +00002733
Duncan Sandsf9516202008-06-30 10:19:09 +00002734 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
2735 &Values[0], NumAggValues));
Dan Gohman041e2eb2008-05-15 19:50:34 +00002736}
2737
Dan Gohman1d685a42008-06-07 02:02:36 +00002738void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2739 const Value *Op0 = I.getOperand(0);
2740 const Type *AggTy = Op0->getType();
2741 const Type *ValTy = I.getType();
2742 bool OutOfUndef = isa<UndefValue>(Op0);
2743
2744 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2745 I.idx_begin(), I.idx_end());
2746
2747 SmallVector<MVT, 4> ValValueVTs;
2748 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2749
2750 unsigned NumValValues = ValValueVTs.size();
Dan Gohman475871a2008-07-27 21:46:04 +00002751 SmallVector<SDValue, 4> Values(NumValValues);
Dan Gohman1d685a42008-06-07 02:02:36 +00002752
Dan Gohman475871a2008-07-27 21:46:04 +00002753 SDValue Agg = getValue(Op0);
Dan Gohman1d685a42008-06-07 02:02:36 +00002754 // Copy out the selected value(s).
2755 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2756 Values[i - LinearIndex] =
Dan Gohmandded0fd2008-06-20 00:54:19 +00002757 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) :
Dan Gohman475871a2008-07-27 21:46:04 +00002758 SDValue(Agg.Val, Agg.ResNo + i);
Dan Gohman1d685a42008-06-07 02:02:36 +00002759
Duncan Sandsf9516202008-06-30 10:19:09 +00002760 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
2761 &Values[0], NumValValues));
Dan Gohman041e2eb2008-05-15 19:50:34 +00002762}
2763
Chris Lattner3e104b12006-04-08 04:15:24 +00002764
Chris Lattner1c08c712005-01-07 07:47:53 +00002765void SelectionDAGLowering::visitGetElementPtr(User &I) {
Dan Gohman475871a2008-07-27 21:46:04 +00002766 SDValue N = getValue(I.getOperand(0));
Chris Lattner1c08c712005-01-07 07:47:53 +00002767 const Type *Ty = I.getOperand(0)->getType();
Chris Lattner1c08c712005-01-07 07:47:53 +00002768
2769 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2770 OI != E; ++OI) {
2771 Value *Idx = *OI;
Chris Lattnerc88d8e92005-12-05 07:10:48 +00002772 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
Reid Spencerb83eb642006-10-20 07:07:24 +00002773 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
Chris Lattner1c08c712005-01-07 07:47:53 +00002774 if (Field) {
2775 // N = N + Offset
Chris Lattnerb1919e22007-02-10 19:55:17 +00002776 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
Chris Lattner1c08c712005-01-07 07:47:53 +00002777 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
Chris Lattner0bd48932008-01-17 07:00:52 +00002778 DAG.getIntPtrConstant(Offset));
Chris Lattner1c08c712005-01-07 07:47:53 +00002779 }
2780 Ty = StTy->getElementType(Field);
2781 } else {
2782 Ty = cast<SequentialType>(Ty)->getElementType();
Chris Lattner7cc47772005-01-07 21:56:57 +00002783
Chris Lattner7c0104b2005-11-09 04:45:33 +00002784 // If this is a constant subscript, handle it quickly.
2785 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
Reid Spencerb83eb642006-10-20 07:07:24 +00002786 if (CI->getZExtValue() == 0) continue;
Reid Spencer47857812006-12-31 05:55:36 +00002787 uint64_t Offs =
Dale Johannesena7ac2bd2007-10-01 23:08:35 +00002788 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
Chris Lattner0bd48932008-01-17 07:00:52 +00002789 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2790 DAG.getIntPtrConstant(Offs));
Chris Lattner7c0104b2005-11-09 04:45:33 +00002791 continue;
Chris Lattner1c08c712005-01-07 07:47:53 +00002792 }
Chris Lattner7c0104b2005-11-09 04:45:33 +00002793
2794 // N = N + Idx * ElementSize;
Dale Johannesena7ac2bd2007-10-01 23:08:35 +00002795 uint64_t ElementSize = TD->getABITypeSize(Ty);
Dan Gohman475871a2008-07-27 21:46:04 +00002796 SDValue IdxN = getValue(Idx);
Chris Lattner7c0104b2005-11-09 04:45:33 +00002797
2798 // If the index is smaller or larger than intptr_t, truncate or extend
2799 // it.
Duncan Sands8e4eb092008-06-08 20:54:56 +00002800 if (IdxN.getValueType().bitsLT(N.getValueType())) {
Reid Spencer47857812006-12-31 05:55:36 +00002801 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
Duncan Sands8e4eb092008-06-08 20:54:56 +00002802 } else if (IdxN.getValueType().bitsGT(N.getValueType()))
Chris Lattner7c0104b2005-11-09 04:45:33 +00002803 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2804
2805 // If this is a multiply by a power of two, turn it into a shl
2806 // immediately. This is a very common case.
2807 if (isPowerOf2_64(ElementSize)) {
2808 unsigned Amt = Log2_64(ElementSize);
2809 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
Chris Lattner6b2d6962005-11-09 16:50:40 +00002810 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
Chris Lattner7c0104b2005-11-09 04:45:33 +00002811 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2812 continue;
2813 }
2814
Dan Gohman475871a2008-07-27 21:46:04 +00002815 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
Chris Lattner7c0104b2005-11-09 04:45:33 +00002816 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2817 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
Chris Lattner1c08c712005-01-07 07:47:53 +00002818 }
2819 }
2820 setValue(&I, N);
2821}
2822
2823void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2824 // If this is a fixed sized alloca in the entry block of the function,
2825 // allocate it statically on the stack.
2826 if (FuncInfo.StaticAllocaMap.count(&I))
2827 return; // getValue will auto-populate this.
2828
2829 const Type *Ty = I.getAllocatedType();
Duncan Sands514ab342007-11-01 20:53:16 +00002830 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
Chris Lattner58092e32007-01-20 22:35:55 +00002831 unsigned Align =
Chris Lattnerd2b7cec2007-02-14 05:52:17 +00002832 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
Chris Lattner58092e32007-01-20 22:35:55 +00002833 I.getAlignment());
Chris Lattner1c08c712005-01-07 07:47:53 +00002834
Dan Gohman475871a2008-07-27 21:46:04 +00002835 SDValue AllocSize = getValue(I.getArraySize());
Duncan Sands83ec4b62008-06-06 12:08:01 +00002836 MVT IntPtr = TLI.getPointerTy();
Duncan Sands8e4eb092008-06-08 20:54:56 +00002837 if (IntPtr.bitsLT(AllocSize.getValueType()))
Chris Lattner68cd65e2005-01-22 23:04:37 +00002838 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
Duncan Sands8e4eb092008-06-08 20:54:56 +00002839 else if (IntPtr.bitsGT(AllocSize.getValueType()))
Chris Lattner68cd65e2005-01-22 23:04:37 +00002840 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
Chris Lattner1c08c712005-01-07 07:47:53 +00002841
Chris Lattner68cd65e2005-01-22 23:04:37 +00002842 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
Chris Lattner0bd48932008-01-17 07:00:52 +00002843 DAG.getIntPtrConstant(TySize));
Chris Lattner1c08c712005-01-07 07:47:53 +00002844
Evan Cheng45157792007-08-16 23:46:29 +00002845 // Handle alignment. If the requested alignment is less than or equal to
2846 // the stack alignment, ignore it. If the size is greater than or equal to
2847 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
Chris Lattner1c08c712005-01-07 07:47:53 +00002848 unsigned StackAlign =
2849 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
Evan Cheng45157792007-08-16 23:46:29 +00002850 if (Align <= StackAlign)
Chris Lattner1c08c712005-01-07 07:47:53 +00002851 Align = 0;
Evan Cheng45157792007-08-16 23:46:29 +00002852
2853 // Round the size of the allocation up to the stack alignment size
2854 // by add SA-1 to the size.
2855 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
Chris Lattner0bd48932008-01-17 07:00:52 +00002856 DAG.getIntPtrConstant(StackAlign-1));
Evan Cheng45157792007-08-16 23:46:29 +00002857 // Mask out the low bits for alignment purposes.
2858 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
Chris Lattner0bd48932008-01-17 07:00:52 +00002859 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
Chris Lattner1c08c712005-01-07 07:47:53 +00002860
Dan Gohman475871a2008-07-27 21:46:04 +00002861 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
Duncan Sands83ec4b62008-06-06 12:08:01 +00002862 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00002863 MVT::Other);
Dan Gohman475871a2008-07-27 21:46:04 +00002864 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
Chris Lattner0da331f2007-02-04 01:31:47 +00002865 setValue(&I, DSA);
2866 DAG.setRoot(DSA.getValue(1));
Chris Lattner1c08c712005-01-07 07:47:53 +00002867
2868 // Inform the Frame Information that we have just allocated a variable-sized
2869 // object.
2870 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2871}
2872
Chris Lattner1c08c712005-01-07 07:47:53 +00002873void SelectionDAGLowering::visitLoad(LoadInst &I) {
Dan Gohman8a6ccb52008-06-09 15:21:47 +00002874 const Value *SV = I.getOperand(0);
Dan Gohman475871a2008-07-27 21:46:04 +00002875 SDValue Ptr = getValue(SV);
Dan Gohman8a6ccb52008-06-09 15:21:47 +00002876
2877 const Type *Ty = I.getType();
2878 bool isVolatile = I.isVolatile();
2879 unsigned Alignment = I.getAlignment();
2880
2881 SmallVector<MVT, 4> ValueVTs;
2882 SmallVector<uint64_t, 4> Offsets;
2883 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2884 unsigned NumValues = ValueVTs.size();
2885 if (NumValues == 0)
2886 return;
Misha Brukmanedf128a2005-04-21 22:36:52 +00002887
Dan Gohman475871a2008-07-27 21:46:04 +00002888 SDValue Root;
Dan Gohman8b4588f2008-07-25 00:04:14 +00002889 bool ConstantMemory = false;
Chris Lattnerd3948112005-01-17 22:19:26 +00002890 if (I.isVolatile())
Dan Gohman8b4588f2008-07-25 00:04:14 +00002891 // Serialize volatile loads with other side effects.
Chris Lattnerd3948112005-01-17 22:19:26 +00002892 Root = getRoot();
Dan Gohman8b4588f2008-07-25 00:04:14 +00002893 else if (AA.pointsToConstantMemory(SV)) {
2894 // Do not serialize (non-volatile) loads of constant memory with anything.
2895 Root = DAG.getEntryNode();
2896 ConstantMemory = true;
2897 } else {
Chris Lattnerd3948112005-01-17 22:19:26 +00002898 // Do not serialize non-volatile loads against each other.
2899 Root = DAG.getRoot();
2900 }
Chris Lattner28b5b1c2006-03-15 22:19:46 +00002901
Dan Gohman475871a2008-07-27 21:46:04 +00002902 SmallVector<SDValue, 4> Values(NumValues);
2903 SmallVector<SDValue, 4> Chains(NumValues);
Dan Gohman1d685a42008-06-07 02:02:36 +00002904 MVT PtrVT = Ptr.getValueType();
2905 for (unsigned i = 0; i != NumValues; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002906 SDValue L = DAG.getLoad(ValueVTs[i], Root,
Dan Gohman1d685a42008-06-07 02:02:36 +00002907 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2908 DAG.getConstant(Offsets[i], PtrVT)),
2909 SV, Offsets[i],
2910 isVolatile, Alignment);
2911 Values[i] = L;
2912 Chains[i] = L.getValue(1);
2913 }
Chris Lattner28b5b1c2006-03-15 22:19:46 +00002914
Dan Gohman8b4588f2008-07-25 00:04:14 +00002915 if (!ConstantMemory) {
Dan Gohman475871a2008-07-27 21:46:04 +00002916 SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
Dan Gohman8b4588f2008-07-25 00:04:14 +00002917 &Chains[0], NumValues);
2918 if (isVolatile)
2919 DAG.setRoot(Chain);
2920 else
2921 PendingLoads.push_back(Chain);
2922 }
Dan Gohman1d685a42008-06-07 02:02:36 +00002923
Duncan Sandsf9516202008-06-30 10:19:09 +00002924 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues),
2925 &Values[0], NumValues));
Chris Lattner1c08c712005-01-07 07:47:53 +00002926}
2927
2928
2929void SelectionDAGLowering::visitStore(StoreInst &I) {
2930 Value *SrcV = I.getOperand(0);
Dan Gohman1d685a42008-06-07 02:02:36 +00002931 Value *PtrV = I.getOperand(1);
Dan Gohman1d685a42008-06-07 02:02:36 +00002932
2933 SmallVector<MVT, 4> ValueVTs;
2934 SmallVector<uint64_t, 4> Offsets;
2935 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2936 unsigned NumValues = ValueVTs.size();
Dan Gohman8a6ccb52008-06-09 15:21:47 +00002937 if (NumValues == 0)
2938 return;
Dan Gohman1d685a42008-06-07 02:02:36 +00002939
Dan Gohman90d33ee2008-07-30 18:36:51 +00002940 // Get the lowered operands. Note that we do this after
2941 // checking if NumResults is zero, because with zero results
2942 // the operands won't have values in the map.
2943 SDValue Src = getValue(SrcV);
2944 SDValue Ptr = getValue(PtrV);
2945
Dan Gohman475871a2008-07-27 21:46:04 +00002946 SDValue Root = getRoot();
2947 SmallVector<SDValue, 4> Chains(NumValues);
Dan Gohman1d685a42008-06-07 02:02:36 +00002948 MVT PtrVT = Ptr.getValueType();
2949 bool isVolatile = I.isVolatile();
2950 unsigned Alignment = I.getAlignment();
2951 for (unsigned i = 0; i != NumValues; ++i)
Dan Gohman475871a2008-07-27 21:46:04 +00002952 Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.ResNo + i),
Dan Gohman1d685a42008-06-07 02:02:36 +00002953 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2954 DAG.getConstant(Offsets[i], PtrVT)),
2955 PtrV, Offsets[i],
2956 isVolatile, Alignment);
2957
2958 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
Chris Lattner1c08c712005-01-07 07:47:53 +00002959}
2960
Chris Lattner0eade312006-03-24 02:22:33 +00002961/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2962/// node.
2963void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2964 unsigned Intrinsic) {
Duncan Sandsa3355ff2007-12-03 20:06:50 +00002965 bool HasChain = !I.doesNotAccessMemory();
2966 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2967
Chris Lattner0eade312006-03-24 02:22:33 +00002968 // Build the operand list.
Dan Gohman475871a2008-07-27 21:46:04 +00002969 SmallVector<SDValue, 8> Ops;
Chris Lattnere58a7802006-04-02 03:41:14 +00002970 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2971 if (OnlyLoad) {
2972 // We don't need to serialize loads against other loads.
2973 Ops.push_back(DAG.getRoot());
2974 } else {
2975 Ops.push_back(getRoot());
2976 }
2977 }
Chris Lattner0eade312006-03-24 02:22:33 +00002978
2979 // Add the intrinsic ID as an integer operand.
2980 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2981
2982 // Add all operands of the call to the operand list.
2983 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002984 SDValue Op = getValue(I.getOperand(i));
Chris Lattner0eade312006-03-24 02:22:33 +00002985 assert(TLI.isTypeLegal(Op.getValueType()) &&
2986 "Intrinsic uses a non-legal type?");
2987 Ops.push_back(Op);
2988 }
2989
Duncan Sands83ec4b62008-06-06 12:08:01 +00002990 std::vector<MVT> VTs;
Chris Lattner0eade312006-03-24 02:22:33 +00002991 if (I.getType() != Type::VoidTy) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00002992 MVT VT = TLI.getValueType(I.getType());
2993 if (VT.isVector()) {
Reid Spencer9d6565a2007-02-15 02:26:10 +00002994 const VectorType *DestTy = cast<VectorType>(I.getType());
Duncan Sands83ec4b62008-06-06 12:08:01 +00002995 MVT EltVT = TLI.getValueType(DestTy->getElementType());
Chris Lattner0eade312006-03-24 02:22:33 +00002996
Duncan Sands83ec4b62008-06-06 12:08:01 +00002997 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
Chris Lattner0eade312006-03-24 02:22:33 +00002998 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2999 }
3000
3001 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
3002 VTs.push_back(VT);
3003 }
3004 if (HasChain)
3005 VTs.push_back(MVT::Other);
3006
Duncan Sands83ec4b62008-06-06 12:08:01 +00003007 const MVT *VTList = DAG.getNodeValueTypes(VTs);
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00003008
Chris Lattner0eade312006-03-24 02:22:33 +00003009 // Create the node.
Dan Gohman475871a2008-07-27 21:46:04 +00003010 SDValue Result;
Chris Lattner48b61a72006-03-28 00:40:33 +00003011 if (!HasChain)
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00003012 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
3013 &Ops[0], Ops.size());
Chris Lattner48b61a72006-03-28 00:40:33 +00003014 else if (I.getType() != Type::VoidTy)
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00003015 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
3016 &Ops[0], Ops.size());
Chris Lattner48b61a72006-03-28 00:40:33 +00003017 else
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00003018 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
3019 &Ops[0], Ops.size());
Chris Lattner48b61a72006-03-28 00:40:33 +00003020
Chris Lattnere58a7802006-04-02 03:41:14 +00003021 if (HasChain) {
Dan Gohman475871a2008-07-27 21:46:04 +00003022 SDValue Chain = Result.getValue(Result.Val->getNumValues()-1);
Chris Lattnere58a7802006-04-02 03:41:14 +00003023 if (OnlyLoad)
3024 PendingLoads.push_back(Chain);
3025 else
3026 DAG.setRoot(Chain);
3027 }
Chris Lattner0eade312006-03-24 02:22:33 +00003028 if (I.getType() != Type::VoidTy) {
Reid Spencer9d6565a2007-02-15 02:26:10 +00003029 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00003030 MVT VT = TLI.getValueType(PTy);
Dan Gohman7f321562007-06-25 16:23:39 +00003031 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
Chris Lattner0eade312006-03-24 02:22:33 +00003032 }
3033 setValue(&I, Result);
3034 }
3035}
3036
Duncan Sandsb4fd45e2007-07-06 09:10:03 +00003037/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
Duncan Sandscf26d7c2007-07-04 20:52:51 +00003038static GlobalVariable *ExtractTypeInfo (Value *V) {
Anton Korobeynikov0b12ecf2008-05-07 22:54:15 +00003039 V = V->stripPointerCasts();
Duncan Sandsb4fd45e2007-07-06 09:10:03 +00003040 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
Anton Korobeynikov4c71dfe2008-02-20 11:10:28 +00003041 assert ((GV || isa<ConstantPointerNull>(V)) &&
Duncan Sandscf26d7c2007-07-04 20:52:51 +00003042 "TypeInfo must be a global variable or NULL");
3043 return GV;
3044}
3045
Duncan Sandsf4070822007-06-15 19:04:19 +00003046/// addCatchInfo - Extract the personality and type infos from an eh.selector
Duncan Sandscf26d7c2007-07-04 20:52:51 +00003047/// call, and add them to the specified machine basic block.
Duncan Sandsf4070822007-06-15 19:04:19 +00003048static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3049 MachineBasicBlock *MBB) {
3050 // Inform the MachineModuleInfo of the personality for this landing pad.
3051 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3052 assert(CE->getOpcode() == Instruction::BitCast &&
3053 isa<Function>(CE->getOperand(0)) &&
3054 "Personality should be a function");
3055 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3056
3057 // Gather all the type infos for this landing pad and pass them along to
3058 // MachineModuleInfo.
3059 std::vector<GlobalVariable *> TyInfo;
Duncan Sandscf26d7c2007-07-04 20:52:51 +00003060 unsigned N = I.getNumOperands();
3061
3062 for (unsigned i = N - 1; i > 2; --i) {
3063 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3064 unsigned FilterLength = CI->getZExtValue();
Duncan Sands6590b042007-08-27 15:47:50 +00003065 unsigned FirstCatch = i + FilterLength + !FilterLength;
Duncan Sandscf26d7c2007-07-04 20:52:51 +00003066 assert (FirstCatch <= N && "Invalid filter length");
3067
3068 if (FirstCatch < N) {
3069 TyInfo.reserve(N - FirstCatch);
3070 for (unsigned j = FirstCatch; j < N; ++j)
3071 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3072 MMI->addCatchTypeInfo(MBB, TyInfo);
3073 TyInfo.clear();
3074 }
3075
Duncan Sands6590b042007-08-27 15:47:50 +00003076 if (!FilterLength) {
3077 // Cleanup.
3078 MMI->addCleanup(MBB);
3079 } else {
3080 // Filter.
3081 TyInfo.reserve(FilterLength - 1);
3082 for (unsigned j = i + 1; j < FirstCatch; ++j)
3083 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3084 MMI->addFilterTypeInfo(MBB, TyInfo);
3085 TyInfo.clear();
3086 }
Duncan Sandscf26d7c2007-07-04 20:52:51 +00003087
3088 N = i;
3089 }
Duncan Sandsf4070822007-06-15 19:04:19 +00003090 }
Duncan Sandscf26d7c2007-07-04 20:52:51 +00003091
3092 if (N > 3) {
3093 TyInfo.reserve(N - 3);
3094 for (unsigned j = 3; j < N; ++j)
3095 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
Duncan Sandsf4070822007-06-15 19:04:19 +00003096 MMI->addCatchTypeInfo(MBB, TyInfo);
Duncan Sandscf26d7c2007-07-04 20:52:51 +00003097 }
Duncan Sandsf4070822007-06-15 19:04:19 +00003098}
3099
Mon P Wang63307c32008-05-05 19:05:59 +00003100
3101/// Inlined utility function to implement binary input atomic intrinsics for
3102// visitIntrinsicCall: I is a call instruction
3103// Op is the associated NodeType for I
3104const char *
3105SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
Dan Gohman475871a2008-07-27 21:46:04 +00003106 SDValue Root = getRoot();
3107 SDValue L = DAG.getAtomic(Op, Root,
Mon P Wang63307c32008-05-05 19:05:59 +00003108 getValue(I.getOperand(1)),
Dan Gohmanfd4418f2008-06-25 16:07:49 +00003109 getValue(I.getOperand(2)),
Mon P Wang28873102008-06-25 08:15:39 +00003110 I.getOperand(1));
Mon P Wang63307c32008-05-05 19:05:59 +00003111 setValue(&I, L);
3112 DAG.setRoot(L.getValue(1));
3113 return 0;
3114}
3115
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003116/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3117/// we want to emit this as a call to a named external function, return the name
3118/// otherwise lower it and return null.
3119const char *
3120SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3121 switch (Intrinsic) {
Chris Lattner0eade312006-03-24 02:22:33 +00003122 default:
3123 // By default, turn this into a target intrinsic node.
3124 visitTargetIntrinsic(I, Intrinsic);
3125 return 0;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003126 case Intrinsic::vastart: visitVAStart(I); return 0;
3127 case Intrinsic::vaend: visitVAEnd(I); return 0;
3128 case Intrinsic::vacopy: visitVACopy(I); return 0;
Nate Begemanbcc5f362007-01-29 22:58:52 +00003129 case Intrinsic::returnaddress:
3130 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
3131 getValue(I.getOperand(1))));
3132 return 0;
3133 case Intrinsic::frameaddress:
3134 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
3135 getValue(I.getOperand(1))));
3136 return 0;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003137 case Intrinsic::setjmp:
Anton Korobeynikovd27a2582006-12-10 23:12:42 +00003138 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003139 break;
3140 case Intrinsic::longjmp:
Anton Korobeynikovd27a2582006-12-10 23:12:42 +00003141 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003142 break;
Chris Lattner03dd4652006-03-03 00:00:25 +00003143 case Intrinsic::memcpy_i32:
Dan Gohman707e0182008-04-12 04:36:06 +00003144 case Intrinsic::memcpy_i64: {
Dan Gohman475871a2008-07-27 21:46:04 +00003145 SDValue Op1 = getValue(I.getOperand(1));
3146 SDValue Op2 = getValue(I.getOperand(2));
3147 SDValue Op3 = getValue(I.getOperand(3));
Dan Gohman707e0182008-04-12 04:36:06 +00003148 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3149 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3150 I.getOperand(1), 0, I.getOperand(2), 0));
Chris Lattner03dd4652006-03-03 00:00:25 +00003151 return 0;
Dan Gohman707e0182008-04-12 04:36:06 +00003152 }
Chris Lattner03dd4652006-03-03 00:00:25 +00003153 case Intrinsic::memset_i32:
Dan Gohman707e0182008-04-12 04:36:06 +00003154 case Intrinsic::memset_i64: {
Dan Gohman475871a2008-07-27 21:46:04 +00003155 SDValue Op1 = getValue(I.getOperand(1));
3156 SDValue Op2 = getValue(I.getOperand(2));
3157 SDValue Op3 = getValue(I.getOperand(3));
Dan Gohman707e0182008-04-12 04:36:06 +00003158 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3159 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3160 I.getOperand(1), 0));
Chris Lattner03dd4652006-03-03 00:00:25 +00003161 return 0;
Dan Gohman707e0182008-04-12 04:36:06 +00003162 }
Chris Lattner03dd4652006-03-03 00:00:25 +00003163 case Intrinsic::memmove_i32:
Dan Gohman707e0182008-04-12 04:36:06 +00003164 case Intrinsic::memmove_i64: {
Dan Gohman475871a2008-07-27 21:46:04 +00003165 SDValue Op1 = getValue(I.getOperand(1));
3166 SDValue Op2 = getValue(I.getOperand(2));
3167 SDValue Op3 = getValue(I.getOperand(3));
Dan Gohman707e0182008-04-12 04:36:06 +00003168 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3169
3170 // If the source and destination are known to not be aliases, we can
3171 // lower memmove as memcpy.
3172 uint64_t Size = -1ULL;
3173 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3174 Size = C->getValue();
3175 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3176 AliasAnalysis::NoAlias) {
3177 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3178 I.getOperand(1), 0, I.getOperand(2), 0));
3179 return 0;
3180 }
3181
3182 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3183 I.getOperand(1), 0, I.getOperand(2), 0));
Chris Lattner03dd4652006-03-03 00:00:25 +00003184 return 0;
Dan Gohman707e0182008-04-12 04:36:06 +00003185 }
Chris Lattner86cb6432005-12-13 17:40:33 +00003186 case Intrinsic::dbg_stoppoint: {
Jim Laskey44c3b9f2007-01-26 21:22:28 +00003187 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Jim Laskey43970fe2006-03-23 18:06:46 +00003188 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
Jim Laskey44c3b9f2007-01-26 21:22:28 +00003189 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
Jim Laskey44c3b9f2007-01-26 21:22:28 +00003190 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
Jim Laskeyce72b172006-02-11 01:01:30 +00003191 assert(DD && "Not a debug information descriptor");
Dan Gohman7f460202008-06-30 20:59:49 +00003192 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3193 SPI.getLine(),
3194 SPI.getColumn(),
3195 cast<CompileUnitDesc>(DD)));
Chris Lattner86cb6432005-12-13 17:40:33 +00003196 }
Jim Laskey43970fe2006-03-23 18:06:46 +00003197
Chris Lattnerb1a5a5c2005-11-16 07:22:30 +00003198 return 0;
Chris Lattner36ce6912005-11-29 06:21:05 +00003199 }
Jim Laskey43970fe2006-03-23 18:06:46 +00003200 case Intrinsic::dbg_region_start: {
Jim Laskey44c3b9f2007-01-26 21:22:28 +00003201 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Jim Laskey43970fe2006-03-23 18:06:46 +00003202 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
Jim Laskey44c3b9f2007-01-26 21:22:28 +00003203 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
3204 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
Dan Gohman44066042008-07-01 00:05:16 +00003205 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
Jim Laskey43970fe2006-03-23 18:06:46 +00003206 }
3207
Chris Lattnerb1a5a5c2005-11-16 07:22:30 +00003208 return 0;
Jim Laskey43970fe2006-03-23 18:06:46 +00003209 }
3210 case Intrinsic::dbg_region_end: {
Jim Laskey44c3b9f2007-01-26 21:22:28 +00003211 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Jim Laskey43970fe2006-03-23 18:06:46 +00003212 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
Jim Laskey44c3b9f2007-01-26 21:22:28 +00003213 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
3214 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
Dan Gohman44066042008-07-01 00:05:16 +00003215 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
Jim Laskey43970fe2006-03-23 18:06:46 +00003216 }
3217
Chris Lattnerb1a5a5c2005-11-16 07:22:30 +00003218 return 0;
Jim Laskey43970fe2006-03-23 18:06:46 +00003219 }
3220 case Intrinsic::dbg_func_start: {
Jim Laskey44c3b9f2007-01-26 21:22:28 +00003221 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Evan Cheng1b08bbc2008-02-01 09:10:45 +00003222 if (!MMI) return 0;
Jim Laskey43970fe2006-03-23 18:06:46 +00003223 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
Evan Cheng1b08bbc2008-02-01 09:10:45 +00003224 Value *SP = FSI.getSubprogram();
3225 if (SP && MMI->Verify(SP)) {
3226 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3227 // what (most?) gdb expects.
3228 DebugInfoDesc *DD = MMI->getDescFor(SP);
3229 assert(DD && "Not a debug information descriptor");
3230 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
3231 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
Dan Gohman99fe47b2008-06-30 22:21:03 +00003232 unsigned SrcFile = MMI->RecordSource(CompileUnit);
Evan Cheng1b08bbc2008-02-01 09:10:45 +00003233 // Record the source line but does create a label. It will be emitted
3234 // at asm emission time.
3235 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
Jim Laskey43970fe2006-03-23 18:06:46 +00003236 }
3237
Chris Lattnerb1a5a5c2005-11-16 07:22:30 +00003238 return 0;
Jim Laskey43970fe2006-03-23 18:06:46 +00003239 }
3240 case Intrinsic::dbg_declare: {
Jim Laskey44c3b9f2007-01-26 21:22:28 +00003241 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Jim Laskey43970fe2006-03-23 18:06:46 +00003242 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
Evan Chenga844bde2008-02-02 04:07:54 +00003243 Value *Variable = DI.getVariable();
3244 if (MMI && Variable && MMI->Verify(Variable))
3245 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
3246 getValue(DI.getAddress()), getValue(Variable)));
Jim Laskey43970fe2006-03-23 18:06:46 +00003247 return 0;
3248 }
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003249
Jim Laskeyb180aa12007-02-21 22:53:45 +00003250 case Intrinsic::eh_exception: {
Dale Johannesen1532f3d2008-04-02 00:25:04 +00003251 if (!CurMBB->isLandingPad()) {
3252 // FIXME: Mark exception register as live in. Hack for PR1508.
3253 unsigned Reg = TLI.getExceptionAddressRegister();
3254 if (Reg) CurMBB->addLiveIn(Reg);
Jim Laskey735b6f82007-02-22 15:38:06 +00003255 }
Dale Johannesen1532f3d2008-04-02 00:25:04 +00003256 // Insert the EXCEPTIONADDR instruction.
3257 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
Dan Gohman475871a2008-07-27 21:46:04 +00003258 SDValue Ops[1];
Dale Johannesen1532f3d2008-04-02 00:25:04 +00003259 Ops[0] = DAG.getRoot();
Dan Gohman475871a2008-07-27 21:46:04 +00003260 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
Dale Johannesen1532f3d2008-04-02 00:25:04 +00003261 setValue(&I, Op);
3262 DAG.setRoot(Op.getValue(1));
Jim Laskeyb180aa12007-02-21 22:53:45 +00003263 return 0;
3264 }
3265
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +00003266 case Intrinsic::eh_selector_i32:
3267 case Intrinsic::eh_selector_i64: {
Jim Laskeyb180aa12007-02-21 22:53:45 +00003268 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Duncan Sands83ec4b62008-06-06 12:08:01 +00003269 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +00003270 MVT::i32 : MVT::i64);
3271
Dale Johannesen1532f3d2008-04-02 00:25:04 +00003272 if (MMI) {
Duncan Sandsf4070822007-06-15 19:04:19 +00003273 if (CurMBB->isLandingPad())
3274 addCatchInfo(I, MMI, CurMBB);
Evan Chenge47c3332007-06-27 18:45:32 +00003275 else {
Duncan Sandsf4070822007-06-15 19:04:19 +00003276#ifndef NDEBUG
Duncan Sandsf4070822007-06-15 19:04:19 +00003277 FuncInfo.CatchInfoLost.insert(&I);
3278#endif
Duncan Sands90291952007-07-06 09:18:59 +00003279 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3280 unsigned Reg = TLI.getExceptionSelectorRegister();
3281 if (Reg) CurMBB->addLiveIn(Reg);
Evan Chenge47c3332007-06-27 18:45:32 +00003282 }
Jim Laskey735b6f82007-02-22 15:38:06 +00003283
3284 // Insert the EHSELECTION instruction.
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +00003285 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
Dan Gohman475871a2008-07-27 21:46:04 +00003286 SDValue Ops[2];
Jim Laskey735b6f82007-02-22 15:38:06 +00003287 Ops[0] = getValue(I.getOperand(1));
3288 Ops[1] = getRoot();
Dan Gohman475871a2008-07-27 21:46:04 +00003289 SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
Jim Laskey735b6f82007-02-22 15:38:06 +00003290 setValue(&I, Op);
3291 DAG.setRoot(Op.getValue(1));
Jim Laskey7a1de982007-02-24 09:45:44 +00003292 } else {
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +00003293 setValue(&I, DAG.getConstant(0, VT));
Jim Laskey735b6f82007-02-22 15:38:06 +00003294 }
Jim Laskeyb180aa12007-02-21 22:53:45 +00003295
3296 return 0;
3297 }
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +00003298
3299 case Intrinsic::eh_typeid_for_i32:
3300 case Intrinsic::eh_typeid_for_i64: {
Jim Laskeyb180aa12007-02-21 22:53:45 +00003301 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Duncan Sands83ec4b62008-06-06 12:08:01 +00003302 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +00003303 MVT::i32 : MVT::i64);
Jim Laskeyb180aa12007-02-21 22:53:45 +00003304
Jim Laskey735b6f82007-02-22 15:38:06 +00003305 if (MMI) {
3306 // Find the type id for the given typeinfo.
Duncan Sandscf26d7c2007-07-04 20:52:51 +00003307 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
Duncan Sands3b346362007-05-04 17:12:26 +00003308
Jim Laskey735b6f82007-02-22 15:38:06 +00003309 unsigned TypeID = MMI->getTypeIDFor(GV);
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +00003310 setValue(&I, DAG.getConstant(TypeID, VT));
Jim Laskey7a1de982007-02-24 09:45:44 +00003311 } else {
Duncan Sandsf664e412007-07-06 14:46:23 +00003312 // Return something different to eh_selector.
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +00003313 setValue(&I, DAG.getConstant(1, VT));
Jim Laskey735b6f82007-02-22 15:38:06 +00003314 }
Jim Laskeyb180aa12007-02-21 22:53:45 +00003315
3316 return 0;
3317 }
3318
Anton Korobeynikov2365f512007-07-14 14:06:15 +00003319 case Intrinsic::eh_return: {
3320 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3321
Dale Johannesen1532f3d2008-04-02 00:25:04 +00003322 if (MMI) {
Anton Korobeynikov2365f512007-07-14 14:06:15 +00003323 MMI->setCallsEHReturn(true);
3324 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
3325 MVT::Other,
Dan Gohman86e1ebf2008-03-27 19:56:19 +00003326 getControlRoot(),
Anton Korobeynikov2365f512007-07-14 14:06:15 +00003327 getValue(I.getOperand(1)),
3328 getValue(I.getOperand(2))));
3329 } else {
3330 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3331 }
3332
3333 return 0;
3334 }
3335
3336 case Intrinsic::eh_unwind_init: {
3337 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3338 MMI->setCallsUnwindInit(true);
3339 }
3340
3341 return 0;
3342 }
3343
3344 case Intrinsic::eh_dwarf_cfa: {
Duncan Sands83ec4b62008-06-06 12:08:01 +00003345 MVT VT = getValue(I.getOperand(1)).getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +00003346 SDValue CfaArg;
Duncan Sands8e4eb092008-06-08 20:54:56 +00003347 if (VT.bitsGT(TLI.getPointerTy()))
Dale Johannesen1532f3d2008-04-02 00:25:04 +00003348 CfaArg = DAG.getNode(ISD::TRUNCATE,
3349 TLI.getPointerTy(), getValue(I.getOperand(1)));
3350 else
3351 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3352 TLI.getPointerTy(), getValue(I.getOperand(1)));
Anton Korobeynikov2365f512007-07-14 14:06:15 +00003353
Dan Gohman475871a2008-07-27 21:46:04 +00003354 SDValue Offset = DAG.getNode(ISD::ADD,
Dale Johannesen1532f3d2008-04-02 00:25:04 +00003355 TLI.getPointerTy(),
3356 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3357 TLI.getPointerTy()),
3358 CfaArg);
3359 setValue(&I, DAG.getNode(ISD::ADD,
3360 TLI.getPointerTy(),
3361 DAG.getNode(ISD::FRAMEADDR,
3362 TLI.getPointerTy(),
3363 DAG.getConstant(0,
3364 TLI.getPointerTy())),
3365 Offset));
Anton Korobeynikov2365f512007-07-14 14:06:15 +00003366 return 0;
3367 }
3368
Dale Johannesen9ab7fb32007-10-02 17:43:59 +00003369 case Intrinsic::sqrt:
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003370 setValue(&I, DAG.getNode(ISD::FSQRT,
3371 getValue(I.getOperand(1)).getValueType(),
3372 getValue(I.getOperand(1))));
3373 return 0;
Dale Johannesen9ab7fb32007-10-02 17:43:59 +00003374 case Intrinsic::powi:
Chris Lattner6ddf8ed2006-09-09 06:03:30 +00003375 setValue(&I, DAG.getNode(ISD::FPOWI,
3376 getValue(I.getOperand(1)).getValueType(),
3377 getValue(I.getOperand(1)),
3378 getValue(I.getOperand(2))));
3379 return 0;
Dan Gohmanac9385a2007-10-12 00:01:22 +00003380 case Intrinsic::sin:
3381 setValue(&I, DAG.getNode(ISD::FSIN,
3382 getValue(I.getOperand(1)).getValueType(),
3383 getValue(I.getOperand(1))));
3384 return 0;
3385 case Intrinsic::cos:
3386 setValue(&I, DAG.getNode(ISD::FCOS,
3387 getValue(I.getOperand(1)).getValueType(),
3388 getValue(I.getOperand(1))));
3389 return 0;
3390 case Intrinsic::pow:
3391 setValue(&I, DAG.getNode(ISD::FPOW,
3392 getValue(I.getOperand(1)).getValueType(),
3393 getValue(I.getOperand(1)),
3394 getValue(I.getOperand(2))));
3395 return 0;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003396 case Intrinsic::pcmarker: {
Dan Gohman475871a2008-07-27 21:46:04 +00003397 SDValue Tmp = getValue(I.getOperand(1));
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003398 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3399 return 0;
3400 }
Andrew Lenharth8b91c772005-11-11 22:48:54 +00003401 case Intrinsic::readcyclecounter: {
Dan Gohman475871a2008-07-27 21:46:04 +00003402 SDValue Op = getRoot();
3403 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00003404 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3405 &Op, 1);
Andrew Lenharth8b91c772005-11-11 22:48:54 +00003406 setValue(&I, Tmp);
3407 DAG.setRoot(Tmp.getValue(1));
Andrew Lenharth51b8d542005-11-11 16:47:30 +00003408 return 0;
Andrew Lenharth8b91c772005-11-11 22:48:54 +00003409 }
Chris Lattnerc6eb6d72007-04-10 03:20:39 +00003410 case Intrinsic::part_select: {
Reid Spencer3f108cb2007-04-05 01:20:18 +00003411 // Currently not implemented: just abort
Reid Spencerf75b8742007-04-12 02:48:46 +00003412 assert(0 && "part_select intrinsic not implemented");
3413 abort();
3414 }
3415 case Intrinsic::part_set: {
3416 // Currently not implemented: just abort
3417 assert(0 && "part_set intrinsic not implemented");
Reid Spencer3f108cb2007-04-05 01:20:18 +00003418 abort();
Reid Spenceraddd11d2007-04-04 23:48:25 +00003419 }
Reid Spencera4f9c4d2007-04-01 07:34:11 +00003420 case Intrinsic::bswap:
Nate Begemand88fc032006-01-14 03:14:10 +00003421 setValue(&I, DAG.getNode(ISD::BSWAP,
3422 getValue(I.getOperand(1)).getValueType(),
3423 getValue(I.getOperand(1))));
3424 return 0;
Reid Spencera4f9c4d2007-04-01 07:34:11 +00003425 case Intrinsic::cttz: {
Dan Gohman475871a2008-07-27 21:46:04 +00003426 SDValue Arg = getValue(I.getOperand(1));
Duncan Sands83ec4b62008-06-06 12:08:01 +00003427 MVT Ty = Arg.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +00003428 SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg);
Reid Spencera4f9c4d2007-04-01 07:34:11 +00003429 setValue(&I, result);
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003430 return 0;
Reid Spencera4f9c4d2007-04-01 07:34:11 +00003431 }
3432 case Intrinsic::ctlz: {
Dan Gohman475871a2008-07-27 21:46:04 +00003433 SDValue Arg = getValue(I.getOperand(1));
Duncan Sands83ec4b62008-06-06 12:08:01 +00003434 MVT Ty = Arg.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +00003435 SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg);
Reid Spencera4f9c4d2007-04-01 07:34:11 +00003436 setValue(&I, result);
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003437 return 0;
Reid Spencera4f9c4d2007-04-01 07:34:11 +00003438 }
3439 case Intrinsic::ctpop: {
Dan Gohman475871a2008-07-27 21:46:04 +00003440 SDValue Arg = getValue(I.getOperand(1));
Duncan Sands83ec4b62008-06-06 12:08:01 +00003441 MVT Ty = Arg.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +00003442 SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg);
Reid Spencera4f9c4d2007-04-01 07:34:11 +00003443 setValue(&I, result);
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003444 return 0;
Reid Spencera4f9c4d2007-04-01 07:34:11 +00003445 }
Chris Lattner140d53c2006-01-13 02:50:02 +00003446 case Intrinsic::stacksave: {
Dan Gohman475871a2008-07-27 21:46:04 +00003447 SDValue Op = getRoot();
3448 SDValue Tmp = DAG.getNode(ISD::STACKSAVE,
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00003449 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
Chris Lattner140d53c2006-01-13 02:50:02 +00003450 setValue(&I, Tmp);
3451 DAG.setRoot(Tmp.getValue(1));
3452 return 0;
3453 }
Chris Lattner39a17dd2006-01-23 05:22:07 +00003454 case Intrinsic::stackrestore: {
Dan Gohman475871a2008-07-27 21:46:04 +00003455 SDValue Tmp = getValue(I.getOperand(1));
Chris Lattner39a17dd2006-01-23 05:22:07 +00003456 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
Chris Lattner140d53c2006-01-13 02:50:02 +00003457 return 0;
Chris Lattner39a17dd2006-01-23 05:22:07 +00003458 }
Tanya Lattner24e5aad2007-06-15 22:26:58 +00003459 case Intrinsic::var_annotation:
3460 // Discard annotate attributes
3461 return 0;
Duncan Sands36397f52007-07-27 12:58:54 +00003462
Duncan Sands36397f52007-07-27 12:58:54 +00003463 case Intrinsic::init_trampoline: {
Anton Korobeynikov0b12ecf2008-05-07 22:54:15 +00003464 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
Duncan Sands36397f52007-07-27 12:58:54 +00003465
Dan Gohman475871a2008-07-27 21:46:04 +00003466 SDValue Ops[6];
Duncan Sands36397f52007-07-27 12:58:54 +00003467 Ops[0] = getRoot();
3468 Ops[1] = getValue(I.getOperand(1));
3469 Ops[2] = getValue(I.getOperand(2));
3470 Ops[3] = getValue(I.getOperand(3));
3471 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3472 Ops[5] = DAG.getSrcValue(F);
3473
Dan Gohman475871a2008-07-27 21:46:04 +00003474 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE,
Duncan Sandsf7331b32007-09-11 14:10:23 +00003475 DAG.getNodeValueTypes(TLI.getPointerTy(),
3476 MVT::Other), 2,
3477 Ops, 6);
3478
3479 setValue(&I, Tmp);
3480 DAG.setRoot(Tmp.getValue(1));
Duncan Sands36397f52007-07-27 12:58:54 +00003481 return 0;
3482 }
Gordon Henriksence224772008-01-07 01:30:38 +00003483
3484 case Intrinsic::gcroot:
3485 if (GCI) {
3486 Value *Alloca = I.getOperand(1);
3487 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3488
3489 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3490 GCI->addStackRoot(FI->getIndex(), TypeMap);
3491 }
3492 return 0;
3493
3494 case Intrinsic::gcread:
3495 case Intrinsic::gcwrite:
3496 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
3497 return 0;
3498
Anton Korobeynikov917c2a62007-11-15 23:25:33 +00003499 case Intrinsic::flt_rounds: {
Dan Gohman1a024862008-01-31 00:41:03 +00003500 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
Anton Korobeynikov917c2a62007-11-15 23:25:33 +00003501 return 0;
3502 }
Anton Korobeynikov66fac792008-01-15 07:02:33 +00003503
3504 case Intrinsic::trap: {
3505 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3506 return 0;
3507 }
Evan Cheng27b7db52008-03-08 00:58:38 +00003508 case Intrinsic::prefetch: {
Dan Gohman475871a2008-07-27 21:46:04 +00003509 SDValue Ops[4];
Evan Cheng27b7db52008-03-08 00:58:38 +00003510 Ops[0] = getRoot();
3511 Ops[1] = getValue(I.getOperand(1));
3512 Ops[2] = getValue(I.getOperand(2));
3513 Ops[3] = getValue(I.getOperand(3));
3514 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3515 return 0;
3516 }
3517
Andrew Lenharth22c5c1b2008-02-16 01:24:58 +00003518 case Intrinsic::memory_barrier: {
Dan Gohman475871a2008-07-27 21:46:04 +00003519 SDValue Ops[6];
Andrew Lenharth22c5c1b2008-02-16 01:24:58 +00003520 Ops[0] = getRoot();
3521 for (int x = 1; x < 6; ++x)
3522 Ops[x] = getValue(I.getOperand(x));
3523
3524 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3525 return 0;
3526 }
Mon P Wang28873102008-06-25 08:15:39 +00003527 case Intrinsic::atomic_cmp_swap: {
Dan Gohman475871a2008-07-27 21:46:04 +00003528 SDValue Root = getRoot();
3529 SDValue L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root,
Andrew Lenharthab0b9492008-02-21 06:45:13 +00003530 getValue(I.getOperand(1)),
3531 getValue(I.getOperand(2)),
Dan Gohmanfd4418f2008-06-25 16:07:49 +00003532 getValue(I.getOperand(3)),
Mon P Wang28873102008-06-25 08:15:39 +00003533 I.getOperand(1));
Andrew Lenharthab0b9492008-02-21 06:45:13 +00003534 setValue(&I, L);
3535 DAG.setRoot(L.getValue(1));
3536 return 0;
3537 }
Mon P Wang28873102008-06-25 08:15:39 +00003538 case Intrinsic::atomic_load_add:
3539 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
3540 case Intrinsic::atomic_load_sub:
3541 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
Mon P Wang63307c32008-05-05 19:05:59 +00003542 case Intrinsic::atomic_load_and:
3543 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
3544 case Intrinsic::atomic_load_or:
3545 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
3546 case Intrinsic::atomic_load_xor:
3547 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
Andrew Lenharth507a58a2008-06-14 05:48:15 +00003548 case Intrinsic::atomic_load_nand:
3549 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
Mon P Wang63307c32008-05-05 19:05:59 +00003550 case Intrinsic::atomic_load_min:
3551 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
3552 case Intrinsic::atomic_load_max:
3553 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
3554 case Intrinsic::atomic_load_umin:
3555 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
3556 case Intrinsic::atomic_load_umax:
3557 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
3558 case Intrinsic::atomic_swap:
3559 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003560 }
3561}
3562
3563
Dan Gohman475871a2008-07-27 21:46:04 +00003564void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
Jim Laskey1da20a72007-02-23 21:45:01 +00003565 bool IsTailCall,
Anton Korobeynikov070280e2007-05-23 11:08:31 +00003566 MachineBasicBlock *LandingPad) {
Duncan Sands6f74b482007-12-19 09:48:52 +00003567 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
Jim Laskey735b6f82007-02-22 15:38:06 +00003568 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
Anton Korobeynikov070280e2007-05-23 11:08:31 +00003569 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3570 unsigned BeginLabel = 0, EndLabel = 0;
Duncan Sands6f74b482007-12-19 09:48:52 +00003571
Jim Laskey735b6f82007-02-22 15:38:06 +00003572 TargetLowering::ArgListTy Args;
3573 TargetLowering::ArgListEntry Entry;
Duncan Sands6f74b482007-12-19 09:48:52 +00003574 Args.reserve(CS.arg_size());
3575 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3576 i != e; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00003577 SDValue ArgNode = getValue(*i);
Duncan Sands6f74b482007-12-19 09:48:52 +00003578 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
Duncan Sands4fee7032007-05-07 20:49:28 +00003579
Duncan Sands6f74b482007-12-19 09:48:52 +00003580 unsigned attrInd = i - CS.arg_begin() + 1;
3581 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3582 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3583 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3584 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3585 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3586 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
Dale Johannesen08e78b12008-02-22 17:49:45 +00003587 Entry.Alignment = CS.getParamAlignment(attrInd);
Jim Laskey735b6f82007-02-22 15:38:06 +00003588 Args.push_back(Entry);
3589 }
3590
Dale Johannesen1532f3d2008-04-02 00:25:04 +00003591 if (LandingPad && MMI) {
Anton Korobeynikov070280e2007-05-23 11:08:31 +00003592 // Insert a label before the invoke call to mark the try range. This can be
3593 // used to detect deletion of the invoke via the MachineModuleInfo.
3594 BeginLabel = MMI->NextLabelID();
Dale Johannesena4091d32008-04-04 23:48:31 +00003595 // Both PendingLoads and PendingExports must be flushed here;
3596 // this call might not return.
3597 (void)getRoot();
Dan Gohman44066042008-07-01 00:05:16 +00003598 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
Anton Korobeynikov070280e2007-05-23 11:08:31 +00003599 }
Duncan Sands6f74b482007-12-19 09:48:52 +00003600
Dan Gohman475871a2008-07-27 21:46:04 +00003601 std::pair<SDValue,SDValue> Result =
Duncan Sands6f74b482007-12-19 09:48:52 +00003602 TLI.LowerCallTo(getRoot(), CS.getType(),
3603 CS.paramHasAttr(0, ParamAttr::SExt),
Duncan Sands00fee652008-02-14 17:28:50 +00003604 CS.paramHasAttr(0, ParamAttr::ZExt),
Duncan Sands6f74b482007-12-19 09:48:52 +00003605 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
Jim Laskey735b6f82007-02-22 15:38:06 +00003606 Callee, Args, DAG);
Duncan Sands6f74b482007-12-19 09:48:52 +00003607 if (CS.getType() != Type::VoidTy)
3608 setValue(CS.getInstruction(), Result.first);
Jim Laskey735b6f82007-02-22 15:38:06 +00003609 DAG.setRoot(Result.second);
Anton Korobeynikov070280e2007-05-23 11:08:31 +00003610
Dale Johannesen1532f3d2008-04-02 00:25:04 +00003611 if (LandingPad && MMI) {
Anton Korobeynikov070280e2007-05-23 11:08:31 +00003612 // Insert a label at the end of the invoke call to mark the try range. This
3613 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3614 EndLabel = MMI->NextLabelID();
Dan Gohman44066042008-07-01 00:05:16 +00003615 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
Anton Korobeynikov070280e2007-05-23 11:08:31 +00003616
Duncan Sands6f74b482007-12-19 09:48:52 +00003617 // Inform MachineModuleInfo of range.
Anton Korobeynikov070280e2007-05-23 11:08:31 +00003618 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3619 }
Jim Laskey735b6f82007-02-22 15:38:06 +00003620}
3621
3622
Chris Lattner1c08c712005-01-07 07:47:53 +00003623void SelectionDAGLowering::visitCall(CallInst &I) {
Chris Lattner64e14b12005-01-08 22:48:57 +00003624 const char *RenameFn = 0;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003625 if (Function *F = I.getCalledFunction()) {
Chris Lattner87b51bc2007-09-10 21:15:22 +00003626 if (F->isDeclaration()) {
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003627 if (unsigned IID = F->getIntrinsicID()) {
3628 RenameFn = visitIntrinsicCall(I, IID);
3629 if (!RenameFn)
3630 return;
Chris Lattner87b51bc2007-09-10 21:15:22 +00003631 }
3632 }
3633
3634 // Check for well-known libc/libm calls. If the function is internal, it
3635 // can't be a library call.
3636 unsigned NameLen = F->getNameLen();
3637 if (!F->hasInternalLinkage() && NameLen) {
3638 const char *NameStr = F->getNameStart();
3639 if (NameStr[0] == 'c' &&
3640 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3641 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3642 if (I.getNumOperands() == 3 && // Basic sanity checks.
3643 I.getOperand(1)->getType()->isFloatingPoint() &&
3644 I.getType() == I.getOperand(1)->getType() &&
3645 I.getType() == I.getOperand(2)->getType()) {
Dan Gohman475871a2008-07-27 21:46:04 +00003646 SDValue LHS = getValue(I.getOperand(1));
3647 SDValue RHS = getValue(I.getOperand(2));
Chris Lattner87b51bc2007-09-10 21:15:22 +00003648 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3649 LHS, RHS));
3650 return;
3651 }
3652 } else if (NameStr[0] == 'f' &&
3653 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
Dale Johannesen2f429012007-09-26 21:10:55 +00003654 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3655 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
Chris Lattner87b51bc2007-09-10 21:15:22 +00003656 if (I.getNumOperands() == 2 && // Basic sanity checks.
3657 I.getOperand(1)->getType()->isFloatingPoint() &&
3658 I.getType() == I.getOperand(1)->getType()) {
Dan Gohman475871a2008-07-27 21:46:04 +00003659 SDValue Tmp = getValue(I.getOperand(1));
Chris Lattner87b51bc2007-09-10 21:15:22 +00003660 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3661 return;
3662 }
3663 } else if (NameStr[0] == 's' &&
3664 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
Dale Johannesen2f429012007-09-26 21:10:55 +00003665 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3666 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
Chris Lattner87b51bc2007-09-10 21:15:22 +00003667 if (I.getNumOperands() == 2 && // Basic sanity checks.
3668 I.getOperand(1)->getType()->isFloatingPoint() &&
3669 I.getType() == I.getOperand(1)->getType()) {
Dan Gohman475871a2008-07-27 21:46:04 +00003670 SDValue Tmp = getValue(I.getOperand(1));
Chris Lattner87b51bc2007-09-10 21:15:22 +00003671 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3672 return;
3673 }
3674 } else if (NameStr[0] == 'c' &&
3675 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
Dale Johannesen2f429012007-09-26 21:10:55 +00003676 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3677 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
Chris Lattner87b51bc2007-09-10 21:15:22 +00003678 if (I.getNumOperands() == 2 && // Basic sanity checks.
3679 I.getOperand(1)->getType()->isFloatingPoint() &&
3680 I.getType() == I.getOperand(1)->getType()) {
Dan Gohman475871a2008-07-27 21:46:04 +00003681 SDValue Tmp = getValue(I.getOperand(1));
Chris Lattner87b51bc2007-09-10 21:15:22 +00003682 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3683 return;
Chris Lattnerf76e7dc2005-04-30 04:43:14 +00003684 }
Chris Lattner1ca85d52005-05-14 13:56:55 +00003685 }
Chris Lattner87b51bc2007-09-10 21:15:22 +00003686 }
Chris Lattnerce7518c2006-01-26 22:24:51 +00003687 } else if (isa<InlineAsm>(I.getOperand(0))) {
Duncan Sandsfd7b3262007-12-17 18:08:19 +00003688 visitInlineAsm(&I);
Chris Lattnerce7518c2006-01-26 22:24:51 +00003689 return;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003690 }
Misha Brukmanedf128a2005-04-21 22:36:52 +00003691
Dan Gohman475871a2008-07-27 21:46:04 +00003692 SDValue Callee;
Chris Lattner64e14b12005-01-08 22:48:57 +00003693 if (!RenameFn)
3694 Callee = getValue(I.getOperand(0));
3695 else
3696 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
Anton Korobeynikov070280e2007-05-23 11:08:31 +00003697
Duncan Sands6f74b482007-12-19 09:48:52 +00003698 LowerCallTo(&I, Callee, I.isTailCall());
Chris Lattner1c08c712005-01-07 07:47:53 +00003699}
3700
Jim Laskey735b6f82007-02-22 15:38:06 +00003701
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003702/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3703/// this value and returns the result as a ValueVT value. This uses
3704/// Chain/Flag as the input and updates them for the output Chain/Flag.
3705/// If the Flag pointer is NULL, no flag is used.
Dan Gohman475871a2008-07-27 21:46:04 +00003706SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3707 SDValue &Chain,
3708 SDValue *Flag) const {
Dan Gohman23ce5022008-04-25 18:27:55 +00003709 // Assemble the legal parts into the final values.
Dan Gohman475871a2008-07-27 21:46:04 +00003710 SmallVector<SDValue, 4> Values(ValueVTs.size());
3711 SmallVector<SDValue, 8> Parts;
Chris Lattner6833b062008-04-28 07:16:35 +00003712 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
Dan Gohman23ce5022008-04-25 18:27:55 +00003713 // Copy the legal parts from the registers.
Duncan Sands83ec4b62008-06-06 12:08:01 +00003714 MVT ValueVT = ValueVTs[Value];
Dan Gohman23ce5022008-04-25 18:27:55 +00003715 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
Duncan Sands83ec4b62008-06-06 12:08:01 +00003716 MVT RegisterVT = RegVTs[Value];
Dan Gohman23ce5022008-04-25 18:27:55 +00003717
Chris Lattner6833b062008-04-28 07:16:35 +00003718 Parts.resize(NumRegs);
Dan Gohman23ce5022008-04-25 18:27:55 +00003719 for (unsigned i = 0; i != NumRegs; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00003720 SDValue P;
Chris Lattner6833b062008-04-28 07:16:35 +00003721 if (Flag == 0)
3722 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
3723 else {
3724 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
Dan Gohman23ce5022008-04-25 18:27:55 +00003725 *Flag = P.getValue(2);
Chris Lattner6833b062008-04-28 07:16:35 +00003726 }
3727 Chain = P.getValue(1);
Chris Lattneread0d882008-06-17 06:09:18 +00003728
3729 // If the source register was virtual and if we know something about it,
3730 // add an assert node.
3731 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
3732 RegisterVT.isInteger() && !RegisterVT.isVector()) {
3733 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
3734 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
3735 if (FLI.LiveOutRegInfo.size() > SlotNo) {
3736 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
3737
3738 unsigned RegSize = RegisterVT.getSizeInBits();
3739 unsigned NumSignBits = LOI.NumSignBits;
3740 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
3741
3742 // FIXME: We capture more information than the dag can represent. For
3743 // now, just use the tightest assertzext/assertsext possible.
3744 bool isSExt = true;
3745 MVT FromVT(MVT::Other);
3746 if (NumSignBits == RegSize)
3747 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
3748 else if (NumZeroBits >= RegSize-1)
3749 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
3750 else if (NumSignBits > RegSize-8)
3751 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
3752 else if (NumZeroBits >= RegSize-9)
3753 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
3754 else if (NumSignBits > RegSize-16)
3755 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
3756 else if (NumZeroBits >= RegSize-17)
3757 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
3758 else if (NumSignBits > RegSize-32)
3759 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
3760 else if (NumZeroBits >= RegSize-33)
3761 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
3762
3763 if (FromVT != MVT::Other) {
3764 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
3765 RegisterVT, P, DAG.getValueType(FromVT));
3766
3767 }
3768 }
3769 }
3770
Dan Gohman23ce5022008-04-25 18:27:55 +00003771 Parts[Part+i] = P;
3772 }
Chris Lattner5df99b32007-03-25 05:00:54 +00003773
Dan Gohman23ce5022008-04-25 18:27:55 +00003774 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT,
3775 ValueVT);
3776 Part += NumRegs;
3777 }
Duncan Sands4bdcb612008-07-02 17:40:58 +00003778
Duncan Sandsf9516202008-06-30 10:19:09 +00003779 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
3780 &Values[0], ValueVTs.size());
Chris Lattner864635a2006-02-22 22:37:12 +00003781}
3782
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00003783/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3784/// specified value into the registers specified by this object. This uses
3785/// Chain/Flag as the input and updates them for the output Chain/Flag.
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003786/// If the Flag pointer is NULL, no flag is used.
Dan Gohman475871a2008-07-27 21:46:04 +00003787void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
3788 SDValue &Chain, SDValue *Flag) const {
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003789 // Get the list of the values's legal parts.
Dan Gohman23ce5022008-04-25 18:27:55 +00003790 unsigned NumRegs = Regs.size();
Dan Gohman475871a2008-07-27 21:46:04 +00003791 SmallVector<SDValue, 8> Parts(NumRegs);
Chris Lattner6833b062008-04-28 07:16:35 +00003792 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00003793 MVT ValueVT = ValueVTs[Value];
Dan Gohman23ce5022008-04-25 18:27:55 +00003794 unsigned NumParts = TLI->getNumRegisters(ValueVT);
Duncan Sands83ec4b62008-06-06 12:08:01 +00003795 MVT RegisterVT = RegVTs[Value];
Dan Gohman23ce5022008-04-25 18:27:55 +00003796
3797 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
3798 &Parts[Part], NumParts, RegisterVT);
3799 Part += NumParts;
3800 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003801
3802 // Copy the parts into the registers.
Dan Gohman475871a2008-07-27 21:46:04 +00003803 SmallVector<SDValue, 8> Chains(NumRegs);
Dan Gohman23ce5022008-04-25 18:27:55 +00003804 for (unsigned i = 0; i != NumRegs; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00003805 SDValue Part;
Chris Lattner6833b062008-04-28 07:16:35 +00003806 if (Flag == 0)
3807 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3808 else {
3809 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003810 *Flag = Part.getValue(1);
Chris Lattner6833b062008-04-28 07:16:35 +00003811 }
3812 Chains[i] = Part.getValue(0);
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00003813 }
Chris Lattner6833b062008-04-28 07:16:35 +00003814
Evan Cheng33bf38a2008-04-28 22:07:13 +00003815 if (NumRegs == 1 || Flag)
3816 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
3817 // flagged to it. That is the CopyToReg nodes and the user are considered
3818 // a single scheduling unit. If we create a TokenFactor and return it as
3819 // chain, then the TokenFactor is both a predecessor (operand) of the
3820 // user as well as a successor (the TF operands are flagged to the user).
3821 // c1, f1 = CopyToReg
3822 // c2, f2 = CopyToReg
3823 // c3 = TokenFactor c1, c2
3824 // ...
3825 // = op c3, ..., f2
3826 Chain = Chains[NumRegs-1];
Chris Lattner6833b062008-04-28 07:16:35 +00003827 else
3828 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00003829}
Chris Lattner864635a2006-02-22 22:37:12 +00003830
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00003831/// AddInlineAsmOperands - Add this value to the specified inlineasm node
3832/// operand list. This adds the code marker and includes the number of
3833/// values added into it.
3834void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
Dan Gohman475871a2008-07-27 21:46:04 +00003835 std::vector<SDValue> &Ops) const {
Duncan Sands83ec4b62008-06-06 12:08:01 +00003836 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
Chris Lattner4b993b12007-04-09 00:33:58 +00003837 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
Chris Lattner6833b062008-04-28 07:16:35 +00003838 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
3839 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
Duncan Sands83ec4b62008-06-06 12:08:01 +00003840 MVT RegisterVT = RegVTs[Value];
Chris Lattner6833b062008-04-28 07:16:35 +00003841 for (unsigned i = 0; i != NumRegs; ++i)
3842 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
Dan Gohman23ce5022008-04-25 18:27:55 +00003843 }
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00003844}
Chris Lattner864635a2006-02-22 22:37:12 +00003845
3846/// isAllocatableRegister - If the specified register is safe to allocate,
3847/// i.e. it isn't a stack pointer or some other special register, return the
3848/// register class for the register. Otherwise, return null.
3849static const TargetRegisterClass *
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00003850isAllocatableRegister(unsigned Reg, MachineFunction &MF,
Dan Gohman6f0d0242008-02-10 18:45:23 +00003851 const TargetLowering &TLI,
3852 const TargetRegisterInfo *TRI) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00003853 MVT FoundVT = MVT::Other;
Chris Lattnerf8814cf2006-04-02 00:24:45 +00003854 const TargetRegisterClass *FoundRC = 0;
Dan Gohman6f0d0242008-02-10 18:45:23 +00003855 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3856 E = TRI->regclass_end(); RCI != E; ++RCI) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00003857 MVT ThisVT = MVT::Other;
Chris Lattnerf8814cf2006-04-02 00:24:45 +00003858
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00003859 const TargetRegisterClass *RC = *RCI;
3860 // If none of the the value types for this register class are valid, we
3861 // can't use it. For example, 64-bit reg classes on 32-bit targets.
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00003862 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3863 I != E; ++I) {
3864 if (TLI.isTypeLegal(*I)) {
Chris Lattnerf8814cf2006-04-02 00:24:45 +00003865 // If we have already found this register in a different register class,
3866 // choose the one with the largest VT specified. For example, on
3867 // PowerPC, we favor f64 register classes over f32.
Duncan Sands8e4eb092008-06-08 20:54:56 +00003868 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
Chris Lattnerf8814cf2006-04-02 00:24:45 +00003869 ThisVT = *I;
3870 break;
3871 }
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00003872 }
3873 }
3874
Chris Lattnerf8814cf2006-04-02 00:24:45 +00003875 if (ThisVT == MVT::Other) continue;
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00003876
Chris Lattner864635a2006-02-22 22:37:12 +00003877 // NOTE: This isn't ideal. In particular, this might allocate the
3878 // frame pointer in functions that need it (due to them not being taken
3879 // out of allocation, because a variable sized allocation hasn't been seen
3880 // yet). This is a slight code pessimization, but should still work.
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00003881 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3882 E = RC->allocation_order_end(MF); I != E; ++I)
Chris Lattnerf8814cf2006-04-02 00:24:45 +00003883 if (*I == Reg) {
3884 // We found a matching register class. Keep looking at others in case
3885 // we find one with larger registers that this physreg is also in.
3886 FoundRC = RC;
3887 FoundVT = ThisVT;
3888 break;
3889 }
Chris Lattner4e4b5762006-02-01 18:59:47 +00003890 }
Chris Lattnerf8814cf2006-04-02 00:24:45 +00003891 return FoundRC;
Chris Lattner864635a2006-02-22 22:37:12 +00003892}
3893
Chris Lattner4e4b5762006-02-01 18:59:47 +00003894
Chris Lattner0c583402007-04-28 20:49:53 +00003895namespace {
3896/// AsmOperandInfo - This contains information for each constraint that we are
3897/// lowering.
Evan Cheng5c807602008-02-26 02:33:44 +00003898struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
3899 /// CallOperand - If this is the result output operand or a clobber
3900 /// this is null, otherwise it is the incoming operand to the CallInst.
3901 /// This gets modified as the asm is processed.
Dan Gohman475871a2008-07-27 21:46:04 +00003902 SDValue CallOperand;
Evan Cheng5c807602008-02-26 02:33:44 +00003903
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003904 /// AssignedRegs - If this is a register or register class operand, this
3905 /// contains the set of register corresponding to the operand.
3906 RegsForValue AssignedRegs;
3907
Dan Gohman23ce5022008-04-25 18:27:55 +00003908 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
Evan Cheng5c807602008-02-26 02:33:44 +00003909 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
Chris Lattner0c583402007-04-28 20:49:53 +00003910 }
Chris Lattner3ff90dc2007-04-30 17:16:27 +00003911
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003912 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3913 /// busy in OutputRegs/InputRegs.
3914 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3915 std::set<unsigned> &OutputRegs,
Chris Lattner7cbeb242008-02-21 04:55:52 +00003916 std::set<unsigned> &InputRegs,
3917 const TargetRegisterInfo &TRI) const {
3918 if (isOutReg) {
3919 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3920 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3921 }
3922 if (isInReg) {
3923 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3924 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3925 }
3926 }
3927
3928private:
3929 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3930 /// specified set.
3931 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3932 const TargetRegisterInfo &TRI) {
3933 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3934 Regs.insert(Reg);
3935 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3936 for (; *Aliases; ++Aliases)
3937 Regs.insert(*Aliases);
3938 }
Chris Lattner0c583402007-04-28 20:49:53 +00003939};
3940} // end anon namespace.
Chris Lattner864635a2006-02-22 22:37:12 +00003941
Chris Lattner3ff90dc2007-04-30 17:16:27 +00003942
Chris Lattner0fe71e92008-02-21 19:43:13 +00003943/// GetRegistersForValue - Assign registers (virtual or physical) for the
3944/// specified operand. We prefer to assign virtual registers, to allow the
3945/// register allocator handle the assignment process. However, if the asm uses
3946/// features that we can't model on machineinstrs, we have SDISel do the
3947/// allocation. This produces generally horrible, but correct, code.
3948///
3949/// OpInfo describes the operand.
3950/// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3951/// or any explicitly clobbered registers.
3952/// Input and OutputRegs are the set of already allocated physical registers.
3953///
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003954void SelectionDAGLowering::
Evan Cheng5c807602008-02-26 02:33:44 +00003955GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
Chris Lattnerbf996f12007-04-30 17:29:31 +00003956 std::set<unsigned> &OutputRegs,
3957 std::set<unsigned> &InputRegs) {
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003958 // Compute whether this value requires an input register, an output register,
3959 // or both.
3960 bool isOutReg = false;
3961 bool isInReg = false;
3962 switch (OpInfo.Type) {
3963 case InlineAsm::isOutput:
3964 isOutReg = true;
3965
3966 // If this is an early-clobber output, or if there is an input
3967 // constraint that matches this, we need to reserve the input register
3968 // so no other inputs allocate to it.
3969 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3970 break;
3971 case InlineAsm::isInput:
3972 isInReg = true;
3973 isOutReg = false;
3974 break;
3975 case InlineAsm::isClobber:
3976 isOutReg = true;
3977 isInReg = true;
3978 break;
3979 }
3980
3981
3982 MachineFunction &MF = DAG.getMachineFunction();
Chris Lattnerb606dba2008-04-28 06:44:42 +00003983 SmallVector<unsigned, 4> Regs;
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003984
3985 // If this is a constraint for a single physreg, or a constraint for a
3986 // register class, find it.
3987 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3988 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3989 OpInfo.ConstraintVT);
Chris Lattnerbf996f12007-04-30 17:29:31 +00003990
3991 unsigned NumRegs = 1;
3992 if (OpInfo.ConstraintVT != MVT::Other)
Dan Gohmanb9f10192007-06-21 14:42:22 +00003993 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
Duncan Sands83ec4b62008-06-06 12:08:01 +00003994 MVT RegVT;
3995 MVT ValueVT = OpInfo.ConstraintVT;
Chris Lattnerbf996f12007-04-30 17:29:31 +00003996
Chris Lattnerbf996f12007-04-30 17:29:31 +00003997
3998 // If this is a constraint for a specific physical register, like {r17},
3999 // assign it now.
4000 if (PhysReg.first) {
4001 if (OpInfo.ConstraintVT == MVT::Other)
4002 ValueVT = *PhysReg.second->vt_begin();
4003
4004 // Get the actual register value type. This is important, because the user
4005 // may have asked for (e.g.) the AX register in i32 type. We need to
4006 // remember that AX is actually i16 to get the right extension.
4007 RegVT = *PhysReg.second->vt_begin();
4008
4009 // This is a explicit reference to a physical register.
4010 Regs.push_back(PhysReg.first);
4011
4012 // If this is an expanded reference, add the rest of the regs to Regs.
4013 if (NumRegs != 1) {
4014 TargetRegisterClass::iterator I = PhysReg.second->begin();
Chris Lattnerbf996f12007-04-30 17:29:31 +00004015 for (; *I != PhysReg.first; ++I)
Evan Cheng50871242008-05-14 20:07:51 +00004016 assert(I != PhysReg.second->end() && "Didn't find reg!");
Chris Lattnerbf996f12007-04-30 17:29:31 +00004017
4018 // Already added the first reg.
4019 --NumRegs; ++I;
4020 for (; NumRegs; --NumRegs, ++I) {
Evan Cheng50871242008-05-14 20:07:51 +00004021 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
Chris Lattnerbf996f12007-04-30 17:29:31 +00004022 Regs.push_back(*I);
4023 }
4024 }
Dan Gohman23ce5022008-04-25 18:27:55 +00004025 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
Chris Lattner7cbeb242008-02-21 04:55:52 +00004026 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4027 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004028 return;
Chris Lattnerbf996f12007-04-30 17:29:31 +00004029 }
4030
4031 // Otherwise, if this was a reference to an LLVM register class, create vregs
4032 // for this reference.
4033 std::vector<unsigned> RegClassRegs;
Chris Lattnerc2c28fc2007-06-15 19:11:01 +00004034 const TargetRegisterClass *RC = PhysReg.second;
4035 if (RC) {
Chris Lattnerbf996f12007-04-30 17:29:31 +00004036 // If this is an early clobber or tied register, our regalloc doesn't know
4037 // how to maintain the constraint. If it isn't, go ahead and create vreg
4038 // and let the regalloc do the right thing.
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004039 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
4040 // If there is some other early clobber and this is an input register,
4041 // then we are forced to pre-allocate the input reg so it doesn't
4042 // conflict with the earlyclobber.
4043 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
Chris Lattnerbf996f12007-04-30 17:29:31 +00004044 RegVT = *PhysReg.second->vt_begin();
4045
4046 if (OpInfo.ConstraintVT == MVT::Other)
4047 ValueVT = RegVT;
4048
4049 // Create the appropriate number of virtual registers.
Chris Lattner84bc5422007-12-31 04:13:23 +00004050 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Chris Lattnerbf996f12007-04-30 17:29:31 +00004051 for (; NumRegs; --NumRegs)
Chris Lattner84bc5422007-12-31 04:13:23 +00004052 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
Chris Lattnerbf996f12007-04-30 17:29:31 +00004053
Dan Gohman23ce5022008-04-25 18:27:55 +00004054 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004055 return;
Chris Lattnerbf996f12007-04-30 17:29:31 +00004056 }
4057
4058 // Otherwise, we can't allocate it. Let the code below figure out how to
4059 // maintain these constraints.
4060 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4061
4062 } else {
4063 // This is a reference to a register class that doesn't directly correspond
4064 // to an LLVM register class. Allocate NumRegs consecutive, available,
4065 // registers from the class.
4066 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4067 OpInfo.ConstraintVT);
4068 }
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004069
Dan Gohman6f0d0242008-02-10 18:45:23 +00004070 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
Chris Lattnerbf996f12007-04-30 17:29:31 +00004071 unsigned NumAllocated = 0;
4072 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4073 unsigned Reg = RegClassRegs[i];
4074 // See if this register is available.
4075 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4076 (isInReg && InputRegs.count(Reg))) { // Already used.
4077 // Make sure we find consecutive registers.
4078 NumAllocated = 0;
4079 continue;
4080 }
4081
4082 // Check to see if this register is allocatable (i.e. don't give out the
4083 // stack pointer).
Chris Lattnerc2c28fc2007-06-15 19:11:01 +00004084 if (RC == 0) {
Dan Gohman6f0d0242008-02-10 18:45:23 +00004085 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
Chris Lattnerc2c28fc2007-06-15 19:11:01 +00004086 if (!RC) { // Couldn't allocate this register.
4087 // Reset NumAllocated to make sure we return consecutive registers.
4088 NumAllocated = 0;
4089 continue;
4090 }
Chris Lattnerbf996f12007-04-30 17:29:31 +00004091 }
4092
4093 // Okay, this register is good, we can use it.
4094 ++NumAllocated;
4095
4096 // If we allocated enough consecutive registers, succeed.
4097 if (NumAllocated == NumRegs) {
4098 unsigned RegStart = (i-NumAllocated)+1;
4099 unsigned RegEnd = i+1;
4100 // Mark all of the allocated registers used.
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004101 for (unsigned i = RegStart; i != RegEnd; ++i)
4102 Regs.push_back(RegClassRegs[i]);
Chris Lattnerbf996f12007-04-30 17:29:31 +00004103
Dan Gohman23ce5022008-04-25 18:27:55 +00004104 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004105 OpInfo.ConstraintVT);
Chris Lattner7cbeb242008-02-21 04:55:52 +00004106 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004107 return;
Chris Lattnerbf996f12007-04-30 17:29:31 +00004108 }
4109 }
4110
4111 // Otherwise, we couldn't allocate enough registers for this.
Chris Lattnerbf996f12007-04-30 17:29:31 +00004112}
4113
4114
Chris Lattnerce7518c2006-01-26 22:24:51 +00004115/// visitInlineAsm - Handle a call to an InlineAsm object.
4116///
Duncan Sandsfd7b3262007-12-17 18:08:19 +00004117void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4118 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
Chris Lattnerce7518c2006-01-26 22:24:51 +00004119
Chris Lattner0c583402007-04-28 20:49:53 +00004120 /// ConstraintOperands - Information about all of the constraints.
Evan Cheng5c807602008-02-26 02:33:44 +00004121 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
Chris Lattnerce7518c2006-01-26 22:24:51 +00004122
Dan Gohman475871a2008-07-27 21:46:04 +00004123 SDValue Chain = getRoot();
4124 SDValue Flag;
Chris Lattnerce7518c2006-01-26 22:24:51 +00004125
Chris Lattner4e4b5762006-02-01 18:59:47 +00004126 std::set<unsigned> OutputRegs, InputRegs;
Chris Lattner1efa40f2006-02-22 00:56:39 +00004127
Chris Lattner0c583402007-04-28 20:49:53 +00004128 // Do a prepass over the constraints, canonicalizing them, and building up the
4129 // ConstraintOperands list.
4130 std::vector<InlineAsm::ConstraintInfo>
4131 ConstraintInfos = IA->ParseConstraints();
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004132
4133 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
4134 // constraint. If so, we can't let the register allocator allocate any input
4135 // registers, because it will not know to avoid the earlyclobbered output reg.
4136 bool SawEarlyClobber = false;
4137
Duncan Sandsfd7b3262007-12-17 18:08:19 +00004138 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
Chris Lattneracf8b012008-04-27 23:44:28 +00004139 unsigned ResNo = 0; // ResNo - The result number of the next output.
Chris Lattner0c583402007-04-28 20:49:53 +00004140 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
Evan Cheng5c807602008-02-26 02:33:44 +00004141 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4142 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
Chris Lattner0c583402007-04-28 20:49:53 +00004143
Duncan Sands83ec4b62008-06-06 12:08:01 +00004144 MVT OpVT = MVT::Other;
Chris Lattner0c583402007-04-28 20:49:53 +00004145
4146 // Compute the value type for each operand.
4147 switch (OpInfo.Type) {
Chris Lattner1efa40f2006-02-22 00:56:39 +00004148 case InlineAsm::isOutput:
Chris Lattneracf8b012008-04-27 23:44:28 +00004149 // Indirect outputs just consume an argument.
4150 if (OpInfo.isIndirect) {
Duncan Sandsfd7b3262007-12-17 18:08:19 +00004151 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
Chris Lattneracf8b012008-04-27 23:44:28 +00004152 break;
Chris Lattner1efa40f2006-02-22 00:56:39 +00004153 }
Chris Lattneracf8b012008-04-27 23:44:28 +00004154 // The return value of the call is this value. As such, there is no
4155 // corresponding argument.
4156 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4157 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4158 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4159 } else {
4160 assert(ResNo == 0 && "Asm only has one result!");
4161 OpVT = TLI.getValueType(CS.getType());
4162 }
4163 ++ResNo;
Chris Lattner1efa40f2006-02-22 00:56:39 +00004164 break;
4165 case InlineAsm::isInput:
Duncan Sandsfd7b3262007-12-17 18:08:19 +00004166 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
Chris Lattner1efa40f2006-02-22 00:56:39 +00004167 break;
4168 case InlineAsm::isClobber:
Chris Lattner0c583402007-04-28 20:49:53 +00004169 // Nothing to do.
Chris Lattner1efa40f2006-02-22 00:56:39 +00004170 break;
4171 }
Chris Lattner1efa40f2006-02-22 00:56:39 +00004172
Chris Lattner0c583402007-04-28 20:49:53 +00004173 // If this is an input or an indirect output, process the call argument.
Dale Johanneseneb57ea72007-11-05 21:20:28 +00004174 // BasicBlocks are labels, currently appearing only in asm's.
Chris Lattner0c583402007-04-28 20:49:53 +00004175 if (OpInfo.CallOperandVal) {
Chris Lattner507ffd22008-04-27 00:16:18 +00004176 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal))
4177 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
Dale Johanneseneb57ea72007-11-05 21:20:28 +00004178 else {
4179 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
4180 const Type *OpTy = OpInfo.CallOperandVal->getType();
4181 // If this is an indirect operand, the operand is a pointer to the
4182 // accessed type.
4183 if (OpInfo.isIndirect)
4184 OpTy = cast<PointerType>(OpTy)->getElementType();
4185
Dan Gohman4fa2a3f2008-05-23 00:34:04 +00004186 // If OpTy is not a single value, it may be a struct/union that we
Dale Johanneseneb57ea72007-11-05 21:20:28 +00004187 // can tile with integers.
Dan Gohman4fa2a3f2008-05-23 00:34:04 +00004188 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
Dale Johanneseneb57ea72007-11-05 21:20:28 +00004189 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4190 switch (BitSize) {
4191 default: break;
4192 case 1:
4193 case 8:
4194 case 16:
4195 case 32:
4196 case 64:
4197 OpTy = IntegerType::get(BitSize);
4198 break;
4199 }
Chris Lattner6995cf62007-04-29 18:58:03 +00004200 }
Dale Johanneseneb57ea72007-11-05 21:20:28 +00004201
4202 OpVT = TLI.getValueType(OpTy, true);
Chris Lattner0c583402007-04-28 20:49:53 +00004203 }
4204 }
4205
4206 OpInfo.ConstraintVT = OpVT;
Chris Lattner2a600be2007-04-28 21:01:43 +00004207
Chris Lattner3ff90dc2007-04-30 17:16:27 +00004208 // Compute the constraint code and ConstraintType to use.
Chris Lattner5a096902008-04-27 00:37:18 +00004209 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
Chris Lattner0c583402007-04-28 20:49:53 +00004210
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004211 // Keep track of whether we see an earlyclobber.
4212 SawEarlyClobber |= OpInfo.isEarlyClobber;
Chris Lattner09e4b7e2007-04-28 21:12:06 +00004213
Chris Lattner0fe71e92008-02-21 19:43:13 +00004214 // If we see a clobber of a register, it is an early clobber.
Chris Lattner69e6a8d2008-02-21 20:54:31 +00004215 if (!SawEarlyClobber &&
4216 OpInfo.Type == InlineAsm::isClobber &&
4217 OpInfo.ConstraintType == TargetLowering::C_Register) {
4218 // Note that we want to ignore things that we don't trick here, like
4219 // dirflag, fpsr, flags, etc.
4220 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4221 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4222 OpInfo.ConstraintVT);
4223 if (PhysReg.first || PhysReg.second) {
4224 // This is a register we know of.
4225 SawEarlyClobber = true;
4226 }
4227 }
Chris Lattner0fe71e92008-02-21 19:43:13 +00004228
Chris Lattner09e4b7e2007-04-28 21:12:06 +00004229 // If this is a memory input, and if the operand is not indirect, do what we
4230 // need to to provide an address for the memory input.
4231 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
4232 !OpInfo.isIndirect) {
4233 assert(OpInfo.Type == InlineAsm::isInput &&
4234 "Can only indirectify direct input operands!");
4235
4236 // Memory operands really want the address of the value. If we don't have
4237 // an indirect input, put it in the constpool if we can, otherwise spill
4238 // it to a stack slot.
4239
4240 // If the operand is a float, integer, or vector constant, spill to a
4241 // constant pool entry to get its address.
4242 Value *OpVal = OpInfo.CallOperandVal;
4243 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
4244 isa<ConstantVector>(OpVal)) {
4245 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
4246 TLI.getPointerTy());
4247 } else {
4248 // Otherwise, create a stack slot and emit a store to it before the
4249 // asm.
4250 const Type *Ty = OpVal->getType();
Duncan Sands514ab342007-11-01 20:53:16 +00004251 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
Chris Lattner09e4b7e2007-04-28 21:12:06 +00004252 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
4253 MachineFunction &MF = DAG.getMachineFunction();
4254 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
Dan Gohman475871a2008-07-27 21:46:04 +00004255 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
Chris Lattner09e4b7e2007-04-28 21:12:06 +00004256 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
4257 OpInfo.CallOperand = StackSlot;
4258 }
4259
4260 // There is no longer a Value* corresponding to this operand.
4261 OpInfo.CallOperandVal = 0;
4262 // It is now an indirect operand.
4263 OpInfo.isIndirect = true;
4264 }
4265
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004266 // If this constraint is for a specific register, allocate it before
4267 // anything else.
4268 if (OpInfo.ConstraintType == TargetLowering::C_Register)
4269 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
Chris Lattner0c583402007-04-28 20:49:53 +00004270 }
Chris Lattner0c583402007-04-28 20:49:53 +00004271 ConstraintInfos.clear();
4272
4273
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004274 // Second pass - Loop over all of the operands, assigning virtual or physregs
4275 // to registerclass operands.
4276 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
Evan Cheng5c807602008-02-26 02:33:44 +00004277 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004278
4279 // C_Register operands have already been allocated, Other/Memory don't need
4280 // to be.
4281 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
4282 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4283 }
4284
Chris Lattner0c583402007-04-28 20:49:53 +00004285 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
Dan Gohman475871a2008-07-27 21:46:04 +00004286 std::vector<SDValue> AsmNodeOperands;
4287 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
Chris Lattner0c583402007-04-28 20:49:53 +00004288 AsmNodeOperands.push_back(
4289 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4290
Chris Lattner2cc2f662006-02-01 01:28:23 +00004291
Chris Lattner0f0b7d42006-02-21 23:12:12 +00004292 // Loop over all of the inputs, copying the operand values into the
4293 // appropriate registers and processing the output regs.
Chris Lattner864635a2006-02-22 22:37:12 +00004294 RegsForValue RetValRegs;
Chris Lattner41f62592008-04-29 04:29:54 +00004295
Chris Lattner0c583402007-04-28 20:49:53 +00004296 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
4297 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
4298
4299 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
Evan Cheng5c807602008-02-26 02:33:44 +00004300 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
Chris Lattner1efa40f2006-02-22 00:56:39 +00004301
Chris Lattner0c583402007-04-28 20:49:53 +00004302 switch (OpInfo.Type) {
Chris Lattner2cc2f662006-02-01 01:28:23 +00004303 case InlineAsm::isOutput: {
Chris Lattnerc83994e2007-04-28 21:03:16 +00004304 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
4305 OpInfo.ConstraintType != TargetLowering::C_Register) {
Chris Lattnerf2f3cd52007-04-28 06:08:13 +00004306 // Memory output, or 'other' output (e.g. 'X' constraint).
Chris Lattner09e4b7e2007-04-28 21:12:06 +00004307 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
Chris Lattner22873462006-02-27 23:45:39 +00004308
Chris Lattner22873462006-02-27 23:45:39 +00004309 // Add information to the INLINEASM node to know about this output.
4310 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
Chris Lattnerc90233b2007-05-15 01:33:58 +00004311 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4312 TLI.getPointerTy()));
Chris Lattner09e4b7e2007-04-28 21:12:06 +00004313 AsmNodeOperands.push_back(OpInfo.CallOperand);
Chris Lattner22873462006-02-27 23:45:39 +00004314 break;
4315 }
4316
Chris Lattner2a600be2007-04-28 21:01:43 +00004317 // Otherwise, this is a register or register class output.
Chris Lattner22873462006-02-27 23:45:39 +00004318
Chris Lattner864635a2006-02-22 22:37:12 +00004319 // Copy the output from the appropriate register. Find a register that
Chris Lattner1efa40f2006-02-22 00:56:39 +00004320 // we can use.
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004321 if (OpInfo.AssignedRegs.Regs.empty()) {
Duncan Sandsa47c6c32008-06-17 03:24:13 +00004322 cerr << "Couldn't allocate output reg for constraint '"
Chris Lattner0c583402007-04-28 20:49:53 +00004323 << OpInfo.ConstraintCode << "'!\n";
Chris Lattnerd03f1582006-10-31 07:33:13 +00004324 exit(1);
4325 }
Chris Lattner1efa40f2006-02-22 00:56:39 +00004326
Chris Lattner41f62592008-04-29 04:29:54 +00004327 // If this is an indirect operand, store through the pointer after the
4328 // asm.
4329 if (OpInfo.isIndirect) {
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004330 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
Chris Lattner0c583402007-04-28 20:49:53 +00004331 OpInfo.CallOperandVal));
Chris Lattner41f62592008-04-29 04:29:54 +00004332 } else {
4333 // This is the result value of the call.
4334 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4335 // Concatenate this output onto the outputs list.
4336 RetValRegs.append(OpInfo.AssignedRegs);
Chris Lattner2cc2f662006-02-01 01:28:23 +00004337 }
Chris Lattner6656dd12006-01-31 02:03:41 +00004338
4339 // Add information to the INLINEASM node to know that this register is
4340 // set.
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004341 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
4342 AsmNodeOperands);
Chris Lattner6656dd12006-01-31 02:03:41 +00004343 break;
4344 }
4345 case InlineAsm::isInput: {
Dan Gohman475871a2008-07-27 21:46:04 +00004346 SDValue InOperandVal = OpInfo.CallOperand;
Chris Lattner3d81fee2006-02-04 02:16:44 +00004347
Chris Lattner0c583402007-04-28 20:49:53 +00004348 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
Chris Lattner2223aea2006-02-02 00:25:23 +00004349 // If this is required to match an output register we have already set,
4350 // just use its register.
Chris Lattner0c583402007-04-28 20:49:53 +00004351 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
Chris Lattner3d81fee2006-02-04 02:16:44 +00004352
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00004353 // Scan until we find the definition we already emitted of this operand.
4354 // When we find it, create a RegsForValue operand.
4355 unsigned CurOp = 2; // The first operand.
4356 for (; OperandNo; --OperandNo) {
4357 // Advance to the next operand.
4358 unsigned NumOps =
4359 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
Chris Lattnera15cf702006-07-20 19:02:21 +00004360 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4361 (NumOps & 7) == 4 /*MEM*/) &&
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00004362 "Skipped past definitions?");
4363 CurOp += (NumOps>>3)+1;
4364 }
4365
4366 unsigned NumOps =
4367 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
Chris Lattner527fae12007-02-01 01:21:12 +00004368 if ((NumOps & 7) == 2 /*REGDEF*/) {
4369 // Add NumOps>>3 registers to MatchedRegs.
4370 RegsForValue MatchedRegs;
Dan Gohman23ce5022008-04-25 18:27:55 +00004371 MatchedRegs.TLI = &TLI;
Dan Gohman1fa850b2008-05-02 00:03:54 +00004372 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
4373 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
Chris Lattner527fae12007-02-01 01:21:12 +00004374 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4375 unsigned Reg =
4376 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4377 MatchedRegs.Regs.push_back(Reg);
4378 }
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00004379
Chris Lattner527fae12007-02-01 01:21:12 +00004380 // Use the produced MatchedRegs object to
Dan Gohmanb6f5b002007-06-28 23:29:44 +00004381 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
Chris Lattner527fae12007-02-01 01:21:12 +00004382 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4383 break;
4384 } else {
4385 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
Chris Lattnerf9853bc2008-02-21 05:27:19 +00004386 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4387 // Add information to the INLINEASM node to know about this input.
4388 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4389 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4390 TLI.getPointerTy()));
4391 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4392 break;
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00004393 }
Chris Lattner2223aea2006-02-02 00:25:23 +00004394 }
Chris Lattner87bc3bd2006-02-24 01:11:24 +00004395
Chris Lattner2a600be2007-04-28 21:01:43 +00004396 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
Chris Lattner0c583402007-04-28 20:49:53 +00004397 assert(!OpInfo.isIndirect &&
Chris Lattner44b2c502007-04-28 06:42:38 +00004398 "Don't know how to handle indirect other inputs yet!");
4399
Dan Gohman475871a2008-07-27 21:46:04 +00004400 std::vector<SDValue> Ops;
Chris Lattner48884cd2007-08-25 00:47:38 +00004401 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4402 Ops, DAG);
4403 if (Ops.empty()) {
Bill Wendling832171c2006-12-07 20:04:42 +00004404 cerr << "Invalid operand for inline asm constraint '"
Chris Lattner0c583402007-04-28 20:49:53 +00004405 << OpInfo.ConstraintCode << "'!\n";
Chris Lattner53069fb2006-10-31 19:41:18 +00004406 exit(1);
4407 }
Chris Lattner87bc3bd2006-02-24 01:11:24 +00004408
4409 // Add information to the INLINEASM node to know about this input.
Chris Lattner48884cd2007-08-25 00:47:38 +00004410 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
Chris Lattnerc90233b2007-05-15 01:33:58 +00004411 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4412 TLI.getPointerTy()));
Chris Lattner48884cd2007-08-25 00:47:38 +00004413 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
Chris Lattner87bc3bd2006-02-24 01:11:24 +00004414 break;
Chris Lattner2a600be2007-04-28 21:01:43 +00004415 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
Chris Lattner09e4b7e2007-04-28 21:12:06 +00004416 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
Chris Lattner44b2c502007-04-28 06:42:38 +00004417 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4418 "Memory operands expect pointer values");
4419
Chris Lattner87bc3bd2006-02-24 01:11:24 +00004420 // Add information to the INLINEASM node to know about this input.
4421 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
Chris Lattnerc90233b2007-05-15 01:33:58 +00004422 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4423 TLI.getPointerTy()));
Chris Lattner87bc3bd2006-02-24 01:11:24 +00004424 AsmNodeOperands.push_back(InOperandVal);
4425 break;
4426 }
4427
Chris Lattner2a600be2007-04-28 21:01:43 +00004428 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4429 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4430 "Unknown constraint type!");
Chris Lattner0c583402007-04-28 20:49:53 +00004431 assert(!OpInfo.isIndirect &&
Chris Lattner44b2c502007-04-28 06:42:38 +00004432 "Don't know how to handle indirect register inputs yet!");
Chris Lattner87bc3bd2006-02-24 01:11:24 +00004433
4434 // Copy the input into the appropriate registers.
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004435 assert(!OpInfo.AssignedRegs.Regs.empty() &&
4436 "Couldn't allocate input reg!");
Chris Lattner87bc3bd2006-02-24 01:11:24 +00004437
Dan Gohmanb6f5b002007-06-28 23:29:44 +00004438 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
Chris Lattner87bc3bd2006-02-24 01:11:24 +00004439
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004440 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
4441 AsmNodeOperands);
Chris Lattner6656dd12006-01-31 02:03:41 +00004442 break;
4443 }
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00004444 case InlineAsm::isClobber: {
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00004445 // Add the clobbered value to the operand list, so that the register
4446 // allocator is aware that the physreg got clobbered.
Chris Lattnere7cf56a2007-04-30 21:11:17 +00004447 if (!OpInfo.AssignedRegs.Regs.empty())
4448 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
4449 AsmNodeOperands);
Chris Lattner6656dd12006-01-31 02:03:41 +00004450 break;
4451 }
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00004452 }
Chris Lattner6656dd12006-01-31 02:03:41 +00004453 }
Chris Lattnerce7518c2006-01-26 22:24:51 +00004454
4455 // Finish up input operands.
4456 AsmNodeOperands[0] = Chain;
4457 if (Flag.Val) AsmNodeOperands.push_back(Flag);
4458
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00004459 Chain = DAG.getNode(ISD::INLINEASM,
4460 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
Chris Lattnerbd564bf2006-08-08 02:23:42 +00004461 &AsmNodeOperands[0], AsmNodeOperands.size());
Chris Lattnerce7518c2006-01-26 22:24:51 +00004462 Flag = Chain.getValue(1);
4463
Chris Lattner6656dd12006-01-31 02:03:41 +00004464 // If this asm returns a register value, copy the result from that register
4465 // and set it as the value of the call.
Chris Lattner3a508c92007-04-12 06:00:20 +00004466 if (!RetValRegs.Regs.empty()) {
Dan Gohman475871a2008-07-27 21:46:04 +00004467 SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
Chris Lattner3fb29682008-04-29 04:48:56 +00004468
4469 // If any of the results of the inline asm is a vector, it may have the
4470 // wrong width/num elts. This can happen for register classes that can
4471 // contain multiple different value types. The preg or vreg allocated may
4472 // not have the same VT as was expected. Convert it to the right type with
Dan Gohman7f321562007-06-25 16:23:39 +00004473 // bit_convert.
Chris Lattner3fb29682008-04-29 04:48:56 +00004474 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
4475 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00004476 if (Val.Val->getValueType(i).isVector())
Chris Lattner3fb29682008-04-29 04:48:56 +00004477 Val = DAG.getNode(ISD::BIT_CONVERT,
4478 TLI.getValueType(ResSTy->getElementType(i)), Val);
4479 }
4480 } else {
Duncan Sands83ec4b62008-06-06 12:08:01 +00004481 if (Val.getValueType().isVector())
Chris Lattner3fb29682008-04-29 04:48:56 +00004482 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
4483 Val);
Chris Lattner3a508c92007-04-12 06:00:20 +00004484 }
Chris Lattner3fb29682008-04-29 04:48:56 +00004485
Duncan Sandsfd7b3262007-12-17 18:08:19 +00004486 setValue(CS.getInstruction(), Val);
Chris Lattner3a508c92007-04-12 06:00:20 +00004487 }
Chris Lattnerce7518c2006-01-26 22:24:51 +00004488
Dan Gohman475871a2008-07-27 21:46:04 +00004489 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
Chris Lattner6656dd12006-01-31 02:03:41 +00004490
4491 // Process indirect outputs, first output all of the flagged copies out of
4492 // physregs.
4493 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
Chris Lattner864635a2006-02-22 22:37:12 +00004494 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
Chris Lattner6656dd12006-01-31 02:03:41 +00004495 Value *Ptr = IndirectStoresToEmit[i].second;
Dan Gohman475871a2008-07-27 21:46:04 +00004496 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
Chris Lattner864635a2006-02-22 22:37:12 +00004497 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
Chris Lattner6656dd12006-01-31 02:03:41 +00004498 }
4499
4500 // Emit the non-flagged stores from the physregs.
Dan Gohman475871a2008-07-27 21:46:04 +00004501 SmallVector<SDValue, 8> OutChains;
Chris Lattner6656dd12006-01-31 02:03:41 +00004502 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
Chris Lattner0c583402007-04-28 20:49:53 +00004503 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
Chris Lattner6656dd12006-01-31 02:03:41 +00004504 getValue(StoresToEmit[i].second),
Evan Cheng8b2794a2006-10-13 21:14:26 +00004505 StoresToEmit[i].second, 0));
Chris Lattner6656dd12006-01-31 02:03:41 +00004506 if (!OutChains.empty())
Chris Lattnerbd564bf2006-08-08 02:23:42 +00004507 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4508 &OutChains[0], OutChains.size());
Chris Lattnerce7518c2006-01-26 22:24:51 +00004509 DAG.setRoot(Chain);
4510}
4511
4512
Chris Lattner1c08c712005-01-07 07:47:53 +00004513void SelectionDAGLowering::visitMalloc(MallocInst &I) {
Dan Gohman475871a2008-07-27 21:46:04 +00004514 SDValue Src = getValue(I.getOperand(0));
Chris Lattner1c08c712005-01-07 07:47:53 +00004515
Duncan Sands83ec4b62008-06-06 12:08:01 +00004516 MVT IntPtr = TLI.getPointerTy();
Chris Lattner68cd65e2005-01-22 23:04:37 +00004517
Duncan Sands8e4eb092008-06-08 20:54:56 +00004518 if (IntPtr.bitsLT(Src.getValueType()))
Chris Lattner68cd65e2005-01-22 23:04:37 +00004519 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
Duncan Sands8e4eb092008-06-08 20:54:56 +00004520 else if (IntPtr.bitsGT(Src.getValueType()))
Chris Lattner68cd65e2005-01-22 23:04:37 +00004521 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
Chris Lattner1c08c712005-01-07 07:47:53 +00004522
4523 // Scale the source by the type size.
Duncan Sands514ab342007-11-01 20:53:16 +00004524 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
Chris Lattner1c08c712005-01-07 07:47:53 +00004525 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
Chris Lattner0bd48932008-01-17 07:00:52 +00004526 Src, DAG.getIntPtrConstant(ElementSize));
Chris Lattner1c08c712005-01-07 07:47:53 +00004527
Reid Spencer47857812006-12-31 05:55:36 +00004528 TargetLowering::ArgListTy Args;
4529 TargetLowering::ArgListEntry Entry;
4530 Entry.Node = Src;
4531 Entry.Ty = TLI.getTargetData()->getIntPtrType();
Reid Spencer47857812006-12-31 05:55:36 +00004532 Args.push_back(Entry);
Chris Lattnercf5734d2005-01-08 19:26:18 +00004533
Dan Gohman475871a2008-07-27 21:46:04 +00004534 std::pair<SDValue,SDValue> Result =
Duncan Sands00fee652008-02-14 17:28:50 +00004535 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4536 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
Chris Lattnercf5734d2005-01-08 19:26:18 +00004537 setValue(&I, Result.first); // Pointers always fit in registers
4538 DAG.setRoot(Result.second);
Chris Lattner1c08c712005-01-07 07:47:53 +00004539}
4540
4541void SelectionDAGLowering::visitFree(FreeInst &I) {
Reid Spencer47857812006-12-31 05:55:36 +00004542 TargetLowering::ArgListTy Args;
4543 TargetLowering::ArgListEntry Entry;
4544 Entry.Node = getValue(I.getOperand(0));
4545 Entry.Ty = TLI.getTargetData()->getIntPtrType();
Reid Spencer47857812006-12-31 05:55:36 +00004546 Args.push_back(Entry);
Duncan Sands83ec4b62008-06-06 12:08:01 +00004547 MVT IntPtr = TLI.getPointerTy();
Dan Gohman475871a2008-07-27 21:46:04 +00004548 std::pair<SDValue,SDValue> Result =
Duncan Sands00fee652008-02-14 17:28:50 +00004549 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4550 CallingConv::C, true,
Chris Lattnercf5734d2005-01-08 19:26:18 +00004551 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4552 DAG.setRoot(Result.second);
Chris Lattner1c08c712005-01-07 07:47:53 +00004553}
4554
Evan Chengff9b3732008-01-30 18:18:23 +00004555// EmitInstrWithCustomInserter - This method should be implemented by targets
4556// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
Chris Lattner025c39b2005-08-26 20:54:47 +00004557// instructions are special in various ways, which require special support to
4558// insert. The specified MachineInstr is created but not inserted into any
4559// basic blocks, and the scheduler passes ownership of it to this method.
Evan Chengff9b3732008-01-30 18:18:23 +00004560MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
Chris Lattner025c39b2005-08-26 20:54:47 +00004561 MachineBasicBlock *MBB) {
Bill Wendling832171c2006-12-07 20:04:42 +00004562 cerr << "If a target marks an instruction with "
4563 << "'usesCustomDAGSchedInserter', it must implement "
Evan Chengff9b3732008-01-30 18:18:23 +00004564 << "TargetLowering::EmitInstrWithCustomInserter!\n";
Chris Lattner025c39b2005-08-26 20:54:47 +00004565 abort();
4566 return 0;
4567}
4568
Chris Lattner39ae3622005-01-09 00:00:49 +00004569void SelectionDAGLowering::visitVAStart(CallInst &I) {
Nate Begemanacc398c2006-01-25 18:21:52 +00004570 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4571 getValue(I.getOperand(1)),
4572 DAG.getSrcValue(I.getOperand(1))));
Chris Lattner39ae3622005-01-09 00:00:49 +00004573}
4574
4575void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
Dan Gohman475871a2008-07-27 21:46:04 +00004576 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
Nate Begemanacc398c2006-01-25 18:21:52 +00004577 getValue(I.getOperand(0)),
4578 DAG.getSrcValue(I.getOperand(0)));
4579 setValue(&I, V);
4580 DAG.setRoot(V.getValue(1));
Chris Lattner1c08c712005-01-07 07:47:53 +00004581}
4582
4583void SelectionDAGLowering::visitVAEnd(CallInst &I) {
Nate Begemanacc398c2006-01-25 18:21:52 +00004584 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4585 getValue(I.getOperand(1)),
4586 DAG.getSrcValue(I.getOperand(1))));
Chris Lattner1c08c712005-01-07 07:47:53 +00004587}
4588
4589void SelectionDAGLowering::visitVACopy(CallInst &I) {
Nate Begemanacc398c2006-01-25 18:21:52 +00004590 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4591 getValue(I.getOperand(1)),
4592 getValue(I.getOperand(2)),
4593 DAG.getSrcValue(I.getOperand(1)),
4594 DAG.getSrcValue(I.getOperand(2))));
Chris Lattner1c08c712005-01-07 07:47:53 +00004595}
4596
Chris Lattnerfdfded52006-04-12 16:20:43 +00004597/// TargetLowering::LowerArguments - This is the default LowerArguments
4598/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004599/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4600/// integrated into SDISel.
Dan Gohmana44b6742008-06-30 20:31:15 +00004601void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
Dan Gohman475871a2008-07-27 21:46:04 +00004602 SmallVectorImpl<SDValue> &ArgValues) {
Chris Lattnerfdfded52006-04-12 16:20:43 +00004603 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
Dan Gohman475871a2008-07-27 21:46:04 +00004604 SmallVector<SDValue, 3+16> Ops;
Chris Lattner8c0c10c2006-05-16 06:45:34 +00004605 Ops.push_back(DAG.getRoot());
Chris Lattnerfdfded52006-04-12 16:20:43 +00004606 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4607 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4608
4609 // Add one result value for each formal argument.
Dan Gohmana44b6742008-06-30 20:31:15 +00004610 SmallVector<MVT, 16> RetVals;
Anton Korobeynikov6aa279d2007-01-28 18:01:49 +00004611 unsigned j = 1;
Anton Korobeynikovac2b2cf2007-01-28 16:04:40 +00004612 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4613 I != E; ++I, ++j) {
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004614 SmallVector<MVT, 4> ValueVTs;
4615 ComputeValueVTs(*this, I->getType(), ValueVTs);
4616 for (unsigned Value = 0, NumValues = ValueVTs.size();
4617 Value != NumValues; ++Value) {
4618 MVT VT = ValueVTs[Value];
4619 const Type *ArgTy = VT.getTypeForMVT();
4620 ISD::ArgFlagsTy Flags;
4621 unsigned OriginalAlignment =
4622 getTargetData()->getABITypeAlignment(ArgTy);
Lauro Ramos Venancio7aa47b62007-02-13 13:50:08 +00004623
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004624 if (F.paramHasAttr(j, ParamAttr::ZExt))
4625 Flags.setZExt();
4626 if (F.paramHasAttr(j, ParamAttr::SExt))
4627 Flags.setSExt();
4628 if (F.paramHasAttr(j, ParamAttr::InReg))
4629 Flags.setInReg();
4630 if (F.paramHasAttr(j, ParamAttr::StructRet))
4631 Flags.setSRet();
4632 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4633 Flags.setByVal();
4634 const PointerType *Ty = cast<PointerType>(I->getType());
4635 const Type *ElementTy = Ty->getElementType();
4636 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4637 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4638 // For ByVal, alignment should be passed from FE. BE will guess if
4639 // this info is not there but there are cases it cannot get right.
4640 if (F.getParamAlignment(j))
4641 FrameAlign = F.getParamAlignment(j);
4642 Flags.setByValAlign(FrameAlign);
4643 Flags.setByValSize(FrameSize);
4644 }
4645 if (F.paramHasAttr(j, ParamAttr::Nest))
4646 Flags.setNest();
4647 Flags.setOrigAlign(OriginalAlignment);
Duncan Sandsb988bac2008-02-11 20:58:28 +00004648
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004649 MVT RegisterVT = getRegisterType(VT);
4650 unsigned NumRegs = getNumRegisters(VT);
4651 for (unsigned i = 0; i != NumRegs; ++i) {
4652 RetVals.push_back(RegisterVT);
4653 ISD::ArgFlagsTy MyFlags = Flags;
4654 if (NumRegs > 1 && i == 0)
4655 MyFlags.setSplit();
4656 // if it isn't first piece, alignment must be 1
4657 else if (i > 0)
4658 MyFlags.setOrigAlign(1);
4659 Ops.push_back(DAG.getArgFlags(MyFlags));
4660 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +00004661 }
Chris Lattnerfdfded52006-04-12 16:20:43 +00004662 }
Evan Cheng3b0d2862006-04-25 23:03:35 +00004663
Chris Lattner8c0c10c2006-05-16 06:45:34 +00004664 RetVals.push_back(MVT::Other);
Chris Lattnerfdfded52006-04-12 16:20:43 +00004665
4666 // Create the node.
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00004667 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
Chris Lattner86ca3ca2008-02-13 07:39:09 +00004668 DAG.getVTList(&RetVals[0], RetVals.size()),
Chris Lattnerbd564bf2006-08-08 02:23:42 +00004669 &Ops[0], Ops.size()).Val;
Chris Lattner86ca3ca2008-02-13 07:39:09 +00004670
4671 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4672 // allows exposing the loads that may be part of the argument access to the
4673 // first DAGCombiner pass.
Dan Gohman475871a2008-07-27 21:46:04 +00004674 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
Chris Lattner86ca3ca2008-02-13 07:39:09 +00004675
4676 // The number of results should match up, except that the lowered one may have
4677 // an extra flag result.
4678 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4679 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4680 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4681 && "Lowering produced unexpected number of results!");
Dan Gohman2dbc1672008-07-21 21:04:07 +00004682
4683 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
4684 if (Result != TmpRes.Val && Result->use_empty()) {
4685 HandleSDNode Dummy(DAG.getRoot());
4686 DAG.RemoveDeadNode(Result);
4687 }
4688
Chris Lattner86ca3ca2008-02-13 07:39:09 +00004689 Result = TmpRes.Val;
4690
Dan Gohman27a70be2007-07-02 16:18:06 +00004691 unsigned NumArgRegs = Result->getNumValues() - 1;
Dan Gohman475871a2008-07-27 21:46:04 +00004692 DAG.setRoot(SDValue(Result, NumArgRegs));
Chris Lattnerfdfded52006-04-12 16:20:43 +00004693
4694 // Set up the return result vector.
Chris Lattnerfdfded52006-04-12 16:20:43 +00004695 unsigned i = 0;
Reid Spencer47857812006-12-31 05:55:36 +00004696 unsigned Idx = 1;
4697 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4698 ++I, ++Idx) {
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004699 SmallVector<MVT, 4> ValueVTs;
4700 ComputeValueVTs(*this, I->getType(), ValueVTs);
4701 for (unsigned Value = 0, NumValues = ValueVTs.size();
4702 Value != NumValues; ++Value) {
4703 MVT VT = ValueVTs[Value];
4704 MVT PartVT = getRegisterType(VT);
Duncan Sandsb988bac2008-02-11 20:58:28 +00004705
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004706 unsigned NumParts = getNumRegisters(VT);
Dan Gohman475871a2008-07-27 21:46:04 +00004707 SmallVector<SDValue, 4> Parts(NumParts);
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004708 for (unsigned j = 0; j != NumParts; ++j)
Dan Gohman475871a2008-07-27 21:46:04 +00004709 Parts[j] = SDValue(Result, i++);
Duncan Sandsb988bac2008-02-11 20:58:28 +00004710
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004711 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4712 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4713 AssertOp = ISD::AssertSext;
4714 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4715 AssertOp = ISD::AssertZext;
Duncan Sandsb988bac2008-02-11 20:58:28 +00004716
Dan Gohmana44b6742008-06-30 20:31:15 +00004717 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4718 AssertOp));
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004719 }
Chris Lattnerfdfded52006-04-12 16:20:43 +00004720 }
Dan Gohman27a70be2007-07-02 16:18:06 +00004721 assert(i == NumArgRegs && "Argument register count mismatch!");
Chris Lattnerfdfded52006-04-12 16:20:43 +00004722}
4723
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004724
4725/// TargetLowering::LowerCallTo - This is the default LowerCallTo
4726/// implementation, which just inserts an ISD::CALL node, which is later custom
4727/// lowered by the target to something concrete. FIXME: When all targets are
4728/// migrated to using ISD::CALL, this hook should be integrated into SDISel.
Dan Gohman475871a2008-07-27 21:46:04 +00004729std::pair<SDValue, SDValue>
4730TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
Duncan Sands00fee652008-02-14 17:28:50 +00004731 bool RetSExt, bool RetZExt, bool isVarArg,
4732 unsigned CallingConv, bool isTailCall,
Dan Gohman475871a2008-07-27 21:46:04 +00004733 SDValue Callee,
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004734 ArgListTy &Args, SelectionDAG &DAG) {
Dan Gohman475871a2008-07-27 21:46:04 +00004735 SmallVector<SDValue, 32> Ops;
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004736 Ops.push_back(Chain); // Op#0 - Chain
4737 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4738 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4739 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4740 Ops.push_back(Callee);
4741
4742 // Handle all of the outgoing arguments.
4743 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004744 SmallVector<MVT, 4> ValueVTs;
4745 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
4746 for (unsigned Value = 0, NumValues = ValueVTs.size();
4747 Value != NumValues; ++Value) {
4748 MVT VT = ValueVTs[Value];
4749 const Type *ArgTy = VT.getTypeForMVT();
Dan Gohman475871a2008-07-27 21:46:04 +00004750 SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.ResNo + Value);
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004751 ISD::ArgFlagsTy Flags;
4752 unsigned OriginalAlignment =
4753 getTargetData()->getABITypeAlignment(ArgTy);
Duncan Sands276dcbd2008-03-21 09:14:45 +00004754
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004755 if (Args[i].isZExt)
4756 Flags.setZExt();
4757 if (Args[i].isSExt)
4758 Flags.setSExt();
4759 if (Args[i].isInReg)
4760 Flags.setInReg();
4761 if (Args[i].isSRet)
4762 Flags.setSRet();
4763 if (Args[i].isByVal) {
4764 Flags.setByVal();
4765 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4766 const Type *ElementTy = Ty->getElementType();
4767 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4768 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4769 // For ByVal, alignment should come from FE. BE will guess if this
4770 // info is not there but there are cases it cannot get right.
4771 if (Args[i].Alignment)
4772 FrameAlign = Args[i].Alignment;
4773 Flags.setByValAlign(FrameAlign);
4774 Flags.setByValSize(FrameSize);
4775 }
4776 if (Args[i].isNest)
4777 Flags.setNest();
4778 Flags.setOrigAlign(OriginalAlignment);
Dan Gohman27a70be2007-07-02 16:18:06 +00004779
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004780 MVT PartVT = getRegisterType(VT);
4781 unsigned NumParts = getNumRegisters(VT);
Dan Gohman475871a2008-07-27 21:46:04 +00004782 SmallVector<SDValue, 4> Parts(NumParts);
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004783 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
Duncan Sandsb988bac2008-02-11 20:58:28 +00004784
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004785 if (Args[i].isSExt)
4786 ExtendKind = ISD::SIGN_EXTEND;
4787 else if (Args[i].isZExt)
4788 ExtendKind = ISD::ZERO_EXTEND;
Duncan Sandsb988bac2008-02-11 20:58:28 +00004789
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004790 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
Duncan Sandsb988bac2008-02-11 20:58:28 +00004791
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004792 for (unsigned i = 0; i != NumParts; ++i) {
4793 // if it isn't first piece, alignment must be 1
4794 ISD::ArgFlagsTy MyFlags = Flags;
4795 if (NumParts > 1 && i == 0)
4796 MyFlags.setSplit();
4797 else if (i != 0)
4798 MyFlags.setOrigAlign(1);
Duncan Sandsb988bac2008-02-11 20:58:28 +00004799
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004800 Ops.push_back(Parts[i]);
4801 Ops.push_back(DAG.getArgFlags(MyFlags));
4802 }
Dan Gohman27a70be2007-07-02 16:18:06 +00004803 }
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004804 }
4805
Dan Gohmanef5d1942008-03-11 21:11:25 +00004806 // Figure out the result value types. We start by making a list of
Dan Gohman23ce5022008-04-25 18:27:55 +00004807 // the potentially illegal return value types.
Duncan Sands83ec4b62008-06-06 12:08:01 +00004808 SmallVector<MVT, 4> LoweredRetTys;
4809 SmallVector<MVT, 4> RetTys;
Dan Gohman23ce5022008-04-25 18:27:55 +00004810 ComputeValueVTs(*this, RetTy, RetTys);
Dan Gohmanef5d1942008-03-11 21:11:25 +00004811
Dan Gohman23ce5022008-04-25 18:27:55 +00004812 // Then we translate that to a list of legal types.
4813 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00004814 MVT VT = RetTys[I];
4815 MVT RegisterVT = getRegisterType(VT);
Dan Gohmanef5d1942008-03-11 21:11:25 +00004816 unsigned NumRegs = getNumRegisters(VT);
4817 for (unsigned i = 0; i != NumRegs; ++i)
4818 LoweredRetTys.push_back(RegisterVT);
4819 }
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004820
Dan Gohmanef5d1942008-03-11 21:11:25 +00004821 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004822
Dan Gohmanb6f5b002007-06-28 23:29:44 +00004823 // Create the CALL node.
Dan Gohman475871a2008-07-27 21:46:04 +00004824 SDValue Res = DAG.getNode(ISD::CALL,
Dan Gohmanef5d1942008-03-11 21:11:25 +00004825 DAG.getVTList(&LoweredRetTys[0],
4826 LoweredRetTys.size()),
Chris Lattnerbe384162006-08-16 22:57:46 +00004827 &Ops[0], Ops.size());
Dan Gohmanef5d1942008-03-11 21:11:25 +00004828 Chain = Res.getValue(LoweredRetTys.size() - 1);
Dan Gohmanb6f5b002007-06-28 23:29:44 +00004829
4830 // Gather up the call result into a single value.
4831 if (RetTy != Type::VoidTy) {
Duncan Sands00fee652008-02-14 17:28:50 +00004832 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4833
4834 if (RetSExt)
4835 AssertOp = ISD::AssertSext;
4836 else if (RetZExt)
Dan Gohmanb6f5b002007-06-28 23:29:44 +00004837 AssertOp = ISD::AssertZext;
Duncan Sands00fee652008-02-14 17:28:50 +00004838
Dan Gohman475871a2008-07-27 21:46:04 +00004839 SmallVector<SDValue, 4> ReturnValues;
Dan Gohmanef5d1942008-03-11 21:11:25 +00004840 unsigned RegNo = 0;
Dan Gohman23ce5022008-04-25 18:27:55 +00004841 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00004842 MVT VT = RetTys[I];
4843 MVT RegisterVT = getRegisterType(VT);
Dan Gohmanef5d1942008-03-11 21:11:25 +00004844 unsigned NumRegs = getNumRegisters(VT);
4845 unsigned RegNoEnd = NumRegs + RegNo;
Dan Gohman475871a2008-07-27 21:46:04 +00004846 SmallVector<SDValue, 4> Results;
Dan Gohmanef5d1942008-03-11 21:11:25 +00004847 for (; RegNo != RegNoEnd; ++RegNo)
4848 Results.push_back(Res.getValue(RegNo));
Dan Gohman475871a2008-07-27 21:46:04 +00004849 SDValue ReturnValue =
Dan Gohmanef5d1942008-03-11 21:11:25 +00004850 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4851 AssertOp);
4852 ReturnValues.push_back(ReturnValue);
4853 }
Duncan Sandsf9516202008-06-30 10:19:09 +00004854 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()),
4855 &ReturnValues[0], ReturnValues.size());
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004856 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +00004857
4858 return std::make_pair(Res, Chain);
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004859}
4860
Dan Gohman475871a2008-07-27 21:46:04 +00004861SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
Chris Lattner171453a2005-01-16 07:28:41 +00004862 assert(0 && "LowerOperation not implemented for this target!");
4863 abort();
Dan Gohman475871a2008-07-27 21:46:04 +00004864 return SDValue();
Chris Lattner171453a2005-01-16 07:28:41 +00004865}
4866
Nate Begeman0aed7842006-01-28 03:14:31 +00004867
Chris Lattner7041ee32005-01-11 05:56:49 +00004868//===----------------------------------------------------------------------===//
4869// SelectionDAGISel code
4870//===----------------------------------------------------------------------===//
Chris Lattner1c08c712005-01-07 07:47:53 +00004871
Duncan Sands83ec4b62008-06-06 12:08:01 +00004872unsigned SelectionDAGISel::MakeReg(MVT VT) {
Chris Lattner84bc5422007-12-31 04:13:23 +00004873 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
Chris Lattner1c08c712005-01-07 07:47:53 +00004874}
4875
Chris Lattner495a0b52005-08-17 06:37:43 +00004876void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
Jim Laskeyc7c3f112006-10-16 20:52:31 +00004877 AU.addRequired<AliasAnalysis>();
Gordon Henriksence224772008-01-07 01:30:38 +00004878 AU.addRequired<CollectorModuleMetadata>();
Chris Lattnerc8d288f2007-03-31 04:18:03 +00004879 AU.setPreservesAll();
Chris Lattner495a0b52005-08-17 06:37:43 +00004880}
Chris Lattner1c08c712005-01-07 07:47:53 +00004881
Chris Lattner1c08c712005-01-07 07:47:53 +00004882bool SelectionDAGISel::runOnFunction(Function &Fn) {
Dan Gohman5f43f922007-08-27 16:26:13 +00004883 // Get alias analysis for load/store combining.
4884 AA = &getAnalysis<AliasAnalysis>();
4885
Chris Lattner1c08c712005-01-07 07:47:53 +00004886 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
Gordon Henriksence224772008-01-07 01:30:38 +00004887 if (MF.getFunction()->hasCollector())
4888 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4889 else
4890 GCI = 0;
Chris Lattner84bc5422007-12-31 04:13:23 +00004891 RegInfo = &MF.getRegInfo();
Bill Wendling832171c2006-12-07 20:04:42 +00004892 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
Chris Lattner1c08c712005-01-07 07:47:53 +00004893
4894 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4895
Dale Johannesen1532f3d2008-04-02 00:25:04 +00004896 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4897 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4898 // Mark landing pad.
4899 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
Duncan Sands9fac0b52007-06-06 10:05:18 +00004900
Dan Gohman0e5f1302008-07-07 23:02:41 +00004901 SelectAllBasicBlocks(Fn, MF, FuncInfo);
Misha Brukmanedf128a2005-04-21 22:36:52 +00004902
Evan Chengad2070c2007-02-10 02:43:39 +00004903 // Add function live-ins to entry block live-in set.
4904 BasicBlock *EntryBB = &Fn.getEntryBlock();
4905 BB = FuncInfo.MBBMap[EntryBB];
Chris Lattner84bc5422007-12-31 04:13:23 +00004906 if (!RegInfo->livein_empty())
4907 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4908 E = RegInfo->livein_end(); I != E; ++I)
Evan Chengad2070c2007-02-10 02:43:39 +00004909 BB->addLiveIn(I->first);
4910
Duncan Sandsf4070822007-06-15 19:04:19 +00004911#ifndef NDEBUG
4912 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4913 "Not all catch info was assigned to a landing pad!");
4914#endif
4915
Chris Lattner1c08c712005-01-07 07:47:53 +00004916 return true;
4917}
4918
Chris Lattner6833b062008-04-28 07:16:35 +00004919void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
Dan Gohman475871a2008-07-27 21:46:04 +00004920 SDValue Op = getValue(V);
Chris Lattner18c2f132005-01-13 20:50:02 +00004921 assert((Op.getOpcode() != ISD::CopyFromReg ||
Chris Lattnerd5d0f9b2005-08-16 21:55:35 +00004922 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
Chris Lattner18c2f132005-01-13 20:50:02 +00004923 "Copy from a reg to the same reg!");
Dan Gohman86e1ebf2008-03-27 19:56:19 +00004924 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
Dan Gohmanb6f5b002007-06-28 23:29:44 +00004925
Dan Gohman23ce5022008-04-25 18:27:55 +00004926 RegsForValue RFV(TLI, Reg, V->getType());
Dan Gohman475871a2008-07-27 21:46:04 +00004927 SDValue Chain = DAG.getEntryNode();
Dan Gohman23ce5022008-04-25 18:27:55 +00004928 RFV.getCopyToRegs(Op, DAG, Chain, 0);
4929 PendingExports.push_back(Chain);
Chris Lattner1c08c712005-01-07 07:47:53 +00004930}
4931
Chris Lattner068a81e2005-01-17 17:15:02 +00004932void SelectionDAGISel::
Dan Gohman86e1ebf2008-03-27 19:56:19 +00004933LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
Chris Lattner068a81e2005-01-17 17:15:02 +00004934 // If this is the entry block, emit arguments.
Evan Cheng15699fc2007-02-10 01:08:18 +00004935 Function &F = *LLVMBB->getParent();
Chris Lattner0afa8e32005-01-17 17:55:19 +00004936 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
Dan Gohman475871a2008-07-27 21:46:04 +00004937 SDValue OldRoot = SDL.DAG.getRoot();
4938 SmallVector<SDValue, 16> Args;
Dan Gohmana44b6742008-06-30 20:31:15 +00004939 TLI.LowerArguments(F, SDL.DAG, Args);
Chris Lattner068a81e2005-01-17 17:15:02 +00004940
Chris Lattnerbf209482005-10-30 19:42:35 +00004941 unsigned a = 0;
4942 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004943 AI != E; ++AI) {
4944 SmallVector<MVT, 4> ValueVTs;
4945 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
4946 unsigned NumValues = ValueVTs.size();
Chris Lattnerbf209482005-10-30 19:42:35 +00004947 if (!AI->use_empty()) {
Duncan Sands4bdcb612008-07-02 17:40:58 +00004948 SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues));
Chris Lattnerbf209482005-10-30 19:42:35 +00004949 // If this argument is live outside of the entry block, insert a copy from
4950 // whereever we got it to the vreg that other BB's will reference it as.
Chris Lattner251db182007-02-25 18:40:32 +00004951 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4952 if (VMI != FuncInfo.ValueMap.end()) {
Dan Gohman86e1ebf2008-03-27 19:56:19 +00004953 SDL.CopyValueToVirtualRegister(AI, VMI->second);
Chris Lattnerbf209482005-10-30 19:42:35 +00004954 }
Chris Lattner0afa8e32005-01-17 17:55:19 +00004955 }
Dan Gohmanf5025cf2008-06-09 21:19:23 +00004956 a += NumValues;
4957 }
Chris Lattnerbf209482005-10-30 19:42:35 +00004958
Chris Lattnerbf209482005-10-30 19:42:35 +00004959 // Finally, if the target has anything special to do, allow it to do so.
Chris Lattner96645412006-05-16 06:10:58 +00004960 // FIXME: this should insert code into the DAG!
Chris Lattnerbf209482005-10-30 19:42:35 +00004961 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
Chris Lattner068a81e2005-01-17 17:15:02 +00004962}
4963
Duncan Sandsf4070822007-06-15 19:04:19 +00004964static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4965 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
Duncan Sandsf4070822007-06-15 19:04:19 +00004966 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
Duncan Sandscf26d7c2007-07-04 20:52:51 +00004967 if (isSelector(I)) {
Duncan Sandsf4070822007-06-15 19:04:19 +00004968 // Apply the catch info to DestBB.
4969 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4970#ifndef NDEBUG
Duncan Sands560a7372007-11-15 09:54:37 +00004971 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4972 FLI.CatchInfoFound.insert(I);
Duncan Sandsf4070822007-06-15 19:04:19 +00004973#endif
4974 }
4975}
4976
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00004977/// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
4978/// whether object offset >= 0.
4979static bool
Dan Gohman475871a2008-07-27 21:46:04 +00004980IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00004981 if (!isa<FrameIndexSDNode>(Op)) return false;
4982
4983 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
4984 int FrameIdx = FrameIdxNode->getIndex();
4985 return MFI->isFixedObjectIndex(FrameIdx) &&
4986 MFI->getObjectOffset(FrameIdx) >= 0;
4987}
4988
4989/// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
4990/// possibly be overwritten when lowering the outgoing arguments in a tail
4991/// call. Currently the implementation of this call is very conservative and
4992/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
4993/// virtual registers would be overwritten by direct lowering.
Dan Gohman475871a2008-07-27 21:46:04 +00004994static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00004995 MachineFrameInfo * MFI) {
4996 RegisterSDNode * OpReg = NULL;
4997 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
4998 (Op.getOpcode()== ISD::CopyFromReg &&
4999 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
5000 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
5001 (Op.getOpcode() == ISD::LOAD &&
5002 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
5003 (Op.getOpcode() == ISD::MERGE_VALUES &&
5004 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
5005 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
5006 getOperand(1))))
5007 return true;
5008 return false;
5009}
5010
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00005011/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +00005012/// DAG and fixes their tailcall attribute operand.
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00005013static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
5014 TargetLowering& TLI) {
5015 SDNode * Ret = NULL;
Dan Gohman475871a2008-07-27 21:46:04 +00005016 SDValue Terminator = DAG.getRoot();
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00005017
5018 // Find RET node.
5019 if (Terminator.getOpcode() == ISD::RET) {
5020 Ret = Terminator.Val;
5021 }
5022
5023 // Fix tail call attribute of CALL nodes.
5024 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
Dan Gohman0e5f1302008-07-07 23:02:41 +00005025 BI = DAG.allnodes_end(); BI != BE; ) {
5026 --BI;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00005027 if (BI->getOpcode() == ISD::CALL) {
Dan Gohman475871a2008-07-27 21:46:04 +00005028 SDValue OpRet(Ret, 0);
5029 SDValue OpCall(BI, 0);
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00005030 bool isMarkedTailCall =
5031 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
5032 // If CALL node has tail call attribute set to true and the call is not
5033 // eligible (no RET or the target rejects) the attribute is fixed to
Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +00005034 // false. The TargetLowering::IsEligibleForTailCallOptimization function
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00005035 // must correctly identify tail call optimizable calls.
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00005036 if (!isMarkedTailCall) continue;
5037 if (Ret==NULL ||
5038 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) {
5039 // Not eligible. Mark CALL node as non tail call.
Dan Gohman475871a2008-07-27 21:46:04 +00005040 SmallVector<SDValue, 32> Ops;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00005041 unsigned idx=0;
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00005042 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
5043 E = OpCall.Val->op_end(); I != E; I++, idx++) {
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00005044 if (idx!=3)
5045 Ops.push_back(*I);
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00005046 else
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00005047 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
5048 }
5049 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00005050 } else {
5051 // Look for tail call clobbered arguments. Emit a series of
5052 // copyto/copyfrom virtual register nodes to protect them.
Dan Gohman475871a2008-07-27 21:46:04 +00005053 SmallVector<SDValue, 32> Ops;
5054 SDValue Chain = OpCall.getOperand(0), InFlag;
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00005055 unsigned idx=0;
5056 for(SDNode::op_iterator I = OpCall.Val->op_begin(),
5057 E = OpCall.Val->op_end(); I != E; I++, idx++) {
Dan Gohman475871a2008-07-27 21:46:04 +00005058 SDValue Arg = *I;
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00005059 if (idx > 4 && (idx % 2)) {
5060 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
5061 getArgFlags().isByVal();
5062 MachineFunction &MF = DAG.getMachineFunction();
5063 MachineFrameInfo *MFI = MF.getFrameInfo();
5064 if (!isByVal &&
5065 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00005066 MVT VT = Arg.getValueType();
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00005067 unsigned VReg = MF.getRegInfo().
5068 createVirtualRegister(TLI.getRegClassFor(VT));
5069 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
5070 InFlag = Chain.getValue(1);
5071 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
5072 Chain = Arg.getValue(1);
5073 InFlag = Arg.getValue(2);
5074 }
5075 }
5076 Ops.push_back(Arg);
5077 }
5078 // Link in chain of CopyTo/CopyFromReg.
5079 Ops[0] = Chain;
5080 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00005081 }
5082 }
5083 }
5084}
5085
Chris Lattner1c08c712005-01-07 07:47:53 +00005086void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
5087 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
Nate Begemanf15485a2006-03-27 01:32:24 +00005088 FunctionLoweringInfo &FuncInfo) {
Gordon Henriksence224772008-01-07 01:30:38 +00005089 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
Chris Lattnerddb870b2005-01-13 17:59:43 +00005090
Chris Lattnerbf209482005-10-30 19:42:35 +00005091 // Lower any arguments needed in this block if this is the entry block.
Dan Gohmanecb7a772007-03-22 16:38:57 +00005092 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
Dan Gohman86e1ebf2008-03-27 19:56:19 +00005093 LowerArguments(LLVMBB, SDL);
Chris Lattner1c08c712005-01-07 07:47:53 +00005094
5095 BB = FuncInfo.MBBMap[LLVMBB];
5096 SDL.setCurrentBasicBlock(BB);
5097
Duncan Sandsf4070822007-06-15 19:04:19 +00005098 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Duncan Sands9fac0b52007-06-06 10:05:18 +00005099
Dale Johannesen1532f3d2008-04-02 00:25:04 +00005100 if (MMI && BB->isLandingPad()) {
Duncan Sandsf4070822007-06-15 19:04:19 +00005101 // Add a label to mark the beginning of the landing pad. Deletion of the
5102 // landing pad can thus be detected via the MachineModuleInfo.
5103 unsigned LabelID = MMI->addLandingPad(BB);
Dan Gohman44066042008-07-01 00:05:16 +00005104 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, DAG.getEntryNode(), LabelID));
Duncan Sandsf4070822007-06-15 19:04:19 +00005105
Evan Chenge47c3332007-06-27 18:45:32 +00005106 // Mark exception register as live in.
5107 unsigned Reg = TLI.getExceptionAddressRegister();
5108 if (Reg) BB->addLiveIn(Reg);
5109
5110 // Mark exception selector register as live in.
5111 Reg = TLI.getExceptionSelectorRegister();
5112 if (Reg) BB->addLiveIn(Reg);
5113
Duncan Sandsf4070822007-06-15 19:04:19 +00005114 // FIXME: Hack around an exception handling flaw (PR1508): the personality
5115 // function and list of typeids logically belong to the invoke (or, if you
5116 // like, the basic block containing the invoke), and need to be associated
5117 // with it in the dwarf exception handling tables. Currently however the
Duncan Sandscf26d7c2007-07-04 20:52:51 +00005118 // information is provided by an intrinsic (eh.selector) that can be moved
5119 // to unexpected places by the optimizers: if the unwind edge is critical,
5120 // then breaking it can result in the intrinsics being in the successor of
5121 // the landing pad, not the landing pad itself. This results in exceptions
5122 // not being caught because no typeids are associated with the invoke.
5123 // This may not be the only way things can go wrong, but it is the only way
5124 // we try to work around for the moment.
Duncan Sandsf4070822007-06-15 19:04:19 +00005125 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
5126
5127 if (Br && Br->isUnconditional()) { // Critical edge?
5128 BasicBlock::iterator I, E;
5129 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
Duncan Sandscf26d7c2007-07-04 20:52:51 +00005130 if (isSelector(I))
Duncan Sandsf4070822007-06-15 19:04:19 +00005131 break;
5132
5133 if (I == E)
5134 // No catch info found - try to extract some from the successor.
5135 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
Duncan Sands9fac0b52007-06-06 10:05:18 +00005136 }
5137 }
5138
Chris Lattner1c08c712005-01-07 07:47:53 +00005139 // Lower all of the non-terminator instructions.
5140 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
5141 I != E; ++I)
5142 SDL.visit(*I);
Duncan Sandsf19f6bb2007-06-13 05:51:31 +00005143
Chris Lattner1c08c712005-01-07 07:47:53 +00005144 // Ensure that all instructions which are used outside of their defining
Duncan Sandsf19f6bb2007-06-13 05:51:31 +00005145 // blocks are available as virtual registers. Invoke is handled elsewhere.
Chris Lattner1c08c712005-01-07 07:47:53 +00005146 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
Duncan Sandsf19f6bb2007-06-13 05:51:31 +00005147 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
Chris Lattner9f24ad72007-02-04 01:35:11 +00005148 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
Chris Lattner1c08c712005-01-07 07:47:53 +00005149 if (VMI != FuncInfo.ValueMap.end())
Dan Gohman86e1ebf2008-03-27 19:56:19 +00005150 SDL.CopyValueToVirtualRegister(I, VMI->second);
Chris Lattner1c08c712005-01-07 07:47:53 +00005151 }
5152
5153 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5154 // ensure constants are generated when needed. Remember the virtual registers
5155 // that need to be added to the Machine PHI nodes as input. We cannot just
5156 // directly add them, because expansion might result in multiple MBB's for one
5157 // BB. As such, the start of the BB might correspond to a different MBB than
5158 // the end.
Misha Brukmanedf128a2005-04-21 22:36:52 +00005159 //
Chris Lattner8c494ab2006-10-27 23:50:33 +00005160 TerminatorInst *TI = LLVMBB->getTerminator();
Chris Lattner1c08c712005-01-07 07:47:53 +00005161
5162 // Emit constants only once even if used by multiple PHI nodes.
5163 std::map<Constant*, unsigned> ConstantsOut;
Chris Lattnerd5e93c02006-09-07 01:59:34 +00005164
Chris Lattner8c494ab2006-10-27 23:50:33 +00005165 // Vector bool would be better, but vector<bool> is really slow.
5166 std::vector<unsigned char> SuccsHandled;
5167 if (TI->getNumSuccessors())
5168 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
5169
Dan Gohman532dc2e2007-07-09 20:59:04 +00005170 // Check successor nodes' PHI nodes that expect a constant to be available
5171 // from this block.
Chris Lattner1c08c712005-01-07 07:47:53 +00005172 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5173 BasicBlock *SuccBB = TI->getSuccessor(succ);
Chris Lattnerd5e93c02006-09-07 01:59:34 +00005174 if (!isa<PHINode>(SuccBB->begin())) continue;
Chris Lattner8c494ab2006-10-27 23:50:33 +00005175 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
Chris Lattnerd5e93c02006-09-07 01:59:34 +00005176
Chris Lattner8c494ab2006-10-27 23:50:33 +00005177 // If this terminator has multiple identical successors (common for
5178 // switches), only handle each succ once.
5179 unsigned SuccMBBNo = SuccMBB->getNumber();
5180 if (SuccsHandled[SuccMBBNo]) continue;
5181 SuccsHandled[SuccMBBNo] = true;
5182
5183 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
Chris Lattner1c08c712005-01-07 07:47:53 +00005184 PHINode *PN;
5185
5186 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5187 // nodes and Machine PHI nodes, but the incoming operands have not been
5188 // emitted yet.
5189 for (BasicBlock::iterator I = SuccBB->begin();
Chris Lattner8c494ab2006-10-27 23:50:33 +00005190 (PN = dyn_cast<PHINode>(I)); ++I) {
5191 // Ignore dead phi's.
5192 if (PN->use_empty()) continue;
5193
5194 unsigned Reg;
5195 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
Chris Lattner3f7927c2006-11-29 01:12:32 +00005196
Chris Lattner8c494ab2006-10-27 23:50:33 +00005197 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5198 unsigned &RegOut = ConstantsOut[C];
5199 if (RegOut == 0) {
5200 RegOut = FuncInfo.CreateRegForValue(C);
Dan Gohman86e1ebf2008-03-27 19:56:19 +00005201 SDL.CopyValueToVirtualRegister(C, RegOut);
Chris Lattner1c08c712005-01-07 07:47:53 +00005202 }
Chris Lattner8c494ab2006-10-27 23:50:33 +00005203 Reg = RegOut;
5204 } else {
5205 Reg = FuncInfo.ValueMap[PHIOp];
5206 if (Reg == 0) {
5207 assert(isa<AllocaInst>(PHIOp) &&
5208 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5209 "Didn't codegen value into a register!??");
5210 Reg = FuncInfo.CreateRegForValue(PHIOp);
Dan Gohman86e1ebf2008-03-27 19:56:19 +00005211 SDL.CopyValueToVirtualRegister(PHIOp, Reg);
Chris Lattner7e021512006-03-31 02:12:18 +00005212 }
Chris Lattner1c08c712005-01-07 07:47:53 +00005213 }
Chris Lattner8c494ab2006-10-27 23:50:33 +00005214
5215 // Remember that this register needs to added to the machine PHI node as
5216 // the input for this MBB.
Duncan Sands83ec4b62008-06-06 12:08:01 +00005217 MVT VT = TLI.getValueType(PN->getType());
Dan Gohman7f321562007-06-25 16:23:39 +00005218 unsigned NumRegisters = TLI.getNumRegisters(VT);
Dan Gohmanb9f10192007-06-21 14:42:22 +00005219 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
Chris Lattner8c494ab2006-10-27 23:50:33 +00005220 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5221 }
Chris Lattner1c08c712005-01-07 07:47:53 +00005222 }
5223 ConstantsOut.clear();
5224
5225 // Lower the terminator after the copies are emitted.
Duncan Sandsf19f6bb2007-06-13 05:51:31 +00005226 SDL.visit(*LLVMBB->getTerminator());
Chris Lattnera651cf62005-01-17 19:43:36 +00005227
Nate Begemanf15485a2006-03-27 01:32:24 +00005228 // Copy over any CaseBlock records that may now exist due to SwitchInst
Nate Begeman37efe672006-04-22 18:53:45 +00005229 // lowering, as well as any jump table information.
Nate Begemanf15485a2006-03-27 01:32:24 +00005230 SwitchCases.clear();
5231 SwitchCases = SDL.SwitchCases;
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00005232 JTCases.clear();
5233 JTCases = SDL.JTCases;
Anton Korobeynikov4198c582007-04-09 12:31:58 +00005234 BitTestCases.clear();
5235 BitTestCases = SDL.BitTestCases;
5236
Chris Lattnera651cf62005-01-17 19:43:36 +00005237 // Make sure the root of the DAG is up-to-date.
Dan Gohman86e1ebf2008-03-27 19:56:19 +00005238 DAG.setRoot(SDL.getControlRoot());
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00005239
5240 // Check whether calls in this block are real tail calls. Fix up CALL nodes
5241 // with correct tailcall attribute so that the target can rely on the tailcall
5242 // attribute indicating whether the call is really eligible for tail call
5243 // optimization.
5244 CheckDAGForTailCallsAndFixThem(DAG, TLI);
Chris Lattner1c08c712005-01-07 07:47:53 +00005245}
5246
Chris Lattneread0d882008-06-17 06:09:18 +00005247void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) {
5248 SmallPtrSet<SDNode*, 128> VisitedNodes;
5249 SmallVector<SDNode*, 128> Worklist;
5250
5251 Worklist.push_back(DAG.getRoot().Val);
5252
5253 APInt Mask;
5254 APInt KnownZero;
5255 APInt KnownOne;
5256
5257 while (!Worklist.empty()) {
5258 SDNode *N = Worklist.back();
5259 Worklist.pop_back();
5260
5261 // If we've already seen this node, ignore it.
5262 if (!VisitedNodes.insert(N))
5263 continue;
5264
5265 // Otherwise, add all chain operands to the worklist.
5266 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5267 if (N->getOperand(i).getValueType() == MVT::Other)
5268 Worklist.push_back(N->getOperand(i).Val);
5269
5270 // If this is a CopyToReg with a vreg dest, process it.
5271 if (N->getOpcode() != ISD::CopyToReg)
5272 continue;
5273
5274 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
5275 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
5276 continue;
5277
5278 // Ignore non-scalar or non-integer values.
Dan Gohman475871a2008-07-27 21:46:04 +00005279 SDValue Src = N->getOperand(2);
Chris Lattneread0d882008-06-17 06:09:18 +00005280 MVT SrcVT = Src.getValueType();
5281 if (!SrcVT.isInteger() || SrcVT.isVector())
5282 continue;
5283
5284 unsigned NumSignBits = DAG.ComputeNumSignBits(Src);
5285 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
5286 DAG.ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
5287
5288 // Only install this information if it tells us something.
5289 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
5290 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
5291 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5292 if (DestReg >= FLI.LiveOutRegInfo.size())
5293 FLI.LiveOutRegInfo.resize(DestReg+1);
5294 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
5295 LOI.NumSignBits = NumSignBits;
5296 LOI.KnownOne = NumSignBits;
5297 LOI.KnownZero = NumSignBits;
5298 }
5299 }
5300}
5301
Nate Begemanf15485a2006-03-27 01:32:24 +00005302void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
Dan Gohman462dc7f2008-07-21 20:00:07 +00005303 std::string GroupName;
5304 if (TimePassesIsEnabled)
5305 GroupName = "Instruction Selection and Scheduling";
5306 std::string BlockName;
5307 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
5308 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs)
5309 BlockName = DAG.getMachineFunction().getFunction()->getName() + ':' +
5310 BB->getBasicBlock()->getName();
5311
5312 DOUT << "Initial selection DAG:\n";
Dan Gohman417e11b2007-10-08 15:12:17 +00005313 DEBUG(DAG.dump());
Dan Gohman462dc7f2008-07-21 20:00:07 +00005314
5315 if (ViewDAGCombine1) DAG.viewGraph("dag-combine1 input for " + BlockName);
Dan Gohman417e11b2007-10-08 15:12:17 +00005316
Chris Lattneraf21d552005-10-10 16:47:10 +00005317 // Run the DAG combiner in pre-legalize mode.
Evan Chengebffb662008-07-01 17:59:20 +00005318 if (TimePassesIsEnabled) {
Dan Gohman5e843682008-07-14 18:19:29 +00005319 NamedRegionTimer T("DAG Combining 1", GroupName);
Evan Chengebffb662008-07-01 17:59:20 +00005320 DAG.Combine(false, *AA);
5321 } else {
5322 DAG.Combine(false, *AA);
5323 }
Nate Begeman2300f552005-09-07 00:15:36 +00005324
Dan Gohman417e11b2007-10-08 15:12:17 +00005325 DOUT << "Optimized lowered selection DAG:\n";
Chris Lattner1c08c712005-01-07 07:47:53 +00005326 DEBUG(DAG.dump());
Duncan Sandsf00e74f2008-07-17 17:06:03 +00005327
Chris Lattner1c08c712005-01-07 07:47:53 +00005328 // Second step, hack on the DAG until it only uses operations and types that
5329 // the target supports.
Duncan Sandsf00e74f2008-07-17 17:06:03 +00005330 if (EnableLegalizeTypes) {// Enable this some day.
Dan Gohman462dc7f2008-07-21 20:00:07 +00005331 if (ViewLegalizeTypesDAGs) DAG.viewGraph("legalize-types input for " +
5332 BlockName);
5333
5334 if (TimePassesIsEnabled) {
5335 NamedRegionTimer T("Type Legalization", GroupName);
5336 DAG.LegalizeTypes();
5337 } else {
5338 DAG.LegalizeTypes();
5339 }
5340
5341 DOUT << "Type-legalized selection DAG:\n";
5342 DEBUG(DAG.dump());
5343
Chris Lattner70587ea2008-07-10 23:37:50 +00005344 // TODO: enable a dag combine pass here.
5345 }
Duncan Sandsf00e74f2008-07-17 17:06:03 +00005346
Dan Gohman462dc7f2008-07-21 20:00:07 +00005347 if (ViewLegalizeDAGs) DAG.viewGraph("legalize input for " + BlockName);
5348
Evan Chengebffb662008-07-01 17:59:20 +00005349 if (TimePassesIsEnabled) {
Dan Gohman5e843682008-07-14 18:19:29 +00005350 NamedRegionTimer T("DAG Legalization", GroupName);
Evan Chengebffb662008-07-01 17:59:20 +00005351 DAG.Legalize();
5352 } else {
5353 DAG.Legalize();
5354 }
Nate Begemanf15485a2006-03-27 01:32:24 +00005355
Bill Wendling832171c2006-12-07 20:04:42 +00005356 DOUT << "Legalized selection DAG:\n";
Chris Lattner1c08c712005-01-07 07:47:53 +00005357 DEBUG(DAG.dump());
Nate Begemanf15485a2006-03-27 01:32:24 +00005358
Dan Gohman462dc7f2008-07-21 20:00:07 +00005359 if (ViewDAGCombine2) DAG.viewGraph("dag-combine2 input for " + BlockName);
5360
Chris Lattneraf21d552005-10-10 16:47:10 +00005361 // Run the DAG combiner in post-legalize mode.
Evan Chengebffb662008-07-01 17:59:20 +00005362 if (TimePassesIsEnabled) {
Dan Gohman5e843682008-07-14 18:19:29 +00005363 NamedRegionTimer T("DAG Combining 2", GroupName);
Evan Chengebffb662008-07-01 17:59:20 +00005364 DAG.Combine(true, *AA);
5365 } else {
5366 DAG.Combine(true, *AA);
5367 }
Nate Begeman2300f552005-09-07 00:15:36 +00005368
Dan Gohman417e11b2007-10-08 15:12:17 +00005369 DOUT << "Optimized legalized selection DAG:\n";
5370 DEBUG(DAG.dump());
5371
Dan Gohman462dc7f2008-07-21 20:00:07 +00005372 if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName);
Chris Lattneread0d882008-06-17 06:09:18 +00005373
Evan Chengf1a792b2008-07-01 18:15:04 +00005374 if (!FastISel && EnableValueProp)
Chris Lattneread0d882008-06-17 06:09:18 +00005375 ComputeLiveOutVRegInfo(DAG);
Evan Cheng552c4a82006-04-28 02:09:19 +00005376
Chris Lattnera33ef482005-03-30 01:10:47 +00005377 // Third, instruction select all of the operations to machine code, adding the
5378 // code to the MachineBasicBlock.
Evan Chengebffb662008-07-01 17:59:20 +00005379 if (TimePassesIsEnabled) {
Dan Gohman5e843682008-07-14 18:19:29 +00005380 NamedRegionTimer T("Instruction Selection", GroupName);
Evan Chengebffb662008-07-01 17:59:20 +00005381 InstructionSelect(DAG);
5382 } else {
5383 InstructionSelect(DAG);
5384 }
Evan Chengdb8d56b2008-06-30 20:45:06 +00005385
Dan Gohman462dc7f2008-07-21 20:00:07 +00005386 DOUT << "Selected selection DAG:\n";
5387 DEBUG(DAG.dump());
5388
5389 if (ViewSchedDAGs) DAG.viewGraph("scheduler input for " + BlockName);
5390
Dan Gohman5e843682008-07-14 18:19:29 +00005391 // Schedule machine code.
5392 ScheduleDAG *Scheduler;
5393 if (TimePassesIsEnabled) {
5394 NamedRegionTimer T("Instruction Scheduling", GroupName);
5395 Scheduler = Schedule(DAG);
5396 } else {
5397 Scheduler = Schedule(DAG);
5398 }
5399
Dan Gohman462dc7f2008-07-21 20:00:07 +00005400 if (ViewSUnitDAGs) Scheduler->viewGraph();
5401
Evan Chengdb8d56b2008-06-30 20:45:06 +00005402 // Emit machine code to BB. This can change 'BB' to the last block being
5403 // inserted into.
Evan Chengebffb662008-07-01 17:59:20 +00005404 if (TimePassesIsEnabled) {
Dan Gohman5e843682008-07-14 18:19:29 +00005405 NamedRegionTimer T("Instruction Creation", GroupName);
5406 BB = Scheduler->EmitSchedule();
Evan Chengebffb662008-07-01 17:59:20 +00005407 } else {
Dan Gohman5e843682008-07-14 18:19:29 +00005408 BB = Scheduler->EmitSchedule();
5409 }
5410
5411 // Free the scheduler state.
5412 if (TimePassesIsEnabled) {
5413 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
5414 delete Scheduler;
5415 } else {
5416 delete Scheduler;
Evan Chengebffb662008-07-01 17:59:20 +00005417 }
Evan Chengdb8d56b2008-06-30 20:45:06 +00005418
5419 // Perform target specific isel post processing.
Evan Chengebffb662008-07-01 17:59:20 +00005420 if (TimePassesIsEnabled) {
Dan Gohman5e843682008-07-14 18:19:29 +00005421 NamedRegionTimer T("Instruction Selection Post Processing", GroupName);
Dan Gohman462dc7f2008-07-21 20:00:07 +00005422 InstructionSelectPostProcessing();
Evan Chengebffb662008-07-01 17:59:20 +00005423 } else {
Dan Gohman462dc7f2008-07-21 20:00:07 +00005424 InstructionSelectPostProcessing();
Evan Chengebffb662008-07-01 17:59:20 +00005425 }
Nate Begemanf15485a2006-03-27 01:32:24 +00005426
Bill Wendling832171c2006-12-07 20:04:42 +00005427 DOUT << "Selected machine code:\n";
Chris Lattner1c08c712005-01-07 07:47:53 +00005428 DEBUG(BB->dump());
Nate Begemanf15485a2006-03-27 01:32:24 +00005429}
Chris Lattner1c08c712005-01-07 07:47:53 +00005430
Dan Gohman0e5f1302008-07-07 23:02:41 +00005431void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
5432 FunctionLoweringInfo &FuncInfo) {
Dan Gohmanfed90b62008-07-28 21:51:04 +00005433 // Define NodeAllocator here so that memory allocation is reused for
Dan Gohman0e5f1302008-07-07 23:02:41 +00005434 // each basic block.
Dan Gohmanfed90b62008-07-28 21:51:04 +00005435 NodeAllocatorType NodeAllocator;
Dan Gohman0e5f1302008-07-07 23:02:41 +00005436
Dan Gohmanfed90b62008-07-28 21:51:04 +00005437 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
5438 SelectBasicBlock(I, MF, FuncInfo, NodeAllocator);
Dan Gohman0e5f1302008-07-07 23:02:41 +00005439}
5440
Dan Gohmanfed90b62008-07-28 21:51:04 +00005441void
5442SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
5443 FunctionLoweringInfo &FuncInfo,
5444 NodeAllocatorType &NodeAllocator) {
Nate Begemanf15485a2006-03-27 01:32:24 +00005445 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
5446 {
Chris Lattneread0d882008-06-17 06:09:18 +00005447 SelectionDAG DAG(TLI, MF, FuncInfo,
Dan Gohman0e5f1302008-07-07 23:02:41 +00005448 getAnalysisToUpdate<MachineModuleInfo>(),
Dan Gohmanfed90b62008-07-28 21:51:04 +00005449 NodeAllocator);
Nate Begemanf15485a2006-03-27 01:32:24 +00005450 CurDAG = &DAG;
5451
5452 // First step, lower LLVM code to some DAG. This DAG may use operations and
5453 // types that are not supported by the target.
5454 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
5455
5456 // Second step, emit the lowered DAG as machine code.
5457 CodeGenAndEmitDAG(DAG);
5458 }
Anton Korobeynikov4198c582007-04-09 12:31:58 +00005459
5460 DOUT << "Total amount of phi nodes to update: "
5461 << PHINodesToUpdate.size() << "\n";
5462 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
5463 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
5464 << ", " << PHINodesToUpdate[i].second << ")\n";);
Nate Begemanf15485a2006-03-27 01:32:24 +00005465
Chris Lattnera33ef482005-03-30 01:10:47 +00005466 // Next, now that we know what the last MBB the LLVM BB expanded is, update
Chris Lattner1c08c712005-01-07 07:47:53 +00005467 // PHI nodes in successors.
Anton Korobeynikov4198c582007-04-09 12:31:58 +00005468 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
Nate Begemanf15485a2006-03-27 01:32:24 +00005469 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5470 MachineInstr *PHI = PHINodesToUpdate[i].first;
5471 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5472 "This is not a machine PHI node that we are updating!");
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00005473 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5474 false));
5475 PHI->addOperand(MachineOperand::CreateMBB(BB));
Nate Begemanf15485a2006-03-27 01:32:24 +00005476 }
5477 return;
Chris Lattner1c08c712005-01-07 07:47:53 +00005478 }
Anton Korobeynikov4198c582007-04-09 12:31:58 +00005479
5480 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
5481 // Lower header first, if it wasn't already lowered
5482 if (!BitTestCases[i].Emitted) {
Chris Lattneread0d882008-06-17 06:09:18 +00005483 SelectionDAG HSDAG(TLI, MF, FuncInfo,
Dan Gohman0e5f1302008-07-07 23:02:41 +00005484 getAnalysisToUpdate<MachineModuleInfo>(),
Dan Gohmanfed90b62008-07-28 21:51:04 +00005485 NodeAllocator);
Anton Korobeynikov4198c582007-04-09 12:31:58 +00005486 CurDAG = &HSDAG;
Gordon Henriksence224772008-01-07 01:30:38 +00005487 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
Anton Korobeynikov4198c582007-04-09 12:31:58 +00005488 // Set the current basic block to the mbb we wish to insert the code into
5489 BB = BitTestCases[i].Parent;
5490 HSDL.setCurrentBasicBlock(BB);
5491 // Emit the code
5492 HSDL.visitBitTestHeader(BitTestCases[i]);
5493 HSDAG.setRoot(HSDL.getRoot());
5494 CodeGenAndEmitDAG(HSDAG);
5495 }
5496
5497 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
Chris Lattneread0d882008-06-17 06:09:18 +00005498 SelectionDAG BSDAG(TLI, MF, FuncInfo,
Dan Gohman0e5f1302008-07-07 23:02:41 +00005499 getAnalysisToUpdate<MachineModuleInfo>(),
Dan Gohmanfed90b62008-07-28 21:51:04 +00005500 NodeAllocator);
Anton Korobeynikov4198c582007-04-09 12:31:58 +00005501 CurDAG = &BSDAG;
Gordon Henriksence224772008-01-07 01:30:38 +00005502 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
Anton Korobeynikov4198c582007-04-09 12:31:58 +00005503 // Set the current basic block to the mbb we wish to insert the code into
5504 BB = BitTestCases[i].Cases[j].ThisBB;
5505 BSDL.setCurrentBasicBlock(BB);
5506 // Emit the code
5507 if (j+1 != ej)
5508 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
5509 BitTestCases[i].Reg,
5510 BitTestCases[i].Cases[j]);
5511 else
5512 BSDL.visitBitTestCase(BitTestCases[i].Default,
5513 BitTestCases[i].Reg,
5514 BitTestCases[i].Cases[j]);
5515
5516
5517 BSDAG.setRoot(BSDL.getRoot());
5518 CodeGenAndEmitDAG(BSDAG);
5519 }
5520
5521 // Update PHI Nodes
5522 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5523 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5524 MachineBasicBlock *PHIBB = PHI->getParent();
5525 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5526 "This is not a machine PHI node that we are updating!");
5527 // This is "default" BB. We have two jumps to it. From "header" BB and
5528 // from last "case" BB.
5529 if (PHIBB == BitTestCases[i].Default) {
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00005530 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5531 false));
5532 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
5533 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5534 false));
5535 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
5536 back().ThisBB));
Anton Korobeynikov4198c582007-04-09 12:31:58 +00005537 }
5538 // One of "cases" BB.
5539 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5540 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
5541 if (cBB->succ_end() !=
5542 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00005543 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5544 false));
5545 PHI->addOperand(MachineOperand::CreateMBB(cBB));
Anton Korobeynikov4198c582007-04-09 12:31:58 +00005546 }
5547 }
5548 }
5549 }
5550
Nate Begeman9453eea2006-04-23 06:26:20 +00005551 // If the JumpTable record is filled in, then we need to emit a jump table.
5552 // Updating the PHI nodes is tricky in this case, since we need to determine
5553 // whether the PHI is a successor of the range check MBB or the jump table MBB
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00005554 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5555 // Lower header first, if it wasn't already lowered
5556 if (!JTCases[i].first.Emitted) {
Chris Lattneread0d882008-06-17 06:09:18 +00005557 SelectionDAG HSDAG(TLI, MF, FuncInfo,
Dan Gohman0e5f1302008-07-07 23:02:41 +00005558 getAnalysisToUpdate<MachineModuleInfo>(),
Dan Gohmanfed90b62008-07-28 21:51:04 +00005559 NodeAllocator);
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00005560 CurDAG = &HSDAG;
Gordon Henriksence224772008-01-07 01:30:38 +00005561 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00005562 // Set the current basic block to the mbb we wish to insert the code into
5563 BB = JTCases[i].first.HeaderBB;
5564 HSDL.setCurrentBasicBlock(BB);
5565 // Emit the code
5566 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5567 HSDAG.setRoot(HSDL.getRoot());
5568 CodeGenAndEmitDAG(HSDAG);
Anton Korobeynikov4198c582007-04-09 12:31:58 +00005569 }
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00005570
Chris Lattneread0d882008-06-17 06:09:18 +00005571 SelectionDAG JSDAG(TLI, MF, FuncInfo,
Dan Gohman0e5f1302008-07-07 23:02:41 +00005572 getAnalysisToUpdate<MachineModuleInfo>(),
Dan Gohmanfed90b62008-07-28 21:51:04 +00005573 NodeAllocator);
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00005574 CurDAG = &JSDAG;
Gordon Henriksence224772008-01-07 01:30:38 +00005575 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
Nate Begeman37efe672006-04-22 18:53:45 +00005576 // Set the current basic block to the mbb we wish to insert the code into
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00005577 BB = JTCases[i].second.MBB;
5578 JSDL.setCurrentBasicBlock(BB);
Nate Begeman37efe672006-04-22 18:53:45 +00005579 // Emit the code
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00005580 JSDL.visitJumpTable(JTCases[i].second);
5581 JSDAG.setRoot(JSDL.getRoot());
5582 CodeGenAndEmitDAG(JSDAG);
5583
Nate Begeman37efe672006-04-22 18:53:45 +00005584 // Update PHI Nodes
5585 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5586 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5587 MachineBasicBlock *PHIBB = PHI->getParent();
5588 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5589 "This is not a machine PHI node that we are updating!");
Anton Korobeynikov4198c582007-04-09 12:31:58 +00005590 // "default" BB. We can go there only from header BB.
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00005591 if (PHIBB == JTCases[i].second.Default) {
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00005592 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5593 false));
5594 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
Nate Begemanf4360a42006-05-03 03:48:02 +00005595 }
Anton Korobeynikov4198c582007-04-09 12:31:58 +00005596 // JT BB. Just iterate over successors here
Nate Begemanf4360a42006-05-03 03:48:02 +00005597 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00005598 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5599 false));
5600 PHI->addOperand(MachineOperand::CreateMBB(BB));
Nate Begeman37efe672006-04-22 18:53:45 +00005601 }
5602 }
Nate Begeman37efe672006-04-22 18:53:45 +00005603 }
5604
Chris Lattnerb2e806e2006-10-22 23:00:53 +00005605 // If the switch block involved a branch to one of the actual successors, we
5606 // need to update PHI nodes in that block.
5607 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5608 MachineInstr *PHI = PHINodesToUpdate[i].first;
5609 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5610 "This is not a machine PHI node that we are updating!");
5611 if (BB->isSuccessor(PHI->getParent())) {
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00005612 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5613 false));
5614 PHI->addOperand(MachineOperand::CreateMBB(BB));
Chris Lattnerb2e806e2006-10-22 23:00:53 +00005615 }
5616 }
5617
Nate Begemanf15485a2006-03-27 01:32:24 +00005618 // If we generated any switch lowering information, build and codegen any
5619 // additional DAGs necessary.
Chris Lattnerd5e93c02006-09-07 01:59:34 +00005620 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
Chris Lattneread0d882008-06-17 06:09:18 +00005621 SelectionDAG SDAG(TLI, MF, FuncInfo,
Dan Gohman0e5f1302008-07-07 23:02:41 +00005622 getAnalysisToUpdate<MachineModuleInfo>(),
Dan Gohmanfed90b62008-07-28 21:51:04 +00005623 NodeAllocator);
Nate Begemanf15485a2006-03-27 01:32:24 +00005624 CurDAG = &SDAG;
Gordon Henriksence224772008-01-07 01:30:38 +00005625 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
Chris Lattnerd5e93c02006-09-07 01:59:34 +00005626
Nate Begemanf15485a2006-03-27 01:32:24 +00005627 // Set the current basic block to the mbb we wish to insert the code into
5628 BB = SwitchCases[i].ThisBB;
5629 SDL.setCurrentBasicBlock(BB);
Chris Lattnerd5e93c02006-09-07 01:59:34 +00005630
Nate Begemanf15485a2006-03-27 01:32:24 +00005631 // Emit the code
5632 SDL.visitSwitchCase(SwitchCases[i]);
5633 SDAG.setRoot(SDL.getRoot());
5634 CodeGenAndEmitDAG(SDAG);
Chris Lattnerd5e93c02006-09-07 01:59:34 +00005635
5636 // Handle any PHI nodes in successors of this chunk, as if we were coming
5637 // from the original BB before switch expansion. Note that PHI nodes can
5638 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5639 // handle them the right number of times.
Chris Lattner57ab6592006-10-24 17:57:59 +00005640 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
Chris Lattnerd5e93c02006-09-07 01:59:34 +00005641 for (MachineBasicBlock::iterator Phi = BB->begin();
5642 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5643 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5644 for (unsigned pn = 0; ; ++pn) {
5645 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5646 if (PHINodesToUpdate[pn].first == Phi) {
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00005647 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5648 second, false));
5649 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
Chris Lattnerd5e93c02006-09-07 01:59:34 +00005650 break;
5651 }
5652 }
Nate Begemanf15485a2006-03-27 01:32:24 +00005653 }
Chris Lattnerd5e93c02006-09-07 01:59:34 +00005654
5655 // Don't process RHS if same block as LHS.
Chris Lattner57ab6592006-10-24 17:57:59 +00005656 if (BB == SwitchCases[i].FalseBB)
5657 SwitchCases[i].FalseBB = 0;
Chris Lattnerd5e93c02006-09-07 01:59:34 +00005658
5659 // If we haven't handled the RHS, do so now. Otherwise, we're done.
Chris Lattner24525952006-10-24 18:07:37 +00005660 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
Chris Lattner57ab6592006-10-24 17:57:59 +00005661 SwitchCases[i].FalseBB = 0;
Nate Begemanf15485a2006-03-27 01:32:24 +00005662 }
Chris Lattner57ab6592006-10-24 17:57:59 +00005663 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
Chris Lattnera33ef482005-03-30 01:10:47 +00005664 }
Chris Lattner1c08c712005-01-07 07:47:53 +00005665}
Evan Chenga9c20912006-01-21 02:32:06 +00005666
Jim Laskey13ec7022006-08-01 14:21:23 +00005667
Dan Gohman5e843682008-07-14 18:19:29 +00005668/// Schedule - Pick a safe ordering for instructions for each
Evan Chenga9c20912006-01-21 02:32:06 +00005669/// target node in the graph.
Dan Gohman5e843682008-07-14 18:19:29 +00005670///
5671ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
Jim Laskeyeb577ba2006-08-02 12:30:23 +00005672 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
Jim Laskey13ec7022006-08-01 14:21:23 +00005673
5674 if (!Ctor) {
Jim Laskeyeb577ba2006-08-02 12:30:23 +00005675 Ctor = ISHeuristic;
Jim Laskey9373beb2006-08-01 19:14:14 +00005676 RegisterScheduler::setDefault(Ctor);
Evan Cheng4ef10862006-01-23 07:01:07 +00005677 }
Jim Laskey13ec7022006-08-01 14:21:23 +00005678
Dan Gohman5e843682008-07-14 18:19:29 +00005679 ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel);
5680 Scheduler->Run();
Dan Gohman3e1a7ae2007-08-28 20:32:58 +00005681
Dan Gohman5e843682008-07-14 18:19:29 +00005682 return Scheduler;
Evan Chenga9c20912006-01-21 02:32:06 +00005683}
Chris Lattner0e43f2b2006-02-24 02:13:54 +00005684
Chris Lattner03fc53c2006-03-06 00:22:00 +00005685
Jim Laskey9ff542f2006-08-01 18:29:48 +00005686HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5687 return new HazardRecognizer();
5688}
5689
Chris Lattner75548062006-10-11 03:58:02 +00005690//===----------------------------------------------------------------------===//
5691// Helper functions used by the generated instruction selector.
5692//===----------------------------------------------------------------------===//
5693// Calls to these methods are generated by tblgen.
5694
5695/// CheckAndMask - The isel is trying to match something like (and X, 255). If
5696/// the dag combiner simplified the 255, we still want to match. RHS is the
5697/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5698/// specified in the .td file (e.g. 255).
Dan Gohman475871a2008-07-27 21:46:04 +00005699bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
Dan Gohmandc9b3d02007-07-24 23:00:27 +00005700 int64_t DesiredMaskS) const {
Dan Gohman2e68b6f2008-02-25 21:11:39 +00005701 const APInt &ActualMask = RHS->getAPIntValue();
5702 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
Chris Lattner75548062006-10-11 03:58:02 +00005703
5704 // If the actual mask exactly matches, success!
5705 if (ActualMask == DesiredMask)
5706 return true;
5707
5708 // If the actual AND mask is allowing unallowed bits, this doesn't match.
Dan Gohman2e68b6f2008-02-25 21:11:39 +00005709 if (ActualMask.intersects(~DesiredMask))
Chris Lattner75548062006-10-11 03:58:02 +00005710 return false;
5711
5712 // Otherwise, the DAG Combiner may have proven that the value coming in is
5713 // either already zero or is not demanded. Check for known zero input bits.
Dan Gohman2e68b6f2008-02-25 21:11:39 +00005714 APInt NeededMask = DesiredMask & ~ActualMask;
Dan Gohmanea859be2007-06-22 14:59:07 +00005715 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
Chris Lattner75548062006-10-11 03:58:02 +00005716 return true;
5717
5718 // TODO: check to see if missing bits are just not demanded.
5719
5720 // Otherwise, this pattern doesn't match.
5721 return false;
5722}
5723
5724/// CheckOrMask - The isel is trying to match something like (or X, 255). If
5725/// the dag combiner simplified the 255, we still want to match. RHS is the
5726/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5727/// specified in the .td file (e.g. 255).
Dan Gohman475871a2008-07-27 21:46:04 +00005728bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
Dan Gohman2e68b6f2008-02-25 21:11:39 +00005729 int64_t DesiredMaskS) const {
5730 const APInt &ActualMask = RHS->getAPIntValue();
5731 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
Chris Lattner75548062006-10-11 03:58:02 +00005732
5733 // If the actual mask exactly matches, success!
5734 if (ActualMask == DesiredMask)
5735 return true;
5736
5737 // If the actual AND mask is allowing unallowed bits, this doesn't match.
Dan Gohman2e68b6f2008-02-25 21:11:39 +00005738 if (ActualMask.intersects(~DesiredMask))
Chris Lattner75548062006-10-11 03:58:02 +00005739 return false;
5740
5741 // Otherwise, the DAG Combiner may have proven that the value coming in is
5742 // either already zero or is not demanded. Check for known zero input bits.
Dan Gohman2e68b6f2008-02-25 21:11:39 +00005743 APInt NeededMask = DesiredMask & ~ActualMask;
Chris Lattner75548062006-10-11 03:58:02 +00005744
Dan Gohman2e68b6f2008-02-25 21:11:39 +00005745 APInt KnownZero, KnownOne;
Dan Gohmanea859be2007-06-22 14:59:07 +00005746 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
Chris Lattner75548062006-10-11 03:58:02 +00005747
5748 // If all the missing bits in the or are already known to be set, match!
5749 if ((NeededMask & KnownOne) == NeededMask)
5750 return true;
5751
5752 // TODO: check to see if missing bits are just not demanded.
5753
5754 // Otherwise, this pattern doesn't match.
5755 return false;
5756}
5757
Jim Laskey9ff542f2006-08-01 18:29:48 +00005758
Chris Lattner0e43f2b2006-02-24 02:13:54 +00005759/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5760/// by tblgen. Others should not call it.
5761void SelectionDAGISel::
Dan Gohman475871a2008-07-27 21:46:04 +00005762SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SelectionDAG &DAG) {
5763 std::vector<SDValue> InOps;
Chris Lattner0e43f2b2006-02-24 02:13:54 +00005764 std::swap(InOps, Ops);
5765
5766 Ops.push_back(InOps[0]); // input chain.
5767 Ops.push_back(InOps[1]); // input asm string.
5768
Chris Lattner0e43f2b2006-02-24 02:13:54 +00005769 unsigned i = 2, e = InOps.size();
5770 if (InOps[e-1].getValueType() == MVT::Flag)
5771 --e; // Don't process a flag operand if it is here.
5772
5773 while (i != e) {
5774 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5775 if ((Flags & 7) != 4 /*MEM*/) {
5776 // Just skip over this operand, copying the operands verbatim.
5777 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5778 i += (Flags >> 3) + 1;
5779 } else {
5780 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5781 // Otherwise, this is a memory operand. Ask the target to select it.
Dan Gohman475871a2008-07-27 21:46:04 +00005782 std::vector<SDValue> SelOps;
Chris Lattner0e43f2b2006-02-24 02:13:54 +00005783 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
Bill Wendling832171c2006-12-07 20:04:42 +00005784 cerr << "Could not match memory address. Inline asm failure!\n";
Chris Lattner0e43f2b2006-02-24 02:13:54 +00005785 exit(1);
5786 }
5787
5788 // Add this to the output node.
Duncan Sands83ec4b62008-06-06 12:08:01 +00005789 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
Chris Lattner36d43962006-12-16 21:14:48 +00005790 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
Chris Lattner4b993b12007-04-09 00:33:58 +00005791 IntPtrTy));
Chris Lattner0e43f2b2006-02-24 02:13:54 +00005792 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5793 i += 2;
5794 }
5795 }
5796
5797 // Add the flag input back if present.
5798 if (e != InOps.size())
5799 Ops.push_back(InOps.back());
5800}
Devang Patel794fd752007-05-01 21:15:47 +00005801
Devang Patel19974732007-05-03 01:11:54 +00005802char SelectionDAGISel::ID = 0;