Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1 | |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 9 | // |
| 10 | // This file describes the X86 instruction set, defining the instructions, and |
| 11 | // properties of the instructions which are needed for code generation, machine |
| 12 | // code emission, and analysis. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 16 | //===----------------------------------------------------------------------===// |
| 17 | // X86 specific DAG Nodes. |
| 18 | // |
| 19 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 20 | def SDTIntShiftDOp: SDTypeProfile<1, 3, |
| 21 | [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, |
| 22 | SDTCisInt<0>, SDTCisInt<3>]>; |
| 23 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 24 | def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 25 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 26 | def SDTX86Cmov : SDTypeProfile<1, 4, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 27 | [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, |
| 28 | SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 29 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 30 | // Unary and binary operator instructions that set EFLAGS as a side-effect. |
| 31 | def SDTUnaryArithWithFlags : SDTypeProfile<1, 1, |
| 32 | [SDTCisInt<0>]>; |
| 33 | def SDTBinaryArithWithFlags : SDTypeProfile<1, 2, |
| 34 | [SDTCisSameAs<0, 1>, |
| 35 | SDTCisSameAs<0, 2>, |
| 36 | SDTCisInt<0>]>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 37 | def SDTX86BrCond : SDTypeProfile<0, 3, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 38 | [SDTCisVT<0, OtherVT>, |
| 39 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 40 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 41 | def SDTX86SetCC : SDTypeProfile<1, 2, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 42 | [SDTCisVT<0, i8>, |
| 43 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | 2e489c4 | 2009-12-16 00:53:11 +0000 | [diff] [blame] | 44 | def SDTX86SetCC_C : SDTypeProfile<1, 2, |
| 45 | [SDTCisInt<0>, |
| 46 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 47 | |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 48 | def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, |
| 49 | SDTCisVT<2, i8>]>; |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 50 | def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 51 | |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 52 | def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, |
| 53 | SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 54 | def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 55 | |
Sean Callanan | 1c97ceb | 2009-06-23 23:25:37 +0000 | [diff] [blame] | 56 | def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; |
| 57 | def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, |
| 58 | SDTCisVT<1, i32>]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 59 | |
Dan Gohman | d35121a | 2008-05-29 19:57:41 +0000 | [diff] [blame] | 60 | def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 61 | |
Dan Gohman | d6708ea | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 62 | def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, |
| 63 | SDTCisVT<1, iPTR>, |
| 64 | SDTCisVT<2, iPTR>]>; |
| 65 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 66 | def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; |
| 67 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 68 | def SDTX86RdTsc : SDTypeProfile<0, 0, []>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 69 | |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 70 | def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; |
| 71 | |
Rafael Espindola | 2ee3db3 | 2009-04-17 14:35:58 +0000 | [diff] [blame] | 72 | def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 73 | |
Rafael Espindola | 094fad3 | 2009-04-08 21:14:34 +0000 | [diff] [blame] | 74 | def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 75 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 76 | def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
| 77 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 78 | def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; |
| 79 | |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 80 | def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>; |
| 81 | def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 82 | def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; |
| 83 | def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 84 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 85 | def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 86 | |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 87 | def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; |
| 88 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 89 | def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 90 | def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 91 | [SDNPHasChain]>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 92 | def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; |
Evan Cheng | 2e489c4 | 2009-12-16 00:53:11 +0000 | [diff] [blame] | 93 | def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 94 | |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 95 | def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, |
| 96 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
| 97 | SDNPMayLoad]>; |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 98 | def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8, |
| 99 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
| 100 | SDNPMayLoad]>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 101 | def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary, |
| 102 | [SDNPHasChain, SDNPMayStore, |
| 103 | SDNPMayLoad, SDNPMemOperand]>; |
| 104 | def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary, |
| 105 | [SDNPHasChain, SDNPMayStore, |
| 106 | SDNPMayLoad, SDNPMemOperand]>; |
| 107 | def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary, |
| 108 | [SDNPHasChain, SDNPMayStore, |
| 109 | SDNPMayLoad, SDNPMemOperand]>; |
| 110 | def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary, |
| 111 | [SDNPHasChain, SDNPMayStore, |
| 112 | SDNPMayLoad, SDNPMemOperand]>; |
| 113 | def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary, |
| 114 | [SDNPHasChain, SDNPMayStore, |
| 115 | SDNPMayLoad, SDNPMemOperand]>; |
| 116 | def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary, |
| 117 | [SDNPHasChain, SDNPMayStore, |
| 118 | SDNPMayLoad, SDNPMemOperand]>; |
Dale Johannesen | 880ae36 | 2008-10-03 22:25:52 +0000 | [diff] [blame] | 119 | def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary, |
| 120 | [SDNPHasChain, SDNPMayStore, |
| 121 | SDNPMayLoad, SDNPMemOperand]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 122 | def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, |
| 123 | [SDNPHasChain, SDNPOptInFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 124 | |
Dan Gohman | d6708ea | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 125 | def X86vastart_save_xmm_regs : |
| 126 | SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", |
| 127 | SDT_X86VASTART_SAVE_XMM_REGS, |
| 128 | [SDNPHasChain]>; |
| 129 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 130 | def X86callseq_start : |
| 131 | SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, |
Evan Cheng | bb7b844 | 2006-08-11 09:03:33 +0000 | [diff] [blame] | 132 | [SDNPHasChain, SDNPOutFlag]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 133 | def X86callseq_end : |
| 134 | SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 135 | [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 136 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 137 | def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, |
| 138 | [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 139 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 140 | def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, |
Chris Lattner | 9b37aaf | 2008-01-10 05:12:37 +0000 | [diff] [blame] | 141 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 142 | def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, |
Chris Lattner | 9b37aaf | 2008-01-10 05:12:37 +0000 | [diff] [blame] | 143 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
| 144 | SDNPMayLoad]>; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 145 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 146 | def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc, |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 147 | [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 148 | |
Evan Cheng | 0085a28 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 149 | def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; |
| 150 | def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 151 | |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 152 | def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, |
Anton Korobeynikov | 6625eff | 2008-05-04 21:36:32 +0000 | [diff] [blame] | 153 | [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; |
Rafael Espindola | 094fad3 | 2009-04-08 21:14:34 +0000 | [diff] [blame] | 154 | def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress", |
| 155 | SDT_X86SegmentBaseAddress, []>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 156 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 157 | def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, |
| 158 | [SDNPHasChain]>; |
| 159 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 160 | def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, |
| 161 | [SDNPHasChain, SDNPOptInFlag]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 162 | |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 163 | def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 164 | [SDNPCommutative]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 165 | def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 166 | def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 167 | [SDNPCommutative]>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 168 | def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 169 | [SDNPCommutative]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 170 | def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; |
| 171 | def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 172 | def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 173 | [SDNPCommutative]>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 174 | def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 175 | [SDNPCommutative]>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 176 | def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 177 | [SDNPCommutative]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 178 | |
Evan Cheng | 73f24c9 | 2009-03-30 21:36:47 +0000 | [diff] [blame] | 179 | def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; |
| 180 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 181 | //===----------------------------------------------------------------------===// |
| 182 | // X86 Operand Definitions. |
| 183 | // |
| 184 | |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 185 | // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for |
| 186 | // the index operand of an address, to conform to x86 encoding restrictions. |
| 187 | def ptr_rc_nosp : PointerLikeRegClass<1>; |
Chris Lattner | 7680e73 | 2009-06-20 19:34:09 +0000 | [diff] [blame] | 188 | |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 189 | // *mem - Operand definitions for the funky X86 addressing mode operands. |
| 190 | // |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 191 | def X86MemAsmOperand : AsmOperandClass { |
| 192 | let Name = "Mem"; |
Daniel Dunbar | 8e00117 | 2009-08-10 19:08:02 +0000 | [diff] [blame] | 193 | let SuperClass = ?; |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 194 | } |
Daniel Dunbar | ec2b1f1 | 2010-01-30 00:24:00 +0000 | [diff] [blame] | 195 | def X86NoSegMemAsmOperand : AsmOperandClass { |
| 196 | let Name = "NoSegMem"; |
| 197 | let SuperClass = X86MemAsmOperand; |
| 198 | } |
Evan Cheng | af78ef5 | 2006-05-17 21:21:41 +0000 | [diff] [blame] | 199 | class X86MemOperand<string printMethod> : Operand<iPTR> { |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 200 | let PrintMethod = printMethod; |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 201 | let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 202 | let ParserMatchClass = X86MemAsmOperand; |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 203 | } |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 204 | |
Sean Callanan | 9947bbb | 2009-09-03 00:04:47 +0000 | [diff] [blame] | 205 | def opaque32mem : X86MemOperand<"printopaquemem">; |
| 206 | def opaque48mem : X86MemOperand<"printopaquemem">; |
| 207 | def opaque80mem : X86MemOperand<"printopaquemem">; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 208 | def opaque512mem : X86MemOperand<"printopaquemem">; |
| 209 | |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 210 | def i8mem : X86MemOperand<"printi8mem">; |
| 211 | def i16mem : X86MemOperand<"printi16mem">; |
| 212 | def i32mem : X86MemOperand<"printi32mem">; |
| 213 | def i64mem : X86MemOperand<"printi64mem">; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 214 | def i128mem : X86MemOperand<"printi128mem">; |
Chris Lattner | e895c61 | 2009-09-20 07:17:49 +0000 | [diff] [blame] | 215 | //def i256mem : X86MemOperand<"printi256mem">; |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 216 | def f32mem : X86MemOperand<"printf32mem">; |
| 217 | def f64mem : X86MemOperand<"printf64mem">; |
Dale Johannesen | 59a5873 | 2007-08-05 18:49:15 +0000 | [diff] [blame] | 218 | def f80mem : X86MemOperand<"printf80mem">; |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 219 | def f128mem : X86MemOperand<"printf128mem">; |
Chris Lattner | e895c61 | 2009-09-20 07:17:49 +0000 | [diff] [blame] | 220 | //def f256mem : X86MemOperand<"printf256mem">; |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 221 | |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 222 | // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of |
| 223 | // plain GR64, so that it doesn't potentially require a REX prefix. |
| 224 | def i8mem_NOREX : Operand<i64> { |
| 225 | let PrintMethod = "printi8mem"; |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 226 | let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm); |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 227 | let ParserMatchClass = X86MemAsmOperand; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 228 | } |
| 229 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 230 | def lea32mem : Operand<i32> { |
Rafael Espindola | 094fad3 | 2009-04-08 21:14:34 +0000 | [diff] [blame] | 231 | let PrintMethod = "printlea32mem"; |
Dan Gohman | 74f6f9a | 2009-08-05 17:40:24 +0000 | [diff] [blame] | 232 | let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm); |
Daniel Dunbar | ec2b1f1 | 2010-01-30 00:24:00 +0000 | [diff] [blame] | 233 | let ParserMatchClass = X86NoSegMemAsmOperand; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 234 | } |
| 235 | |
Daniel Dunbar | 728e5eb | 2010-01-30 00:24:12 +0000 | [diff] [blame^] | 236 | let PrintMethod = "print_pcrel_imm" in { |
| 237 | def i32imm_pcrel : Operand<i32>; |
| 238 | |
| 239 | def offset8 : Operand<i64>; |
| 240 | def offset16 : Operand<i64>; |
| 241 | def offset32 : Operand<i64>; |
| 242 | def offset64 : Operand<i64>; |
| 243 | |
| 244 | // Branch targets have OtherVT type and print as pc-relative values. |
| 245 | def brtarget : Operand<OtherVT>; |
| 246 | def brtarget8 : Operand<OtherVT>; |
| 247 | |
| 248 | } |
| 249 | |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 250 | def SSECC : Operand<i8> { |
| 251 | let PrintMethod = "printSSECC"; |
| 252 | } |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 253 | |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 254 | def ImmSExt8AsmOperand : AsmOperandClass { |
| 255 | let Name = "ImmSExt8"; |
| 256 | let SuperClass = ImmAsmOperand; |
| 257 | } |
| 258 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 259 | // A couple of more descriptive operand definitions. |
| 260 | // 16-bits but only 8 bits are significant. |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 261 | def i16i8imm : Operand<i16> { |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 262 | let ParserMatchClass = ImmSExt8AsmOperand; |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 263 | } |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 264 | // 32-bits but only 8 bits are significant. |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 265 | def i32i8imm : Operand<i32> { |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 266 | let ParserMatchClass = ImmSExt8AsmOperand; |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 267 | } |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 268 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 269 | //===----------------------------------------------------------------------===// |
| 270 | // X86 Complex Pattern Definitions. |
| 271 | // |
| 272 | |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 273 | // Define X86 specific addressing mode. |
Rafael Espindola | 094fad3 | 2009-04-08 21:14:34 +0000 | [diff] [blame] | 274 | def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 275 | def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr", |
Dan Gohman | a98634b | 2009-08-02 16:09:17 +0000 | [diff] [blame] | 276 | [add, sub, mul, X86mul_imm, shl, or, frameindex], |
| 277 | []>; |
Chris Lattner | 5c0b16d | 2009-06-20 20:38:48 +0000 | [diff] [blame] | 278 | def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr", |
| 279 | [tglobaltlsaddr], []>; |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 280 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 281 | //===----------------------------------------------------------------------===// |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 282 | // X86 Instruction Predicate Definitions. |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 283 | def HasMMX : Predicate<"Subtarget->hasMMX()">; |
| 284 | def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; |
| 285 | def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; |
| 286 | def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; |
Bill Wendling | bb1ee05 | 2007-04-10 22:10:25 +0000 | [diff] [blame] | 287 | def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 288 | def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; |
| 289 | def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; |
David Greene | 343dadb | 2009-06-26 22:46:54 +0000 | [diff] [blame] | 290 | def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; |
| 291 | def HasAVX : Predicate<"Subtarget->hasAVX()">; |
| 292 | def HasFMA3 : Predicate<"Subtarget->hasFMA3()">; |
| 293 | def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 294 | def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; |
| 295 | def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 296 | def In32BitMode : Predicate<"!Subtarget->is64Bit()">; |
| 297 | def In64BitMode : Predicate<"Subtarget->is64Bit()">; |
Anton Korobeynikov | cf6b739 | 2009-08-03 08:12:53 +0000 | [diff] [blame] | 298 | def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; |
| 299 | def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; |
Anton Korobeynikov | d7697d0 | 2009-08-06 11:23:24 +0000 | [diff] [blame] | 300 | def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; |
| 301 | def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; |
| 302 | def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&" |
Anton Korobeynikov | 186fa1d | 2009-08-06 09:11:19 +0000 | [diff] [blame] | 303 | "TM.getCodeModel() != CodeModel::Kernel">; |
Anton Korobeynikov | d7697d0 | 2009-08-06 11:23:24 +0000 | [diff] [blame] | 304 | def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" |
| 305 | "TM.getCodeModel() == CodeModel::Kernel">; |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 306 | def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; |
Evan Cheng | b1f4981 | 2009-12-22 17:47:23 +0000 | [diff] [blame] | 307 | def OptForSize : Predicate<"OptForSize">; |
Evan Cheng | b7a75a5 | 2008-09-26 23:41:32 +0000 | [diff] [blame] | 308 | def OptForSpeed : Predicate<"!OptForSize">; |
Evan Cheng | ccb6976 | 2009-01-02 05:35:45 +0000 | [diff] [blame] | 309 | def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; |
Evan Cheng | d7f666a | 2009-05-20 04:53:57 +0000 | [diff] [blame] | 310 | def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 311 | |
| 312 | //===----------------------------------------------------------------------===// |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 313 | // X86 Instruction Format Definitions. |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 314 | // |
| 315 | |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 316 | include "X86InstrFormats.td" |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 317 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 318 | //===----------------------------------------------------------------------===// |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 319 | // Pattern fragments... |
| 320 | // |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 321 | |
| 322 | // X86 specific condition code. These correspond to CondCode in |
Nate Begeman | 9a22530 | 2007-05-06 04:00:55 +0000 | [diff] [blame] | 323 | // X86InstrInfo.h. They must be kept in synch. |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 324 | def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE |
| 325 | def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC |
| 326 | def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C |
| 327 | def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA |
| 328 | def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z |
| 329 | def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE |
| 330 | def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL |
| 331 | def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE |
| 332 | def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG |
| 333 | def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 334 | def X86_COND_NO : PatLeaf<(i8 10)>; |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 335 | def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 336 | def X86_COND_NS : PatLeaf<(i8 12)>; |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 337 | def X86_COND_O : PatLeaf<(i8 13)>; |
| 338 | def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE |
| 339 | def X86_COND_S : PatLeaf<(i8 15)>; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 340 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 341 | def i16immSExt8 : PatLeaf<(i16 imm), [{ |
| 342 | // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 343 | // sign extended field. |
Dan Gohman | f5aeb1a | 2008-09-12 16:56:44 +0000 | [diff] [blame] | 344 | return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue(); |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 345 | }]>; |
| 346 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 347 | def i32immSExt8 : PatLeaf<(i32 imm), [{ |
| 348 | // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 349 | // sign extended field. |
Dan Gohman | f5aeb1a | 2008-09-12 16:56:44 +0000 | [diff] [blame] | 350 | return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue(); |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 351 | }]>; |
| 352 | |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 353 | // Helper fragments for loads. |
Evan Cheng | b656443 | 2008-05-13 18:59:59 +0000 | [diff] [blame] | 354 | // It's always safe to treat a anyext i16 load as a i32 load if the i16 is |
| 355 | // known to be 32-bit aligned or better. Ditto for i8 to i16. |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 356 | def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 357 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 358 | if (const Value *Src = LD->getSrcValue()) |
| 359 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 360 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 361 | return false; |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 362 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 363 | if (ExtType == ISD::NON_EXTLOAD) |
| 364 | return true; |
| 365 | if (ExtType == ISD::EXTLOAD) |
| 366 | return LD->getAlignment() >= 2 && !LD->isVolatile(); |
Evan Cheng | fa7fd33 | 2008-05-13 00:54:02 +0000 | [diff] [blame] | 367 | return false; |
| 368 | }]>; |
| 369 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 370 | def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), |
| 371 | [{ |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 372 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 373 | if (const Value *Src = LD->getSrcValue()) |
| 374 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 375 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 376 | return false; |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 377 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 378 | if (ExtType == ISD::EXTLOAD) |
| 379 | return LD->getAlignment() >= 2 && !LD->isVolatile(); |
| 380 | return false; |
| 381 | }]>; |
| 382 | |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 383 | def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 384 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 385 | if (const Value *Src = LD->getSrcValue()) |
| 386 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 387 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 388 | return false; |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 389 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 390 | if (ExtType == ISD::NON_EXTLOAD) |
| 391 | return true; |
| 392 | if (ExtType == ISD::EXTLOAD) |
| 393 | return LD->getAlignment() >= 4 && !LD->isVolatile(); |
Evan Cheng | fa7fd33 | 2008-05-13 00:54:02 +0000 | [diff] [blame] | 394 | return false; |
| 395 | }]>; |
| 396 | |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 397 | def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ |
Evan Cheng | d47e0b6 | 2008-09-29 17:26:18 +0000 | [diff] [blame] | 398 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 399 | if (const Value *Src = LD->getSrcValue()) |
| 400 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 401 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 402 | return false; |
Evan Cheng | d47e0b6 | 2008-09-29 17:26:18 +0000 | [diff] [blame] | 403 | if (LD->isVolatile()) |
| 404 | return false; |
Evan Cheng | d47e0b6 | 2008-09-29 17:26:18 +0000 | [diff] [blame] | 405 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 406 | if (ExtType == ISD::NON_EXTLOAD) |
| 407 | return true; |
| 408 | if (ExtType == ISD::EXTLOAD) |
| 409 | return LD->getAlignment() >= 4; |
| 410 | return false; |
| 411 | }]>; |
| 412 | |
Nate Begeman | 51a0437 | 2009-01-26 01:24:32 +0000 | [diff] [blame] | 413 | def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 414 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 415 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
| 416 | return PT->getAddressSpace() == 256; |
Nate Begeman | 51a0437 | 2009-01-26 01:24:32 +0000 | [diff] [blame] | 417 | return false; |
| 418 | }]>; |
| 419 | |
Chris Lattner | 1777d0c | 2009-05-05 18:52:19 +0000 | [diff] [blame] | 420 | def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ |
| 421 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 422 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
| 423 | return PT->getAddressSpace() == 257; |
| 424 | return false; |
| 425 | }]>; |
| 426 | |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 427 | def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{ |
| 428 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 429 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 430 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 431 | return false; |
| 432 | return true; |
| 433 | }]>; |
| 434 | def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{ |
| 435 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 436 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 437 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 438 | return false; |
| 439 | return true; |
| 440 | }]>; |
Evan Cheng | 06a8aa1 | 2006-03-17 19:55:52 +0000 | [diff] [blame] | 441 | |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 442 | def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{ |
| 443 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 444 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 445 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 446 | return false; |
| 447 | return true; |
| 448 | }]>; |
| 449 | def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{ |
| 450 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 451 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 452 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 453 | return false; |
| 454 | return true; |
| 455 | }]>; |
| 456 | def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{ |
| 457 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 458 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 459 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 460 | return false; |
| 461 | return true; |
| 462 | }]>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 463 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 464 | def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; |
| 465 | def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; |
| 466 | def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 467 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 468 | def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; |
| 469 | def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; |
| 470 | def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; |
| 471 | def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; |
| 472 | def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; |
| 473 | def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 474 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 475 | def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; |
| 476 | def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; |
| 477 | def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; |
| 478 | def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; |
| 479 | def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; |
| 480 | def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 481 | |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 482 | |
| 483 | // An 'and' node with a single use. |
| 484 | def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ |
Evan Cheng | 07b7ea1 | 2008-03-04 00:40:35 +0000 | [diff] [blame] | 485 | return N->hasOneUse(); |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 486 | }]>; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 487 | // An 'srl' node with a single use. |
| 488 | def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ |
| 489 | return N->hasOneUse(); |
| 490 | }]>; |
| 491 | // An 'trunc' node with a single use. |
| 492 | def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ |
| 493 | return N->hasOneUse(); |
| 494 | }]>; |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 495 | |
Evan Cheng | 4b0345b | 2010-01-11 17:03:47 +0000 | [diff] [blame] | 496 | // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. |
| 497 | def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ |
| 498 | if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) |
| 499 | return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); |
Evan Cheng | 199c424 | 2010-01-11 22:03:29 +0000 | [diff] [blame] | 500 | else { |
| 501 | unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); |
| 502 | APInt Mask = APInt::getAllOnesValue(BitWidth); |
| 503 | APInt KnownZero0, KnownOne0; |
| 504 | CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0); |
| 505 | APInt KnownZero1, KnownOne1; |
| 506 | CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0); |
| 507 | return (~KnownZero0 & ~KnownZero1) == 0; |
| 508 | } |
Evan Cheng | 4b0345b | 2010-01-11 17:03:47 +0000 | [diff] [blame] | 509 | }]>; |
Evan Cheng | 4b0345b | 2010-01-11 17:03:47 +0000 | [diff] [blame] | 510 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 511 | // 'shld' and 'shrd' instruction patterns. Note that even though these have |
| 512 | // the srl and shl in their patterns, the C++ code must still check for them, |
| 513 | // because predicates are tested before children nodes are explored. |
| 514 | |
| 515 | def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2), |
| 516 | (or (srl node:$src1, node:$amt1), |
| 517 | (shl node:$src2, node:$amt2)), [{ |
| 518 | assert(N->getOpcode() == ISD::OR); |
| 519 | return N->getOperand(0).getOpcode() == ISD::SRL && |
| 520 | N->getOperand(1).getOpcode() == ISD::SHL && |
| 521 | isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) && |
| 522 | isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) && |
| 523 | N->getOperand(0).getConstantOperandVal(1) == |
| 524 | N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1); |
| 525 | }]>; |
| 526 | |
| 527 | def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2), |
| 528 | (or (shl node:$src1, node:$amt1), |
| 529 | (srl node:$src2, node:$amt2)), [{ |
| 530 | assert(N->getOpcode() == ISD::OR); |
| 531 | return N->getOperand(0).getOpcode() == ISD::SHL && |
| 532 | N->getOperand(1).getOpcode() == ISD::SRL && |
| 533 | isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) && |
| 534 | isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) && |
| 535 | N->getOperand(0).getConstantOperandVal(1) == |
| 536 | N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1); |
| 537 | }]>; |
| 538 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 539 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 540 | // Instruction list... |
| 541 | // |
| 542 | |
Chris Lattner | f18c074 | 2006-10-12 17:42:56 +0000 | [diff] [blame] | 543 | // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into |
| 544 | // a stack adjustment and the codegen must know that they may modify the stack |
| 545 | // pointer before prolog-epilog rewriting occurs. |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 546 | // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become |
| 547 | // sub / add which can clobber EFLAGS. |
Evan Cheng | 8decf6b | 2007-09-28 01:19:48 +0000 | [diff] [blame] | 548 | let Defs = [ESP, EFLAGS], Uses = [ESP] in { |
Dan Gohman | 6d4b052 | 2008-10-01 18:28:06 +0000 | [diff] [blame] | 549 | def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt), |
| 550 | "#ADJCALLSTACKDOWN", |
Chris Lattner | e563bbc | 2008-10-11 22:08:30 +0000 | [diff] [blame] | 551 | [(X86callseq_start timm:$amt)]>, |
Dan Gohman | 6d4b052 | 2008-10-01 18:28:06 +0000 | [diff] [blame] | 552 | Requires<[In32BitMode]>; |
| 553 | def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), |
| 554 | "#ADJCALLSTACKUP", |
Chris Lattner | e563bbc | 2008-10-11 22:08:30 +0000 | [diff] [blame] | 555 | [(X86callseq_end timm:$amt1, timm:$amt2)]>, |
Dan Gohman | 6d4b052 | 2008-10-01 18:28:06 +0000 | [diff] [blame] | 556 | Requires<[In32BitMode]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 557 | } |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 558 | |
Dan Gohman | d6708ea | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 559 | // x86-64 va_start lowering magic. |
Dan Gohman | 533297b | 2009-10-29 18:10:34 +0000 | [diff] [blame] | 560 | let usesCustomInserter = 1 in |
Dan Gohman | d6708ea | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 561 | def VASTART_SAVE_XMM_REGS : I<0, Pseudo, |
| 562 | (outs), |
| 563 | (ins GR8:$al, |
| 564 | i64imm:$regsavefi, i64imm:$offset, |
| 565 | variable_ops), |
| 566 | "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset", |
| 567 | [(X86vastart_save_xmm_regs GR8:$al, |
| 568 | imm:$regsavefi, |
| 569 | imm:$offset)]>; |
| 570 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 571 | // Nop |
Sean Callanan | 74e5210 | 2009-07-23 23:39:34 +0000 | [diff] [blame] | 572 | let neverHasSideEffects = 1 in { |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 573 | def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 574 | def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero), |
| 575 | "nop{w}\t$zero", []>, TB, OpSize; |
Sean Callanan | 74e5210 | 2009-07-23 23:39:34 +0000 | [diff] [blame] | 576 | def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 577 | "nop{l}\t$zero", []>, TB; |
Sean Callanan | 74e5210 | 2009-07-23 23:39:34 +0000 | [diff] [blame] | 578 | } |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 579 | |
Sean Callanan | 1c5cf1b | 2009-08-11 01:09:06 +0000 | [diff] [blame] | 580 | // Trap |
Dan Gohman | e94975e | 2009-11-11 18:07:16 +0000 | [diff] [blame] | 581 | def INT3 : I<0xcc, RawFrm, (outs), (ins), "int\t3", []>; |
Sean Callanan | 1c5cf1b | 2009-08-11 01:09:06 +0000 | [diff] [blame] | 582 | def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 583 | def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize; |
| 584 | def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>; |
Sean Callanan | 1c5cf1b | 2009-08-11 01:09:06 +0000 | [diff] [blame] | 585 | |
Chris Lattner | 71c7ace | 2009-09-20 07:32:00 +0000 | [diff] [blame] | 586 | // PIC base construction. This expands to code that looks like this: |
| 587 | // call $next_inst |
| 588 | // popl %destreg" |
Dan Gohman | 2662d55 | 2008-10-01 04:14:30 +0000 | [diff] [blame] | 589 | let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in |
Chris Lattner | b3c8547 | 2009-09-20 07:28:26 +0000 | [diff] [blame] | 590 | def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), |
Chris Lattner | 71c7ace | 2009-09-20 07:32:00 +0000 | [diff] [blame] | 591 | "", []>; |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 592 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 593 | //===----------------------------------------------------------------------===// |
| 594 | // Control Flow Instructions... |
| 595 | // |
| 596 | |
Chris Lattner | 1be4811 | 2005-05-13 17:56:48 +0000 | [diff] [blame] | 597 | // Return instructions. |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 598 | let isTerminator = 1, isReturn = 1, isBarrier = 1, |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 599 | hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in { |
Dan Gohman | e4c67cd | 2008-05-31 02:11:25 +0000 | [diff] [blame] | 600 | def RET : I <0xC3, RawFrm, (outs), (ins variable_ops), |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 601 | "ret", |
Dan Gohman | e4c67cd | 2008-05-31 02:11:25 +0000 | [diff] [blame] | 602 | [(X86retflag 0)]>; |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 603 | def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), |
| 604 | "ret\t$amt", |
Dan Gohman | 2f67df7 | 2009-09-03 17:18:51 +0000 | [diff] [blame] | 605 | [(X86retflag timm:$amt)]>; |
Sean Callanan | 356aed5 | 2009-09-15 23:37:51 +0000 | [diff] [blame] | 606 | def LRET : I <0xCB, RawFrm, (outs), (ins), |
| 607 | "lret", []>; |
| 608 | def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), |
| 609 | "lret\t$amt", []>; |
Evan Cheng | 171049d | 2005-12-23 22:14:32 +0000 | [diff] [blame] | 610 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 611 | |
| 612 | // All branches are RawFrm, Void, Branch, and Terminators |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 613 | let isBranch = 1, isTerminator = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 614 | class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> : |
| 615 | I<opcode, RawFrm, (outs), ins, asm, pattern>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 616 | |
Sean Callanan | 5292588 | 2009-07-22 01:05:20 +0000 | [diff] [blame] | 617 | let isBranch = 1, isBarrier = 1 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 618 | def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>; |
Sean Callanan | 5292588 | 2009-07-22 01:05:20 +0000 | [diff] [blame] | 619 | def JMP8 : IBr<0xEB, (ins brtarget8:$dst), "jmp\t$dst", []>; |
| 620 | } |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 621 | |
Owen Anderson | 20ab290 | 2007-11-12 07:39:39 +0000 | [diff] [blame] | 622 | // Indirect branches |
| 623 | let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 624 | def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 625 | [(brind GR32:$dst)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 626 | def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 627 | [(brind (loadi32 addr:$dst))]>; |
Sean Callanan | 76f14be | 2009-09-15 00:35:17 +0000 | [diff] [blame] | 628 | |
| 629 | def FARJMP16i : Iseg16<0xEA, RawFrm, (outs), |
| 630 | (ins i16imm:$seg, i16imm:$off), |
| 631 | "ljmp{w}\t$seg, $off", []>, OpSize; |
| 632 | def FARJMP32i : Iseg32<0xEA, RawFrm, (outs), |
| 633 | (ins i16imm:$seg, i32imm:$off), |
| 634 | "ljmp{l}\t$seg, $off", []>; |
| 635 | |
| 636 | def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst), |
Sean Callanan | 9947bbb | 2009-09-03 00:04:47 +0000 | [diff] [blame] | 637 | "ljmp{w}\t{*}$dst", []>, OpSize; |
Sean Callanan | 76f14be | 2009-09-15 00:35:17 +0000 | [diff] [blame] | 638 | def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst), |
Sean Callanan | 9947bbb | 2009-09-03 00:04:47 +0000 | [diff] [blame] | 639 | "ljmp{l}\t{*}$dst", []>; |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 640 | } |
| 641 | |
| 642 | // Conditional branches |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 643 | let Uses = [EFLAGS] in { |
Evan Cheng | 77159e3 | 2009-07-21 06:00:18 +0000 | [diff] [blame] | 644 | // Short conditional jumps |
| 645 | def JO8 : IBr<0x70, (ins brtarget8:$dst), "jo\t$dst", []>; |
| 646 | def JNO8 : IBr<0x71, (ins brtarget8:$dst), "jno\t$dst", []>; |
| 647 | def JB8 : IBr<0x72, (ins brtarget8:$dst), "jb\t$dst", []>; |
| 648 | def JAE8 : IBr<0x73, (ins brtarget8:$dst), "jae\t$dst", []>; |
| 649 | def JE8 : IBr<0x74, (ins brtarget8:$dst), "je\t$dst", []>; |
| 650 | def JNE8 : IBr<0x75, (ins brtarget8:$dst), "jne\t$dst", []>; |
| 651 | def JBE8 : IBr<0x76, (ins brtarget8:$dst), "jbe\t$dst", []>; |
| 652 | def JA8 : IBr<0x77, (ins brtarget8:$dst), "ja\t$dst", []>; |
| 653 | def JS8 : IBr<0x78, (ins brtarget8:$dst), "js\t$dst", []>; |
| 654 | def JNS8 : IBr<0x79, (ins brtarget8:$dst), "jns\t$dst", []>; |
| 655 | def JP8 : IBr<0x7A, (ins brtarget8:$dst), "jp\t$dst", []>; |
| 656 | def JNP8 : IBr<0x7B, (ins brtarget8:$dst), "jnp\t$dst", []>; |
| 657 | def JL8 : IBr<0x7C, (ins brtarget8:$dst), "jl\t$dst", []>; |
| 658 | def JGE8 : IBr<0x7D, (ins brtarget8:$dst), "jge\t$dst", []>; |
| 659 | def JLE8 : IBr<0x7E, (ins brtarget8:$dst), "jle\t$dst", []>; |
| 660 | def JG8 : IBr<0x7F, (ins brtarget8:$dst), "jg\t$dst", []>; |
| 661 | |
| 662 | def JCXZ8 : IBr<0xE3, (ins brtarget8:$dst), "jcxz\t$dst", []>; |
| 663 | |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 664 | def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 665 | [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 666 | def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 667 | [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 668 | def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 669 | [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 670 | def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 671 | [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 672 | def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 673 | [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 674 | def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 675 | [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 676 | |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 677 | def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 678 | [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 679 | def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 680 | [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 681 | def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 682 | [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 683 | def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 684 | [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 685 | |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 686 | def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 687 | [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 688 | def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 689 | [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 690 | def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 691 | [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 692 | def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 693 | [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 694 | def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 695 | [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 696 | def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 697 | [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB; |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 698 | } // Uses = [EFLAGS] |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 699 | |
Sean Callanan | 7e6d727 | 2009-09-16 21:50:07 +0000 | [diff] [blame] | 700 | // Loop instructions |
| 701 | |
| 702 | def LOOP : I<0xE2, RawFrm, (ins brtarget8:$dst), (outs), "loop\t$dst", []>; |
| 703 | def LOOPE : I<0xE1, RawFrm, (ins brtarget8:$dst), (outs), "loope\t$dst", []>; |
| 704 | def LOOPNE : I<0xE0, RawFrm, (ins brtarget8:$dst), (outs), "loopne\t$dst", []>; |
| 705 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 706 | //===----------------------------------------------------------------------===// |
| 707 | // Call Instructions... |
| 708 | // |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 709 | let isCall = 1 in |
Dan Gohman | 6d4b052 | 2008-10-01 18:28:06 +0000 | [diff] [blame] | 710 | // All calls clobber the non-callee saved registers. ESP is marked as |
| 711 | // a use to prevent stack-pointer assignments that appear immediately |
| 712 | // before calls from potentially appearing dead. Uses for argument |
| 713 | // registers are added manually. |
Nate Begeman | f63be7d | 2005-07-06 18:59:04 +0000 | [diff] [blame] | 714 | let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, |
Bill Wendling | 3f3a17d | 2007-04-25 21:31:48 +0000 | [diff] [blame] | 715 | MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, |
Evan Cheng | 109a562 | 2008-10-17 21:02:22 +0000 | [diff] [blame] | 716 | XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, |
| 717 | XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], |
Dan Gohman | 2662d55 | 2008-10-01 04:14:30 +0000 | [diff] [blame] | 718 | Uses = [ESP] in { |
Chris Lattner | 7680e73 | 2009-06-20 19:34:09 +0000 | [diff] [blame] | 719 | def CALLpcrel32 : Ii32<0xE8, RawFrm, |
| 720 | (outs), (ins i32imm_pcrel:$dst,variable_ops), |
| 721 | "call\t$dst", []>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 722 | def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 723 | "call\t{*}$dst", [(X86call GR32:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 724 | def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops), |
Dan Gohman | b410617 | 2008-05-29 21:50:34 +0000 | [diff] [blame] | 725 | "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>; |
Sean Callanan | 9947bbb | 2009-09-03 00:04:47 +0000 | [diff] [blame] | 726 | |
Sean Callanan | 76f14be | 2009-09-15 00:35:17 +0000 | [diff] [blame] | 727 | def FARCALL16i : Iseg16<0x9A, RawFrm, (outs), |
| 728 | (ins i16imm:$seg, i16imm:$off), |
| 729 | "lcall{w}\t$seg, $off", []>, OpSize; |
| 730 | def FARCALL32i : Iseg32<0x9A, RawFrm, (outs), |
| 731 | (ins i16imm:$seg, i32imm:$off), |
| 732 | "lcall{l}\t$seg, $off", []>; |
| 733 | |
| 734 | def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst), |
Sean Callanan | 9947bbb | 2009-09-03 00:04:47 +0000 | [diff] [blame] | 735 | "lcall{w}\t{*}$dst", []>, OpSize; |
Sean Callanan | 76f14be | 2009-09-15 00:35:17 +0000 | [diff] [blame] | 736 | def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst), |
Sean Callanan | 9947bbb | 2009-09-03 00:04:47 +0000 | [diff] [blame] | 737 | "lcall{l}\t{*}$dst", []>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 738 | } |
| 739 | |
Sean Callanan | 8d70854 | 2009-09-16 02:57:13 +0000 | [diff] [blame] | 740 | // Constructing a stack frame. |
| 741 | |
| 742 | def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl), |
| 743 | "enter\t$len, $lvl", []>; |
| 744 | |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 745 | // Tail call stuff. |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 746 | |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 747 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 748 | def TCRETURNdi : I<0, Pseudo, (outs), |
| 749 | (ins i32imm:$dst, i32imm:$offset, variable_ops), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 750 | "#TC_RETURN $dst $offset", |
| 751 | []>; |
| 752 | |
| 753 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 754 | def TCRETURNri : I<0, Pseudo, (outs), |
| 755 | (ins GR32:$dst, i32imm:$offset, variable_ops), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 756 | "#TC_RETURN $dst $offset", |
| 757 | []>; |
| 758 | |
| 759 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Chris Lattner | 7680e73 | 2009-06-20 19:34:09 +0000 | [diff] [blame] | 760 | def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst), "jmp\t$dst # TAILCALL", |
Evan Cheng | f10c17f | 2006-09-22 21:43:59 +0000 | [diff] [blame] | 761 | []>; |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 762 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 763 | def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), |
| 764 | "jmp{l}\t{*}$dst # TAILCALL", |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 765 | []>; |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 766 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 767 | def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 768 | "jmp\t{*}$dst # TAILCALL", []>; |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 769 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 770 | //===----------------------------------------------------------------------===// |
| 771 | // Miscellaneous Instructions... |
| 772 | // |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 773 | let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 774 | def LEAVE : I<0xC9, RawFrm, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 775 | (outs), (ins), "leave", []>; |
| 776 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 777 | def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
| 778 | "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS; |
| 779 | def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
| 780 | "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS; |
| 781 | def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
| 782 | "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS; |
| 783 | def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
| 784 | "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS; |
| 785 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 786 | let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in { |
Sean Callanan | 1f24e01 | 2009-09-10 18:29:13 +0000 | [diff] [blame] | 787 | let mayLoad = 1 in { |
| 788 | def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, |
| 789 | OpSize; |
| 790 | def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>; |
| 791 | def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, |
| 792 | OpSize; |
| 793 | def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>, |
| 794 | OpSize; |
| 795 | def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>; |
| 796 | def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>; |
| 797 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 798 | |
Sean Callanan | 1f24e01 | 2009-09-10 18:29:13 +0000 | [diff] [blame] | 799 | let mayStore = 1 in { |
| 800 | def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, |
| 801 | OpSize; |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 802 | def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>; |
Sean Callanan | 1f24e01 | 2009-09-10 18:29:13 +0000 | [diff] [blame] | 803 | def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, |
| 804 | OpSize; |
| 805 | def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>, |
| 806 | OpSize; |
| 807 | def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>; |
| 808 | def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>; |
| 809 | } |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 810 | } |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 811 | |
Bill Wendling | 453eb26 | 2009-06-15 19:39:04 +0000 | [diff] [blame] | 812 | let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in { |
| 813 | def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm), |
Bill Wendling | 927788c | 2009-06-15 20:59:31 +0000 | [diff] [blame] | 814 | "push{l}\t$imm", []>; |
Bill Wendling | 453eb26 | 2009-06-15 19:39:04 +0000 | [diff] [blame] | 815 | def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), |
Bill Wendling | 927788c | 2009-06-15 20:59:31 +0000 | [diff] [blame] | 816 | "push{l}\t$imm", []>; |
Bill Wendling | 453eb26 | 2009-06-15 19:39:04 +0000 | [diff] [blame] | 817 | def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), |
Bill Wendling | 927788c | 2009-06-15 20:59:31 +0000 | [diff] [blame] | 818 | "push{l}\t$imm", []>; |
Bill Wendling | 453eb26 | 2009-06-15 19:39:04 +0000 | [diff] [blame] | 819 | } |
| 820 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 821 | let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in { |
| 822 | def POPF : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize; |
| 823 | def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf{l}", []>; |
| 824 | } |
| 825 | let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in { |
| 826 | def PUSHF : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize; |
| 827 | def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf{l}", []>; |
| 828 | } |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 829 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 830 | let isTwoAddress = 1 in // GR32 = bswap GR32 |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 831 | def BSWAP32r : I<0xC8, AddRegFrm, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 832 | (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 833 | "bswap{l}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 834 | [(set GR32:$dst, (bswap GR32:$src))]>, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 835 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 836 | |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 837 | // Bit scan instructions. |
| 838 | let Defs = [EFLAGS] in { |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 839 | def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 840 | "bsf{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 841 | [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 842 | def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 843 | "bsf{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 844 | [(set GR16:$dst, (X86bsf (loadi16 addr:$src))), |
| 845 | (implicit EFLAGS)]>, TB; |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 846 | def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 847 | "bsf{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 848 | [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 849 | def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 850 | "bsf{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 851 | [(set GR32:$dst, (X86bsf (loadi32 addr:$src))), |
| 852 | (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 853 | |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 854 | def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 855 | "bsr{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 856 | [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 857 | def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 858 | "bsr{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 859 | [(set GR16:$dst, (X86bsr (loadi16 addr:$src))), |
| 860 | (implicit EFLAGS)]>, TB; |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 861 | def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 862 | "bsr{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 863 | [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 864 | def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 865 | "bsr{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 866 | [(set GR32:$dst, (X86bsr (loadi32 addr:$src))), |
| 867 | (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 868 | } // Defs = [EFLAGS] |
| 869 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 870 | let neverHasSideEffects = 1 in |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 871 | def LEA16r : I<0x8D, MRMSrcMem, |
Evan Cheng | 15b0d97 | 2009-12-12 18:51:56 +0000 | [diff] [blame] | 872 | (outs GR16:$dst), (ins lea32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 873 | "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize; |
Evan Cheng | e771ebd | 2008-03-27 01:41:09 +0000 | [diff] [blame] | 874 | let isReMaterializable = 1 in |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 875 | def LEA32r : I<0x8D, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 876 | (outs GR32:$dst), (ins lea32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 877 | "lea{l}\t{$src|$dst}, {$dst|$src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 878 | [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 879 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 880 | let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 881 | def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 882 | [(X86rep_movs i8)]>, REP; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 883 | def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 884 | [(X86rep_movs i16)]>, REP, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 885 | def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 886 | [(X86rep_movs i32)]>, REP; |
| 887 | } |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 888 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 889 | let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 890 | def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 891 | [(X86rep_stos i8)]>, REP; |
| 892 | let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 893 | def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 894 | [(X86rep_stos i16)]>, REP, OpSize; |
| 895 | let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 896 | def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 897 | [(X86rep_stos i32)]>, REP; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 898 | |
Sean Callanan | a82e465 | 2009-09-12 00:37:19 +0000 | [diff] [blame] | 899 | def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>; |
| 900 | def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize; |
| 901 | def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>; |
| 902 | |
Sean Callanan | 6f8f462 | 2009-09-12 02:25:20 +0000 | [diff] [blame] | 903 | def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>; |
| 904 | def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize; |
| 905 | def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>; |
| 906 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 907 | let Defs = [RAX, RDX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 908 | def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 909 | TB; |
Chris Lattner | b89abef | 2004-02-14 04:45:37 +0000 | [diff] [blame] | 910 | |
Anton Korobeynikov | 66fac79 | 2008-01-15 07:02:33 +0000 | [diff] [blame] | 911 | let isBarrier = 1, hasCtrlDep = 1 in { |
Chris Lattner | da68d30 | 2008-01-15 21:58:22 +0000 | [diff] [blame] | 912 | def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB; |
Anton Korobeynikov | 66fac79 | 2008-01-15 07:02:33 +0000 | [diff] [blame] | 913 | } |
| 914 | |
Chris Lattner | 02552de | 2009-08-11 16:58:39 +0000 | [diff] [blame] | 915 | def SYSCALL : I<0x05, RawFrm, |
| 916 | (outs), (ins), "syscall", []>, TB; |
| 917 | def SYSRET : I<0x07, RawFrm, |
| 918 | (outs), (ins), "sysret", []>, TB; |
| 919 | def SYSENTER : I<0x34, RawFrm, |
| 920 | (outs), (ins), "sysenter", []>, TB; |
| 921 | def SYSEXIT : I<0x35, RawFrm, |
| 922 | (outs), (ins), "sysexit", []>, TB; |
| 923 | |
Sean Callanan | 2a46f36 | 2009-09-12 02:52:41 +0000 | [diff] [blame] | 924 | def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>; |
Chris Lattner | 02552de | 2009-08-11 16:58:39 +0000 | [diff] [blame] | 925 | |
| 926 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 927 | //===----------------------------------------------------------------------===// |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 928 | // Input/Output Instructions... |
| 929 | // |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 930 | let Defs = [AL], Uses = [DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 931 | def IN8rr : I<0xEC, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 932 | "in{b}\t{%dx, %al|%AL, %DX}", []>; |
| 933 | let Defs = [AX], Uses = [DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 934 | def IN16rr : I<0xED, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 935 | "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize; |
| 936 | let Defs = [EAX], Uses = [DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 937 | def IN32rr : I<0xED, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 938 | "in{l}\t{%dx, %eax|%EAX, %DX}", []>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 939 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 940 | let Defs = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 941 | def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 942 | "in{b}\t{$port, %al|%AL, $port}", []>; |
| 943 | let Defs = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 944 | def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 945 | "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize; |
| 946 | let Defs = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 947 | def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 948 | "in{l}\t{$port, %eax|%EAX, $port}", []>; |
Chris Lattner | 440bbc2 | 2004-04-13 17:19:31 +0000 | [diff] [blame] | 949 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 950 | let Uses = [DX, AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 951 | def OUT8rr : I<0xEE, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 952 | "out{b}\t{%al, %dx|%DX, %AL}", []>; |
| 953 | let Uses = [DX, AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 954 | def OUT16rr : I<0xEF, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 955 | "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize; |
| 956 | let Uses = [DX, EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 957 | def OUT32rr : I<0xEF, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 958 | "out{l}\t{%eax, %dx|%DX, %EAX}", []>; |
Chris Lattner | ffff708 | 2004-08-01 07:44:35 +0000 | [diff] [blame] | 959 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 960 | let Uses = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 961 | def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 962 | "out{b}\t{%al, $port|$port, %AL}", []>; |
| 963 | let Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 964 | def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 965 | "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize; |
| 966 | let Uses = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 967 | def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 968 | "out{l}\t{%eax, $port|$port, %EAX}", []>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 969 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 970 | def IN8 : I<0x6C, RawFrm, (outs), (ins), |
| 971 | "ins{b}", []>; |
| 972 | def IN16 : I<0x6D, RawFrm, (outs), (ins), |
| 973 | "ins{w}", []>, OpSize; |
| 974 | def IN32 : I<0x6D, RawFrm, (outs), (ins), |
| 975 | "ins{l}", []>; |
| 976 | |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 977 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 978 | // Move Instructions... |
| 979 | // |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 980 | let neverHasSideEffects = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 981 | def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 982 | "mov{b}\t{$src, $dst|$dst, $src}", []>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 983 | def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 984 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 985 | def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 986 | "mov{l}\t{$src, $dst|$dst, $src}", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 987 | } |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 988 | let isReMaterializable = 1, isAsCheapAsAMove = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 989 | def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 990 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 991 | [(set GR8:$dst, imm:$src)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 992 | def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 993 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 994 | [(set GR16:$dst, imm:$src)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 995 | def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 996 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 997 | [(set GR32:$dst, imm:$src)]>; |
Dan Gohman | d45eddd | 2007-06-26 00:48:07 +0000 | [diff] [blame] | 998 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 999 | def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1000 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 1001 | [(store (i8 imm:$src), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1002 | def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1003 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 1004 | [(store (i16 imm:$src), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1005 | def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1006 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 1007 | [(store (i32 imm:$src), addr:$dst)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1008 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1009 | def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins offset8:$src), |
Sean Callanan | 2f34a13 | 2009-09-10 18:33:42 +0000 | [diff] [blame] | 1010 | "mov{b}\t{$src, %al|%al, $src}", []>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1011 | def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins offset16:$src), |
Sean Callanan | 2f34a13 | 2009-09-10 18:33:42 +0000 | [diff] [blame] | 1012 | "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1013 | def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src), |
Sean Callanan | 2f34a13 | 2009-09-10 18:33:42 +0000 | [diff] [blame] | 1014 | "mov{l}\t{$src, %eax|%eax, $src}", []>; |
| 1015 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1016 | def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs offset8:$dst), (ins), |
Sean Callanan | 2f34a13 | 2009-09-10 18:33:42 +0000 | [diff] [blame] | 1017 | "mov{b}\t{%al, $dst|$dst, %al}", []>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1018 | def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs offset16:$dst), (ins), |
Sean Callanan | 2f34a13 | 2009-09-10 18:33:42 +0000 | [diff] [blame] | 1019 | "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1020 | def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins), |
Sean Callanan | 2f34a13 | 2009-09-10 18:33:42 +0000 | [diff] [blame] | 1021 | "mov{l}\t{%eax, $dst|$dst, %eax}", []>; |
| 1022 | |
Sean Callanan | 38fee0e | 2009-09-15 18:47:29 +0000 | [diff] [blame] | 1023 | // Moves to and from segment registers |
| 1024 | def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src), |
| 1025 | "mov{w}\t{$src, $dst|$dst, $src}", []>; |
| 1026 | def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src), |
| 1027 | "mov{w}\t{$src, $dst|$dst, $src}", []>; |
| 1028 | def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src), |
| 1029 | "mov{w}\t{$src, $dst|$dst, $src}", []>; |
| 1030 | def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src), |
| 1031 | "mov{w}\t{$src, $dst|$dst, $src}", []>; |
| 1032 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1033 | def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), |
| 1034 | "mov{b}\t{$src, $dst|$dst, $src}", []>; |
| 1035 | def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
| 1036 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; |
| 1037 | def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
| 1038 | "mov{l}\t{$src, $dst|$dst, $src}", []>; |
| 1039 | |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 1040 | let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1041 | def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1042 | "mov{b}\t{$src, $dst|$dst, $src}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 1043 | [(set GR8:$dst, (loadi8 addr:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1044 | def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1045 | "mov{w}\t{$src, $dst|$dst, $src}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 1046 | [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1047 | def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1048 | "mov{l}\t{$src, $dst|$dst, $src}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 1049 | [(set GR32:$dst, (loadi32 addr:$src))]>; |
Evan Cheng | 2f39426 | 2007-08-30 05:49:43 +0000 | [diff] [blame] | 1050 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1051 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1052 | def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1053 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1054 | [(store GR8:$src, addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1055 | def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1056 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1057 | [(store GR16:$src, addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1058 | def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1059 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1060 | [(store GR32:$src, addr:$dst)]>; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 1061 | |
Dan Gohman | 4af325d | 2009-04-27 16:41:36 +0000 | [diff] [blame] | 1062 | // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so |
| 1063 | // that they can be used for copying and storing h registers, which can't be |
| 1064 | // encoded when a REX prefix is present. |
Dan Gohman | 6d9305c | 2009-04-15 00:04:23 +0000 | [diff] [blame] | 1065 | let neverHasSideEffects = 1 in |
Dan Gohman | df7dfc7 | 2009-04-15 19:48:57 +0000 | [diff] [blame] | 1066 | def MOV8rr_NOREX : I<0x88, MRMDestReg, |
| 1067 | (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), |
Dan Gohman | 6d9305c | 2009-04-15 00:04:23 +0000 | [diff] [blame] | 1068 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; |
Evan Cheng | 8c14740 | 2009-04-30 00:58:57 +0000 | [diff] [blame] | 1069 | let mayStore = 1 in |
Dan Gohman | 6d9305c | 2009-04-15 00:04:23 +0000 | [diff] [blame] | 1070 | def MOV8mr_NOREX : I<0x88, MRMDestMem, |
| 1071 | (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), |
| 1072 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; |
Evan Cheng | 8c14740 | 2009-04-30 00:58:57 +0000 | [diff] [blame] | 1073 | let mayLoad = 1, |
| 1074 | canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in |
Dan Gohman | 4af325d | 2009-04-27 16:41:36 +0000 | [diff] [blame] | 1075 | def MOV8rm_NOREX : I<0x8A, MRMSrcMem, |
| 1076 | (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), |
| 1077 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 1078 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1079 | // Moves to and from debug registers |
| 1080 | def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src), |
| 1081 | "mov{l}\t{$src, $dst|$dst, $src}", []>, TB; |
| 1082 | def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src), |
| 1083 | "mov{l}\t{$src, $dst|$dst, $src}", []>, TB; |
| 1084 | |
| 1085 | // Moves to and from control registers |
| 1086 | def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG_32:$src), |
| 1087 | "mov{q}\t{$src, $dst|$dst, $src}", []>, TB; |
| 1088 | def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_32:$dst), (ins GR32:$src), |
| 1089 | "mov{q}\t{$src, $dst|$dst, $src}", []>, TB; |
| 1090 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1091 | //===----------------------------------------------------------------------===// |
| 1092 | // Fixed-Register Multiplication and Division Instructions... |
| 1093 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1094 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 1095 | // Extra precision multiplication |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1096 | let Defs = [AL,AH,EFLAGS], Uses = [AL] in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1097 | def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src", |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 1098 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 1099 | // This probably ought to be moved to a def : Pat<> if the |
| 1100 | // syntax can be accepted. |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1101 | [(set AL, (mul AL, GR8:$src)), |
| 1102 | (implicit EFLAGS)]>; // AL,AH = AL*GR8 |
| 1103 | |
Chris Lattner | a731c9f | 2008-01-11 07:18:17 +0000 | [diff] [blame] | 1104 | let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1105 | def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), |
| 1106 | "mul{w}\t$src", |
| 1107 | []>, OpSize; // AX,DX = AX*GR16 |
| 1108 | |
Chris Lattner | a731c9f | 2008-01-11 07:18:17 +0000 | [diff] [blame] | 1109 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1110 | def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), |
| 1111 | "mul{l}\t$src", |
| 1112 | []>; // EAX,EDX = EAX*GR32 |
| 1113 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1114 | let Defs = [AL,AH,EFLAGS], Uses = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1115 | def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1116 | "mul{b}\t$src", |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 1117 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 1118 | // This probably ought to be moved to a def : Pat<> if the |
| 1119 | // syntax can be accepted. |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1120 | [(set AL, (mul AL, (loadi8 addr:$src))), |
| 1121 | (implicit EFLAGS)]>; // AL,AH = AL*[mem8] |
| 1122 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1123 | let mayLoad = 1, neverHasSideEffects = 1 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1124 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1125 | def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1126 | "mul{w}\t$src", |
| 1127 | []>, OpSize; // AX,DX = AX*[mem16] |
| 1128 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1129 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1130 | def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1131 | "mul{l}\t$src", |
| 1132 | []>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1133 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1134 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1135 | let neverHasSideEffects = 1 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1136 | let Defs = [AL,AH,EFLAGS], Uses = [AL] in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1137 | def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>; |
| 1138 | // AL,AH = AL*GR8 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1139 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1140 | def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1141 | OpSize; // AX,DX = AX*GR16 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1142 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1143 | def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>; |
| 1144 | // EAX,EDX = EAX*GR32 |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1145 | let mayLoad = 1 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1146 | let Defs = [AL,AH,EFLAGS], Uses = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1147 | def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1148 | "imul{b}\t$src", []>; // AL,AH = AL*[mem8] |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1149 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1150 | def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1151 | "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16] |
Eli Friedman | ba7b1c4 | 2009-12-26 20:08:30 +0000 | [diff] [blame] | 1152 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1153 | def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1154 | "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1155 | } |
Dan Gohman | c99da13 | 2008-11-18 21:29:14 +0000 | [diff] [blame] | 1156 | } // neverHasSideEffects |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 1157 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 1158 | // unsigned division/remainder |
Dale Johannesen | 2cb48ea | 2008-10-07 18:54:28 +0000 | [diff] [blame] | 1159 | let Defs = [AL,AH,EFLAGS], Uses = [AX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1160 | def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1161 | "div{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1162 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1163 | def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1164 | "div{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1165 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1166 | def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1167 | "div{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1168 | let mayLoad = 1 in { |
Dale Johannesen | 2cb48ea | 2008-10-07 18:54:28 +0000 | [diff] [blame] | 1169 | let Defs = [AL,AH,EFLAGS], Uses = [AX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1170 | def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1171 | "div{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1172 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1173 | def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1174 | "div{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1175 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1176 | // EDX:EAX/[mem32] = EAX,EDX |
| 1177 | def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1178 | "div{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1179 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1180 | |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 1181 | // Signed division/remainder. |
Dale Johannesen | 2cb48ea | 2008-10-07 18:54:28 +0000 | [diff] [blame] | 1182 | let Defs = [AL,AH,EFLAGS], Uses = [AX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1183 | def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1184 | "idiv{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1185 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1186 | def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1187 | "idiv{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1188 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1189 | def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1190 | "idiv{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1191 | let mayLoad = 1, mayLoad = 1 in { |
Dale Johannesen | 2cb48ea | 2008-10-07 18:54:28 +0000 | [diff] [blame] | 1192 | let Defs = [AL,AH,EFLAGS], Uses = [AX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1193 | def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1194 | "idiv{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1195 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1196 | def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1197 | "idiv{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1198 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1199 | def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), |
| 1200 | // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1201 | "idiv{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1202 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1203 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1204 | //===----------------------------------------------------------------------===// |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1205 | // Two address Instructions. |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1206 | // |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1207 | let isTwoAddress = 1 in { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1208 | |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 1209 | // Conditional moves |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 1210 | let Uses = [EFLAGS] in { |
Dan Gohman | cbbea0f | 2009-08-27 00:14:12 +0000 | [diff] [blame] | 1211 | |
Dan Gohman | 533297b | 2009-10-29 18:10:34 +0000 | [diff] [blame] | 1212 | // X86 doesn't have 8-bit conditional moves. Use a customInserter to |
Dan Gohman | cbbea0f | 2009-08-27 00:14:12 +0000 | [diff] [blame] | 1213 | // emit control flow. An alternative to this is to mark i8 SELECT as Promote, |
| 1214 | // however that requires promoting the operands, and can induce additional |
Dan Gohman | 71a258c | 2009-08-29 22:19:15 +0000 | [diff] [blame] | 1215 | // i8 register pressure. Note that CMOV_GR8 is conservatively considered to |
| 1216 | // clobber EFLAGS, because if one of the operands is zero, the expansion |
| 1217 | // could involve an xor. |
Dan Gohman | 533297b | 2009-10-29 18:10:34 +0000 | [diff] [blame] | 1218 | let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in |
Dan Gohman | cbbea0f | 2009-08-27 00:14:12 +0000 | [diff] [blame] | 1219 | def CMOV_GR8 : I<0, Pseudo, |
| 1220 | (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond), |
| 1221 | "#CMOV_GR8 PSEUDO!", |
| 1222 | [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2, |
| 1223 | imm:$cond, EFLAGS))]>; |
| 1224 | |
Dan Gohman | a4c5c33 | 2009-08-27 18:16:24 +0000 | [diff] [blame] | 1225 | let isCommutable = 1 in { |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1226 | def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1227 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1228 | "cmovb{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1229 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1230 | X86_COND_B, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1231 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1232 | def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1233 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1234 | "cmovb{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1235 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1236 | X86_COND_B, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1237 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1238 | def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1239 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1240 | "cmovae{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1241 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1242 | X86_COND_AE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1243 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1244 | def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1245 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1246 | "cmovae{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1247 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1248 | X86_COND_AE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1249 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1250 | def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1251 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1252 | "cmove{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1253 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1254 | X86_COND_E, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1255 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1256 | def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1257 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1258 | "cmove{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1259 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1260 | X86_COND_E, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1261 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1262 | def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1263 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1264 | "cmovne{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1265 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1266 | X86_COND_NE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1267 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1268 | def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1269 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1270 | "cmovne{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1271 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1272 | X86_COND_NE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1273 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1274 | def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1275 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1276 | "cmovbe{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1277 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1278 | X86_COND_BE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1279 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1280 | def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1281 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1282 | "cmovbe{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1283 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1284 | X86_COND_BE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1285 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1286 | def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1287 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1288 | "cmova{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1289 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1290 | X86_COND_A, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1291 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1292 | def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1293 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1294 | "cmova{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1295 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1296 | X86_COND_A, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1297 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1298 | def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1299 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1300 | "cmovl{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1301 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1302 | X86_COND_L, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1303 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1304 | def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1305 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1306 | "cmovl{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1307 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1308 | X86_COND_L, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1309 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1310 | def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1311 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1312 | "cmovge{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1313 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1314 | X86_COND_GE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1315 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1316 | def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1317 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1318 | "cmovge{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1319 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1320 | X86_COND_GE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1321 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1322 | def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1323 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1324 | "cmovle{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1325 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1326 | X86_COND_LE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1327 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1328 | def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1329 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1330 | "cmovle{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1331 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1332 | X86_COND_LE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1333 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1334 | def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1335 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1336 | "cmovg{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1337 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1338 | X86_COND_G, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1339 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1340 | def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1341 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1342 | "cmovg{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1343 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1344 | X86_COND_G, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1345 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1346 | def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1347 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1348 | "cmovs{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1349 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1350 | X86_COND_S, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1351 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1352 | def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1353 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1354 | "cmovs{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1355 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1356 | X86_COND_S, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1357 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1358 | def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1359 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1360 | "cmovns{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1361 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1362 | X86_COND_NS, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1363 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1364 | def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1365 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1366 | "cmovns{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1367 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1368 | X86_COND_NS, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1369 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1370 | def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1371 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1372 | "cmovp{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1373 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1374 | X86_COND_P, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1375 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1376 | def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1377 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1378 | "cmovp{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1379 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1380 | X86_COND_P, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1381 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1382 | def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1383 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1384 | "cmovnp{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1385 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1386 | X86_COND_NP, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1387 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1388 | def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1389 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1390 | "cmovnp{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1391 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1392 | X86_COND_NP, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1393 | TB; |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1394 | def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16 |
| 1395 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1396 | "cmovo{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1397 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
| 1398 | X86_COND_O, EFLAGS))]>, |
| 1399 | TB, OpSize; |
| 1400 | def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32 |
| 1401 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1402 | "cmovo{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1403 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
| 1404 | X86_COND_O, EFLAGS))]>, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 1405 | TB; |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1406 | def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16 |
| 1407 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1408 | "cmovno{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1409 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
| 1410 | X86_COND_NO, EFLAGS))]>, |
| 1411 | TB, OpSize; |
| 1412 | def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32 |
| 1413 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1414 | "cmovno{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1415 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
| 1416 | X86_COND_NO, EFLAGS))]>, |
| 1417 | TB; |
| 1418 | } // isCommutable = 1 |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1419 | |
| 1420 | def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16] |
| 1421 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1422 | "cmovb{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1423 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1424 | X86_COND_B, EFLAGS))]>, |
| 1425 | TB, OpSize; |
| 1426 | def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32] |
| 1427 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1428 | "cmovb{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1429 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1430 | X86_COND_B, EFLAGS))]>, |
| 1431 | TB; |
| 1432 | def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16] |
| 1433 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1434 | "cmovae{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1435 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1436 | X86_COND_AE, EFLAGS))]>, |
| 1437 | TB, OpSize; |
| 1438 | def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32] |
| 1439 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1440 | "cmovae{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1441 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1442 | X86_COND_AE, EFLAGS))]>, |
| 1443 | TB; |
| 1444 | def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16] |
| 1445 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1446 | "cmove{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1447 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1448 | X86_COND_E, EFLAGS))]>, |
| 1449 | TB, OpSize; |
| 1450 | def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32] |
| 1451 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1452 | "cmove{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1453 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1454 | X86_COND_E, EFLAGS))]>, |
| 1455 | TB; |
| 1456 | def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16] |
| 1457 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1458 | "cmovne{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1459 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1460 | X86_COND_NE, EFLAGS))]>, |
| 1461 | TB, OpSize; |
| 1462 | def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32] |
| 1463 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1464 | "cmovne{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1465 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1466 | X86_COND_NE, EFLAGS))]>, |
| 1467 | TB; |
| 1468 | def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16] |
| 1469 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1470 | "cmovbe{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1471 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1472 | X86_COND_BE, EFLAGS))]>, |
| 1473 | TB, OpSize; |
| 1474 | def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32] |
| 1475 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1476 | "cmovbe{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1477 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1478 | X86_COND_BE, EFLAGS))]>, |
| 1479 | TB; |
| 1480 | def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16] |
| 1481 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1482 | "cmova{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1483 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1484 | X86_COND_A, EFLAGS))]>, |
| 1485 | TB, OpSize; |
| 1486 | def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32] |
| 1487 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1488 | "cmova{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1489 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1490 | X86_COND_A, EFLAGS))]>, |
| 1491 | TB; |
| 1492 | def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16] |
| 1493 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1494 | "cmovl{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1495 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1496 | X86_COND_L, EFLAGS))]>, |
| 1497 | TB, OpSize; |
| 1498 | def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32] |
| 1499 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1500 | "cmovl{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1501 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1502 | X86_COND_L, EFLAGS))]>, |
| 1503 | TB; |
| 1504 | def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16] |
| 1505 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1506 | "cmovge{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1507 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1508 | X86_COND_GE, EFLAGS))]>, |
| 1509 | TB, OpSize; |
| 1510 | def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32] |
| 1511 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1512 | "cmovge{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1513 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1514 | X86_COND_GE, EFLAGS))]>, |
| 1515 | TB; |
| 1516 | def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16] |
| 1517 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1518 | "cmovle{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1519 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1520 | X86_COND_LE, EFLAGS))]>, |
| 1521 | TB, OpSize; |
| 1522 | def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32] |
| 1523 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1524 | "cmovle{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1525 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1526 | X86_COND_LE, EFLAGS))]>, |
| 1527 | TB; |
| 1528 | def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16] |
| 1529 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1530 | "cmovg{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1531 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1532 | X86_COND_G, EFLAGS))]>, |
| 1533 | TB, OpSize; |
| 1534 | def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32] |
| 1535 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1536 | "cmovg{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1537 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1538 | X86_COND_G, EFLAGS))]>, |
| 1539 | TB; |
| 1540 | def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16] |
| 1541 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1542 | "cmovs{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1543 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1544 | X86_COND_S, EFLAGS))]>, |
| 1545 | TB, OpSize; |
| 1546 | def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32] |
| 1547 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1548 | "cmovs{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1549 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1550 | X86_COND_S, EFLAGS))]>, |
| 1551 | TB; |
| 1552 | def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16] |
| 1553 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1554 | "cmovns{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1555 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1556 | X86_COND_NS, EFLAGS))]>, |
| 1557 | TB, OpSize; |
| 1558 | def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32] |
| 1559 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1560 | "cmovns{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1561 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1562 | X86_COND_NS, EFLAGS))]>, |
| 1563 | TB; |
| 1564 | def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16] |
| 1565 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1566 | "cmovp{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1567 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1568 | X86_COND_P, EFLAGS))]>, |
| 1569 | TB, OpSize; |
| 1570 | def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32] |
| 1571 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1572 | "cmovp{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1573 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1574 | X86_COND_P, EFLAGS))]>, |
| 1575 | TB; |
| 1576 | def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16] |
| 1577 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1578 | "cmovnp{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1579 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1580 | X86_COND_NP, EFLAGS))]>, |
| 1581 | TB, OpSize; |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1582 | def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32] |
| 1583 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1584 | "cmovnp{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1585 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1586 | X86_COND_NP, EFLAGS))]>, |
| 1587 | TB; |
| 1588 | def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16] |
| 1589 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1590 | "cmovo{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1591 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1592 | X86_COND_O, EFLAGS))]>, |
| 1593 | TB, OpSize; |
| 1594 | def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32] |
| 1595 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1596 | "cmovo{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1597 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1598 | X86_COND_O, EFLAGS))]>, |
| 1599 | TB; |
| 1600 | def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16] |
| 1601 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1602 | "cmovno{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1603 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1604 | X86_COND_NO, EFLAGS))]>, |
| 1605 | TB, OpSize; |
| 1606 | def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32] |
| 1607 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1608 | "cmovno{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1609 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1610 | X86_COND_NO, EFLAGS))]>, |
| 1611 | TB; |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 1612 | } // Uses = [EFLAGS] |
| 1613 | |
| 1614 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1615 | // unary instructions |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1616 | let CodeSize = 2 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1617 | let Defs = [EFLAGS] in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1618 | def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1619 | [(set GR8:$dst, (ineg GR8:$src)), |
| 1620 | (implicit EFLAGS)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1621 | def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1622 | [(set GR16:$dst, (ineg GR16:$src)), |
| 1623 | (implicit EFLAGS)]>, OpSize; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1624 | def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1625 | [(set GR32:$dst, (ineg GR32:$src)), |
| 1626 | (implicit EFLAGS)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1627 | let isTwoAddress = 0 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1628 | def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1629 | [(store (ineg (loadi8 addr:$dst)), addr:$dst), |
| 1630 | (implicit EFLAGS)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1631 | def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1632 | [(store (ineg (loadi16 addr:$dst)), addr:$dst), |
| 1633 | (implicit EFLAGS)]>, OpSize; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1634 | def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1635 | [(store (ineg (loadi32 addr:$dst)), addr:$dst), |
| 1636 | (implicit EFLAGS)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1637 | } |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1638 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1639 | |
Evan Cheng | aaf414c | 2009-01-21 02:09:05 +0000 | [diff] [blame] | 1640 | // Match xor -1 to not. Favors these over a move imm + xor to save code size. |
| 1641 | let AddedComplexity = 15 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1642 | def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1643 | [(set GR8:$dst, (not GR8:$src))]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1644 | def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1645 | [(set GR16:$dst, (not GR16:$src))]>, OpSize; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1646 | def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1647 | [(set GR32:$dst, (not GR32:$src))]>; |
Evan Cheng | aaf414c | 2009-01-21 02:09:05 +0000 | [diff] [blame] | 1648 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1649 | let isTwoAddress = 0 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1650 | def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1651 | [(store (not (loadi8 addr:$dst)), addr:$dst)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1652 | def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1653 | [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1654 | def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1655 | [(store (not (loadi32 addr:$dst)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1656 | } |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1657 | } // CodeSize |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1658 | |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 1659 | // TODO: inc/dec is slow for P4, but fast for Pentium-M. |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1660 | let Defs = [EFLAGS] in { |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1661 | let CodeSize = 2 in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1662 | def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1663 | [(set GR8:$dst, (add GR8:$src, 1)), |
| 1664 | (implicit EFLAGS)]>; |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1665 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1666 | def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), |
| 1667 | "inc{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1668 | [(set GR16:$dst, (add GR16:$src, 1)), |
| 1669 | (implicit EFLAGS)]>, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1670 | OpSize, Requires<[In32BitMode]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1671 | def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), |
| 1672 | "inc{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1673 | [(set GR32:$dst, (add GR32:$src, 1)), |
| 1674 | (implicit EFLAGS)]>, Requires<[In32BitMode]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1675 | } |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1676 | let isTwoAddress = 0, CodeSize = 2 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1677 | def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1678 | [(store (add (loadi8 addr:$dst), 1), addr:$dst), |
| 1679 | (implicit EFLAGS)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1680 | def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1681 | [(store (add (loadi16 addr:$dst), 1), addr:$dst), |
| 1682 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1683 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1684 | def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1685 | [(store (add (loadi32 addr:$dst), 1), addr:$dst), |
| 1686 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1687 | Requires<[In32BitMode]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1688 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1689 | |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1690 | let CodeSize = 2 in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1691 | def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1692 | [(set GR8:$dst, (add GR8:$src, -1)), |
| 1693 | (implicit EFLAGS)]>; |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1694 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1695 | def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), |
| 1696 | "dec{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1697 | [(set GR16:$dst, (add GR16:$src, -1)), |
| 1698 | (implicit EFLAGS)]>, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1699 | OpSize, Requires<[In32BitMode]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1700 | def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), |
| 1701 | "dec{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1702 | [(set GR32:$dst, (add GR32:$src, -1)), |
| 1703 | (implicit EFLAGS)]>, Requires<[In32BitMode]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1704 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1705 | |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1706 | let isTwoAddress = 0, CodeSize = 2 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1707 | def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1708 | [(store (add (loadi8 addr:$dst), -1), addr:$dst), |
| 1709 | (implicit EFLAGS)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1710 | def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1711 | [(store (add (loadi16 addr:$dst), -1), addr:$dst), |
| 1712 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1713 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1714 | def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1715 | [(store (add (loadi32 addr:$dst), -1), addr:$dst), |
| 1716 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1717 | Requires<[In32BitMode]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1718 | } |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1719 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1720 | |
| 1721 | // Logical operators... |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1722 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1723 | let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1724 | def AND8rr : I<0x20, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1725 | (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1726 | "and{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1727 | [(set GR8:$dst, (and GR8:$src1, GR8:$src2)), |
| 1728 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1729 | def AND16rr : I<0x21, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1730 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1731 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1732 | [(set GR16:$dst, (and GR16:$src1, GR16:$src2)), |
| 1733 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1734 | def AND32rr : I<0x21, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1735 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1736 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1737 | [(set GR32:$dst, (and GR32:$src1, GR32:$src2)), |
| 1738 | (implicit EFLAGS)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1739 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1740 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1741 | // AND instructions with the destination register in REG and the source register |
| 1742 | // in R/M. Included for the disassembler. |
| 1743 | def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 1744 | "and{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 1745 | def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst), |
| 1746 | (ins GR16:$src1, GR16:$src2), |
| 1747 | "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 1748 | def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst), |
| 1749 | (ins GR32:$src1, GR32:$src2), |
| 1750 | "and{l}\t{$src2, $dst|$dst, $src2}", []>; |
| 1751 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1752 | def AND8rm : I<0x22, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1753 | (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1754 | "and{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 1755 | [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1756 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1757 | def AND16rm : I<0x23, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1758 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1759 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 1760 | [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1761 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1762 | def AND32rm : I<0x23, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1763 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1764 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 1765 | [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1766 | (implicit EFLAGS)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1767 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1768 | def AND8ri : Ii8<0x80, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1769 | (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1770 | "and{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1771 | [(set GR8:$dst, (and GR8:$src1, imm:$src2)), |
| 1772 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1773 | def AND16ri : Ii16<0x81, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1774 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1775 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1776 | [(set GR16:$dst, (and GR16:$src1, imm:$src2)), |
| 1777 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1778 | def AND32ri : Ii32<0x81, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1779 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1780 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1781 | [(set GR32:$dst, (and GR32:$src1, imm:$src2)), |
| 1782 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1783 | def AND16ri8 : Ii8<0x83, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1784 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1785 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1786 | [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)), |
| 1787 | (implicit EFLAGS)]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1788 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1789 | def AND32ri8 : Ii8<0x83, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1790 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1791 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1792 | [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)), |
| 1793 | (implicit EFLAGS)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1794 | |
| 1795 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1796 | def AND8mr : I<0x20, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1797 | (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1798 | "and{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1799 | [(store (and (load addr:$dst), GR8:$src), addr:$dst), |
| 1800 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1801 | def AND16mr : I<0x21, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1802 | (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1803 | "and{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1804 | [(store (and (load addr:$dst), GR16:$src), addr:$dst), |
| 1805 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1806 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1807 | def AND32mr : I<0x21, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1808 | (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1809 | "and{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1810 | [(store (and (load addr:$dst), GR32:$src), addr:$dst), |
| 1811 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1812 | def AND8mi : Ii8<0x80, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1813 | (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1814 | "and{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1815 | [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst), |
| 1816 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1817 | def AND16mi : Ii16<0x81, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1818 | (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1819 | "and{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1820 | [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst), |
| 1821 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1822 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1823 | def AND32mi : Ii32<0x81, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1824 | (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1825 | "and{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1826 | [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst), |
| 1827 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1828 | def AND16mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1829 | (outs), (ins i16mem:$dst, i16i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1830 | "and{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1831 | [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst), |
| 1832 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1833 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1834 | def AND32mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1835 | (outs), (ins i32mem:$dst, i32i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1836 | "and{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1837 | [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst), |
| 1838 | (implicit EFLAGS)]>; |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 1839 | |
| 1840 | def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src), |
| 1841 | "and{b}\t{$src, %al|%al, $src}", []>; |
| 1842 | def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src), |
| 1843 | "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 1844 | def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src), |
| 1845 | "and{l}\t{$src, %eax|%eax, $src}", []>; |
| 1846 | |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1847 | } |
| 1848 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1849 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1850 | let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1851 | def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), |
| 1852 | (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1853 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1854 | [(set GR8:$dst, (or GR8:$src1, GR8:$src2)), |
| 1855 | (implicit EFLAGS)]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1856 | def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), |
| 1857 | (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1858 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 3bda201 | 2010-01-12 18:31:19 +0000 | [diff] [blame] | 1859 | [(set GR16:$dst, (or GR16:$src1, GR16:$src2)), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1860 | (implicit EFLAGS)]>, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1861 | def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), |
| 1862 | (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1863 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 3bda201 | 2010-01-12 18:31:19 +0000 | [diff] [blame] | 1864 | [(set GR32:$dst, (or GR32:$src1, GR32:$src2)), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1865 | (implicit EFLAGS)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1866 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1867 | |
| 1868 | // OR instructions with the destination register in REG and the source register |
| 1869 | // in R/M. Included for the disassembler. |
| 1870 | def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 1871 | "or{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 1872 | def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst), |
| 1873 | (ins GR16:$src1, GR16:$src2), |
| 1874 | "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 1875 | def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst), |
| 1876 | (ins GR32:$src1, GR32:$src2), |
| 1877 | "or{l}\t{$src2, $dst|$dst, $src2}", []>; |
| 1878 | |
| 1879 | def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), |
| 1880 | (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1881 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1882 | [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))), |
| 1883 | (implicit EFLAGS)]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1884 | def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), |
| 1885 | (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1886 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1887 | [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))), |
| 1888 | (implicit EFLAGS)]>, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1889 | def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), |
| 1890 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1891 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1892 | [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))), |
| 1893 | (implicit EFLAGS)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1894 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1895 | def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), |
| 1896 | (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1897 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | ac000fa | 2010-01-11 20:18:04 +0000 | [diff] [blame] | 1898 | [(set GR8:$dst, (or GR8:$src1, imm:$src2)), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1899 | (implicit EFLAGS)]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1900 | def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), |
| 1901 | (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1902 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 3bda201 | 2010-01-12 18:31:19 +0000 | [diff] [blame] | 1903 | [(set GR16:$dst, (or GR16:$src1, imm:$src2)), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1904 | (implicit EFLAGS)]>, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1905 | def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), |
| 1906 | (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1907 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 3bda201 | 2010-01-12 18:31:19 +0000 | [diff] [blame] | 1908 | [(set GR32:$dst, (or GR32:$src1, imm:$src2)), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1909 | (implicit EFLAGS)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1910 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1911 | def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), |
| 1912 | (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1913 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 3bda201 | 2010-01-12 18:31:19 +0000 | [diff] [blame] | 1914 | [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1915 | (implicit EFLAGS)]>, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1916 | def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), |
| 1917 | (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1918 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 3bda201 | 2010-01-12 18:31:19 +0000 | [diff] [blame] | 1919 | [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1920 | (implicit EFLAGS)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1921 | let isTwoAddress = 0 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1922 | def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1923 | "or{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1924 | [(store (or (load addr:$dst), GR8:$src), addr:$dst), |
| 1925 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1926 | def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1927 | "or{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1928 | [(store (or (load addr:$dst), GR16:$src), addr:$dst), |
| 1929 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1930 | def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1931 | "or{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1932 | [(store (or (load addr:$dst), GR32:$src), addr:$dst), |
| 1933 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1934 | def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1935 | "or{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1936 | [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst), |
| 1937 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1938 | def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1939 | "or{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1940 | [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst), |
| 1941 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1942 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1943 | def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1944 | "or{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1945 | [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst), |
| 1946 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1947 | def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1948 | "or{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1949 | [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst), |
| 1950 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1951 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1952 | def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1953 | "or{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1954 | [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst), |
| 1955 | (implicit EFLAGS)]>; |
Sean Callanan | d00025a | 2009-09-11 19:01:56 +0000 | [diff] [blame] | 1956 | |
| 1957 | def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src), |
| 1958 | "or{b}\t{$src, %al|%al, $src}", []>; |
| 1959 | def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src), |
| 1960 | "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 1961 | def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src), |
| 1962 | "or{l}\t{$src, %eax|%eax, $src}", []>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1963 | } // isTwoAddress = 0 |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1964 | |
| 1965 | |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 1966 | let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1967 | def XOR8rr : I<0x30, MRMDestReg, |
| 1968 | (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), |
| 1969 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1970 | [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)), |
| 1971 | (implicit EFLAGS)]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1972 | def XOR16rr : I<0x31, MRMDestReg, |
| 1973 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
| 1974 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1975 | [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)), |
| 1976 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1977 | def XOR32rr : I<0x31, MRMDestReg, |
| 1978 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
| 1979 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1980 | [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)), |
| 1981 | (implicit EFLAGS)]>; |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 1982 | } // isCommutable = 1 |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1983 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1984 | // XOR instructions with the destination register in REG and the source register |
| 1985 | // in R/M. Included for the disassembler. |
| 1986 | def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 1987 | "xor{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 1988 | def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst), |
| 1989 | (ins GR16:$src1, GR16:$src2), |
| 1990 | "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 1991 | def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst), |
| 1992 | (ins GR32:$src1, GR32:$src2), |
| 1993 | "xor{l}\t{$src2, $dst|$dst, $src2}", []>; |
| 1994 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1995 | def XOR8rm : I<0x32, MRMSrcMem , |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1996 | (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1997 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1998 | [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))), |
| 1999 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2000 | def XOR16rm : I<0x33, MRMSrcMem , |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2001 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2002 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 2003 | [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))), |
| 2004 | (implicit EFLAGS)]>, |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 2005 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2006 | def XOR32rm : I<0x33, MRMSrcMem , |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2007 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2008 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 2009 | [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))), |
| 2010 | (implicit EFLAGS)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2011 | |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 2012 | def XOR8ri : Ii8<0x80, MRM6r, |
| 2013 | (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
| 2014 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 2015 | [(set GR8:$dst, (xor GR8:$src1, imm:$src2)), |
| 2016 | (implicit EFLAGS)]>; |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 2017 | def XOR16ri : Ii16<0x81, MRM6r, |
| 2018 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
| 2019 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 2020 | [(set GR16:$dst, (xor GR16:$src1, imm:$src2)), |
| 2021 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 2022 | def XOR32ri : Ii32<0x81, MRM6r, |
| 2023 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
| 2024 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 2025 | [(set GR32:$dst, (xor GR32:$src1, imm:$src2)), |
| 2026 | (implicit EFLAGS)]>; |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 2027 | def XOR16ri8 : Ii8<0x83, MRM6r, |
| 2028 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
| 2029 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 2030 | [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)), |
| 2031 | (implicit EFLAGS)]>, |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 2032 | OpSize; |
| 2033 | def XOR32ri8 : Ii8<0x83, MRM6r, |
| 2034 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
| 2035 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 2036 | [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)), |
| 2037 | (implicit EFLAGS)]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 2038 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2039 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2040 | def XOR8mr : I<0x30, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2041 | (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2042 | "xor{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 2043 | [(store (xor (load addr:$dst), GR8:$src), addr:$dst), |
| 2044 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2045 | def XOR16mr : I<0x31, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2046 | (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2047 | "xor{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 2048 | [(store (xor (load addr:$dst), GR16:$src), addr:$dst), |
| 2049 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 2050 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2051 | def XOR32mr : I<0x31, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2052 | (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2053 | "xor{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 2054 | [(store (xor (load addr:$dst), GR32:$src), addr:$dst), |
| 2055 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2056 | def XOR8mi : Ii8<0x80, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2057 | (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2058 | "xor{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 2059 | [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst), |
| 2060 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2061 | def XOR16mi : Ii16<0x81, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2062 | (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2063 | "xor{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 2064 | [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst), |
| 2065 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 2066 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2067 | def XOR32mi : Ii32<0x81, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2068 | (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2069 | "xor{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 2070 | [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst), |
| 2071 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2072 | def XOR16mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2073 | (outs), (ins i16mem:$dst, i16i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2074 | "xor{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 2075 | [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst), |
| 2076 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 2077 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2078 | def XOR32mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2079 | (outs), (ins i32mem:$dst, i32i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2080 | "xor{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 2081 | [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst), |
| 2082 | (implicit EFLAGS)]>; |
Sean Callanan | 7893ec6 | 2009-09-10 19:52:26 +0000 | [diff] [blame] | 2083 | |
| 2084 | def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src), |
| 2085 | "xor{b}\t{$src, %al|%al, $src}", []>; |
| 2086 | def XOR16i16 : Ii16 <0x35, RawFrm, (outs), (ins i16imm:$src), |
| 2087 | "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 2088 | def XOR32i32 : Ii32 <0x35, RawFrm, (outs), (ins i32imm:$src), |
| 2089 | "xor{l}\t{$src, %eax|%eax, $src}", []>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 2090 | } // isTwoAddress = 0 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2091 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2092 | |
| 2093 | // Shift instructions |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2094 | let Defs = [EFLAGS] in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2095 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2096 | def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2097 | "shl{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2098 | [(set GR8:$dst, (shl GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2099 | def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2100 | "shl{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2101 | [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2102 | def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2103 | "shl{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2104 | [(set GR32:$dst, (shl GR32:$src, CL))]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 2105 | } // Uses = [CL] |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2106 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2107 | def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2108 | "shl{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2109 | [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2110 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2111 | def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2112 | "shl{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2113 | [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2114 | def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2115 | "shl{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2116 | [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>; |
Sean Callanan | 13cf8e9 | 2009-09-16 02:28:43 +0000 | [diff] [blame] | 2117 | |
| 2118 | // NOTE: We don't include patterns for shifts of a register by one, because |
| 2119 | // 'add reg,reg' is cheaper. |
| 2120 | |
| 2121 | def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1), |
| 2122 | "shl{b}\t$dst", []>; |
| 2123 | def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1), |
| 2124 | "shl{w}\t$dst", []>, OpSize; |
| 2125 | def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1), |
| 2126 | "shl{l}\t$dst", []>; |
| 2127 | |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 2128 | } // isConvertibleToThreeAddress = 1 |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2129 | |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 2130 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2131 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2132 | def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2133 | "shl{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2134 | [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2135 | def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2136 | "shl{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2137 | [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2138 | def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2139 | "shl{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2140 | [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 2141 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2142 | def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2143 | "shl{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 2144 | [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2145 | def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2146 | "shl{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 2147 | [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 2148 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2149 | def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2150 | "shl{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 2151 | [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2152 | |
| 2153 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2154 | def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2155 | "shl{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2156 | [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2157 | def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2158 | "shl{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2159 | [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 2160 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2161 | def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2162 | "shl{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2163 | [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 2164 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2165 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2166 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2167 | def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2168 | "shr{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2169 | [(set GR8:$dst, (srl GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2170 | def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2171 | "shr{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2172 | [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2173 | def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2174 | "shr{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2175 | [(set GR32:$dst, (srl GR32:$src, CL))]>; |
| 2176 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2177 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2178 | def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2179 | "shr{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2180 | [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2181 | def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2182 | "shr{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2183 | [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2184 | def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2185 | "shr{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2186 | [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 2187 | |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2188 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2189 | def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2190 | "shr{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2191 | [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2192 | def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2193 | "shr{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2194 | [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2195 | def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2196 | "shr{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2197 | [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>; |
| 2198 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2199 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2200 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2201 | def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2202 | "shr{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2203 | [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2204 | def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2205 | "shr{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 2206 | [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2207 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2208 | def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2209 | "shr{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2210 | [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 2211 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2212 | def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2213 | "shr{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 2214 | [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2215 | def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2216 | "shr{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 2217 | [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 2218 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2219 | def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2220 | "shr{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 2221 | [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2222 | |
| 2223 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2224 | def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2225 | "shr{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2226 | [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2227 | def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2228 | "shr{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2229 | [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2230 | def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2231 | "shr{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2232 | [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2233 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2234 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2235 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2236 | def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2237 | "sar{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2238 | [(set GR8:$dst, (sra GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2239 | def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2240 | "sar{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2241 | [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2242 | def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2243 | "sar{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2244 | [(set GR32:$dst, (sra GR32:$src, CL))]>; |
| 2245 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2246 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2247 | def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2248 | "sar{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2249 | [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2250 | def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2251 | "sar{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2252 | [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>, |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 2253 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2254 | def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2255 | "sar{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2256 | [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2257 | |
| 2258 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2259 | def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2260 | "sar{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2261 | [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2262 | def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2263 | "sar{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2264 | [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2265 | def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2266 | "sar{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2267 | [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>; |
| 2268 | |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 2269 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2270 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2271 | def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2272 | "sar{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2273 | [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2274 | def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2275 | "sar{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2276 | [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2277 | def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2278 | "sar{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2279 | [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 2280 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2281 | def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2282 | "sar{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 2283 | [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2284 | def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2285 | "sar{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 2286 | [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 2287 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2288 | def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2289 | "sar{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 2290 | [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2291 | |
| 2292 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2293 | def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2294 | "sar{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2295 | [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2296 | def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2297 | "sar{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2298 | [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 2299 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2300 | def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2301 | "sar{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2302 | [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 2303 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2304 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2305 | // Rotate instructions |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 2306 | |
| 2307 | def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src), |
| 2308 | "rcl{b}\t{1, $dst|$dst, 1}", []>; |
| 2309 | def RCL8m1 : I<0xD0, MRM2m, (outs i8mem:$dst), (ins i8mem:$src), |
| 2310 | "rcl{b}\t{1, $dst|$dst, 1}", []>; |
| 2311 | let Uses = [CL] in { |
| 2312 | def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src), |
| 2313 | "rcl{b}\t{%cl, $dst|$dst, CL}", []>; |
| 2314 | def RCL8mCL : I<0xD2, MRM2m, (outs i8mem:$dst), (ins i8mem:$src), |
| 2315 | "rcl{b}\t{%cl, $dst|$dst, CL}", []>; |
| 2316 | } |
| 2317 | def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt), |
| 2318 | "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 2319 | def RCL8mi : Ii8<0xC0, MRM2m, (outs i8mem:$dst), (ins i8mem:$src, i8imm:$cnt), |
| 2320 | "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 2321 | |
| 2322 | def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src), |
| 2323 | "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize; |
| 2324 | def RCL16m1 : I<0xD1, MRM2m, (outs i16mem:$dst), (ins i16mem:$src), |
| 2325 | "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize; |
| 2326 | let Uses = [CL] in { |
| 2327 | def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src), |
| 2328 | "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; |
| 2329 | def RCL16mCL : I<0xD3, MRM2m, (outs i16mem:$dst), (ins i16mem:$src), |
| 2330 | "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; |
| 2331 | } |
| 2332 | def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt), |
| 2333 | "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2334 | def RCL16mi : Ii8<0xC1, MRM2m, (outs i16mem:$dst), |
| 2335 | (ins i16mem:$src, i8imm:$cnt), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 2336 | "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; |
| 2337 | |
| 2338 | def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src), |
| 2339 | "rcl{l}\t{1, $dst|$dst, 1}", []>; |
| 2340 | def RCL32m1 : I<0xD1, MRM2m, (outs i32mem:$dst), (ins i32mem:$src), |
| 2341 | "rcl{l}\t{1, $dst|$dst, 1}", []>; |
| 2342 | let Uses = [CL] in { |
| 2343 | def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src), |
| 2344 | "rcl{l}\t{%cl, $dst|$dst, CL}", []>; |
| 2345 | def RCL32mCL : I<0xD3, MRM2m, (outs i32mem:$dst), (ins i32mem:$src), |
| 2346 | "rcl{l}\t{%cl, $dst|$dst, CL}", []>; |
| 2347 | } |
| 2348 | def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt), |
| 2349 | "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2350 | def RCL32mi : Ii8<0xC1, MRM2m, (outs i32mem:$dst), |
| 2351 | (ins i32mem:$src, i8imm:$cnt), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 2352 | "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 2353 | |
| 2354 | def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src), |
| 2355 | "rcr{b}\t{1, $dst|$dst, 1}", []>; |
| 2356 | def RCR8m1 : I<0xD0, MRM3m, (outs i8mem:$dst), (ins i8mem:$src), |
| 2357 | "rcr{b}\t{1, $dst|$dst, 1}", []>; |
| 2358 | let Uses = [CL] in { |
| 2359 | def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src), |
| 2360 | "rcr{b}\t{%cl, $dst|$dst, CL}", []>; |
| 2361 | def RCR8mCL : I<0xD2, MRM3m, (outs i8mem:$dst), (ins i8mem:$src), |
| 2362 | "rcr{b}\t{%cl, $dst|$dst, CL}", []>; |
| 2363 | } |
| 2364 | def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt), |
| 2365 | "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 2366 | def RCR8mi : Ii8<0xC0, MRM3m, (outs i8mem:$dst), (ins i8mem:$src, i8imm:$cnt), |
| 2367 | "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 2368 | |
| 2369 | def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src), |
| 2370 | "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize; |
| 2371 | def RCR16m1 : I<0xD1, MRM3m, (outs i16mem:$dst), (ins i16mem:$src), |
| 2372 | "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize; |
| 2373 | let Uses = [CL] in { |
| 2374 | def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src), |
| 2375 | "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; |
| 2376 | def RCR16mCL : I<0xD3, MRM3m, (outs i16mem:$dst), (ins i16mem:$src), |
| 2377 | "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; |
| 2378 | } |
| 2379 | def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt), |
| 2380 | "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2381 | def RCR16mi : Ii8<0xC1, MRM3m, (outs i16mem:$dst), |
| 2382 | (ins i16mem:$src, i8imm:$cnt), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 2383 | "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; |
| 2384 | |
| 2385 | def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src), |
| 2386 | "rcr{l}\t{1, $dst|$dst, 1}", []>; |
| 2387 | def RCR32m1 : I<0xD1, MRM3m, (outs i32mem:$dst), (ins i32mem:$src), |
| 2388 | "rcr{l}\t{1, $dst|$dst, 1}", []>; |
| 2389 | let Uses = [CL] in { |
| 2390 | def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src), |
| 2391 | "rcr{l}\t{%cl, $dst|$dst, CL}", []>; |
| 2392 | def RCR32mCL : I<0xD3, MRM3m, (outs i32mem:$dst), (ins i32mem:$src), |
| 2393 | "rcr{l}\t{%cl, $dst|$dst, CL}", []>; |
| 2394 | } |
| 2395 | def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt), |
| 2396 | "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2397 | def RCR32mi : Ii8<0xC1, MRM3m, (outs i32mem:$dst), |
| 2398 | (ins i32mem:$src, i8imm:$cnt), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 2399 | "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 2400 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2401 | // FIXME: provide shorter instructions when imm8 == 1 |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2402 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2403 | def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2404 | "rol{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2405 | [(set GR8:$dst, (rotl GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2406 | def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2407 | "rol{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2408 | [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2409 | def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2410 | "rol{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2411 | [(set GR32:$dst, (rotl GR32:$src, CL))]>; |
| 2412 | } |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2413 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2414 | def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2415 | "rol{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2416 | [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2417 | def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2418 | "rol{w}\t{$src2, $dst|$dst, $src2}", |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2419 | [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, |
| 2420 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2421 | def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2422 | "rol{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2423 | [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2424 | |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2425 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2426 | def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2427 | "rol{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2428 | [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2429 | def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2430 | "rol{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2431 | [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2432 | def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2433 | "rol{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2434 | [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>; |
| 2435 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2436 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2437 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2438 | def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2439 | "rol{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2440 | [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2441 | def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2442 | "rol{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2443 | [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2444 | def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2445 | "rol{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2446 | [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 2447 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2448 | def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2449 | "rol{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 2450 | [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2451 | def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2452 | "rol{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 2453 | [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 2454 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2455 | def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2456 | "rol{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 2457 | [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2458 | |
| 2459 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2460 | def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2461 | "rol{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2462 | [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2463 | def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2464 | "rol{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2465 | [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 2466 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2467 | def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2468 | "rol{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2469 | [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2470 | } |
| 2471 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2472 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2473 | def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2474 | "ror{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2475 | [(set GR8:$dst, (rotr GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2476 | def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2477 | "ror{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2478 | [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2479 | def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2480 | "ror{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2481 | [(set GR32:$dst, (rotr GR32:$src, CL))]>; |
| 2482 | } |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2483 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2484 | def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2485 | "ror{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2486 | [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2487 | def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2488 | "ror{w}\t{$src2, $dst|$dst, $src2}", |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2489 | [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, |
| 2490 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2491 | def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2492 | "ror{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2493 | [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2494 | |
| 2495 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2496 | def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2497 | "ror{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2498 | [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2499 | def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2500 | "ror{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2501 | [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2502 | def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2503 | "ror{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2504 | [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>; |
| 2505 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2506 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2507 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2508 | def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2509 | "ror{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2510 | [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2511 | def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2512 | "ror{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2513 | [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2514 | def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2515 | "ror{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2516 | [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 2517 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2518 | def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2519 | "ror{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 2520 | [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2521 | def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2522 | "ror{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 2523 | [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 2524 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2525 | def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2526 | "ror{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 2527 | [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2528 | |
| 2529 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2530 | def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2531 | "ror{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2532 | [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2533 | def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2534 | "ror{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2535 | [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 2536 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2537 | def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2538 | "ror{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2539 | [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2540 | } |
| 2541 | |
| 2542 | |
| 2543 | |
| 2544 | // Double shift instructions (generalizations of rotate) |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2545 | let Uses = [CL] in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2546 | def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), |
| 2547 | (ins GR32:$src1, GR32:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2548 | "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2549 | [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2550 | def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), |
| 2551 | (ins GR32:$src1, GR32:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2552 | "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2553 | [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2554 | def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), |
| 2555 | (ins GR16:$src1, GR16:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2556 | "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2557 | [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2558 | TB, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2559 | def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), |
| 2560 | (ins GR16:$src1, GR16:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2561 | "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2562 | [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2563 | TB, OpSize; |
| 2564 | } |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 2565 | |
| 2566 | let isCommutable = 1 in { // These instructions commute to each other. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2567 | def SHLD32rri8 : Ii8<0xA4, MRMDestReg, |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2568 | (outs GR32:$dst), |
| 2569 | (ins GR32:$src1, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2570 | "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2571 | [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2572 | (i8 imm:$src3)))]>, |
| 2573 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2574 | def SHRD32rri8 : Ii8<0xAC, MRMDestReg, |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2575 | (outs GR32:$dst), |
| 2576 | (ins GR32:$src1, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2577 | "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2578 | [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2579 | (i8 imm:$src3)))]>, |
| 2580 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2581 | def SHLD16rri8 : Ii8<0xA4, MRMDestReg, |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2582 | (outs GR16:$dst), |
| 2583 | (ins GR16:$src1, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2584 | "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2585 | [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2586 | (i8 imm:$src3)))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2587 | TB, OpSize; |
| 2588 | def SHRD16rri8 : Ii8<0xAC, MRMDestReg, |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2589 | (outs GR16:$dst), |
| 2590 | (ins GR16:$src1, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2591 | "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2592 | [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2593 | (i8 imm:$src3)))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2594 | TB, OpSize; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 2595 | } |
Chris Lattner | 0e967d4 | 2004-08-01 08:13:11 +0000 | [diff] [blame] | 2596 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2597 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2598 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2599 | def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2600 | "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2601 | [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2602 | addr:$dst)]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2603 | def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2604 | "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2605 | [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2606 | addr:$dst)]>, TB; |
| 2607 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2608 | def SHLD32mri8 : Ii8<0xA4, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2609 | (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2610 | "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2611 | [(store (X86shld (loadi32 addr:$dst), GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2612 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 2613 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2614 | def SHRD32mri8 : Ii8<0xAC, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2615 | (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2616 | "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2617 | [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2618 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 2619 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2620 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2621 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2622 | def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2623 | "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2624 | [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2625 | addr:$dst)]>, TB, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2626 | def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2627 | "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2628 | [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2629 | addr:$dst)]>, TB, OpSize; |
| 2630 | } |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2631 | def SHLD16mri8 : Ii8<0xA4, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2632 | (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2633 | "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2634 | [(store (X86shld (loadi16 addr:$dst), GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2635 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2636 | TB, OpSize; |
| 2637 | def SHRD16mri8 : Ii8<0xAC, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2638 | (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2639 | "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2640 | [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2641 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2642 | TB, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2643 | } |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2644 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2645 | |
| 2646 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2647 | // Arithmetic. |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2648 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2649 | let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2650 | // Register-Register Addition |
| 2651 | def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst), |
| 2652 | (ins GR8 :$src1, GR8 :$src2), |
| 2653 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2654 | [(set GR8:$dst, (add GR8:$src1, GR8:$src2)), |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2655 | (implicit EFLAGS)]>; |
| 2656 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2657 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2658 | // Register-Register Addition |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2659 | def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst), |
| 2660 | (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2661 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2662 | [(set GR16:$dst, (add GR16:$src1, GR16:$src2)), |
| 2663 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2664 | def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), |
| 2665 | (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2666 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2667 | [(set GR32:$dst, (add GR32:$src1, GR32:$src2)), |
| 2668 | (implicit EFLAGS)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2669 | } // end isConvertibleToThreeAddress |
| 2670 | } // end isCommutable |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2671 | |
| 2672 | // Register-Memory Addition |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2673 | def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst), |
| 2674 | (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2675 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2676 | [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))), |
| 2677 | (implicit EFLAGS)]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2678 | def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), |
| 2679 | (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2680 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2681 | [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))), |
| 2682 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2683 | def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), |
| 2684 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2685 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2686 | [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))), |
| 2687 | (implicit EFLAGS)]>; |
Sean Callanan | 37be590 | 2009-09-15 20:53:57 +0000 | [diff] [blame] | 2688 | |
Sean Callanan | 62c28e3 | 2009-09-15 21:43:27 +0000 | [diff] [blame] | 2689 | // Register-Register Addition - Equivalent to the normal rr forms (ADD8rr, |
| 2690 | // ADD16rr, and ADD32rr), but differently encoded. |
Sean Callanan | 37be590 | 2009-09-15 20:53:57 +0000 | [diff] [blame] | 2691 | def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 2692 | "add{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 2693 | def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), |
| 2694 | "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 2695 | def ADD32mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), |
| 2696 | "add{l}\t{$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2697 | |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2698 | // Register-Integer Addition |
| 2699 | def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
| 2700 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2701 | [(set GR8:$dst, (add GR8:$src1, imm:$src2)), |
| 2702 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2703 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2704 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2705 | // Register-Integer Addition |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2706 | def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst), |
| 2707 | (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2708 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2709 | [(set GR16:$dst, (add GR16:$src1, imm:$src2)), |
| 2710 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2711 | def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst), |
| 2712 | (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2713 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2714 | [(set GR32:$dst, (add GR32:$src1, imm:$src2)), |
| 2715 | (implicit EFLAGS)]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2716 | def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst), |
| 2717 | (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2718 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2719 | [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)), |
| 2720 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2721 | def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst), |
| 2722 | (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2723 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2724 | [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)), |
| 2725 | (implicit EFLAGS)]>; |
Evan Cheng | 09e3c80 | 2006-05-19 18:40:54 +0000 | [diff] [blame] | 2726 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2727 | |
| 2728 | let isTwoAddress = 0 in { |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2729 | // Memory-Register Addition |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2730 | def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2731 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2732 | [(store (add (load addr:$dst), GR8:$src2), addr:$dst), |
| 2733 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2734 | def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2735 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2736 | [(store (add (load addr:$dst), GR16:$src2), addr:$dst), |
| 2737 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2738 | def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2739 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2740 | [(store (add (load addr:$dst), GR32:$src2), addr:$dst), |
| 2741 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2742 | def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2743 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2744 | [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst), |
| 2745 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2746 | def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2747 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2748 | [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst), |
| 2749 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2750 | def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2751 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2752 | [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst), |
| 2753 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2754 | def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2755 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2756 | [(store (add (load addr:$dst), i16immSExt8:$src2), |
| 2757 | addr:$dst), |
| 2758 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2759 | def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2760 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2761 | [(store (add (load addr:$dst), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2762 | addr:$dst), |
| 2763 | (implicit EFLAGS)]>; |
Sean Callanan | b08ae6b | 2009-08-11 21:26:06 +0000 | [diff] [blame] | 2764 | |
| 2765 | // addition to rAX |
| 2766 | def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src), |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 2767 | "add{b}\t{$src, %al|%al, $src}", []>; |
Sean Callanan | b08ae6b | 2009-08-11 21:26:06 +0000 | [diff] [blame] | 2768 | def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src), |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 2769 | "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
Sean Callanan | b08ae6b | 2009-08-11 21:26:06 +0000 | [diff] [blame] | 2770 | def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src), |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 2771 | "add{l}\t{$src, %eax|%eax, $src}", []>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2772 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2773 | |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2774 | let Uses = [EFLAGS] in { |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2775 | let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2776 | def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2777 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2778 | [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2779 | def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst), |
| 2780 | (ins GR16:$src1, GR16:$src2), |
| 2781 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2782 | [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2783 | def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), |
| 2784 | (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2785 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2786 | [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2787 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2788 | |
| 2789 | def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 2790 | "adc{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 2791 | def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst), |
| 2792 | (ins GR16:$src1, GR16:$src2), |
| 2793 | "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 2794 | def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst), |
| 2795 | (ins GR32:$src1, GR32:$src2), |
| 2796 | "adc{l}\t{$src2, $dst|$dst, $src2}", []>; |
| 2797 | |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2798 | def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst), |
| 2799 | (ins GR8:$src1, i8mem:$src2), |
| 2800 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2801 | [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2802 | def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst), |
| 2803 | (ins GR16:$src1, i16mem:$src2), |
| 2804 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2805 | [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 2806 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2807 | def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), |
| 2808 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2809 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2810 | [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>; |
| 2811 | def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2812 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2813 | [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2814 | def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst), |
| 2815 | (ins GR16:$src1, i16imm:$src2), |
| 2816 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2817 | [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2818 | def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst), |
| 2819 | (ins GR16:$src1, i16i8imm:$src2), |
| 2820 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2821 | [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>, |
| 2822 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2823 | def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), |
| 2824 | (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2825 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2826 | [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2827 | def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), |
| 2828 | (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2829 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2830 | [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2831 | |
| 2832 | let isTwoAddress = 0 in { |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2833 | def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2834 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2835 | [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>; |
| 2836 | def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2837 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2838 | [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>, |
| 2839 | OpSize; |
| 2840 | def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2841 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2842 | [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>; |
| 2843 | def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2844 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2845 | [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
| 2846 | def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2847 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2848 | [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
| 2849 | OpSize; |
| 2850 | def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2851 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2852 | [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
| 2853 | OpSize; |
| 2854 | def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2855 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2856 | [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
| 2857 | def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2858 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2859 | [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Sean Callanan | d00025a | 2009-09-11 19:01:56 +0000 | [diff] [blame] | 2860 | |
| 2861 | def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src), |
| 2862 | "adc{b}\t{$src, %al|%al, $src}", []>; |
| 2863 | def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src), |
| 2864 | "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 2865 | def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src), |
| 2866 | "adc{l}\t{$src, %eax|%eax, $src}", []>; |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2867 | } |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2868 | } // Uses = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2869 | |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2870 | // Register-Register Subtraction |
| 2871 | def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 2872 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2873 | [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)), |
| 2874 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2875 | def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2), |
| 2876 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2877 | [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)), |
| 2878 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2879 | def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), |
| 2880 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2881 | [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)), |
| 2882 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2883 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2884 | def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 2885 | "sub{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 2886 | def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst), |
| 2887 | (ins GR16:$src1, GR16:$src2), |
| 2888 | "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 2889 | def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst), |
| 2890 | (ins GR32:$src1, GR32:$src2), |
| 2891 | "sub{l}\t{$src2, $dst|$dst, $src2}", []>; |
| 2892 | |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2893 | // Register-Memory Subtraction |
| 2894 | def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), |
| 2895 | (ins GR8 :$src1, i8mem :$src2), |
| 2896 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2897 | [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))), |
| 2898 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2899 | def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), |
| 2900 | (ins GR16:$src1, i16mem:$src2), |
| 2901 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2902 | [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))), |
| 2903 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2904 | def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), |
| 2905 | (ins GR32:$src1, i32mem:$src2), |
| 2906 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2907 | [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))), |
| 2908 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2909 | |
| 2910 | // Register-Integer Subtraction |
| 2911 | def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), |
| 2912 | (ins GR8:$src1, i8imm:$src2), |
| 2913 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2914 | [(set GR8:$dst, (sub GR8:$src1, imm:$src2)), |
| 2915 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2916 | def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), |
| 2917 | (ins GR16:$src1, i16imm:$src2), |
| 2918 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2919 | [(set GR16:$dst, (sub GR16:$src1, imm:$src2)), |
| 2920 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2921 | def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), |
| 2922 | (ins GR32:$src1, i32imm:$src2), |
| 2923 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2924 | [(set GR32:$dst, (sub GR32:$src1, imm:$src2)), |
| 2925 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2926 | def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), |
| 2927 | (ins GR16:$src1, i16i8imm:$src2), |
| 2928 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2929 | [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)), |
| 2930 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2931 | def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), |
| 2932 | (ins GR32:$src1, i32i8imm:$src2), |
| 2933 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2934 | [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)), |
| 2935 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2936 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2937 | let isTwoAddress = 0 in { |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2938 | // Memory-Register Subtraction |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2939 | def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2940 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2941 | [(store (sub (load addr:$dst), GR8:$src2), addr:$dst), |
| 2942 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2943 | def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2944 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2945 | [(store (sub (load addr:$dst), GR16:$src2), addr:$dst), |
| 2946 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2947 | def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2948 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2949 | [(store (sub (load addr:$dst), GR32:$src2), addr:$dst), |
| 2950 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2951 | |
| 2952 | // Memory-Integer Subtraction |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2953 | def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2954 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2955 | [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst), |
| 2956 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2957 | def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2958 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2959 | [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst), |
| 2960 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2961 | def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2962 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2963 | [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst), |
| 2964 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2965 | def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2966 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2967 | [(store (sub (load addr:$dst), i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2968 | addr:$dst), |
| 2969 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2970 | def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2971 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2972 | [(store (sub (load addr:$dst), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2973 | addr:$dst), |
| 2974 | (implicit EFLAGS)]>; |
Sean Callanan | d00025a | 2009-09-11 19:01:56 +0000 | [diff] [blame] | 2975 | |
| 2976 | def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src), |
| 2977 | "sub{b}\t{$src, %al|%al, $src}", []>; |
| 2978 | def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src), |
| 2979 | "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 2980 | def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src), |
| 2981 | "sub{l}\t{$src, %eax|%eax, $src}", []>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2982 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2983 | |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2984 | let Uses = [EFLAGS] in { |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2985 | def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst), |
| 2986 | (ins GR8:$src1, GR8:$src2), |
| 2987 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2988 | [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2989 | def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst), |
| 2990 | (ins GR16:$src1, GR16:$src2), |
| 2991 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2992 | [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2993 | def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), |
| 2994 | (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2995 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2996 | [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 2997 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2998 | let isTwoAddress = 0 in { |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2999 | def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), |
| 3000 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 3001 | [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 3002 | def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
| 3003 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 3004 | [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 3005 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3006 | def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3007 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 3008 | [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3009 | def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3010 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 3011 | [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 3012 | def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2), |
| 3013 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 3014 | [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 3015 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 3016 | def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
| 3017 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 3018 | [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 3019 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3020 | def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3021 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 3022 | [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3023 | def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3024 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 3025 | [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Sean Callanan | d00025a | 2009-09-11 19:01:56 +0000 | [diff] [blame] | 3026 | |
| 3027 | def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src), |
| 3028 | "sbb{b}\t{$src, %al|%al, $src}", []>; |
| 3029 | def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src), |
| 3030 | "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 3031 | def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src), |
| 3032 | "sbb{l}\t{$src, %eax|%eax, $src}", []>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 3033 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3034 | |
| 3035 | def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 3036 | "sbb{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 3037 | def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst), |
| 3038 | (ins GR16:$src1, GR16:$src2), |
| 3039 | "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 3040 | def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst), |
| 3041 | (ins GR32:$src1, GR32:$src2), |
| 3042 | "sbb{l}\t{$src2, $dst|$dst, $src2}", []>; |
| 3043 | |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 3044 | def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2), |
| 3045 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 3046 | [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 3047 | def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst), |
| 3048 | (ins GR16:$src1, i16mem:$src2), |
| 3049 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 3050 | [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 3051 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 3052 | def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), |
| 3053 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3054 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 3055 | [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 3056 | def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
| 3057 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 3058 | [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 3059 | def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst), |
| 3060 | (ins GR16:$src1, i16imm:$src2), |
| 3061 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 3062 | [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 3063 | def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst), |
| 3064 | (ins GR16:$src1, i16i8imm:$src2), |
| 3065 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 3066 | [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>, |
| 3067 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 3068 | def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), |
| 3069 | (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3070 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 3071 | [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 3072 | def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), |
| 3073 | (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3074 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 3075 | [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>; |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 3076 | } // Uses = [EFLAGS] |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 3077 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 3078 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 3079 | let Defs = [EFLAGS] in { |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 3080 | let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3081 | // Register-Register Signed Integer Multiply |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 3082 | def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3083 | "imul{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3084 | [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)), |
| 3085 | (implicit EFLAGS)]>, TB, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 3086 | def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3087 | "imul{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3088 | [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)), |
| 3089 | (implicit EFLAGS)]>, TB; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 3090 | } |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 3091 | |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3092 | // Register-Memory Signed Integer Multiply |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 3093 | def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), |
| 3094 | (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3095 | "imul{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3096 | [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))), |
| 3097 | (implicit EFLAGS)]>, TB, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3098 | def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), |
| 3099 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3100 | "imul{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3101 | [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))), |
| 3102 | (implicit EFLAGS)]>, TB; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 3103 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 3104 | } // end Two Address instructions |
| 3105 | |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 3106 | // Suprisingly enough, these are not two address instructions! |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 3107 | let Defs = [EFLAGS] in { |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3108 | // Register-Integer Signed Integer Multiply |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3109 | def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3110 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3111 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3112 | [(set GR16:$dst, (mul GR16:$src1, imm:$src2)), |
| 3113 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3114 | def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3115 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3116 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3117 | [(set GR32:$dst, (mul GR32:$src1, imm:$src2)), |
| 3118 | (implicit EFLAGS)]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3119 | def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3120 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3121 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3122 | [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)), |
| 3123 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3124 | def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3125 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3126 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3127 | [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)), |
| 3128 | (implicit EFLAGS)]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 3129 | |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3130 | // Memory-Integer Signed Integer Multiply |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3131 | def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3132 | (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3133 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3134 | [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)), |
| 3135 | (implicit EFLAGS)]>, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3136 | def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3137 | (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3138 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3139 | [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)), |
| 3140 | (implicit EFLAGS)]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3141 | def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3142 | (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3143 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 3144 | [(set GR16:$dst, (mul (load addr:$src1), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3145 | i16immSExt8:$src2)), |
| 3146 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3147 | def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3148 | (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3149 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 3150 | [(set GR32:$dst, (mul (load addr:$src1), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3151 | i32immSExt8:$src2)), |
| 3152 | (implicit EFLAGS)]>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 3153 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 3154 | |
| 3155 | //===----------------------------------------------------------------------===// |
| 3156 | // Test instructions are just like AND, except they don't generate a result. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3157 | // |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 3158 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 3159 | let isCommutable = 1 in { // TEST X, Y --> TEST Y, X |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3160 | def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3161 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 3162 | [(X86cmp (and_su GR8:$src1, GR8:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3163 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3164 | def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3165 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 3166 | [(X86cmp (and_su GR16:$src1, GR16:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3167 | (implicit EFLAGS)]>, |
| 3168 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3169 | def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3170 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 3171 | [(X86cmp (and_su GR32:$src1, GR32:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3172 | (implicit EFLAGS)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 3173 | } |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 3174 | |
Sean Callanan | 4a93b71 | 2009-09-01 18:14:18 +0000 | [diff] [blame] | 3175 | def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src), |
| 3176 | "test{b}\t{$src, %al|%al, $src}", []>; |
| 3177 | def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src), |
| 3178 | "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 3179 | def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src), |
| 3180 | "test{l}\t{$src, %eax|%eax, $src}", []>; |
| 3181 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3182 | def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3183 | "test{b}\t{$src2, $src1|$src1, $src2}", |
| 3184 | [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0), |
| 3185 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3186 | def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3187 | "test{w}\t{$src2, $src1|$src1, $src2}", |
| 3188 | [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0), |
| 3189 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3190 | def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3191 | "test{l}\t{$src2, $src1|$src1, $src2}", |
| 3192 | [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0), |
| 3193 | (implicit EFLAGS)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 3194 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3195 | def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3196 | (outs), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3197 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 3198 | [(X86cmp (and_su GR8:$src1, imm:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3199 | (implicit EFLAGS)]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3200 | def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3201 | (outs), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3202 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 3203 | [(X86cmp (and_su GR16:$src1, imm:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3204 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3205 | def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3206 | (outs), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3207 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 3208 | [(X86cmp (and_su GR32:$src1, imm:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3209 | (implicit EFLAGS)]>; |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 3210 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3211 | def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3212 | (outs), (ins i8mem:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3213 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3214 | [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0), |
| 3215 | (implicit EFLAGS)]>; |
| 3216 | def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3217 | (outs), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3218 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3219 | [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0), |
| 3220 | (implicit EFLAGS)]>, OpSize; |
| 3221 | def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3222 | (outs), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3223 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3224 | [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 3225 | (implicit EFLAGS)]>; |
| 3226 | } // Defs = [EFLAGS] |
| 3227 | |
| 3228 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 3229 | // Condition code ops, incl. set if equal/not equal/... |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 3230 | let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 3231 | def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 3232 | let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 3233 | def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 3234 | |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 3235 | let Uses = [EFLAGS] in { |
Evan Cheng | ad9c0a3 | 2009-12-15 00:53:42 +0000 | [diff] [blame] | 3236 | // Use sbb to materialize carry bit. |
| 3237 | |
| 3238 | let Defs = [EFLAGS], isCodeGenOnly = 1 in { |
| 3239 | def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), |
| 3240 | "sbb{b}\t$dst, $dst", |
| 3241 | [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; |
| 3242 | def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), |
| 3243 | "sbb{w}\t$dst, $dst", |
Evan Cheng | 2e489c4 | 2009-12-16 00:53:11 +0000 | [diff] [blame] | 3244 | [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>, |
Evan Cheng | ad9c0a3 | 2009-12-15 00:53:42 +0000 | [diff] [blame] | 3245 | OpSize; |
| 3246 | def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), |
| 3247 | "sbb{l}\t$dst, $dst", |
Evan Cheng | 2e489c4 | 2009-12-16 00:53:11 +0000 | [diff] [blame] | 3248 | [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; |
Evan Cheng | ad9c0a3 | 2009-12-15 00:53:42 +0000 | [diff] [blame] | 3249 | } // isCodeGenOnly |
| 3250 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3251 | def SETEr : I<0x94, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3252 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3253 | "sete\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3254 | [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3255 | TB; // GR8 = == |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3256 | def SETEm : I<0x94, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3257 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3258 | "sete\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3259 | [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3260 | TB; // [mem8] = == |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3261 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3262 | def SETNEr : I<0x95, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3263 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3264 | "setne\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3265 | [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3266 | TB; // GR8 = != |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3267 | def SETNEm : I<0x95, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3268 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3269 | "setne\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3270 | [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3271 | TB; // [mem8] = != |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3272 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3273 | def SETLr : I<0x9C, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3274 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3275 | "setl\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3276 | [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3277 | TB; // GR8 = < signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3278 | def SETLm : I<0x9C, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3279 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3280 | "setl\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3281 | [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3282 | TB; // [mem8] = < signed |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3283 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3284 | def SETGEr : I<0x9D, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3285 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3286 | "setge\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3287 | [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3288 | TB; // GR8 = >= signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3289 | def SETGEm : I<0x9D, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3290 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3291 | "setge\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3292 | [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3293 | TB; // [mem8] = >= signed |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3294 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3295 | def SETLEr : I<0x9E, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3296 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3297 | "setle\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3298 | [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3299 | TB; // GR8 = <= signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3300 | def SETLEm : I<0x9E, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3301 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3302 | "setle\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3303 | [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3304 | TB; // [mem8] = <= signed |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3305 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3306 | def SETGr : I<0x9F, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3307 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3308 | "setg\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3309 | [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3310 | TB; // GR8 = > signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3311 | def SETGm : I<0x9F, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3312 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3313 | "setg\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3314 | [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3315 | TB; // [mem8] = > signed |
| 3316 | |
| 3317 | def SETBr : I<0x92, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3318 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3319 | "setb\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3320 | [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3321 | TB; // GR8 = < unsign |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3322 | def SETBm : I<0x92, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3323 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3324 | "setb\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3325 | [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3326 | TB; // [mem8] = < unsign |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3327 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3328 | def SETAEr : I<0x93, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3329 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3330 | "setae\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3331 | [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3332 | TB; // GR8 = >= unsign |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3333 | def SETAEm : I<0x93, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3334 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3335 | "setae\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3336 | [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3337 | TB; // [mem8] = >= unsign |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3338 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3339 | def SETBEr : I<0x96, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3340 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3341 | "setbe\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3342 | [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3343 | TB; // GR8 = <= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3344 | def SETBEm : I<0x96, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3345 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3346 | "setbe\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3347 | [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3348 | TB; // [mem8] = <= unsign |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3349 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3350 | def SETAr : I<0x97, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3351 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3352 | "seta\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3353 | [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3354 | TB; // GR8 = > signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3355 | def SETAm : I<0x97, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3356 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3357 | "seta\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3358 | [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3359 | TB; // [mem8] = > signed |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 3360 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3361 | def SETSr : I<0x98, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3362 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3363 | "sets\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3364 | [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3365 | TB; // GR8 = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3366 | def SETSm : I<0x98, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3367 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3368 | "sets\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3369 | [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 3370 | TB; // [mem8] = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3371 | def SETNSr : I<0x99, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3372 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3373 | "setns\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3374 | [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3375 | TB; // GR8 = !<sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3376 | def SETNSm : I<0x99, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3377 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3378 | "setns\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3379 | [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 3380 | TB; // [mem8] = !<sign bit> |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3381 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3382 | def SETPr : I<0x9A, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3383 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3384 | "setp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3385 | [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3386 | TB; // GR8 = parity |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3387 | def SETPm : I<0x9A, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3388 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3389 | "setp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3390 | [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 3391 | TB; // [mem8] = parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 3392 | def SETNPr : I<0x9B, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3393 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3394 | "setnp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3395 | [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3396 | TB; // GR8 = not parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 3397 | def SETNPm : I<0x9B, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3398 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3399 | "setnp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3400 | [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 3401 | TB; // [mem8] = not parity |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3402 | |
| 3403 | def SETOr : I<0x90, MRM0r, |
| 3404 | (outs GR8 :$dst), (ins), |
| 3405 | "seto\t$dst", |
| 3406 | [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>, |
| 3407 | TB; // GR8 = overflow |
| 3408 | def SETOm : I<0x90, MRM0m, |
| 3409 | (outs), (ins i8mem:$dst), |
| 3410 | "seto\t$dst", |
| 3411 | [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>, |
| 3412 | TB; // [mem8] = overflow |
| 3413 | def SETNOr : I<0x91, MRM0r, |
| 3414 | (outs GR8 :$dst), (ins), |
| 3415 | "setno\t$dst", |
| 3416 | [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>, |
| 3417 | TB; // GR8 = not overflow |
| 3418 | def SETNOm : I<0x91, MRM0m, |
| 3419 | (outs), (ins i8mem:$dst), |
| 3420 | "setno\t$dst", |
| 3421 | [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>, |
| 3422 | TB; // [mem8] = not overflow |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 3423 | } // Uses = [EFLAGS] |
| 3424 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 3425 | |
| 3426 | // Integer comparisons |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 3427 | let Defs = [EFLAGS] in { |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 3428 | def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src), |
| 3429 | "cmp{b}\t{$src, %al|%al, $src}", []>; |
| 3430 | def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src), |
| 3431 | "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 3432 | def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src), |
| 3433 | "cmp{l}\t{$src, %eax|%eax, $src}", []>; |
| 3434 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3435 | def CMP8rr : I<0x38, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3436 | (outs), (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3437 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3438 | [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3439 | def CMP16rr : I<0x39, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3440 | (outs), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3441 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3442 | [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3443 | def CMP32rr : I<0x39, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3444 | (outs), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3445 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3446 | [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3447 | def CMP8mr : I<0x38, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3448 | (outs), (ins i8mem :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3449 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3450 | [(X86cmp (loadi8 addr:$src1), GR8:$src2), |
| 3451 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3452 | def CMP16mr : I<0x39, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3453 | (outs), (ins i16mem:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3454 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3455 | [(X86cmp (loadi16 addr:$src1), GR16:$src2), |
| 3456 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3457 | def CMP32mr : I<0x39, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3458 | (outs), (ins i32mem:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3459 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3460 | [(X86cmp (loadi32 addr:$src1), GR32:$src2), |
| 3461 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3462 | def CMP8rm : I<0x3A, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3463 | (outs), (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3464 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3465 | [(X86cmp GR8:$src1, (loadi8 addr:$src2)), |
| 3466 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3467 | def CMP16rm : I<0x3B, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3468 | (outs), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3469 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3470 | [(X86cmp GR16:$src1, (loadi16 addr:$src2)), |
| 3471 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3472 | def CMP32rm : I<0x3B, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3473 | (outs), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3474 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3475 | [(X86cmp GR32:$src1, (loadi32 addr:$src2)), |
| 3476 | (implicit EFLAGS)]>; |
Sean Callanan | d2125a0 | 2009-09-16 21:11:23 +0000 | [diff] [blame] | 3477 | def CMP8mrmrr : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2), |
| 3478 | "cmp{b}\t{$src2, $src1|$src1, $src2}", []>; |
| 3479 | def CMP16mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2), |
| 3480 | "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize; |
| 3481 | def CMP32mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2), |
| 3482 | "cmp{l}\t{$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3483 | def CMP8ri : Ii8<0x80, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3484 | (outs), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3485 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3486 | [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3487 | def CMP16ri : Ii16<0x81, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3488 | (outs), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3489 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3490 | [(X86cmp GR16:$src1, imm:$src2), |
| 3491 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3492 | def CMP32ri : Ii32<0x81, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3493 | (outs), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3494 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3495 | [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3496 | def CMP8mi : Ii8 <0x80, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3497 | (outs), (ins i8mem :$src1, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3498 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3499 | [(X86cmp (loadi8 addr:$src1), imm:$src2), |
| 3500 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3501 | def CMP16mi : Ii16<0x81, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3502 | (outs), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3503 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3504 | [(X86cmp (loadi16 addr:$src1), imm:$src2), |
| 3505 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3506 | def CMP32mi : Ii32<0x81, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3507 | (outs), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3508 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3509 | [(X86cmp (loadi32 addr:$src1), imm:$src2), |
| 3510 | (implicit EFLAGS)]>; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 3511 | def CMP16ri8 : Ii8<0x83, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3512 | (outs), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3513 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3514 | [(X86cmp GR16:$src1, i16immSExt8:$src2), |
| 3515 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 3516 | def CMP16mi8 : Ii8<0x83, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3517 | (outs), (ins i16mem:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3518 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3519 | [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2), |
| 3520 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 3521 | def CMP32mi8 : Ii8<0x83, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3522 | (outs), (ins i32mem:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3523 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3524 | [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2), |
| 3525 | (implicit EFLAGS)]>; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 3526 | def CMP32ri8 : Ii8<0x83, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3527 | (outs), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3528 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3529 | [(X86cmp GR32:$src1, i32immSExt8:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 3530 | (implicit EFLAGS)]>; |
| 3531 | } // Defs = [EFLAGS] |
| 3532 | |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 3533 | // Bit tests. |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 3534 | // TODO: BTC, BTR, and BTS |
| 3535 | let Defs = [EFLAGS] in { |
Dan Gohman | 0c89b7e | 2009-01-13 20:32:45 +0000 | [diff] [blame] | 3536 | def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 3537 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
| 3538 | [(X86bt GR16:$src1, GR16:$src2), |
Chris Lattner | f1e9fd5 | 2008-12-25 01:32:49 +0000 | [diff] [blame] | 3539 | (implicit EFLAGS)]>, OpSize, TB; |
Dan Gohman | 0c89b7e | 2009-01-13 20:32:45 +0000 | [diff] [blame] | 3540 | def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 3541 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
| 3542 | [(X86bt GR32:$src1, GR32:$src2), |
Chris Lattner | f1e9fd5 | 2008-12-25 01:32:49 +0000 | [diff] [blame] | 3543 | (implicit EFLAGS)]>, TB; |
Dan Gohman | f31408d | 2009-01-13 23:23:30 +0000 | [diff] [blame] | 3544 | |
| 3545 | // Unlike with the register+register form, the memory+register form of the |
| 3546 | // bt instruction does not ignore the high bits of the index. From ISel's |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3547 | // perspective, this is pretty bizarre. Make these instructions disassembly |
| 3548 | // only for now. |
| 3549 | |
| 3550 | def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
| 3551 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
Dan Gohman | f31408d | 2009-01-13 23:23:30 +0000 | [diff] [blame] | 3552 | // [(X86bt (loadi16 addr:$src1), GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3553 | // (implicit EFLAGS)] |
| 3554 | [] |
| 3555 | >, OpSize, TB, Requires<[FastBTMem]>; |
| 3556 | def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
| 3557 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
Dan Gohman | f31408d | 2009-01-13 23:23:30 +0000 | [diff] [blame] | 3558 | // [(X86bt (loadi32 addr:$src1), GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3559 | // (implicit EFLAGS)] |
| 3560 | [] |
| 3561 | >, TB, Requires<[FastBTMem]>; |
Dan Gohman | 4afe15b | 2009-01-13 20:33:23 +0000 | [diff] [blame] | 3562 | |
| 3563 | def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
| 3564 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
| 3565 | [(X86bt GR16:$src1, i16immSExt8:$src2), |
| 3566 | (implicit EFLAGS)]>, OpSize, TB; |
| 3567 | def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
| 3568 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
| 3569 | [(X86bt GR32:$src1, i32immSExt8:$src2), |
| 3570 | (implicit EFLAGS)]>, TB; |
| 3571 | // Note that these instructions don't need FastBTMem because that |
| 3572 | // only applies when the other operand is in a register. When it's |
| 3573 | // an immediate, bt is still fast. |
| 3574 | def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
| 3575 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
| 3576 | [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2), |
| 3577 | (implicit EFLAGS)]>, OpSize, TB; |
| 3578 | def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
| 3579 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
| 3580 | [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2), |
| 3581 | (implicit EFLAGS)]>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3582 | |
| 3583 | def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
| 3584 | "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 3585 | def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
| 3586 | "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 3587 | def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
| 3588 | "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 3589 | def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
| 3590 | "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 3591 | def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
| 3592 | "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 3593 | def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
| 3594 | "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 3595 | def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
| 3596 | "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 3597 | def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
| 3598 | "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 3599 | |
| 3600 | def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
| 3601 | "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 3602 | def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
| 3603 | "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 3604 | def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
| 3605 | "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 3606 | def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
| 3607 | "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 3608 | def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
| 3609 | "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 3610 | def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
| 3611 | "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 3612 | def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
| 3613 | "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 3614 | def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
| 3615 | "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 3616 | |
| 3617 | def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
| 3618 | "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 3619 | def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
| 3620 | "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 3621 | def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
| 3622 | "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 3623 | def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
| 3624 | "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 3625 | def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
| 3626 | "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 3627 | def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
| 3628 | "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 3629 | def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
| 3630 | "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 3631 | def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
| 3632 | "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 3633 | } // Defs = [EFLAGS] |
| 3634 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 3635 | // Sign/Zero extenders |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 3636 | // Use movsbl intead of movsbw; we don't care about the high 16 bits |
| 3637 | // of the register here. This has a smaller encoding and avoids a |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3638 | // partial-register update. Actual movsbw included for the disassembler. |
| 3639 | def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src), |
| 3640 | "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 3641 | def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), |
| 3642 | "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3643 | def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src), |
Chris Lattner | 172862a | 2009-10-19 19:51:42 +0000 | [diff] [blame] | 3644 | "", [(set GR16:$dst, (sext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3645 | def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src), |
Chris Lattner | 172862a | 2009-10-19 19:51:42 +0000 | [diff] [blame] | 3646 | "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3647 | def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3648 | "movs{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3649 | [(set GR32:$dst, (sext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3650 | def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3651 | "movs{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3652 | [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3653 | def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3654 | "movs{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3655 | [(set GR32:$dst, (sext GR16:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3656 | def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3657 | "movs{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3658 | [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB; |
Alkis Evlogimenos | a7be982 | 2004-02-17 09:14:23 +0000 | [diff] [blame] | 3659 | |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 3660 | // Use movzbl intead of movzbw; we don't care about the high 16 bits |
| 3661 | // of the register here. This has a smaller encoding and avoids a |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3662 | // partial-register update. Actual movzbw included for the disassembler. |
| 3663 | def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src), |
| 3664 | "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 3665 | def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), |
| 3666 | "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3667 | def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src), |
Chris Lattner | 172862a | 2009-10-19 19:51:42 +0000 | [diff] [blame] | 3668 | "", [(set GR16:$dst, (zext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3669 | def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src), |
Chris Lattner | 172862a | 2009-10-19 19:51:42 +0000 | [diff] [blame] | 3670 | "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3671 | def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3672 | "movz{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3673 | [(set GR32:$dst, (zext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3674 | def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3675 | "movz{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3676 | [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3677 | def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3678 | "movz{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3679 | [(set GR32:$dst, (zext GR16:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3680 | def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3681 | "movz{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3682 | [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 3683 | |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3684 | // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8 |
| 3685 | // except that they use GR32_NOREX for the output operand register class |
| 3686 | // instead of GR32. This allows them to operate on h registers on x86-64. |
| 3687 | def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg, |
| 3688 | (outs GR32_NOREX:$dst), (ins GR8:$src), |
| 3689 | "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX", |
| 3690 | []>, TB; |
Dan Gohman | 78e04d4 | 2009-04-30 03:11:48 +0000 | [diff] [blame] | 3691 | let mayLoad = 1 in |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3692 | def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem, |
| 3693 | (outs GR32_NOREX:$dst), (ins i8mem:$src), |
| 3694 | "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX", |
| 3695 | []>, TB; |
| 3696 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 3697 | let neverHasSideEffects = 1 in { |
| 3698 | let Defs = [AX], Uses = [AL] in |
| 3699 | def CBW : I<0x98, RawFrm, (outs), (ins), |
| 3700 | "{cbtw|cbw}", []>, OpSize; // AX = signext(AL) |
| 3701 | let Defs = [EAX], Uses = [AX] in |
| 3702 | def CWDE : I<0x98, RawFrm, (outs), (ins), |
| 3703 | "{cwtl|cwde}", []>; // EAX = signext(AX) |
Evan Cheng | f91c101 | 2006-05-31 22:05:11 +0000 | [diff] [blame] | 3704 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 3705 | let Defs = [AX,DX], Uses = [AX] in |
| 3706 | def CWD : I<0x99, RawFrm, (outs), (ins), |
| 3707 | "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX) |
| 3708 | let Defs = [EAX,EDX], Uses = [EAX] in |
| 3709 | def CDQ : I<0x99, RawFrm, (outs), (ins), |
| 3710 | "{cltd|cdq}", []>; // EDX:EAX = signext(EAX) |
| 3711 | } |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 3712 | |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 3713 | //===----------------------------------------------------------------------===// |
| 3714 | // Alias Instructions |
| 3715 | //===----------------------------------------------------------------------===// |
| 3716 | |
| 3717 | // Alias instructions that map movr0 to xor. |
| 3718 | // FIXME: remove when we can teach regalloc that xor reg, reg is ok. |
Daniel Dunbar | 7417b76 | 2009-08-11 22:17:52 +0000 | [diff] [blame] | 3719 | let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, |
| 3720 | isCodeGenOnly = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3721 | def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3722 | "xor{b}\t$dst, $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3723 | [(set GR8:$dst, 0)]>; |
Dan Gohman | f1b4d26 | 2010-01-12 04:42:54 +0000 | [diff] [blame] | 3724 | |
| 3725 | // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller |
| 3726 | // encoding and avoids a partial-register update sometimes, but doing so |
| 3727 | // at isel time interferes with rematerialization in the current register |
| 3728 | // allocator. For now, this is rewritten when the instruction is lowered |
| 3729 | // to an MCInst. |
| 3730 | def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins), |
| 3731 | "", |
| 3732 | [(set GR16:$dst, 0)]>, OpSize; |
Chris Lattner | 6a38182 | 2009-12-23 01:30:26 +0000 | [diff] [blame] | 3733 | |
Chris Lattner | ac105c4 | 2009-12-23 01:46:40 +0000 | [diff] [blame] | 3734 | def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), |
| 3735 | "xor{l}\t$dst, $dst", |
| 3736 | [(set GR32:$dst, 0)]>; |
| 3737 | } |
Chris Lattner | 6a38182 | 2009-12-23 01:30:26 +0000 | [diff] [blame] | 3738 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3739 | //===----------------------------------------------------------------------===// |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 3740 | // Thread Local Storage Instructions |
| 3741 | // |
| 3742 | |
Rafael Espindola | 15f1b66 | 2009-04-24 12:59:40 +0000 | [diff] [blame] | 3743 | // All calls clobber the non-callee saved registers. ESP is marked as |
| 3744 | // a use to prevent stack-pointer assignments that appear immediately |
| 3745 | // before calls from potentially appearing dead. |
| 3746 | let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, |
| 3747 | MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, |
| 3748 | XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, |
| 3749 | XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], |
Chris Lattner | 5c0b16d | 2009-06-20 20:38:48 +0000 | [diff] [blame] | 3750 | Uses = [ESP] in |
| 3751 | def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym), |
| 3752 | "leal\t$sym, %eax; " |
Dan Gohman | 4d47b9b | 2009-04-27 15:13:28 +0000 | [diff] [blame] | 3753 | "call\t___tls_get_addr@PLT", |
Chris Lattner | 5c0b16d | 2009-06-20 20:38:48 +0000 | [diff] [blame] | 3754 | [(X86tlsaddr tls32addr:$sym)]>, |
Rafael Espindola | 2ee3db3 | 2009-04-17 14:35:58 +0000 | [diff] [blame] | 3755 | Requires<[In32BitMode]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 3756 | |
Daniel Dunbar | 0c420fc | 2009-08-11 22:24:40 +0000 | [diff] [blame] | 3757 | let AddedComplexity = 5, isCodeGenOnly = 1 in |
Nate Begeman | 51a0437 | 2009-01-26 01:24:32 +0000 | [diff] [blame] | 3758 | def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
| 3759 | "movl\t%gs:$src, $dst", |
| 3760 | [(set GR32:$dst, (gsload addr:$src))]>, SegGS; |
| 3761 | |
Daniel Dunbar | 0c420fc | 2009-08-11 22:24:40 +0000 | [diff] [blame] | 3762 | let AddedComplexity = 5, isCodeGenOnly = 1 in |
Chris Lattner | 1777d0c | 2009-05-05 18:52:19 +0000 | [diff] [blame] | 3763 | def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
| 3764 | "movl\t%fs:$src, $dst", |
| 3765 | [(set GR32:$dst, (fsload addr:$src))]>, SegFS; |
| 3766 | |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 3767 | //===----------------------------------------------------------------------===// |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 3768 | // EH Pseudo Instructions |
| 3769 | // |
| 3770 | let isTerminator = 1, isReturn = 1, isBarrier = 1, |
Daniel Dunbar | 1ca3a0b | 2009-08-27 07:58:05 +0000 | [diff] [blame] | 3771 | hasCtrlDep = 1, isCodeGenOnly = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3772 | def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3773 | "ret\t#eh_return, addr: $addr", |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 3774 | [(X86ehret GR32:$addr)]>; |
| 3775 | |
| 3776 | } |
| 3777 | |
| 3778 | //===----------------------------------------------------------------------===// |
Andrew Lenharth | ab0b949 | 2008-02-21 06:45:13 +0000 | [diff] [blame] | 3779 | // Atomic support |
| 3780 | // |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 3781 | |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 3782 | // Atomic swap. These are just normal xchg instructions. But since a memory |
| 3783 | // operand is referenced, the atomicity is ensured. |
Dan Gohman | 165660e | 2008-08-06 15:52:50 +0000 | [diff] [blame] | 3784 | let Constraints = "$val = $dst" in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3785 | def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), |
| 3786 | (ins GR32:$val, i32mem:$ptr), |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 3787 | "xchg{l}\t{$val, $ptr|$ptr, $val}", |
| 3788 | [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3789 | def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), |
| 3790 | (ins GR16:$val, i16mem:$ptr), |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 3791 | "xchg{w}\t{$val, $ptr|$ptr, $val}", |
| 3792 | [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>, |
| 3793 | OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3794 | def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr), |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 3795 | "xchg{b}\t{$val, $ptr|$ptr, $val}", |
| 3796 | [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3797 | |
| 3798 | def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src), |
| 3799 | "xchg{l}\t{$val, $src|$src, $val}", []>; |
| 3800 | def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src), |
| 3801 | "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize; |
| 3802 | def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src), |
| 3803 | "xchg{b}\t{$val, $src|$src, $val}", []>; |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 3804 | } |
| 3805 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3806 | def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src), |
| 3807 | "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 3808 | def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src), |
| 3809 | "xchg{l}\t{$src, %eax|%eax, $src}", []>; |
| 3810 | |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3811 | // Atomic compare and swap. |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 3812 | let Defs = [EAX, EFLAGS], Uses = [EAX] in { |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3813 | def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap), |
Dan Gohman | 4d47b9b | 2009-04-27 15:13:28 +0000 | [diff] [blame] | 3814 | "lock\n\t" |
| 3815 | "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}", |
Evan Cheng | 32967d2 | 2008-03-04 03:20:06 +0000 | [diff] [blame] | 3816 | [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK; |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 3817 | } |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3818 | let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in { |
Evan Cheng | b093bd0 | 2010-01-08 01:29:19 +0000 | [diff] [blame] | 3819 | def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr), |
Dan Gohman | 4d47b9b | 2009-04-27 15:13:28 +0000 | [diff] [blame] | 3820 | "lock\n\t" |
| 3821 | "cmpxchg8b\t$ptr", |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 3822 | [(X86cas8 addr:$ptr)]>, TB, LOCK; |
| 3823 | } |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 3824 | |
| 3825 | let Defs = [AX, EFLAGS], Uses = [AX] in { |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3826 | def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap), |
Dan Gohman | 4d47b9b | 2009-04-27 15:13:28 +0000 | [diff] [blame] | 3827 | "lock\n\t" |
| 3828 | "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}", |
Evan Cheng | 32967d2 | 2008-03-04 03:20:06 +0000 | [diff] [blame] | 3829 | [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK; |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 3830 | } |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 3831 | let Defs = [AL, EFLAGS], Uses = [AL] in { |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3832 | def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap), |
Dan Gohman | 4d47b9b | 2009-04-27 15:13:28 +0000 | [diff] [blame] | 3833 | "lock\n\t" |
| 3834 | "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}", |
Evan Cheng | 32967d2 | 2008-03-04 03:20:06 +0000 | [diff] [blame] | 3835 | [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK; |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 3836 | } |
| 3837 | |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3838 | // Atomic exchange and add |
| 3839 | let Constraints = "$val = $dst", Defs = [EFLAGS] in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3840 | def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr), |
Dan Gohman | 4d47b9b | 2009-04-27 15:13:28 +0000 | [diff] [blame] | 3841 | "lock\n\t" |
| 3842 | "xadd{l}\t{$val, $ptr|$ptr, $val}", |
Mon P Wang | 2887310 | 2008-06-25 08:15:39 +0000 | [diff] [blame] | 3843 | [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>, |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3844 | TB, LOCK; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3845 | def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr), |
Dan Gohman | 4d47b9b | 2009-04-27 15:13:28 +0000 | [diff] [blame] | 3846 | "lock\n\t" |
| 3847 | "xadd{w}\t{$val, $ptr|$ptr, $val}", |
Mon P Wang | 2887310 | 2008-06-25 08:15:39 +0000 | [diff] [blame] | 3848 | [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>, |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3849 | TB, OpSize, LOCK; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3850 | def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr), |
Dan Gohman | 4d47b9b | 2009-04-27 15:13:28 +0000 | [diff] [blame] | 3851 | "lock\n\t" |
| 3852 | "xadd{b}\t{$val, $ptr|$ptr, $val}", |
Mon P Wang | 2887310 | 2008-06-25 08:15:39 +0000 | [diff] [blame] | 3853 | [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>, |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3854 | TB, LOCK; |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 3855 | } |
| 3856 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3857 | def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), |
| 3858 | "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB; |
| 3859 | def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), |
| 3860 | "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 3861 | def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), |
| 3862 | "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB; |
| 3863 | |
| 3864 | def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), |
| 3865 | "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB; |
| 3866 | def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
| 3867 | "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 3868 | def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
| 3869 | "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB; |
| 3870 | |
| 3871 | def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), |
| 3872 | "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB; |
| 3873 | def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), |
| 3874 | "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 3875 | def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), |
| 3876 | "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB; |
| 3877 | |
| 3878 | def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), |
| 3879 | "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB; |
| 3880 | def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
| 3881 | "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 3882 | def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
| 3883 | "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB; |
| 3884 | |
Evan Cheng | b093bd0 | 2010-01-08 01:29:19 +0000 | [diff] [blame] | 3885 | let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3886 | def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), |
| 3887 | "cmpxchg8b\t$dst", []>, TB; |
| 3888 | |
Evan Cheng | 37b7387 | 2009-07-30 08:33:02 +0000 | [diff] [blame] | 3889 | // Optimized codegen when the non-memory output is not used. |
| 3890 | // FIXME: Use normal add / sub instructions and add lock prefix dynamically. |
Dan Gohman | bab42bd | 2009-10-20 18:14:49 +0000 | [diff] [blame] | 3891 | let Defs = [EFLAGS] in { |
Evan Cheng | 37b7387 | 2009-07-30 08:33:02 +0000 | [diff] [blame] | 3892 | def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), |
| 3893 | "lock\n\t" |
| 3894 | "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3895 | def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
| 3896 | "lock\n\t" |
| 3897 | "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK; |
| 3898 | def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
| 3899 | "lock\n\t" |
| 3900 | "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3901 | def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2), |
| 3902 | "lock\n\t" |
| 3903 | "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3904 | def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2), |
| 3905 | "lock\n\t" |
| 3906 | "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3907 | def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2), |
| 3908 | "lock\n\t" |
| 3909 | "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3910 | def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
| 3911 | "lock\n\t" |
| 3912 | "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK; |
| 3913 | def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
| 3914 | "lock\n\t" |
| 3915 | "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3916 | |
| 3917 | def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), |
| 3918 | "lock\n\t" |
| 3919 | "inc{b}\t$dst", []>, LOCK; |
| 3920 | def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), |
| 3921 | "lock\n\t" |
| 3922 | "inc{w}\t$dst", []>, OpSize, LOCK; |
| 3923 | def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), |
| 3924 | "lock\n\t" |
| 3925 | "inc{l}\t$dst", []>, LOCK; |
| 3926 | |
| 3927 | def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2), |
| 3928 | "lock\n\t" |
| 3929 | "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3930 | def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
| 3931 | "lock\n\t" |
| 3932 | "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK; |
| 3933 | def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
| 3934 | "lock\n\t" |
| 3935 | "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3936 | def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2), |
| 3937 | "lock\n\t" |
| 3938 | "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3939 | def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2), |
| 3940 | "lock\n\t" |
| 3941 | "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK; |
| 3942 | def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2), |
| 3943 | "lock\n\t" |
| 3944 | "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 3945 | def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
Evan Cheng | 37b7387 | 2009-07-30 08:33:02 +0000 | [diff] [blame] | 3946 | "lock\n\t" |
| 3947 | "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK; |
| 3948 | def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
| 3949 | "lock\n\t" |
| 3950 | "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3951 | |
| 3952 | def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), |
| 3953 | "lock\n\t" |
| 3954 | "dec{b}\t$dst", []>, LOCK; |
| 3955 | def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), |
| 3956 | "lock\n\t" |
| 3957 | "dec{w}\t$dst", []>, OpSize, LOCK; |
| 3958 | def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), |
| 3959 | "lock\n\t" |
| 3960 | "dec{l}\t$dst", []>, LOCK; |
Dan Gohman | bab42bd | 2009-10-20 18:14:49 +0000 | [diff] [blame] | 3961 | } |
Evan Cheng | 37b7387 | 2009-07-30 08:33:02 +0000 | [diff] [blame] | 3962 | |
Mon P Wang | 2887310 | 2008-06-25 08:15:39 +0000 | [diff] [blame] | 3963 | // Atomic exchange, and, or, xor |
Mon P Wang | 63307c3 | 2008-05-05 19:05:59 +0000 | [diff] [blame] | 3964 | let Constraints = "$val = $dst", Defs = [EFLAGS], |
Dan Gohman | 533297b | 2009-10-29 18:10:34 +0000 | [diff] [blame] | 3965 | usesCustomInserter = 1 in { |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3966 | def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3967 | "#ATOMAND32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3968 | [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3969 | def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3970 | "#ATOMOR32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3971 | [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3972 | def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3973 | "#ATOMXOR32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3974 | [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>; |
Andrew Lenharth | 507a58a | 2008-06-14 05:48:15 +0000 | [diff] [blame] | 3975 | def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3976 | "#ATOMNAND32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3977 | [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3978 | def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3979 | "#ATOMMIN32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3980 | [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3981 | def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3982 | "#ATOMMAX32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3983 | [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3984 | def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3985 | "#ATOMUMIN32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3986 | [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3987 | def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3988 | "#ATOMUMAX32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3989 | [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3990 | |
| 3991 | def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3992 | "#ATOMAND16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3993 | [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3994 | def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3995 | "#ATOMOR16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3996 | [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3997 | def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3998 | "#ATOMXOR16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3999 | [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 4000 | def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 4001 | "#ATOMNAND16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 4002 | [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 4003 | def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 4004 | "#ATOMMIN16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 4005 | [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 4006 | def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 4007 | "#ATOMMAX16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 4008 | [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 4009 | def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 4010 | "#ATOMUMIN16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 4011 | [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 4012 | def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 4013 | "#ATOMUMAX16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 4014 | [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 4015 | |
| 4016 | def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 4017 | "#ATOMAND8 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 4018 | [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 4019 | def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 4020 | "#ATOMOR8 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 4021 | [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 4022 | def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 4023 | "#ATOMXOR8 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 4024 | [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 4025 | def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 4026 | "#ATOMNAND8 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 4027 | [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>; |
Mon P Wang | 63307c3 | 2008-05-05 19:05:59 +0000 | [diff] [blame] | 4028 | } |
| 4029 | |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 4030 | let Constraints = "$val1 = $dst1, $val2 = $dst2", |
| 4031 | Defs = [EFLAGS, EAX, EBX, ECX, EDX], |
| 4032 | Uses = [EAX, EBX, ECX, EDX], |
Dale Johannesen | 1b54c7f | 2008-10-03 19:41:08 +0000 | [diff] [blame] | 4033 | mayLoad = 1, mayStore = 1, |
Dan Gohman | 533297b | 2009-10-29 18:10:34 +0000 | [diff] [blame] | 4034 | usesCustomInserter = 1 in { |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 4035 | def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 4036 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 4037 | "#ATOMAND6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 4038 | def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 4039 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 4040 | "#ATOMOR6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 4041 | def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 4042 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 4043 | "#ATOMXOR6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 4044 | def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 4045 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 4046 | "#ATOMNAND6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 4047 | def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 4048 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 4049 | "#ATOMADD6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 4050 | def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 4051 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 4052 | "#ATOMSUB6432 PSEUDO!", []>; |
Dale Johannesen | 880ae36 | 2008-10-03 22:25:52 +0000 | [diff] [blame] | 4053 | def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 4054 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 4055 | "#ATOMSWAP6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 4056 | } |
| 4057 | |
Sean Callanan | 358f1ef | 2009-09-16 21:55:34 +0000 | [diff] [blame] | 4058 | // Segmentation support instructions. |
| 4059 | |
| 4060 | def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
| 4061 | "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 4062 | def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
| 4063 | "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 4064 | |
| 4065 | // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo. |
| 4066 | def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), |
| 4067 | "lar{l}\t{$src, $dst|$dst, $src}", []>, TB; |
| 4068 | def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
| 4069 | "lar{l}\t{$src, $dst|$dst, $src}", []>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 4070 | |
| 4071 | def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
| 4072 | "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 4073 | def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
| 4074 | "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 4075 | def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
| 4076 | "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB; |
| 4077 | def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
| 4078 | "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB; |
| 4079 | |
| 4080 | def INVLPG : I<0x01, RawFrm, (outs), (ins), "invlpg", []>, TB; |
| 4081 | |
| 4082 | def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins), |
| 4083 | "str{w}\t{$dst}", []>, TB; |
| 4084 | def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins), |
| 4085 | "str{w}\t{$dst}", []>, TB; |
| 4086 | def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), |
| 4087 | "ltr{w}\t{$src}", []>, TB; |
| 4088 | def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), |
| 4089 | "ltr{w}\t{$src}", []>, TB; |
| 4090 | |
| 4091 | def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), |
| 4092 | "push{w}\t%fs", []>, OpSize, TB; |
| 4093 | def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), |
| 4094 | "push{l}\t%fs", []>, TB; |
| 4095 | def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), |
| 4096 | "push{w}\t%gs", []>, OpSize, TB; |
| 4097 | def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), |
| 4098 | "push{l}\t%gs", []>, TB; |
| 4099 | |
| 4100 | def POPFS16 : I<0xa1, RawFrm, (outs), (ins), |
| 4101 | "pop{w}\t%fs", []>, OpSize, TB; |
| 4102 | def POPFS32 : I<0xa1, RawFrm, (outs), (ins), |
| 4103 | "pop{l}\t%fs", []>, TB; |
| 4104 | def POPGS16 : I<0xa9, RawFrm, (outs), (ins), |
| 4105 | "pop{w}\t%gs", []>, OpSize, TB; |
| 4106 | def POPGS32 : I<0xa9, RawFrm, (outs), (ins), |
| 4107 | "pop{l}\t%gs", []>, TB; |
| 4108 | |
| 4109 | def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), |
| 4110 | "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize; |
| 4111 | def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), |
| 4112 | "lds{l}\t{$src, $dst|$dst, $src}", []>; |
| 4113 | def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), |
| 4114 | "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 4115 | def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), |
| 4116 | "lss{l}\t{$src, $dst|$dst, $src}", []>, TB; |
| 4117 | def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), |
| 4118 | "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize; |
| 4119 | def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), |
| 4120 | "les{l}\t{$src, $dst|$dst, $src}", []>; |
| 4121 | def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), |
| 4122 | "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 4123 | def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), |
| 4124 | "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB; |
| 4125 | def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), |
| 4126 | "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 4127 | def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), |
| 4128 | "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB; |
| 4129 | |
| 4130 | def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), |
| 4131 | "verr\t$seg", []>, TB; |
| 4132 | def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), |
| 4133 | "verr\t$seg", []>, TB; |
| 4134 | def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), |
| 4135 | "verw\t$seg", []>, TB; |
| 4136 | def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), |
| 4137 | "verw\t$seg", []>, TB; |
| 4138 | |
| 4139 | // Descriptor-table support instructions |
| 4140 | |
| 4141 | def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins), |
| 4142 | "sgdt\t$dst", []>, TB; |
| 4143 | def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins), |
| 4144 | "sidt\t$dst", []>, TB; |
| 4145 | def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins), |
| 4146 | "sldt{w}\t$dst", []>, TB; |
| 4147 | def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins), |
| 4148 | "sldt{w}\t$dst", []>, TB; |
| 4149 | def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src), |
| 4150 | "lgdt\t$src", []>, TB; |
| 4151 | def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src), |
| 4152 | "lidt\t$src", []>, TB; |
| 4153 | def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src), |
| 4154 | "lldt{w}\t$src", []>, TB; |
| 4155 | def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src), |
| 4156 | "lldt{w}\t$src", []>, TB; |
Sean Callanan | 9a86f10 | 2009-09-16 22:59:28 +0000 | [diff] [blame] | 4157 | |
| 4158 | // String manipulation instructions |
| 4159 | |
| 4160 | def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>; |
| 4161 | def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 4162 | def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>; |
| 4163 | |
| 4164 | def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>; |
| 4165 | def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize; |
| 4166 | def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>; |
| 4167 | |
| 4168 | // CPU flow control instructions |
| 4169 | |
| 4170 | def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>; |
| 4171 | def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB; |
| 4172 | |
| 4173 | // FPU control instructions |
| 4174 | |
| 4175 | def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB; |
| 4176 | |
| 4177 | // Flag instructions |
| 4178 | |
| 4179 | def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>; |
| 4180 | def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>; |
| 4181 | def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>; |
| 4182 | def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>; |
| 4183 | def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>; |
| 4184 | def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>; |
| 4185 | def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>; |
| 4186 | |
| 4187 | def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB; |
| 4188 | |
| 4189 | // Table lookup instructions |
| 4190 | |
| 4191 | def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>; |
| 4192 | |
| 4193 | // Specialized register support |
| 4194 | |
| 4195 | def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB; |
| 4196 | def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB; |
| 4197 | def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB; |
| 4198 | |
| 4199 | def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins), |
| 4200 | "smsw{w}\t$dst", []>, OpSize, TB; |
| 4201 | def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins), |
| 4202 | "smsw{l}\t$dst", []>, TB; |
| 4203 | // For memory operands, there is only a 16-bit form |
| 4204 | def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins), |
| 4205 | "smsw{w}\t$dst", []>, TB; |
| 4206 | |
| 4207 | def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src), |
| 4208 | "lmsw{w}\t$src", []>, TB; |
| 4209 | def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src), |
| 4210 | "lmsw{w}\t$src", []>, TB; |
| 4211 | |
| 4212 | def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB; |
| 4213 | |
| 4214 | // Cache instructions |
| 4215 | |
| 4216 | def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB; |
| 4217 | def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB; |
| 4218 | |
| 4219 | // VMX instructions |
| 4220 | |
| 4221 | // 66 0F 38 80 |
| 4222 | def INVEPT : I<0x38, RawFrm, (outs), (ins), "invept", []>, OpSize, TB; |
| 4223 | // 66 0F 38 81 |
| 4224 | def INVVPID : I<0x38, RawFrm, (outs), (ins), "invvpid", []>, OpSize, TB; |
| 4225 | // 0F 01 C1 |
| 4226 | def VMCALL : I<0x01, RawFrm, (outs), (ins), "vmcall", []>, TB; |
| 4227 | def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs), |
| 4228 | "vmclear\t$vmcs", []>, OpSize, TB; |
| 4229 | // 0F 01 C2 |
| 4230 | def VMLAUNCH : I<0x01, RawFrm, (outs), (ins), "vmlaunch", []>, TB; |
| 4231 | // 0F 01 C3 |
| 4232 | def VMRESUME : I<0x01, RawFrm, (outs), (ins), "vmresume", []>, TB; |
| 4233 | def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs), |
| 4234 | "vmptrld\t$vmcs", []>, TB; |
| 4235 | def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins), |
| 4236 | "vmptrst\t$vmcs", []>, TB; |
| 4237 | def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src), |
| 4238 | "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB; |
| 4239 | def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), |
| 4240 | "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB; |
| 4241 | def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src), |
| 4242 | "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB; |
| 4243 | def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), |
| 4244 | "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB; |
| 4245 | def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), |
| 4246 | "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB; |
| 4247 | def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), |
| 4248 | "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB; |
| 4249 | def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
| 4250 | "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB; |
| 4251 | def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
| 4252 | "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB; |
| 4253 | // 0F 01 C4 |
| 4254 | def VMXOFF : I<0x01, RawFrm, (outs), (ins), "vmxoff", []>, OpSize; |
| 4255 | def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon), |
| 4256 | "vmxon\t{$vmxon}", []>, XD; |
Sean Callanan | 358f1ef | 2009-09-16 21:55:34 +0000 | [diff] [blame] | 4257 | |
Andrew Lenharth | ab0b949 | 2008-02-21 06:45:13 +0000 | [diff] [blame] | 4258 | //===----------------------------------------------------------------------===// |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 4259 | // Non-Instruction Patterns |
| 4260 | //===----------------------------------------------------------------------===// |
| 4261 | |
Bill Wendling | 056292f | 2008-09-16 21:48:12 +0000 | [diff] [blame] | 4262 | // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 4263 | def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>; |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 4264 | def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>; |
Nate Begeman | 6795ebb | 2008-04-12 00:47:57 +0000 | [diff] [blame] | 4265 | def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 4266 | def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>; |
| 4267 | def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>; |
Dan Gohman | f705adb | 2009-10-30 01:28:02 +0000 | [diff] [blame] | 4268 | def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 4269 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4270 | def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)), |
| 4271 | (ADD32ri GR32:$src1, tconstpool:$src2)>; |
| 4272 | def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)), |
| 4273 | (ADD32ri GR32:$src1, tjumptable:$src2)>; |
| 4274 | def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)), |
| 4275 | (ADD32ri GR32:$src1, tglobaladdr:$src2)>; |
| 4276 | def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)), |
| 4277 | (ADD32ri GR32:$src1, texternalsym:$src2)>; |
Dan Gohman | f705adb | 2009-10-30 01:28:02 +0000 | [diff] [blame] | 4278 | def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)), |
| 4279 | (ADD32ri GR32:$src1, tblockaddress:$src2)>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 4280 | |
Evan Cheng | fc8feb1 | 2006-05-19 07:30:36 +0000 | [diff] [blame] | 4281 | def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst), |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 4282 | (MOV32mi addr:$dst, tglobaladdr:$src)>; |
Evan Cheng | fc8feb1 | 2006-05-19 07:30:36 +0000 | [diff] [blame] | 4283 | def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst), |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 4284 | (MOV32mi addr:$dst, texternalsym:$src)>; |
Dan Gohman | f705adb | 2009-10-30 01:28:02 +0000 | [diff] [blame] | 4285 | def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst), |
| 4286 | (MOV32mi addr:$dst, tblockaddress:$src)>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 4287 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 4288 | // Calls |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 4289 | // tailcall stuff |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 4290 | def : Pat<(X86tcret GR32:$dst, imm:$off), |
| 4291 | (TCRETURNri GR32:$dst, imm:$off)>; |
| 4292 | |
| 4293 | def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), |
| 4294 | (TCRETURNdi texternalsym:$dst, imm:$off)>; |
| 4295 | |
| 4296 | def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), |
| 4297 | (TCRETURNdi texternalsym:$dst, imm:$off)>; |
Evan Cheng | fea89c1 | 2006-04-27 08:40:39 +0000 | [diff] [blame] | 4298 | |
Dan Gohman | cadb226 | 2009-08-02 16:10:01 +0000 | [diff] [blame] | 4299 | // Normal calls, with various flavors of addresses. |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4300 | def : Pat<(X86call (i32 tglobaladdr:$dst)), |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 4301 | (CALLpcrel32 tglobaladdr:$dst)>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4302 | def : Pat<(X86call (i32 texternalsym:$dst)), |
Evan Cheng | 8700e14 | 2006-01-11 06:09:51 +0000 | [diff] [blame] | 4303 | (CALLpcrel32 texternalsym:$dst)>; |
Evan Cheng | d7f666a | 2009-05-20 04:53:57 +0000 | [diff] [blame] | 4304 | def : Pat<(X86call (i32 imm:$dst)), |
| 4305 | (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 4306 | |
| 4307 | // X86 specific add which produces a flag. |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4308 | def : Pat<(addc GR32:$src1, GR32:$src2), |
| 4309 | (ADD32rr GR32:$src1, GR32:$src2)>; |
| 4310 | def : Pat<(addc GR32:$src1, (load addr:$src2)), |
| 4311 | (ADD32rm GR32:$src1, addr:$src2)>; |
| 4312 | def : Pat<(addc GR32:$src1, imm:$src2), |
| 4313 | (ADD32ri GR32:$src1, imm:$src2)>; |
| 4314 | def : Pat<(addc GR32:$src1, i32immSExt8:$src2), |
| 4315 | (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 4316 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4317 | def : Pat<(subc GR32:$src1, GR32:$src2), |
| 4318 | (SUB32rr GR32:$src1, GR32:$src2)>; |
| 4319 | def : Pat<(subc GR32:$src1, (load addr:$src2)), |
| 4320 | (SUB32rm GR32:$src1, addr:$src2)>; |
| 4321 | def : Pat<(subc GR32:$src1, imm:$src2), |
| 4322 | (SUB32ri GR32:$src1, imm:$src2)>; |
| 4323 | def : Pat<(subc GR32:$src1, i32immSExt8:$src2), |
| 4324 | (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 4325 | |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 4326 | // Comparisons. |
| 4327 | |
| 4328 | // TEST R,R is smaller than CMP R,0 |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 4329 | def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 4330 | (TEST8rr GR8:$src1, GR8:$src1)>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 4331 | def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)), |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 4332 | (TEST16rr GR16:$src1, GR16:$src1)>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 4333 | def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)), |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 4334 | (TEST32rr GR32:$src1, GR32:$src1)>; |
| 4335 | |
Dan Gohman | fbb7486 | 2009-01-07 01:00:24 +0000 | [diff] [blame] | 4336 | // Conditional moves with folded loads with operands swapped and conditions |
| 4337 | // inverted. |
| 4338 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS), |
| 4339 | (CMOVAE16rm GR16:$src2, addr:$src1)>; |
| 4340 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS), |
| 4341 | (CMOVAE32rm GR32:$src2, addr:$src1)>; |
| 4342 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS), |
| 4343 | (CMOVB16rm GR16:$src2, addr:$src1)>; |
| 4344 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS), |
| 4345 | (CMOVB32rm GR32:$src2, addr:$src1)>; |
| 4346 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS), |
| 4347 | (CMOVNE16rm GR16:$src2, addr:$src1)>; |
| 4348 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS), |
| 4349 | (CMOVNE32rm GR32:$src2, addr:$src1)>; |
| 4350 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS), |
| 4351 | (CMOVE16rm GR16:$src2, addr:$src1)>; |
| 4352 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS), |
| 4353 | (CMOVE32rm GR32:$src2, addr:$src1)>; |
| 4354 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS), |
| 4355 | (CMOVA16rm GR16:$src2, addr:$src1)>; |
| 4356 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS), |
| 4357 | (CMOVA32rm GR32:$src2, addr:$src1)>; |
| 4358 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS), |
| 4359 | (CMOVBE16rm GR16:$src2, addr:$src1)>; |
| 4360 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS), |
| 4361 | (CMOVBE32rm GR32:$src2, addr:$src1)>; |
| 4362 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS), |
| 4363 | (CMOVGE16rm GR16:$src2, addr:$src1)>; |
| 4364 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS), |
| 4365 | (CMOVGE32rm GR32:$src2, addr:$src1)>; |
| 4366 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS), |
| 4367 | (CMOVL16rm GR16:$src2, addr:$src1)>; |
| 4368 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS), |
| 4369 | (CMOVL32rm GR32:$src2, addr:$src1)>; |
| 4370 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS), |
| 4371 | (CMOVG16rm GR16:$src2, addr:$src1)>; |
| 4372 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS), |
| 4373 | (CMOVG32rm GR32:$src2, addr:$src1)>; |
| 4374 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS), |
| 4375 | (CMOVLE16rm GR16:$src2, addr:$src1)>; |
| 4376 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS), |
| 4377 | (CMOVLE32rm GR32:$src2, addr:$src1)>; |
| 4378 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS), |
| 4379 | (CMOVNP16rm GR16:$src2, addr:$src1)>; |
| 4380 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS), |
| 4381 | (CMOVNP32rm GR32:$src2, addr:$src1)>; |
| 4382 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS), |
| 4383 | (CMOVP16rm GR16:$src2, addr:$src1)>; |
| 4384 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS), |
| 4385 | (CMOVP32rm GR32:$src2, addr:$src1)>; |
| 4386 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS), |
| 4387 | (CMOVNS16rm GR16:$src2, addr:$src1)>; |
| 4388 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS), |
| 4389 | (CMOVNS32rm GR32:$src2, addr:$src1)>; |
| 4390 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS), |
| 4391 | (CMOVS16rm GR16:$src2, addr:$src1)>; |
| 4392 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS), |
| 4393 | (CMOVS32rm GR32:$src2, addr:$src1)>; |
| 4394 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS), |
| 4395 | (CMOVNO16rm GR16:$src2, addr:$src1)>; |
| 4396 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS), |
| 4397 | (CMOVNO32rm GR32:$src2, addr:$src1)>; |
| 4398 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS), |
| 4399 | (CMOVO16rm GR16:$src2, addr:$src1)>; |
| 4400 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS), |
| 4401 | (CMOVO32rm GR32:$src2, addr:$src1)>; |
| 4402 | |
Duncan Sands | f9c98e6 | 2008-01-23 20:39:46 +0000 | [diff] [blame] | 4403 | // zextload bool -> zextload byte |
Evan Cheng | e5d9343 | 2006-01-17 07:02:46 +0000 | [diff] [blame] | 4404 | def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 4405 | def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; |
| 4406 | def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; |
| 4407 | |
| 4408 | // extload bool -> extload byte |
Evan Cheng | 4713724 | 2006-05-05 08:23:07 +0000 | [diff] [blame] | 4409 | def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; |
Dan Gohman | af70e5c | 2009-08-26 14:59:13 +0000 | [diff] [blame] | 4410 | def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; |
Evan Cheng | 4713724 | 2006-05-05 08:23:07 +0000 | [diff] [blame] | 4411 | def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; |
Dan Gohman | af70e5c | 2009-08-26 14:59:13 +0000 | [diff] [blame] | 4412 | def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; |
Evan Cheng | 4713724 | 2006-05-05 08:23:07 +0000 | [diff] [blame] | 4413 | def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; |
| 4414 | def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 4415 | |
Dan Gohman | af70e5c | 2009-08-26 14:59:13 +0000 | [diff] [blame] | 4416 | // anyext. Define these to do an explicit zero-extend to |
| 4417 | // avoid partial-register updates. |
| 4418 | def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>; |
| 4419 | def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; |
| 4420 | def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 4421 | |
Evan Cheng | 1314b00 | 2007-12-13 00:43:27 +0000 | [diff] [blame] | 4422 | // (and (i32 load), 255) -> (zextload i8) |
Evan Cheng | d47e0b6 | 2008-09-29 17:26:18 +0000 | [diff] [blame] | 4423 | def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))), |
| 4424 | (MOVZX32rm8 addr:$src)>; |
| 4425 | def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))), |
| 4426 | (MOVZX32rm16 addr:$src)>; |
Evan Cheng | 1314b00 | 2007-12-13 00:43:27 +0000 | [diff] [blame] | 4427 | |
Evan Cheng | cfa260b | 2006-01-06 02:31:59 +0000 | [diff] [blame] | 4428 | //===----------------------------------------------------------------------===// |
| 4429 | // Some peepholes |
| 4430 | //===----------------------------------------------------------------------===// |
| 4431 | |
Dan Gohman | 63f9720 | 2008-10-17 01:33:43 +0000 | [diff] [blame] | 4432 | // Odd encoding trick: -128 fits into an 8-bit immediate field while |
| 4433 | // +128 doesn't, so in this special case use a sub instead of an add. |
| 4434 | def : Pat<(add GR16:$src1, 128), |
| 4435 | (SUB16ri8 GR16:$src1, -128)>; |
| 4436 | def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), |
| 4437 | (SUB16mi8 addr:$dst, -128)>; |
| 4438 | def : Pat<(add GR32:$src1, 128), |
| 4439 | (SUB32ri8 GR32:$src1, -128)>; |
| 4440 | def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), |
| 4441 | (SUB32mi8 addr:$dst, -128)>; |
| 4442 | |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 4443 | // r & (2^16-1) ==> movz |
| 4444 | def : Pat<(and GR32:$src1, 0xffff), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4445 | (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>; |
Dan Gohman | 8a1510d | 2008-08-06 18:27:21 +0000 | [diff] [blame] | 4446 | // r & (2^8-1) ==> movz |
| 4447 | def : Pat<(and GR32:$src1, 0xff), |
Anton Korobeynikov | 3a639a0 | 2009-11-02 00:11:39 +0000 | [diff] [blame] | 4448 | (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1, |
| 4449 | GR32_ABCD)), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4450 | x86_subreg_8bit))>, |
Dan Gohman | 8a1510d | 2008-08-06 18:27:21 +0000 | [diff] [blame] | 4451 | Requires<[In32BitMode]>; |
| 4452 | // r & (2^8-1) ==> movz |
| 4453 | def : Pat<(and GR16:$src1, 0xff), |
Anton Korobeynikov | 3a639a0 | 2009-11-02 00:11:39 +0000 | [diff] [blame] | 4454 | (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1, |
| 4455 | GR16_ABCD)), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4456 | x86_subreg_8bit))>, |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 4457 | Requires<[In32BitMode]>; |
| 4458 | |
| 4459 | // sext_inreg patterns |
| 4460 | def : Pat<(sext_inreg GR32:$src, i16), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4461 | (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>; |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 4462 | def : Pat<(sext_inreg GR32:$src, i8), |
Anton Korobeynikov | 3a639a0 | 2009-11-02 00:11:39 +0000 | [diff] [blame] | 4463 | (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, |
| 4464 | GR32_ABCD)), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4465 | x86_subreg_8bit))>, |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 4466 | Requires<[In32BitMode]>; |
| 4467 | def : Pat<(sext_inreg GR16:$src, i8), |
Anton Korobeynikov | 3a639a0 | 2009-11-02 00:11:39 +0000 | [diff] [blame] | 4468 | (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, |
| 4469 | GR16_ABCD)), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4470 | x86_subreg_8bit))>, |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 4471 | Requires<[In32BitMode]>; |
| 4472 | |
| 4473 | // trunc patterns |
| 4474 | def : Pat<(i16 (trunc GR32:$src)), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4475 | (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>; |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 4476 | def : Pat<(i8 (trunc GR32:$src)), |
Anton Korobeynikov | 3a639a0 | 2009-11-02 00:11:39 +0000 | [diff] [blame] | 4477 | (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4478 | x86_subreg_8bit)>, |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 4479 | Requires<[In32BitMode]>; |
| 4480 | def : Pat<(i8 (trunc GR16:$src)), |
Anton Korobeynikov | 3a639a0 | 2009-11-02 00:11:39 +0000 | [diff] [blame] | 4481 | (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4482 | x86_subreg_8bit)>, |
| 4483 | Requires<[In32BitMode]>; |
| 4484 | |
| 4485 | // h-register tricks |
| 4486 | def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), |
Anton Korobeynikov | 3a639a0 | 2009-11-02 00:11:39 +0000 | [diff] [blame] | 4487 | (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4488 | x86_subreg_8bit_hi)>, |
| 4489 | Requires<[In32BitMode]>; |
| 4490 | def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), |
Anton Korobeynikov | 3a639a0 | 2009-11-02 00:11:39 +0000 | [diff] [blame] | 4491 | (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4492 | x86_subreg_8bit_hi)>, |
| 4493 | Requires<[In32BitMode]>; |
Dan Gohman | 7e0d64a | 2010-01-11 17:21:05 +0000 | [diff] [blame] | 4494 | def : Pat<(srl GR16:$src, (i8 8)), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4495 | (EXTRACT_SUBREG |
| 4496 | (MOVZX32rr8 |
Anton Korobeynikov | 3a639a0 | 2009-11-02 00:11:39 +0000 | [diff] [blame] | 4497 | (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4498 | x86_subreg_8bit_hi)), |
| 4499 | x86_subreg_16bit)>, |
| 4500 | Requires<[In32BitMode]>; |
Evan Cheng | cb219f0 | 2009-05-29 01:44:43 +0000 | [diff] [blame] | 4501 | def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 4502 | (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, |
| 4503 | GR16_ABCD)), |
Evan Cheng | cb219f0 | 2009-05-29 01:44:43 +0000 | [diff] [blame] | 4504 | x86_subreg_8bit_hi))>, |
| 4505 | Requires<[In32BitMode]>; |
Dan Gohman | af70e5c | 2009-08-26 14:59:13 +0000 | [diff] [blame] | 4506 | def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 4507 | (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, |
| 4508 | GR16_ABCD)), |
Dan Gohman | af70e5c | 2009-08-26 14:59:13 +0000 | [diff] [blame] | 4509 | x86_subreg_8bit_hi))>, |
| 4510 | Requires<[In32BitMode]>; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4511 | def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 4512 | (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, |
| 4513 | GR32_ABCD)), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4514 | x86_subreg_8bit_hi))>, |
Dan Gohman | 8a1510d | 2008-08-06 18:27:21 +0000 | [diff] [blame] | 4515 | Requires<[In32BitMode]>; |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 4516 | |
Evan Cheng | cfa260b | 2006-01-06 02:31:59 +0000 | [diff] [blame] | 4517 | // (shl x, 1) ==> (add x, x) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4518 | def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; |
| 4519 | def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; |
| 4520 | def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; |
Evan Cheng | 68b951a | 2006-01-19 01:56:29 +0000 | [diff] [blame] | 4521 | |
Evan Cheng | eb9f892 | 2008-08-30 02:03:58 +0000 | [diff] [blame] | 4522 | // (shl x (and y, 31)) ==> (shl x, y) |
| 4523 | def : Pat<(shl GR8:$src1, (and CL:$amt, 31)), |
| 4524 | (SHL8rCL GR8:$src1)>; |
| 4525 | def : Pat<(shl GR16:$src1, (and CL:$amt, 31)), |
| 4526 | (SHL16rCL GR16:$src1)>; |
| 4527 | def : Pat<(shl GR32:$src1, (and CL:$amt, 31)), |
| 4528 | (SHL32rCL GR32:$src1)>; |
| 4529 | def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4530 | (SHL8mCL addr:$dst)>; |
| 4531 | def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4532 | (SHL16mCL addr:$dst)>; |
| 4533 | def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4534 | (SHL32mCL addr:$dst)>; |
| 4535 | |
| 4536 | def : Pat<(srl GR8:$src1, (and CL:$amt, 31)), |
| 4537 | (SHR8rCL GR8:$src1)>; |
| 4538 | def : Pat<(srl GR16:$src1, (and CL:$amt, 31)), |
| 4539 | (SHR16rCL GR16:$src1)>; |
| 4540 | def : Pat<(srl GR32:$src1, (and CL:$amt, 31)), |
| 4541 | (SHR32rCL GR32:$src1)>; |
| 4542 | def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4543 | (SHR8mCL addr:$dst)>; |
| 4544 | def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4545 | (SHR16mCL addr:$dst)>; |
| 4546 | def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4547 | (SHR32mCL addr:$dst)>; |
| 4548 | |
| 4549 | def : Pat<(sra GR8:$src1, (and CL:$amt, 31)), |
| 4550 | (SAR8rCL GR8:$src1)>; |
| 4551 | def : Pat<(sra GR16:$src1, (and CL:$amt, 31)), |
| 4552 | (SAR16rCL GR16:$src1)>; |
| 4553 | def : Pat<(sra GR32:$src1, (and CL:$amt, 31)), |
| 4554 | (SAR32rCL GR32:$src1)>; |
| 4555 | def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4556 | (SAR8mCL addr:$dst)>; |
| 4557 | def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4558 | (SAR16mCL addr:$dst)>; |
| 4559 | def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4560 | (SAR32mCL addr:$dst)>; |
| 4561 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 4562 | // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4563 | def : Pat<(or (srl GR32:$src1, CL:$amt), |
| 4564 | (shl GR32:$src2, (sub 32, CL:$amt))), |
| 4565 | (SHRD32rrCL GR32:$src1, GR32:$src2)>; |
Evan Cheng | 68b951a | 2006-01-19 01:56:29 +0000 | [diff] [blame] | 4566 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 4567 | def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4568 | (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst), |
| 4569 | (SHRD32mrCL addr:$dst, GR32:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 4570 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 4571 | def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))), |
| 4572 | (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))), |
| 4573 | (SHRD32rrCL GR32:$src1, GR32:$src2)>; |
| 4574 | |
| 4575 | def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))), |
| 4576 | (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))), |
| 4577 | addr:$dst), |
| 4578 | (SHRD32mrCL addr:$dst, GR32:$src2)>; |
| 4579 | |
| 4580 | def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)), |
| 4581 | (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>; |
| 4582 | |
| 4583 | def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1), |
| 4584 | GR32:$src2, (i8 imm:$amt2)), addr:$dst), |
| 4585 | (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>; |
| 4586 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 4587 | // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4588 | def : Pat<(or (shl GR32:$src1, CL:$amt), |
| 4589 | (srl GR32:$src2, (sub 32, CL:$amt))), |
| 4590 | (SHLD32rrCL GR32:$src1, GR32:$src2)>; |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 4591 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 4592 | def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4593 | (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst), |
| 4594 | (SHLD32mrCL addr:$dst, GR32:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 4595 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 4596 | def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))), |
| 4597 | (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))), |
| 4598 | (SHLD32rrCL GR32:$src1, GR32:$src2)>; |
| 4599 | |
| 4600 | def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))), |
| 4601 | (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))), |
| 4602 | addr:$dst), |
| 4603 | (SHLD32mrCL addr:$dst, GR32:$src2)>; |
| 4604 | |
| 4605 | def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)), |
| 4606 | (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>; |
| 4607 | |
| 4608 | def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1), |
| 4609 | GR32:$src2, (i8 imm:$amt2)), addr:$dst), |
| 4610 | (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>; |
| 4611 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 4612 | // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4613 | def : Pat<(or (srl GR16:$src1, CL:$amt), |
| 4614 | (shl GR16:$src2, (sub 16, CL:$amt))), |
| 4615 | (SHRD16rrCL GR16:$src1, GR16:$src2)>; |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 4616 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 4617 | def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4618 | (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst), |
| 4619 | (SHRD16mrCL addr:$dst, GR16:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 4620 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 4621 | def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))), |
| 4622 | (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))), |
| 4623 | (SHRD16rrCL GR16:$src1, GR16:$src2)>; |
| 4624 | |
| 4625 | def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))), |
| 4626 | (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))), |
| 4627 | addr:$dst), |
| 4628 | (SHRD16mrCL addr:$dst, GR16:$src2)>; |
| 4629 | |
| 4630 | def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)), |
| 4631 | (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>; |
| 4632 | |
| 4633 | def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1), |
| 4634 | GR16:$src2, (i8 imm:$amt2)), addr:$dst), |
| 4635 | (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>; |
| 4636 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 4637 | // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4638 | def : Pat<(or (shl GR16:$src1, CL:$amt), |
| 4639 | (srl GR16:$src2, (sub 16, CL:$amt))), |
| 4640 | (SHLD16rrCL GR16:$src1, GR16:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 4641 | |
| 4642 | def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4643 | (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst), |
| 4644 | (SHLD16mrCL addr:$dst, GR16:$src2)>; |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 4645 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 4646 | def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))), |
| 4647 | (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))), |
| 4648 | (SHLD16rrCL GR16:$src1, GR16:$src2)>; |
| 4649 | |
| 4650 | def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))), |
| 4651 | (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))), |
| 4652 | addr:$dst), |
| 4653 | (SHLD16mrCL addr:$dst, GR16:$src2)>; |
| 4654 | |
| 4655 | def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)), |
| 4656 | (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>; |
| 4657 | |
| 4658 | def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1), |
| 4659 | GR16:$src2, (i8 imm:$amt2)), addr:$dst), |
| 4660 | (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>; |
| 4661 | |
Evan Cheng | 2e489c4 | 2009-12-16 00:53:11 +0000 | [diff] [blame] | 4662 | // (anyext (setcc_carry)) -> (setcc_carry) |
| 4663 | def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), |
Evan Cheng | ad9c0a3 | 2009-12-15 00:53:42 +0000 | [diff] [blame] | 4664 | (SETB_C16r)>; |
Evan Cheng | 2e489c4 | 2009-12-16 00:53:11 +0000 | [diff] [blame] | 4665 | def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), |
Evan Cheng | ad9c0a3 | 2009-12-15 00:53:42 +0000 | [diff] [blame] | 4666 | (SETB_C32r)>; |
| 4667 | |
Evan Cheng | 199c424 | 2010-01-11 22:03:29 +0000 | [diff] [blame] | 4668 | // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. |
Evan Cheng | 3bda201 | 2010-01-12 18:31:19 +0000 | [diff] [blame] | 4669 | let AddedComplexity = 5 in { // Try this before the selecting to OR |
Evan Cheng | 4b0345b | 2010-01-11 17:03:47 +0000 | [diff] [blame] | 4670 | def : Pat<(parallel (or_is_add GR16:$src1, imm:$src2), |
| 4671 | (implicit EFLAGS)), |
| 4672 | (ADD16ri GR16:$src1, imm:$src2)>; |
| 4673 | def : Pat<(parallel (or_is_add GR32:$src1, imm:$src2), |
| 4674 | (implicit EFLAGS)), |
| 4675 | (ADD32ri GR32:$src1, imm:$src2)>; |
| 4676 | def : Pat<(parallel (or_is_add GR16:$src1, i16immSExt8:$src2), |
| 4677 | (implicit EFLAGS)), |
| 4678 | (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; |
| 4679 | def : Pat<(parallel (or_is_add GR32:$src1, i32immSExt8:$src2), |
| 4680 | (implicit EFLAGS)), |
| 4681 | (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; |
Evan Cheng | 199c424 | 2010-01-11 22:03:29 +0000 | [diff] [blame] | 4682 | def : Pat<(parallel (or_is_add GR16:$src1, GR16:$src2), |
| 4683 | (implicit EFLAGS)), |
| 4684 | (ADD16rr GR16:$src1, GR16:$src2)>; |
| 4685 | def : Pat<(parallel (or_is_add GR32:$src1, GR32:$src2), |
| 4686 | (implicit EFLAGS)), |
| 4687 | (ADD32rr GR32:$src1, GR32:$src2)>; |
Evan Cheng | 3bda201 | 2010-01-12 18:31:19 +0000 | [diff] [blame] | 4688 | } // AddedComplexity |
Evan Cheng | 4b0345b | 2010-01-11 17:03:47 +0000 | [diff] [blame] | 4689 | |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 4690 | //===----------------------------------------------------------------------===// |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4691 | // EFLAGS-defining Patterns |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4692 | //===----------------------------------------------------------------------===// |
| 4693 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4694 | // Register-Register Addition with EFLAGS result |
| 4695 | def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4696 | (implicit EFLAGS)), |
| 4697 | (ADD8rr GR8:$src1, GR8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4698 | def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4699 | (implicit EFLAGS)), |
| 4700 | (ADD16rr GR16:$src1, GR16:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4701 | def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4702 | (implicit EFLAGS)), |
| 4703 | (ADD32rr GR32:$src1, GR32:$src2)>; |
| 4704 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4705 | // Register-Memory Addition with EFLAGS result |
| 4706 | def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4707 | (implicit EFLAGS)), |
| 4708 | (ADD8rm GR8:$src1, addr:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4709 | def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4710 | (implicit EFLAGS)), |
| 4711 | (ADD16rm GR16:$src1, addr:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4712 | def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4713 | (implicit EFLAGS)), |
| 4714 | (ADD32rm GR32:$src1, addr:$src2)>; |
| 4715 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4716 | // Register-Integer Addition with EFLAGS result |
| 4717 | def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4718 | (implicit EFLAGS)), |
| 4719 | (ADD8ri GR8:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4720 | def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4721 | (implicit EFLAGS)), |
| 4722 | (ADD16ri GR16:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4723 | def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4724 | (implicit EFLAGS)), |
| 4725 | (ADD32ri GR32:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4726 | def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4727 | (implicit EFLAGS)), |
| 4728 | (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4729 | def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4730 | (implicit EFLAGS)), |
| 4731 | (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; |
| 4732 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4733 | // Memory-Register Addition with EFLAGS result |
| 4734 | def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4735 | addr:$dst), |
| 4736 | (implicit EFLAGS)), |
| 4737 | (ADD8mr addr:$dst, GR8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4738 | def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4739 | addr:$dst), |
| 4740 | (implicit EFLAGS)), |
| 4741 | (ADD16mr addr:$dst, GR16:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4742 | def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4743 | addr:$dst), |
| 4744 | (implicit EFLAGS)), |
| 4745 | (ADD32mr addr:$dst, GR32:$src2)>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 4746 | |
| 4747 | // Memory-Integer Addition with EFLAGS result |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4748 | def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4749 | addr:$dst), |
| 4750 | (implicit EFLAGS)), |
| 4751 | (ADD8mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4752 | def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4753 | addr:$dst), |
| 4754 | (implicit EFLAGS)), |
| 4755 | (ADD16mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4756 | def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4757 | addr:$dst), |
| 4758 | (implicit EFLAGS)), |
| 4759 | (ADD32mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4760 | def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4761 | addr:$dst), |
| 4762 | (implicit EFLAGS)), |
| 4763 | (ADD16mi8 addr:$dst, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4764 | def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4765 | addr:$dst), |
| 4766 | (implicit EFLAGS)), |
| 4767 | (ADD32mi8 addr:$dst, i32immSExt8:$src2)>; |
| 4768 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4769 | // Register-Register Subtraction with EFLAGS result |
| 4770 | def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4771 | (implicit EFLAGS)), |
| 4772 | (SUB8rr GR8:$src1, GR8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4773 | def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4774 | (implicit EFLAGS)), |
| 4775 | (SUB16rr GR16:$src1, GR16:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4776 | def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4777 | (implicit EFLAGS)), |
| 4778 | (SUB32rr GR32:$src1, GR32:$src2)>; |
| 4779 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4780 | // Register-Memory Subtraction with EFLAGS result |
| 4781 | def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4782 | (implicit EFLAGS)), |
| 4783 | (SUB8rm GR8:$src1, addr:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4784 | def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4785 | (implicit EFLAGS)), |
| 4786 | (SUB16rm GR16:$src1, addr:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4787 | def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4788 | (implicit EFLAGS)), |
| 4789 | (SUB32rm GR32:$src1, addr:$src2)>; |
| 4790 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4791 | // Register-Integer Subtraction with EFLAGS result |
| 4792 | def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4793 | (implicit EFLAGS)), |
| 4794 | (SUB8ri GR8:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4795 | def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4796 | (implicit EFLAGS)), |
| 4797 | (SUB16ri GR16:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4798 | def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4799 | (implicit EFLAGS)), |
| 4800 | (SUB32ri GR32:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4801 | def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4802 | (implicit EFLAGS)), |
| 4803 | (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4804 | def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4805 | (implicit EFLAGS)), |
| 4806 | (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; |
| 4807 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4808 | // Memory-Register Subtraction with EFLAGS result |
| 4809 | def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4810 | addr:$dst), |
| 4811 | (implicit EFLAGS)), |
| 4812 | (SUB8mr addr:$dst, GR8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4813 | def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4814 | addr:$dst), |
| 4815 | (implicit EFLAGS)), |
| 4816 | (SUB16mr addr:$dst, GR16:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4817 | def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4818 | addr:$dst), |
| 4819 | (implicit EFLAGS)), |
| 4820 | (SUB32mr addr:$dst, GR32:$src2)>; |
| 4821 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4822 | // Memory-Integer Subtraction with EFLAGS result |
| 4823 | def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4824 | addr:$dst), |
| 4825 | (implicit EFLAGS)), |
| 4826 | (SUB8mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4827 | def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4828 | addr:$dst), |
| 4829 | (implicit EFLAGS)), |
| 4830 | (SUB16mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4831 | def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4832 | addr:$dst), |
| 4833 | (implicit EFLAGS)), |
| 4834 | (SUB32mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4835 | def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4836 | addr:$dst), |
| 4837 | (implicit EFLAGS)), |
| 4838 | (SUB16mi8 addr:$dst, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4839 | def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4840 | addr:$dst), |
| 4841 | (implicit EFLAGS)), |
| 4842 | (SUB32mi8 addr:$dst, i32immSExt8:$src2)>; |
| 4843 | |
| 4844 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4845 | // Register-Register Signed Integer Multiply with EFLAGS result |
| 4846 | def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4847 | (implicit EFLAGS)), |
| 4848 | (IMUL16rr GR16:$src1, GR16:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4849 | def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4850 | (implicit EFLAGS)), |
| 4851 | (IMUL32rr GR32:$src1, GR32:$src2)>; |
| 4852 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4853 | // Register-Memory Signed Integer Multiply with EFLAGS result |
| 4854 | def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4855 | (implicit EFLAGS)), |
| 4856 | (IMUL16rm GR16:$src1, addr:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4857 | def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4858 | (implicit EFLAGS)), |
| 4859 | (IMUL32rm GR32:$src1, addr:$src2)>; |
| 4860 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4861 | // Register-Integer Signed Integer Multiply with EFLAGS result |
| 4862 | def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4863 | (implicit EFLAGS)), |
| 4864 | (IMUL16rri GR16:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4865 | def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4866 | (implicit EFLAGS)), |
| 4867 | (IMUL32rri GR32:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4868 | def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4869 | (implicit EFLAGS)), |
| 4870 | (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4871 | def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4872 | (implicit EFLAGS)), |
| 4873 | (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; |
| 4874 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4875 | // Memory-Integer Signed Integer Multiply with EFLAGS result |
| 4876 | def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4877 | (implicit EFLAGS)), |
| 4878 | (IMUL16rmi addr:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4879 | def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4880 | (implicit EFLAGS)), |
| 4881 | (IMUL32rmi addr:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4882 | def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4883 | (implicit EFLAGS)), |
| 4884 | (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4885 | def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4886 | (implicit EFLAGS)), |
| 4887 | (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; |
| 4888 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4889 | // Optimize multiply by 2 with EFLAGS result. |
Evan Cheng | 6a86bd7 | 2009-01-27 03:30:42 +0000 | [diff] [blame] | 4890 | let AddedComplexity = 2 in { |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4891 | def : Pat<(parallel (X86smul_flag GR16:$src1, 2), |
Evan Cheng | 6a86bd7 | 2009-01-27 03:30:42 +0000 | [diff] [blame] | 4892 | (implicit EFLAGS)), |
| 4893 | (ADD16rr GR16:$src1, GR16:$src1)>; |
| 4894 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4895 | def : Pat<(parallel (X86smul_flag GR32:$src1, 2), |
Evan Cheng | 6a86bd7 | 2009-01-27 03:30:42 +0000 | [diff] [blame] | 4896 | (implicit EFLAGS)), |
| 4897 | (ADD32rr GR32:$src1, GR32:$src1)>; |
| 4898 | } |
| 4899 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4900 | // INC and DEC with EFLAGS result. Note that these do not set CF. |
| 4901 | def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)), |
| 4902 | (INC8r GR8:$src)>; |
| 4903 | def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst), |
| 4904 | (implicit EFLAGS)), |
| 4905 | (INC8m addr:$dst)>; |
| 4906 | def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)), |
| 4907 | (DEC8r GR8:$src)>; |
| 4908 | def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst), |
| 4909 | (implicit EFLAGS)), |
| 4910 | (DEC8m addr:$dst)>; |
| 4911 | |
| 4912 | def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 4913 | (INC16r GR16:$src)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4914 | def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst), |
| 4915 | (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 4916 | (INC16m addr:$dst)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4917 | def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 4918 | (DEC16r GR16:$src)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4919 | def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst), |
| 4920 | (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 4921 | (DEC16m addr:$dst)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4922 | |
| 4923 | def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 4924 | (INC32r GR32:$src)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4925 | def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst), |
| 4926 | (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 4927 | (INC32m addr:$dst)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4928 | def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 4929 | (DEC32r GR32:$src)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4930 | def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst), |
| 4931 | (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 4932 | (DEC32m addr:$dst)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4933 | |
Dan Gohman | e220c4b | 2009-09-18 19:59:53 +0000 | [diff] [blame] | 4934 | // Register-Register Or with EFLAGS result |
| 4935 | def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2), |
| 4936 | (implicit EFLAGS)), |
| 4937 | (OR8rr GR8:$src1, GR8:$src2)>; |
| 4938 | def : Pat<(parallel (X86or_flag GR16:$src1, GR16:$src2), |
| 4939 | (implicit EFLAGS)), |
| 4940 | (OR16rr GR16:$src1, GR16:$src2)>; |
| 4941 | def : Pat<(parallel (X86or_flag GR32:$src1, GR32:$src2), |
| 4942 | (implicit EFLAGS)), |
| 4943 | (OR32rr GR32:$src1, GR32:$src2)>; |
| 4944 | |
| 4945 | // Register-Memory Or with EFLAGS result |
| 4946 | def : Pat<(parallel (X86or_flag GR8:$src1, (loadi8 addr:$src2)), |
| 4947 | (implicit EFLAGS)), |
| 4948 | (OR8rm GR8:$src1, addr:$src2)>; |
| 4949 | def : Pat<(parallel (X86or_flag GR16:$src1, (loadi16 addr:$src2)), |
| 4950 | (implicit EFLAGS)), |
| 4951 | (OR16rm GR16:$src1, addr:$src2)>; |
| 4952 | def : Pat<(parallel (X86or_flag GR32:$src1, (loadi32 addr:$src2)), |
| 4953 | (implicit EFLAGS)), |
| 4954 | (OR32rm GR32:$src1, addr:$src2)>; |
| 4955 | |
| 4956 | // Register-Integer Or with EFLAGS result |
| 4957 | def : Pat<(parallel (X86or_flag GR8:$src1, imm:$src2), |
| 4958 | (implicit EFLAGS)), |
| 4959 | (OR8ri GR8:$src1, imm:$src2)>; |
| 4960 | def : Pat<(parallel (X86or_flag GR16:$src1, imm:$src2), |
| 4961 | (implicit EFLAGS)), |
| 4962 | (OR16ri GR16:$src1, imm:$src2)>; |
| 4963 | def : Pat<(parallel (X86or_flag GR32:$src1, imm:$src2), |
| 4964 | (implicit EFLAGS)), |
| 4965 | (OR32ri GR32:$src1, imm:$src2)>; |
| 4966 | def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2), |
| 4967 | (implicit EFLAGS)), |
| 4968 | (OR16ri8 GR16:$src1, i16immSExt8:$src2)>; |
| 4969 | def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2), |
| 4970 | (implicit EFLAGS)), |
| 4971 | (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; |
| 4972 | |
| 4973 | // Memory-Register Or with EFLAGS result |
| 4974 | def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2), |
| 4975 | addr:$dst), |
| 4976 | (implicit EFLAGS)), |
| 4977 | (OR8mr addr:$dst, GR8:$src2)>; |
| 4978 | def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), GR16:$src2), |
| 4979 | addr:$dst), |
| 4980 | (implicit EFLAGS)), |
| 4981 | (OR16mr addr:$dst, GR16:$src2)>; |
| 4982 | def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), GR32:$src2), |
| 4983 | addr:$dst), |
| 4984 | (implicit EFLAGS)), |
| 4985 | (OR32mr addr:$dst, GR32:$src2)>; |
| 4986 | |
| 4987 | // Memory-Integer Or with EFLAGS result |
| 4988 | def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), imm:$src2), |
| 4989 | addr:$dst), |
| 4990 | (implicit EFLAGS)), |
| 4991 | (OR8mi addr:$dst, imm:$src2)>; |
| 4992 | def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), imm:$src2), |
| 4993 | addr:$dst), |
| 4994 | (implicit EFLAGS)), |
| 4995 | (OR16mi addr:$dst, imm:$src2)>; |
| 4996 | def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), imm:$src2), |
| 4997 | addr:$dst), |
| 4998 | (implicit EFLAGS)), |
| 4999 | (OR32mi addr:$dst, imm:$src2)>; |
| 5000 | def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), i16immSExt8:$src2), |
| 5001 | addr:$dst), |
| 5002 | (implicit EFLAGS)), |
| 5003 | (OR16mi8 addr:$dst, i16immSExt8:$src2)>; |
| 5004 | def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2), |
| 5005 | addr:$dst), |
| 5006 | (implicit EFLAGS)), |
| 5007 | (OR32mi8 addr:$dst, i32immSExt8:$src2)>; |
| 5008 | |
| 5009 | // Register-Register XOr with EFLAGS result |
| 5010 | def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2), |
| 5011 | (implicit EFLAGS)), |
| 5012 | (XOR8rr GR8:$src1, GR8:$src2)>; |
| 5013 | def : Pat<(parallel (X86xor_flag GR16:$src1, GR16:$src2), |
| 5014 | (implicit EFLAGS)), |
| 5015 | (XOR16rr GR16:$src1, GR16:$src2)>; |
| 5016 | def : Pat<(parallel (X86xor_flag GR32:$src1, GR32:$src2), |
| 5017 | (implicit EFLAGS)), |
| 5018 | (XOR32rr GR32:$src1, GR32:$src2)>; |
| 5019 | |
| 5020 | // Register-Memory XOr with EFLAGS result |
| 5021 | def : Pat<(parallel (X86xor_flag GR8:$src1, (loadi8 addr:$src2)), |
| 5022 | (implicit EFLAGS)), |
| 5023 | (XOR8rm GR8:$src1, addr:$src2)>; |
| 5024 | def : Pat<(parallel (X86xor_flag GR16:$src1, (loadi16 addr:$src2)), |
| 5025 | (implicit EFLAGS)), |
| 5026 | (XOR16rm GR16:$src1, addr:$src2)>; |
| 5027 | def : Pat<(parallel (X86xor_flag GR32:$src1, (loadi32 addr:$src2)), |
| 5028 | (implicit EFLAGS)), |
| 5029 | (XOR32rm GR32:$src1, addr:$src2)>; |
| 5030 | |
| 5031 | // Register-Integer XOr with EFLAGS result |
| 5032 | def : Pat<(parallel (X86xor_flag GR8:$src1, imm:$src2), |
| 5033 | (implicit EFLAGS)), |
| 5034 | (XOR8ri GR8:$src1, imm:$src2)>; |
| 5035 | def : Pat<(parallel (X86xor_flag GR16:$src1, imm:$src2), |
| 5036 | (implicit EFLAGS)), |
| 5037 | (XOR16ri GR16:$src1, imm:$src2)>; |
| 5038 | def : Pat<(parallel (X86xor_flag GR32:$src1, imm:$src2), |
| 5039 | (implicit EFLAGS)), |
| 5040 | (XOR32ri GR32:$src1, imm:$src2)>; |
| 5041 | def : Pat<(parallel (X86xor_flag GR16:$src1, i16immSExt8:$src2), |
| 5042 | (implicit EFLAGS)), |
| 5043 | (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; |
| 5044 | def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2), |
| 5045 | (implicit EFLAGS)), |
| 5046 | (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; |
| 5047 | |
| 5048 | // Memory-Register XOr with EFLAGS result |
| 5049 | def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2), |
| 5050 | addr:$dst), |
| 5051 | (implicit EFLAGS)), |
| 5052 | (XOR8mr addr:$dst, GR8:$src2)>; |
| 5053 | def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), GR16:$src2), |
| 5054 | addr:$dst), |
| 5055 | (implicit EFLAGS)), |
| 5056 | (XOR16mr addr:$dst, GR16:$src2)>; |
| 5057 | def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), GR32:$src2), |
| 5058 | addr:$dst), |
| 5059 | (implicit EFLAGS)), |
| 5060 | (XOR32mr addr:$dst, GR32:$src2)>; |
| 5061 | |
| 5062 | // Memory-Integer XOr with EFLAGS result |
| 5063 | def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), imm:$src2), |
| 5064 | addr:$dst), |
| 5065 | (implicit EFLAGS)), |
| 5066 | (XOR8mi addr:$dst, imm:$src2)>; |
| 5067 | def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), imm:$src2), |
| 5068 | addr:$dst), |
| 5069 | (implicit EFLAGS)), |
| 5070 | (XOR16mi addr:$dst, imm:$src2)>; |
| 5071 | def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), imm:$src2), |
| 5072 | addr:$dst), |
| 5073 | (implicit EFLAGS)), |
| 5074 | (XOR32mi addr:$dst, imm:$src2)>; |
| 5075 | def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), i16immSExt8:$src2), |
| 5076 | addr:$dst), |
| 5077 | (implicit EFLAGS)), |
| 5078 | (XOR16mi8 addr:$dst, i16immSExt8:$src2)>; |
| 5079 | def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2), |
| 5080 | addr:$dst), |
| 5081 | (implicit EFLAGS)), |
| 5082 | (XOR32mi8 addr:$dst, i32immSExt8:$src2)>; |
| 5083 | |
| 5084 | // Register-Register And with EFLAGS result |
| 5085 | def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2), |
| 5086 | (implicit EFLAGS)), |
| 5087 | (AND8rr GR8:$src1, GR8:$src2)>; |
| 5088 | def : Pat<(parallel (X86and_flag GR16:$src1, GR16:$src2), |
| 5089 | (implicit EFLAGS)), |
| 5090 | (AND16rr GR16:$src1, GR16:$src2)>; |
| 5091 | def : Pat<(parallel (X86and_flag GR32:$src1, GR32:$src2), |
| 5092 | (implicit EFLAGS)), |
| 5093 | (AND32rr GR32:$src1, GR32:$src2)>; |
| 5094 | |
| 5095 | // Register-Memory And with EFLAGS result |
| 5096 | def : Pat<(parallel (X86and_flag GR8:$src1, (loadi8 addr:$src2)), |
| 5097 | (implicit EFLAGS)), |
| 5098 | (AND8rm GR8:$src1, addr:$src2)>; |
| 5099 | def : Pat<(parallel (X86and_flag GR16:$src1, (loadi16 addr:$src2)), |
| 5100 | (implicit EFLAGS)), |
| 5101 | (AND16rm GR16:$src1, addr:$src2)>; |
| 5102 | def : Pat<(parallel (X86and_flag GR32:$src1, (loadi32 addr:$src2)), |
| 5103 | (implicit EFLAGS)), |
| 5104 | (AND32rm GR32:$src1, addr:$src2)>; |
| 5105 | |
| 5106 | // Register-Integer And with EFLAGS result |
| 5107 | def : Pat<(parallel (X86and_flag GR8:$src1, imm:$src2), |
| 5108 | (implicit EFLAGS)), |
| 5109 | (AND8ri GR8:$src1, imm:$src2)>; |
| 5110 | def : Pat<(parallel (X86and_flag GR16:$src1, imm:$src2), |
| 5111 | (implicit EFLAGS)), |
| 5112 | (AND16ri GR16:$src1, imm:$src2)>; |
| 5113 | def : Pat<(parallel (X86and_flag GR32:$src1, imm:$src2), |
| 5114 | (implicit EFLAGS)), |
| 5115 | (AND32ri GR32:$src1, imm:$src2)>; |
| 5116 | def : Pat<(parallel (X86and_flag GR16:$src1, i16immSExt8:$src2), |
| 5117 | (implicit EFLAGS)), |
| 5118 | (AND16ri8 GR16:$src1, i16immSExt8:$src2)>; |
| 5119 | def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2), |
| 5120 | (implicit EFLAGS)), |
| 5121 | (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; |
| 5122 | |
| 5123 | // Memory-Register And with EFLAGS result |
| 5124 | def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2), |
| 5125 | addr:$dst), |
| 5126 | (implicit EFLAGS)), |
| 5127 | (AND8mr addr:$dst, GR8:$src2)>; |
| 5128 | def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), GR16:$src2), |
| 5129 | addr:$dst), |
| 5130 | (implicit EFLAGS)), |
| 5131 | (AND16mr addr:$dst, GR16:$src2)>; |
| 5132 | def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), GR32:$src2), |
| 5133 | addr:$dst), |
| 5134 | (implicit EFLAGS)), |
| 5135 | (AND32mr addr:$dst, GR32:$src2)>; |
| 5136 | |
| 5137 | // Memory-Integer And with EFLAGS result |
| 5138 | def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), imm:$src2), |
| 5139 | addr:$dst), |
| 5140 | (implicit EFLAGS)), |
| 5141 | (AND8mi addr:$dst, imm:$src2)>; |
| 5142 | def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), imm:$src2), |
| 5143 | addr:$dst), |
| 5144 | (implicit EFLAGS)), |
| 5145 | (AND16mi addr:$dst, imm:$src2)>; |
| 5146 | def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), imm:$src2), |
| 5147 | addr:$dst), |
| 5148 | (implicit EFLAGS)), |
| 5149 | (AND32mi addr:$dst, imm:$src2)>; |
| 5150 | def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), i16immSExt8:$src2), |
| 5151 | addr:$dst), |
| 5152 | (implicit EFLAGS)), |
| 5153 | (AND16mi8 addr:$dst, i16immSExt8:$src2)>; |
| 5154 | def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2), |
| 5155 | addr:$dst), |
| 5156 | (implicit EFLAGS)), |
| 5157 | (AND32mi8 addr:$dst, i32immSExt8:$src2)>; |
| 5158 | |
Dan Gohman | 2f67df7 | 2009-09-03 17:18:51 +0000 | [diff] [blame] | 5159 | // -disable-16bit support. |
| 5160 | def : Pat<(truncstorei16 (i32 imm:$src), addr:$dst), |
| 5161 | (MOV16mi addr:$dst, imm:$src)>; |
| 5162 | def : Pat<(truncstorei16 GR32:$src, addr:$dst), |
| 5163 | (MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>; |
| 5164 | def : Pat<(i32 (sextloadi16 addr:$dst)), |
| 5165 | (MOVSX32rm16 addr:$dst)>; |
| 5166 | def : Pat<(i32 (zextloadi16 addr:$dst)), |
| 5167 | (MOVZX32rm16 addr:$dst)>; |
| 5168 | def : Pat<(i32 (extloadi16 addr:$dst)), |
| 5169 | (MOVZX32rm16 addr:$dst)>; |
| 5170 | |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 5171 | //===----------------------------------------------------------------------===// |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 5172 | // Floating Point Stack Support |
| 5173 | //===----------------------------------------------------------------------===// |
| 5174 | |
| 5175 | include "X86InstrFPStack.td" |
| 5176 | |
| 5177 | //===----------------------------------------------------------------------===// |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 5178 | // X86-64 Support |
| 5179 | //===----------------------------------------------------------------------===// |
| 5180 | |
Chris Lattner | 36fe6d2 | 2008-01-10 05:50:42 +0000 | [diff] [blame] | 5181 | include "X86Instr64bit.td" |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 5182 | |
| 5183 | //===----------------------------------------------------------------------===// |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 5184 | // XMM Floating point support (requires SSE / SSE2) |
| 5185 | //===----------------------------------------------------------------------===// |
| 5186 | |
| 5187 | include "X86InstrSSE.td" |
Evan Cheng | 80f5404 | 2008-04-25 18:19:54 +0000 | [diff] [blame] | 5188 | |
| 5189 | //===----------------------------------------------------------------------===// |
| 5190 | // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2) |
| 5191 | //===----------------------------------------------------------------------===// |
| 5192 | |
| 5193 | include "X86InstrMMX.td" |