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Jim Grosbach31c24bf2009-11-07 22:00:39 +00001//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
Anton Korobeynikovd49ea772009-06-26 21:28:53 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
David Goodwinb50ea5c2009-07-02 22:18:33 +000010// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000011//
12//===----------------------------------------------------------------------===//
13
Evan Chengb9803a82009-11-06 23:52:48 +000014#include "Thumb1InstrInfo.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000015#include "ARM.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000016#include "ARMMachineFunctionInfo.h"
17#include "llvm/CodeGen/MachineFrameInfo.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
Evan Cheng2457f2c2010-05-22 01:47:14 +000019#include "llvm/CodeGen/MachineRegisterInfo.h"
Evan Chenge3ce8aa2009-11-01 22:04:35 +000020#include "llvm/CodeGen/MachineMemOperand.h"
21#include "llvm/CodeGen/PseudoSourceValue.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000022#include "llvm/ADT/SmallVector.h"
David Goodwinb50ea5c2009-07-02 22:18:33 +000023#include "Thumb1InstrInfo.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000024
25using namespace llvm;
26
Anton Korobeynikovf95215f2009-11-02 00:10:38 +000027Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
28 : ARMBaseInstrInfo(STI), RI(*this, STI) {
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000029}
30
Evan Cheng446c4282009-07-11 06:43:01 +000031unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
David Goodwin334c2642009-07-08 16:09:28 +000032 return 0;
33}
34
Jakob Stoklund Olesenac273662010-07-11 06:33:54 +000035void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
36 MachineBasicBlock::iterator I, DebugLoc DL,
37 unsigned DestReg, unsigned SrcReg,
38 bool KillSrc) const {
39 bool tDest = ARM::tGPRRegClass.contains(DestReg);
40 bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
41 unsigned Opc = ARM::tMOVgpr2gpr;
42 if (tDest && tSrc)
43 Opc = ARM::tMOVr;
44 else if (tSrc)
45 Opc = ARM::tMOVtgpr2gpr;
46 else if (tDest)
47 Opc = ARM::tMOVgpr2tgpr;
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000048
Jakob Stoklund Olesenac273662010-07-11 06:33:54 +000049 BuildMI(MBB, I, DL, get(Opc), DestReg)
50 .addReg(SrcReg, getKillRegState(KillSrc));
51 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
52 "Thumb1 can only copy GPR registers");
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000053}
54
David Goodwinb50ea5c2009-07-02 22:18:33 +000055void Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000056storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
57 unsigned SrcReg, bool isKill, int FI,
Evan Cheng746ad692010-05-06 19:06:44 +000058 const TargetRegisterClass *RC,
59 const TargetRegisterInfo *TRI) const {
Evan Cheng86e5f7b2009-08-13 05:40:51 +000060 assert((RC == ARM::tGPRRegisterClass ||
61 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
62 isARMLowRegister(SrcReg))) && "Unknown regclass!");
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000063
Jim Grosbach98793b92010-01-15 22:21:03 +000064 if (RC == ARM::tGPRRegisterClass ||
65 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
66 isARMLowRegister(SrcReg))) {
Evan Cheng746ad692010-05-06 19:06:44 +000067 DebugLoc DL;
68 if (I != MBB.end()) DL = I->getDebugLoc();
69
Evan Chenge3ce8aa2009-11-01 22:04:35 +000070 MachineFunction &MF = *MBB.getParent();
71 MachineFrameInfo &MFI = *MF.getFrameInfo();
72 MachineMemOperand *MMO =
Chris Lattner59db5492010-09-21 04:39:43 +000073 MF.getMachineMemOperand(
74 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
75 MachineMemOperand::MOStore,
Evan Chenge3ce8aa2009-11-01 22:04:35 +000076 MFI.getObjectSize(FI),
77 MFI.getObjectAlignment(FI));
Jim Grosbach74472b42011-06-29 20:26:39 +000078 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
Evan Cheng446c4282009-07-11 06:43:01 +000079 .addReg(SrcReg, getKillRegState(isKill))
Evan Chenge3ce8aa2009-11-01 22:04:35 +000080 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000081 }
82}
83
David Goodwinb50ea5c2009-07-02 22:18:33 +000084void Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000085loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
86 unsigned DestReg, int FI,
Evan Cheng746ad692010-05-06 19:06:44 +000087 const TargetRegisterClass *RC,
88 const TargetRegisterInfo *TRI) const {
Evan Cheng86e5f7b2009-08-13 05:40:51 +000089 assert((RC == ARM::tGPRRegisterClass ||
90 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
91 isARMLowRegister(DestReg))) && "Unknown regclass!");
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000092
Jim Grosbach98793b92010-01-15 22:21:03 +000093 if (RC == ARM::tGPRRegisterClass ||
94 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
95 isARMLowRegister(DestReg))) {
Evan Cheng746ad692010-05-06 19:06:44 +000096 DebugLoc DL;
97 if (I != MBB.end()) DL = I->getDebugLoc();
98
Evan Chenge3ce8aa2009-11-01 22:04:35 +000099 MachineFunction &MF = *MBB.getParent();
100 MachineFrameInfo &MFI = *MF.getFrameInfo();
101 MachineMemOperand *MMO =
Chris Lattner59db5492010-09-21 04:39:43 +0000102 MF.getMachineMemOperand(
103 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
104 MachineMemOperand::MOLoad,
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000105 MFI.getObjectSize(FI),
106 MFI.getObjectAlignment(FI));
Jim Grosbach74472b42011-06-29 20:26:39 +0000107 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000108 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000109 }
110}