blob: 76952e0f5faf6452c0c7cd46b466e53d7b7bda22 [file] [log] [blame]
Nate Begeman1d9d7422005-10-18 00:28:58 +00001//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
Chris Lattner7c5a3d32005-08-16 17:14:42 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Chris Lattner7c5a3d32005-08-16 17:14:42 +00007//
8//===----------------------------------------------------------------------===//
9//
Nate Begeman21e463b2005-10-16 05:39:50 +000010// This file implements the PPCISelLowering class.
Chris Lattner7c5a3d32005-08-16 17:14:42 +000011//
12//===----------------------------------------------------------------------===//
13
Chris Lattner16e71f22005-10-14 23:59:06 +000014#include "PPCISelLowering.h"
Jim Laskey2f616bf2006-11-16 22:43:37 +000015#include "PPCMachineFunctionInfo.h"
Chris Lattnerdf4ed632006-11-17 22:10:59 +000016#include "PPCPredicates.h"
Chris Lattner16e71f22005-10-14 23:59:06 +000017#include "PPCTargetMachine.h"
Chris Lattner59138102006-04-17 05:28:54 +000018#include "PPCPerfectShuffle.h"
Owen Anderson718cb662007-09-07 04:06:50 +000019#include "llvm/ADT/STLExtras.h"
Nate Begeman750ac1b2006-02-01 07:19:44 +000020#include "llvm/ADT/VectorExtras.h"
Evan Chengc4c62572006-03-13 23:20:37 +000021#include "llvm/Analysis/ScalarEvolutionExpressions.h"
Chris Lattnerb9a7bea2007-03-06 00:59:59 +000022#include "llvm/CodeGen/CallingConvLower.h"
Chris Lattner7c5a3d32005-08-16 17:14:42 +000023#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner8a2d3ca2005-08-26 21:23:58 +000025#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000026#include "llvm/CodeGen/MachineRegisterInfo.h"
Dan Gohman69de1932008-02-06 22:27:42 +000027#include "llvm/CodeGen/PseudoSourceValue.h"
Chris Lattner7c5a3d32005-08-16 17:14:42 +000028#include "llvm/CodeGen/SelectionDAG.h"
Chris Lattner0b1e4e52005-08-26 17:36:52 +000029#include "llvm/Constants.h"
Chris Lattner7c5a3d32005-08-16 17:14:42 +000030#include "llvm/Function.h"
Chris Lattner6d92cad2006-03-26 10:06:40 +000031#include "llvm/Intrinsics.h"
Nate Begeman750ac1b2006-02-01 07:19:44 +000032#include "llvm/Support/MathExtras.h"
Evan Chengd2ee2182006-02-18 00:08:58 +000033#include "llvm/Target/TargetOptions.h"
Chris Lattner4eab7142006-11-10 02:08:47 +000034#include "llvm/Support/CommandLine.h"
Chris Lattner7c5a3d32005-08-16 17:14:42 +000035using namespace llvm;
36
Chris Lattner3ee77402007-06-19 05:46:06 +000037static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
38cl::desc("enable preincrement load/store generation on PPC (experimental)"),
39 cl::Hidden);
Chris Lattner4eab7142006-11-10 02:08:47 +000040
Chris Lattner331d1bc2006-11-02 01:44:04 +000041PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
42 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
Chris Lattner7c5a3d32005-08-16 17:14:42 +000043
Nate Begeman405e3ec2005-10-21 00:02:42 +000044 setPow2DivIsCheap();
Chris Lattner7c5a3d32005-08-16 17:14:42 +000045
Chris Lattnerd145a612005-09-27 22:18:25 +000046 // Use _setjmp/_longjmp instead of setjmp/longjmp.
Anton Korobeynikovd27a2582006-12-10 23:12:42 +000047 setUseUnderscoreSetJmp(true);
48 setUseUnderscoreLongJmp(true);
Chris Lattnerd145a612005-09-27 22:18:25 +000049
Chris Lattner7c5a3d32005-08-16 17:14:42 +000050 // Set up the register classes.
Nate Begeman1d9d7422005-10-18 00:28:58 +000051 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
52 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
53 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
Chris Lattner7c5a3d32005-08-16 17:14:42 +000054
Evan Chengc5484282006-10-04 00:56:09 +000055 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
Duncan Sandsf9c98e62008-01-23 20:39:46 +000056 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
Evan Chengc5484282006-10-04 00:56:09 +000057 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
Duncan Sandsf9c98e62008-01-23 20:39:46 +000058
Chris Lattnerddf89562008-01-17 19:59:44 +000059 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
60
Chris Lattner94e509c2006-11-10 23:58:45 +000061 // PowerPC has pre-inc load and store's.
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
Evan Chengcd633192006-11-09 19:11:50 +000065 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
Chris Lattner94e509c2006-11-10 23:58:45 +000067 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
Evan Chengcd633192006-11-09 19:11:50 +000070 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
72
Dale Johannesen638ccd52007-10-06 01:24:11 +000073 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
74 setConvertAction(MVT::ppcf128, MVT::f64, Expand);
75 setConvertAction(MVT::ppcf128, MVT::f32, Expand);
Dale Johannesen6eaeff22007-10-10 01:01:31 +000076 // This is used in the ppcf128->int sequence. Note it has different semantics
77 // from FP_ROUND: that rounds to nearest, this rounds to zero.
78 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
Dale Johannesen638ccd52007-10-06 01:24:11 +000079
Chris Lattner7c5a3d32005-08-16 17:14:42 +000080 // PowerPC has no intrinsics for these particular operations
81 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
82 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
83 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
Andrew Lenharthd497d9f2008-02-16 14:46:26 +000084 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
85
Chris Lattner7c5a3d32005-08-16 17:14:42 +000086 // PowerPC has no SREM/UREM instructions
87 setOperationAction(ISD::SREM, MVT::i32, Expand);
88 setOperationAction(ISD::UREM, MVT::i32, Expand);
Chris Lattner563ecfb2006-06-27 18:18:41 +000089 setOperationAction(ISD::SREM, MVT::i64, Expand);
90 setOperationAction(ISD::UREM, MVT::i64, Expand);
Dan Gohman3ce990d2007-10-08 17:28:24 +000091
92 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
93 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
94 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
95 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
96 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
97 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
98 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
99 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
100 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000101
Dan Gohmanf96e4de2007-10-11 23:21:31 +0000102 // We don't support sin/cos/sqrt/fmod/pow
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000103 setOperationAction(ISD::FSIN , MVT::f64, Expand);
104 setOperationAction(ISD::FCOS , MVT::f64, Expand);
Chris Lattner615c2d02005-09-28 22:29:58 +0000105 setOperationAction(ISD::FREM , MVT::f64, Expand);
Dan Gohmanf96e4de2007-10-11 23:21:31 +0000106 setOperationAction(ISD::FPOW , MVT::f64, Expand);
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000107 setOperationAction(ISD::FSIN , MVT::f32, Expand);
108 setOperationAction(ISD::FCOS , MVT::f32, Expand);
Chris Lattner615c2d02005-09-28 22:29:58 +0000109 setOperationAction(ISD::FREM , MVT::f32, Expand);
Dan Gohmanf96e4de2007-10-11 23:21:31 +0000110 setOperationAction(ISD::FPOW , MVT::f32, Expand);
Dale Johannesen5c5eb802008-01-18 19:55:37 +0000111
Dan Gohman1a024862008-01-31 00:41:03 +0000112 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000113
114 // If we're enabling GP optimizations, use hardware square root
Chris Lattner1e9de3e2005-09-02 18:33:05 +0000115 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000116 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
117 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
118 }
119
Chris Lattner9601a862006-03-05 05:08:37 +0000120 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
121 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
122
Nate Begemand88fc032006-01-14 03:14:10 +0000123 // PowerPC does not have BSWAP, CTPOP or CTTZ
124 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000125 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
126 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
Chris Lattnerf89437d2006-06-27 20:14:52 +0000127 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
128 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
129 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000130
Nate Begeman35ef9132006-01-11 21:21:00 +0000131 // PowerPC does not have ROTR
132 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
133
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000134 // PowerPC does not have Select
135 setOperationAction(ISD::SELECT, MVT::i32, Expand);
Chris Lattnerf89437d2006-06-27 20:14:52 +0000136 setOperationAction(ISD::SELECT, MVT::i64, Expand);
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000137 setOperationAction(ISD::SELECT, MVT::f32, Expand);
138 setOperationAction(ISD::SELECT, MVT::f64, Expand);
Chris Lattnere4bc9ea2005-08-26 00:52:45 +0000139
Chris Lattner0b1e4e52005-08-26 17:36:52 +0000140 // PowerPC wants to turn select_cc of FP into fsel when possible.
141 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
Nate Begeman44775902006-01-31 08:17:29 +0000143
Nate Begeman750ac1b2006-02-01 07:19:44 +0000144 // PowerPC wants to optimize integer setcc a bit
Nate Begeman44775902006-01-31 08:17:29 +0000145 setOperationAction(ISD::SETCC, MVT::i32, Custom);
Chris Lattnereb9b62e2005-08-31 19:09:57 +0000146
Nate Begeman81e80972006-03-17 01:40:33 +0000147 // PowerPC does not have BRCOND which requires SetCC
148 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
Evan Chengc35497f2006-10-30 08:02:39 +0000149
150 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000151
Chris Lattnerf7605322005-08-31 21:09:52 +0000152 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
153 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
Nate Begemanc09eeec2005-09-06 22:03:27 +0000154
Jim Laskeyad23c9d2005-08-17 00:40:22 +0000155 // PowerPC does not have [U|S]INT_TO_FP
156 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
157 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
158
Chris Lattner53e88452005-12-23 05:13:35 +0000159 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
160 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
Chris Lattner5f9faea2006-06-27 18:40:08 +0000161 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
162 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
Chris Lattner53e88452005-12-23 05:13:35 +0000163
Chris Lattner25b8b8c2006-04-28 21:56:10 +0000164 // We cannot sextinreg(i1). Expand to shifts.
165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
Jim Laskey2ad9f172007-02-22 14:56:36 +0000166
Jim Laskeyabf6d172006-01-05 01:25:28 +0000167 // Support label based line numbers.
Chris Lattnerf73bae12005-11-29 06:16:21 +0000168 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
Jim Laskeye0bce712006-01-05 01:47:43 +0000169 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
Nicolas Geoffray616585b2007-12-21 12:19:44 +0000170
171 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
172 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
173 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
174 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
175
Chris Lattnere6ec9f22005-09-10 00:21:06 +0000176
Nate Begeman28a6b022005-12-10 02:36:00 +0000177 // We want to legalize GlobalAddress and ConstantPool nodes into the
178 // appropriate instructions to materialize the address.
Chris Lattner3eef4e32005-11-17 18:26:56 +0000179 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
Lauro Ramos Venancio75ce0102007-07-11 17:19:51 +0000180 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
Nate Begeman28a6b022005-12-10 02:36:00 +0000181 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
Nate Begeman37efe672006-04-22 18:53:45 +0000182 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
Chris Lattner059ca0f2006-06-16 21:01:35 +0000183 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
Lauro Ramos Venancio75ce0102007-07-11 17:19:51 +0000184 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
Chris Lattner059ca0f2006-06-16 21:01:35 +0000185 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
186 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
187
Nate Begemanee625572006-01-27 21:09:22 +0000188 // RET must be custom lowered, to meet ABI requirements
189 setOperationAction(ISD::RET , MVT::Other, Custom);
Duncan Sands36397f52007-07-27 12:58:54 +0000190
Nate Begemanacc398c2006-01-25 18:21:52 +0000191 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
192 setOperationAction(ISD::VASTART , MVT::Other, Custom);
193
Nicolas Geoffray01119992007-04-03 13:59:52 +0000194 // VAARG is custom lowered with ELF 32 ABI
195 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
196 setOperationAction(ISD::VAARG, MVT::Other, Custom);
197 else
198 setOperationAction(ISD::VAARG, MVT::Other, Expand);
199
Chris Lattnerb22c08b2006-01-15 09:02:48 +0000200 // Use the default implementation.
Nate Begemanacc398c2006-01-25 18:21:52 +0000201 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
202 setOperationAction(ISD::VAEND , MVT::Other, Expand);
Chris Lattnerb22c08b2006-01-15 09:02:48 +0000203 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
Jim Laskeyefc7e522006-12-04 22:04:42 +0000204 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
Jim Laskey2f616bf2006-11-16 22:43:37 +0000205 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
Chris Lattner56a752e2006-10-18 01:18:48 +0000207
Chris Lattner6d92cad2006-03-26 10:06:40 +0000208 // We want to custom lower some of our intrinsics.
Chris Lattner48b61a72006-03-28 00:40:33 +0000209 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
Chris Lattner6d92cad2006-03-26 10:06:40 +0000210
Chris Lattnera7a58542006-06-16 17:34:12 +0000211 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
Nate Begeman1d9d7422005-10-18 00:28:58 +0000212 // They also have instructions for converting between i64 and fp.
Nate Begemanc09eeec2005-09-06 22:03:27 +0000213 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
Jim Laskeyca367b42006-12-15 14:32:57 +0000214 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
Nate Begemanc09eeec2005-09-06 22:03:27 +0000215 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
Chris Lattner85c671b2006-12-07 01:24:16 +0000216 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
Jim Laskeyca367b42006-12-15 14:32:57 +0000217 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
218
Chris Lattner7fbcef72006-03-24 07:53:47 +0000219 // FIXME: disable this lowered code. This generates 64-bit register values,
220 // and we don't model the fact that the top part is clobbered by calls. We
221 // need to flag these together so that the value isn't live across a call.
222 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
223
Nate Begemanae749a92005-10-25 23:48:36 +0000224 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
225 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
226 } else {
Chris Lattner860e8862005-11-17 07:30:41 +0000227 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
Nate Begemanae749a92005-10-25 23:48:36 +0000228 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
Nate Begeman9d2b8172005-10-18 00:56:42 +0000229 }
230
Chris Lattnera7a58542006-06-16 17:34:12 +0000231 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
Chris Lattner26cb2862007-10-19 04:08:28 +0000232 // 64-bit PowerPC implementations can support i64 types directly
Nate Begeman9d2b8172005-10-18 00:56:42 +0000233 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
Nate Begeman1d9d7422005-10-18 00:28:58 +0000234 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
235 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
Dan Gohman9ed06db2008-03-07 20:36:53 +0000236 // 64-bit PowerPC wants to expand i128 shifts itself.
237 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
238 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
239 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
Nate Begeman1d9d7422005-10-18 00:28:58 +0000240 } else {
Chris Lattner26cb2862007-10-19 04:08:28 +0000241 // 32-bit PowerPC wants to expand i64 shifts itself.
Chris Lattner3fe6c1d2006-09-20 03:47:40 +0000242 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
243 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
244 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
Nate Begemanc09eeec2005-09-06 22:03:27 +0000245 }
Evan Chengd30bf012006-03-01 01:11:20 +0000246
Nate Begeman425a9692005-11-29 08:17:20 +0000247 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
Chris Lattnere3fea5a2006-03-31 19:52:36 +0000248 // First set operation action for all vector types to expand. Then we
249 // will selectively turn on ones that can be effectively codegen'd.
250 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
Dan Gohmanf5135be2007-05-18 23:21:46 +0000251 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
Chris Lattnerf3f69de2006-04-16 01:37:57 +0000252 // add/sub are legal for all supported vector VT's.
Chris Lattnere3fea5a2006-03-31 19:52:36 +0000253 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
254 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
Chris Lattnere3fea5a2006-03-31 19:52:36 +0000255
Chris Lattner7ff7e672006-04-04 17:25:31 +0000256 // We promote all shuffles to v16i8.
257 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
Chris Lattnerf3f69de2006-04-16 01:37:57 +0000258 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
259
260 // We promote all non-typed operations to v4i32.
261 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
262 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
263 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
264 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
265 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
266 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
267 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
268 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
269 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
270 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
271 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
272 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
Chris Lattnere3fea5a2006-03-31 19:52:36 +0000273
Chris Lattnerf3f69de2006-04-16 01:37:57 +0000274 // No other operations are legal.
Chris Lattnere3fea5a2006-03-31 19:52:36 +0000275 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
276 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
277 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
278 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
279 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
Chris Lattner2ef5e892006-05-24 00:15:25 +0000280 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
Evan Cheng66ffe6b2007-07-30 07:51:22 +0000281 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
Chris Lattnere3fea5a2006-03-31 19:52:36 +0000282 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
283 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
284 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
Dan Gohman3ce990d2007-10-08 17:28:24 +0000285 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
286 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand);
287 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
288 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
Chris Lattner01cae072006-04-03 23:55:43 +0000289 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
Dan Gohmana3f269f2007-10-12 14:08:57 +0000290 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
291 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
292 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
293 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
Chris Lattnere3fea5a2006-03-31 19:52:36 +0000294 }
295
Chris Lattner7ff7e672006-04-04 17:25:31 +0000296 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
297 // with merges, splats, etc.
298 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
299
Chris Lattnerf3f69de2006-04-16 01:37:57 +0000300 setOperationAction(ISD::AND , MVT::v4i32, Legal);
301 setOperationAction(ISD::OR , MVT::v4i32, Legal);
302 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
303 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
304 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
305 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
306
Nate Begeman425a9692005-11-29 08:17:20 +0000307 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
Nate Begeman7fd1edd2005-12-19 23:25:09 +0000308 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
Chris Lattner8d052bc2006-03-25 07:39:07 +0000309 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
310 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
Chris Lattnerec4a0c72006-01-29 06:32:58 +0000311
Chris Lattnere3fea5a2006-03-31 19:52:36 +0000312 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
Chris Lattnere7c768e2006-04-18 03:24:30 +0000313 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
Chris Lattner72dd9bd2006-04-18 03:43:48 +0000314 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
Chris Lattner19a81522006-04-18 03:57:35 +0000315 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
Chris Lattnerf1d0b2b2006-03-20 01:53:53 +0000316
Chris Lattnerb2177b92006-03-19 06:55:52 +0000317 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
318 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
Chris Lattner64b3a082006-03-24 07:48:08 +0000319
Chris Lattner541f91b2006-04-02 00:43:36 +0000320 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
321 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
Chris Lattner64b3a082006-03-24 07:48:08 +0000322 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
323 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
Nate Begeman425a9692005-11-29 08:17:20 +0000324 }
325
Chris Lattner7b0c58c2006-06-27 17:34:57 +0000326 setShiftAmountType(MVT::i32);
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000327 setSetCCResultContents(ZeroOrOneSetCCResult);
Chris Lattner10da9572006-10-18 01:20:43 +0000328
Jim Laskey2ad9f172007-02-22 14:56:36 +0000329 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
Chris Lattner10da9572006-10-18 01:20:43 +0000330 setStackPointerRegisterToSaveRestore(PPC::X1);
Jim Laskey2ad9f172007-02-22 14:56:36 +0000331 setExceptionPointerRegister(PPC::X3);
332 setExceptionSelectorRegister(PPC::X4);
333 } else {
Chris Lattner10da9572006-10-18 01:20:43 +0000334 setStackPointerRegisterToSaveRestore(PPC::R1);
Jim Laskey2ad9f172007-02-22 14:56:36 +0000335 setExceptionPointerRegister(PPC::R3);
336 setExceptionSelectorRegister(PPC::R4);
337 }
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000338
Chris Lattner8c13d0a2006-03-01 04:57:39 +0000339 // We have target-specific dag combine patterns for the following nodes:
340 setTargetDAGCombine(ISD::SINT_TO_FP);
Chris Lattner51269842006-03-01 05:50:56 +0000341 setTargetDAGCombine(ISD::STORE);
Chris Lattner90564f22006-04-18 17:59:36 +0000342 setTargetDAGCombine(ISD::BR_CC);
Chris Lattnerd9989382006-07-10 20:56:58 +0000343 setTargetDAGCombine(ISD::BSWAP);
Chris Lattner8c13d0a2006-03-01 04:57:39 +0000344
Dale Johannesenfabd32d2007-10-19 00:59:18 +0000345 // Darwin long double math library functions have $LDBL128 appended.
346 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
Duncan Sands007f9842008-01-10 10:28:30 +0000347 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
Dale Johannesenfabd32d2007-10-19 00:59:18 +0000348 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
349 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
Duncan Sands007f9842008-01-10 10:28:30 +0000350 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
351 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
Dale Johannesenfabd32d2007-10-19 00:59:18 +0000352 }
353
Chris Lattner7c5a3d32005-08-16 17:14:42 +0000354 computeRegisterProperties();
355}
356
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000357/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
358/// function arguments in the caller parameter area.
359unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
360 TargetMachine &TM = getTargetMachine();
361 // Darwin passes everything on 4 byte boundary.
362 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
363 return 4;
364 // FIXME Elf TBD
365 return 4;
366}
367
Chris Lattnerda6d20f2006-01-09 23:52:17 +0000368const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
369 switch (Opcode) {
370 default: return 0;
371 case PPCISD::FSEL: return "PPCISD::FSEL";
372 case PPCISD::FCFID: return "PPCISD::FCFID";
373 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
374 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
Chris Lattner51269842006-03-01 05:50:56 +0000375 case PPCISD::STFIWX: return "PPCISD::STFIWX";
Chris Lattnerda6d20f2006-01-09 23:52:17 +0000376 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
377 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
Chris Lattnerf1d0b2b2006-03-20 01:53:53 +0000378 case PPCISD::VPERM: return "PPCISD::VPERM";
Chris Lattnerda6d20f2006-01-09 23:52:17 +0000379 case PPCISD::Hi: return "PPCISD::Hi";
380 case PPCISD::Lo: return "PPCISD::Lo";
Jim Laskey2060a822006-12-11 18:45:56 +0000381 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
Chris Lattnerda6d20f2006-01-09 23:52:17 +0000382 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
383 case PPCISD::SRL: return "PPCISD::SRL";
384 case PPCISD::SRA: return "PPCISD::SRA";
385 case PPCISD::SHL: return "PPCISD::SHL";
Chris Lattnerecfe55e2006-03-22 05:30:33 +0000386 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
387 case PPCISD::STD_32: return "PPCISD::STD_32";
Nicolas Geoffray63f8fb12007-02-27 13:01:19 +0000388 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
389 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
Chris Lattnerc703a8f2006-05-17 19:00:46 +0000390 case PPCISD::MTCTR: return "PPCISD::MTCTR";
Chris Lattner9f0bc652007-02-25 05:34:32 +0000391 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
392 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
Chris Lattnerda6d20f2006-01-09 23:52:17 +0000393 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
Chris Lattner6d92cad2006-03-26 10:06:40 +0000394 case PPCISD::MFCR: return "PPCISD::MFCR";
Chris Lattnera17b1552006-03-31 05:13:27 +0000395 case PPCISD::VCMP: return "PPCISD::VCMP";
Chris Lattner6d92cad2006-03-26 10:06:40 +0000396 case PPCISD::VCMPo: return "PPCISD::VCMPo";
Chris Lattnerd9989382006-07-10 20:56:58 +0000397 case PPCISD::LBRX: return "PPCISD::LBRX";
398 case PPCISD::STBRX: return "PPCISD::STBRX";
Chris Lattnerf70f8d92006-04-18 18:05:58 +0000399 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
Chris Lattneref97c672008-01-18 18:51:16 +0000400 case PPCISD::MFFS: return "PPCISD::MFFS";
401 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
402 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
403 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
404 case PPCISD::MTFSF: return "PPCISD::MTFSF";
Chris Lattnerda6d20f2006-01-09 23:52:17 +0000405 }
406}
407
Scott Michel5b8f82e2008-03-10 15:42:14 +0000408
409MVT::ValueType
410PPCTargetLowering::getSetCCResultType(const SDOperand &) const {
411 return MVT::i32;
412}
413
414
Chris Lattner1a635d62006-04-14 06:01:58 +0000415//===----------------------------------------------------------------------===//
416// Node matching predicates, for use by the tblgen matching code.
417//===----------------------------------------------------------------------===//
418
Chris Lattner0b1e4e52005-08-26 17:36:52 +0000419/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
420static bool isFloatingPointZero(SDOperand Op) {
421 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
Dale Johanneseneaf08942007-08-31 04:03:46 +0000422 return CFP->getValueAPF().isZero();
Evan Cheng466685d2006-10-09 20:57:25 +0000423 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
Chris Lattner0b1e4e52005-08-26 17:36:52 +0000424 // Maybe this has already been legalized into the constant pool?
425 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
Evan Chengc356a572006-09-12 21:04:05 +0000426 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
Dale Johanneseneaf08942007-08-31 04:03:46 +0000427 return CFP->getValueAPF().isZero();
Chris Lattner0b1e4e52005-08-26 17:36:52 +0000428 }
429 return false;
430}
431
Chris Lattnerddb739e2006-04-06 17:23:16 +0000432/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
433/// true if Op is undef or if it matches the specified value.
434static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
435 return Op.getOpcode() == ISD::UNDEF ||
436 cast<ConstantSDNode>(Op)->getValue() == Val;
437}
438
439/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
440/// VPKUHUM instruction.
Chris Lattnerf24380e2006-04-06 22:28:36 +0000441bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
442 if (!isUnary) {
443 for (unsigned i = 0; i != 16; ++i)
444 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
445 return false;
446 } else {
447 for (unsigned i = 0; i != 8; ++i)
448 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
449 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
450 return false;
451 }
Chris Lattnerd0608e12006-04-06 18:26:28 +0000452 return true;
Chris Lattnerddb739e2006-04-06 17:23:16 +0000453}
454
455/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
456/// VPKUWUM instruction.
Chris Lattnerf24380e2006-04-06 22:28:36 +0000457bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
458 if (!isUnary) {
459 for (unsigned i = 0; i != 16; i += 2)
460 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
461 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
462 return false;
463 } else {
464 for (unsigned i = 0; i != 8; i += 2)
465 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
466 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
467 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
468 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
469 return false;
470 }
Chris Lattnerd0608e12006-04-06 18:26:28 +0000471 return true;
Chris Lattnerddb739e2006-04-06 17:23:16 +0000472}
473
Chris Lattnercaad1632006-04-06 22:02:42 +0000474/// isVMerge - Common function, used to match vmrg* shuffles.
475///
476static bool isVMerge(SDNode *N, unsigned UnitSize,
477 unsigned LHSStart, unsigned RHSStart) {
Chris Lattner116cc482006-04-06 21:11:54 +0000478 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
479 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
480 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
481 "Unsupported merge size!");
482
483 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
484 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
485 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
Chris Lattnercaad1632006-04-06 22:02:42 +0000486 LHSStart+j+i*UnitSize) ||
Chris Lattner116cc482006-04-06 21:11:54 +0000487 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
Chris Lattnercaad1632006-04-06 22:02:42 +0000488 RHSStart+j+i*UnitSize))
Chris Lattner116cc482006-04-06 21:11:54 +0000489 return false;
490 }
Chris Lattnercaad1632006-04-06 22:02:42 +0000491 return true;
492}
493
494/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
495/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
496bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
497 if (!isUnary)
498 return isVMerge(N, UnitSize, 8, 24);
499 return isVMerge(N, UnitSize, 8, 8);
Chris Lattner116cc482006-04-06 21:11:54 +0000500}
501
502/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
503/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
Chris Lattnercaad1632006-04-06 22:02:42 +0000504bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
505 if (!isUnary)
506 return isVMerge(N, UnitSize, 0, 16);
507 return isVMerge(N, UnitSize, 0, 0);
Chris Lattner116cc482006-04-06 21:11:54 +0000508}
509
510
Chris Lattnerd0608e12006-04-06 18:26:28 +0000511/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
512/// amount, otherwise return -1.
Chris Lattnerf24380e2006-04-06 22:28:36 +0000513int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
Chris Lattner116cc482006-04-06 21:11:54 +0000514 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
515 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
Chris Lattnerd0608e12006-04-06 18:26:28 +0000516 // Find the first non-undef value in the shuffle mask.
517 unsigned i;
518 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
519 /*search*/;
520
521 if (i == 16) return -1; // all undef.
522
523 // Otherwise, check to see if the rest of the elements are consequtively
524 // numbered from this value.
525 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
526 if (ShiftAmt < i) return -1;
527 ShiftAmt -= i;
Chris Lattnerddb739e2006-04-06 17:23:16 +0000528
Chris Lattnerf24380e2006-04-06 22:28:36 +0000529 if (!isUnary) {
530 // Check the rest of the elements to see if they are consequtive.
531 for (++i; i != 16; ++i)
532 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
533 return -1;
534 } else {
535 // Check the rest of the elements to see if they are consequtive.
536 for (++i; i != 16; ++i)
537 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
538 return -1;
539 }
Chris Lattnerd0608e12006-04-06 18:26:28 +0000540
541 return ShiftAmt;
542}
Chris Lattneref819f82006-03-20 06:33:01 +0000543
544/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
545/// specifies a splat of a single element that is suitable for input to
546/// VSPLTB/VSPLTH/VSPLTW.
Chris Lattner7ff7e672006-04-04 17:25:31 +0000547bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
548 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
549 N->getNumOperands() == 16 &&
550 (EltSize == 1 || EltSize == 2 || EltSize == 4));
Chris Lattnerdd4d2d02006-03-20 06:51:10 +0000551
Chris Lattner88a99ef2006-03-20 06:37:44 +0000552 // This is a splat operation if each element of the permute is the same, and
553 // if the value doesn't reference the second vector.
Chris Lattner7ff7e672006-04-04 17:25:31 +0000554 unsigned ElementBase = 0;
Chris Lattner88a99ef2006-03-20 06:37:44 +0000555 SDOperand Elt = N->getOperand(0);
Chris Lattner7ff7e672006-04-04 17:25:31 +0000556 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
557 ElementBase = EltV->getValue();
558 else
559 return false; // FIXME: Handle UNDEF elements too!
560
561 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
562 return false;
563
564 // Check that they are consequtive.
565 for (unsigned i = 1; i != EltSize; ++i) {
566 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
567 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
568 return false;
569 }
570
Chris Lattner88a99ef2006-03-20 06:37:44 +0000571 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
Chris Lattner7ff7e672006-04-04 17:25:31 +0000572 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
Chris Lattnerb097aa92006-04-14 23:19:08 +0000573 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
Chris Lattner88a99ef2006-03-20 06:37:44 +0000574 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
575 "Invalid VECTOR_SHUFFLE mask!");
Chris Lattner7ff7e672006-04-04 17:25:31 +0000576 for (unsigned j = 0; j != EltSize; ++j)
577 if (N->getOperand(i+j) != N->getOperand(j))
578 return false;
Chris Lattner88a99ef2006-03-20 06:37:44 +0000579 }
580
Chris Lattner7ff7e672006-04-04 17:25:31 +0000581 return true;
Chris Lattneref819f82006-03-20 06:33:01 +0000582}
583
Evan Cheng66ffe6b2007-07-30 07:51:22 +0000584/// isAllNegativeZeroVector - Returns true if all elements of build_vector
585/// are -0.0.
586bool PPC::isAllNegativeZeroVector(SDNode *N) {
587 assert(N->getOpcode() == ISD::BUILD_VECTOR);
588 if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
589 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
Dale Johanneseneaf08942007-08-31 04:03:46 +0000590 return CFP->getValueAPF().isNegZero();
Evan Cheng66ffe6b2007-07-30 07:51:22 +0000591 return false;
592}
593
Chris Lattneref819f82006-03-20 06:33:01 +0000594/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
595/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
Chris Lattner7ff7e672006-04-04 17:25:31 +0000596unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
597 assert(isSplatShuffleMask(N, EltSize));
598 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
Chris Lattneref819f82006-03-20 06:33:01 +0000599}
600
Chris Lattnere87192a2006-04-12 17:37:20 +0000601/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
Chris Lattner140a58f2006-04-08 06:46:53 +0000602/// by using a vspltis[bhw] instruction of the specified element size, return
603/// the constant being splatted. The ByteSize field indicates the number of
604/// bytes of each element [124] -> [bhw].
Chris Lattnere87192a2006-04-12 17:37:20 +0000605SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000606 SDOperand OpVal(0, 0);
Chris Lattner79d9a882006-04-08 07:14:26 +0000607
608 // If ByteSize of the splat is bigger than the element size of the
609 // build_vector, then we have a case where we are checking for a splat where
610 // multiple elements of the buildvector are folded together into a single
611 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
612 unsigned EltSize = 16/N->getNumOperands();
613 if (EltSize < ByteSize) {
614 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
615 SDOperand UniquedVals[4];
616 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
617
618 // See if all of the elements in the buildvector agree across.
619 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
620 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
621 // If the element isn't a constant, bail fully out.
622 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
623
624
625 if (UniquedVals[i&(Multiple-1)].Val == 0)
626 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
627 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
628 return SDOperand(); // no match.
629 }
630
631 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
632 // either constant or undef values that are identical for each chunk. See
633 // if these chunks can form into a larger vspltis*.
634
635 // Check to see if all of the leading entries are either 0 or -1. If
636 // neither, then this won't fit into the immediate field.
637 bool LeadingZero = true;
638 bool LeadingOnes = true;
639 for (unsigned i = 0; i != Multiple-1; ++i) {
640 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
641
642 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
643 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
644 }
645 // Finally, check the least significant entry.
646 if (LeadingZero) {
647 if (UniquedVals[Multiple-1].Val == 0)
648 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
649 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
650 if (Val < 16)
651 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
652 }
653 if (LeadingOnes) {
654 if (UniquedVals[Multiple-1].Val == 0)
655 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
656 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
657 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
658 return DAG.getTargetConstant(Val, MVT::i32);
659 }
660
661 return SDOperand();
662 }
663
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000664 // Check to see if this buildvec has a single non-undef value in its elements.
665 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
666 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
667 if (OpVal.Val == 0)
668 OpVal = N->getOperand(i);
669 else if (OpVal != N->getOperand(i))
Chris Lattner140a58f2006-04-08 06:46:53 +0000670 return SDOperand();
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000671 }
672
Chris Lattner140a58f2006-04-08 06:46:53 +0000673 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000674
Nate Begeman98e70cc2006-03-28 04:15:58 +0000675 unsigned ValSizeInBytes = 0;
676 uint64_t Value = 0;
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000677 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
678 Value = CN->getValue();
679 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
680 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
681 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
Dale Johanneseneaf08942007-08-31 04:03:46 +0000682 Value = FloatToBits(CN->getValueAPF().convertToFloat());
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000683 ValSizeInBytes = 4;
684 }
685
686 // If the splat value is larger than the element value, then we can never do
687 // this splat. The only case that we could fit the replicated bits into our
688 // immediate field for would be zero, and we prefer to use vxor for it.
Chris Lattner140a58f2006-04-08 06:46:53 +0000689 if (ValSizeInBytes < ByteSize) return SDOperand();
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000690
691 // If the element value is larger than the splat value, cut it in half and
692 // check to see if the two halves are equal. Continue doing this until we
693 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
694 while (ValSizeInBytes > ByteSize) {
695 ValSizeInBytes >>= 1;
696
697 // If the top half equals the bottom half, we're still ok.
Chris Lattner9b42bdd2006-04-05 17:39:25 +0000698 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
699 (Value & ((1 << (8*ValSizeInBytes))-1)))
Chris Lattner140a58f2006-04-08 06:46:53 +0000700 return SDOperand();
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000701 }
702
703 // Properly sign extend the value.
704 int ShAmt = (4-ByteSize)*8;
705 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
706
Evan Cheng5b6a01b2006-03-26 09:52:32 +0000707 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
Chris Lattner140a58f2006-04-08 06:46:53 +0000708 if (MaskVal == 0) return SDOperand();
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000709
Chris Lattner140a58f2006-04-08 06:46:53 +0000710 // Finally, if this value fits in a 5 bit sext field, return it
711 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
712 return DAG.getTargetConstant(MaskVal, MVT::i32);
713 return SDOperand();
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000714}
715
Chris Lattner1a635d62006-04-14 06:01:58 +0000716//===----------------------------------------------------------------------===//
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000717// Addressing Mode Selection
718//===----------------------------------------------------------------------===//
719
720/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
721/// or 64-bit immediate, and if the value can be accurately represented as a
722/// sign extension from a 16-bit value. If so, this returns true and the
723/// immediate.
724static bool isIntS16Immediate(SDNode *N, short &Imm) {
725 if (N->getOpcode() != ISD::Constant)
726 return false;
727
728 Imm = (short)cast<ConstantSDNode>(N)->getValue();
729 if (N->getValueType(0) == MVT::i32)
730 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
731 else
732 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
733}
734static bool isIntS16Immediate(SDOperand Op, short &Imm) {
735 return isIntS16Immediate(Op.Val, Imm);
736}
737
738
739/// SelectAddressRegReg - Given the specified addressed, check to see if it
740/// can be represented as an indexed [r+r] operation. Returns false if it
741/// can be more efficiently represented with [r+imm].
742bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
743 SDOperand &Index,
744 SelectionDAG &DAG) {
745 short imm = 0;
746 if (N.getOpcode() == ISD::ADD) {
747 if (isIntS16Immediate(N.getOperand(1), imm))
748 return false; // r+i
749 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
750 return false; // r+i
751
752 Base = N.getOperand(0);
753 Index = N.getOperand(1);
754 return true;
755 } else if (N.getOpcode() == ISD::OR) {
756 if (isIntS16Immediate(N.getOperand(1), imm))
757 return false; // r+i can fold it if we can.
758
759 // If this is an or of disjoint bitfields, we can codegen this as an add
760 // (for better address arithmetic) if the LHS and RHS of the OR are provably
761 // disjoint.
Dan Gohmanb3564aa2008-02-27 01:23:58 +0000762 APInt LHSKnownZero, LHSKnownOne;
763 APInt RHSKnownZero, RHSKnownOne;
764 DAG.ComputeMaskedBits(N.getOperand(0),
Dan Gohmanec59b952008-02-27 21:12:32 +0000765 APInt::getAllOnesValue(N.getOperand(0)
766 .getValueSizeInBits()),
Dan Gohmanb3564aa2008-02-27 01:23:58 +0000767 LHSKnownZero, LHSKnownOne);
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000768
Dan Gohmanb3564aa2008-02-27 01:23:58 +0000769 if (LHSKnownZero.getBoolValue()) {
770 DAG.ComputeMaskedBits(N.getOperand(1),
Dan Gohmanec59b952008-02-27 21:12:32 +0000771 APInt::getAllOnesValue(N.getOperand(1)
772 .getValueSizeInBits()),
Dan Gohmanb3564aa2008-02-27 01:23:58 +0000773 RHSKnownZero, RHSKnownOne);
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000774 // If all of the bits are known zero on the LHS or RHS, the add won't
775 // carry.
Dan Gohmanec59b952008-02-27 21:12:32 +0000776 if (~(LHSKnownZero | RHSKnownZero) == 0) {
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000777 Base = N.getOperand(0);
778 Index = N.getOperand(1);
779 return true;
780 }
781 }
782 }
783
784 return false;
785}
786
787/// Returns true if the address N can be represented by a base register plus
788/// a signed 16-bit displacement [r+imm], and if it is not better
789/// represented as reg+reg.
790bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
791 SDOperand &Base, SelectionDAG &DAG){
792 // If this can be more profitably realized as r+r, fail.
793 if (SelectAddressRegReg(N, Disp, Base, DAG))
794 return false;
795
796 if (N.getOpcode() == ISD::ADD) {
797 short imm = 0;
798 if (isIntS16Immediate(N.getOperand(1), imm)) {
799 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
800 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
801 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
802 } else {
803 Base = N.getOperand(0);
804 }
805 return true; // [r+i]
806 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
807 // Match LOAD (ADD (X, Lo(G))).
808 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
809 && "Cannot handle constant offsets yet!");
810 Disp = N.getOperand(1).getOperand(0); // The global address.
811 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
812 Disp.getOpcode() == ISD::TargetConstantPool ||
813 Disp.getOpcode() == ISD::TargetJumpTable);
814 Base = N.getOperand(0);
815 return true; // [&g+r]
816 }
817 } else if (N.getOpcode() == ISD::OR) {
818 short imm = 0;
819 if (isIntS16Immediate(N.getOperand(1), imm)) {
820 // If this is an or of disjoint bitfields, we can codegen this as an add
821 // (for better address arithmetic) if the LHS and RHS of the OR are
822 // provably disjoint.
Dan Gohmanb3564aa2008-02-27 01:23:58 +0000823 APInt LHSKnownZero, LHSKnownOne;
824 DAG.ComputeMaskedBits(N.getOperand(0),
825 APInt::getAllOnesValue(32),
826 LHSKnownZero, LHSKnownOne);
827 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000828 // If all of the bits are known zero on the LHS or RHS, the add won't
829 // carry.
830 Base = N.getOperand(0);
831 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
832 return true;
833 }
834 }
835 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
836 // Loading from a constant address.
837
838 // If this address fits entirely in a 16-bit sext immediate field, codegen
839 // this as "d, 0"
840 short Imm;
841 if (isIntS16Immediate(CN, Imm)) {
842 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
843 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
844 return true;
845 }
Chris Lattnerbc681d62007-02-17 06:44:03 +0000846
847 // Handle 32-bit sext immediates with LIS + addr mode.
848 if (CN->getValueType(0) == MVT::i32 ||
849 (int64_t)CN->getValue() == (int)CN->getValue()) {
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000850 int Addr = (int)CN->getValue();
851
852 // Otherwise, break this down into an LIS + disp.
Chris Lattnerbc681d62007-02-17 06:44:03 +0000853 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
854
855 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
856 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
857 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000858 return true;
859 }
860 }
861
862 Disp = DAG.getTargetConstant(0, getPointerTy());
863 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
864 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
865 else
866 Base = N;
867 return true; // [r+0]
868}
869
870/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
871/// represented as an indexed [r+r] operation.
872bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
873 SDOperand &Index,
874 SelectionDAG &DAG) {
875 // Check to see if we can easily represent this as an [r+r] address. This
876 // will fail if it thinks that the address is more profitably represented as
877 // reg+imm, e.g. where imm = 0.
878 if (SelectAddressRegReg(N, Base, Index, DAG))
879 return true;
880
881 // If the operand is an addition, always emit this as [r+r], since this is
882 // better (for code size, and execution, as the memop does the add for free)
883 // than emitting an explicit add.
884 if (N.getOpcode() == ISD::ADD) {
885 Base = N.getOperand(0);
886 Index = N.getOperand(1);
887 return true;
888 }
889
890 // Otherwise, do it the hard way, using R0 as the base register.
891 Base = DAG.getRegister(PPC::R0, N.getValueType());
892 Index = N;
893 return true;
894}
895
896/// SelectAddressRegImmShift - Returns true if the address N can be
897/// represented by a base register plus a signed 14-bit displacement
898/// [r+imm*4]. Suitable for use by STD and friends.
899bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
900 SDOperand &Base,
901 SelectionDAG &DAG) {
902 // If this can be more profitably realized as r+r, fail.
903 if (SelectAddressRegReg(N, Disp, Base, DAG))
904 return false;
905
906 if (N.getOpcode() == ISD::ADD) {
907 short imm = 0;
908 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
909 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
910 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
911 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
912 } else {
913 Base = N.getOperand(0);
914 }
915 return true; // [r+i]
916 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
917 // Match LOAD (ADD (X, Lo(G))).
918 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
919 && "Cannot handle constant offsets yet!");
920 Disp = N.getOperand(1).getOperand(0); // The global address.
921 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
922 Disp.getOpcode() == ISD::TargetConstantPool ||
923 Disp.getOpcode() == ISD::TargetJumpTable);
924 Base = N.getOperand(0);
925 return true; // [&g+r]
926 }
927 } else if (N.getOpcode() == ISD::OR) {
928 short imm = 0;
929 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
930 // If this is an or of disjoint bitfields, we can codegen this as an add
931 // (for better address arithmetic) if the LHS and RHS of the OR are
932 // provably disjoint.
Dan Gohmanb3564aa2008-02-27 01:23:58 +0000933 APInt LHSKnownZero, LHSKnownOne;
934 DAG.ComputeMaskedBits(N.getOperand(0),
935 APInt::getAllOnesValue(32),
936 LHSKnownZero, LHSKnownOne);
937 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000938 // If all of the bits are known zero on the LHS or RHS, the add won't
939 // carry.
940 Base = N.getOperand(0);
941 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
942 return true;
943 }
944 }
945 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
Chris Lattnerdee5a5a2007-02-17 06:57:26 +0000946 // Loading from a constant address. Verify low two bits are clear.
947 if ((CN->getValue() & 3) == 0) {
948 // If this address fits entirely in a 14-bit sext immediate field, codegen
949 // this as "d, 0"
950 short Imm;
951 if (isIntS16Immediate(CN, Imm)) {
952 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
953 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
954 return true;
955 }
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000956
Chris Lattnerdee5a5a2007-02-17 06:57:26 +0000957 // Fold the low-part of 32-bit absolute addresses into addr mode.
958 if (CN->getValueType(0) == MVT::i32 ||
959 (int64_t)CN->getValue() == (int)CN->getValue()) {
960 int Addr = (int)CN->getValue();
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000961
Chris Lattnerdee5a5a2007-02-17 06:57:26 +0000962 // Otherwise, break this down into an LIS + disp.
963 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
964
965 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
966 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
967 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
968 return true;
969 }
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000970 }
971 }
972
973 Disp = DAG.getTargetConstant(0, getPointerTy());
974 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
975 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
976 else
977 Base = N;
978 return true; // [r+0]
979}
980
981
982/// getPreIndexedAddressParts - returns true by value, base pointer and
983/// offset pointer and addressing mode by reference if the node's address
984/// can be legally represented as pre-indexed load / store address.
985bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
986 SDOperand &Offset,
Evan Cheng144d8f02006-11-09 17:55:04 +0000987 ISD::MemIndexedMode &AM,
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000988 SelectionDAG &DAG) {
Chris Lattner4eab7142006-11-10 02:08:47 +0000989 // Disabled by default for now.
990 if (!EnablePPCPreinc) return false;
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000991
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000992 SDOperand Ptr;
Chris Lattner2fe4bf42006-11-14 01:38:31 +0000993 MVT::ValueType VT;
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000994 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
995 Ptr = LD->getBasePtr();
Dan Gohmanb625f2f2008-01-30 00:15:11 +0000996 VT = LD->getMemoryVT();
Chris Lattner0851b4f2006-11-15 19:55:13 +0000997
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +0000998 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
Chris Lattner4eab7142006-11-10 02:08:47 +0000999 ST = ST;
Chris Lattner2fe4bf42006-11-14 01:38:31 +00001000 Ptr = ST->getBasePtr();
Dan Gohmanb625f2f2008-01-30 00:15:11 +00001001 VT = ST->getMemoryVT();
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +00001002 } else
1003 return false;
1004
Chris Lattner2fe4bf42006-11-14 01:38:31 +00001005 // PowerPC doesn't have preinc load/store instructions for vectors.
1006 if (MVT::isVector(VT))
1007 return false;
1008
Chris Lattner0851b4f2006-11-15 19:55:13 +00001009 // TODO: Check reg+reg first.
1010
1011 // LDU/STU use reg+imm*4, others use reg+imm.
1012 if (VT != MVT::i64) {
1013 // reg + imm
1014 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1015 return false;
1016 } else {
1017 // reg + imm * 4.
1018 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1019 return false;
1020 }
Chris Lattnerf6edf4d2006-11-11 00:08:42 +00001021
Chris Lattnerf6edf4d2006-11-11 00:08:42 +00001022 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Chris Lattner0851b4f2006-11-15 19:55:13 +00001023 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1024 // sext i32 to i64 when addr mode is r+i.
Dan Gohmanb625f2f2008-01-30 00:15:11 +00001025 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
Chris Lattnerf6edf4d2006-11-11 00:08:42 +00001026 LD->getExtensionType() == ISD::SEXTLOAD &&
1027 isa<ConstantSDNode>(Offset))
1028 return false;
Chris Lattner0851b4f2006-11-15 19:55:13 +00001029 }
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +00001030
Chris Lattner4eab7142006-11-10 02:08:47 +00001031 AM = ISD::PRE_INC;
1032 return true;
Chris Lattnerfc5b1ab2006-11-08 02:15:41 +00001033}
1034
1035//===----------------------------------------------------------------------===//
Chris Lattner1a635d62006-04-14 06:01:58 +00001036// LowerOperation implementation
1037//===----------------------------------------------------------------------===//
1038
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001039SDOperand PPCTargetLowering::LowerConstantPool(SDOperand Op,
1040 SelectionDAG &DAG) {
Chris Lattner059ca0f2006-06-16 21:01:35 +00001041 MVT::ValueType PtrVT = Op.getValueType();
Chris Lattner1a635d62006-04-14 06:01:58 +00001042 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Evan Chengc356a572006-09-12 21:04:05 +00001043 Constant *C = CP->getConstVal();
Chris Lattner059ca0f2006-06-16 21:01:35 +00001044 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1045 SDOperand Zero = DAG.getConstant(0, PtrVT);
Chris Lattner1a635d62006-04-14 06:01:58 +00001046
1047 const TargetMachine &TM = DAG.getTarget();
1048
Chris Lattner059ca0f2006-06-16 21:01:35 +00001049 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
1050 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
1051
Chris Lattner1a635d62006-04-14 06:01:58 +00001052 // If this is a non-darwin platform, we don't support non-static relo models
1053 // yet.
1054 if (TM.getRelocationModel() == Reloc::Static ||
1055 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1056 // Generate non-pic code that has direct accesses to the constant pool.
1057 // The address of the global is just (hi(&g)+lo(&g)).
Chris Lattner059ca0f2006-06-16 21:01:35 +00001058 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
Chris Lattner1a635d62006-04-14 06:01:58 +00001059 }
1060
Chris Lattner35d86fe2006-07-26 21:12:04 +00001061 if (TM.getRelocationModel() == Reloc::PIC_) {
Chris Lattner1a635d62006-04-14 06:01:58 +00001062 // With PIC, the first instruction is actually "GR+hi(&G)".
Chris Lattner059ca0f2006-06-16 21:01:35 +00001063 Hi = DAG.getNode(ISD::ADD, PtrVT,
1064 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
Chris Lattner1a635d62006-04-14 06:01:58 +00001065 }
1066
Chris Lattner059ca0f2006-06-16 21:01:35 +00001067 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
Chris Lattner1a635d62006-04-14 06:01:58 +00001068 return Lo;
1069}
1070
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001071SDOperand PPCTargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner059ca0f2006-06-16 21:01:35 +00001072 MVT::ValueType PtrVT = Op.getValueType();
Nate Begeman37efe672006-04-22 18:53:45 +00001073 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
Chris Lattner059ca0f2006-06-16 21:01:35 +00001074 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1075 SDOperand Zero = DAG.getConstant(0, PtrVT);
Nate Begeman37efe672006-04-22 18:53:45 +00001076
1077 const TargetMachine &TM = DAG.getTarget();
Chris Lattner059ca0f2006-06-16 21:01:35 +00001078
1079 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
1080 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
1081
Nate Begeman37efe672006-04-22 18:53:45 +00001082 // If this is a non-darwin platform, we don't support non-static relo models
1083 // yet.
1084 if (TM.getRelocationModel() == Reloc::Static ||
1085 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1086 // Generate non-pic code that has direct accesses to the constant pool.
1087 // The address of the global is just (hi(&g)+lo(&g)).
Chris Lattner059ca0f2006-06-16 21:01:35 +00001088 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
Nate Begeman37efe672006-04-22 18:53:45 +00001089 }
1090
Chris Lattner35d86fe2006-07-26 21:12:04 +00001091 if (TM.getRelocationModel() == Reloc::PIC_) {
Nate Begeman37efe672006-04-22 18:53:45 +00001092 // With PIC, the first instruction is actually "GR+hi(&G)".
Chris Lattner059ca0f2006-06-16 21:01:35 +00001093 Hi = DAG.getNode(ISD::ADD, PtrVT,
Chris Lattner0d72a202006-07-28 16:45:47 +00001094 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
Nate Begeman37efe672006-04-22 18:53:45 +00001095 }
1096
Chris Lattner059ca0f2006-06-16 21:01:35 +00001097 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
Nate Begeman37efe672006-04-22 18:53:45 +00001098 return Lo;
1099}
1100
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001101SDOperand PPCTargetLowering::LowerGlobalTLSAddress(SDOperand Op,
1102 SelectionDAG &DAG) {
Lauro Ramos Venancio75ce0102007-07-11 17:19:51 +00001103 assert(0 && "TLS not implemented for PPC.");
1104}
1105
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001106SDOperand PPCTargetLowering::LowerGlobalAddress(SDOperand Op,
1107 SelectionDAG &DAG) {
Chris Lattner059ca0f2006-06-16 21:01:35 +00001108 MVT::ValueType PtrVT = Op.getValueType();
Chris Lattner1a635d62006-04-14 06:01:58 +00001109 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1110 GlobalValue *GV = GSDN->getGlobal();
Chris Lattner059ca0f2006-06-16 21:01:35 +00001111 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
Evan Chengfcf5d4f2008-02-02 05:06:29 +00001112 // If it's a debug information descriptor, don't mess with it.
1113 if (DAG.isVerifiedDebugInfoDesc(Op))
1114 return GA;
Chris Lattner059ca0f2006-06-16 21:01:35 +00001115 SDOperand Zero = DAG.getConstant(0, PtrVT);
Chris Lattner1a635d62006-04-14 06:01:58 +00001116
1117 const TargetMachine &TM = DAG.getTarget();
1118
Chris Lattner059ca0f2006-06-16 21:01:35 +00001119 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1120 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1121
Chris Lattner1a635d62006-04-14 06:01:58 +00001122 // If this is a non-darwin platform, we don't support non-static relo models
1123 // yet.
1124 if (TM.getRelocationModel() == Reloc::Static ||
1125 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1126 // Generate non-pic code that has direct accesses to globals.
1127 // The address of the global is just (hi(&g)+lo(&g)).
Chris Lattner059ca0f2006-06-16 21:01:35 +00001128 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
Chris Lattner1a635d62006-04-14 06:01:58 +00001129 }
1130
Chris Lattner35d86fe2006-07-26 21:12:04 +00001131 if (TM.getRelocationModel() == Reloc::PIC_) {
Chris Lattner1a635d62006-04-14 06:01:58 +00001132 // With PIC, the first instruction is actually "GR+hi(&G)".
Chris Lattner059ca0f2006-06-16 21:01:35 +00001133 Hi = DAG.getNode(ISD::ADD, PtrVT,
1134 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
Chris Lattner1a635d62006-04-14 06:01:58 +00001135 }
1136
Chris Lattner059ca0f2006-06-16 21:01:35 +00001137 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
Chris Lattner1a635d62006-04-14 06:01:58 +00001138
Chris Lattner57fc62c2006-12-11 23:22:45 +00001139 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
Chris Lattner1a635d62006-04-14 06:01:58 +00001140 return Lo;
1141
1142 // If the global is weak or external, we have to go through the lazy
1143 // resolution stub.
Evan Cheng466685d2006-10-09 20:57:25 +00001144 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
Chris Lattner1a635d62006-04-14 06:01:58 +00001145}
1146
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001147SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner1a635d62006-04-14 06:01:58 +00001148 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1149
1150 // If we're comparing for equality to zero, expose the fact that this is
1151 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1152 // fold the new nodes.
1153 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1154 if (C->isNullValue() && CC == ISD::SETEQ) {
1155 MVT::ValueType VT = Op.getOperand(0).getValueType();
1156 SDOperand Zext = Op.getOperand(0);
1157 if (VT < MVT::i32) {
1158 VT = MVT::i32;
1159 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1160 }
1161 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1162 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1163 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1164 DAG.getConstant(Log2b, MVT::i32));
1165 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1166 }
1167 // Leave comparisons against 0 and -1 alone for now, since they're usually
1168 // optimized. FIXME: revisit this when we can custom lower all setcc
1169 // optimizations.
1170 if (C->isAllOnesValue() || C->isNullValue())
1171 return SDOperand();
1172 }
1173
1174 // If we have an integer seteq/setne, turn it into a compare against zero
Chris Lattnerac011bc2006-11-14 05:28:08 +00001175 // by xor'ing the rhs with the lhs, which is faster than setting a
1176 // condition register, reading it back out, and masking the correct bit. The
1177 // normal approach here uses sub to do this instead of xor. Using xor exposes
1178 // the result to other bit-twiddling opportunities.
Chris Lattner1a635d62006-04-14 06:01:58 +00001179 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1180 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1181 MVT::ValueType VT = Op.getValueType();
Chris Lattnerac011bc2006-11-14 05:28:08 +00001182 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
Chris Lattner1a635d62006-04-14 06:01:58 +00001183 Op.getOperand(1));
1184 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1185 }
1186 return SDOperand();
1187}
1188
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001189SDOperand PPCTargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG,
Nicolas Geoffray01119992007-04-03 13:59:52 +00001190 int VarArgsFrameIndex,
1191 int VarArgsStackOffset,
1192 unsigned VarArgsNumGPR,
1193 unsigned VarArgsNumFPR,
1194 const PPCSubtarget &Subtarget) {
1195
1196 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1197}
1198
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001199SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG,
Nicolas Geoffray01119992007-04-03 13:59:52 +00001200 int VarArgsFrameIndex,
1201 int VarArgsStackOffset,
1202 unsigned VarArgsNumGPR,
1203 unsigned VarArgsNumFPR,
1204 const PPCSubtarget &Subtarget) {
1205
1206 if (Subtarget.isMachoABI()) {
1207 // vastart just stores the address of the VarArgsFrameIndex slot into the
1208 // memory location argument.
1209 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1210 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
Dan Gohman69de1932008-02-06 22:27:42 +00001211 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1212 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
Nicolas Geoffray01119992007-04-03 13:59:52 +00001213 }
1214
1215 // For ELF 32 ABI we follow the layout of the va_list struct.
1216 // We suppose the given va_list is already allocated.
1217 //
1218 // typedef struct {
1219 // char gpr; /* index into the array of 8 GPRs
1220 // * stored in the register save area
1221 // * gpr=0 corresponds to r3,
1222 // * gpr=1 to r4, etc.
1223 // */
1224 // char fpr; /* index into the array of 8 FPRs
1225 // * stored in the register save area
1226 // * fpr=0 corresponds to f1,
1227 // * fpr=1 to f2, etc.
1228 // */
1229 // char *overflow_arg_area;
1230 // /* location on stack that holds
1231 // * the next overflow argument
1232 // */
1233 // char *reg_save_area;
1234 // /* where r3:r10 and f1:f8 (if saved)
1235 // * are stored
1236 // */
1237 // } va_list[1];
1238
1239
1240 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1241 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1242
1243
Chris Lattner0d72a202006-07-28 16:45:47 +00001244 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Nicolas Geoffray01119992007-04-03 13:59:52 +00001245
Dan Gohman69de1932008-02-06 22:27:42 +00001246 SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
Chris Lattner0d72a202006-07-28 16:45:47 +00001247 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
Nicolas Geoffray01119992007-04-03 13:59:52 +00001248
Dan Gohman69de1932008-02-06 22:27:42 +00001249 uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8;
1250 SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1251
1252 uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1;
1253 SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1254
1255 uint64_t FPROffset = 1;
1256 SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
Nicolas Geoffray01119992007-04-03 13:59:52 +00001257
Dan Gohman69de1932008-02-06 22:27:42 +00001258 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Nicolas Geoffray01119992007-04-03 13:59:52 +00001259
1260 // Store first byte : number of int regs
1261 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
Dan Gohman69de1932008-02-06 22:27:42 +00001262 Op.getOperand(1), SV, 0);
1263 uint64_t nextOffset = FPROffset;
Nicolas Geoffray01119992007-04-03 13:59:52 +00001264 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
1265 ConstFPROffset);
1266
1267 // Store second byte : number of float regs
Dan Gohman69de1932008-02-06 22:27:42 +00001268 SDOperand secondStore =
1269 DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset);
1270 nextOffset += StackOffset;
Nicolas Geoffray01119992007-04-03 13:59:52 +00001271 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
1272
1273 // Store second word : arguments given on stack
Dan Gohman69de1932008-02-06 22:27:42 +00001274 SDOperand thirdStore =
1275 DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset);
1276 nextOffset += FrameOffset;
Nicolas Geoffray01119992007-04-03 13:59:52 +00001277 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
1278
1279 // Store third word : arguments given in registers
Dan Gohman69de1932008-02-06 22:27:42 +00001280 return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset);
Nicolas Geoffray01119992007-04-03 13:59:52 +00001281
Chris Lattner1a635d62006-04-14 06:01:58 +00001282}
1283
Chris Lattnerb9a7bea2007-03-06 00:59:59 +00001284#include "PPCGenCallingConv.inc"
1285
Chris Lattner9f0bc652007-02-25 05:34:32 +00001286/// GetFPR - Get the set of FP registers that should be allocated for arguments,
1287/// depending on which subtarget is selected.
1288static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1289 if (Subtarget.isMachoABI()) {
1290 static const unsigned FPR[] = {
1291 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1292 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1293 };
1294 return FPR;
1295 }
1296
1297
1298 static const unsigned FPR[] = {
1299 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
Nicolas Geoffrayef3c0302007-04-03 10:27:07 +00001300 PPC::F8
Chris Lattner9f0bc652007-02-25 05:34:32 +00001301 };
1302 return FPR;
1303}
1304
Bill Wendling5f5bf3a2008-03-07 20:49:02 +00001305SDOperand
1306PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
1307 SelectionDAG &DAG,
1308 int &VarArgsFrameIndex,
1309 int &VarArgsStackOffset,
1310 unsigned &VarArgsNumGPR,
1311 unsigned &VarArgsNumFPR,
1312 const PPCSubtarget &Subtarget) {
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001313 // TODO: add description of PPC stack frame format, or at least some docs.
1314 //
1315 MachineFunction &MF = DAG.getMachineFunction();
1316 MachineFrameInfo *MFI = MF.getFrameInfo();
Chris Lattner84bc5422007-12-31 04:13:23 +00001317 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Chris Lattner79e490a2006-08-11 17:18:05 +00001318 SmallVector<SDOperand, 8> ArgValues;
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001319 SDOperand Root = Op.getOperand(0);
Dale Johannesen75092de2008-03-12 00:22:17 +00001320 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001321
Jim Laskey2f616bf2006-11-16 22:43:37 +00001322 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1323 bool isPPC64 = PtrVT == MVT::i64;
Chris Lattner9f0bc652007-02-25 05:34:32 +00001324 bool isMachoABI = Subtarget.isMachoABI();
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00001325 bool isELF32_ABI = Subtarget.isELF32_ABI();
Jim Laskeye9bd7b22006-11-28 14:53:52 +00001326 unsigned PtrByteSize = isPPC64 ? 8 : 4;
Jim Laskey2f616bf2006-11-16 22:43:37 +00001327
Chris Lattner9f0bc652007-02-25 05:34:32 +00001328 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
Chris Lattnerc91a4752006-06-26 22:48:35 +00001329
1330 static const unsigned GPR_32[] = { // 32-bit registers.
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001331 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1332 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1333 };
Chris Lattnerc91a4752006-06-26 22:48:35 +00001334 static const unsigned GPR_64[] = { // 64-bit registers.
1335 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1336 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1337 };
Chris Lattner9f0bc652007-02-25 05:34:32 +00001338
1339 static const unsigned *FPR = GetFPR(Subtarget);
1340
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001341 static const unsigned VR[] = {
1342 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1343 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1344 };
Chris Lattnerc91a4752006-06-26 22:48:35 +00001345
Owen Anderson718cb662007-09-07 04:06:50 +00001346 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
Nicolas Geoffrayef3c0302007-04-03 10:27:07 +00001347 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
Owen Anderson718cb662007-09-07 04:06:50 +00001348 const unsigned Num_VR_Regs = array_lengthof( VR);
Jim Laskey2f616bf2006-11-16 22:43:37 +00001349
1350 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1351
Chris Lattnerc91a4752006-06-26 22:48:35 +00001352 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001353
1354 // Add DAG nodes to load the arguments or copy them out of registers. On
Jim Laskey2f616bf2006-11-16 22:43:37 +00001355 // entry to a function on PPC, the arguments start after the linkage area,
1356 // although the first ones are often in registers.
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001357 //
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00001358 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001359 // represented with two words (long long or double) must be copied to an
1360 // even GPR_idx value or to an even ArgOffset value.
1361
Dale Johannesen8419dd62008-03-07 20:27:40 +00001362 SmallVector<SDOperand, 8> MemOps;
1363
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001364 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1365 SDOperand ArgVal;
1366 bool needsLoad = false;
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001367 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1368 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
Jim Laskey619965d2006-11-29 13:37:09 +00001369 unsigned ArgSize = ObjSize;
Dale Johannesenb8cafe32008-03-10 02:17:22 +00001370 ISD::ParamFlags::ParamFlagsTy Flags =
1371 cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue();
1372 unsigned AlignFlag = ISD::ParamFlags::One
1373 << ISD::ParamFlags::OrigAlignmentOffs;
Dale Johannesen8419dd62008-03-07 20:27:40 +00001374 unsigned isByVal = Flags & ISD::ParamFlags::ByVal;
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001375 // See if next argument requires stack alignment in ELF
1376 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) &&
1377 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) &&
1378 (!(Flags & AlignFlag)));
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001379
Chris Lattnerbe4849a2006-05-16 18:51:52 +00001380 unsigned CurArgOffset = ArgOffset;
Dale Johannesen8419dd62008-03-07 20:27:40 +00001381
1382 // FIXME alignment for ELF may not be right
1383 // FIXME the codegen can be much improved in some cases.
1384 // We do not have to keep everything in memory.
1385 if (isByVal) {
Dale Johannesen8419dd62008-03-07 20:27:40 +00001386 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1387 ObjSize = (Flags & ISD::ParamFlags::ByValSize) >>
1388 ISD::ParamFlags::ByValSizeOffs;
1389 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
Dale Johannesen7f96f392008-03-08 01:41:42 +00001390 // Double word align in ELF
1391 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1392 // Objects of size 1 and 2 are right justified, everything else is
1393 // left justified. This means the memory address is adjusted forwards.
1394 if (ObjSize==1 || ObjSize==2) {
1395 CurArgOffset = CurArgOffset + (4 - ObjSize);
1396 }
Dale Johannesen8419dd62008-03-07 20:27:40 +00001397 // The value of the object is its address.
1398 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
1399 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1400 ArgValues.push_back(FIN);
Dale Johannesen7f96f392008-03-08 01:41:42 +00001401 if (ObjSize==1 || ObjSize==2) {
1402 if (GPR_idx != Num_GPR_Regs) {
1403 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1404 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1405 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1406 SDOperand Store = DAG.getTruncStore(Val.getValue(1), Val, FIN,
1407 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
1408 MemOps.push_back(Store);
1409 ++GPR_idx;
1410 if (isMachoABI) ArgOffset += PtrByteSize;
1411 } else {
1412 ArgOffset += PtrByteSize;
1413 }
1414 continue;
1415 }
Dale Johannesen8419dd62008-03-07 20:27:40 +00001416 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1417 // Store whatever pieces of the object are in registers
1418 // to memory. ArgVal will be address of the beginning of
1419 // the object.
1420 if (GPR_idx != Num_GPR_Regs) {
1421 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1422 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1423 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
1424 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1425 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1426 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1427 MemOps.push_back(Store);
1428 ++GPR_idx;
1429 if (isMachoABI) ArgOffset += PtrByteSize;
1430 } else {
1431 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1432 break;
1433 }
1434 }
1435 continue;
1436 }
1437
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001438 switch (ObjectVT) {
1439 default: assert(0 && "Unhandled argument type!");
1440 case MVT::i32:
Bill Wendling5f5bf3a2008-03-07 20:49:02 +00001441 if (!isPPC64) {
1442 // Double word align in ELF
1443 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1444
1445 if (GPR_idx != Num_GPR_Regs) {
1446 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1447 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1448 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1449 ++GPR_idx;
1450 } else {
1451 needsLoad = true;
1452 ArgSize = PtrByteSize;
1453 }
1454 // Stack align in ELF
1455 if (needsLoad && Expand && isELF32_ABI)
1456 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1457 // All int arguments reserve stack space in Macho ABI.
1458 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1459 break;
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001460 }
Bill Wendling5f5bf3a2008-03-07 20:49:02 +00001461 // FALLTHROUGH
Chris Lattner9f0bc652007-02-25 05:34:32 +00001462 case MVT::i64: // PPC64
Chris Lattnerc91a4752006-06-26 22:48:35 +00001463 if (GPR_idx != Num_GPR_Regs) {
Chris Lattner84bc5422007-12-31 04:13:23 +00001464 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1465 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
Chris Lattnerc91a4752006-06-26 22:48:35 +00001466 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
Bill Wendling5f5bf3a2008-03-07 20:49:02 +00001467
1468 if (ObjectVT == MVT::i32) {
1469 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1470 // value to MVT::i64 and then truncate to the correct register size.
1471 if (Flags & ISD::ParamFlags::SExt)
1472 ArgVal = DAG.getNode(ISD::AssertSext, MVT::i64, ArgVal,
1473 DAG.getValueType(ObjectVT));
1474 else if (Flags & ISD::ParamFlags::ZExt)
1475 ArgVal = DAG.getNode(ISD::AssertZext, MVT::i64, ArgVal,
1476 DAG.getValueType(ObjectVT));
1477
1478 ArgVal = DAG.getNode(ISD::TRUNCATE, MVT::i32, ArgVal);
1479 }
1480
Chris Lattnerc91a4752006-06-26 22:48:35 +00001481 ++GPR_idx;
1482 } else {
1483 needsLoad = true;
1484 }
Chris Lattner9f0bc652007-02-25 05:34:32 +00001485 // All int arguments reserve stack space in Macho ABI.
1486 if (isMachoABI || needsLoad) ArgOffset += 8;
Chris Lattnerc91a4752006-06-26 22:48:35 +00001487 break;
Chris Lattner9f0bc652007-02-25 05:34:32 +00001488
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001489 case MVT::f32:
1490 case MVT::f64:
Chris Lattnerbe4849a2006-05-16 18:51:52 +00001491 // Every 4 bytes of argument space consumes one of the GPRs available for
1492 // argument passing.
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001493 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
Chris Lattneraf4ec0c2006-05-16 18:58:15 +00001494 ++GPR_idx;
Chris Lattnerb1eb9872006-11-18 01:57:19 +00001495 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
Chris Lattneraf4ec0c2006-05-16 18:58:15 +00001496 ++GPR_idx;
Chris Lattnerbe4849a2006-05-16 18:51:52 +00001497 }
Chris Lattneraf4ec0c2006-05-16 18:58:15 +00001498 if (FPR_idx != Num_FPR_Regs) {
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001499 unsigned VReg;
1500 if (ObjectVT == MVT::f32)
Chris Lattner84bc5422007-12-31 04:13:23 +00001501 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass);
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001502 else
Chris Lattner84bc5422007-12-31 04:13:23 +00001503 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1504 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001505 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001506 ++FPR_idx;
1507 } else {
1508 needsLoad = true;
1509 }
Chris Lattner9f0bc652007-02-25 05:34:32 +00001510
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001511 // Stack align in ELF
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00001512 if (needsLoad && Expand && isELF32_ABI)
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001513 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
Chris Lattner9f0bc652007-02-25 05:34:32 +00001514 // All FP arguments reserve stack space in Macho ABI.
1515 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001516 break;
1517 case MVT::v4f32:
1518 case MVT::v4i32:
1519 case MVT::v8i16:
1520 case MVT::v16i8:
Dale Johannesen75092de2008-03-12 00:22:17 +00001521 // Note that vector arguments in registers don't reserve stack space,
1522 // except in varargs functions.
Chris Lattneraf4ec0c2006-05-16 18:58:15 +00001523 if (VR_idx != Num_VR_Regs) {
Chris Lattner84bc5422007-12-31 04:13:23 +00001524 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
1525 RegInfo.addLiveIn(VR[VR_idx], VReg);
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001526 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
Dale Johannesen75092de2008-03-12 00:22:17 +00001527 if (isVarArg) {
1528 while ((ArgOffset % 16) != 0) {
1529 ArgOffset += PtrByteSize;
1530 if (GPR_idx != Num_GPR_Regs)
1531 GPR_idx++;
1532 }
1533 ArgOffset += 16;
1534 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs);
1535 }
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001536 ++VR_idx;
1537 } else {
1538 // This should be simple, but requires getting 16-byte aligned stack
1539 // values.
1540 assert(0 && "Loading VR argument not implemented yet!");
1541 needsLoad = true;
1542 }
1543 break;
1544 }
1545
1546 // We need to load the argument to a virtual register if we determined above
Chris Lattner9f72d1a2008-02-13 07:35:30 +00001547 // that we ran out of physical registers of the appropriate type.
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001548 if (needsLoad) {
Chris Lattner9f72d1a2008-02-13 07:35:30 +00001549 int FI = MFI->CreateFixedObject(ObjSize,
1550 CurArgOffset + (ArgSize - ObjSize));
1551 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1552 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001553 }
1554
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001555 ArgValues.push_back(ArgVal);
1556 }
Dale Johannesen8419dd62008-03-07 20:27:40 +00001557
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001558 // If the function takes variable number of arguments, make a frame index for
1559 // the start of the first vararg value... for expansion of llvm.va_start.
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001560 if (isVarArg) {
Nicolas Geoffray01119992007-04-03 13:59:52 +00001561
1562 int depth;
1563 if (isELF32_ABI) {
1564 VarArgsNumGPR = GPR_idx;
1565 VarArgsNumFPR = FPR_idx;
1566
1567 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1568 // pointer.
1569 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 +
1570 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 +
1571 MVT::getSizeInBits(PtrVT)/8);
1572
1573 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1574 ArgOffset);
1575
1576 }
1577 else
1578 depth = ArgOffset;
1579
Chris Lattnerc91a4752006-06-26 22:48:35 +00001580 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
Nicolas Geoffray01119992007-04-03 13:59:52 +00001581 depth);
Chris Lattnerc91a4752006-06-26 22:48:35 +00001582 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
Nicolas Geoffray01119992007-04-03 13:59:52 +00001583
Nicolas Geoffray01119992007-04-03 13:59:52 +00001584 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1585 // stored to the VarArgsFrameIndex on the stack.
1586 if (isELF32_ABI) {
1587 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1588 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1589 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1590 MemOps.push_back(Store);
1591 // Increment the address by four for the next argument to store
1592 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1593 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1594 }
1595 }
1596
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001597 // If this function is vararg, store any remaining integer argument regs
1598 // to their spots on the stack so that they may be loaded by deferencing the
1599 // result of va_next.
Chris Lattneraf4ec0c2006-05-16 18:58:15 +00001600 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
Chris Lattnerb1eb9872006-11-18 01:57:19 +00001601 unsigned VReg;
1602 if (isPPC64)
Chris Lattner84bc5422007-12-31 04:13:23 +00001603 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
Chris Lattnerb1eb9872006-11-18 01:57:19 +00001604 else
Chris Lattner84bc5422007-12-31 04:13:23 +00001605 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
Chris Lattnerb1eb9872006-11-18 01:57:19 +00001606
Chris Lattner84bc5422007-12-31 04:13:23 +00001607 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
Chris Lattnerc91a4752006-06-26 22:48:35 +00001608 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
Evan Cheng8b2794a2006-10-13 21:14:26 +00001609 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001610 MemOps.push_back(Store);
1611 // Increment the address by four for the next argument to store
Chris Lattnerc91a4752006-06-26 22:48:35 +00001612 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1613 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001614 }
Nicolas Geoffray01119992007-04-03 13:59:52 +00001615
1616 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1617 // on the stack.
1618 if (isELF32_ABI) {
1619 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1620 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1621 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1622 MemOps.push_back(Store);
1623 // Increment the address by eight for the next argument to store
1624 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1625 PtrVT);
1626 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1627 }
1628
1629 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1630 unsigned VReg;
Chris Lattner84bc5422007-12-31 04:13:23 +00001631 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
Nicolas Geoffray01119992007-04-03 13:59:52 +00001632
Chris Lattner84bc5422007-12-31 04:13:23 +00001633 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
Nicolas Geoffray01119992007-04-03 13:59:52 +00001634 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1635 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1636 MemOps.push_back(Store);
1637 // Increment the address by eight for the next argument to store
1638 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1639 PtrVT);
1640 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1641 }
1642 }
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001643 }
1644
Dale Johannesen8419dd62008-03-07 20:27:40 +00001645 if (!MemOps.empty())
1646 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1647
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001648 ArgValues.push_back(Root);
1649
1650 // Return the new list of results.
1651 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1652 Op.Val->value_end());
Chris Lattner79e490a2006-08-11 17:18:05 +00001653 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
Chris Lattner8ab5fe52006-05-16 18:18:50 +00001654}
1655
Chris Lattnerc703a8f2006-05-17 19:00:46 +00001656/// isCallCompatibleAddress - Return the immediate to use if the specified
1657/// 32-bit value is representable in the immediate field of a BxA instruction.
1658static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1659 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1660 if (!C) return 0;
1661
1662 int Addr = C->getValue();
1663 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1664 (Addr << 6 >> 6) != Addr)
1665 return 0; // Top 6 bits have to be sext of immediate.
1666
Evan Cheng33118762007-10-22 19:46:19 +00001667 return DAG.getConstant((int)C->getValue() >> 2,
1668 DAG.getTargetLoweringInfo().getPointerTy()).Val;
Chris Lattnerc703a8f2006-05-17 19:00:46 +00001669}
1670
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001671/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1672/// by "Src" to address "Dst" of size "Size". Alignment information is
1673/// specified by the specific parameter attribute. The copy will be passed as
1674/// a byval function parameter.
1675/// Sometimes what we are copying is the end of a larger object, the part that
1676/// does not fit in registers.
1677static SDOperand
1678CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain,
Dale Johannesenb8cafe32008-03-10 02:17:22 +00001679 ISD::ParamFlags::ParamFlagsTy Flags,
1680 SelectionDAG &DAG, unsigned Size) {
1681 unsigned Align = ISD::ParamFlags::One <<
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001682 ((Flags & ISD::ParamFlags::ByValAlign) >> ISD::ParamFlags::ByValAlignOffs);
1683 SDOperand AlignNode = DAG.getConstant(Align, MVT::i32);
1684 SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
Dale Johannesen1f797a32008-03-05 23:31:27 +00001685 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i32);
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001686 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, AlignNode, AlwaysInline);
1687}
Chris Lattner9f0bc652007-02-25 05:34:32 +00001688
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001689SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG,
1690 const PPCSubtarget &Subtarget) {
Chris Lattner9f0bc652007-02-25 05:34:32 +00001691 SDOperand Chain = Op.getOperand(0);
1692 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1693 SDOperand Callee = Op.getOperand(4);
1694 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1695
1696 bool isMachoABI = Subtarget.isMachoABI();
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00001697 bool isELF32_ABI = Subtarget.isELF32_ABI();
Evan Cheng4360bdc2006-05-25 00:57:32 +00001698
Chris Lattnerc91a4752006-06-26 22:48:35 +00001699 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1700 bool isPPC64 = PtrVT == MVT::i64;
1701 unsigned PtrByteSize = isPPC64 ? 8 : 4;
Chris Lattnerc91a4752006-06-26 22:48:35 +00001702
Chris Lattnerabde4602006-05-16 22:56:08 +00001703 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1704 // SelectExpr to use to put the arguments in the appropriate registers.
1705 std::vector<SDOperand> args_to_use;
1706
1707 // Count how many bytes are to be pushed on the stack, including the linkage
Chris Lattnerc91a4752006-06-26 22:48:35 +00001708 // area, and parameter passing area. We start with 24/48 bytes, which is
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001709 // prereserved space for [SP][CR][LR][3 x unused].
Chris Lattner9f0bc652007-02-25 05:34:32 +00001710 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
Dale Johannesen75092de2008-03-12 00:22:17 +00001711
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001712 // Add up all the space actually used.
Jim Laskeye9bd7b22006-11-28 14:53:52 +00001713 for (unsigned i = 0; i != NumOps; ++i) {
Dale Johannesen75092de2008-03-12 00:22:17 +00001714 SDOperand Arg = Op.getOperand(5+2*i);
1715 MVT::ValueType ArgVT = Arg.getValueType();
1716 // Non-varargs Altivec parameters do not have corresponding stack space.
1717 if (!isVarArg &&
1718 (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
1719 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8))
1720 continue;
Dale Johannesenb8cafe32008-03-10 02:17:22 +00001721 ISD::ParamFlags::ParamFlagsTy Flags =
1722 cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
Jim Laskeye9bd7b22006-11-28 14:53:52 +00001723 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001724 if (Flags & ISD::ParamFlags::ByVal)
1725 ArgSize = (Flags & ISD::ParamFlags::ByValSize) >>
1726 ISD::ParamFlags::ByValSizeOffs;
Dale Johannesen7f96f392008-03-08 01:41:42 +00001727 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
Dale Johannesen75092de2008-03-12 00:22:17 +00001728 // Varargs Altivec parameters are padded to a 16 byte boundary.
1729 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
1730 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8)
1731 NumBytes = ((NumBytes+15)/16)*16;
Jim Laskeye9bd7b22006-11-28 14:53:52 +00001732 NumBytes += ArgSize;
1733 }
Chris Lattnerc04ba7a2006-05-16 23:54:25 +00001734
Chris Lattner7b053502006-05-30 21:21:04 +00001735 // The prolog code of the callee may store up to 8 GPR argument registers to
1736 // the stack, allowing va_start to index over them in memory if its varargs.
1737 // Because we cannot tell if this is needed on the caller side, we have to
1738 // conservatively assume that it is needed. As such, make sure we have at
1739 // least enough stack space for the caller to store the 8 GPRs.
Chris Lattner9f0bc652007-02-25 05:34:32 +00001740 NumBytes = std::max(NumBytes,
1741 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001742
1743 // Adjust the stack pointer for the new arguments...
1744 // These operations are automatically eliminated by the prolog/epilog pass
1745 Chain = DAG.getCALLSEQ_START(Chain,
Chris Lattnerc91a4752006-06-26 22:48:35 +00001746 DAG.getConstant(NumBytes, PtrVT));
Dale Johannesen1f797a32008-03-05 23:31:27 +00001747 SDOperand CallSeqStart = Chain;
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001748
1749 // Set up a copy of the stack pointer for use loading and storing any
1750 // arguments that may not fit in the registers available for argument
1751 // passing.
Chris Lattnerc91a4752006-06-26 22:48:35 +00001752 SDOperand StackPtr;
1753 if (isPPC64)
1754 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
1755 else
1756 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001757
1758 // Figure out which arguments are going to go in registers, and which in
1759 // memory. Also, if this is a vararg function, floating point operations
1760 // must be stored to our stack, and loaded into integer regs as well, if
1761 // any integer regs are available for argument passing.
Chris Lattner9f0bc652007-02-25 05:34:32 +00001762 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
Chris Lattner9a2a4972006-05-17 06:01:33 +00001763 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
Jim Laskey2f616bf2006-11-16 22:43:37 +00001764
Chris Lattnerc91a4752006-06-26 22:48:35 +00001765 static const unsigned GPR_32[] = { // 32-bit registers.
Chris Lattner9a2a4972006-05-17 06:01:33 +00001766 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1767 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1768 };
Chris Lattnerc91a4752006-06-26 22:48:35 +00001769 static const unsigned GPR_64[] = { // 64-bit registers.
1770 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1771 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1772 };
Chris Lattner9f0bc652007-02-25 05:34:32 +00001773 static const unsigned *FPR = GetFPR(Subtarget);
1774
Chris Lattner9a2a4972006-05-17 06:01:33 +00001775 static const unsigned VR[] = {
1776 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1777 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1778 };
Owen Anderson718cb662007-09-07 04:06:50 +00001779 const unsigned NumGPRs = array_lengthof(GPR_32);
Nicolas Geoffrayef3c0302007-04-03 10:27:07 +00001780 const unsigned NumFPRs = isMachoABI ? 13 : 8;
Owen Anderson718cb662007-09-07 04:06:50 +00001781 const unsigned NumVRs = array_lengthof( VR);
Chris Lattner9a2a4972006-05-17 06:01:33 +00001782
Chris Lattnerc91a4752006-06-26 22:48:35 +00001783 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1784
Chris Lattner9a2a4972006-05-17 06:01:33 +00001785 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
Chris Lattnere2199452006-08-11 17:38:39 +00001786 SmallVector<SDOperand, 8> MemOpChains;
Evan Cheng4360bdc2006-05-25 00:57:32 +00001787 for (unsigned i = 0; i != NumOps; ++i) {
Chris Lattner9f0bc652007-02-25 05:34:32 +00001788 bool inMem = false;
Evan Cheng4360bdc2006-05-25 00:57:32 +00001789 SDOperand Arg = Op.getOperand(5+2*i);
Dale Johannesenb8cafe32008-03-10 02:17:22 +00001790 ISD::ParamFlags::ParamFlagsTy Flags =
1791 cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
1792 unsigned AlignFlag = ISD::ParamFlags::One <<
1793 ISD::ParamFlags::OrigAlignmentOffs;
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001794 // See if next argument requires stack alignment in ELF
1795 unsigned next = 5+2*(i+1)+1;
1796 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) &&
1797 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) &&
1798 (!(Flags & AlignFlag)));
1799
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001800 // PtrOff will be used to store the current argument to the stack if a
1801 // register cannot be found for it.
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001802 SDOperand PtrOff;
1803
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00001804 // Stack align in ELF 32
1805 if (isELF32_ABI && Expand)
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001806 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
1807 StackPtr.getValueType());
1808 else
1809 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1810
Chris Lattnerc91a4752006-06-26 22:48:35 +00001811 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1812
1813 // On PPC64, promote integers to 64-bit values.
1814 if (isPPC64 && Arg.getValueType() == MVT::i32) {
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001815 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
Chris Lattnerc91a4752006-06-26 22:48:35 +00001816 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1817 }
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001818
1819 // FIXME Elf untested, what are alignment rules?
Dale Johannesen8419dd62008-03-07 20:27:40 +00001820 // FIXME memcpy is used way more than necessary. Correctness first.
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001821 if (Flags & ISD::ParamFlags::ByVal) {
1822 unsigned Size = (Flags & ISD::ParamFlags::ByValSize) >>
1823 ISD::ParamFlags::ByValSizeOffs;
1824 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
Dale Johannesen8419dd62008-03-07 20:27:40 +00001825 if (Size==1 || Size==2) {
1826 // Very small objects are passed right-justified.
1827 // Everything else is passed left-justified.
1828 MVT::ValueType VT = (Size==1) ? MVT::i8 : MVT::i16;
1829 if (GPR_idx != NumGPRs) {
1830 SDOperand Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg,
1831 NULL, 0, VT);
1832 MemOpChains.push_back(Load.getValue(1));
1833 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1834 if (isMachoABI)
1835 ArgOffset += PtrByteSize;
1836 } else {
1837 SDOperand Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
1838 SDOperand AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const);
1839 SDOperand MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
1840 CallSeqStart.Val->getOperand(0),
1841 Flags, DAG, Size);
1842 // This must go outside the CALLSEQ_START..END.
1843 SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
1844 CallSeqStart.Val->getOperand(1));
1845 DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
1846 Chain = CallSeqStart = NewCallSeqStart;
1847 ArgOffset += PtrByteSize;
1848 }
1849 continue;
1850 }
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001851 for (unsigned j=0; j<Size; j+=PtrByteSize) {
1852 SDOperand Const = DAG.getConstant(j, PtrOff.getValueType());
1853 SDOperand AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const);
1854 if (GPR_idx != NumGPRs) {
1855 SDOperand Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0);
Dale Johannesen1f797a32008-03-05 23:31:27 +00001856 MemOpChains.push_back(Load.getValue(1));
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001857 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1858 if (isMachoABI)
1859 ArgOffset += PtrByteSize;
1860 } else {
1861 SDOperand AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const);
Dale Johannesen1f797a32008-03-05 23:31:27 +00001862 SDOperand MemcpyCall = CreateCopyOfByValArgument(AddArg, AddPtr,
1863 CallSeqStart.Val->getOperand(0),
1864 Flags, DAG, Size - j);
1865 // This must go outside the CALLSEQ_START..END.
1866 SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
1867 CallSeqStart.Val->getOperand(1));
1868 DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
Dale Johannesen8419dd62008-03-07 20:27:40 +00001869 Chain = CallSeqStart = NewCallSeqStart;
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001870 ArgOffset += ((Size - j + 3)/4)*4;
Dale Johannesen8419dd62008-03-07 20:27:40 +00001871 break;
Dale Johannesen5b3b6952008-03-04 23:17:14 +00001872 }
1873 }
1874 continue;
1875 }
1876
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001877 switch (Arg.getValueType()) {
1878 default: assert(0 && "Unexpected ValueType for argument!");
1879 case MVT::i32:
Chris Lattnerc91a4752006-06-26 22:48:35 +00001880 case MVT::i64:
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001881 // Double word align in ELF
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00001882 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
Chris Lattner9a2a4972006-05-17 06:01:33 +00001883 if (GPR_idx != NumGPRs) {
1884 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001885 } else {
Evan Cheng8b2794a2006-10-13 21:14:26 +00001886 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
Chris Lattner9f0bc652007-02-25 05:34:32 +00001887 inMem = true;
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001888 }
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001889 if (inMem || isMachoABI) {
1890 // Stack align in ELF
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00001891 if (isELF32_ABI && Expand)
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001892 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1893
1894 ArgOffset += PtrByteSize;
1895 }
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001896 break;
1897 case MVT::f32:
1898 case MVT::f64:
Chris Lattner4ddf7a42007-02-25 20:01:40 +00001899 if (isVarArg) {
Jim Laskeyfbb74e62006-12-01 16:30:47 +00001900 // Float varargs need to be promoted to double.
1901 if (Arg.getValueType() == MVT::f32)
1902 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
1903 }
1904
Chris Lattner9a2a4972006-05-17 06:01:33 +00001905 if (FPR_idx != NumFPRs) {
1906 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1907
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001908 if (isVarArg) {
Evan Cheng8b2794a2006-10-13 21:14:26 +00001909 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
Chris Lattner9a2a4972006-05-17 06:01:33 +00001910 MemOpChains.push_back(Store);
1911
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001912 // Float varargs are always shadowed in available integer registers
Chris Lattner9a2a4972006-05-17 06:01:33 +00001913 if (GPR_idx != NumGPRs) {
Evan Cheng466685d2006-10-09 20:57:25 +00001914 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
Chris Lattner9a2a4972006-05-17 06:01:33 +00001915 MemOpChains.push_back(Load.getValue(1));
Chris Lattner9f0bc652007-02-25 05:34:32 +00001916 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1917 Load));
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001918 }
Jim Laskeyfbb74e62006-12-01 16:30:47 +00001919 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001920 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
Chris Lattnerc91a4752006-06-26 22:48:35 +00001921 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
Evan Cheng466685d2006-10-09 20:57:25 +00001922 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
Chris Lattner9a2a4972006-05-17 06:01:33 +00001923 MemOpChains.push_back(Load.getValue(1));
Chris Lattner9f0bc652007-02-25 05:34:32 +00001924 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1925 Load));
Chris Lattnerabde4602006-05-16 22:56:08 +00001926 }
1927 } else {
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001928 // If we have any FPRs remaining, we may also have GPRs remaining.
1929 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1930 // GPRs.
Chris Lattner9f0bc652007-02-25 05:34:32 +00001931 if (isMachoABI) {
1932 if (GPR_idx != NumGPRs)
1933 ++GPR_idx;
1934 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
1935 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
1936 ++GPR_idx;
1937 }
Chris Lattnerabde4602006-05-16 22:56:08 +00001938 }
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001939 } else {
Evan Cheng8b2794a2006-10-13 21:14:26 +00001940 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
Chris Lattner9f0bc652007-02-25 05:34:32 +00001941 inMem = true;
Chris Lattnerabde4602006-05-16 22:56:08 +00001942 }
Chris Lattner9f0bc652007-02-25 05:34:32 +00001943 if (inMem || isMachoABI) {
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001944 // Stack align in ELF
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00001945 if (isELF32_ABI && Expand)
Nicolas Geoffrayb2ec1cc2007-03-13 15:02:46 +00001946 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
Chris Lattner9f0bc652007-02-25 05:34:32 +00001947 if (isPPC64)
1948 ArgOffset += 8;
1949 else
1950 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1951 }
Chris Lattnerc8b682c2006-05-17 00:15:40 +00001952 break;
1953 case MVT::v4f32:
1954 case MVT::v4i32:
1955 case MVT::v8i16:
1956 case MVT::v16i8:
Dale Johannesen75092de2008-03-12 00:22:17 +00001957 if (isVarArg) {
1958 // These go aligned on the stack, or in the corresponding R registers
1959 // when within range. The Darwin PPC ABI doc claims they also go in
1960 // V registers; in fact gcc does this only for arguments that are
1961 // prototyped, not for those that match the ... We do it for all
1962 // arguments, seems to work.
1963 while (ArgOffset % 16 !=0) {
1964 ArgOffset += PtrByteSize;
1965 if (GPR_idx != NumGPRs)
1966 GPR_idx++;
1967 }
1968 // We could elide this store in the case where the object fits
1969 // entirely in R registers. Maybe later.
1970 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr,
1971 DAG.getConstant(ArgOffset, PtrVT));
1972 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1973 MemOpChains.push_back(Store);
1974 if (VR_idx != NumVRs) {
1975 SDOperand Load = DAG.getLoad(MVT::v4f32, Store, PtrOff, NULL, 0);
1976 MemOpChains.push_back(Load.getValue(1));
1977 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
1978 }
1979 ArgOffset += 16;
1980 for (unsigned i=0; i<16; i+=PtrByteSize) {
1981 if (GPR_idx == NumGPRs)
1982 break;
1983 SDOperand Ix = DAG.getNode(ISD::ADD, PtrVT, PtrOff,
1984 DAG.getConstant(i, PtrVT));
1985 SDOperand Load = DAG.getLoad(PtrVT, Store, Ix, NULL, 0);
1986 MemOpChains.push_back(Load.getValue(1));
1987 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1988 }
1989 break;
1990 }
1991 if (VR_idx == NumVRs) {
1992 // Out of V registers; these go aligned on the stack.
1993 while (ArgOffset % 16 !=0) {
1994 ArgOffset += PtrByteSize;
1995 }
1996 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr,
1997 DAG.getConstant(ArgOffset, PtrVT));
1998 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1999 MemOpChains.push_back(Store);
2000 ArgOffset += 16;
2001 } else {
2002 // Doesn't have memory or GPR space allocated
2003 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
2004 }
Chris Lattnerc8b682c2006-05-17 00:15:40 +00002005 break;
Chris Lattnerabde4602006-05-16 22:56:08 +00002006 }
Chris Lattnerabde4602006-05-16 22:56:08 +00002007 }
Chris Lattner9a2a4972006-05-17 06:01:33 +00002008 if (!MemOpChains.empty())
Chris Lattnere2199452006-08-11 17:38:39 +00002009 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2010 &MemOpChains[0], MemOpChains.size());
Chris Lattnerabde4602006-05-16 22:56:08 +00002011
Chris Lattner9a2a4972006-05-17 06:01:33 +00002012 // Build a sequence of copy-to-reg nodes chained together with token chain
2013 // and flag operands which copy the outgoing args into the appropriate regs.
2014 SDOperand InFlag;
2015 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2016 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
2017 InFlag);
2018 InFlag = Chain.getValue(1);
2019 }
Chris Lattner9f0bc652007-02-25 05:34:32 +00002020
Nicolas Geoffrayec58d9f2007-04-03 12:35:28 +00002021 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
2022 if (isVarArg && isELF32_ABI) {
Nicolas Geoffray0404cd92008-03-10 14:12:10 +00002023 SDOperand SetCR(DAG.getTargetNode(PPC::CRSET, MVT::i32), 0);
2024 Chain = DAG.getCopyToReg(Chain, PPC::CR1EQ, SetCR, InFlag);
Chris Lattner9f0bc652007-02-25 05:34:32 +00002025 InFlag = Chain.getValue(1);
2026 }
2027
Chris Lattnerc703a8f2006-05-17 19:00:46 +00002028 std::vector<MVT::ValueType> NodeTys;
Chris Lattner4a45abf2006-06-10 01:14:28 +00002029 NodeTys.push_back(MVT::Other); // Returns a chain
2030 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2031
Chris Lattner79e490a2006-08-11 17:18:05 +00002032 SmallVector<SDOperand, 8> Ops;
Nicolas Geoffray63f8fb12007-02-27 13:01:19 +00002033 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
Chris Lattnerc703a8f2006-05-17 19:00:46 +00002034
2035 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2036 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2037 // node so that legalize doesn't hack it.
Nicolas Geoffray5a6c91a2007-12-21 12:22:29 +00002038 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2039 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
2040 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
Chris Lattnerc703a8f2006-05-17 19:00:46 +00002041 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
2042 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
2043 // If this is an absolute destination address, use the munged value.
2044 Callee = SDOperand(Dest, 0);
2045 else {
2046 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2047 // to do the call, we can't use PPCISD::CALL.
Chris Lattner79e490a2006-08-11 17:18:05 +00002048 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
2049 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
Chris Lattnerc703a8f2006-05-17 19:00:46 +00002050 InFlag = Chain.getValue(1);
2051
Chris Lattnerdc9971a2008-03-09 20:49:33 +00002052 // Copy the callee address into R12/X12 on darwin.
Chris Lattner9f0bc652007-02-25 05:34:32 +00002053 if (isMachoABI) {
Chris Lattnerdc9971a2008-03-09 20:49:33 +00002054 unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12;
2055 Chain = DAG.getCopyToReg(Chain, Reg, Callee, InFlag);
Chris Lattner9f0bc652007-02-25 05:34:32 +00002056 InFlag = Chain.getValue(1);
2057 }
Chris Lattnerc703a8f2006-05-17 19:00:46 +00002058
2059 NodeTys.clear();
2060 NodeTys.push_back(MVT::Other);
2061 NodeTys.push_back(MVT::Flag);
Chris Lattnerc703a8f2006-05-17 19:00:46 +00002062 Ops.push_back(Chain);
Chris Lattner9f0bc652007-02-25 05:34:32 +00002063 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
Chris Lattnerc703a8f2006-05-17 19:00:46 +00002064 Callee.Val = 0;
2065 }
Chris Lattner9a2a4972006-05-17 06:01:33 +00002066
Chris Lattner4a45abf2006-06-10 01:14:28 +00002067 // If this is a direct call, pass the chain and the callee.
Chris Lattnerc703a8f2006-05-17 19:00:46 +00002068 if (Callee.Val) {
Chris Lattnerc703a8f2006-05-17 19:00:46 +00002069 Ops.push_back(Chain);
2070 Ops.push_back(Callee);
Chris Lattnerc703a8f2006-05-17 19:00:46 +00002071 }
Chris Lattnerabde4602006-05-16 22:56:08 +00002072
Chris Lattner4a45abf2006-06-10 01:14:28 +00002073 // Add argument registers to the end of the list so that they are known live
2074 // into the call.
2075 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2076 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2077 RegsToPass[i].second.getValueType()));
2078
2079 if (InFlag.Val)
2080 Ops.push_back(InFlag);
Chris Lattner79e490a2006-08-11 17:18:05 +00002081 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
Chris Lattner4a45abf2006-06-10 01:14:28 +00002082 InFlag = Chain.getValue(1);
2083
Bill Wendling0f8d9c02007-11-13 00:44:25 +00002084 Chain = DAG.getCALLSEQ_END(Chain,
2085 DAG.getConstant(NumBytes, PtrVT),
2086 DAG.getConstant(0, PtrVT),
2087 InFlag);
2088 if (Op.Val->getValueType(0) != MVT::Other)
2089 InFlag = Chain.getValue(1);
2090
Chris Lattner79e490a2006-08-11 17:18:05 +00002091 SDOperand ResultVals[3];
2092 unsigned NumResults = 0;
Chris Lattner9a2a4972006-05-17 06:01:33 +00002093 NodeTys.clear();
2094
2095 // If the call has results, copy the values out of the ret val registers.
2096 switch (Op.Val->getValueType(0)) {
2097 default: assert(0 && "Unexpected ret value!");
2098 case MVT::Other: break;
2099 case MVT::i32:
2100 if (Op.Val->getValueType(1) == MVT::i32) {
Dan Gohman532dc2e2007-07-09 20:59:04 +00002101 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
Chris Lattner79e490a2006-08-11 17:18:05 +00002102 ResultVals[0] = Chain.getValue(0);
Dan Gohman532dc2e2007-07-09 20:59:04 +00002103 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32,
Chris Lattner9a2a4972006-05-17 06:01:33 +00002104 Chain.getValue(2)).getValue(1);
Chris Lattner79e490a2006-08-11 17:18:05 +00002105 ResultVals[1] = Chain.getValue(0);
2106 NumResults = 2;
Chris Lattner9a2a4972006-05-17 06:01:33 +00002107 NodeTys.push_back(MVT::i32);
2108 } else {
2109 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
Chris Lattner79e490a2006-08-11 17:18:05 +00002110 ResultVals[0] = Chain.getValue(0);
2111 NumResults = 1;
Chris Lattner9a2a4972006-05-17 06:01:33 +00002112 }
2113 NodeTys.push_back(MVT::i32);
2114 break;
Chris Lattnerc91a4752006-06-26 22:48:35 +00002115 case MVT::i64:
Dan Gohmana2fcff42008-03-08 00:19:12 +00002116 if (Op.Val->getValueType(1) == MVT::i64) {
2117 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
2118 ResultVals[0] = Chain.getValue(0);
2119 Chain = DAG.getCopyFromReg(Chain, PPC::X4, MVT::i64,
2120 Chain.getValue(2)).getValue(1);
2121 ResultVals[1] = Chain.getValue(0);
2122 NumResults = 2;
2123 NodeTys.push_back(MVT::i64);
2124 } else {
2125 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
2126 ResultVals[0] = Chain.getValue(0);
2127 NumResults = 1;
2128 }
Chris Lattnerc91a4752006-06-26 22:48:35 +00002129 NodeTys.push_back(MVT::i64);
2130 break;
Chris Lattner9a2a4972006-05-17 06:01:33 +00002131 case MVT::f64:
Dale Johannesen161e8972007-10-05 20:04:43 +00002132 if (Op.Val->getValueType(1) == MVT::f64) {
2133 Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1);
2134 ResultVals[0] = Chain.getValue(0);
2135 Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64,
2136 Chain.getValue(2)).getValue(1);
2137 ResultVals[1] = Chain.getValue(0);
2138 NumResults = 2;
2139 NodeTys.push_back(MVT::f64);
2140 NodeTys.push_back(MVT::f64);
2141 break;
2142 }
2143 // else fall through
2144 case MVT::f32:
Chris Lattner9a2a4972006-05-17 06:01:33 +00002145 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
2146 InFlag).getValue(1);
Chris Lattner79e490a2006-08-11 17:18:05 +00002147 ResultVals[0] = Chain.getValue(0);
2148 NumResults = 1;
Chris Lattner9a2a4972006-05-17 06:01:33 +00002149 NodeTys.push_back(Op.Val->getValueType(0));
2150 break;
2151 case MVT::v4f32:
2152 case MVT::v4i32:
2153 case MVT::v8i16:
2154 case MVT::v16i8:
2155 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
2156 InFlag).getValue(1);
Chris Lattner79e490a2006-08-11 17:18:05 +00002157 ResultVals[0] = Chain.getValue(0);
2158 NumResults = 1;
Chris Lattner9a2a4972006-05-17 06:01:33 +00002159 NodeTys.push_back(Op.Val->getValueType(0));
2160 break;
2161 }
2162
Chris Lattner9a2a4972006-05-17 06:01:33 +00002163 NodeTys.push_back(MVT::Other);
Chris Lattnerabde4602006-05-16 22:56:08 +00002164
Chris Lattnerc703a8f2006-05-17 19:00:46 +00002165 // If the function returns void, just return the chain.
Chris Lattnerf6e190f2006-08-12 07:20:05 +00002166 if (NumResults == 0)
Chris Lattnerc703a8f2006-05-17 19:00:46 +00002167 return Chain;
2168
2169 // Otherwise, merge everything together with a MERGE_VALUES node.
Chris Lattner79e490a2006-08-11 17:18:05 +00002170 ResultVals[NumResults++] = Chain;
2171 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
2172 ResultVals, NumResults);
Chris Lattnerabde4602006-05-16 22:56:08 +00002173 return Res.getValue(Op.ResNo);
2174}
2175
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002176SDOperand PPCTargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG,
2177 TargetMachine &TM) {
Chris Lattnerb9a7bea2007-03-06 00:59:59 +00002178 SmallVector<CCValAssign, 16> RVLocs;
2179 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
Chris Lattner52387be2007-06-19 00:13:10 +00002180 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
2181 CCState CCInfo(CC, isVarArg, TM, RVLocs);
Chris Lattnerb9a7bea2007-03-06 00:59:59 +00002182 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
2183
2184 // If this is the first return lowered for this function, add the regs to the
2185 // liveout set for the function.
Chris Lattner84bc5422007-12-31 04:13:23 +00002186 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
Chris Lattnerb9a7bea2007-03-06 00:59:59 +00002187 for (unsigned i = 0; i != RVLocs.size(); ++i)
Chris Lattner84bc5422007-12-31 04:13:23 +00002188 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
Chris Lattnerb9a7bea2007-03-06 00:59:59 +00002189 }
2190
Chris Lattnercaddd442007-02-26 19:44:02 +00002191 SDOperand Chain = Op.getOperand(0);
Chris Lattnerb9a7bea2007-03-06 00:59:59 +00002192 SDOperand Flag;
2193
2194 // Copy the result values into the output registers.
2195 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2196 CCValAssign &VA = RVLocs[i];
2197 assert(VA.isRegLoc() && "Can only return in registers!");
2198 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
2199 Flag = Chain.getValue(1);
2200 }
2201
2202 if (Flag.Val)
2203 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
2204 else
Chris Lattnercaddd442007-02-26 19:44:02 +00002205 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
Chris Lattner1a635d62006-04-14 06:01:58 +00002206}
2207
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002208SDOperand PPCTargetLowering::LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
Jim Laskeyefc7e522006-12-04 22:04:42 +00002209 const PPCSubtarget &Subtarget) {
2210 // When we pop the dynamic allocation we need to restore the SP link.
2211
2212 // Get the corect type for pointers.
2213 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2214
2215 // Construct the stack pointer operand.
2216 bool IsPPC64 = Subtarget.isPPC64();
2217 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
2218 SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
2219
2220 // Get the operands for the STACKRESTORE.
2221 SDOperand Chain = Op.getOperand(0);
2222 SDOperand SaveSP = Op.getOperand(1);
2223
2224 // Load the old link SP.
2225 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
2226
2227 // Restore the stack pointer.
2228 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
2229
2230 // Store the old link SP.
2231 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
2232}
2233
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002234SDOperand PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
2235 SelectionDAG &DAG,
Jim Laskey2f616bf2006-11-16 22:43:37 +00002236 const PPCSubtarget &Subtarget) {
2237 MachineFunction &MF = DAG.getMachineFunction();
2238 bool IsPPC64 = Subtarget.isPPC64();
Chris Lattner9f0bc652007-02-25 05:34:32 +00002239 bool isMachoABI = Subtarget.isMachoABI();
Jim Laskey2f616bf2006-11-16 22:43:37 +00002240
2241 // Get current frame pointer save index. The users of this index will be
2242 // primarily DYNALLOC instructions.
2243 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2244 int FPSI = FI->getFramePointerSaveIndex();
Chris Lattner9f0bc652007-02-25 05:34:32 +00002245
Jim Laskey2f616bf2006-11-16 22:43:37 +00002246 // If the frame pointer save index hasn't been defined yet.
2247 if (!FPSI) {
2248 // Find out what the fix offset of the frame pointer save area.
Chris Lattner9f0bc652007-02-25 05:34:32 +00002249 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
2250
Jim Laskey2f616bf2006-11-16 22:43:37 +00002251 // Allocate the frame index for frame pointer save area.
Chris Lattner9f0bc652007-02-25 05:34:32 +00002252 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
Jim Laskey2f616bf2006-11-16 22:43:37 +00002253 // Save the result.
2254 FI->setFramePointerSaveIndex(FPSI);
2255 }
2256
2257 // Get the inputs.
2258 SDOperand Chain = Op.getOperand(0);
2259 SDOperand Size = Op.getOperand(1);
2260
2261 // Get the corect type for pointers.
2262 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2263 // Negate the size.
2264 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
2265 DAG.getConstant(0, PtrVT), Size);
2266 // Construct a node for the frame pointer save index.
2267 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT);
2268 // Build a DYNALLOC node.
2269 SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
2270 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
2271 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
2272}
2273
2274
Chris Lattner1a635d62006-04-14 06:01:58 +00002275/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
2276/// possible.
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002277SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner1a635d62006-04-14 06:01:58 +00002278 // Not FP? Not a fsel.
2279 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
2280 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
2281 return SDOperand();
2282
2283 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2284
2285 // Cannot handle SETEQ/SETNE.
2286 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
2287
2288 MVT::ValueType ResVT = Op.getValueType();
2289 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
2290 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2291 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
2292
2293 // If the RHS of the comparison is a 0.0, we don't need to do the
2294 // subtraction at all.
2295 if (isFloatingPointZero(RHS))
2296 switch (CC) {
2297 default: break; // SETUO etc aren't handled by fsel.
2298 case ISD::SETULT:
Chris Lattner57340122006-05-24 00:06:44 +00002299 case ISD::SETOLT:
Chris Lattner1a635d62006-04-14 06:01:58 +00002300 case ISD::SETLT:
2301 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2302 case ISD::SETUGE:
Chris Lattner57340122006-05-24 00:06:44 +00002303 case ISD::SETOGE:
Chris Lattner1a635d62006-04-14 06:01:58 +00002304 case ISD::SETGE:
2305 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2306 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2307 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
2308 case ISD::SETUGT:
Chris Lattner57340122006-05-24 00:06:44 +00002309 case ISD::SETOGT:
Chris Lattner1a635d62006-04-14 06:01:58 +00002310 case ISD::SETGT:
2311 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2312 case ISD::SETULE:
Chris Lattner57340122006-05-24 00:06:44 +00002313 case ISD::SETOLE:
Chris Lattner1a635d62006-04-14 06:01:58 +00002314 case ISD::SETLE:
2315 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2316 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2317 return DAG.getNode(PPCISD::FSEL, ResVT,
2318 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
2319 }
2320
Chris Lattner1de7c1d2007-10-15 20:14:52 +00002321 SDOperand Cmp;
Chris Lattner1a635d62006-04-14 06:01:58 +00002322 switch (CC) {
2323 default: break; // SETUO etc aren't handled by fsel.
2324 case ISD::SETULT:
Chris Lattner57340122006-05-24 00:06:44 +00002325 case ISD::SETOLT:
Chris Lattner1a635d62006-04-14 06:01:58 +00002326 case ISD::SETLT:
2327 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2328 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2329 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2330 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2331 case ISD::SETUGE:
Chris Lattner57340122006-05-24 00:06:44 +00002332 case ISD::SETOGE:
Chris Lattner1a635d62006-04-14 06:01:58 +00002333 case ISD::SETGE:
2334 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2335 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2336 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2337 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2338 case ISD::SETUGT:
Chris Lattner57340122006-05-24 00:06:44 +00002339 case ISD::SETOGT:
Chris Lattner1a635d62006-04-14 06:01:58 +00002340 case ISD::SETGT:
2341 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2342 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2343 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2344 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2345 case ISD::SETULE:
Chris Lattner57340122006-05-24 00:06:44 +00002346 case ISD::SETOLE:
Chris Lattner1a635d62006-04-14 06:01:58 +00002347 case ISD::SETLE:
2348 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2349 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2350 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2351 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2352 }
2353 return SDOperand();
2354}
2355
Chris Lattner1f873002007-11-28 18:44:47 +00002356// FIXME: Split this code up when LegalizeDAGTypes lands.
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002357SDOperand PPCTargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner1a635d62006-04-14 06:01:58 +00002358 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
2359 SDOperand Src = Op.getOperand(0);
2360 if (Src.getValueType() == MVT::f32)
2361 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
2362
2363 SDOperand Tmp;
2364 switch (Op.getValueType()) {
2365 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2366 case MVT::i32:
2367 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
2368 break;
2369 case MVT::i64:
2370 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
2371 break;
2372 }
2373
2374 // Convert the FP value to an int value through memory.
Chris Lattner1de7c1d2007-10-15 20:14:52 +00002375 SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64);
2376
2377 // Emit a store to the stack slot.
2378 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0);
2379
2380 // Result is a load from the stack slot. If loading 4 bytes, make sure to
2381 // add in a bias.
Chris Lattner1a635d62006-04-14 06:01:58 +00002382 if (Op.getValueType() == MVT::i32)
Chris Lattner1de7c1d2007-10-15 20:14:52 +00002383 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr,
2384 DAG.getConstant(4, FIPtr.getValueType()));
2385 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0);
Chris Lattner1a635d62006-04-14 06:01:58 +00002386}
2387
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002388SDOperand PPCTargetLowering::LowerFP_ROUND_INREG(SDOperand Op,
2389 SelectionDAG &DAG) {
Dale Johannesen6eaeff22007-10-10 01:01:31 +00002390 assert(Op.getValueType() == MVT::ppcf128);
2391 SDNode *Node = Op.Val;
2392 assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
Chris Lattner26cb2862007-10-19 04:08:28 +00002393 assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR);
Dale Johannesen6eaeff22007-10-10 01:01:31 +00002394 SDOperand Lo = Node->getOperand(0).Val->getOperand(0);
2395 SDOperand Hi = Node->getOperand(0).Val->getOperand(1);
2396
2397 // This sequence changes FPSCR to do round-to-zero, adds the two halves
2398 // of the long double, and puts FPSCR back the way it was. We do not
2399 // actually model FPSCR.
2400 std::vector<MVT::ValueType> NodeTys;
2401 SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg;
2402
2403 NodeTys.push_back(MVT::f64); // Return register
2404 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
2405 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2406 MFFSreg = Result.getValue(0);
2407 InFlag = Result.getValue(1);
2408
2409 NodeTys.clear();
2410 NodeTys.push_back(MVT::Flag); // Returns a flag
2411 Ops[0] = DAG.getConstant(31, MVT::i32);
2412 Ops[1] = InFlag;
2413 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2);
2414 InFlag = Result.getValue(0);
2415
2416 NodeTys.clear();
2417 NodeTys.push_back(MVT::Flag); // Returns a flag
2418 Ops[0] = DAG.getConstant(30, MVT::i32);
2419 Ops[1] = InFlag;
2420 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2);
2421 InFlag = Result.getValue(0);
2422
2423 NodeTys.clear();
2424 NodeTys.push_back(MVT::f64); // result of add
2425 NodeTys.push_back(MVT::Flag); // Returns a flag
2426 Ops[0] = Lo;
2427 Ops[1] = Hi;
2428 Ops[2] = InFlag;
2429 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3);
2430 FPreg = Result.getValue(0);
2431 InFlag = Result.getValue(1);
2432
2433 NodeTys.clear();
2434 NodeTys.push_back(MVT::f64);
2435 Ops[0] = DAG.getConstant(1, MVT::i32);
2436 Ops[1] = MFFSreg;
2437 Ops[2] = FPreg;
2438 Ops[3] = InFlag;
2439 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4);
2440 FPreg = Result.getValue(0);
2441
2442 // We know the low half is about to be thrown away, so just use something
2443 // convenient.
2444 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg);
2445}
2446
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002447SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
Dan Gohman034f60e2008-03-11 01:59:03 +00002448 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
2449 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
2450 return SDOperand();
2451
Chris Lattner1a635d62006-04-14 06:01:58 +00002452 if (Op.getOperand(0).getValueType() == MVT::i64) {
2453 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
2454 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
2455 if (Op.getValueType() == MVT::f32)
Chris Lattner0bd48932008-01-17 07:00:52 +00002456 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
Chris Lattner1a635d62006-04-14 06:01:58 +00002457 return FP;
2458 }
2459
2460 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2461 "Unhandled SINT_TO_FP type in custom expander!");
2462 // Since we only generate this in 64-bit mode, we can take advantage of
2463 // 64-bit registers. In particular, sign extend the input value into the
2464 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2465 // then lfd it and fcfid it.
2466 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2467 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
Chris Lattner0d72a202006-07-28 16:45:47 +00002468 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2469 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
Chris Lattner1a635d62006-04-14 06:01:58 +00002470
2471 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
2472 Op.getOperand(0));
2473
2474 // STD the extended value into the stack slot.
Dan Gohman3069b872008-02-07 18:41:25 +00002475 MemOperand MO(PseudoSourceValue::getFixedStack(),
Dan Gohman69de1932008-02-06 22:27:42 +00002476 MemOperand::MOStore, FrameIdx, 8, 8);
Chris Lattner1a635d62006-04-14 06:01:58 +00002477 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
2478 DAG.getEntryNode(), Ext64, FIdx,
Dan Gohman69de1932008-02-06 22:27:42 +00002479 DAG.getMemOperand(MO));
Chris Lattner1a635d62006-04-14 06:01:58 +00002480 // Load the value as a double.
Evan Cheng466685d2006-10-09 20:57:25 +00002481 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
Chris Lattner1a635d62006-04-14 06:01:58 +00002482
2483 // FCFID it and return it.
2484 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
2485 if (Op.getValueType() == MVT::f32)
Chris Lattner0bd48932008-01-17 07:00:52 +00002486 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
Chris Lattner1a635d62006-04-14 06:01:58 +00002487 return FP;
2488}
2489
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002490SDOperand PPCTargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
Dale Johannesen5c5eb802008-01-18 19:55:37 +00002491 /*
2492 The rounding mode is in bits 30:31 of FPSR, and has the following
2493 settings:
2494 00 Round to nearest
2495 01 Round to 0
2496 10 Round to +inf
2497 11 Round to -inf
2498
2499 FLT_ROUNDS, on the other hand, expects the following:
2500 -1 Undefined
2501 0 Round to 0
2502 1 Round to nearest
2503 2 Round to +inf
2504 3 Round to -inf
2505
2506 To perform the conversion, we do:
2507 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
2508 */
2509
2510 MachineFunction &MF = DAG.getMachineFunction();
2511 MVT::ValueType VT = Op.getValueType();
2512 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2513 std::vector<MVT::ValueType> NodeTys;
2514 SDOperand MFFSreg, InFlag;
2515
2516 // Save FP Control Word to register
2517 NodeTys.push_back(MVT::f64); // return register
2518 NodeTys.push_back(MVT::Flag); // unused in this context
2519 SDOperand Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2520
2521 // Save FP register to stack slot
2522 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
2523 SDOperand StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
2524 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Chain,
2525 StackSlot, NULL, 0);
2526
2527 // Load FP Control Word from low 32 bits of stack slot.
2528 SDOperand Four = DAG.getConstant(4, PtrVT);
2529 SDOperand Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four);
2530 SDOperand CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0);
2531
2532 // Transform as necessary
2533 SDOperand CWD1 =
2534 DAG.getNode(ISD::AND, MVT::i32,
2535 CWD, DAG.getConstant(3, MVT::i32));
2536 SDOperand CWD2 =
2537 DAG.getNode(ISD::SRL, MVT::i32,
2538 DAG.getNode(ISD::AND, MVT::i32,
2539 DAG.getNode(ISD::XOR, MVT::i32,
2540 CWD, DAG.getConstant(3, MVT::i32)),
2541 DAG.getConstant(3, MVT::i32)),
2542 DAG.getConstant(1, MVT::i8));
2543
2544 SDOperand RetVal =
2545 DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2);
2546
2547 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ?
2548 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
2549}
2550
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002551SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
Dan Gohman9ed06db2008-03-07 20:36:53 +00002552 MVT::ValueType VT = Op.getValueType();
2553 unsigned BitWidth = MVT::getSizeInBits(VT);
2554 assert(Op.getNumOperands() == 3 &&
2555 VT == Op.getOperand(1).getValueType() &&
2556 "Unexpected SHL!");
Chris Lattner1a635d62006-04-14 06:01:58 +00002557
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002558 // Expand into a bunch of logical ops. Note that these ops
Chris Lattner1a635d62006-04-14 06:01:58 +00002559 // depend on the PPC behavior for oversized shift amounts.
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002560 SDOperand Lo = Op.getOperand(0);
2561 SDOperand Hi = Op.getOperand(1);
2562 SDOperand Amt = Op.getOperand(2);
Dan Gohman9ed06db2008-03-07 20:36:53 +00002563 MVT::ValueType AmtVT = Amt.getValueType();
Chris Lattner1a635d62006-04-14 06:01:58 +00002564
Dan Gohman9ed06db2008-03-07 20:36:53 +00002565 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
2566 DAG.getConstant(BitWidth, AmtVT), Amt);
2567 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt);
2568 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1);
2569 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
2570 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
2571 DAG.getConstant(-BitWidth, AmtVT));
2572 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5);
2573 SDOperand OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
2574 SDOperand OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt);
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002575 SDOperand OutOps[] = { OutLo, OutHi };
Dan Gohman9ed06db2008-03-07 20:36:53 +00002576 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002577 OutOps, 2);
Chris Lattner1a635d62006-04-14 06:01:58 +00002578}
2579
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002580SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
Dan Gohman9ed06db2008-03-07 20:36:53 +00002581 MVT::ValueType VT = Op.getValueType();
2582 unsigned BitWidth = MVT::getSizeInBits(VT);
2583 assert(Op.getNumOperands() == 3 &&
2584 VT == Op.getOperand(1).getValueType() &&
2585 "Unexpected SRL!");
Chris Lattner1a635d62006-04-14 06:01:58 +00002586
Dan Gohman9ed06db2008-03-07 20:36:53 +00002587 // Expand into a bunch of logical ops. Note that these ops
Chris Lattner1a635d62006-04-14 06:01:58 +00002588 // depend on the PPC behavior for oversized shift amounts.
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002589 SDOperand Lo = Op.getOperand(0);
2590 SDOperand Hi = Op.getOperand(1);
2591 SDOperand Amt = Op.getOperand(2);
Dan Gohman9ed06db2008-03-07 20:36:53 +00002592 MVT::ValueType AmtVT = Amt.getValueType();
Chris Lattner1a635d62006-04-14 06:01:58 +00002593
Dan Gohman9ed06db2008-03-07 20:36:53 +00002594 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
2595 DAG.getConstant(BitWidth, AmtVT), Amt);
2596 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
2597 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
2598 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
2599 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
2600 DAG.getConstant(-BitWidth, AmtVT));
2601 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5);
2602 SDOperand OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
2603 SDOperand OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt);
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002604 SDOperand OutOps[] = { OutLo, OutHi };
Dan Gohman9ed06db2008-03-07 20:36:53 +00002605 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002606 OutOps, 2);
Chris Lattner1a635d62006-04-14 06:01:58 +00002607}
2608
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002609SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
Dan Gohman9ed06db2008-03-07 20:36:53 +00002610 MVT::ValueType VT = Op.getValueType();
2611 unsigned BitWidth = MVT::getSizeInBits(VT);
2612 assert(Op.getNumOperands() == 3 &&
2613 VT == Op.getOperand(1).getValueType() &&
2614 "Unexpected SRA!");
Chris Lattner1a635d62006-04-14 06:01:58 +00002615
Dan Gohman9ed06db2008-03-07 20:36:53 +00002616 // Expand into a bunch of logical ops, followed by a select_cc.
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002617 SDOperand Lo = Op.getOperand(0);
2618 SDOperand Hi = Op.getOperand(1);
2619 SDOperand Amt = Op.getOperand(2);
Dan Gohman9ed06db2008-03-07 20:36:53 +00002620 MVT::ValueType AmtVT = Amt.getValueType();
Chris Lattner1a635d62006-04-14 06:01:58 +00002621
Dan Gohman9ed06db2008-03-07 20:36:53 +00002622 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
2623 DAG.getConstant(BitWidth, AmtVT), Amt);
2624 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
2625 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
2626 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
2627 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
2628 DAG.getConstant(-BitWidth, AmtVT));
2629 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5);
2630 SDOperand OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt);
2631 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT),
Chris Lattner1a635d62006-04-14 06:01:58 +00002632 Tmp4, Tmp6, ISD::SETLE);
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002633 SDOperand OutOps[] = { OutLo, OutHi };
Dan Gohman9ed06db2008-03-07 20:36:53 +00002634 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00002635 OutOps, 2);
Chris Lattner1a635d62006-04-14 06:01:58 +00002636}
2637
2638//===----------------------------------------------------------------------===//
2639// Vector related lowering.
2640//
2641
Chris Lattnerac225ca2006-04-12 19:07:14 +00002642// If this is a vector of constants or undefs, get the bits. A bit in
2643// UndefBits is set if the corresponding element of the vector is an
2644// ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2645// zero. Return true if this is not an array of constants, false if it is.
2646//
Chris Lattnerac225ca2006-04-12 19:07:14 +00002647static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
2648 uint64_t UndefBits[2]) {
2649 // Start with zero'd results.
2650 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
2651
2652 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
2653 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2654 SDOperand OpVal = BV->getOperand(i);
2655
2656 unsigned PartNo = i >= e/2; // In the upper 128 bits?
Chris Lattnerb17f1672006-04-16 01:01:29 +00002657 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
Chris Lattnerac225ca2006-04-12 19:07:14 +00002658
2659 uint64_t EltBits = 0;
2660 if (OpVal.getOpcode() == ISD::UNDEF) {
2661 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
2662 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
2663 continue;
2664 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2665 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
2666 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2667 assert(CN->getValueType(0) == MVT::f32 &&
2668 "Only one legal FP vector type!");
Dale Johanneseneaf08942007-08-31 04:03:46 +00002669 EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
Chris Lattnerac225ca2006-04-12 19:07:14 +00002670 } else {
2671 // Nonconstant element.
2672 return true;
2673 }
2674
2675 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
2676 }
2677
2678 //printf("%llx %llx %llx %llx\n",
2679 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
2680 return false;
2681}
Chris Lattneref819f82006-03-20 06:33:01 +00002682
Chris Lattnerb17f1672006-04-16 01:01:29 +00002683// If this is a splat (repetition) of a value across the whole vector, return
2684// the smallest size that splats it. For example, "0x01010101010101..." is a
2685// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2686// SplatSize = 1 byte.
2687static bool isConstantSplat(const uint64_t Bits128[2],
2688 const uint64_t Undef128[2],
2689 unsigned &SplatBits, unsigned &SplatUndef,
2690 unsigned &SplatSize) {
2691
2692 // Don't let undefs prevent splats from matching. See if the top 64-bits are
2693 // the same as the lower 64-bits, ignoring undefs.
2694 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
2695 return false; // Can't be a splat if two pieces don't match.
2696
2697 uint64_t Bits64 = Bits128[0] | Bits128[1];
2698 uint64_t Undef64 = Undef128[0] & Undef128[1];
2699
2700 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
2701 // undefs.
2702 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
2703 return false; // Can't be a splat if two pieces don't match.
2704
2705 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
2706 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
2707
2708 // If the top 16-bits are different than the lower 16-bits, ignoring
2709 // undefs, we have an i32 splat.
2710 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
2711 SplatBits = Bits32;
2712 SplatUndef = Undef32;
2713 SplatSize = 4;
2714 return true;
2715 }
2716
2717 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
2718 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
2719
2720 // If the top 8-bits are different than the lower 8-bits, ignoring
2721 // undefs, we have an i16 splat.
2722 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
2723 SplatBits = Bits16;
2724 SplatUndef = Undef16;
2725 SplatSize = 2;
2726 return true;
2727 }
2728
2729 // Otherwise, we have an 8-bit splat.
2730 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
2731 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
2732 SplatSize = 1;
2733 return true;
2734}
2735
Chris Lattner4a998b92006-04-17 06:00:21 +00002736/// BuildSplatI - Build a canonical splati of Val with an element size of
2737/// SplatSize. Cast the result to VT.
2738static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
2739 SelectionDAG &DAG) {
2740 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
Chris Lattner70fa4932006-12-01 01:45:39 +00002741
Chris Lattner4a998b92006-04-17 06:00:21 +00002742 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
2743 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
2744 };
Chris Lattner70fa4932006-12-01 01:45:39 +00002745
2746 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
2747
2748 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
2749 if (Val == -1)
2750 SplatSize = 1;
2751
Chris Lattner4a998b92006-04-17 06:00:21 +00002752 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
2753
2754 // Build a canonical splat for this value.
Dan Gohman51eaa862007-06-14 22:58:02 +00002755 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT));
Chris Lattnere2199452006-08-11 17:38:39 +00002756 SmallVector<SDOperand, 8> Ops;
2757 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
2758 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
2759 &Ops[0], Ops.size());
Chris Lattner70fa4932006-12-01 01:45:39 +00002760 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
Chris Lattner4a998b92006-04-17 06:00:21 +00002761}
2762
Chris Lattnere7c768e2006-04-18 03:24:30 +00002763/// BuildIntrinsicOp - Return a binary operator intrinsic node with the
Chris Lattner6876e662006-04-17 06:58:41 +00002764/// specified intrinsic ID.
Chris Lattnere7c768e2006-04-18 03:24:30 +00002765static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
2766 SelectionDAG &DAG,
2767 MVT::ValueType DestVT = MVT::Other) {
2768 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
2769 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
Chris Lattner6876e662006-04-17 06:58:41 +00002770 DAG.getConstant(IID, MVT::i32), LHS, RHS);
2771}
2772
Chris Lattnere7c768e2006-04-18 03:24:30 +00002773/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
2774/// specified intrinsic ID.
2775static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
2776 SDOperand Op2, SelectionDAG &DAG,
2777 MVT::ValueType DestVT = MVT::Other) {
2778 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
2779 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2780 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
2781}
2782
2783
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002784/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
2785/// amount. The result has the specified value type.
2786static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
2787 MVT::ValueType VT, SelectionDAG &DAG) {
2788 // Force LHS/RHS to be the right type.
2789 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
2790 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
2791
Chris Lattnere2199452006-08-11 17:38:39 +00002792 SDOperand Ops[16];
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002793 for (unsigned i = 0; i != 16; ++i)
Chris Lattnere2199452006-08-11 17:38:39 +00002794 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002795 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
Chris Lattnere2199452006-08-11 17:38:39 +00002796 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002797 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
2798}
2799
Chris Lattnerf1b47082006-04-14 05:19:18 +00002800// If this is a case we can't handle, return null and let the default
2801// expansion code take care of it. If we CAN select this case, and if it
2802// selects to a single instruction, return Op. Otherwise, if we can codegen
2803// this case more efficiently than a constant pool load, lower it to the
2804// sequence of ops that should be used.
Dale Johannesen5b3b6952008-03-04 23:17:14 +00002805SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op,
2806 SelectionDAG &DAG) {
Chris Lattnerf1b47082006-04-14 05:19:18 +00002807 // If this is a vector of constants or undefs, get the bits. A bit in
2808 // UndefBits is set if the corresponding element of the vector is an
2809 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2810 // zero.
2811 uint64_t VectorBits[2];
2812 uint64_t UndefBits[2];
2813 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
2814 return SDOperand(); // Not a constant vector.
2815
Chris Lattnerb17f1672006-04-16 01:01:29 +00002816 // If this is a splat (repetition) of a value across the whole vector, return
2817 // the smallest size that splats it. For example, "0x01010101010101..." is a
2818 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2819 // SplatSize = 1 byte.
2820 unsigned SplatBits, SplatUndef, SplatSize;
2821 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
2822 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
2823
2824 // First, handle single instruction cases.
2825
2826 // All zeros?
2827 if (SplatBits == 0) {
2828 // Canonicalize all zero vectors to be v4i32.
2829 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
2830 SDOperand Z = DAG.getConstant(0, MVT::i32);
2831 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
2832 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
2833 }
2834 return Op;
Chris Lattnerf1b47082006-04-14 05:19:18 +00002835 }
Chris Lattnerb17f1672006-04-16 01:01:29 +00002836
2837 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
2838 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
Chris Lattner4a998b92006-04-17 06:00:21 +00002839 if (SextVal >= -16 && SextVal <= 15)
2840 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
Chris Lattnerb17f1672006-04-16 01:01:29 +00002841
Chris Lattnerdbce85d2006-04-17 18:09:22 +00002842
2843 // Two instruction sequences.
2844
Chris Lattner4a998b92006-04-17 06:00:21 +00002845 // If this value is in the range [-32,30] and is even, use:
2846 // tmp = VSPLTI[bhw], result = add tmp, tmp
2847 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
2848 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
2849 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
2850 }
Chris Lattner6876e662006-04-17 06:58:41 +00002851
2852 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
2853 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
2854 // for fneg/fabs.
2855 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
2856 // Make -1 and vspltisw -1:
2857 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
2858
2859 // Make the VSLW intrinsic, computing 0x8000_0000.
Chris Lattnere7c768e2006-04-18 03:24:30 +00002860 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
2861 OnesV, DAG);
Chris Lattner6876e662006-04-17 06:58:41 +00002862
2863 // xor by OnesV to invert it.
2864 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
2865 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2866 }
2867
2868 // Check to see if this is a wide variety of vsplti*, binop self cases.
2869 unsigned SplatBitSize = SplatSize*8;
Lauro Ramos Venancio1baa1972007-03-27 16:33:08 +00002870 static const signed char SplatCsts[] = {
Chris Lattner6876e662006-04-17 06:58:41 +00002871 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
Chris Lattnerdbce85d2006-04-17 18:09:22 +00002872 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
Chris Lattner6876e662006-04-17 06:58:41 +00002873 };
Chris Lattner15eb3292006-11-29 19:58:49 +00002874
Owen Anderson718cb662007-09-07 04:06:50 +00002875 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
Chris Lattner6876e662006-04-17 06:58:41 +00002876 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
2877 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
2878 int i = SplatCsts[idx];
2879
2880 // Figure out what shift amount will be used by altivec if shifted by i in
2881 // this splat size.
2882 unsigned TypeShiftAmt = i & (SplatBitSize-1);
2883
2884 // vsplti + shl self.
2885 if (SextVal == (i << (int)TypeShiftAmt)) {
Chris Lattner15eb3292006-11-29 19:58:49 +00002886 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
Chris Lattner6876e662006-04-17 06:58:41 +00002887 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2888 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
2889 Intrinsic::ppc_altivec_vslw
2890 };
Chris Lattner15eb3292006-11-29 19:58:49 +00002891 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2892 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
Chris Lattner6876e662006-04-17 06:58:41 +00002893 }
2894
2895 // vsplti + srl self.
2896 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
Chris Lattner15eb3292006-11-29 19:58:49 +00002897 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
Chris Lattner6876e662006-04-17 06:58:41 +00002898 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2899 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
2900 Intrinsic::ppc_altivec_vsrw
2901 };
Chris Lattner15eb3292006-11-29 19:58:49 +00002902 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2903 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
Chris Lattner6876e662006-04-17 06:58:41 +00002904 }
2905
2906 // vsplti + sra self.
2907 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
Chris Lattner15eb3292006-11-29 19:58:49 +00002908 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
Chris Lattner6876e662006-04-17 06:58:41 +00002909 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2910 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
2911 Intrinsic::ppc_altivec_vsraw
2912 };
Chris Lattner15eb3292006-11-29 19:58:49 +00002913 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2914 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
Chris Lattner6876e662006-04-17 06:58:41 +00002915 }
2916
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002917 // vsplti + rol self.
2918 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
2919 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
Chris Lattner15eb3292006-11-29 19:58:49 +00002920 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002921 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2922 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
2923 Intrinsic::ppc_altivec_vrlw
2924 };
Chris Lattner15eb3292006-11-29 19:58:49 +00002925 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2926 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002927 }
2928
2929 // t = vsplti c, result = vsldoi t, t, 1
2930 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
2931 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2932 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
2933 }
2934 // t = vsplti c, result = vsldoi t, t, 2
2935 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
2936 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2937 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
2938 }
2939 // t = vsplti c, result = vsldoi t, t, 3
2940 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
2941 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2942 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
2943 }
Chris Lattner6876e662006-04-17 06:58:41 +00002944 }
2945
Chris Lattner6876e662006-04-17 06:58:41 +00002946 // Three instruction sequences.
2947
Chris Lattnerdbce85d2006-04-17 18:09:22 +00002948 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
2949 if (SextVal >= 0 && SextVal <= 31) {
Chris Lattner15eb3292006-11-29 19:58:49 +00002950 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
2951 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
Dale Johannesen296c1762007-10-14 01:58:32 +00002952 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS);
Chris Lattner15eb3292006-11-29 19:58:49 +00002953 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
Chris Lattnerdbce85d2006-04-17 18:09:22 +00002954 }
2955 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
2956 if (SextVal >= -31 && SextVal <= 0) {
Chris Lattner15eb3292006-11-29 19:58:49 +00002957 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
2958 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
Dale Johannesen296c1762007-10-14 01:58:32 +00002959 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
Chris Lattner15eb3292006-11-29 19:58:49 +00002960 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
Chris Lattnerf1b47082006-04-14 05:19:18 +00002961 }
2962 }
Chris Lattnerb17f1672006-04-16 01:01:29 +00002963
Chris Lattnerf1b47082006-04-14 05:19:18 +00002964 return SDOperand();
2965}
2966
Chris Lattner59138102006-04-17 05:28:54 +00002967/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2968/// the specified operations to build the shuffle.
2969static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
2970 SDOperand RHS, SelectionDAG &DAG) {
2971 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2972 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2973 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2974
2975 enum {
Chris Lattner00402c72006-05-16 04:20:24 +00002976 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
Chris Lattner59138102006-04-17 05:28:54 +00002977 OP_VMRGHW,
2978 OP_VMRGLW,
2979 OP_VSPLTISW0,
2980 OP_VSPLTISW1,
2981 OP_VSPLTISW2,
2982 OP_VSPLTISW3,
2983 OP_VSLDOI4,
2984 OP_VSLDOI8,
Chris Lattnerd74ea2b2006-05-24 17:04:05 +00002985 OP_VSLDOI12
Chris Lattner59138102006-04-17 05:28:54 +00002986 };
2987
2988 if (OpNum == OP_COPY) {
2989 if (LHSID == (1*9+2)*9+3) return LHS;
2990 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2991 return RHS;
2992 }
2993
Chris Lattnerbdd558c2006-04-17 17:55:10 +00002994 SDOperand OpLHS, OpRHS;
2995 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
2996 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
2997
Chris Lattner59138102006-04-17 05:28:54 +00002998 unsigned ShufIdxs[16];
2999 switch (OpNum) {
3000 default: assert(0 && "Unknown i32 permute!");
3001 case OP_VMRGHW:
3002 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
3003 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
3004 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
3005 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
3006 break;
3007 case OP_VMRGLW:
3008 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
3009 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
3010 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
3011 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
3012 break;
3013 case OP_VSPLTISW0:
3014 for (unsigned i = 0; i != 16; ++i)
3015 ShufIdxs[i] = (i&3)+0;
3016 break;
3017 case OP_VSPLTISW1:
3018 for (unsigned i = 0; i != 16; ++i)
3019 ShufIdxs[i] = (i&3)+4;
3020 break;
3021 case OP_VSPLTISW2:
3022 for (unsigned i = 0; i != 16; ++i)
3023 ShufIdxs[i] = (i&3)+8;
3024 break;
3025 case OP_VSPLTISW3:
3026 for (unsigned i = 0; i != 16; ++i)
3027 ShufIdxs[i] = (i&3)+12;
3028 break;
3029 case OP_VSLDOI4:
Chris Lattnerbdd558c2006-04-17 17:55:10 +00003030 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
Chris Lattner59138102006-04-17 05:28:54 +00003031 case OP_VSLDOI8:
Chris Lattnerbdd558c2006-04-17 17:55:10 +00003032 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
Chris Lattner59138102006-04-17 05:28:54 +00003033 case OP_VSLDOI12:
Chris Lattnerbdd558c2006-04-17 17:55:10 +00003034 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
Chris Lattner59138102006-04-17 05:28:54 +00003035 }
Chris Lattnere2199452006-08-11 17:38:39 +00003036 SDOperand Ops[16];
Chris Lattner59138102006-04-17 05:28:54 +00003037 for (unsigned i = 0; i != 16; ++i)
Chris Lattnere2199452006-08-11 17:38:39 +00003038 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
Chris Lattner59138102006-04-17 05:28:54 +00003039
3040 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
Chris Lattnere2199452006-08-11 17:38:39 +00003041 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
Chris Lattner59138102006-04-17 05:28:54 +00003042}
3043
Chris Lattnerf1b47082006-04-14 05:19:18 +00003044/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
3045/// is a shuffle we can handle in a single instruction, return it. Otherwise,
3046/// return the code it can be lowered into. Worst case, it can always be
3047/// lowered into a vperm.
Dale Johannesen5b3b6952008-03-04 23:17:14 +00003048SDOperand PPCTargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op,
3049 SelectionDAG &DAG) {
Chris Lattnerf1b47082006-04-14 05:19:18 +00003050 SDOperand V1 = Op.getOperand(0);
3051 SDOperand V2 = Op.getOperand(1);
3052 SDOperand PermMask = Op.getOperand(2);
3053
3054 // Cases that are handled by instructions that take permute immediates
3055 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
3056 // selected by the instruction selector.
3057 if (V2.getOpcode() == ISD::UNDEF) {
3058 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
3059 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
3060 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
3061 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
3062 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
3063 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
3064 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
3065 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
3066 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
3067 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
3068 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
3069 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
3070 return Op;
3071 }
3072 }
3073
3074 // Altivec has a variety of "shuffle immediates" that take two vector inputs
3075 // and produce a fixed permutation. If any of these match, do not lower to
3076 // VPERM.
3077 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
3078 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
3079 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
3080 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
3081 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
3082 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
3083 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
3084 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
3085 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
3086 return Op;
3087
Chris Lattner59138102006-04-17 05:28:54 +00003088 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
3089 // perfect shuffle table to emit an optimal matching sequence.
3090 unsigned PFIndexes[4];
3091 bool isFourElementShuffle = true;
3092 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
3093 unsigned EltNo = 8; // Start out undef.
3094 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
3095 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
3096 continue; // Undef, ignore it.
3097
3098 unsigned ByteSource =
3099 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
3100 if ((ByteSource & 3) != j) {
3101 isFourElementShuffle = false;
3102 break;
3103 }
3104
3105 if (EltNo == 8) {
3106 EltNo = ByteSource/4;
3107 } else if (EltNo != ByteSource/4) {
3108 isFourElementShuffle = false;
3109 break;
3110 }
3111 }
3112 PFIndexes[i] = EltNo;
3113 }
3114
3115 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
3116 // perfect shuffle vector to determine if it is cost effective to do this as
3117 // discrete instructions, or whether we should use a vperm.
3118 if (isFourElementShuffle) {
3119 // Compute the index in the perfect shuffle table.
3120 unsigned PFTableIndex =
3121 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3122
3123 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3124 unsigned Cost = (PFEntry >> 30);
3125
3126 // Determining when to avoid vperm is tricky. Many things affect the cost
3127 // of vperm, particularly how many times the perm mask needs to be computed.
3128 // For example, if the perm mask can be hoisted out of a loop or is already
3129 // used (perhaps because there are multiple permutes with the same shuffle
3130 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
3131 // the loop requires an extra register.
3132 //
3133 // As a compromise, we only emit discrete instructions if the shuffle can be
3134 // generated in 3 or fewer operations. When we have loop information
3135 // available, if this block is within a loop, we should avoid using vperm
3136 // for 3-operation perms and use a constant pool load instead.
3137 if (Cost < 3)
3138 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
3139 }
Chris Lattnerf1b47082006-04-14 05:19:18 +00003140
3141 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
3142 // vector that will get spilled to the constant pool.
3143 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
3144
3145 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
3146 // that it is in input element units, not in bytes. Convert now.
Dan Gohman51eaa862007-06-14 22:58:02 +00003147 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
Chris Lattnerf1b47082006-04-14 05:19:18 +00003148 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
3149
Chris Lattnere2199452006-08-11 17:38:39 +00003150 SmallVector<SDOperand, 16> ResultMask;
Chris Lattnerf1b47082006-04-14 05:19:18 +00003151 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
Chris Lattner730b4562006-04-15 23:48:05 +00003152 unsigned SrcElt;
3153 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
3154 SrcElt = 0;
3155 else
3156 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
Chris Lattnerf1b47082006-04-14 05:19:18 +00003157
3158 for (unsigned j = 0; j != BytesPerElement; ++j)
3159 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
3160 MVT::i8));
3161 }
3162
Chris Lattnere2199452006-08-11 17:38:39 +00003163 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
3164 &ResultMask[0], ResultMask.size());
Chris Lattnerf1b47082006-04-14 05:19:18 +00003165 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
3166}
3167
Chris Lattner90564f22006-04-18 17:59:36 +00003168/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
3169/// altivec comparison. If it is, return true and fill in Opc/isDot with
3170/// information about the intrinsic.
3171static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
3172 bool &isDot) {
3173 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
3174 CompareOpc = -1;
3175 isDot = false;
3176 switch (IntrinsicID) {
3177 default: return false;
3178 // Comparison predicates.
Chris Lattner1a635d62006-04-14 06:01:58 +00003179 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
3180 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
3181 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
3182 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
3183 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
3184 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
3185 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
3186 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
3187 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
3188 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
3189 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
3190 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
3191 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
3192
3193 // Normal Comparisons.
3194 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
3195 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
3196 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
3197 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
3198 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
3199 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
3200 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
3201 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
3202 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
3203 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
3204 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
3205 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
3206 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
3207 }
Chris Lattner90564f22006-04-18 17:59:36 +00003208 return true;
3209}
3210
3211/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
3212/// lower, do it, otherwise return null.
Dale Johannesen5b3b6952008-03-04 23:17:14 +00003213SDOperand PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op,
3214 SelectionDAG &DAG) {
Chris Lattner90564f22006-04-18 17:59:36 +00003215 // If this is a lowered altivec predicate compare, CompareOpc is set to the
3216 // opcode number of the comparison.
3217 int CompareOpc;
3218 bool isDot;
3219 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
3220 return SDOperand(); // Don't custom lower most intrinsics.
Chris Lattner1a635d62006-04-14 06:01:58 +00003221
Chris Lattner90564f22006-04-18 17:59:36 +00003222 // If this is a non-dot comparison, make the VCMP node and we are done.
Chris Lattner1a635d62006-04-14 06:01:58 +00003223 if (!isDot) {
3224 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
3225 Op.getOperand(1), Op.getOperand(2),
3226 DAG.getConstant(CompareOpc, MVT::i32));
3227 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
3228 }
3229
3230 // Create the PPCISD altivec 'dot' comparison node.
Chris Lattner79e490a2006-08-11 17:18:05 +00003231 SDOperand Ops[] = {
3232 Op.getOperand(2), // LHS
3233 Op.getOperand(3), // RHS
3234 DAG.getConstant(CompareOpc, MVT::i32)
3235 };
Chris Lattner1a635d62006-04-14 06:01:58 +00003236 std::vector<MVT::ValueType> VTs;
Chris Lattner1a635d62006-04-14 06:01:58 +00003237 VTs.push_back(Op.getOperand(2).getValueType());
3238 VTs.push_back(MVT::Flag);
Chris Lattner79e490a2006-08-11 17:18:05 +00003239 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
Chris Lattner1a635d62006-04-14 06:01:58 +00003240
3241 // Now that we have the comparison, emit a copy from the CR to a GPR.
3242 // This is flagged to the above dot comparison.
3243 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
3244 DAG.getRegister(PPC::CR6, MVT::i32),
3245 CompNode.getValue(1));
3246
3247 // Unpack the result based on how the target uses it.
3248 unsigned BitNo; // Bit # of CR6.
3249 bool InvertBit; // Invert result?
3250 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
3251 default: // Can't happen, don't crash on invalid number though.
3252 case 0: // Return the value of the EQ bit of CR6.
3253 BitNo = 0; InvertBit = false;
3254 break;
3255 case 1: // Return the inverted value of the EQ bit of CR6.
3256 BitNo = 0; InvertBit = true;
3257 break;
3258 case 2: // Return the value of the LT bit of CR6.
3259 BitNo = 2; InvertBit = false;
3260 break;
3261 case 3: // Return the inverted value of the LT bit of CR6.
3262 BitNo = 2; InvertBit = true;
3263 break;
3264 }
3265
3266 // Shift the bit into the low position.
3267 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
3268 DAG.getConstant(8-(3-BitNo), MVT::i32));
3269 // Isolate the bit.
3270 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
3271 DAG.getConstant(1, MVT::i32));
3272
3273 // If we are supposed to, toggle the bit.
3274 if (InvertBit)
3275 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
3276 DAG.getConstant(1, MVT::i32));
3277 return Flags;
3278}
3279
Dale Johannesen5b3b6952008-03-04 23:17:14 +00003280SDOperand PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op,
3281 SelectionDAG &DAG) {
Chris Lattner1a635d62006-04-14 06:01:58 +00003282 // Create a stack slot that is 16-byte aligned.
3283 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3284 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
Chris Lattner0d72a202006-07-28 16:45:47 +00003285 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3286 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
Chris Lattner1a635d62006-04-14 06:01:58 +00003287
3288 // Store the input value into Value#0 of the stack slot.
Evan Cheng786225a2006-10-05 23:01:46 +00003289 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
Evan Cheng8b2794a2006-10-13 21:14:26 +00003290 Op.getOperand(0), FIdx, NULL, 0);
Chris Lattner1a635d62006-04-14 06:01:58 +00003291 // Load it out.
Evan Cheng466685d2006-10-09 20:57:25 +00003292 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
Chris Lattner1a635d62006-04-14 06:01:58 +00003293}
3294
Dale Johannesen5b3b6952008-03-04 23:17:14 +00003295SDOperand PPCTargetLowering::LowerMUL(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner72dd9bd2006-04-18 03:43:48 +00003296 if (Op.getValueType() == MVT::v4i32) {
3297 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3298
3299 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
3300 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
3301
3302 SDOperand RHSSwap = // = vrlw RHS, 16
3303 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
3304
3305 // Shrinkify inputs to v8i16.
3306 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
3307 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
3308 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
3309
3310 // Low parts multiplied together, generating 32-bit results (we ignore the
3311 // top parts).
3312 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
3313 LHS, RHS, DAG, MVT::v4i32);
3314
3315 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
3316 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
3317 // Shift the high parts up 16 bits.
3318 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
3319 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
3320 } else if (Op.getValueType() == MVT::v8i16) {
3321 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3322
Chris Lattnercea2aa72006-04-18 04:28:57 +00003323 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
Chris Lattner72dd9bd2006-04-18 03:43:48 +00003324
Chris Lattnercea2aa72006-04-18 04:28:57 +00003325 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
3326 LHS, RHS, Zero, DAG);
Chris Lattner19a81522006-04-18 03:57:35 +00003327 } else if (Op.getValueType() == MVT::v16i8) {
3328 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3329
3330 // Multiply the even 8-bit parts, producing 16-bit sums.
3331 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
3332 LHS, RHS, DAG, MVT::v8i16);
3333 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
3334
3335 // Multiply the odd 8-bit parts, producing 16-bit sums.
3336 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
3337 LHS, RHS, DAG, MVT::v8i16);
3338 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
3339
3340 // Merge the results together.
Chris Lattnere2199452006-08-11 17:38:39 +00003341 SDOperand Ops[16];
Chris Lattner19a81522006-04-18 03:57:35 +00003342 for (unsigned i = 0; i != 8; ++i) {
Chris Lattnere2199452006-08-11 17:38:39 +00003343 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
3344 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
Chris Lattner19a81522006-04-18 03:57:35 +00003345 }
Chris Lattner19a81522006-04-18 03:57:35 +00003346 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
Chris Lattnere2199452006-08-11 17:38:39 +00003347 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
Chris Lattner72dd9bd2006-04-18 03:43:48 +00003348 } else {
3349 assert(0 && "Unknown mul to lower!");
3350 abort();
3351 }
Chris Lattnere7c768e2006-04-18 03:24:30 +00003352}
3353
Chris Lattnere4bc9ea2005-08-26 00:52:45 +00003354/// LowerOperation - Provide custom lowering hooks for some operations.
3355///
Nate Begeman21e463b2005-10-16 05:39:50 +00003356SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
Chris Lattnere4bc9ea2005-08-26 00:52:45 +00003357 switch (Op.getOpcode()) {
3358 default: assert(0 && "Wasn't expecting to be able to lower this!");
Chris Lattner1a635d62006-04-14 06:01:58 +00003359 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3360 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
Lauro Ramos Venancio75ce0102007-07-11 17:19:51 +00003361 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
Nate Begeman37efe672006-04-22 18:53:45 +00003362 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
Chris Lattner1a635d62006-04-14 06:01:58 +00003363 case ISD::SETCC: return LowerSETCC(Op, DAG);
Nicolas Geoffray01119992007-04-03 13:59:52 +00003364 case ISD::VASTART:
3365 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3366 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3367
3368 case ISD::VAARG:
3369 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3370 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3371
Chris Lattneref957102006-06-21 00:34:03 +00003372 case ISD::FORMAL_ARGUMENTS:
Nicolas Geoffray01119992007-04-03 13:59:52 +00003373 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
3374 VarArgsStackOffset, VarArgsNumGPR,
3375 VarArgsNumFPR, PPCSubTarget);
3376
Chris Lattner9f0bc652007-02-25 05:34:32 +00003377 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget);
Chris Lattnerb9a7bea2007-03-06 00:59:59 +00003378 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
Jim Laskeyefc7e522006-12-04 22:04:42 +00003379 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
Chris Lattner9f0bc652007-02-25 05:34:32 +00003380 case ISD::DYNAMIC_STACKALLOC:
3381 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
Chris Lattner7c0d6642005-10-02 06:37:13 +00003382
Chris Lattner1a635d62006-04-14 06:01:58 +00003383 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3384 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
3385 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
Dale Johannesen6eaeff22007-10-10 01:01:31 +00003386 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG);
Dan Gohman1a024862008-01-31 00:41:03 +00003387 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
Chris Lattnerecfe55e2006-03-22 05:30:33 +00003388
Chris Lattner1a635d62006-04-14 06:01:58 +00003389 // Lower 64-bit shifts.
Chris Lattner3fe6c1d2006-09-20 03:47:40 +00003390 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
3391 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
3392 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
Chris Lattnerecfe55e2006-03-22 05:30:33 +00003393
Chris Lattner1a635d62006-04-14 06:01:58 +00003394 // Vector-related lowering.
3395 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3396 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3397 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3398 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
Chris Lattnere7c768e2006-04-18 03:24:30 +00003399 case ISD::MUL: return LowerMUL(Op, DAG);
Nate Begemanbcc5f362007-01-29 22:58:52 +00003400
Chris Lattner3fc027d2007-12-08 06:59:59 +00003401 // Frame & Return address.
3402 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
Nicolas Geoffray43c6e7c2007-03-01 13:11:38 +00003403 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Chris Lattnerbc11c342005-08-31 20:23:54 +00003404 }
Chris Lattnere4bc9ea2005-08-26 00:52:45 +00003405 return SDOperand();
3406}
3407
Chris Lattner1f873002007-11-28 18:44:47 +00003408SDNode *PPCTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
3409 switch (N->getOpcode()) {
3410 default: assert(0 && "Wasn't expecting to be able to lower this!");
3411 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(SDOperand(N, 0), DAG).Val;
3412 }
3413}
3414
3415
Chris Lattner1a635d62006-04-14 06:01:58 +00003416//===----------------------------------------------------------------------===//
3417// Other Lowering Code
3418//===----------------------------------------------------------------------===//
3419
Chris Lattner8a2d3ca2005-08-26 21:23:58 +00003420MachineBasicBlock *
Evan Chengff9b3732008-01-30 18:18:23 +00003421PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3422 MachineBasicBlock *BB) {
Evan Chengc0f64ff2006-11-27 23:37:22 +00003423 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
Chris Lattnerc08f9022006-06-27 00:04:13 +00003424 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
3425 MI->getOpcode() == PPC::SELECT_CC_I8 ||
Chris Lattner919c0322005-10-01 01:35:02 +00003426 MI->getOpcode() == PPC::SELECT_CC_F4 ||
Chris Lattner710ff322006-04-08 22:45:08 +00003427 MI->getOpcode() == PPC::SELECT_CC_F8 ||
3428 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
Chris Lattner8a2d3ca2005-08-26 21:23:58 +00003429 "Unexpected instr type to insert");
3430
3431 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
3432 // control-flow pattern. The incoming instruction knows the destination vreg
3433 // to set, the condition code register to branch on, the true/false values to
3434 // select between, and a branch opcode to use.
3435 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3436 ilist<MachineBasicBlock>::iterator It = BB;
3437 ++It;
3438
3439 // thisMBB:
3440 // ...
3441 // TrueVal = ...
3442 // cmpTY ccX, r1, r2
3443 // bCC copy1MBB
3444 // fallthrough --> copy0MBB
3445 MachineBasicBlock *thisMBB = BB;
3446 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
3447 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
Chris Lattnerdf4ed632006-11-17 22:10:59 +00003448 unsigned SelectPred = MI->getOperand(4).getImm();
Evan Chengc0f64ff2006-11-27 23:37:22 +00003449 BuildMI(BB, TII->get(PPC::BCC))
Chris Lattner18258c62006-11-17 22:37:34 +00003450 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
Chris Lattner8a2d3ca2005-08-26 21:23:58 +00003451 MachineFunction *F = BB->getParent();
3452 F->getBasicBlockList().insert(It, copy0MBB);
3453 F->getBasicBlockList().insert(It, sinkMBB);
Nate Begemanf15485a2006-03-27 01:32:24 +00003454 // Update machine-CFG edges by first adding all successors of the current
3455 // block to the new block which will contain the Phi node for the select.
3456 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
3457 e = BB->succ_end(); i != e; ++i)
3458 sinkMBB->addSuccessor(*i);
3459 // Next, remove all successors of the current block, and add the true
3460 // and fallthrough blocks as its successors.
3461 while(!BB->succ_empty())
3462 BB->removeSuccessor(BB->succ_begin());
Chris Lattner8a2d3ca2005-08-26 21:23:58 +00003463 BB->addSuccessor(copy0MBB);
3464 BB->addSuccessor(sinkMBB);
3465
3466 // copy0MBB:
3467 // %FalseValue = ...
3468 // # fallthrough to sinkMBB
3469 BB = copy0MBB;
3470
3471 // Update machine-CFG edges
3472 BB->addSuccessor(sinkMBB);
3473
3474 // sinkMBB:
3475 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3476 // ...
3477 BB = sinkMBB;
Evan Chengc0f64ff2006-11-27 23:37:22 +00003478 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
Chris Lattner8a2d3ca2005-08-26 21:23:58 +00003479 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
3480 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3481
3482 delete MI; // The pseudo instruction is gone now.
3483 return BB;
3484}
3485
Chris Lattner1a635d62006-04-14 06:01:58 +00003486//===----------------------------------------------------------------------===//
3487// Target Optimization Hooks
3488//===----------------------------------------------------------------------===//
3489
Chris Lattner8c13d0a2006-03-01 04:57:39 +00003490SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
3491 DAGCombinerInfo &DCI) const {
3492 TargetMachine &TM = getTargetMachine();
3493 SelectionDAG &DAG = DCI.DAG;
3494 switch (N->getOpcode()) {
3495 default: break;
Chris Lattnercf9d0ac2006-09-19 05:22:59 +00003496 case PPCISD::SHL:
3497 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3498 if (C->getValue() == 0) // 0 << V -> 0.
3499 return N->getOperand(0);
3500 }
3501 break;
3502 case PPCISD::SRL:
3503 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3504 if (C->getValue() == 0) // 0 >>u V -> 0.
3505 return N->getOperand(0);
3506 }
3507 break;
3508 case PPCISD::SRA:
3509 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3510 if (C->getValue() == 0 || // 0 >>s V -> 0.
3511 C->isAllOnesValue()) // -1 >>s V -> -1.
3512 return N->getOperand(0);
3513 }
3514 break;
3515
Chris Lattner8c13d0a2006-03-01 04:57:39 +00003516 case ISD::SINT_TO_FP:
Chris Lattnera7a58542006-06-16 17:34:12 +00003517 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
Chris Lattnerecfe55e2006-03-22 05:30:33 +00003518 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
3519 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
3520 // We allow the src/dst to be either f32/f64, but the intermediate
3521 // type must be i64.
Dale Johannesen79217062007-10-23 23:20:14 +00003522 if (N->getOperand(0).getValueType() == MVT::i64 &&
3523 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
Chris Lattnerecfe55e2006-03-22 05:30:33 +00003524 SDOperand Val = N->getOperand(0).getOperand(0);
3525 if (Val.getValueType() == MVT::f32) {
3526 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3527 DCI.AddToWorklist(Val.Val);
3528 }
3529
3530 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
Chris Lattner8c13d0a2006-03-01 04:57:39 +00003531 DCI.AddToWorklist(Val.Val);
Chris Lattnerecfe55e2006-03-22 05:30:33 +00003532 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
Chris Lattner8c13d0a2006-03-01 04:57:39 +00003533 DCI.AddToWorklist(Val.Val);
Chris Lattnerecfe55e2006-03-22 05:30:33 +00003534 if (N->getValueType(0) == MVT::f32) {
Chris Lattner0bd48932008-01-17 07:00:52 +00003535 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val,
3536 DAG.getIntPtrConstant(0));
Chris Lattnerecfe55e2006-03-22 05:30:33 +00003537 DCI.AddToWorklist(Val.Val);
3538 }
3539 return Val;
3540 } else if (N->getOperand(0).getValueType() == MVT::i32) {
3541 // If the intermediate type is i32, we can avoid the load/store here
3542 // too.
Chris Lattner8c13d0a2006-03-01 04:57:39 +00003543 }
Chris Lattner8c13d0a2006-03-01 04:57:39 +00003544 }
3545 }
3546 break;
Chris Lattner51269842006-03-01 05:50:56 +00003547 case ISD::STORE:
3548 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
3549 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
Chris Lattnera7a02fb2008-01-18 16:54:56 +00003550 !cast<StoreSDNode>(N)->isTruncatingStore() &&
Chris Lattner51269842006-03-01 05:50:56 +00003551 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
Dale Johannesen79217062007-10-23 23:20:14 +00003552 N->getOperand(1).getValueType() == MVT::i32 &&
3553 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
Chris Lattner51269842006-03-01 05:50:56 +00003554 SDOperand Val = N->getOperand(1).getOperand(0);
3555 if (Val.getValueType() == MVT::f32) {
3556 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3557 DCI.AddToWorklist(Val.Val);
3558 }
3559 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
3560 DCI.AddToWorklist(Val.Val);
3561
3562 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
3563 N->getOperand(2), N->getOperand(3));
3564 DCI.AddToWorklist(Val.Val);
3565 return Val;
3566 }
Chris Lattnerd9989382006-07-10 20:56:58 +00003567
3568 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
3569 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
3570 N->getOperand(1).Val->hasOneUse() &&
3571 (N->getOperand(1).getValueType() == MVT::i32 ||
3572 N->getOperand(1).getValueType() == MVT::i16)) {
3573 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
3574 // Do an any-extend to 32-bits if this is a half-word input.
3575 if (BSwapOp.getValueType() == MVT::i16)
3576 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
3577
3578 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
3579 N->getOperand(2), N->getOperand(3),
3580 DAG.getValueType(N->getOperand(1).getValueType()));
3581 }
3582 break;
3583 case ISD::BSWAP:
3584 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
Evan Cheng466685d2006-10-09 20:57:25 +00003585 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
Chris Lattnerd9989382006-07-10 20:56:58 +00003586 N->getOperand(0).hasOneUse() &&
3587 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
3588 SDOperand Load = N->getOperand(0);
Evan Cheng466685d2006-10-09 20:57:25 +00003589 LoadSDNode *LD = cast<LoadSDNode>(Load);
Chris Lattnerd9989382006-07-10 20:56:58 +00003590 // Create the byte-swapping load.
3591 std::vector<MVT::ValueType> VTs;
3592 VTs.push_back(MVT::i32);
3593 VTs.push_back(MVT::Other);
Dan Gohman69de1932008-02-06 22:27:42 +00003594 SDOperand MO = DAG.getMemOperand(LD->getMemOperand());
Chris Lattner79e490a2006-08-11 17:18:05 +00003595 SDOperand Ops[] = {
Evan Cheng466685d2006-10-09 20:57:25 +00003596 LD->getChain(), // Chain
3597 LD->getBasePtr(), // Ptr
Dan Gohman69de1932008-02-06 22:27:42 +00003598 MO, // MemOperand
Chris Lattner79e490a2006-08-11 17:18:05 +00003599 DAG.getValueType(N->getValueType(0)) // VT
3600 };
3601 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
Chris Lattnerd9989382006-07-10 20:56:58 +00003602
3603 // If this is an i16 load, insert the truncate.
3604 SDOperand ResVal = BSLoad;
3605 if (N->getValueType(0) == MVT::i16)
3606 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
3607
3608 // First, combine the bswap away. This makes the value produced by the
3609 // load dead.
3610 DCI.CombineTo(N, ResVal);
3611
3612 // Next, combine the load away, we give it a bogus result value but a real
3613 // chain result. The result value is dead because the bswap is dead.
3614 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
3615
3616 // Return N so it doesn't get rechecked!
3617 return SDOperand(N, 0);
3618 }
3619
Chris Lattner51269842006-03-01 05:50:56 +00003620 break;
Chris Lattner4468c222006-03-31 06:02:07 +00003621 case PPCISD::VCMP: {
3622 // If a VCMPo node already exists with exactly the same operands as this
3623 // node, use its result instead of this node (VCMPo computes both a CR6 and
3624 // a normal output).
3625 //
3626 if (!N->getOperand(0).hasOneUse() &&
3627 !N->getOperand(1).hasOneUse() &&
3628 !N->getOperand(2).hasOneUse()) {
3629
3630 // Scan all of the users of the LHS, looking for VCMPo's that match.
3631 SDNode *VCMPoNode = 0;
3632
3633 SDNode *LHSN = N->getOperand(0).Val;
3634 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
3635 UI != E; ++UI)
3636 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
3637 (*UI)->getOperand(1) == N->getOperand(1) &&
3638 (*UI)->getOperand(2) == N->getOperand(2) &&
3639 (*UI)->getOperand(0) == N->getOperand(0)) {
3640 VCMPoNode = *UI;
3641 break;
3642 }
3643
Chris Lattner00901202006-04-18 18:28:22 +00003644 // If there is no VCMPo node, or if the flag value has a single use, don't
3645 // transform this.
3646 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
3647 break;
3648
3649 // Look at the (necessarily single) use of the flag value. If it has a
3650 // chain, this transformation is more complex. Note that multiple things
3651 // could use the value result, which we should ignore.
3652 SDNode *FlagUser = 0;
3653 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
3654 FlagUser == 0; ++UI) {
3655 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
3656 SDNode *User = *UI;
3657 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
3658 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
3659 FlagUser = User;
3660 break;
3661 }
3662 }
3663 }
3664
3665 // If the user is a MFCR instruction, we know this is safe. Otherwise we
3666 // give up for right now.
3667 if (FlagUser->getOpcode() == PPCISD::MFCR)
Chris Lattner4468c222006-03-31 06:02:07 +00003668 return SDOperand(VCMPoNode, 0);
3669 }
3670 break;
3671 }
Chris Lattner90564f22006-04-18 17:59:36 +00003672 case ISD::BR_CC: {
3673 // If this is a branch on an altivec predicate comparison, lower this so
3674 // that we don't have to do a MFCR: instead, branch directly on CR6. This
3675 // lowering is done pre-legalize, because the legalizer lowers the predicate
3676 // compare down to code that is difficult to reassemble.
3677 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
3678 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
3679 int CompareOpc;
3680 bool isDot;
3681
3682 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
3683 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
3684 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
3685 assert(isDot && "Can't compare against a vector result!");
3686
3687 // If this is a comparison against something other than 0/1, then we know
3688 // that the condition is never/always true.
3689 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
3690 if (Val != 0 && Val != 1) {
3691 if (CC == ISD::SETEQ) // Cond never true, remove branch.
3692 return N->getOperand(0);
3693 // Always !=, turn it into an unconditional branch.
3694 return DAG.getNode(ISD::BR, MVT::Other,
3695 N->getOperand(0), N->getOperand(4));
3696 }
3697
3698 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
3699
3700 // Create the PPCISD altivec 'dot' comparison node.
Chris Lattner90564f22006-04-18 17:59:36 +00003701 std::vector<MVT::ValueType> VTs;
Chris Lattner79e490a2006-08-11 17:18:05 +00003702 SDOperand Ops[] = {
3703 LHS.getOperand(2), // LHS of compare
3704 LHS.getOperand(3), // RHS of compare
3705 DAG.getConstant(CompareOpc, MVT::i32)
3706 };
Chris Lattner90564f22006-04-18 17:59:36 +00003707 VTs.push_back(LHS.getOperand(2).getValueType());
3708 VTs.push_back(MVT::Flag);
Chris Lattner79e490a2006-08-11 17:18:05 +00003709 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
Chris Lattner90564f22006-04-18 17:59:36 +00003710
3711 // Unpack the result based on how the target uses it.
Chris Lattnerdf4ed632006-11-17 22:10:59 +00003712 PPC::Predicate CompOpc;
Chris Lattner90564f22006-04-18 17:59:36 +00003713 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
3714 default: // Can't happen, don't crash on invalid number though.
3715 case 0: // Branch on the value of the EQ bit of CR6.
Chris Lattnerdf4ed632006-11-17 22:10:59 +00003716 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
Chris Lattner90564f22006-04-18 17:59:36 +00003717 break;
3718 case 1: // Branch on the inverted value of the EQ bit of CR6.
Chris Lattnerdf4ed632006-11-17 22:10:59 +00003719 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
Chris Lattner90564f22006-04-18 17:59:36 +00003720 break;
3721 case 2: // Branch on the value of the LT bit of CR6.
Chris Lattnerdf4ed632006-11-17 22:10:59 +00003722 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
Chris Lattner90564f22006-04-18 17:59:36 +00003723 break;
3724 case 3: // Branch on the inverted value of the LT bit of CR6.
Chris Lattnerdf4ed632006-11-17 22:10:59 +00003725 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
Chris Lattner90564f22006-04-18 17:59:36 +00003726 break;
3727 }
3728
3729 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
Chris Lattner90564f22006-04-18 17:59:36 +00003730 DAG.getConstant(CompOpc, MVT::i32),
Chris Lattner18258c62006-11-17 22:37:34 +00003731 DAG.getRegister(PPC::CR6, MVT::i32),
Chris Lattner90564f22006-04-18 17:59:36 +00003732 N->getOperand(4), CompNode.getValue(1));
3733 }
3734 break;
3735 }
Chris Lattner8c13d0a2006-03-01 04:57:39 +00003736 }
3737
3738 return SDOperand();
3739}
3740
Chris Lattner1a635d62006-04-14 06:01:58 +00003741//===----------------------------------------------------------------------===//
3742// Inline Assembly Support
3743//===----------------------------------------------------------------------===//
3744
Chris Lattnerbbe77de2006-04-02 06:26:07 +00003745void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
Dan Gohman977a76f2008-02-13 22:28:48 +00003746 const APInt &Mask,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +00003747 APInt &KnownZero,
3748 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +00003749 const SelectionDAG &DAG,
Chris Lattnerbbe77de2006-04-02 06:26:07 +00003750 unsigned Depth) const {
Dan Gohmanfd29e0e2008-02-13 00:35:47 +00003751 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
Chris Lattnerbbe77de2006-04-02 06:26:07 +00003752 switch (Op.getOpcode()) {
3753 default: break;
Chris Lattnerd9989382006-07-10 20:56:58 +00003754 case PPCISD::LBRX: {
3755 // lhbrx is known to have the top bits cleared out.
3756 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
3757 KnownZero = 0xFFFF0000;
3758 break;
3759 }
Chris Lattnerbbe77de2006-04-02 06:26:07 +00003760 case ISD::INTRINSIC_WO_CHAIN: {
3761 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
3762 default: break;
3763 case Intrinsic::ppc_altivec_vcmpbfp_p:
3764 case Intrinsic::ppc_altivec_vcmpeqfp_p:
3765 case Intrinsic::ppc_altivec_vcmpequb_p:
3766 case Intrinsic::ppc_altivec_vcmpequh_p:
3767 case Intrinsic::ppc_altivec_vcmpequw_p:
3768 case Intrinsic::ppc_altivec_vcmpgefp_p:
3769 case Intrinsic::ppc_altivec_vcmpgtfp_p:
3770 case Intrinsic::ppc_altivec_vcmpgtsb_p:
3771 case Intrinsic::ppc_altivec_vcmpgtsh_p:
3772 case Intrinsic::ppc_altivec_vcmpgtsw_p:
3773 case Intrinsic::ppc_altivec_vcmpgtub_p:
3774 case Intrinsic::ppc_altivec_vcmpgtuh_p:
3775 case Intrinsic::ppc_altivec_vcmpgtuw_p:
3776 KnownZero = ~1U; // All bits but the low one are known to be zero.
3777 break;
3778 }
3779 }
3780 }
3781}
3782
3783
Chris Lattner4234f572007-03-25 02:14:49 +00003784/// getConstraintType - Given a constraint, return the type of
Chris Lattnerad3bc8d2006-02-07 20:16:30 +00003785/// constraint it is for this target.
3786PPCTargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +00003787PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
3788 if (Constraint.size() == 1) {
3789 switch (Constraint[0]) {
3790 default: break;
3791 case 'b':
3792 case 'r':
3793 case 'f':
3794 case 'v':
3795 case 'y':
3796 return C_RegisterClass;
3797 }
3798 }
3799 return TargetLowering::getConstraintType(Constraint);
Chris Lattnerad3bc8d2006-02-07 20:16:30 +00003800}
3801
Chris Lattner331d1bc2006-11-02 01:44:04 +00003802std::pair<unsigned, const TargetRegisterClass*>
3803PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3804 MVT::ValueType VT) const {
Chris Lattnerddc787d2006-01-31 19:20:21 +00003805 if (Constraint.size() == 1) {
Chris Lattner331d1bc2006-11-02 01:44:04 +00003806 // GCC RS6000 Constraint Letters
3807 switch (Constraint[0]) {
3808 case 'b': // R1-R31
3809 case 'r': // R0-R31
3810 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
3811 return std::make_pair(0U, PPC::G8RCRegisterClass);
3812 return std::make_pair(0U, PPC::GPRCRegisterClass);
3813 case 'f':
3814 if (VT == MVT::f32)
3815 return std::make_pair(0U, PPC::F4RCRegisterClass);
3816 else if (VT == MVT::f64)
3817 return std::make_pair(0U, PPC::F8RCRegisterClass);
3818 break;
Chris Lattnerddc787d2006-01-31 19:20:21 +00003819 case 'v':
Chris Lattner331d1bc2006-11-02 01:44:04 +00003820 return std::make_pair(0U, PPC::VRRCRegisterClass);
3821 case 'y': // crrc
3822 return std::make_pair(0U, PPC::CRRCRegisterClass);
Chris Lattnerddc787d2006-01-31 19:20:21 +00003823 }
3824 }
3825
Chris Lattner331d1bc2006-11-02 01:44:04 +00003826 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
Chris Lattnerddc787d2006-01-31 19:20:21 +00003827}
Chris Lattner763317d2006-02-07 00:47:13 +00003828
Chris Lattner331d1bc2006-11-02 01:44:04 +00003829
Chris Lattner48884cd2007-08-25 00:47:38 +00003830/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3831/// vector. If it is invalid, don't add anything to Ops.
3832void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
3833 std::vector<SDOperand>&Ops,
3834 SelectionDAG &DAG) {
3835 SDOperand Result(0,0);
Chris Lattner763317d2006-02-07 00:47:13 +00003836 switch (Letter) {
3837 default: break;
3838 case 'I':
3839 case 'J':
3840 case 'K':
3841 case 'L':
3842 case 'M':
3843 case 'N':
3844 case 'O':
3845 case 'P': {
Chris Lattner9f5d5782007-05-15 01:31:05 +00003846 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
Chris Lattner48884cd2007-08-25 00:47:38 +00003847 if (!CST) return; // Must be an immediate to match.
Chris Lattner9f5d5782007-05-15 01:31:05 +00003848 unsigned Value = CST->getValue();
Chris Lattner763317d2006-02-07 00:47:13 +00003849 switch (Letter) {
3850 default: assert(0 && "Unknown constraint letter!");
3851 case 'I': // "I" is a signed 16-bit constant.
Chris Lattner9f5d5782007-05-15 01:31:05 +00003852 if ((short)Value == (int)Value)
Chris Lattner48884cd2007-08-25 00:47:38 +00003853 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattnerdba1aee2006-10-31 19:40:43 +00003854 break;
Chris Lattner763317d2006-02-07 00:47:13 +00003855 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
3856 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
Chris Lattner9f5d5782007-05-15 01:31:05 +00003857 if ((short)Value == 0)
Chris Lattner48884cd2007-08-25 00:47:38 +00003858 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattnerdba1aee2006-10-31 19:40:43 +00003859 break;
Chris Lattner763317d2006-02-07 00:47:13 +00003860 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
Chris Lattner9f5d5782007-05-15 01:31:05 +00003861 if ((Value >> 16) == 0)
Chris Lattner48884cd2007-08-25 00:47:38 +00003862 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattnerdba1aee2006-10-31 19:40:43 +00003863 break;
Chris Lattner763317d2006-02-07 00:47:13 +00003864 case 'M': // "M" is a constant that is greater than 31.
Chris Lattner9f5d5782007-05-15 01:31:05 +00003865 if (Value > 31)
Chris Lattner48884cd2007-08-25 00:47:38 +00003866 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattnerdba1aee2006-10-31 19:40:43 +00003867 break;
Chris Lattner763317d2006-02-07 00:47:13 +00003868 case 'N': // "N" is a positive constant that is an exact power of two.
Chris Lattner9f5d5782007-05-15 01:31:05 +00003869 if ((int)Value > 0 && isPowerOf2_32(Value))
Chris Lattner48884cd2007-08-25 00:47:38 +00003870 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattnerdba1aee2006-10-31 19:40:43 +00003871 break;
Chris Lattner763317d2006-02-07 00:47:13 +00003872 case 'O': // "O" is the constant zero.
Chris Lattner9f5d5782007-05-15 01:31:05 +00003873 if (Value == 0)
Chris Lattner48884cd2007-08-25 00:47:38 +00003874 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattnerdba1aee2006-10-31 19:40:43 +00003875 break;
Chris Lattner763317d2006-02-07 00:47:13 +00003876 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
Chris Lattner9f5d5782007-05-15 01:31:05 +00003877 if ((short)-Value == (int)-Value)
Chris Lattner48884cd2007-08-25 00:47:38 +00003878 Result = DAG.getTargetConstant(Value, Op.getValueType());
Chris Lattnerdba1aee2006-10-31 19:40:43 +00003879 break;
Chris Lattner763317d2006-02-07 00:47:13 +00003880 }
3881 break;
3882 }
3883 }
3884
Chris Lattner48884cd2007-08-25 00:47:38 +00003885 if (Result.Val) {
3886 Ops.push_back(Result);
3887 return;
3888 }
3889
Chris Lattner763317d2006-02-07 00:47:13 +00003890 // Handle standard constraint letters.
Chris Lattner48884cd2007-08-25 00:47:38 +00003891 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
Chris Lattner763317d2006-02-07 00:47:13 +00003892}
Evan Chengc4c62572006-03-13 23:20:37 +00003893
Chris Lattnerc9addb72007-03-30 23:15:24 +00003894// isLegalAddressingMode - Return true if the addressing mode represented
3895// by AM is legal for this target, for a load/store of the specified type.
3896bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3897 const Type *Ty) const {
3898 // FIXME: PPC does not allow r+i addressing modes for vectors!
3899
3900 // PPC allows a sign-extended 16-bit immediate field.
3901 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3902 return false;
3903
3904 // No global is ever allowed as a base.
3905 if (AM.BaseGV)
3906 return false;
3907
3908 // PPC only support r+r,
3909 switch (AM.Scale) {
3910 case 0: // "r+i" or just "i", depending on HasBaseReg.
3911 break;
3912 case 1:
3913 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3914 return false;
3915 // Otherwise we have r+r or r+i.
3916 break;
3917 case 2:
3918 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3919 return false;
3920 // Allow 2*r as r+r.
3921 break;
Chris Lattner7c7ba9d2007-04-09 22:10:05 +00003922 default:
3923 // No other scales are supported.
3924 return false;
Chris Lattnerc9addb72007-03-30 23:15:24 +00003925 }
3926
3927 return true;
3928}
3929
Evan Chengc4c62572006-03-13 23:20:37 +00003930/// isLegalAddressImmediate - Return true if the integer value can be used
Evan Cheng86193912007-03-12 23:29:01 +00003931/// as the offset of the target addressing mode for load / store of the
3932/// given type.
3933bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
Evan Chengc4c62572006-03-13 23:20:37 +00003934 // PPC allows a sign-extended 16-bit immediate field.
3935 return (V > -(1 << 16) && V < (1 << 16)-1);
3936}
Reid Spencer3a9ec242006-08-28 01:02:49 +00003937
3938bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
Chris Lattnerc9addb72007-03-30 23:15:24 +00003939 return false;
Reid Spencer3a9ec242006-08-28 01:02:49 +00003940}
Nicolas Geoffray43c6e7c2007-03-01 13:11:38 +00003941
Chris Lattner3fc027d2007-12-08 06:59:59 +00003942SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
3943 // Depths > 0 not supported yet!
3944 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3945 return SDOperand();
3946
3947 MachineFunction &MF = DAG.getMachineFunction();
3948 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3949 int RAIdx = FuncInfo->getReturnAddrSaveIndex();
3950 if (RAIdx == 0) {
3951 bool isPPC64 = PPCSubTarget.isPPC64();
3952 int Offset =
3953 PPCFrameInfo::getReturnSaveOffset(isPPC64, PPCSubTarget.isMachoABI());
3954
3955 // Set up a frame object for the return address.
3956 RAIdx = MF.getFrameInfo()->CreateFixedObject(isPPC64 ? 8 : 4, Offset);
3957
3958 // Remember it for next time.
3959 FuncInfo->setReturnAddrSaveIndex(RAIdx);
3960
3961 // Make sure the function really does not optimize away the store of the RA
3962 // to the stack.
3963 FuncInfo->setLRStoreRequired();
3964 }
3965
3966 // Just load the return address off the stack.
3967 SDOperand RetAddrFI = DAG.getFrameIndex(RAIdx, getPointerTy());
3968 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
3969}
3970
3971SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
Nicolas Geoffray43c6e7c2007-03-01 13:11:38 +00003972 // Depths > 0 not supported yet!
3973 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3974 return SDOperand();
3975
3976 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3977 bool isPPC64 = PtrVT == MVT::i64;
3978
3979 MachineFunction &MF = DAG.getMachineFunction();
3980 MachineFrameInfo *MFI = MF.getFrameInfo();
3981 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
3982 && MFI->getStackSize();
3983
3984 if (isPPC64)
3985 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
Bill Wendlingb8a80f02007-08-30 00:59:19 +00003986 MVT::i64);
Nicolas Geoffray43c6e7c2007-03-01 13:11:38 +00003987 else
3988 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,
3989 MVT::i32);
3990}