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Misha Brukman5dfe3a92004-06-21 16:55:25 +00001//===- PowerPCInstrInfo.cpp - PowerPC Instruction Information ---*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PowerPCInstrInfo.h"
15#include "PowerPC.h"
Misha Brukman5dfe3a92004-06-21 16:55:25 +000016#include "PowerPCGenInstrInfo.inc"
Misha Brukmanbe15f672004-07-16 20:54:25 +000017#include "llvm/CodeGen/MachineInstrBuilder.h"
Misha Brukman01d46e92004-07-16 20:51:55 +000018#include <iostream>
Misha Brukman5dfe3a92004-06-21 16:55:25 +000019using namespace llvm;
20
21PowerPCInstrInfo::PowerPCInstrInfo()
Misha Brukmanbe15f672004-07-16 20:54:25 +000022 : TargetInstrInfo(PowerPCInsts, sizeof(PowerPCInsts)/sizeof(PowerPCInsts[0]))
23{ }
Misha Brukman01d46e92004-07-16 20:51:55 +000024
25bool PowerPCInstrInfo::isMoveInstr(const MachineInstr& MI,
Misha Brukmanbe15f672004-07-16 20:54:25 +000026 unsigned& sourceReg,
27 unsigned& destReg) const {
Misha Brukman01d46e92004-07-16 20:51:55 +000028 MachineOpCode oc = MI.getOpcode();
Misha Brukman774a2972004-07-26 21:29:00 +000029 if (oc == PPC32::OR) { // or r1, r2, r2
Misha Brukmanbe15f672004-07-16 20:54:25 +000030 assert(MI.getNumOperands() == 3 &&
31 MI.getOperand(0).isRegister() &&
32 MI.getOperand(1).isRegister() &&
33 MI.getOperand(2).isRegister() &&
34 "invalid register-register int move instruction");
35 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
Misha Brukman01d46e92004-07-16 20:51:55 +000036 sourceReg = MI.getOperand(1).getReg();
37 destReg = MI.getOperand(0).getReg();
38 return true;
Misha Brukmanbe15f672004-07-16 20:54:25 +000039 }
Misha Brukman774a2972004-07-26 21:29:00 +000040 } else if (oc == PPC32::ADDI) { // addi r1, r2, 0
41 if (MI.getNumOperands() == 3 &&
42 MI.getOperand(0).isRegister() &&
43 MI.getOperand(1).isRegister() &&
44 MI.getOperand(2).isImmediate() &&
45 MI.getOperand(2).getImmedValue() == 0) {
46 sourceReg = MI.getOperand(1).getReg();
47 destReg = MI.getOperand(0).getReg();
48 return true;
49 }
50 } else if (oc == PPC32::FMR) { // fmr r1, r2
Misha Brukmanbe15f672004-07-16 20:54:25 +000051 assert(MI.getNumOperands() == 2 &&
52 MI.getOperand(0).isRegister() &&
53 MI.getOperand(1).isRegister() &&
54 "invalid register-register fp move instruction");
55 sourceReg = MI.getOperand(1).getReg();
56 destReg = MI.getOperand(0).getReg();
57 return true;
Misha Brukman01d46e92004-07-16 20:51:55 +000058 }
59 return false;
60}