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Chris Lattnera3b8b5c2004-07-23 17:56:30 +00001//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LiveInterval analysis pass which is used
11// by the Linear Scan Register allocator. This pass linearizes the
12// basic blocks of the function in DFS order and uses the
13// LiveVariables pass to conservatively compute live intervals for
14// each virtual and physical register.
15//
16//===----------------------------------------------------------------------===//
17
Jakob Stoklund Olesen4281e202012-01-07 07:39:47 +000018#define DEBUG_TYPE "regalloc"
Chris Lattner3c3fe462005-09-21 04:19:09 +000019#include "llvm/CodeGen/LiveIntervalAnalysis.h"
Chris Lattner015959e2004-05-01 21:24:39 +000020#include "llvm/Value.h"
Dan Gohman6d69ba82008-07-25 00:02:30 +000021#include "llvm/Analysis/AliasAnalysis.h"
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000022#include "llvm/CodeGen/LiveVariables.h"
Jakob Stoklund Olesen34c6f982012-06-05 22:02:15 +000023#include "llvm/CodeGen/MachineDominators.h"
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000024#include "llvm/CodeGen/MachineInstr.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000025#include "llvm/CodeGen/MachineRegisterInfo.h"
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000026#include "llvm/CodeGen/Passes.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +000027#include "llvm/Target/TargetRegisterInfo.h"
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000028#include "llvm/Target/TargetInstrInfo.h"
29#include "llvm/Target/TargetMachine.h"
Jakob Stoklund Olesen3dfa38a2012-07-27 20:58:46 +000030#include "llvm/Support/CommandLine.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000031#include "llvm/Support/Debug.h"
Torok Edwin7d696d82009-07-11 13:10:19 +000032#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/raw_ostream.h"
Andrew Trickd35576b2012-02-13 20:44:42 +000034#include "llvm/ADT/DenseSet.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000035#include "llvm/ADT/STLExtras.h"
Jakob Stoklund Olesen34c6f982012-06-05 22:02:15 +000036#include "LiveRangeCalc.h"
Jakob Stoklund Olesene617ccb2012-09-06 18:15:18 +000037#include "VirtRegMap.h"
Alkis Evlogimenos20aa4742004-09-03 18:19:51 +000038#include <algorithm>
Lang Hamesf41538d2009-06-02 16:53:25 +000039#include <limits>
Jeff Cohen97af7512006-12-02 02:22:01 +000040#include <cmath>
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000041using namespace llvm;
42
Jakob Stoklund Olesen3dfa38a2012-07-27 20:58:46 +000043// Switch to the new experimental algorithm for computing live intervals.
44static cl::opt<bool>
45NewLiveIntervals("new-live-intervals", cl::Hidden,
46 cl::desc("Use new algorithm forcomputing live intervals"));
47
Devang Patel19974732007-05-03 01:11:54 +000048char LiveIntervals::ID = 0;
Jakob Stoklund Olesendcc44362012-08-03 22:12:54 +000049char &llvm::LiveIntervalsID = LiveIntervals::ID;
Owen Anderson2ab36d32010-10-12 19:48:12 +000050INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
51 "Live Interval Analysis", false, false)
Andrew Trick8dd26252012-02-10 04:10:36 +000052INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
Owen Anderson2ab36d32010-10-12 19:48:12 +000053INITIALIZE_PASS_DEPENDENCY(LiveVariables)
Andrew Trick8dd26252012-02-10 04:10:36 +000054INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
Owen Anderson2ab36d32010-10-12 19:48:12 +000055INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
Owen Anderson2ab36d32010-10-12 19:48:12 +000056INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
Owen Andersonce665bd2010-10-07 22:25:06 +000057 "Live Interval Analysis", false, false)
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000058
Chris Lattnerf7da2c72006-08-24 22:43:55 +000059void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
Dan Gohman845012e2009-07-31 23:37:33 +000060 AU.setPreservesCFG();
Dan Gohman6d69ba82008-07-25 00:02:30 +000061 AU.addRequired<AliasAnalysis>();
62 AU.addPreserved<AliasAnalysis>();
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +000063 AU.addRequired<LiveVariables>();
Evan Cheng148341c2010-08-17 21:00:37 +000064 AU.addPreserved<LiveVariables>();
Andrew Trickd35576b2012-02-13 20:44:42 +000065 AU.addPreservedID(MachineLoopInfoID);
Jakob Stoklund Olesenc4118452012-06-20 23:31:34 +000066 AU.addRequiredTransitiveID(MachineDominatorsID);
Bill Wendling67d65bb2008-01-04 20:54:55 +000067 AU.addPreservedID(MachineDominatorsID);
Lang Hames233a60e2009-11-03 23:52:08 +000068 AU.addPreserved<SlotIndexes>();
69 AU.addRequiredTransitive<SlotIndexes>();
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +000070 MachineFunctionPass::getAnalysisUsage(AU);
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000071}
72
Jakob Stoklund Olesen34c6f982012-06-05 22:02:15 +000073LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
74 DomTree(0), LRCalc(0) {
75 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
76}
77
78LiveIntervals::~LiveIntervals() {
79 delete LRCalc;
80}
81
Chris Lattnerf7da2c72006-08-24 22:43:55 +000082void LiveIntervals::releaseMemory() {
Owen Anderson03857b22008-08-13 21:49:13 +000083 // Free the live intervals themselves.
Jakob Stoklund Olesen7fa67842012-06-22 20:37:52 +000084 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
85 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
86 VirtRegIntervals.clear();
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +000087 RegMaskSlots.clear();
88 RegMaskBits.clear();
Jakob Stoklund Olesen34e85d02012-02-10 01:26:29 +000089 RegMaskBlocks.clear();
Lang Hamesffd13262009-07-09 03:57:02 +000090
Jakob Stoklund Olesen34c6f982012-06-05 22:02:15 +000091 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
92 delete RegUnitIntervals[i];
93 RegUnitIntervals.clear();
94
Benjamin Kramerce9a20b2010-06-26 11:30:59 +000095 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
96 VNInfoAllocator.Reset();
Alkis Evlogimenos08cec002004-01-31 19:59:32 +000097}
98
Owen Anderson80b3ce62008-05-28 20:54:50 +000099/// runOnMachineFunction - Register allocate the whole function
100///
101bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000102 MF = &fn;
103 MRI = &MF->getRegInfo();
104 TM = &fn.getTarget();
105 TRI = TM->getRegisterInfo();
106 TII = TM->getInstrInfo();
107 AA = &getAnalysis<AliasAnalysis>();
108 LV = &getAnalysis<LiveVariables>();
109 Indexes = &getAnalysis<SlotIndexes>();
Jakob Stoklund Olesenc4118452012-06-20 23:31:34 +0000110 DomTree = &getAnalysis<MachineDominatorTree>();
111 if (!LRCalc)
Jakob Stoklund Olesen34c6f982012-06-05 22:02:15 +0000112 LRCalc = new LiveRangeCalc();
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000113 AllocatableRegs = TRI->getAllocatableSet(fn);
114 ReservedRegs = TRI->getReservedRegs(fn);
Owen Anderson80b3ce62008-05-28 20:54:50 +0000115
Jakob Stoklund Olesen3dfa38a2012-07-27 20:58:46 +0000116 // Allocate space for all virtual registers.
117 VirtRegIntervals.resize(MRI->getNumVirtRegs());
118
119 if (NewLiveIntervals) {
120 // This is the new way of computing live intervals.
121 // It is independent of LiveVariables, and it can run at any time.
Jakob Stoklund Olesenc16bf792012-07-27 21:56:39 +0000122 computeVirtRegs();
123 computeRegMasks();
Jakob Stoklund Olesen3dfa38a2012-07-27 20:58:46 +0000124 } else {
125 // This is the old way of computing live intervals.
126 // It depends on LiveVariables.
127 computeIntervals();
128 }
Jakob Stoklund Olesenc4118452012-06-20 23:31:34 +0000129 computeLiveInRegUnits();
Jakob Stoklund Olesen34c6f982012-06-05 22:02:15 +0000130
Chris Lattner70ca3582004-09-30 15:59:17 +0000131 DEBUG(dump());
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000132 return true;
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000133}
134
Chris Lattner70ca3582004-09-30 15:59:17 +0000135/// print - Implement the dump method.
Chris Lattner45cfe542009-08-23 06:03:38 +0000136void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
Chris Lattner705e07f2009-08-23 03:41:05 +0000137 OS << "********** INTERVALS **********\n";
Jakob Stoklund Olesenf658af52012-02-14 23:46:21 +0000138
Jakob Stoklund Olesen34c6f982012-06-05 22:02:15 +0000139 // Dump the regunits.
140 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
141 if (LiveInterval *LI = RegUnitIntervals[i])
142 OS << PrintRegUnit(i, TRI) << " = " << *LI << '\n';
143
Jakob Stoklund Olesenf658af52012-02-14 23:46:21 +0000144 // Dump the virtregs.
Jakob Stoklund Olesen7fa67842012-06-22 20:37:52 +0000145 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
146 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
147 if (hasInterval(Reg))
148 OS << PrintReg(Reg) << " = " << getInterval(Reg) << '\n';
149 }
Chris Lattner70ca3582004-09-30 15:59:17 +0000150
Evan Cheng752195e2009-09-14 21:33:42 +0000151 printInstrs(OS);
152}
153
154void LiveIntervals::printInstrs(raw_ostream &OS) const {
Chris Lattner705e07f2009-08-23 03:41:05 +0000155 OS << "********** MACHINEINSTRS **********\n";
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000156 MF->print(OS, Indexes);
Chris Lattner70ca3582004-09-30 15:59:17 +0000157}
158
Evan Cheng752195e2009-09-14 21:33:42 +0000159void LiveIntervals::dumpInstrs() const {
David Greene8a342292010-01-04 22:49:02 +0000160 printInstrs(dbgs());
Evan Cheng752195e2009-09-14 21:33:42 +0000161}
162
Evan Chengafff40a2010-05-04 20:26:52 +0000163static
Evan Cheng37499432010-05-05 18:27:40 +0000164bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
Evan Chengafff40a2010-05-04 20:26:52 +0000165 unsigned Reg = MI.getOperand(MOIdx).getReg();
166 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
167 const MachineOperand &MO = MI.getOperand(i);
168 if (!MO.isReg())
169 continue;
170 if (MO.getReg() == Reg && MO.isDef()) {
171 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
172 MI.getOperand(MOIdx).getSubReg() &&
Jakob Stoklund Olesened2185e2010-07-06 23:26:25 +0000173 (MO.getSubReg() || MO.isImplicit()));
Evan Chengafff40a2010-05-04 20:26:52 +0000174 return true;
175 }
176 }
177 return false;
178}
179
Evan Cheng37499432010-05-05 18:27:40 +0000180/// isPartialRedef - Return true if the specified def at the specific index is
181/// partially re-defining the specified live interval. A common case of this is
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000182/// a definition of the sub-register.
Evan Cheng37499432010-05-05 18:27:40 +0000183bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
184 LiveInterval &interval) {
185 if (!MO.getSubReg() || MO.isEarlyClobber())
186 return false;
187
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000188 SlotIndex RedefIndex = MIIdx.getRegSlot();
Evan Cheng37499432010-05-05 18:27:40 +0000189 const LiveRange *OldLR =
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000190 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
Lang Hames6e2968c2010-09-25 12:04:16 +0000191 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
192 if (DefMI != 0) {
Evan Cheng37499432010-05-05 18:27:40 +0000193 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
194 }
195 return false;
196}
197
Chris Lattnerbe4f88a2006-08-22 18:19:46 +0000198void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000199 MachineBasicBlock::iterator mi,
Lang Hames233a60e2009-11-03 23:52:08 +0000200 SlotIndex MIIdx,
Lang Hames86511252009-09-04 20:41:11 +0000201 MachineOperand& MO,
Evan Chengef0732d2008-07-10 07:35:43 +0000202 unsigned MOIdx,
Chris Lattnerbe4f88a2006-08-22 18:19:46 +0000203 LiveInterval &interval) {
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000204 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI));
Evan Cheng419852c2008-04-03 16:39:43 +0000205
Alkis Evlogimenos70651572004-08-04 09:46:56 +0000206 // Virtual registers may be defined multiple times (due to phi
207 // elimination and 2-addr elimination). Much of what we do only has to be
208 // done once for the vreg. We use an empty interval to detect the first
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000209 // time we see a vreg.
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000210 LiveVariables::VarInfo& vi = LV->getVarInfo(interval.reg);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000211 if (interval.empty()) {
212 // Get the Idx of the defining instructions.
Jakob Stoklund Olesend14614e2011-11-13 22:05:42 +0000213 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
Jakob Stoklund Olesen63e6a482010-05-21 16:32:16 +0000214
Jakob Stoklund Olesen92b7df02012-03-04 19:19:10 +0000215 // Make sure the first definition is not a partial redefinition.
216 assert(!MO.readsReg() && "First def cannot also read virtual register "
217 "missing <undef> flag?");
Jakob Stoklund Olesen63e6a482010-05-21 16:32:16 +0000218
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000219 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
Evan Cheng7ecb38b2007-08-29 20:45:00 +0000220 assert(ValNo->id == 0 && "First value in interval is not 0?");
Chris Lattner7ac2d312004-07-24 02:59:07 +0000221
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000222 // Loop over all of the blocks that the vreg is defined in. There are
223 // two cases we have to handle here. The most common case is a vreg
224 // whose lifetime is contained within a basic block. In this case there
225 // will be a single kill, in MBB, which comes after the definition.
226 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
227 // FIXME: what about dead vars?
Lang Hames233a60e2009-11-03 23:52:08 +0000228 SlotIndex killIdx;
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000229 if (vi.Kills[0] != mi)
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000230 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000231 else
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000232 killIdx = defIndex.getDeadSlot();
Chris Lattner6097d132004-07-19 02:15:56 +0000233
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000234 // If the kill happens after the definition, we have an intra-block
235 // live range.
236 if (killIdx > defIndex) {
Jeffrey Yasskin493a3d02009-05-26 18:27:15 +0000237 assert(vi.AliveBlocks.empty() &&
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000238 "Shouldn't be alive across any blocks!");
Evan Cheng7ecb38b2007-08-29 20:45:00 +0000239 LiveRange LR(defIndex, killIdx, ValNo);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000240 interval.addRange(LR);
David Greene8a342292010-01-04 22:49:02 +0000241 DEBUG(dbgs() << " +" << LR << "\n");
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000242 return;
243 }
Alkis Evlogimenosdd2cc652003-12-18 08:48:48 +0000244 }
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000245
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000246 // The other case we handle is when a virtual register lives to the end
247 // of the defining block, potentially live across some blocks, then is
248 // live into some number of blocks, but gets killed. Start by adding a
249 // range that goes from this definition to the end of the defining block.
Lang Hames74ab5ee2009-12-22 00:11:50 +0000250 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
David Greene8a342292010-01-04 22:49:02 +0000251 DEBUG(dbgs() << " +" << NewLR);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000252 interval.addRange(NewLR);
253
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000254 bool PHIJoin = LV->isPHIJoin(interval.reg);
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000255
256 if (PHIJoin) {
Jakob Stoklund Olesenfa8becb2012-06-19 22:50:53 +0000257 // A phi join register is killed at the end of the MBB and revived as a
258 // new valno in the killing blocks.
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000259 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
260 DEBUG(dbgs() << " phi-join");
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000261 } else {
262 // Iterate over all of the blocks that the variable is completely
263 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
264 // live interval.
265 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
266 E = vi.AliveBlocks.end(); I != E; ++I) {
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000267 MachineBasicBlock *aliveBlock = MF->getBlockNumbered(*I);
Jakob Stoklund Olesenfa8becb2012-06-19 22:50:53 +0000268 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock),
269 ValNo);
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000270 interval.addRange(LR);
271 DEBUG(dbgs() << " +" << LR);
272 }
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000273 }
274
275 // Finally, this virtual register is live from the start of any killing
276 // block to the 'use' slot of the killing instruction.
277 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
278 MachineInstr *Kill = vi.Kills[i];
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000279 SlotIndex Start = getMBBStartIdx(Kill->getParent());
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000280 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000281
282 // Create interval with one of a NEW value number. Note that this value
283 // number isn't actually defined by an instruction, weird huh? :)
284 if (PHIJoin) {
Lang Hames6e2968c2010-09-25 12:04:16 +0000285 assert(getInstructionFromIndex(Start) == 0 &&
286 "PHI def index points at actual instruction.");
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000287 ValNo = interval.getNextValue(Start, VNInfoAllocator);
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000288 }
289 LiveRange LR(Start, killIdx, ValNo);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000290 interval.addRange(LR);
David Greene8a342292010-01-04 22:49:02 +0000291 DEBUG(dbgs() << " +" << LR);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000292 }
293
294 } else {
Evan Cheng37499432010-05-05 18:27:40 +0000295 if (MultipleDefsBySameMI(*mi, MOIdx))
Nick Lewycky761fd4c2010-05-20 03:30:09 +0000296 // Multiple defs of the same virtual register by the same instruction.
297 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
Evan Chengafff40a2010-05-04 20:26:52 +0000298 // This is likely due to elimination of REG_SEQUENCE instructions. Return
299 // here since there is nothing to do.
300 return;
301
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000302 // If this is the second time we see a virtual register definition, it
303 // must be due to phi elimination or two addr elimination. If this is
Evan Chengbf105c82006-11-03 03:04:46 +0000304 // the result of two address elimination, then the vreg is one of the
305 // def-and-use register operand.
Evan Cheng37499432010-05-05 18:27:40 +0000306
307 // It may also be partial redef like this:
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000308 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
309 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
Evan Cheng37499432010-05-05 18:27:40 +0000310 bool PartReDef = isPartialRedef(MIIdx, MO, interval);
311 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000312 // If this is a two-address definition, then we have already processed
313 // the live range. The only problem is that we didn't realize there
314 // are actually two values in the live interval. Because of this we
315 // need to take the LiveRegion that defines this register and split it
316 // into two values.
Jakob Stoklund Olesend14614e2011-11-13 22:05:42 +0000317 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000318
Lang Hames35f291d2009-09-12 03:34:03 +0000319 const LiveRange *OldLR =
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000320 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
Evan Cheng7ecb38b2007-08-29 20:45:00 +0000321 VNInfo *OldValNo = OldLR->valno;
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000322 SlotIndex DefIndex = OldValNo->def.getRegSlot();
Evan Cheng4f8ff162007-08-11 00:59:19 +0000323
Jakob Stoklund Olesenc66d0f22010-06-16 21:29:40 +0000324 // Delete the previous value, which should be short and continuous,
Chris Lattnerbe4f88a2006-08-22 18:19:46 +0000325 // because the 2-addr copy must be in the same MBB as the redef.
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000326 interval.removeRange(DefIndex, RedefIndex);
Alkis Evlogimenos70651572004-08-04 09:46:56 +0000327
Chris Lattner91725b72006-08-31 05:54:43 +0000328 // The new value number (#1) is defined by the instruction we claimed
329 // defined value #0.
Lang Hames6e2968c2010-09-25 12:04:16 +0000330 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
Lang Hames857c4e02009-06-17 21:01:20 +0000331
Chris Lattner91725b72006-08-31 05:54:43 +0000332 // Value#0 is now defined by the 2-addr instruction.
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000333 OldValNo->def = RedefIndex;
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000334
Chris Lattnerbe4f88a2006-08-22 18:19:46 +0000335 // Add the new live interval which replaces the range for the input copy.
336 LiveRange LR(DefIndex, RedefIndex, ValNo);
David Greene8a342292010-01-04 22:49:02 +0000337 DEBUG(dbgs() << " replace range with " << LR);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000338 interval.addRange(LR);
339
340 // If this redefinition is dead, we need to add a dummy unit live
341 // range covering the def slot.
Owen Anderson6b098de2008-06-25 23:39:39 +0000342 if (MO.isDead())
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000343 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
Lang Hames233a60e2009-11-03 23:52:08 +0000344 OldValNo));
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000345
Jakob Stoklund Olesenb77ec7d2012-06-05 22:51:54 +0000346 DEBUG(dbgs() << " RESULT: " << interval);
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000347 } else if (LV->isPHIJoin(interval.reg)) {
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000348 // In the case of PHI elimination, each variable definition is only
349 // live until the end of the block. We've already taken care of the
350 // rest of the live range.
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000351
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000352 SlotIndex defIndex = MIIdx.getRegSlot();
Evan Chengfb112882009-03-23 08:01:15 +0000353 if (MO.isEarlyClobber())
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000354 defIndex = MIIdx.getRegSlot(true);
Evan Cheng752195e2009-09-14 21:33:42 +0000355
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000356 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000357
Lang Hames74ab5ee2009-12-22 00:11:50 +0000358 SlotIndex killIndex = getMBBEndIdx(mbb);
Evan Cheng7ecb38b2007-08-29 20:45:00 +0000359 LiveRange LR(defIndex, killIndex, ValNo);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000360 interval.addRange(LR);
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000361 DEBUG(dbgs() << " phi-join +" << LR);
Evan Cheng37499432010-05-05 18:27:40 +0000362 } else {
363 llvm_unreachable("Multiply defined register");
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000364 }
365 }
366
David Greene8a342292010-01-04 22:49:02 +0000367 DEBUG(dbgs() << '\n');
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000368}
369
Chris Lattnerf35fef72004-07-23 21:24:19 +0000370void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
371 MachineBasicBlock::iterator MI,
Lang Hames233a60e2009-11-03 23:52:08 +0000372 SlotIndex MIIdx,
Evan Chengef0732d2008-07-10 07:35:43 +0000373 MachineOperand& MO,
374 unsigned MOIdx) {
Owen Anderson6b098de2008-06-25 23:39:39 +0000375 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
Evan Chengef0732d2008-07-10 07:35:43 +0000376 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
Owen Anderson6b098de2008-06-25 23:39:39 +0000377 getOrCreateInterval(MO.getReg()));
Evan Chengb371f452007-02-19 21:49:54 +0000378}
379
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000380/// computeIntervals - computes the live intervals for virtual
Alkis Evlogimenos4d46e1e2004-01-31 14:37:41 +0000381/// registers. for some ordering of the machine instructions [1,N] a
Alkis Evlogimenos08cec002004-01-31 19:59:32 +0000382/// live interval is an interval [i, j) where 1 <= i <= j < N for
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000383/// which a variable is live
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000384void LiveIntervals::computeIntervals() {
David Greene8a342292010-01-04 22:49:02 +0000385 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
David Blaikie986d76d2012-08-22 17:18:53 +0000386 << "********** Function: " << MF->getName() << '\n');
Evan Chengd129d732009-07-17 19:43:40 +0000387
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000388 RegMaskBlocks.resize(MF->getNumBlockIDs());
Jakob Stoklund Olesen34e85d02012-02-10 01:26:29 +0000389
Evan Chengd129d732009-07-17 19:43:40 +0000390 SmallVector<unsigned, 8> UndefUses;
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000391 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
Chris Lattner428b92e2006-09-15 03:57:23 +0000392 MBBI != E; ++MBBI) {
393 MachineBasicBlock *MBB = MBBI;
Jakob Stoklund Olesen34e85d02012-02-10 01:26:29 +0000394 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
395
Evan Cheng00a99a32010-02-06 09:07:11 +0000396 if (MBB->empty())
397 continue;
398
Owen Anderson134eb732008-09-21 20:43:24 +0000399 // Track the index of the current machine instr.
Lang Hames233a60e2009-11-03 23:52:08 +0000400 SlotIndex MIIndex = getMBBStartIdx(MBB);
Bob Wilsonad98f792010-05-03 21:38:11 +0000401 DEBUG(dbgs() << "BB#" << MBB->getNumber()
402 << ":\t\t# derived from " << MBB->getName() << "\n");
Alkis Evlogimenos6b4edba2003-12-21 20:19:10 +0000403
Owen Anderson99500ae2008-09-15 22:00:38 +0000404 // Skip over empty initial indices.
Lang Hames233a60e2009-11-03 23:52:08 +0000405 if (getInstructionFromIndex(MIIndex) == 0)
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000406 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000407
Dale Johannesen1caedd02010-01-22 22:38:21 +0000408 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
409 MI != miEnd; ++MI) {
David Greene8a342292010-01-04 22:49:02 +0000410 DEBUG(dbgs() << MIIndex << "\t" << *MI);
Chris Lattner518bb532010-02-09 19:54:29 +0000411 if (MI->isDebugValue())
Dale Johannesen1caedd02010-01-22 22:38:21 +0000412 continue;
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000413 assert(Indexes->getInstructionFromIndex(MIIndex) == MI &&
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +0000414 "Lost SlotIndex synchronization");
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000415
Evan Cheng438f7bc2006-11-10 08:43:01 +0000416 // Handle defs.
Chris Lattner428b92e2006-09-15 03:57:23 +0000417 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
418 MachineOperand &MO = MI->getOperand(i);
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +0000419
420 // Collect register masks.
421 if (MO.isRegMask()) {
422 RegMaskSlots.push_back(MIIndex.getRegSlot());
423 RegMaskBits.push_back(MO.getRegMask());
424 continue;
425 }
426
Jakob Stoklund Olesen27b76692012-06-22 18:20:50 +0000427 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
Evan Chengd129d732009-07-17 19:43:40 +0000428 continue;
429
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000430 // handle register defs - build intervals
Evan Chengd129d732009-07-17 19:43:40 +0000431 if (MO.isDef())
Evan Chengef0732d2008-07-10 07:35:43 +0000432 handleRegisterDef(MBB, MI, MIIndex, MO, i);
Evan Chengd129d732009-07-17 19:43:40 +0000433 else if (MO.isUndef())
434 UndefUses.push_back(MO.getReg());
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000435 }
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000436
Lang Hames233a60e2009-11-03 23:52:08 +0000437 // Move to the next instr slot.
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000438 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000439 }
Jakob Stoklund Olesen34e85d02012-02-10 01:26:29 +0000440
441 // Compute the number of register mask instructions in this block.
442 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
443 RMB.second = RegMaskSlots.size() - RMB.first;;
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000444 }
Evan Chengd129d732009-07-17 19:43:40 +0000445
446 // Create empty intervals for registers defined by implicit_def's (except
447 // for those implicit_def that define values which are liveout of their
448 // blocks.
449 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
450 unsigned UndefReg = UndefUses[i];
451 (void)getOrCreateInterval(UndefReg);
452 }
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000453}
Alkis Evlogimenosb27ef242003-12-05 10:38:28 +0000454
Owen Anderson03857b22008-08-13 21:49:13 +0000455LiveInterval* LiveIntervals::createInterval(unsigned reg) {
Evan Cheng0a1fcce2009-02-08 11:04:35 +0000456 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
Owen Anderson03857b22008-08-13 21:49:13 +0000457 return new LiveInterval(reg, Weight);
Alkis Evlogimenos9a8b4902004-04-09 18:07:57 +0000458}
Evan Chengf2fbca62007-11-12 06:35:08 +0000459
Jakob Stoklund Olesen34c6f982012-06-05 22:02:15 +0000460
Jakob Stoklund Olesen3dfa38a2012-07-27 20:58:46 +0000461/// computeVirtRegInterval - Compute the live interval of a virtual register,
462/// based on defs and uses.
463void LiveIntervals::computeVirtRegInterval(LiveInterval *LI) {
464 assert(LRCalc && "LRCalc not initialized.");
465 assert(LI->empty() && "Should only compute empty intervals.");
466 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
467 LRCalc->createDeadDefs(LI);
468 LRCalc->extendToUses(LI);
469}
470
Jakob Stoklund Olesenc16bf792012-07-27 21:56:39 +0000471void LiveIntervals::computeVirtRegs() {
472 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
473 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
474 if (MRI->reg_nodbg_empty(Reg))
475 continue;
476 LiveInterval *LI = createInterval(Reg);
477 VirtRegIntervals[Reg] = LI;
478 computeVirtRegInterval(LI);
479 }
480}
481
482void LiveIntervals::computeRegMasks() {
483 RegMaskBlocks.resize(MF->getNumBlockIDs());
484
485 // Find all instructions with regmask operands.
486 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
487 MBBI != E; ++MBBI) {
488 MachineBasicBlock *MBB = MBBI;
489 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
490 RMB.first = RegMaskSlots.size();
491 for (MachineBasicBlock::iterator MI = MBB->begin(), ME = MBB->end();
492 MI != ME; ++MI)
493 for (MIOperands MO(MI); MO.isValid(); ++MO) {
494 if (!MO->isRegMask())
495 continue;
496 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
497 RegMaskBits.push_back(MO->getRegMask());
498 }
499 // Compute the number of register mask instructions in this block.
500 RMB.second = RegMaskSlots.size() - RMB.first;;
501 }
502}
Jakob Stoklund Olesen3dfa38a2012-07-27 20:58:46 +0000503
Jakob Stoklund Olesen34c6f982012-06-05 22:02:15 +0000504//===----------------------------------------------------------------------===//
505// Register Unit Liveness
506//===----------------------------------------------------------------------===//
507//
508// Fixed interference typically comes from ABI boundaries: Function arguments
509// and return values are passed in fixed registers, and so are exception
510// pointers entering landing pads. Certain instructions require values to be
511// present in specific registers. That is also represented through fixed
512// interference.
513//
514
515/// computeRegUnitInterval - Compute the live interval of a register unit, based
516/// on the uses and defs of aliasing registers. The interval should be empty,
517/// or contain only dead phi-defs from ABI blocks.
518void LiveIntervals::computeRegUnitInterval(LiveInterval *LI) {
519 unsigned Unit = LI->reg;
520
521 assert(LRCalc && "LRCalc not initialized.");
522 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
523
524 // The physregs aliasing Unit are the roots and their super-registers.
525 // Create all values as dead defs before extending to uses. Note that roots
526 // may share super-registers. That's OK because createDeadDefs() is
527 // idempotent. It is very rare for a register unit to have multiple roots, so
528 // uniquing super-registers is probably not worthwhile.
529 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
530 unsigned Root = *Roots;
531 if (!MRI->reg_empty(Root))
532 LRCalc->createDeadDefs(LI, Root);
533 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
534 if (!MRI->reg_empty(*Supers))
535 LRCalc->createDeadDefs(LI, *Supers);
536 }
537 }
538
539 // Now extend LI to reach all uses.
540 // Ignore uses of reserved registers. We only track defs of those.
541 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
542 unsigned Root = *Roots;
543 if (!isReserved(Root) && !MRI->reg_empty(Root))
544 LRCalc->extendToUses(LI, Root);
545 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
546 unsigned Reg = *Supers;
547 if (!isReserved(Reg) && !MRI->reg_empty(Reg))
548 LRCalc->extendToUses(LI, Reg);
549 }
550 }
551}
552
553
554/// computeLiveInRegUnits - Precompute the live ranges of any register units
555/// that are live-in to an ABI block somewhere. Register values can appear
556/// without a corresponding def when entering the entry block or a landing pad.
557///
558void LiveIntervals::computeLiveInRegUnits() {
559 RegUnitIntervals.resize(TRI->getNumRegUnits());
560 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
561
562 // Keep track of the intervals allocated.
563 SmallVector<LiveInterval*, 8> NewIntvs;
564
565 // Check all basic blocks for live-ins.
566 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
567 MFI != MFE; ++MFI) {
568 const MachineBasicBlock *MBB = MFI;
569
570 // We only care about ABI blocks: Entry + landing pads.
571 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
572 continue;
573
574 // Create phi-defs at Begin for all live-in registers.
575 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
576 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
577 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
578 LIE = MBB->livein_end(); LII != LIE; ++LII) {
579 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
580 unsigned Unit = *Units;
581 LiveInterval *Intv = RegUnitIntervals[Unit];
582 if (!Intv) {
583 Intv = RegUnitIntervals[Unit] = new LiveInterval(Unit, HUGE_VALF);
584 NewIntvs.push_back(Intv);
585 }
586 VNInfo *VNI = Intv->createDeadDef(Begin, getVNInfoAllocator());
Matt Beaumont-Gay05b46f02012-06-05 23:00:03 +0000587 (void)VNI;
Jakob Stoklund Olesen34c6f982012-06-05 22:02:15 +0000588 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
589 }
590 }
591 DEBUG(dbgs() << '\n');
592 }
593 DEBUG(dbgs() << "Created " << NewIntvs.size() << " new intervals.\n");
594
595 // Compute the 'normal' part of the intervals.
596 for (unsigned i = 0, e = NewIntvs.size(); i != e; ++i)
597 computeRegUnitInterval(NewIntvs[i]);
598}
599
600
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000601/// shrinkToUses - After removing some uses of a register, shrink its live
602/// range to just the remaining uses. This method does not compute reaching
603/// defs for new uses, and it doesn't remove dead defs.
Jakob Stoklund Olesen6a3dbd32011-03-17 20:37:07 +0000604bool LiveIntervals::shrinkToUses(LiveInterval *li,
Jakob Stoklund Olesen0d8ccaa2011-03-07 23:29:10 +0000605 SmallVectorImpl<MachineInstr*> *dead) {
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000606 DEBUG(dbgs() << "Shrink: " << *li << '\n');
607 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
Lang Hames567cdba2012-01-03 20:05:57 +0000608 && "Can only shrink virtual registers");
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000609 // Find all the values used, including PHI kills.
610 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
611
Jakob Stoklund Olesen031432f2011-09-15 15:24:16 +0000612 // Blocks that have already been added to WorkList as live-out.
613 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
614
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000615 // Visit all instructions reading li->reg.
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000616 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(li->reg);
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000617 MachineInstr *UseMI = I.skipInstruction();) {
618 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
619 continue;
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000620 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
Jakob Stoklund Olesen97769fc2012-05-20 02:54:52 +0000621 LiveRangeQuery LRQ(*li, Idx);
622 VNInfo *VNI = LRQ.valueIn();
Jakob Stoklund Olesen9ef931e2011-03-18 03:06:04 +0000623 if (!VNI) {
624 // This shouldn't happen: readsVirtualRegister returns true, but there is
625 // no live value. It is likely caused by a target getting <undef> flags
626 // wrong.
627 DEBUG(dbgs() << Idx << '\t' << *UseMI
628 << "Warning: Instr claims to read non-existent value in "
629 << *li << '\n');
630 continue;
631 }
Jakob Stoklund Olesenf054e192011-11-14 18:45:38 +0000632 // Special case: An early-clobber tied operand reads and writes the
Jakob Stoklund Olesen97769fc2012-05-20 02:54:52 +0000633 // register one slot early.
634 if (VNInfo *DefVNI = LRQ.valueDefined())
635 Idx = DefVNI->def;
636
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000637 WorkList.push_back(std::make_pair(Idx, VNI));
638 }
639
640 // Create a new live interval with only minimal live segments per def.
641 LiveInterval NewLI(li->reg, 0);
642 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
643 I != E; ++I) {
644 VNInfo *VNI = *I;
645 if (VNI->isUnused())
646 continue;
Jakob Stoklund Olesen1f81e312011-11-13 22:42:13 +0000647 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000648 }
649
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000650 // Keep track of the PHIs that are in use.
651 SmallPtrSet<VNInfo*, 8> UsedPHIs;
652
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000653 // Extend intervals to reach all uses in WorkList.
654 while (!WorkList.empty()) {
655 SlotIndex Idx = WorkList.back().first;
656 VNInfo *VNI = WorkList.back().second;
657 WorkList.pop_back();
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000658 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000659 SlotIndex BlockStart = getMBBStartIdx(MBB);
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000660
661 // Extend the live range for VNI to be live at Idx.
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000662 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
Nick Lewycky4b11a702011-03-02 01:43:30 +0000663 (void)ExtVNI;
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000664 assert(ExtVNI == VNI && "Unexpected existing value number");
665 // Is this a PHIDef we haven't seen before?
Jakob Stoklund Olesenc29d9b32011-03-03 00:20:51 +0000666 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000667 continue;
668 // The PHI is live, make sure the predecessors are live-out.
669 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
670 PE = MBB->pred_end(); PI != PE; ++PI) {
Jakob Stoklund Olesen031432f2011-09-15 15:24:16 +0000671 if (!LiveOut.insert(*PI))
672 continue;
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000673 SlotIndex Stop = getMBBEndIdx(*PI);
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000674 // A predecessor is not required to have a live-out value for a PHI.
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000675 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000676 WorkList.push_back(std::make_pair(Stop, PVNI));
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000677 }
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000678 continue;
679 }
680
681 // VNI is live-in to MBB.
682 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000683 NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000684
685 // Make sure VNI is live-out from the predecessors.
686 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
687 PE = MBB->pred_end(); PI != PE; ++PI) {
Jakob Stoklund Olesen031432f2011-09-15 15:24:16 +0000688 if (!LiveOut.insert(*PI))
689 continue;
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000690 SlotIndex Stop = getMBBEndIdx(*PI);
691 assert(li->getVNInfoBefore(Stop) == VNI &&
692 "Wrong value out of predecessor");
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000693 WorkList.push_back(std::make_pair(Stop, VNI));
694 }
695 }
696
697 // Handle dead values.
Jakob Stoklund Olesen6a3dbd32011-03-17 20:37:07 +0000698 bool CanSeparate = false;
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000699 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
700 I != E; ++I) {
701 VNInfo *VNI = *I;
702 if (VNI->isUnused())
703 continue;
704 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
705 assert(LII != NewLI.end() && "Missing live range for PHI");
Jakob Stoklund Olesen1f81e312011-11-13 22:42:13 +0000706 if (LII->end != VNI->def.getDeadSlot())
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000707 continue;
Jakob Stoklund Olesena4d34732011-03-02 00:33:01 +0000708 if (VNI->isPHIDef()) {
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000709 // This is a dead PHI. Remove it.
Jakob Stoklund Olesenb2beac22012-08-03 20:59:32 +0000710 VNI->markUnused();
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000711 NewLI.removeRange(*LII);
Jakob Stoklund Olesen6a3dbd32011-03-17 20:37:07 +0000712 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
713 CanSeparate = true;
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000714 } else {
715 // This is a dead def. Make sure the instruction knows.
716 MachineInstr *MI = getInstructionFromIndex(VNI->def);
717 assert(MI && "No instruction defining live value");
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000718 MI->addRegisterDead(li->reg, TRI);
Jakob Stoklund Olesen0d8ccaa2011-03-07 23:29:10 +0000719 if (dead && MI->allDefsAreDead()) {
Jakob Stoklund Olesenc46570d2011-03-16 22:56:08 +0000720 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
Jakob Stoklund Olesen0d8ccaa2011-03-07 23:29:10 +0000721 dead->push_back(MI);
722 }
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000723 }
724 }
725
726 // Move the trimmed ranges back.
727 li->ranges.swap(NewLI.ranges);
Jakob Stoklund Olesenc46570d2011-03-16 22:56:08 +0000728 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
Jakob Stoklund Olesen6a3dbd32011-03-17 20:37:07 +0000729 return CanSeparate;
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000730}
731
732
Evan Chengf2fbca62007-11-12 06:35:08 +0000733//===----------------------------------------------------------------------===//
734// Register allocator hooks.
735//
736
Jakob Stoklund Olesene617ccb2012-09-06 18:15:18 +0000737void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
738 // Keep track of regunit ranges.
739 SmallVector<std::pair<LiveInterval*, LiveInterval::iterator>, 8> RU;
740
Jakob Stoklund Olesen12a7be92012-06-20 23:23:59 +0000741 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
742 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000743 if (MRI->reg_nodbg_empty(Reg))
Jakob Stoklund Olesen8a61da82011-02-08 21:13:03 +0000744 continue;
Jakob Stoklund Olesen12a7be92012-06-20 23:23:59 +0000745 LiveInterval *LI = &getInterval(Reg);
Jakob Stoklund Olesene617ccb2012-09-06 18:15:18 +0000746 if (LI->empty())
747 continue;
748
749 // Find the regunit intervals for the assigned register. They may overlap
750 // the virtual register live range, cancelling any kills.
751 RU.clear();
752 for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
753 ++Units) {
754 LiveInterval *RUInt = &getRegUnit(*Units);
755 if (RUInt->empty())
756 continue;
757 RU.push_back(std::make_pair(RUInt, RUInt->find(LI->begin()->end)));
758 }
Jakob Stoklund Olesen8a61da82011-02-08 21:13:03 +0000759
760 // Every instruction that kills Reg corresponds to a live range end point.
761 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
762 ++RI) {
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000763 // A block index indicates an MBB edge.
764 if (RI->end.isBlock())
Jakob Stoklund Olesen8a61da82011-02-08 21:13:03 +0000765 continue;
766 MachineInstr *MI = getInstructionFromIndex(RI->end);
767 if (!MI)
768 continue;
Jakob Stoklund Olesene617ccb2012-09-06 18:15:18 +0000769
770 // Check if any of the reguints are live beyond the end of RI. That could
771 // happen when a physreg is defined as a copy of a virtreg:
772 //
773 // %EAX = COPY %vreg5
774 // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
775 // BAR %EAX<kill>
776 //
777 // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
778 bool CancelKill = false;
779 for (unsigned u = 0, e = RU.size(); u != e; ++u) {
780 LiveInterval *RInt = RU[u].first;
781 LiveInterval::iterator &I = RU[u].second;
782 if (I == RInt->end())
783 continue;
784 I = RInt->advanceTo(I, RI->end);
785 if (I == RInt->end() || I->start >= RI->end)
786 continue;
787 // I is overlapping RI.
788 CancelKill = true;
789 break;
790 }
791 if (CancelKill)
792 MI->clearRegisterKills(Reg, NULL);
793 else
794 MI->addRegisterKilled(Reg, NULL);
Jakob Stoklund Olesen8a61da82011-02-08 21:13:03 +0000795 }
796 }
797}
798
Jakob Stoklund Olesenebf27502012-02-10 01:23:55 +0000799MachineBasicBlock*
800LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
801 // A local live range must be fully contained inside the block, meaning it is
802 // defined and killed at instructions, not at block boundaries. It is not
803 // live in or or out of any block.
804 //
805 // It is technically possible to have a PHI-defined live range identical to a
806 // single block, but we are going to return false in that case.
Lang Hames233a60e2009-11-03 23:52:08 +0000807
Jakob Stoklund Olesenebf27502012-02-10 01:23:55 +0000808 SlotIndex Start = LI.beginIndex();
809 if (Start.isBlock())
810 return NULL;
Lang Hames233a60e2009-11-03 23:52:08 +0000811
Jakob Stoklund Olesenebf27502012-02-10 01:23:55 +0000812 SlotIndex Stop = LI.endIndex();
813 if (Stop.isBlock())
814 return NULL;
Lang Hames233a60e2009-11-03 23:52:08 +0000815
Jakob Stoklund Olesenebf27502012-02-10 01:23:55 +0000816 // getMBBFromIndex doesn't need to search the MBB table when both indexes
817 // belong to proper instructions.
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000818 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
819 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
Jakob Stoklund Olesenebf27502012-02-10 01:23:55 +0000820 return MBB1 == MBB2 ? MBB1 : NULL;
Evan Cheng81a03822007-11-17 00:40:40 +0000821}
822
Jakob Stoklund Olesen0ab71032012-08-03 20:10:24 +0000823bool
824LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
825 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
826 I != E; ++I) {
827 const VNInfo *PHI = *I;
828 if (PHI->isUnused() || !PHI->isPHIDef())
829 continue;
830 const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
831 // Conservatively return true instead of scanning huge predecessor lists.
832 if (PHIMBB->pred_size() > 100)
833 return true;
834 for (MachineBasicBlock::const_pred_iterator
835 PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
836 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
837 return true;
838 }
839 return false;
840}
841
Jakob Stoklund Olesene5d90412010-03-01 20:59:38 +0000842float
843LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
844 // Limit the loop depth ridiculousness.
845 if (loopDepth > 200)
846 loopDepth = 200;
847
848 // The loop depth is used to roughly estimate the number of times the
849 // instruction is executed. Something like 10^d is simple, but will quickly
850 // overflow a float. This expression behaves like 10^d for small d, but is
851 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
852 // headroom before overflow.
NAKAMURA Takumidc5198b2011-03-31 12:11:33 +0000853 // By the way, powf() might be unavailable here. For consistency,
854 // We may take pow(double,double).
855 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
Jakob Stoklund Olesene5d90412010-03-01 20:59:38 +0000856
857 return (isDef + isUse) * lc;
858}
859
Owen Andersonc4dc1322008-06-05 17:15:43 +0000860LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
Lang Hamesffd13262009-07-09 03:57:02 +0000861 MachineInstr* startInst) {
Owen Andersonc4dc1322008-06-05 17:15:43 +0000862 LiveInterval& Interval = getOrCreateInterval(reg);
863 VNInfo* VN = Interval.getNextValue(
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000864 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000865 getVNInfoAllocator());
Lang Hames86511252009-09-04 20:41:11 +0000866 LiveRange LR(
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000867 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
Lang Hames74ab5ee2009-12-22 00:11:50 +0000868 getMBBEndIdx(startInst->getParent()), VN);
Owen Andersonc4dc1322008-06-05 17:15:43 +0000869 Interval.addRange(LR);
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000870
Owen Andersonc4dc1322008-06-05 17:15:43 +0000871 return LR;
872}
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +0000873
874
875//===----------------------------------------------------------------------===//
876// Register mask functions
877//===----------------------------------------------------------------------===//
878
879bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
880 BitVector &UsableRegs) {
881 if (LI.empty())
882 return false;
Jakob Stoklund Olesen9f10ac62012-02-10 01:31:31 +0000883 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
884
885 // Use a smaller arrays for local live ranges.
886 ArrayRef<SlotIndex> Slots;
887 ArrayRef<const uint32_t*> Bits;
888 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
889 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
890 Bits = getRegMaskBitsInBlock(MBB->getNumber());
891 } else {
892 Slots = getRegMaskSlots();
893 Bits = getRegMaskBits();
894 }
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +0000895
896 // We are going to enumerate all the register mask slots contained in LI.
897 // Start with a binary search of RegMaskSlots to find a starting point.
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +0000898 ArrayRef<SlotIndex>::iterator SlotI =
899 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
900 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
901
902 // No slots in range, LI begins after the last call.
903 if (SlotI == SlotE)
904 return false;
905
906 bool Found = false;
907 for (;;) {
908 assert(*SlotI >= LiveI->start);
909 // Loop over all slots overlapping this segment.
910 while (*SlotI < LiveI->end) {
911 // *SlotI overlaps LI. Collect mask bits.
912 if (!Found) {
913 // This is the first overlap. Initialize UsableRegs to all ones.
914 UsableRegs.clear();
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +0000915 UsableRegs.resize(TRI->getNumRegs(), true);
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +0000916 Found = true;
917 }
918 // Remove usable registers clobbered by this mask.
Jakob Stoklund Olesen9f10ac62012-02-10 01:31:31 +0000919 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +0000920 if (++SlotI == SlotE)
921 return Found;
922 }
923 // *SlotI is beyond the current LI segment.
924 LiveI = LI.advanceTo(LiveI, *SlotI);
925 if (LiveI == LiveE)
926 return Found;
927 // Advance SlotI until it overlaps.
928 while (*SlotI < LiveI->start)
929 if (++SlotI == SlotE)
930 return Found;
931 }
932}
Lang Hames3dc7c512012-02-17 18:44:18 +0000933
934//===----------------------------------------------------------------------===//
935// IntervalUpdate class.
936//===----------------------------------------------------------------------===//
937
Lang Hamesfd6d3212012-02-21 00:00:36 +0000938// HMEditor is a toolkit used by handleMove to trim or extend live intervals.
Lang Hames3dc7c512012-02-17 18:44:18 +0000939class LiveIntervals::HMEditor {
940private:
Lang Hamesecb50622012-02-17 23:43:40 +0000941 LiveIntervals& LIS;
942 const MachineRegisterInfo& MRI;
943 const TargetRegisterInfo& TRI;
944 SlotIndex NewIdx;
Lang Hames3dc7c512012-02-17 18:44:18 +0000945
Lang Hames55fed622012-02-19 03:00:30 +0000946 typedef std::pair<LiveInterval*, LiveRange*> IntRangePair;
947 typedef DenseSet<IntRangePair> RangeSet;
948
Lang Hames6aceab12012-02-19 07:13:05 +0000949 struct RegRanges {
950 LiveRange* Use;
951 LiveRange* EC;
952 LiveRange* Dead;
953 LiveRange* Def;
954 RegRanges() : Use(0), EC(0), Dead(0), Def(0) {}
955 };
956 typedef DenseMap<unsigned, RegRanges> BundleRanges;
957
Lang Hames3dc7c512012-02-17 18:44:18 +0000958public:
Lang Hamesecb50622012-02-17 23:43:40 +0000959 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
960 const TargetRegisterInfo& TRI, SlotIndex NewIdx)
961 : LIS(LIS), MRI(MRI), TRI(TRI), NewIdx(NewIdx) {}
Lang Hames3dc7c512012-02-17 18:44:18 +0000962
Lang Hames55fed622012-02-19 03:00:30 +0000963 // Update intervals for all operands of MI from OldIdx to NewIdx.
964 // This assumes that MI used to be at OldIdx, and now resides at
965 // NewIdx.
Lang Hames4586d252012-02-21 22:29:38 +0000966 void moveAllRangesFrom(MachineInstr* MI, SlotIndex OldIdx) {
Lang Hames6aceab12012-02-19 07:13:05 +0000967 assert(NewIdx != OldIdx && "No-op move? That's a bit strange.");
968
Lang Hames55fed622012-02-19 03:00:30 +0000969 // Collect the operands.
970 RangeSet Entering, Internal, Exiting;
Lang Hamesac027142012-02-19 03:09:55 +0000971 bool hasRegMaskOp = false;
972 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
Lang Hames55fed622012-02-19 03:00:30 +0000973
Andrew Trickf70af522012-03-21 04:12:16 +0000974 // To keep the LiveRanges valid within an interval, move the ranges closest
975 // to the destination first. This prevents ranges from overlapping, to that
976 // APIs like removeRange still work.
977 if (NewIdx < OldIdx) {
978 moveAllEnteringFrom(OldIdx, Entering);
979 moveAllInternalFrom(OldIdx, Internal);
980 moveAllExitingFrom(OldIdx, Exiting);
981 }
982 else {
983 moveAllExitingFrom(OldIdx, Exiting);
984 moveAllInternalFrom(OldIdx, Internal);
985 moveAllEnteringFrom(OldIdx, Entering);
986 }
Lang Hames55fed622012-02-19 03:00:30 +0000987
Lang Hamesac027142012-02-19 03:09:55 +0000988 if (hasRegMaskOp)
989 updateRegMaskSlots(OldIdx);
990
Lang Hames55fed622012-02-19 03:00:30 +0000991#ifndef NDEBUG
992 LIValidator validator;
Pete Cooper722b6f12012-04-18 20:29:17 +0000993 validator = std::for_each(Entering.begin(), Entering.end(), validator);
994 validator = std::for_each(Internal.begin(), Internal.end(), validator);
995 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
Lang Hames6aceab12012-02-19 07:13:05 +0000996 assert(validator.rangesOk() && "moveAllOperandsFrom broke liveness.");
Lang Hames55fed622012-02-19 03:00:30 +0000997#endif
998
Lang Hames3dc7c512012-02-17 18:44:18 +0000999 }
1000
Lang Hames4586d252012-02-21 22:29:38 +00001001 // Update intervals for all operands of MI to refer to BundleStart's
1002 // SlotIndex.
1003 void moveAllRangesInto(MachineInstr* MI, MachineInstr* BundleStart) {
Lang Hames6aceab12012-02-19 07:13:05 +00001004 if (MI == BundleStart)
1005 return; // Bundling instr with itself - nothing to do.
1006
Lang Hamesfd6d3212012-02-21 00:00:36 +00001007 SlotIndex OldIdx = LIS.getSlotIndexes()->getInstructionIndex(MI);
1008 assert(LIS.getSlotIndexes()->getInstructionFromIndex(OldIdx) == MI &&
1009 "SlotIndex <-> Instruction mapping broken for MI");
1010
Lang Hames4586d252012-02-21 22:29:38 +00001011 // Collect all ranges already in the bundle.
1012 MachineBasicBlock::instr_iterator BII(BundleStart);
Lang Hames6aceab12012-02-19 07:13:05 +00001013 RangeSet Entering, Internal, Exiting;
1014 bool hasRegMaskOp = false;
Lang Hames4586d252012-02-21 22:29:38 +00001015 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
1016 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1017 for (++BII; &*BII == MI || BII->isInsideBundle(); ++BII) {
1018 if (&*BII == MI)
1019 continue;
1020 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
1021 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1022 }
1023
1024 BundleRanges BR = createBundleRanges(Entering, Internal, Exiting);
1025
Lang Hamesf905f692012-05-29 18:19:54 +00001026 Entering.clear();
1027 Internal.clear();
1028 Exiting.clear();
Lang Hames6aceab12012-02-19 07:13:05 +00001029 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
Lang Hames4586d252012-02-21 22:29:38 +00001030 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1031
1032 DEBUG(dbgs() << "Entering: " << Entering.size() << "\n");
1033 DEBUG(dbgs() << "Internal: " << Internal.size() << "\n");
1034 DEBUG(dbgs() << "Exiting: " << Exiting.size() << "\n");
Lang Hames6aceab12012-02-19 07:13:05 +00001035
1036 moveAllEnteringFromInto(OldIdx, Entering, BR);
1037 moveAllInternalFromInto(OldIdx, Internal, BR);
1038 moveAllExitingFromInto(OldIdx, Exiting, BR);
1039
Lang Hames4586d252012-02-21 22:29:38 +00001040
Lang Hames6aceab12012-02-19 07:13:05 +00001041#ifndef NDEBUG
1042 LIValidator validator;
Pete Cooper722b6f12012-04-18 20:29:17 +00001043 validator = std::for_each(Entering.begin(), Entering.end(), validator);
1044 validator = std::for_each(Internal.begin(), Internal.end(), validator);
1045 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
Lang Hames6aceab12012-02-19 07:13:05 +00001046 assert(validator.rangesOk() && "moveAllOperandsInto broke liveness.");
1047#endif
1048 }
1049
Lang Hames55fed622012-02-19 03:00:30 +00001050private:
Lang Hames3dc7c512012-02-17 18:44:18 +00001051
Lang Hames55fed622012-02-19 03:00:30 +00001052#ifndef NDEBUG
1053 class LIValidator {
1054 private:
1055 DenseSet<const LiveInterval*> Checked, Bogus;
1056 public:
1057 void operator()(const IntRangePair& P) {
1058 const LiveInterval* LI = P.first;
1059 if (Checked.count(LI))
1060 return;
1061 Checked.insert(LI);
1062 if (LI->empty())
1063 return;
1064 SlotIndex LastEnd = LI->begin()->start;
1065 for (LiveInterval::const_iterator LRI = LI->begin(), LRE = LI->end();
1066 LRI != LRE; ++LRI) {
1067 const LiveRange& LR = *LRI;
1068 if (LastEnd > LR.start || LR.start >= LR.end)
1069 Bogus.insert(LI);
1070 LastEnd = LR.end;
Lang Hames3dc7c512012-02-17 18:44:18 +00001071 }
1072 }
Lang Hames3dc7c512012-02-17 18:44:18 +00001073
Lang Hames55fed622012-02-19 03:00:30 +00001074 bool rangesOk() const {
1075 return Bogus.empty();
Lang Hames3dc7c512012-02-17 18:44:18 +00001076 }
Lang Hames55fed622012-02-19 03:00:30 +00001077 };
1078#endif
Lang Hames3dc7c512012-02-17 18:44:18 +00001079
Lang Hames55fed622012-02-19 03:00:30 +00001080 // Collect IntRangePairs for all operands of MI that may need fixing.
1081 // Treat's MI's index as OldIdx (regardless of what it is in SlotIndexes'
1082 // maps).
1083 void collectRanges(MachineInstr* MI, RangeSet& Entering, RangeSet& Internal,
Lang Hamesac027142012-02-19 03:09:55 +00001084 RangeSet& Exiting, bool& hasRegMaskOp, SlotIndex OldIdx) {
1085 hasRegMaskOp = false;
Lang Hamesecb50622012-02-17 23:43:40 +00001086 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
1087 MOE = MI->operands_end();
1088 MOI != MOE; ++MOI) {
1089 const MachineOperand& MO = *MOI;
Lang Hamesac027142012-02-19 03:09:55 +00001090
1091 if (MO.isRegMask()) {
1092 hasRegMaskOp = true;
1093 continue;
1094 }
1095
Lang Hamesecb50622012-02-17 23:43:40 +00001096 if (!MO.isReg() || MO.getReg() == 0)
Lang Hames3dc7c512012-02-17 18:44:18 +00001097 continue;
1098
Lang Hamesecb50622012-02-17 23:43:40 +00001099 unsigned Reg = MO.getReg();
Lang Hames3dc7c512012-02-17 18:44:18 +00001100
1101 // TODO: Currently we're skipping uses that are reserved or have no
1102 // interval, but we're not updating their kills. This should be
1103 // fixed.
Jakob Stoklund Olesenbf833f02012-06-19 23:50:18 +00001104 if (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg))
Lang Hames3dc7c512012-02-17 18:44:18 +00001105 continue;
1106
Jakob Stoklund Olesen78241522012-06-20 18:00:57 +00001107 // Collect ranges for register units. These live ranges are computed on
1108 // demand, so just skip any that haven't been computed yet.
Jakob Stoklund Olesene0248742012-06-22 18:38:57 +00001109 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
Jakob Stoklund Olesen78241522012-06-20 18:00:57 +00001110 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
1111 if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))
1112 collectRanges(MO, LI, Entering, Internal, Exiting, OldIdx);
Jakob Stoklund Olesene0248742012-06-22 18:38:57 +00001113 } else {
1114 // Collect ranges for individual virtual registers.
Jakob Stoklund Olesenbf833f02012-06-19 23:50:18 +00001115 collectRanges(MO, &LIS.getInterval(Reg),
1116 Entering, Internal, Exiting, OldIdx);
Jakob Stoklund Olesene0248742012-06-22 18:38:57 +00001117 }
Jakob Stoklund Olesenbf833f02012-06-19 23:50:18 +00001118 }
1119 }
Lang Hames55fed622012-02-19 03:00:30 +00001120
Jakob Stoklund Olesenbf833f02012-06-19 23:50:18 +00001121 void collectRanges(const MachineOperand &MO, LiveInterval *LI,
1122 RangeSet &Entering, RangeSet &Internal, RangeSet &Exiting,
1123 SlotIndex OldIdx) {
1124 if (MO.readsReg()) {
1125 LiveRange* LR = LI->getLiveRangeContaining(OldIdx);
1126 if (LR != 0)
1127 Entering.insert(std::make_pair(LI, LR));
1128 }
1129 if (MO.isDef()) {
1130 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot());
1131 assert(LR != 0 && "No live range for def?");
1132 if (LR->end > OldIdx.getDeadSlot())
1133 Exiting.insert(std::make_pair(LI, LR));
1134 else
1135 Internal.insert(std::make_pair(LI, LR));
Lang Hames3dc7c512012-02-17 18:44:18 +00001136 }
Lang Hames3dc7c512012-02-17 18:44:18 +00001137 }
1138
Jakob Stoklund Olesenfa8becb2012-06-19 22:50:53 +00001139 BundleRanges createBundleRanges(RangeSet& Entering,
1140 RangeSet& Internal,
1141 RangeSet& Exiting) {
Lang Hames4586d252012-02-21 22:29:38 +00001142 BundleRanges BR;
Lang Hames6aceab12012-02-19 07:13:05 +00001143
1144 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
Lang Hamesfd6d3212012-02-21 00:00:36 +00001145 EI != EE; ++EI) {
Lang Hames6aceab12012-02-19 07:13:05 +00001146 LiveInterval* LI = EI->first;
1147 LiveRange* LR = EI->second;
1148 BR[LI->reg].Use = LR;
1149 }
1150
1151 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
Lang Hamesfd6d3212012-02-21 00:00:36 +00001152 II != IE; ++II) {
Lang Hames6aceab12012-02-19 07:13:05 +00001153 LiveInterval* LI = II->first;
1154 LiveRange* LR = II->second;
1155 if (LR->end.isDead()) {
1156 BR[LI->reg].Dead = LR;
1157 } else {
1158 BR[LI->reg].EC = LR;
1159 }
1160 }
1161
1162 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
Lang Hamesfd6d3212012-02-21 00:00:36 +00001163 EI != EE; ++EI) {
Lang Hames6aceab12012-02-19 07:13:05 +00001164 LiveInterval* LI = EI->first;
1165 LiveRange* LR = EI->second;
1166 BR[LI->reg].Def = LR;
1167 }
1168
1169 return BR;
1170 }
1171
Lang Hamesecb50622012-02-17 23:43:40 +00001172 void moveKillFlags(unsigned reg, SlotIndex OldIdx, SlotIndex newKillIdx) {
1173 MachineInstr* OldKillMI = LIS.getInstructionFromIndex(OldIdx);
1174 if (!OldKillMI->killsRegister(reg))
Lang Hames3dc7c512012-02-17 18:44:18 +00001175 return; // Bail out if we don't have kill flags on the old register.
Lang Hamesecb50622012-02-17 23:43:40 +00001176 MachineInstr* NewKillMI = LIS.getInstructionFromIndex(newKillIdx);
1177 assert(OldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
Jakob Stoklund Olesenfa8becb2012-06-19 22:50:53 +00001178 assert(!NewKillMI->killsRegister(reg) &&
1179 "New kill instr is already a kill.");
Lang Hamesecb50622012-02-17 23:43:40 +00001180 OldKillMI->clearRegisterKills(reg, &TRI);
1181 NewKillMI->addRegisterKilled(reg, &TRI);
Lang Hames3dc7c512012-02-17 18:44:18 +00001182 }
1183
Lang Hamesecb50622012-02-17 23:43:40 +00001184 void updateRegMaskSlots(SlotIndex OldIdx) {
1185 SmallVectorImpl<SlotIndex>::iterator RI =
1186 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1187 OldIdx);
1188 assert(*RI == OldIdx && "No RegMask at OldIdx.");
1189 *RI = NewIdx;
1190 assert(*prior(RI) < *RI && *RI < *next(RI) &&
Lang Hamesfbc8dd32012-02-17 21:29:41 +00001191 "RegSlots out of order. Did you move one call across another?");
1192 }
Lang Hames55fed622012-02-19 03:00:30 +00001193
1194 // Return the last use of reg between NewIdx and OldIdx.
1195 SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {
1196 SlotIndex LastUse = NewIdx;
1197 for (MachineRegisterInfo::use_nodbg_iterator
1198 UI = MRI.use_nodbg_begin(Reg),
1199 UE = MRI.use_nodbg_end();
Lang Hames038d2d52012-02-19 04:38:25 +00001200 UI != UE; UI.skipInstruction()) {
Lang Hames55fed622012-02-19 03:00:30 +00001201 const MachineInstr* MI = &*UI;
1202 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1203 if (InstSlot > LastUse && InstSlot < OldIdx)
1204 LastUse = InstSlot;
1205 }
1206 return LastUse;
1207 }
1208
1209 void moveEnteringUpFrom(SlotIndex OldIdx, IntRangePair& P) {
1210 LiveInterval* LI = P.first;
1211 LiveRange* LR = P.second;
1212 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1213 if (LiveThrough)
1214 return;
1215 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1216 if (LastUse != NewIdx)
1217 moveKillFlags(LI->reg, NewIdx, LastUse);
Lang Hames7b23d082012-09-03 06:31:45 +00001218 LR->end = LastUse.getRegSlot(LR->end.isEarlyClobber());
Lang Hames55fed622012-02-19 03:00:30 +00001219 }
1220
1221 void moveEnteringDownFrom(SlotIndex OldIdx, IntRangePair& P) {
1222 LiveInterval* LI = P.first;
1223 LiveRange* LR = P.second;
Andrew Tricke0b51ab2012-03-21 04:12:01 +00001224 // Extend the LiveRange if NewIdx is past the end.
Lang Hames4a0b2d62012-02-19 06:13:56 +00001225 if (NewIdx > LR->end) {
Andrew Tricke0b51ab2012-03-21 04:12:01 +00001226 // Move kill flags if OldIdx was not originally the end
1227 // (otherwise LR->end points to an invalid slot).
1228 if (LR->end.getRegSlot() != OldIdx.getRegSlot()) {
1229 assert(LR->end > OldIdx && "LiveRange does not cover original slot");
1230 moveKillFlags(LI->reg, LR->end, NewIdx);
1231 }
Lang Hames7b23d082012-09-03 06:31:45 +00001232 LR->end = NewIdx.getRegSlot(LR->end.isEarlyClobber());
Lang Hames55fed622012-02-19 03:00:30 +00001233 }
1234 }
1235
1236 void moveAllEnteringFrom(SlotIndex OldIdx, RangeSet& Entering) {
1237 bool GoingUp = NewIdx < OldIdx;
1238
1239 if (GoingUp) {
1240 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1241 EI != EE; ++EI)
1242 moveEnteringUpFrom(OldIdx, *EI);
1243 } else {
1244 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1245 EI != EE; ++EI)
1246 moveEnteringDownFrom(OldIdx, *EI);
1247 }
1248 }
1249
1250 void moveInternalFrom(SlotIndex OldIdx, IntRangePair& P) {
1251 LiveInterval* LI = P.first;
1252 LiveRange* LR = P.second;
1253 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1254 LR->end <= OldIdx.getDeadSlot() &&
1255 "Range should be internal to OldIdx.");
1256 LiveRange Tmp(*LR);
1257 Tmp.start = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1258 Tmp.valno->def = Tmp.start;
1259 Tmp.end = LR->end.isDead() ? NewIdx.getDeadSlot() : NewIdx.getRegSlot();
1260 LI->removeRange(*LR);
1261 LI->addRange(Tmp);
1262 }
1263
1264 void moveAllInternalFrom(SlotIndex OldIdx, RangeSet& Internal) {
1265 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1266 II != IE; ++II)
1267 moveInternalFrom(OldIdx, *II);
1268 }
1269
1270 void moveExitingFrom(SlotIndex OldIdx, IntRangePair& P) {
1271 LiveRange* LR = P.second;
1272 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1273 "Range should start in OldIdx.");
1274 assert(LR->end > OldIdx.getDeadSlot() && "Range should exit OldIdx.");
1275 SlotIndex NewStart = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1276 LR->start = NewStart;
1277 LR->valno->def = NewStart;
1278 }
1279
1280 void moveAllExitingFrom(SlotIndex OldIdx, RangeSet& Exiting) {
1281 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1282 EI != EE; ++EI)
1283 moveExitingFrom(OldIdx, *EI);
1284 }
1285
Lang Hames6aceab12012-02-19 07:13:05 +00001286 void moveEnteringUpFromInto(SlotIndex OldIdx, IntRangePair& P,
1287 BundleRanges& BR) {
1288 LiveInterval* LI = P.first;
1289 LiveRange* LR = P.second;
1290 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1291 if (LiveThrough) {
1292 assert((LR->start < NewIdx || BR[LI->reg].Def == LR) &&
1293 "Def in bundle should be def range.");
1294 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1295 "If bundle has use for this reg it should be LR.");
1296 BR[LI->reg].Use = LR;
1297 return;
1298 }
1299
1300 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
Lang Hamesfd6d3212012-02-21 00:00:36 +00001301 moveKillFlags(LI->reg, OldIdx, LastUse);
Lang Hames6aceab12012-02-19 07:13:05 +00001302
1303 if (LR->start < NewIdx) {
1304 // Becoming a new entering range.
1305 assert(BR[LI->reg].Dead == 0 && BR[LI->reg].Def == 0 &&
1306 "Bundle shouldn't be re-defining reg mid-range.");
Benjamin Kramer7db76e72012-02-19 12:25:07 +00001307 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
Lang Hames6aceab12012-02-19 07:13:05 +00001308 "Bundle shouldn't have different use range for same reg.");
1309 LR->end = LastUse.getRegSlot();
1310 BR[LI->reg].Use = LR;
1311 } else {
1312 // Becoming a new Dead-def.
1313 assert(LR->start == NewIdx.getRegSlot(LR->start.isEarlyClobber()) &&
1314 "Live range starting at unexpected slot.");
1315 assert(BR[LI->reg].Def == LR && "Reg should have def range.");
1316 assert(BR[LI->reg].Dead == 0 &&
1317 "Can't have def and dead def of same reg in a bundle.");
1318 LR->end = LastUse.getDeadSlot();
1319 BR[LI->reg].Dead = BR[LI->reg].Def;
1320 BR[LI->reg].Def = 0;
1321 }
1322 }
1323
1324 void moveEnteringDownFromInto(SlotIndex OldIdx, IntRangePair& P,
1325 BundleRanges& BR) {
1326 LiveInterval* LI = P.first;
1327 LiveRange* LR = P.second;
1328 if (NewIdx > LR->end) {
1329 // Range extended to bundle. Add to bundle uses.
1330 // Note: Currently adds kill flags to bundle start.
1331 assert(BR[LI->reg].Use == 0 &&
1332 "Bundle already has use range for reg.");
1333 moveKillFlags(LI->reg, LR->end, NewIdx);
1334 LR->end = NewIdx.getRegSlot();
1335 BR[LI->reg].Use = LR;
1336 } else {
1337 assert(BR[LI->reg].Use != 0 &&
1338 "Bundle should already have a use range for reg.");
1339 }
1340 }
1341
1342 void moveAllEnteringFromInto(SlotIndex OldIdx, RangeSet& Entering,
1343 BundleRanges& BR) {
1344 bool GoingUp = NewIdx < OldIdx;
1345
1346 if (GoingUp) {
1347 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1348 EI != EE; ++EI)
1349 moveEnteringUpFromInto(OldIdx, *EI, BR);
1350 } else {
1351 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1352 EI != EE; ++EI)
1353 moveEnteringDownFromInto(OldIdx, *EI, BR);
1354 }
1355 }
1356
1357 void moveInternalFromInto(SlotIndex OldIdx, IntRangePair& P,
1358 BundleRanges& BR) {
1359 // TODO: Sane rules for moving ranges into bundles.
1360 }
1361
1362 void moveAllInternalFromInto(SlotIndex OldIdx, RangeSet& Internal,
1363 BundleRanges& BR) {
1364 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1365 II != IE; ++II)
1366 moveInternalFromInto(OldIdx, *II, BR);
1367 }
1368
1369 void moveExitingFromInto(SlotIndex OldIdx, IntRangePair& P,
1370 BundleRanges& BR) {
1371 LiveInterval* LI = P.first;
1372 LiveRange* LR = P.second;
1373
1374 assert(LR->start.isRegister() &&
1375 "Don't know how to merge exiting ECs into bundles yet.");
1376
1377 if (LR->end > NewIdx.getDeadSlot()) {
1378 // This range is becoming an exiting range on the bundle.
1379 // If there was an old dead-def of this reg, delete it.
1380 if (BR[LI->reg].Dead != 0) {
1381 LI->removeRange(*BR[LI->reg].Dead);
1382 BR[LI->reg].Dead = 0;
1383 }
1384 assert(BR[LI->reg].Def == 0 &&
1385 "Can't have two defs for the same variable exiting a bundle.");
1386 LR->start = NewIdx.getRegSlot();
1387 LR->valno->def = LR->start;
1388 BR[LI->reg].Def = LR;
1389 } else {
1390 // This range is becoming internal to the bundle.
1391 assert(LR->end == NewIdx.getRegSlot() &&
1392 "Can't bundle def whose kill is before the bundle");
1393 if (BR[LI->reg].Dead || BR[LI->reg].Def) {
1394 // Already have a def for this. Just delete range.
1395 LI->removeRange(*LR);
1396 } else {
1397 // Make range dead, record.
1398 LR->end = NewIdx.getDeadSlot();
1399 BR[LI->reg].Dead = LR;
1400 assert(BR[LI->reg].Use == LR &&
1401 "Range becoming dead should currently be use.");
1402 }
1403 // In both cases the range is no longer a use on the bundle.
1404 BR[LI->reg].Use = 0;
1405 }
1406 }
1407
1408 void moveAllExitingFromInto(SlotIndex OldIdx, RangeSet& Exiting,
1409 BundleRanges& BR) {
1410 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1411 EI != EE; ++EI)
1412 moveExitingFromInto(OldIdx, *EI, BR);
1413 }
1414
Lang Hames3dc7c512012-02-17 18:44:18 +00001415};
1416
Lang Hamesecb50622012-02-17 23:43:40 +00001417void LiveIntervals::handleMove(MachineInstr* MI) {
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +00001418 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1419 Indexes->removeMachineInstrFromMaps(MI);
Lang Hamesecb50622012-02-17 23:43:40 +00001420 SlotIndex NewIndex = MI->isInsideBundle() ?
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +00001421 Indexes->getInstructionIndex(MI) :
1422 Indexes->insertMachineInstrInMaps(MI);
Lang Hamesecb50622012-02-17 23:43:40 +00001423 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1424 OldIndex < getMBBEndIdx(MI->getParent()) &&
Lang Hames3dc7c512012-02-17 18:44:18 +00001425 "Cannot handle moves across basic block boundaries.");
Lang Hamesecb50622012-02-17 23:43:40 +00001426 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
Lang Hames3dc7c512012-02-17 18:44:18 +00001427
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +00001428 HMEditor HME(*this, *MRI, *TRI, NewIndex);
Lang Hames4586d252012-02-21 22:29:38 +00001429 HME.moveAllRangesFrom(MI, OldIndex);
1430}
1431
Jakob Stoklund Olesenfa8becb2012-06-19 22:50:53 +00001432void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1433 MachineInstr* BundleStart) {
Jakob Stoklund Olesen15f1d8c2012-06-04 22:39:14 +00001434 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1435 HMEditor HME(*this, *MRI, *TRI, NewIndex);
Lang Hames4586d252012-02-21 22:29:38 +00001436 HME.moveAllRangesInto(MI, BundleStart);
Lang Hames3dc7c512012-02-17 18:44:18 +00001437}