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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 7f354557089d93cc681c440f9e064c906e1fbd58 / . / lib / CodeGen / SelectionDAG / TargetLowering.cpp
blob: 82a91de2bbc9edcb8e4baae2a24e1e7d7cd7cc5f [file] [log] [blame]
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]2//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]7//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
Chris Lattneraf76e592009-08-22 20:48:53 +0000[diff] [blame]15#include "llvm/MC/MCAsmInfo.h"
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]16#include "llvm/MC/MCExpr.h"
Owen Anderson07000c62006-05-12 06:33:49 +0000[diff] [blame]17#include "llvm/Target/TargetData.h"
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]18#include "llvm/Target/TargetLoweringObjectFile.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]19#include "llvm/Target/TargetMachine.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]20#include "llvm/Target/TargetRegisterInfo.h"
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]21#include "llvm/GlobalVariable.h"
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]22#include "llvm/DerivedTypes.h"
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]23#include "llvm/CodeGen/Analysis.h"
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]25#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]26#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]27#include "llvm/CodeGen/SelectionDAG.h"
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]28#include "llvm/ADT/STLExtras.h"
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]29#include "llvm/Support/CommandLine.h"
Torok Edwinc25e7582009-07-11 20:10:48 +0000[diff] [blame]30#include "llvm/Support/ErrorHandling.h"
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]31#include "llvm/Support/MathExtras.h"
Nick Lewycky476b2422010-12-19 20:43:38 +0000[diff] [blame]32#include <cctype>
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]33using namespace llvm;
34
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]35/// We are in the process of implementing a new TypeLegalization action
36/// - the promotion of vector elements. This feature is disabled by default
37/// and only enabled using this flag.
38static cl::opt<bool>
Nadav Rotem8fb06b32011-10-16 20:31:33 +0000[diff] [blame]39AllowPromoteIntElem("promote-elements", cl::Hidden, cl::init(true),
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]40 cl::desc("Allow promotion of integer vector element types"));
41
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]42/// InitLibcallNames - Set default libcall names.
43///
Evan Cheng79cca502007-01-12 22:51:10 +0000[diff] [blame]44static void InitLibcallNames(const char **Names) {
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]45 Names[RTLIB::SHL_I16] = "__ashlhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]46 Names[RTLIB::SHL_I32] = "__ashlsi3";
47 Names[RTLIB::SHL_I64] = "__ashldi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]48 Names[RTLIB::SHL_I128] = "__ashlti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]49 Names[RTLIB::SRL_I16] = "__lshrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]50 Names[RTLIB::SRL_I32] = "__lshrsi3";
51 Names[RTLIB::SRL_I64] = "__lshrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]52 Names[RTLIB::SRL_I128] = "__lshrti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]53 Names[RTLIB::SRA_I16] = "__ashrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]54 Names[RTLIB::SRA_I32] = "__ashrsi3";
55 Names[RTLIB::SRA_I64] = "__ashrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]56 Names[RTLIB::SRA_I128] = "__ashrti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]57 Names[RTLIB::MUL_I8] = "__mulqi3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]58 Names[RTLIB::MUL_I16] = "__mulhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]59 Names[RTLIB::MUL_I32] = "__mulsi3";
60 Names[RTLIB::MUL_I64] = "__muldi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]61 Names[RTLIB::MUL_I128] = "__multi3";
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]62 Names[RTLIB::MULO_I32] = "__mulosi4";
63 Names[RTLIB::MULO_I64] = "__mulodi4";
64 Names[RTLIB::MULO_I128] = "__muloti4";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]65 Names[RTLIB::SDIV_I8] = "__divqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]66 Names[RTLIB::SDIV_I16] = "__divhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]67 Names[RTLIB::SDIV_I32] = "__divsi3";
68 Names[RTLIB::SDIV_I64] = "__divdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]69 Names[RTLIB::SDIV_I128] = "__divti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]70 Names[RTLIB::UDIV_I8] = "__udivqi3";
Anton Korobeynikovfb3f84f2009-05-08 18:50:54 +0000[diff] [blame]71 Names[RTLIB::UDIV_I16] = "__udivhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]72 Names[RTLIB::UDIV_I32] = "__udivsi3";
73 Names[RTLIB::UDIV_I64] = "__udivdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]74 Names[RTLIB::UDIV_I128] = "__udivti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]75 Names[RTLIB::SREM_I8] = "__modqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]76 Names[RTLIB::SREM_I16] = "__modhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]77 Names[RTLIB::SREM_I32] = "__modsi3";
78 Names[RTLIB::SREM_I64] = "__moddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]79 Names[RTLIB::SREM_I128] = "__modti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]80 Names[RTLIB::UREM_I8] = "__umodqi3";
Anton Korobeynikov9fe9c8e2009-05-03 13:19:57 +0000[diff] [blame]81 Names[RTLIB::UREM_I16] = "__umodhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]82 Names[RTLIB::UREM_I32] = "__umodsi3";
83 Names[RTLIB::UREM_I64] = "__umoddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]84 Names[RTLIB::UREM_I128] = "__umodti3";
Evan Cheng8e23e812011-04-01 00:42:02 +0000[diff] [blame]85
86 // These are generally not available.
87 Names[RTLIB::SDIVREM_I8] = 0;
88 Names[RTLIB::SDIVREM_I16] = 0;
89 Names[RTLIB::SDIVREM_I32] = 0;
90 Names[RTLIB::SDIVREM_I64] = 0;
91 Names[RTLIB::SDIVREM_I128] = 0;
92 Names[RTLIB::UDIVREM_I8] = 0;
93 Names[RTLIB::UDIVREM_I16] = 0;
94 Names[RTLIB::UDIVREM_I32] = 0;
95 Names[RTLIB::UDIVREM_I64] = 0;
96 Names[RTLIB::UDIVREM_I128] = 0;
97
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]98 Names[RTLIB::NEG_I32] = "__negsi2";
99 Names[RTLIB::NEG_I64] = "__negdi2";
100 Names[RTLIB::ADD_F32] = "__addsf3";
101 Names[RTLIB::ADD_F64] = "__adddf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]102 Names[RTLIB::ADD_F80] = "__addxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]103 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]104 Names[RTLIB::SUB_F32] = "__subsf3";
105 Names[RTLIB::SUB_F64] = "__subdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]106 Names[RTLIB::SUB_F80] = "__subxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]107 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]108 Names[RTLIB::MUL_F32] = "__mulsf3";
109 Names[RTLIB::MUL_F64] = "__muldf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]110 Names[RTLIB::MUL_F80] = "__mulxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]111 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]112 Names[RTLIB::DIV_F32] = "__divsf3";
113 Names[RTLIB::DIV_F64] = "__divdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]114 Names[RTLIB::DIV_F80] = "__divxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]115 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]116 Names[RTLIB::REM_F32] = "fmodf";
117 Names[RTLIB::REM_F64] = "fmod";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]118 Names[RTLIB::REM_F80] = "fmodl";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]119 Names[RTLIB::REM_PPCF128] = "fmodl";
Cameron Zwarich33390842011-07-08 21:39:21 +0000[diff] [blame]120 Names[RTLIB::FMA_F32] = "fmaf";
121 Names[RTLIB::FMA_F64] = "fma";
122 Names[RTLIB::FMA_F80] = "fmal";
123 Names[RTLIB::FMA_PPCF128] = "fmal";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]124 Names[RTLIB::POWI_F32] = "__powisf2";
125 Names[RTLIB::POWI_F64] = "__powidf2";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]126 Names[RTLIB::POWI_F80] = "__powixf2";
127 Names[RTLIB::POWI_PPCF128] = "__powitf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]128 Names[RTLIB::SQRT_F32] = "sqrtf";
129 Names[RTLIB::SQRT_F64] = "sqrt";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]130 Names[RTLIB::SQRT_F80] = "sqrtl";
131 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000[diff] [blame]132 Names[RTLIB::LOG_F32] = "logf";
133 Names[RTLIB::LOG_F64] = "log";
134 Names[RTLIB::LOG_F80] = "logl";
135 Names[RTLIB::LOG_PPCF128] = "logl";
136 Names[RTLIB::LOG2_F32] = "log2f";
137 Names[RTLIB::LOG2_F64] = "log2";
138 Names[RTLIB::LOG2_F80] = "log2l";
139 Names[RTLIB::LOG2_PPCF128] = "log2l";
140 Names[RTLIB::LOG10_F32] = "log10f";
141 Names[RTLIB::LOG10_F64] = "log10";
142 Names[RTLIB::LOG10_F80] = "log10l";
143 Names[RTLIB::LOG10_PPCF128] = "log10l";
144 Names[RTLIB::EXP_F32] = "expf";
145 Names[RTLIB::EXP_F64] = "exp";
146 Names[RTLIB::EXP_F80] = "expl";
147 Names[RTLIB::EXP_PPCF128] = "expl";
148 Names[RTLIB::EXP2_F32] = "exp2f";
149 Names[RTLIB::EXP2_F64] = "exp2";
150 Names[RTLIB::EXP2_F80] = "exp2l";
151 Names[RTLIB::EXP2_PPCF128] = "exp2l";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]152 Names[RTLIB::SIN_F32] = "sinf";
153 Names[RTLIB::SIN_F64] = "sin";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]154 Names[RTLIB::SIN_F80] = "sinl";
155 Names[RTLIB::SIN_PPCF128] = "sinl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]156 Names[RTLIB::COS_F32] = "cosf";
157 Names[RTLIB::COS_F64] = "cos";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]158 Names[RTLIB::COS_F80] = "cosl";
159 Names[RTLIB::COS_PPCF128] = "cosl";
Dan Gohmane54be102007-10-11 23:09:10 +0000[diff] [blame]160 Names[RTLIB::POW_F32] = "powf";
161 Names[RTLIB::POW_F64] = "pow";
162 Names[RTLIB::POW_F80] = "powl";
163 Names[RTLIB::POW_PPCF128] = "powl";
Dan Gohman2bb1e3e2008-08-21 18:38:14 +0000[diff] [blame]164 Names[RTLIB::CEIL_F32] = "ceilf";
165 Names[RTLIB::CEIL_F64] = "ceil";
166 Names[RTLIB::CEIL_F80] = "ceill";
167 Names[RTLIB::CEIL_PPCF128] = "ceill";
168 Names[RTLIB::TRUNC_F32] = "truncf";
169 Names[RTLIB::TRUNC_F64] = "trunc";
170 Names[RTLIB::TRUNC_F80] = "truncl";
171 Names[RTLIB::TRUNC_PPCF128] = "truncl";
172 Names[RTLIB::RINT_F32] = "rintf";
173 Names[RTLIB::RINT_F64] = "rint";
174 Names[RTLIB::RINT_F80] = "rintl";
175 Names[RTLIB::RINT_PPCF128] = "rintl";
176 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
177 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
178 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
179 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
180 Names[RTLIB::FLOOR_F32] = "floorf";
181 Names[RTLIB::FLOOR_F64] = "floor";
182 Names[RTLIB::FLOOR_F80] = "floorl";
183 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Duncan Sandsd2c817e2010-03-14 21:08:40 +0000[diff] [blame]184 Names[RTLIB::COPYSIGN_F32] = "copysignf";
185 Names[RTLIB::COPYSIGN_F64] = "copysign";
186 Names[RTLIB::COPYSIGN_F80] = "copysignl";
187 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]188 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]189 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
190 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]191 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]192 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
193 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
194 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
195 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]196 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
197 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]198 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
199 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]200 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]201 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
202 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]203 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
204 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]205 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
Duncan Sandsbe1ad4d2008-07-10 15:33:02 +0000[diff] [blame]206 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]207 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]208 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]209 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]210 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]211 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]212 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
213 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]214 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
215 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]216 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]217 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
218 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]219 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
220 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]221 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]222 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
223 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]224 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]225 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]226 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]227 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]228 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
229 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
Duncan Sands9bed0f52008-07-11 16:57:02 +0000[diff] [blame]230 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
231 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]232 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
233 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]234 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
235 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
Dan Gohmand91446d2008-03-05 01:08:17 +0000[diff] [blame]236 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
237 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
238 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
239 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]240 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
241 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]242 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
243 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]244 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
245 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]246 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
247 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
248 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
249 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
250 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
251 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]252 Names[RTLIB::OEQ_F32] = "__eqsf2";
253 Names[RTLIB::OEQ_F64] = "__eqdf2";
254 Names[RTLIB::UNE_F32] = "__nesf2";
255 Names[RTLIB::UNE_F64] = "__nedf2";
256 Names[RTLIB::OGE_F32] = "__gesf2";
257 Names[RTLIB::OGE_F64] = "__gedf2";
258 Names[RTLIB::OLT_F32] = "__ltsf2";
259 Names[RTLIB::OLT_F64] = "__ltdf2";
260 Names[RTLIB::OLE_F32] = "__lesf2";
261 Names[RTLIB::OLE_F64] = "__ledf2";
262 Names[RTLIB::OGT_F32] = "__gtsf2";
263 Names[RTLIB::OGT_F64] = "__gtdf2";
264 Names[RTLIB::UO_F32] = "__unordsf2";
265 Names[RTLIB::UO_F64] = "__unorddf2";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]266 Names[RTLIB::O_F32] = "__unordsf2";
267 Names[RTLIB::O_F64] = "__unorddf2";
Sanjiv Guptaa114baa2009-07-30 09:12:56 +0000[diff] [blame]268 Names[RTLIB::MEMCPY] = "memcpy";
269 Names[RTLIB::MEMMOVE] = "memmove";
270 Names[RTLIB::MEMSET] = "memset";
Duncan Sandsb0f1e172009-05-22 20:36:31 +0000[diff] [blame]271 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]272 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
273 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
274 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
275 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
Jim Grosbachef6eb9c2010-06-18 23:03:10 +0000[diff] [blame]276 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
277 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
278 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
279 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]280 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
281 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
282 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
283 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
284 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
285 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
286 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
287 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
288 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
289 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
290 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
291 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
292 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
293 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
294 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
295 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
296 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
297 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
Jim Grosbach312b7c92011-10-14 15:53:48 +0000[diff] [blame]298 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]299 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
300 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
301 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
302 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
303 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]304}
305
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]306/// InitLibcallCallingConvs - Set default libcall CallingConvs.
307///
308static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
309 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
310 CCs[i] = CallingConv::C;
311 }
312}
313
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]314/// getFPEXT - Return the FPEXT_*_* value for the given types, or
315/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]316RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]317 if (OpVT == MVT::f32) {
318 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]319 return FPEXT_F32_F64;
320 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]321
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]322 return UNKNOWN_LIBCALL;
323}
324
325/// getFPROUND - Return the FPROUND_*_* value for the given types, or
326/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]327RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]328 if (RetVT == MVT::f32) {
329 if (OpVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]330 return FPROUND_F64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]331 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]332 return FPROUND_F80_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]333 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]334 return FPROUND_PPCF128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]335 } else if (RetVT == MVT::f64) {
336 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]337 return FPROUND_F80_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]338 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]339 return FPROUND_PPCF128_F64;
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]340 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]341
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]342 return UNKNOWN_LIBCALL;
343}
344
345/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
346/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]347RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]348 if (OpVT == MVT::f32) {
349 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]350 return FPTOSINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]351 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]352 return FPTOSINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]353 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]354 return FPTOSINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]355 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]356 return FPTOSINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]357 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]358 return FPTOSINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]359 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]360 if (RetVT == MVT::i8)
361 return FPTOSINT_F64_I8;
362 if (RetVT == MVT::i16)
363 return FPTOSINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]364 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]365 return FPTOSINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]366 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]367 return FPTOSINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]368 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]369 return FPTOSINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]370 } else if (OpVT == MVT::f80) {
371 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]372 return FPTOSINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]373 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]374 return FPTOSINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]375 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]376 return FPTOSINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]377 } else if (OpVT == MVT::ppcf128) {
378 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]379 return FPTOSINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]380 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]381 return FPTOSINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]382 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]383 return FPTOSINT_PPCF128_I128;
384 }
385 return UNKNOWN_LIBCALL;
386}
387
388/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
389/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]390RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]391 if (OpVT == MVT::f32) {
392 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]393 return FPTOUINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]394 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]395 return FPTOUINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]396 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]397 return FPTOUINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]398 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]399 return FPTOUINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]400 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]401 return FPTOUINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]402 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]403 if (RetVT == MVT::i8)
404 return FPTOUINT_F64_I8;
405 if (RetVT == MVT::i16)
406 return FPTOUINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]407 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]408 return FPTOUINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]409 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]410 return FPTOUINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]411 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]412 return FPTOUINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]413 } else if (OpVT == MVT::f80) {
414 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]415 return FPTOUINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]416 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]417 return FPTOUINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]418 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]419 return FPTOUINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]420 } else if (OpVT == MVT::ppcf128) {
421 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]422 return FPTOUINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]423 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]424 return FPTOUINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]425 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]426 return FPTOUINT_PPCF128_I128;
427 }
428 return UNKNOWN_LIBCALL;
429}
430
431/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
432/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]433RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]434 if (OpVT == MVT::i32) {
435 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]436 return SINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]437 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]438 return SINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]439 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]440 return SINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]441 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]442 return SINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]443 } else if (OpVT == MVT::i64) {
444 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]445 return SINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]446 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]447 return SINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]448 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]449 return SINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]450 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]451 return SINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]452 } else if (OpVT == MVT::i128) {
453 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]454 return SINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]455 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]456 return SINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]457 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]458 return SINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]459 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]460 return SINTTOFP_I128_PPCF128;
461 }
462 return UNKNOWN_LIBCALL;
463}
464
465/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
466/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]467RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]468 if (OpVT == MVT::i32) {
469 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]470 return UINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]471 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]472 return UINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]473 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]474 return UINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]475 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]476 return UINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]477 } else if (OpVT == MVT::i64) {
478 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]479 return UINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]480 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]481 return UINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]482 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]483 return UINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]484 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]485 return UINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]486 } else if (OpVT == MVT::i128) {
487 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]488 return UINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]489 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]490 return UINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]491 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]492 return UINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]493 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]494 return UINTTOFP_I128_PPCF128;
495 }
496 return UNKNOWN_LIBCALL;
497}
498
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]499/// InitCmpLibcallCCs - Set default comparison libcall CC.
500///
501static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
502 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
503 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
504 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
505 CCs[RTLIB::UNE_F32] = ISD::SETNE;
506 CCs[RTLIB::UNE_F64] = ISD::SETNE;
507 CCs[RTLIB::OGE_F32] = ISD::SETGE;
508 CCs[RTLIB::OGE_F64] = ISD::SETGE;
509 CCs[RTLIB::OLT_F32] = ISD::SETLT;
510 CCs[RTLIB::OLT_F64] = ISD::SETLT;
511 CCs[RTLIB::OLE_F32] = ISD::SETLE;
512 CCs[RTLIB::OLE_F64] = ISD::SETLE;
513 CCs[RTLIB::OGT_F32] = ISD::SETGT;
514 CCs[RTLIB::OGT_F64] = ISD::SETGT;
515 CCs[RTLIB::UO_F32] = ISD::SETNE;
516 CCs[RTLIB::UO_F64] = ISD::SETNE;
517 CCs[RTLIB::O_F32] = ISD::SETEQ;
518 CCs[RTLIB::O_F64] = ISD::SETEQ;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]519}
520
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]521/// NOTE: The constructor takes ownership of TLOF.
Dan Gohmanf0757b02010-04-21 01:34:56 +0000[diff] [blame]522TargetLowering::TargetLowering(const TargetMachine &tm,
523 const TargetLoweringObjectFile *tlof)
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]524 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof),
525 mayPromoteElements(AllowPromoteIntElem) {
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]526 // All operations default to being supported.
527 memset(OpActions, 0, sizeof(OpActions));
Evan Cheng03294662008-10-14 21:26:46 +0000[diff] [blame]528 memset(LoadExtActions, 0, sizeof(LoadExtActions));
Chris Lattnerddf89562008-01-17 19:59:44 +0000[diff] [blame]529 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
Chris Lattnerc9133f92008-01-18 19:36:20 +0000[diff] [blame]530 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
Evan Cheng7f042682008-10-15 02:05:31 +0000[diff] [blame]531 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Dan Gohman93f81e22007-07-09 20:49:44 +0000[diff] [blame]532
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]533 // Set default actions for various operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]534 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]535 // Default all indexed load / store to expand.
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]536 for (unsigned IM = (unsigned)ISD::PRE_INC;
537 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]538 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
539 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]540 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]541
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]542 // These operations default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]543 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]545 }
Evan Chengd2cde682008-03-10 19:38:10 +0000[diff] [blame]546
547 // Most targets ignore the @llvm.prefetch intrinsic.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]548 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]549
550 // ConstantFP nodes default to expand. Targets can either change this to
Evan Chengeb2f9692009-10-27 19:56:55 +0000[diff] [blame]551 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
Nate Begemane1795842008-02-14 08:57:00 +0000[diff] [blame]552 // to optimize expansions for certain constants.
Dan Gohmane3376ec2011-12-20 00:02:33 +0000[diff] [blame]553 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]554 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
555 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
556 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]557
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]558 // These library functions default to expand.
Dan Gohmane3376ec2011-12-20 00:02:33 +0000[diff] [blame]559 setOperationAction(ISD::FLOG , MVT::f16, Expand);
560 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
561 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
562 setOperationAction(ISD::FEXP , MVT::f16, Expand);
563 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
564 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
565 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
566 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
567 setOperationAction(ISD::FRINT, MVT::f16, Expand);
568 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
Owen Anderson4a4fdf32011-12-08 19:32:14 +0000[diff] [blame]569 setOperationAction(ISD::FLOG , MVT::f32, Expand);
570 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
571 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
572 setOperationAction(ISD::FEXP , MVT::f32, Expand);
573 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
574 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
575 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
576 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
577 setOperationAction(ISD::FRINT, MVT::f32, Expand);
578 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
Dan Gohmane3376ec2011-12-20 00:02:33 +0000[diff] [blame]579 setOperationAction(ISD::FLOG , MVT::f64, Expand);
580 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
581 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
582 setOperationAction(ISD::FEXP , MVT::f64, Expand);
583 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
584 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
585 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
586 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
587 setOperationAction(ISD::FRINT, MVT::f64, Expand);
588 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]589
Chris Lattner41bab0b2008-01-15 21:58:08 +0000[diff] [blame]590 // Default ISD::TRAP to expand (which turns it into abort).
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]591 setOperationAction(ISD::TRAP, MVT::Other, Expand);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]592
Owen Andersona69571c2006-05-03 01:29:57 +0000[diff] [blame]593 IsLittleEndian = TD->isLittleEndian();
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]594 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]595 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]596 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Evan Chenga03a5dc2006-02-14 08:38:30 +0000[diff] [blame]597 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
Evan Cheng05219282011-01-06 06:52:41 +0000[diff] [blame]598 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
599 = maxStoresPerMemmoveOptSize = 4;
Evan Cheng6ebf7bc2009-05-13 21:42:09 +0000[diff] [blame]600 benefitFromCodePlacementOpt = false;
Anton Korobeynikovd27a2582006-12-10 23:12:42 +0000[diff] [blame]601 UseUnderscoreSetJmp = false;
602 UseUnderscoreLongJmp = false;
Chris Lattner66180392007-02-25 01:28:05 +0000[diff] [blame]603 SelectIsExpensive = false;
Nate Begeman405e3ec2005-10-21 00:02:42 +0000[diff] [blame]604 IntDivIsCheap = false;
605 Pow2DivIsCheap = false;
Chris Lattnerde189be2010-11-30 18:12:52 +0000[diff] [blame]606 JumpIsExpensive = false;
Chris Lattneree4a7652006-01-25 18:57:15 +0000[diff] [blame]607 StackPointerRegisterToSaveRestore = 0;
Jim Laskey9bb3c932007-02-22 18:04:49 +0000[diff] [blame]608 ExceptionPointerRegister = 0;
609 ExceptionSelectorRegister = 0;
Duncan Sands03228082008-11-23 15:47:28 +0000[diff] [blame]610 BooleanContents = UndefinedBooleanContent;
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]611 BooleanVectorContents = UndefinedBooleanContent;
Dan Gohman8c2d2702011-10-24 17:45:02 +0000[diff] [blame]612 SchedPreferenceInfo = Sched::ILP;
Chris Lattner7acf5f32006-09-05 17:39:15 +0000[diff] [blame]613 JumpBufSize = 0;
Duraid Madina0c9e0ff2006-09-04 07:44:11 +0000[diff] [blame]614 JumpBufAlignment = 0;
Eli Friedmanfc5d3052011-05-06 20:34:06 +0000[diff] [blame]615 MinFunctionAlignment = 0;
616 PrefFunctionAlignment = 0;
Evan Chengfb8075d2008-02-28 00:43:03 +0000[diff] [blame]617 PrefLoopAlignment = 0;
Rafael Espindolacbeeae22010-07-11 04:01:49 +0000[diff] [blame]618 MinStackArgumentAlignment = 1;
Jim Grosbach9a526492010-06-23 16:07:42 +0000[diff] [blame]619 ShouldFoldAtomicFences = false;
Eli Friedman26689ac2011-08-03 21:06:02 +0000[diff] [blame]620 InsertFencesForAtomic = false;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]621
622 InitLibcallNames(LibcallRoutineNames);
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]623 InitCmpLibcallCCs(CmpLibcallCCs);
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]624 InitLibcallCallingConvs(LibcallCallingConvs);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]625}
626
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]627TargetLowering::~TargetLowering() {
628 delete &TLOF;
629}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]630
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]631MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
632 return MVT::getIntegerVT(8*TD->getPointerSize());
633}
634
Mon P Wangf7ea6c32010-02-10 23:37:45 +0000[diff] [blame]635/// canOpTrap - Returns true if the operation can trap for the value type.
636/// VT must be a legal type.
637bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
638 assert(isTypeLegal(VT));
639 switch (Op) {
640 default:
641 return false;
642 case ISD::FDIV:
643 case ISD::FREM:
644 case ISD::SDIV:
645 case ISD::UDIV:
646 case ISD::SREM:
647 case ISD::UREM:
648 return true;
649 }
650}
651
652
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]653static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]654 unsigned &NumIntermediates,
655 EVT &RegisterVT,
656 TargetLowering *TLI) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]657 // Figure out the right, legal destination reg to copy into.
658 unsigned NumElts = VT.getVectorNumElements();
659 MVT EltTy = VT.getVectorElementType();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]660
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]661 unsigned NumVectorRegs = 1;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]662
663 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]664 // could break down into LHS/RHS like LegalizeDAG does.
665 if (!isPowerOf2_32(NumElts)) {
666 NumVectorRegs = NumElts;
667 NumElts = 1;
668 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]669
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]670 // Divide the input until we get to a supported size. This will always
671 // end with a scalar if the target doesn't support vectors.
672 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
673 NumElts >>= 1;
674 NumVectorRegs <<= 1;
675 }
676
677 NumIntermediates = NumVectorRegs;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]678
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]679 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
680 if (!TLI->isTypeLegal(NewVT))
681 NewVT = EltTy;
682 IntermediateVT = NewVT;
683
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]684 unsigned NewVTSize = NewVT.getSizeInBits();
685
686 // Convert sizes such as i33 to i64.
687 if (!isPowerOf2_32(NewVTSize))
688 NewVTSize = NextPowerOf2(NewVTSize);
689
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]690 EVT DestVT = TLI->getRegisterType(NewVT);
691 RegisterVT = DestVT;
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]692 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]693 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]694
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]695 // Otherwise, promotion or legal types use the same number of registers as
696 // the vector decimated to the appropriate level.
697 return NumVectorRegs;
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]698}
699
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]700/// isLegalRC - Return true if the value types that can be represented by the
701/// specified register class are all legal.
702bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
703 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
704 I != E; ++I) {
705 if (isTypeLegal(*I))
706 return true;
707 }
708 return false;
709}
710
711/// hasLegalSuperRegRegClasses - Return true if the specified register class
712/// has one or more super-reg register classes that are legal.
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]713bool
714TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]715 if (*RC->superregclasses_begin() == 0)
716 return false;
717 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
718 E = RC->superregclasses_end(); I != E; ++I) {
719 const TargetRegisterClass *RRC = *I;
720 if (isLegalRC(RRC))
721 return true;
722 }
723 return false;
724}
725
726/// findRepresentativeClass - Return the largest legal super-reg register class
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]727/// of the register class for the specified type and its associated "cost".
728std::pair<const TargetRegisterClass*, uint8_t>
729TargetLowering::findRepresentativeClass(EVT VT) const {
730 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
731 if (!RC)
732 return std::make_pair(RC, 0);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]733 const TargetRegisterClass *BestRC = RC;
734 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
735 E = RC->superregclasses_end(); I != E; ++I) {
736 const TargetRegisterClass *RRC = *I;
737 if (RRC->isASubClass() || !isLegalRC(RRC))
738 continue;
739 if (!hasLegalSuperRegRegClasses(RRC))
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]740 return std::make_pair(RRC, 1);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]741 BestRC = RRC;
742 }
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]743 return std::make_pair(BestRC, 1);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]744}
745
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]746
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]747/// computeRegisterProperties - Once all of the register classes are added,
748/// this allows us to compute derived properties we expose.
749void TargetLowering::computeRegisterProperties() {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]750 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]751 "Too many value types for ValueTypeActions to hold!");
752
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]753 // Everything defaults to needing one register.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]754 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]755 NumRegistersForVT[i] = 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]756 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]757 }
758 // ...except isVoid, which doesn't need any registers.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]759 NumRegistersForVT[MVT::isVoid] = 0;
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]760
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]761 // Find the largest integer register class.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]762 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]763 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]764 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]765
766 // Every integer value type larger than this largest register takes twice as
767 // many registers to represent as the previous ValueType.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]768 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
Dan Gohman8a55ce42009-09-23 21:02:20 +0000[diff] [blame]769 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
770 if (!ExpandedVT.isInteger())
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]771 break;
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]772 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]773 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
774 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]775 ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger);
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]776 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]777
778 // Inspect all of the ValueType's smaller than the largest integer
779 // register to see which ones need promotion.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]780 unsigned LegalIntReg = LargestIntReg;
781 for (unsigned IntReg = LargestIntReg - 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]782 IntReg >= (unsigned)MVT::i1; --IntReg) {
783 EVT IVT = (MVT::SimpleValueType)IntReg;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]784 if (isTypeLegal(IVT)) {
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]785 LegalIntReg = IntReg;
786 } else {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]787 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]788 (MVT::SimpleValueType)LegalIntReg;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]789 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]790 }
791 }
792
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]793 // ppcf128 type is really two f64's.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]794 if (!isTypeLegal(MVT::ppcf128)) {
795 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
796 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
797 TransformToType[MVT::ppcf128] = MVT::f64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]798 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]799 }
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]800
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]801 // Decide how to handle f64. If the target does not have native f64 support,
802 // expand it to i64 and we will be generating soft float library calls.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]803 if (!isTypeLegal(MVT::f64)) {
804 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
805 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
806 TransformToType[MVT::f64] = MVT::i64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]807 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]808 }
809
810 // Decide how to handle f32. If the target does not have native support for
811 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]812 if (!isTypeLegal(MVT::f32)) {
813 if (isTypeLegal(MVT::f64)) {
814 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
815 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
816 TransformToType[MVT::f32] = MVT::f64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]817 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]818 } else {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]819 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
820 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
821 TransformToType[MVT::f32] = MVT::i32;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]822 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]823 }
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]824 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]825
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]826 // Loop over all of the vector value types to see which need transformations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]827 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
828 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]829 MVT VT = (MVT::SimpleValueType)i;
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]830 if (isTypeLegal(VT)) continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]831
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]832 // Determine if there is a legal wider type. If so, we should promote to
833 // that wider vector type.
834 EVT EltVT = VT.getVectorElementType();
835 unsigned NElts = VT.getVectorNumElements();
836 if (NElts != 1) {
837 bool IsLegalWiderType = false;
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]838 // If we allow the promotion of vector elements using a flag,
839 // then return TypePromoteInteger on vector elements.
840 // First try to promote the elements of integer vectors. If no legal
841 // promotion was found, fallback to the widen-vector method.
842 if (mayPromoteElements)
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]843 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
844 EVT SVT = (MVT::SimpleValueType)nVT;
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]845 // Promote vectors of integers to vectors with the same number
846 // of elements, with a wider element type.
847 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
848 && SVT.getVectorNumElements() == NElts &&
849 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
850 TransformToType[i] = SVT;
851 RegisterTypeForVT[i] = SVT;
852 NumRegistersForVT[i] = 1;
853 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
854 IsLegalWiderType = true;
855 break;
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]856 }
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]857 }
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]858
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]859 if (IsLegalWiderType) continue;
860
861 // Try to widen the vector.
862 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
863 EVT SVT = (MVT::SimpleValueType)nVT;
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]864 if (SVT.getVectorElementType() == EltVT &&
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]865 SVT.getVectorNumElements() > NElts &&
Dale Johannesene93d99c2010-10-20 21:32:10 +0000[diff] [blame]866 isTypeLegal(SVT)) {
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]867 TransformToType[i] = SVT;
868 RegisterTypeForVT[i] = SVT;
869 NumRegistersForVT[i] = 1;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]870 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]871 IsLegalWiderType = true;
872 break;
873 }
874 }
875 if (IsLegalWiderType) continue;
876 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]877
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]878 MVT IntermediateVT;
879 EVT RegisterVT;
880 unsigned NumIntermediates;
881 NumRegistersForVT[i] =
882 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
883 RegisterVT, this);
884 RegisterTypeForVT[i] = RegisterVT;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]885
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]886 EVT NVT = VT.getPow2VectorType();
887 if (NVT == VT) {
888 // Type is already a power of 2. The default action is to split.
889 TransformToType[i] = MVT::Other;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]890 unsigned NumElts = VT.getVectorNumElements();
891 ValueTypeActions.setTypeAction(VT,
892 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]893 } else {
894 TransformToType[i] = NVT;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]895 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]896 }
Chris Lattner3a5935842006-03-16 19:50:01 +0000[diff] [blame]897 }
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]898
899 // Determine the 'representative' register class for each value type.
900 // An representative register class is the largest (meaning one which is
901 // not a sub-register class / subreg register class) legal register class for
902 // a group of value types. For example, on i386, i8, i16, and i32
903 // representative would be GR32; while on x86_64 it's GR64.
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]904 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]905 const TargetRegisterClass* RRC;
906 uint8_t Cost;
907 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
908 RepRegClassForVT[i] = RRC;
909 RepRegClassCostForVT[i] = Cost;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]910 }
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]911}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]912
Evan Cheng72261582005-12-20 06:22:03 +0000[diff] [blame]913const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
914 return NULL;
915}
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]916
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]917
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]918EVT TargetLowering::getSetCCResultType(EVT VT) const {
919 assert(!VT.isVector() && "No default SetCC type for vectors!");
Owen Anderson1d0be152009-08-13 21:58:54 +0000[diff] [blame]920 return PointerTy.SimpleTy;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]921}
922
Sanjiv Gupta8f17a362009-12-28 02:40:33 +0000[diff] [blame]923MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
924 return MVT::i32; // return the default value
925}
926
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]927/// getVectorTypeBreakdown - Vector types are broken down into some number of
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]928/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
929/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
930/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]931///
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]932/// This method returns the number of registers needed, and the VT for each
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]933/// register. It also returns the VT and quantity of the intermediate values
934/// before they are promoted/expanded.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]935///
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]936unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]937 EVT &IntermediateVT,
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]938 unsigned &NumIntermediates,
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]939 EVT &RegisterVT) const {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]940 unsigned NumElts = VT.getVectorNumElements();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]941
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]942 // If there is a wider vector type with the same element type as this one,
943 // we should widen to that legal vector type. This handles things like
944 // <2 x float> -> <4 x float>.
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]945 if (NumElts != 1 && getTypeAction(Context, VT) == TypeWidenVector) {
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]946 RegisterVT = getTypeToTransformTo(Context, VT);
947 if (isTypeLegal(RegisterVT)) {
948 IntermediateVT = RegisterVT;
949 NumIntermediates = 1;
950 return 1;
951 }
952 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]953
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]954 // Figure out the right, legal destination reg to copy into.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]955 EVT EltTy = VT.getVectorElementType();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]956
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]957 unsigned NumVectorRegs = 1;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]958
959 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Nate Begemand73ab882007-11-27 19:28:48 +0000[diff] [blame]960 // could break down into LHS/RHS like LegalizeDAG does.
961 if (!isPowerOf2_32(NumElts)) {
962 NumVectorRegs = NumElts;
963 NumElts = 1;
964 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]965
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]966 // Divide the input until we get to a supported size. This will always
967 // end with a scalar if the target doesn't support vectors.
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]968 while (NumElts > 1 && !isTypeLegal(
969 EVT::getVectorVT(Context, EltTy, NumElts))) {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]970 NumElts >>= 1;
971 NumVectorRegs <<= 1;
972 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]973
974 NumIntermediates = NumVectorRegs;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]975
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]976 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]977 if (!isTypeLegal(NewVT))
978 NewVT = EltTy;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]979 IntermediateVT = NewVT;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]980
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]981 EVT DestVT = getRegisterType(Context, NewVT);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]982 RegisterVT = DestVT;
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]983 unsigned NewVTSize = NewVT.getSizeInBits();
984
985 // Convert sizes such as i33 to i64.
986 if (!isPowerOf2_32(NewVTSize))
987 NewVTSize = NextPowerOf2(NewVTSize);
988
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]989 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]990 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]991
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]992 // Otherwise, promotion or legal types use the same number of registers as
993 // the vector decimated to the appropriate level.
994 return NumVectorRegs;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]995}
996
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]997/// Get the EVTs and ArgFlags collections that represent the legalized return
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]998/// type of the given function. This does not require a DAG or a return value,
999/// and is suitable for use before any DAGs for the function are constructed.
1000/// TODO: Move this out of TargetLowering.cpp.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]1001void llvm::GetReturnInfo(Type* ReturnType, Attributes attr,
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1002 SmallVectorImpl<ISD::OutputArg> &Outs,
1003 const TargetLowering &TLI,
1004 SmallVectorImpl<uint64_t> *Offsets) {
1005 SmallVector<EVT, 4> ValueVTs;
1006 ComputeValueVTs(TLI, ReturnType, ValueVTs);
1007 unsigned NumValues = ValueVTs.size();
1008 if (NumValues == 0) return;
1009 unsigned Offset = 0;
1010
1011 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1012 EVT VT = ValueVTs[j];
1013 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1014
1015 if (attr & Attribute::SExt)
1016 ExtendKind = ISD::SIGN_EXTEND;
1017 else if (attr & Attribute::ZExt)
1018 ExtendKind = ISD::ZERO_EXTEND;
1019
1020 // FIXME: C calling convention requires the return type to be promoted to
1021 // at least 32-bit. But this is not necessary for non-C calling
1022 // conventions. The frontend should mark functions whose return values
1023 // require promoting with signext or zeroext attributes.
1024 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1025 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1026 if (VT.bitsLT(MinVT))
1027 VT = MinVT;
1028 }
1029
1030 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1031 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1032 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
1033 PartVT.getTypeForEVT(ReturnType->getContext()));
1034
1035 // 'inreg' on function refers to return value
1036 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1037 if (attr & Attribute::InReg)
1038 Flags.setInReg();
1039
1040 // Propagate extension type if any
1041 if (attr & Attribute::SExt)
1042 Flags.setSExt();
1043 else if (attr & Attribute::ZExt)
1044 Flags.setZExt();
1045
1046 for (unsigned i = 0; i < NumParts; ++i) {
1047 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
1048 if (Offsets) {
1049 Offsets->push_back(Offset);
1050 Offset += PartSize;
1051 }
1052 }
1053 }
1054}
1055
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]1056/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]1057/// function arguments in the caller parameter area. This is the actual
1058/// alignment, not its logarithm.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]1059unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]1060 return TD->getCallFrameTypeAlignment(Ty);
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]1061}
1062
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1063/// getJumpTableEncoding - Return the entry encoding for a jump table in the
1064/// current function. The returned value is a member of the
1065/// MachineJumpTableInfo::JTEntryKind enum.
1066unsigned TargetLowering::getJumpTableEncoding() const {
1067 // In non-pic modes, just use the address of a block.
1068 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1069 return MachineJumpTableInfo::EK_BlockAddress;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1070
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1071 // In PIC mode, if the target supports a GPRel32 directive, use it.
1072 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1073 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1074
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1075 // Otherwise, use a label difference.
1076 return MachineJumpTableInfo::EK_LabelDifference32;
1077}
1078
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1079SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1080 SelectionDAG &DAG) const {
Chris Lattnerf1214cb2010-01-26 06:53:37 +0000[diff] [blame]1081 // If our PIC model is GP relative, use the global offset table as the base.
1082 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
Dale Johannesenb300d2a2009-02-07 00:55:49 +0000[diff] [blame]1083 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
Evan Chengcc415862007-11-09 01:32:10 +0000[diff] [blame]1084 return Table;
1085}
1086
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1087/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1088/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1089/// MCExpr.
1090const MCExpr *
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1091TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1092 unsigned JTI,MCContext &Ctx) const{
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]1093 // The normal PIC reloc base is the label at the start of the jump table.
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1094 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1095}
1096
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1097bool
1098TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1099 // Assume that everything is safe in static mode.
1100 if (getTargetMachine().getRelocationModel() == Reloc::Static)
1101 return true;
1102
1103 // In dynamic-no-pic mode, assume that known defined values are safe.
1104 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1105 GA &&
1106 !GA->getGlobal()->isDeclaration() &&
Duncan Sands667d4b82009-03-07 15:45:40 +0000[diff] [blame]1107 !GA->getGlobal()->isWeakForLinker())
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1108 return true;
1109
1110 // Otherwise assume nothing is safe.
1111 return false;
1112}
1113
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]1114//===----------------------------------------------------------------------===//
1115// Optimization Methods
1116//===----------------------------------------------------------------------===//
1117
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1118/// ShrinkDemandedConstant - Check to see if the specified operand of the
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1119/// specified instruction is a constant integer. If so, check to see if there
1120/// are any bits set in the constant that are not demanded. If so, shrink the
1121/// constant and return true.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1122bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1123 const APInt &Demanded) {
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1124 DebugLoc dl = Op.getDebugLoc();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1125
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1126 // FIXME: ISD::SELECT, ISD::SELECT_CC
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1127 switch (Op.getOpcode()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1128 default: break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1129 case ISD::XOR:
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1130 case ISD::AND:
1131 case ISD::OR: {
1132 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1133 if (!C) return false;
1134
1135 if (Op.getOpcode() == ISD::XOR &&
1136 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1137 return false;
1138
1139 // if we can expand it to have all bits set, do it
1140 if (C->getAPIntValue().intersects(~Demanded)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1141 EVT VT = Op.getValueType();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1142 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1143 DAG.getConstant(Demanded &
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1144 C->getAPIntValue(),
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1145 VT));
1146 return CombineTo(Op, New);
1147 }
1148
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1149 break;
1150 }
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1151 }
1152
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1153 return false;
1154}
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1155
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1156/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1157/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1158/// cast, but it could be generalized for targets with other types of
1159/// implicit widening casts.
1160bool
1161TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1162 unsigned BitWidth,
1163 const APInt &Demanded,
1164 DebugLoc dl) {
1165 assert(Op.getNumOperands() == 2 &&
1166 "ShrinkDemandedOp only supports binary operators!");
1167 assert(Op.getNode()->getNumValues() == 1 &&
1168 "ShrinkDemandedOp only supports nodes with one result!");
1169
1170 // Don't do this if the node has another user, which may require the
1171 // full value.
1172 if (!Op.getNode()->hasOneUse())
1173 return false;
1174
1175 // Search for the smallest integer type with free casts to and from
1176 // Op's type. For expedience, just check power-of-2 integer types.
1177 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1178 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1179 if (!isPowerOf2_32(SmallVTBits))
1180 SmallVTBits = NextPowerOf2(SmallVTBits);
1181 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1182 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1183 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1184 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1185 // We found a type with free casts.
1186 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1187 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1188 Op.getNode()->getOperand(0)),
1189 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1190 Op.getNode()->getOperand(1)));
1191 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1192 return CombineTo(Op, Z);
1193 }
1194 }
1195 return false;
1196}
1197
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1198/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
Chad Rosier8c1ec5a2011-06-11 02:27:46 +0000[diff] [blame]1199/// DemandedMask bits of the result of Op are ever used downstream. If we can
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1200/// use this information to simplify Op, create a new simplified DAG node and
1201/// return true, returning the original and new nodes in Old and New. Otherwise,
1202/// analyze the expression and return a mask of KnownOne and KnownZero bits for
1203/// the expression (used to simplify the caller). The KnownZero/One bits may
1204/// only be accurate for those bits in the DemandedMask.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1205bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1206 const APInt &DemandedMask,
1207 APInt &KnownZero,
1208 APInt &KnownOne,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1209 TargetLoweringOpt &TLO,
1210 unsigned Depth) const {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1211 unsigned BitWidth = DemandedMask.getBitWidth();
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1212 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1213 "Mask size mismatches value type size!");
1214 APInt NewMask = DemandedMask;
Dale Johannesen6f38cb62009-02-07 19:59:05 +0000[diff] [blame]1215 DebugLoc dl = Op.getDebugLoc();
Chris Lattner3fc5b012007-05-17 18:19:23 +0000[diff] [blame]1216
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1217 // Don't know anything.
1218 KnownZero = KnownOne = APInt(BitWidth, 0);
1219
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1220 // Other users may use these bits.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1221 if (!Op.getNode()->hasOneUse()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1222 if (Depth != 0) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1223 // If not at the root, Just compute the KnownZero/KnownOne bits to
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1224 // simplify things downstream.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1225 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1226 return false;
1227 }
1228 // If this is the root being simplified, allow it to have multiple uses,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1229 // just set the NewMask to all bits.
1230 NewMask = APInt::getAllOnesValue(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1231 } else if (DemandedMask == 0) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1232 // Not demanding any bits from Op.
1233 if (Op.getOpcode() != ISD::UNDEF)
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]1234 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1235 return false;
1236 } else if (Depth == 6) { // Limit search depth.
1237 return false;
1238 }
1239
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1240 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1241 switch (Op.getOpcode()) {
1242 case ISD::Constant:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1243 // We know all of the bits for a constant!
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1244 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
1245 KnownZero = ~KnownOne;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1246 return false; // Don't fall through, will infinitely loop.
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1247 case ISD::AND:
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1248 // If the RHS is a constant, check to see if the LHS would be zero without
1249 // using the bits from the RHS. Below, we use knowledge about the RHS to
1250 // simplify the LHS, here we're using information from the LHS to simplify
1251 // the RHS.
1252 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1253 APInt LHSZero, LHSOne;
Dale Johannesen97fd9a52011-01-10 21:53:07 +0000[diff] [blame]1254 // Do not increment Depth here; that can cause an infinite loop.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1255 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1256 // If the LHS already has zeros where RHSC does, this and is dead.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1257 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1258 return TLO.CombineTo(Op, Op.getOperand(0));
1259 // If any of the set bits in the RHS are known zero on the LHS, shrink
1260 // the constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1261 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1262 return true;
1263 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1264
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1265 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1266 KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1267 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1268 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1269 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1270 KnownZero2, KnownOne2, TLO, Depth+1))
1271 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1272 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1273
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1274 // If all of the demanded bits are known one on one side, return the other.
1275 // These bits cannot contribute to the result of the 'and'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1276 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1277 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1278 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1279 return TLO.CombineTo(Op, Op.getOperand(1));
1280 // If all of the demanded bits in the inputs are known zeros, return zero.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1281 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1282 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1283 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1284 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1285 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1286 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1287 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1288 return true;
1289
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1290 // Output known-1 bits are only known if set in both the LHS & RHS.
1291 KnownOne &= KnownOne2;
1292 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1293 KnownZero |= KnownZero2;
1294 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1295 case ISD::OR:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1296 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1297 KnownOne, TLO, Depth+1))
1298 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1299 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1300 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1301 KnownZero2, KnownOne2, TLO, Depth+1))
1302 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1303 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1304
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1305 // If all of the demanded bits are known zero on one side, return the other.
1306 // These bits cannot contribute to the result of the 'or'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1307 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1308 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1309 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1310 return TLO.CombineTo(Op, Op.getOperand(1));
1311 // If all of the potentially set bits on one side are known to be set on
1312 // the other side, just use the 'other' side.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1313 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1314 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1315 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1316 return TLO.CombineTo(Op, Op.getOperand(1));
1317 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1318 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1319 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1320 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1321 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1322 return true;
1323
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1324 // Output known-0 bits are only known if clear in both the LHS & RHS.
1325 KnownZero &= KnownZero2;
1326 // Output known-1 are known to be set if set in either the LHS | RHS.
1327 KnownOne |= KnownOne2;
1328 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1329 case ISD::XOR:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1330 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1331 KnownOne, TLO, Depth+1))
1332 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1333 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1334 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1335 KnownOne2, TLO, Depth+1))
1336 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1337 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1338
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1339 // If all of the demanded bits are known zero on one side, return the other.
1340 // These bits cannot contribute to the result of the 'xor'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1341 if ((KnownZero & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1342 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1343 if ((KnownZero2 & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1344 return TLO.CombineTo(Op, Op.getOperand(1));
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1345 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1346 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1347 return true;
1348
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1349 // If all of the unknown bits are known to be zero on one side or the other
1350 // (but not both) turn this into an *inclusive* or.
1351 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1352 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1353 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1354 Op.getOperand(0),
1355 Op.getOperand(1)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1356
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1357 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1358 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1359 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1360 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1361
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1362 // If all of the demanded bits on one side are known, and all of the set
1363 // bits on that side are also known to be set on the other side, turn this
1364 // into an AND, as we know the bits will be cleared.
1365 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1366 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1367 if ((KnownOne & KnownOne2) == KnownOne) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1368 EVT VT = Op.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1369 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1370 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1371 Op.getOperand(0), ANDC));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1372 }
1373 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1374
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1375 // If the RHS is a constant, see if we can simplify it.
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1376 // for XOR, we prefer to force bits to 1 if they will make a -1.
1377 // if we can't force bits, try to shrink constant
1378 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1379 APInt Expanded = C->getAPIntValue() | (~NewMask);
1380 // if we can expand it to have all bits set, do it
1381 if (Expanded.isAllOnesValue()) {
1382 if (Expanded != C->getAPIntValue()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1383 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1384 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1385 TLO.DAG.getConstant(Expanded, VT));
1386 return TLO.CombineTo(Op, New);
1387 }
1388 // if it already has all the bits set, nothing to change
1389 // but don't shrink either!
1390 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1391 return true;
1392 }
1393 }
1394
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1395 KnownZero = KnownZeroOut;
1396 KnownOne = KnownOneOut;
1397 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1398 case ISD::SELECT:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1399 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1400 KnownOne, TLO, Depth+1))
1401 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1402 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1403 KnownOne2, TLO, Depth+1))
1404 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1405 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1406 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1407
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1408 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1409 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1410 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1411
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1412 // Only known if known in both the LHS and RHS.
1413 KnownOne &= KnownOne2;
1414 KnownZero &= KnownZero2;
1415 break;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1416 case ISD::SELECT_CC:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1417 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1418 KnownOne, TLO, Depth+1))
1419 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1420 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1421 KnownOne2, TLO, Depth+1))
1422 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1423 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1424 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1425
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1426 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1427 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1428 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1429
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1430 // Only known if known in both the LHS and RHS.
1431 KnownOne &= KnownOne2;
1432 KnownZero &= KnownZero2;
1433 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1434 case ISD::SHL:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1435 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1436 unsigned ShAmt = SA->getZExtValue();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1437 SDValue InOp = Op.getOperand(0);
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1438
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1439 // If the shift count is an invalid immediate, don't do anything.
1440 if (ShAmt >= BitWidth)
1441 break;
1442
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1443 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1444 // single shift. We can do this if the bottom bits (which are shifted
1445 // out) are never demanded.
1446 if (InOp.getOpcode() == ISD::SRL &&
1447 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1448 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1449 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1450 unsigned Opc = ISD::SHL;
1451 int Diff = ShAmt-C1;
1452 if (Diff < 0) {
1453 Diff = -Diff;
1454 Opc = ISD::SRL;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1455 }
1456
1457 SDValue NewSA =
Chris Lattner4e7e6cd2007-05-30 16:30:06 +0000[diff] [blame]1458 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1459 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1460 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1461 InOp.getOperand(0), NewSA));
1462 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1463 }
1464
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1465 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1466 KnownZero, KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1467 return true;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1468
1469 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1470 // are not demanded. This will likely allow the anyext to be folded away.
1471 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1472 SDValue InnerOp = InOp.getNode()->getOperand(0);
1473 EVT InnerVT = InnerOp.getValueType();
Eli Friedman2dd03532011-12-09 01:16:26 +0000[diff] [blame]1474 unsigned InnerBits = InnerVT.getSizeInBits();
1475 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1476 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]1477 EVT ShTy = getShiftAmountTy(InnerVT);
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1478 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1479 ShTy = InnerVT;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1480 SDValue NarrowShl =
1481 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1482 TLO.DAG.getConstant(ShAmt, ShTy));
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1483 return
1484 TLO.CombineTo(Op,
1485 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1486 NarrowShl));
1487 }
1488 }
1489
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1490 KnownZero <<= SA->getZExtValue();
1491 KnownOne <<= SA->getZExtValue();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1492 // low bits known zero.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1493 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1494 }
1495 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1496 case ISD::SRL:
1497 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1498 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1499 unsigned ShAmt = SA->getZExtValue();
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1500 unsigned VTSize = VT.getSizeInBits();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1501 SDValue InOp = Op.getOperand(0);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1502
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1503 // If the shift count is an invalid immediate, don't do anything.
1504 if (ShAmt >= BitWidth)
1505 break;
1506
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1507 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1508 // single shift. We can do this if the top bits (which are shifted out)
1509 // are never demanded.
1510 if (InOp.getOpcode() == ISD::SHL &&
1511 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1512 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1513 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1514 unsigned Opc = ISD::SRL;
1515 int Diff = ShAmt-C1;
1516 if (Diff < 0) {
1517 Diff = -Diff;
1518 Opc = ISD::SHL;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1519 }
1520
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1521 SDValue NewSA =
Chris Lattner8c7d2d52007-04-17 22:53:02 +0000[diff] [blame]1522 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1523 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1524 InOp.getOperand(0), NewSA));
1525 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1526 }
1527
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1528 // Compute the new bits that are at the top now.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1529 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1530 KnownZero, KnownOne, TLO, Depth+1))
1531 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1532 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1533 KnownZero = KnownZero.lshr(ShAmt);
1534 KnownOne = KnownOne.lshr(ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1535
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1536 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1537 KnownZero |= HighBits; // High bits known zero.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1538 }
1539 break;
1540 case ISD::SRA:
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1541 // If this is an arithmetic shift right and only the low-bit is set, we can
1542 // always convert this into a logical shr, even if the shift amount is
1543 // variable. The low bit of the shift cannot be an input sign bit unless
1544 // the shift amount is >= the size of the datatype, which is undefined.
Eli Friedman2dd03532011-12-09 01:16:26 +0000[diff] [blame]1545 if (NewMask == 1)
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1546 return TLO.CombineTo(Op,
1547 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1548 Op.getOperand(0), Op.getOperand(1)));
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1549
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1550 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1551 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1552 unsigned ShAmt = SA->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1553
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1554 // If the shift count is an invalid immediate, don't do anything.
1555 if (ShAmt >= BitWidth)
1556 break;
1557
1558 APInt InDemandedMask = (NewMask << ShAmt);
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1559
1560 // If any of the demanded bits are produced by the sign extension, we also
1561 // demand the input sign bit.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1562 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1563 if (HighBits.intersects(NewMask))
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1564 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1565
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1566 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1567 KnownZero, KnownOne, TLO, Depth+1))
1568 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1569 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1570 KnownZero = KnownZero.lshr(ShAmt);
1571 KnownOne = KnownOne.lshr(ShAmt);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1572
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1573 // Handle the sign bit, adjusted to where it is now in the mask.
1574 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1575
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1576 // If the input sign bit is known to be zero, or if none of the top bits
1577 // are demanded, turn this into an unsigned shift right.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1578 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1579 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1580 Op.getOperand(0),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1581 Op.getOperand(1)));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1582 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1583 KnownOne |= HighBits;
1584 }
1585 }
1586 break;
1587 case ISD::SIGN_EXTEND_INREG: {
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1588 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1589
1590 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
1591 // If we only care about the highest bit, don't bother shifting right.
Eli Friedmand49db362012-01-31 01:08:03 +0000[diff] [blame]1592 if (MsbMask == DemandedMask) {
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1593 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
1594 SDValue InOp = Op.getOperand(0);
Eli Friedmand49db362012-01-31 01:08:03 +0000[diff] [blame]1595
1596 // Compute the correct shift amount type, which must be getShiftAmountTy
1597 // for scalar types after legalization.
1598 EVT ShiftAmtTy = Op.getValueType();
1599 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1600 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
1601
1602 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1603 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1604 Op.getValueType(), InOp, ShiftAmt));
1605 }
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1606
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1607 // Sign extension. Compute the demanded bits in the result that are not
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1608 // present in the input.
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1609 APInt NewBits =
1610 APInt::getHighBitsSet(BitWidth,
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1611 BitWidth - ExVT.getScalarType().getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1612
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1613 // If none of the extended bits are demanded, eliminate the sextinreg.
Eli Friedman1d17d192010-08-02 04:42:25 +0000[diff] [blame]1614 if ((NewBits & NewMask) == 0)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1615 return TLO.CombineTo(Op, Op.getOperand(0));
1616
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1617 APInt InSignBit =
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1618 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1619 APInt InputDemandedBits =
1620 APInt::getLowBitsSet(BitWidth,
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1621 ExVT.getScalarType().getSizeInBits()) &
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1622 NewMask;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1623
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1624 // Since the sign extended bits are demanded, we know that the sign
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1625 // bit is demanded.
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1626 InputDemandedBits |= InSignBit;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1627
1628 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1629 KnownZero, KnownOne, TLO, Depth+1))
1630 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1631 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1632
1633 // If the sign bit of the input is known set or clear, then we know the
1634 // top bits of the result.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1635
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1636 // If the input sign bit is known zero, convert this into a zero extension.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1637 if (KnownZero.intersects(InSignBit))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1638 return TLO.CombineTo(Op,
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1639 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1640
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1641 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1642 KnownOne |= NewBits;
1643 KnownZero &= ~NewBits;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1644 } else { // Input sign bit unknown
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1645 KnownZero &= ~NewBits;
1646 KnownOne &= ~NewBits;
1647 }
1648 break;
1649 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1650 case ISD::ZERO_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1651 unsigned OperandBitWidth =
1652 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1653 APInt InMask = NewMask.trunc(OperandBitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1654
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1655 // If none of the top bits are demanded, convert this into an any_extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1656 APInt NewBits =
1657 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1658 if (!NewBits.intersects(NewMask))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1659 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1660 Op.getValueType(),
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1661 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1662
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1663 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1664 KnownZero, KnownOne, TLO, Depth+1))
1665 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1666 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1667 KnownZero = KnownZero.zext(BitWidth);
1668 KnownOne = KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1669 KnownZero |= NewBits;
1670 break;
1671 }
1672 case ISD::SIGN_EXTEND: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1673 EVT InVT = Op.getOperand(0).getValueType();
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1674 unsigned InBits = InVT.getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1675 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
Dan Gohman97360282008-03-11 21:29:43 +0000[diff] [blame]1676 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1677 APInt NewBits = ~InMask & NewMask;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1678
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1679 // If none of the top bits are demanded, convert this into an any_extend.
1680 if (NewBits == 0)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1681 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1682 Op.getValueType(),
1683 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1684
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1685 // Since some of the sign extended bits are demanded, we know that the sign
1686 // bit is demanded.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1687 APInt InDemandedBits = InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1688 InDemandedBits |= InSignBit;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1689 InDemandedBits = InDemandedBits.trunc(InBits);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1690
1691 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1692 KnownOne, TLO, Depth+1))
1693 return true;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1694 KnownZero = KnownZero.zext(BitWidth);
1695 KnownOne = KnownOne.zext(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1696
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1697 // If the sign bit is known zero, convert this to a zero extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1698 if (KnownZero.intersects(InSignBit))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1699 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1700 Op.getValueType(),
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1701 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1702
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1703 // If the sign bit is known one, the top bits match.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1704 if (KnownOne.intersects(InSignBit)) {
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1705 KnownOne |= NewBits;
1706 assert((KnownZero & NewBits) == 0);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1707 } else { // Otherwise, top bits aren't known.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1708 assert((KnownOne & NewBits) == 0);
1709 assert((KnownZero & NewBits) == 0);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1710 }
1711 break;
1712 }
1713 case ISD::ANY_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1714 unsigned OperandBitWidth =
1715 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1716 APInt InMask = NewMask.trunc(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1717 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1718 KnownZero, KnownOne, TLO, Depth+1))
1719 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1720 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1721 KnownZero = KnownZero.zext(BitWidth);
1722 KnownOne = KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1723 break;
1724 }
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1725 case ISD::TRUNCATE: {
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1726 // Simplify the input, using demanded bit information, and compute the known
1727 // zero/one bits live out.
Dan Gohman042919c2010-03-01 17:59:21 +0000[diff] [blame]1728 unsigned OperandBitWidth =
1729 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1730 APInt TruncMask = NewMask.zext(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1731 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1732 KnownZero, KnownOne, TLO, Depth+1))
1733 return true;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1734 KnownZero = KnownZero.trunc(BitWidth);
1735 KnownOne = KnownOne.trunc(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1736
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1737 // If the input is only used by this truncate, see if we can shrink it based
1738 // on the known demanded bits.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1739 if (Op.getOperand(0).getNode()->hasOneUse()) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1740 SDValue In = Op.getOperand(0);
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1741 switch (In.getOpcode()) {
1742 default: break;
1743 case ISD::SRL:
1744 // Shrink SRL by a constant if none of the high bits shifted in are
1745 // demanded.
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1746 if (TLO.LegalTypes() &&
1747 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1748 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1749 // undesirable.
1750 break;
1751 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1752 if (!ShAmt)
1753 break;
Owen Anderson7adf8622011-04-13 23:22:23 +0000[diff] [blame]1754 SDValue Shift = In.getOperand(1);
1755 if (TLO.LegalTypes()) {
1756 uint64_t ShVal = ShAmt->getZExtValue();
1757 Shift =
1758 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1759 }
1760
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1761 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1762 OperandBitWidth - BitWidth);
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1763 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1764
1765 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1766 // None of the shifted in bits are needed. Add a truncate of the
1767 // shift input, then shift it.
1768 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1769 Op.getValueType(),
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1770 In.getOperand(0));
1771 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1772 Op.getValueType(),
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1773 NewTrunc,
Owen Anderson7adf8622011-04-13 23:22:23 +0000[diff] [blame]1774 Shift));
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1775 }
1776 break;
1777 }
1778 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1779
1780 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1781 break;
1782 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1783 case ISD::AssertZext: {
Owen Anderson7ab15f62011-09-03 00:26:49 +0000[diff] [blame]1784 // AssertZext demands all of the high bits, plus any of the low bits
1785 // demanded by its users.
1786 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1787 APInt InMask = APInt::getLowBitsSet(BitWidth,
1788 VT.getSizeInBits());
1789 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1790 KnownZero, KnownOne, TLO, Depth+1))
1791 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1792 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman400f75c2010-06-03 20:21:33 +0000[diff] [blame]1793
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1794 KnownZero |= ~InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1795 break;
1796 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1797 case ISD::BITCAST:
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1798 // If this is an FP->Int bitcast and if the sign bit is the only
1799 // thing demanded, turn this into a FGETSIGN.
Eli Friedmanca072a32011-12-15 02:07:20 +0000[diff] [blame]1800 if (!TLO.LegalOperations() &&
1801 !Op.getValueType().isVector() &&
Eli Friedman0948f0a2011-11-09 22:25:12 +0000[diff] [blame]1802 !Op.getOperand(0).getValueType().isVector() &&
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]1803 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1804 Op.getOperand(0).getValueType().isFloatingPoint()) {
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1805 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1806 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1807 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1808 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1809 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1810 // place. We expect the SHL to be eliminated by other optimizations.
Stuart Hastings090bf192011-06-01 18:32:25 +0000[diff] [blame]1811 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1812 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1813 if (!OpVTLegal && OpVTSizeInBits > 32)
Stuart Hastings090bf192011-06-01 18:32:25 +0000[diff] [blame]1814 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1815 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
Stuart Hastingsbdce3722011-06-01 14:04:17 +0000[diff] [blame]1816 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
Stuart Hastings3dfc4b122011-05-19 18:48:20 +0000[diff] [blame]1817 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1818 Op.getValueType(),
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1819 Sign, ShAmt));
1820 }
1821 }
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1822 break;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1823 case ISD::ADD:
1824 case ISD::MUL:
1825 case ISD::SUB: {
1826 // Add, Sub, and Mul don't demand any bits in positions beyond that
1827 // of the highest bit demanded of them.
1828 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1829 BitWidth - NewMask.countLeadingZeros());
1830 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1831 KnownOne2, TLO, Depth+1))
1832 return true;
1833 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1834 KnownOne2, TLO, Depth+1))
1835 return true;
1836 // See if the operation should be performed at a smaller bit width.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1837 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1838 return true;
1839 }
1840 // FALL THROUGH
Dan Gohman54eed372008-05-06 00:53:29 +0000[diff] [blame]1841 default:
Chris Lattner1482b5f2006-04-02 06:15:09 +0000[diff] [blame]1842 // Just use ComputeMaskedBits to compute output bits.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1843 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
Chris Lattnera6bc5a42006-02-27 01:00:42 +0000[diff] [blame]1844 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1845 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1846
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1847 // If we know the value of all of the demanded bits, return this as a
1848 // constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1849 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1850 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1851
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1852 return false;
1853}
1854
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1855/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1856/// in Mask are known to be either zero or one and return them in the
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1857/// KnownZero/KnownOne bitsets.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1858void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1859 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]1860 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1861 const SelectionDAG &DAG,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1862 unsigned Depth) const {
Chris Lattner1b5232a2006-04-02 06:19:46 +0000[diff] [blame]1863 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1864 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1865 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1866 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1867 "Should use MaskedValueIsZero if you don't know whether Op"
1868 " is a target node!");
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1869 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]1870}
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]1871
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1872/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1873/// targets that want to expose additional information about sign bits to the
1874/// DAG Combiner.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1875unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1876 unsigned Depth) const {
1877 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1878 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1879 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1880 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1881 "Should use ComputeNumSignBits if you don't know whether Op"
1882 " is a target node!");
1883 return 1;
1884}
1885
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1886/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1887/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1888/// determine which bit is set.
1889///
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1890static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1891 // A left-shift of a constant one will have exactly one bit set, because
1892 // shifting the bit off the end is undefined.
1893 if (Val.getOpcode() == ISD::SHL)
1894 if (ConstantSDNode *C =
1895 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1896 if (C->getAPIntValue() == 1)
1897 return true;
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1898
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1899 // Similarly, a right-shift of a constant sign-bit will have exactly
1900 // one bit set.
1901 if (Val.getOpcode() == ISD::SRL)
1902 if (ConstantSDNode *C =
1903 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1904 if (C->getAPIntValue().isSignBit())
1905 return true;
1906
1907 // More could be done here, though the above checks are enough
1908 // to handle some common cases.
1909
1910 // Fall back to ComputeMaskedBits to catch other known cases.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1911 EVT OpVT = Val.getValueType();
Dan Gohman5b870af2010-03-02 02:14:38 +0000[diff] [blame]1912 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1913 APInt KnownZero, KnownOne;
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1914 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1915 return (KnownZero.countPopulation() == BitWidth - 1) &&
1916 (KnownOne.countPopulation() == 1);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1917}
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1918
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1919/// SimplifySetCC - Try to simplify a setcc built with the specified operands
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1920/// and cc. If it is unable to simplify it, return a null SDValue.
1921SDValue
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1922TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1923 ISD::CondCode Cond, bool foldBooleans,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1924 DAGCombinerInfo &DCI, DebugLoc dl) const {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1925 SelectionDAG &DAG = DCI.DAG;
1926
1927 // These setcc operations always fold.
1928 switch (Cond) {
1929 default: break;
1930 case ISD::SETFALSE:
1931 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1932 case ISD::SETTRUE:
1933 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1934 }
1935
Chris Lattner7a2bdde2011-04-15 05:18:47 +0000[diff] [blame]1936 // Ensure that the constant occurs on the RHS, and fold constant
1937 // comparisons.
1938 if (isa<ConstantSDNode>(N0.getNode()))
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1939 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]1940
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1941 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
Dan Gohman6c6cd1c2008-03-03 22:22:56 +0000[diff] [blame]1942 const APInt &C1 = N1C->getAPIntValue();
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1943
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1944 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1945 // equality comparison, then we're just comparing whether X itself is
1946 // zero.
1947 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1948 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1949 N0.getOperand(1).getOpcode() == ISD::Constant) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1950 const APInt &ShAmt
1951 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1952 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1953 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1954 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1955 // (srl (ctlz x), 5) == 0 -> X != 0
1956 // (srl (ctlz x), 5) != 1 -> X != 0
1957 Cond = ISD::SETNE;
1958 } else {
1959 // (srl (ctlz x), 5) != 0 -> X == 0
1960 // (srl (ctlz x), 5) == 1 -> X == 0
1961 Cond = ISD::SETEQ;
1962 }
1963 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1964 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1965 Zero, Cond);
1966 }
1967 }
1968
Benjamin Kramerd8228922011-01-17 12:04:57 +0000[diff] [blame]1969 SDValue CTPOP = N0;
1970 // Look through truncs that don't change the value of a ctpop.
1971 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1972 CTPOP = N0.getOperand(0);
1973
1974 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
Benjamin Kramerc9b6a3e2011-01-17 18:00:28 +0000[diff] [blame]1975 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
Benjamin Kramerd8228922011-01-17 12:04:57 +0000[diff] [blame]1976 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1977 EVT CTVT = CTPOP.getValueType();
1978 SDValue CTOp = CTPOP.getOperand(0);
1979
1980 // (ctpop x) u< 2 -> (x & x-1) == 0
1981 // (ctpop x) u> 1 -> (x & x-1) != 0
1982 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1983 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1984 DAG.getConstant(1, CTVT));
1985 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1986 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1987 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1988 }
1989
1990 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1991 }
1992
Benjamin Kramere7cf0622011-04-22 18:47:44 +0000[diff] [blame]1993 // (zext x) == C --> x == (trunc C)
1994 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1995 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1996 unsigned MinBits = N0.getValueSizeInBits();
1997 SDValue PreZExt;
1998 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1999 // ZExt
2000 MinBits = N0->getOperand(0).getValueSizeInBits();
2001 PreZExt = N0->getOperand(0);
2002 } else if (N0->getOpcode() == ISD::AND) {
2003 // DAGCombine turns costly ZExts into ANDs
2004 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
2005 if ((C->getAPIntValue()+1).isPowerOf2()) {
2006 MinBits = C->getAPIntValue().countTrailingOnes();
2007 PreZExt = N0->getOperand(0);
2008 }
2009 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
2010 // ZEXTLOAD
2011 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
2012 MinBits = LN0->getMemoryVT().getSizeInBits();
2013 PreZExt = N0;
2014 }
2015 }
2016
2017 // Make sure we're not loosing bits from the constant.
2018 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
2019 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2020 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2021 // Will get folded away.
2022 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2023 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
2024 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2025 }
2026 }
2027 }
2028
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2029 // If the LHS is '(and load, const)', the RHS is 0,
2030 // the test is for equality or unsigned, and all 1 bits of the const are
2031 // in the same partial word, see if we can shorten the load.
2032 if (DCI.isBeforeLegalize() &&
2033 N0.getOpcode() == ISD::AND && C1 == 0 &&
2034 N0.getNode()->hasOneUse() &&
2035 isa<LoadSDNode>(N0.getOperand(0)) &&
2036 N0.getOperand(0).getNode()->hasOneUse() &&
2037 isa<ConstantSDNode>(N0.getOperand(1))) {
2038 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2039 APInt bestMask;
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2040 unsigned bestWidth = 0, bestOffset = 0;
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2041 if (!Lod->isVolatile() && Lod->isUnindexed()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2042 unsigned origWidth = N0.getValueType().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2043 unsigned maskWidth = origWidth;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2044 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2045 // 8 bits, but have to be careful...
2046 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2047 origWidth = Lod->getMemoryVT().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2048 const APInt &Mask =
2049 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2050 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2051 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2052 for (unsigned offset=0; offset<origWidth/width; offset++) {
2053 if ((newMask & Mask) == Mask) {
2054 if (!TD->isLittleEndian())
2055 bestOffset = (origWidth/width - offset - 1) * (width/8);
2056 else
2057 bestOffset = (uint64_t)offset * (width/8);
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2058 bestMask = Mask.lshr(offset * (width/8) * 8);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2059 bestWidth = width;
2060 break;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]2061 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2062 newMask = newMask << width;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]2063 }
2064 }
2065 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2066 if (bestWidth) {
Chris Lattnerc0c7fca2011-04-14 04:12:47 +0000[diff] [blame]2067 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2068 if (newVT.isRound()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2069 EVT PtrType = Lod->getOperand(1).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2070 SDValue Ptr = Lod->getBasePtr();
2071 if (bestOffset != 0)
2072 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2073 DAG.getConstant(bestOffset, PtrType));
2074 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2075 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
Chris Lattnerecf42c42010-09-21 16:36:31 +0000[diff] [blame]2076 Lod->getPointerInfo().getWithOffset(bestOffset),
Pete Cooperd752e0f2011-11-08 18:42:53 +0000[diff] [blame]2077 false, false, false, NewAlign);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2078 return DAG.getSetCC(dl, VT,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2079 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2080 DAG.getConstant(bestMask.trunc(bestWidth),
2081 newVT)),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2082 DAG.getConstant(0LL, newVT), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2083 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2084 }
2085 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2086
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2087 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2088 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2089 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2090
2091 // If the comparison constant has bits in the upper part, the
2092 // zero-extended value could never match.
2093 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2094 C1.getBitWidth() - InSize))) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2095 switch (Cond) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2096 case ISD::SETUGT:
2097 case ISD::SETUGE:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2098 case ISD::SETEQ: return DAG.getConstant(0, VT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2099 case ISD::SETULT:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2100 case ISD::SETULE:
2101 case ISD::SETNE: return DAG.getConstant(1, VT);
2102 case ISD::SETGT:
2103 case ISD::SETGE:
2104 // True if the sign bit of C1 is set.
2105 return DAG.getConstant(C1.isNegative(), VT);
2106 case ISD::SETLT:
2107 case ISD::SETLE:
2108 // True if the sign bit of C1 isn't set.
2109 return DAG.getConstant(C1.isNonNegative(), VT);
2110 default:
Jakob Stoklund Olesen78d12642009-07-24 18:22:59 +0000[diff] [blame]2111 break;
2112 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2113 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2114
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2115 // Otherwise, we can perform the comparison with the low bits.
2116 switch (Cond) {
2117 case ISD::SETEQ:
2118 case ISD::SETNE:
2119 case ISD::SETUGT:
2120 case ISD::SETUGE:
2121 case ISD::SETULT:
2122 case ISD::SETULE: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2123 EVT newVT = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2124 if (DCI.isBeforeLegalizeOps() ||
2125 (isOperationLegal(ISD::SETCC, newVT) &&
2126 getCondCodeAction(Cond, newVT)==Legal))
2127 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]2128 DAG.getConstant(C1.trunc(InSize), newVT),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2129 Cond);
2130 break;
2131 }
2132 default:
2133 break; // todo, be more careful with signed comparisons
2134 }
2135 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2136 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2137 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2138 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2139 EVT ExtDstTy = N0.getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2140 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2141
Eli Friedmanad78a882010-07-30 06:44:31 +0000[diff] [blame]2142 // If the constant doesn't fit into the number of bits for the source of
2143 // the sign extension, it is impossible for both sides to be equal.
2144 if (C1.getMinSignedBits() > ExtSrcTyBits)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2145 return DAG.getConstant(Cond == ISD::SETNE, VT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2146
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2147 SDValue ZextOp;
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2148 EVT Op0Ty = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2149 if (Op0Ty == ExtSrcTy) {
2150 ZextOp = N0.getOperand(0);
2151 } else {
2152 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2153 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2154 DAG.getConstant(Imm, Op0Ty));
2155 }
2156 if (!DCI.isCalledByLegalizer())
2157 DCI.AddToWorklist(ZextOp.getNode());
2158 // Otherwise, make this a use of a zext.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2159 return DAG.getSetCC(dl, VT, ZextOp,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2160 DAG.getConstant(C1 & APInt::getLowBitsSet(
2161 ExtDstTyBits,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2162 ExtSrcTyBits),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2163 ExtDstTy),
2164 Cond);
2165 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2166 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2167 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2168 if (N0.getOpcode() == ISD::SETCC &&
2169 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2170 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2171 if (TrueWhenTrue)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2172 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2173 // Invert the condition.
2174 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2175 CC = ISD::getSetCCInverse(CC,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2176 N0.getOperand(0).getValueType().isInteger());
2177 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2178 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2179
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2180 if ((N0.getOpcode() == ISD::XOR ||
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2181 (N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2182 N0.getOperand(0).getOpcode() == ISD::XOR &&
2183 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2184 isa<ConstantSDNode>(N0.getOperand(1)) &&
2185 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2186 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2187 // can only do this if the top bits are known zero.
2188 unsigned BitWidth = N0.getValueSizeInBits();
2189 if (DAG.MaskedValueIsZero(N0,
2190 APInt::getHighBitsSet(BitWidth,
2191 BitWidth-1))) {
2192 // Okay, get the un-inverted input value.
2193 SDValue Val;
2194 if (N0.getOpcode() == ISD::XOR)
2195 Val = N0.getOperand(0);
2196 else {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2197 assert(N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2198 N0.getOperand(0).getOpcode() == ISD::XOR);
2199 // ((X^1)&1)^1 -> X & 1
2200 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2201 N0.getOperand(0).getOperand(0),
2202 N0.getOperand(1));
2203 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2204
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2205 return DAG.getSetCC(dl, VT, Val, N1,
2206 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2207 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2208 } else if (N1C->getAPIntValue() == 1 &&
2209 (VT == MVT::i1 ||
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]2210 getBooleanContents(false) == ZeroOrOneBooleanContent)) {
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2211 SDValue Op0 = N0;
2212 if (Op0.getOpcode() == ISD::TRUNCATE)
2213 Op0 = Op0.getOperand(0);
2214
2215 if ((Op0.getOpcode() == ISD::XOR) &&
2216 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2217 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2218 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2219 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2220 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2221 Cond);
2222 } else if (Op0.getOpcode() == ISD::AND &&
2223 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2224 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2225 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2226 if (Op0.getValueType().bitsGT(VT))
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2227 Op0 = DAG.getNode(ISD::AND, dl, VT,
2228 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2229 DAG.getConstant(1, VT));
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2230 else if (Op0.getValueType().bitsLT(VT))
2231 Op0 = DAG.getNode(ISD::AND, dl, VT,
2232 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2233 DAG.getConstant(1, VT));
2234
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2235 return DAG.getSetCC(dl, VT, Op0,
2236 DAG.getConstant(0, Op0.getValueType()),
2237 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2238 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2239 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2240 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2241
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2242 APInt MinVal, MaxVal;
2243 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2244 if (ISD::isSignedIntSetCC(Cond)) {
2245 MinVal = APInt::getSignedMinValue(OperandBitSize);
2246 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2247 } else {
2248 MinVal = APInt::getMinValue(OperandBitSize);
2249 MaxVal = APInt::getMaxValue(OperandBitSize);
2250 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2251
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2252 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2253 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2254 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2255 // X >= C0 --> X > (C0-1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2256 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2257 DAG.getConstant(C1-1, N1.getValueType()),
2258 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2259 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2260
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2261 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2262 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2263 // X <= C0 --> X < (C0+1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2264 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2265 DAG.getConstant(C1+1, N1.getValueType()),
2266 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2267 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2268
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2269 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2270 return DAG.getConstant(0, VT); // X < MIN --> false
2271 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2272 return DAG.getConstant(1, VT); // X >= MIN --> true
2273 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2274 return DAG.getConstant(0, VT); // X > MAX --> false
2275 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2276 return DAG.getConstant(1, VT); // X <= MAX --> true
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2277
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2278 // Canonicalize setgt X, Min --> setne X, Min
2279 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2280 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2281 // Canonicalize setlt X, Max --> setne X, Max
2282 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2283 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2284
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2285 // If we have setult X, 1, turn it into seteq X, 0
2286 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2287 return DAG.getSetCC(dl, VT, N0,
2288 DAG.getConstant(MinVal, N0.getValueType()),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2289 ISD::SETEQ);
2290 // If we have setugt X, Max-1, turn it into seteq X, Max
2291 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2292 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2293 DAG.getConstant(MaxVal, N0.getValueType()),
2294 ISD::SETEQ);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2295
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2296 // If we have "setcc X, C0", check to see if we can shrink the immediate
2297 // by changing cc.
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2298
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2299 // SETUGT X, SINTMAX -> SETLT X, 0
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2300 if (Cond == ISD::SETUGT &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2301 C1 == APInt::getSignedMaxValue(OperandBitSize))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2302 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2303 DAG.getConstant(0, N1.getValueType()),
2304 ISD::SETLT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2305
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2306 // SETULT X, SINTMIN -> SETGT X, -1
2307 if (Cond == ISD::SETULT &&
2308 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2309 SDValue ConstMinusOne =
2310 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2311 N1.getValueType());
2312 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2313 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2314
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2315 // Fold bit comparisons when we can.
2316 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2317 (VT == N0.getValueType() ||
2318 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2319 N0.getOpcode() == ISD::AND)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2320 if (ConstantSDNode *AndRHS =
2321 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2322 EVT ShiftTy = DCI.isBeforeLegalize() ?
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2323 getPointerTy() : getShiftAmountTy(N0.getValueType());
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2324 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2325 // Perform the xform if the AND RHS is a single bit.
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2326 if (AndRHS->getAPIntValue().isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2327 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2328 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2329 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2330 }
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2331 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2332 // (X & 8) == 8 --> (X & 8) >> 3
2333 // Perform the xform if C1 is a single bit.
2334 if (C1.isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2335 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2336 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2337 DAG.getConstant(C1.logBase2(), ShiftTy)));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2338 }
2339 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2340 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2341 }
2342
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2343 if (isa<ConstantFPSDNode>(N0.getNode())) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2344 // Constant fold or commute setcc.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2345 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2346 if (O.getNode()) return O;
2347 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2348 // If the RHS of an FP comparison is a constant, simplify it away in
2349 // some cases.
2350 if (CFP->getValueAPF().isNaN()) {
2351 // If an operand is known to be a nan, we can fold it.
2352 switch (ISD::getUnorderedFlavor(Cond)) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2353 default: llvm_unreachable("Unknown flavor!");
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2354 case 0: // Known false.
2355 return DAG.getConstant(0, VT);
2356 case 1: // Known true.
2357 return DAG.getConstant(1, VT);
Chris Lattner1c3e1e22007-12-30 21:21:10 +0000[diff] [blame]2358 case 2: // Undefined.
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]2359 return DAG.getUNDEF(VT);
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2360 }
2361 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2362
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2363 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2364 // constant if knowing that the operand is non-nan is enough. We prefer to
2365 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2366 // materialize 0.0.
2367 if (Cond == ISD::SETO || Cond == ISD::SETUO)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2368 return DAG.getSetCC(dl, VT, N0, N0, Cond);
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2369
2370 // If the condition is not legal, see if we can find an equivalent one
2371 // which is legal.
2372 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2373 // If the comparison was an awkward floating-point == or != and one of
2374 // the comparison operands is infinity or negative infinity, convert the
2375 // condition to a less-awkward <= or >=.
2376 if (CFP->getValueAPF().isInfinity()) {
2377 if (CFP->getValueAPF().isNegative()) {
2378 if (Cond == ISD::SETOEQ &&
2379 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2380 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2381 if (Cond == ISD::SETUEQ &&
2382 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2383 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2384 if (Cond == ISD::SETUNE &&
2385 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2386 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2387 if (Cond == ISD::SETONE &&
2388 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2389 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2390 } else {
2391 if (Cond == ISD::SETOEQ &&
2392 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2393 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2394 if (Cond == ISD::SETUEQ &&
2395 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2396 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2397 if (Cond == ISD::SETUNE &&
2398 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2399 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2400 if (Cond == ISD::SETONE &&
2401 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2402 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2403 }
2404 }
2405 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2406 }
2407
2408 if (N0 == N1) {
2409 // We can always fold X == X for integer setcc's.
Chad Rosier9dbb0182012-04-03 20:11:24 +0000[diff] [blame]2410 if (N0.getValueType().isInteger()) {
2411 switch (getBooleanContents(N0.getValueType().isVector())) {
Chad Rosier9dbb0182012-04-03 20:11:24 +0000[diff] [blame]2412 case UndefinedBooleanContent:
2413 case ZeroOrOneBooleanContent:
2414 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2415 case ZeroOrNegativeOneBooleanContent:
2416 return DAG.getConstant(ISD::isTrueWhenEqual(Cond) ? -1 : 0, VT);
2417 }
2418 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2419 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2420 if (UOF == 2) // FP operators that are undefined on NaNs.
2421 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2422 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2423 return DAG.getConstant(UOF, VT);
2424 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2425 // if it is not already.
2426 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2427 if (NewCond != Cond)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2428 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2429 }
2430
2431 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2432 N0.getValueType().isInteger()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2433 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2434 N0.getOpcode() == ISD::XOR) {
2435 // Simplify (X+Y) == (X+Z) --> Y == Z
2436 if (N0.getOpcode() == N1.getOpcode()) {
2437 if (N0.getOperand(0) == N1.getOperand(0))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2438 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2439 if (N0.getOperand(1) == N1.getOperand(1))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2440 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2441 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2442 // If X op Y == Y op X, try other combinations.
2443 if (N0.getOperand(0) == N1.getOperand(1))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2444 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2445 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2446 if (N0.getOperand(1) == N1.getOperand(0))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2447 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2448 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2449 }
2450 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2451
Jakob Stoklund Olesen740cd652012-04-05 20:30:20 +0000[diff] [blame]2452 // If RHS is a legal immediate value for a compare instruction, we need
2453 // to be careful about increasing register pressure needlessly.
2454 bool LegalRHSImm = false;
2455
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2456 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2457 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2458 // Turn (X+C1) == C2 --> X == C2-C1
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2459 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2460 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2461 DAG.getConstant(RHSC->getAPIntValue()-
2462 LHSR->getAPIntValue(),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2463 N0.getValueType()), Cond);
2464 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2465
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2466 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2467 if (N0.getOpcode() == ISD::XOR)
2468 // If we know that all of the inverted bits are zero, don't bother
2469 // performing the inversion.
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2470 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2471 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2472 DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2473 DAG.getConstant(LHSR->getAPIntValue() ^
2474 RHSC->getAPIntValue(),
2475 N0.getValueType()),
2476 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2477 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2478
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2479 // Turn (C1-X) == C2 --> X == C1-C2
2480 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2481 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2482 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2483 DAG.getSetCC(dl, VT, N0.getOperand(1),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2484 DAG.getConstant(SUBC->getAPIntValue() -
2485 RHSC->getAPIntValue(),
2486 N0.getValueType()),
2487 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2488 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2489 }
Jakob Stoklund Olesen740cd652012-04-05 20:30:20 +0000[diff] [blame]2490
2491 // Could RHSC fold directly into a compare?
2492 if (RHSC->getValueType(0).getSizeInBits() <= 64)
2493 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2494 }
2495
2496 // Simplify (X+Z) == X --> Z == 0
Jakob Stoklund Olesen740cd652012-04-05 20:30:20 +0000[diff] [blame]2497 // Don't do this if X is an immediate that can fold into a cmp
2498 // instruction and X+Z has other uses. It could be an induction variable
2499 // chain, and the transform would increase register pressure.
2500 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
2501 if (N0.getOperand(0) == N1)
2502 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2503 DAG.getConstant(0, N0.getValueType()), Cond);
2504 if (N0.getOperand(1) == N1) {
2505 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2506 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2507 DAG.getConstant(0, N0.getValueType()), Cond);
2508 else if (N0.getNode()->hasOneUse()) {
2509 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2510 // (Z-X) == X --> Z == X<<1
2511 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2512 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
Jakob Stoklund Olesen740cd652012-04-05 20:30:20 +0000[diff] [blame]2513 if (!DCI.isCalledByLegalizer())
2514 DCI.AddToWorklist(SH.getNode());
2515 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2516 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2517 }
2518 }
2519 }
2520
2521 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2522 N1.getOpcode() == ISD::XOR) {
2523 // Simplify X == (X+Z) --> Z == 0
2524 if (N1.getOperand(0) == N0) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2525 return DAG.getSetCC(dl, VT, N1.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2526 DAG.getConstant(0, N1.getValueType()), Cond);
2527 } else if (N1.getOperand(1) == N0) {
2528 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2529 return DAG.getSetCC(dl, VT, N1.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2530 DAG.getConstant(0, N1.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2531 } else if (N1.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2532 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2533 // X == (Z-X) --> X<<1 == Z
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2534 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2535 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2536 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2537 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2538 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2539 }
2540 }
2541 }
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2542
Dan Gohman2c65c3d2009-01-29 16:18:12 +0000[diff] [blame]2543 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2544 // Note that where y is variable and is known to have at most
2545 // one bit set (for example, if it is z&1) we cannot do this;
2546 // the expressions are not equivalent when y==0.
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2547 if (N0.getOpcode() == ISD::AND)
2548 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2549 if (ValueHasExactlyOneBitSet(N1, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2550 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2551 SDValue Zero = DAG.getConstant(0, N1.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2552 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2553 }
2554 }
2555 if (N1.getOpcode() == ISD::AND)
2556 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2557 if (ValueHasExactlyOneBitSet(N0, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2558 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2559 SDValue Zero = DAG.getConstant(0, N0.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2560 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2561 }
2562 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2563 }
2564
2565 // Fold away ALL boolean setcc's.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2566 SDValue Temp;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2567 if (N0.getValueType() == MVT::i1 && foldBooleans) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2568 switch (Cond) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2569 default: llvm_unreachable("Unknown integer setcc!");
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2570 case ISD::SETEQ: // X == Y -> ~(X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2571 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2572 N0 = DAG.getNOT(dl, Temp, MVT::i1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2573 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2574 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2575 break;
2576 case ISD::SETNE: // X != Y --> (X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2577 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2578 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2579 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2580 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2581 Temp = DAG.getNOT(dl, N0, MVT::i1);
2582 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2583 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2584 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2585 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2586 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2587 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2588 Temp = DAG.getNOT(dl, N1, MVT::i1);
2589 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2590 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2591 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2592 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2593 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2594 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2595 Temp = DAG.getNOT(dl, N0, MVT::i1);
2596 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2597 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2598 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2599 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2600 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2601 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2602 Temp = DAG.getNOT(dl, N1, MVT::i1);
2603 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2604 break;
2605 }
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2606 if (VT != MVT::i1) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2607 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2608 DCI.AddToWorklist(N0.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2609 // FIXME: If running after legalize, we probably can't do this.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2610 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2611 }
2612 return N0;
2613 }
2614
2615 // Could not fold it.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2616 return SDValue();
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2617}
2618
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2619/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2620/// node is a GlobalAddress + offset.
Chris Lattner0a9481f2011-02-13 22:25:43 +0000[diff] [blame]2621bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2622 int64_t &Offset) const {
2623 if (isa<GlobalAddressSDNode>(N)) {
Dan Gohman9ea3f562008-06-09 22:05:52 +0000[diff] [blame]2624 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2625 GA = GASD->getGlobal();
2626 Offset += GASD->getOffset();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2627 return true;
2628 }
2629
2630 if (N->getOpcode() == ISD::ADD) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2631 SDValue N1 = N->getOperand(0);
2632 SDValue N2 = N->getOperand(1);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2633 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2634 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2635 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2636 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2637 return true;
2638 }
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2639 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2640 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2641 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2642 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2643 return true;
2644 }
2645 }
2646 }
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2647
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2648 return false;
2649}
2650
2651
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2652SDValue TargetLowering::
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2653PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2654 // Default implementation: no optimization.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2655 return SDValue();
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2656}
2657
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2658//===----------------------------------------------------------------------===//
2659// Inline Assembler Implementation Methods
2660//===----------------------------------------------------------------------===//
2661
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2662
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2663TargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2664TargetLowering::getConstraintType(const std::string &Constraint) const {
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2665 if (Constraint.size() == 1) {
2666 switch (Constraint[0]) {
2667 default: break;
2668 case 'r': return C_RegisterClass;
2669 case 'm': // memory
2670 case 'o': // offsetable
2671 case 'V': // not offsetable
2672 return C_Memory;
2673 case 'i': // Simple Integer or Relocatable Constant
2674 case 'n': // Simple Integer
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2675 case 'E': // Floating Point Constant
2676 case 'F': // Floating Point Constant
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2677 case 's': // Relocatable Constant
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2678 case 'p': // Address.
Chris Lattnerc13dd1c2007-03-25 04:35:41 +0000[diff] [blame]2679 case 'X': // Allow ANY value.
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2680 case 'I': // Target registers.
2681 case 'J':
2682 case 'K':
2683 case 'L':
2684 case 'M':
2685 case 'N':
2686 case 'O':
2687 case 'P':
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2688 case '<':
2689 case '>':
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2690 return C_Other;
2691 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2692 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2693
2694 if (Constraint.size() > 1 && Constraint[0] == '{' &&
Chris Lattner065421f2007-03-25 02:18:14 +0000[diff] [blame]2695 Constraint[Constraint.size()-1] == '}')
2696 return C_Register;
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2697 return C_Unknown;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2698}
2699
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2700/// LowerXConstraint - try to replace an X constraint, which matches anything,
2701/// with another that has more specific requirements based on the type of the
2702/// corresponding operand.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2703const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2704 if (ConstraintVT.isInteger())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2705 return "r";
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2706 if (ConstraintVT.isFloatingPoint())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2707 return "f"; // works for many targets
2708 return 0;
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2709}
2710
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2711/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2712/// vector. If it is invalid, don't add anything to Ops.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2713void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2714 std::string &Constraint,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2715 std::vector<SDValue> &Ops,
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2716 SelectionDAG &DAG) const {
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2717
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2718 if (Constraint.length() > 1) return;
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2719
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2720 char ConstraintLetter = Constraint[0];
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2721 switch (ConstraintLetter) {
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2722 default: break;
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2723 case 'X': // Allows any operand; labels (basic block) use this.
2724 if (Op.getOpcode() == ISD::BasicBlock) {
2725 Ops.push_back(Op);
2726 return;
2727 }
2728 // fall through
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2729 case 'i': // Simple Integer or Relocatable Constant
2730 case 'n': // Simple Integer
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2731 case 's': { // Relocatable Constant
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2732 // These operands are interested in values of the form (GV+C), where C may
2733 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2734 // is possible and fine if either GV or C are missing.
2735 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2736 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2737
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2738 // If we have "(add GV, C)", pull out GV/C
2739 if (Op.getOpcode() == ISD::ADD) {
2740 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2741 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2742 if (C == 0 || GA == 0) {
2743 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2744 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2745 }
2746 if (C == 0 || GA == 0)
2747 C = 0, GA = 0;
2748 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2749
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2750 // If we find a valid operand, map to the TargetXXX version so that the
2751 // value itself doesn't get selected.
2752 if (GA) { // Either &GV or &GV+C
2753 if (ConstraintLetter != 'n') {
2754 int64_t Offs = GA->getOffset();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2755 if (C) Offs += C->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2756 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
Devang Patel07538ad2010-07-15 18:45:27 +0000[diff] [blame]2757 C ? C->getDebugLoc() : DebugLoc(),
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2758 Op.getValueType(), Offs));
2759 return;
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2760 }
2761 }
2762 if (C) { // just C, no GV.
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2763 // Simple constants are not allowed for 's'.
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2764 if (ConstraintLetter != 's') {
Dale Johannesen78e3e522009-02-12 20:58:09 +0000[diff] [blame]2765 // gcc prints these as sign extended. Sign extend value to 64 bits
2766 // now; without this it would get ZExt'd later in
2767 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2768 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2769 MVT::i64));
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2770 return;
2771 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2772 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2773 break;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2774 }
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2775 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2776}
2777
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2778std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
Chris Lattner4217ca8dc2006-02-21 23:11:00 +0000[diff] [blame]2779getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2780 EVT VT) const {
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2781 if (Constraint[0] != '{')
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2782 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
Chris Lattnera55079a2006-02-01 01:29:47 +0000[diff] [blame]2783 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2784
2785 // Remove the braces from around the name.
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2786 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2787
2788 // Figure out which register class contains this reg.
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]2789 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2790 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2791 E = RI->regclass_end(); RCI != E; ++RCI) {
2792 const TargetRegisterClass *RC = *RCI;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2793
2794 // If none of the value types for this register class are valid, we
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]2795 // can't use it. For example, 64-bit reg classes on 32-bit targets.
Jakob Stoklund Olesen22e8a362011-10-12 01:24:51 +0000[diff] [blame]2796 if (!isLegalRC(RC))
2797 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2798
2799 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2800 I != E; ++I) {
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2801 if (RegName.equals_lower(RI->getName(*I)))
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2802 return std::make_pair(*I, RC);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2803 }
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2804 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2805
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2806 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2807}
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]2808
2809//===----------------------------------------------------------------------===//
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2810// Constraint Selection.
2811
Chris Lattner6bdcda32008-10-17 16:47:46 +0000[diff] [blame]2812/// isMatchingInputConstraint - Return true of this is an input operand that is
2813/// a matching constraint like "4".
2814bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]2815 assert(!ConstraintCode.empty() && "No known constraint!");
2816 return isdigit(ConstraintCode[0]);
2817}
2818
2819/// getMatchedOperand - If this is an input matching constraint, this method
2820/// returns the output operand it matches.
2821unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2822 assert(!ConstraintCode.empty() && "No known constraint!");
2823 return atoi(ConstraintCode.c_str());
2824}
2825
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2826
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2827/// ParseConstraints - Split up the constraint string from the inline
2828/// assembly value into the specific constraints and their prefixes,
2829/// and also tie in the associated operand values.
2830/// If this returns an empty vector, and if the constraint string itself
2831/// isn't empty, there was an error parsing.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2832TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2833 ImmutableCallSite CS) const {
2834 /// ConstraintOperands - Information about all of the constraints.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2835 AsmOperandInfoVector ConstraintOperands;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2836 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2837 unsigned maCount = 0; // Largest number of multiple alternative constraints.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2838
2839 // Do a prepass over the constraints, canonicalizing them, and building up the
2840 // ConstraintOperands list.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2841 InlineAsm::ConstraintInfoVector
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2842 ConstraintInfos = IA->ParseConstraints();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2843
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2844 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2845 unsigned ResNo = 0; // ResNo - The result number of the next output.
2846
2847 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2848 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2849 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2850
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2851 // Update multiple alternative constraint count.
2852 if (OpInfo.multipleAlternatives.size() > maCount)
2853 maCount = OpInfo.multipleAlternatives.size();
2854
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2855 OpInfo.ConstraintVT = MVT::Other;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2856
2857 // Compute the value type for each operand.
2858 switch (OpInfo.Type) {
2859 case InlineAsm::isOutput:
2860 // Indirect outputs just consume an argument.
2861 if (OpInfo.isIndirect) {
2862 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2863 break;
2864 }
2865
2866 // The return value of the call is this value. As such, there is no
2867 // corresponding argument.
2868 assert(!CS.getType()->isVoidTy() &&
2869 "Bad inline asm!");
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2870 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2871 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2872 } else {
2873 assert(ResNo == 0 && "Asm only has one result!");
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2874 OpInfo.ConstraintVT = getValueType(CS.getType());
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2875 }
2876 ++ResNo;
2877 break;
2878 case InlineAsm::isInput:
2879 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2880 break;
2881 case InlineAsm::isClobber:
2882 // Nothing to do.
2883 break;
2884 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2885
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2886 if (OpInfo.CallOperandVal) {
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2887 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2888 if (OpInfo.isIndirect) {
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2889 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2890 if (!PtrTy)
2891 report_fatal_error("Indirect operand for inline asm not a pointer!");
2892 OpTy = PtrTy->getElementType();
2893 }
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2894
Eric Christophercef81b72011-05-09 20:04:43 +0000[diff] [blame]2895 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2896 if (StructType *STy = dyn_cast<StructType>(OpTy))
Eric Christophercef81b72011-05-09 20:04:43 +0000[diff] [blame]2897 if (STy->getNumElements() == 1)
2898 OpTy = STy->getElementType(0);
2899
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2900 // If OpTy is not a single value, it may be a struct/union that we
2901 // can tile with integers.
2902 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2903 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2904 switch (BitSize) {
2905 default: break;
2906 case 1:
2907 case 8:
2908 case 16:
2909 case 32:
2910 case 64:
2911 case 128:
Dale Johannesen71365d32010-11-09 01:15:07 +0000[diff] [blame]2912 OpInfo.ConstraintVT =
2913 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2914 break;
2915 }
2916 } else if (dyn_cast<PointerType>(OpTy)) {
2917 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
2918 } else {
2919 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2920 }
2921 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2922 }
2923
2924 // If we have multiple alternative constraints, select the best alternative.
2925 if (ConstraintInfos.size()) {
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2926 if (maCount) {
2927 unsigned bestMAIndex = 0;
2928 int bestWeight = -1;
2929 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2930 int weight = -1;
2931 unsigned maIndex;
2932 // Compute the sums of the weights for each alternative, keeping track
2933 // of the best (highest weight) one so far.
2934 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2935 int weightSum = 0;
2936 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2937 cIndex != eIndex; ++cIndex) {
2938 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2939 if (OpInfo.Type == InlineAsm::isClobber)
2940 continue;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2941
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2942 // If this is an output operand with a matching input operand,
2943 // look up the matching input. If their types mismatch, e.g. one
2944 // is an integer, the other is floating point, or their sizes are
2945 // different, flag it as an maCantMatch.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2946 if (OpInfo.hasMatchingInput()) {
2947 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2948 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2949 if ((OpInfo.ConstraintVT.isInteger() !=
2950 Input.ConstraintVT.isInteger()) ||
2951 (OpInfo.ConstraintVT.getSizeInBits() !=
2952 Input.ConstraintVT.getSizeInBits())) {
2953 weightSum = -1; // Can't match.
2954 break;
2955 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2956 }
2957 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2958 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2959 if (weight == -1) {
2960 weightSum = -1;
2961 break;
2962 }
2963 weightSum += weight;
2964 }
2965 // Update best.
2966 if (weightSum > bestWeight) {
2967 bestWeight = weightSum;
2968 bestMAIndex = maIndex;
2969 }
2970 }
2971
2972 // Now select chosen alternative in each constraint.
2973 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2974 cIndex != eIndex; ++cIndex) {
2975 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2976 if (cInfo.Type == InlineAsm::isClobber)
2977 continue;
2978 cInfo.selectAlternative(bestMAIndex);
2979 }
2980 }
2981 }
2982
2983 // Check and hook up tied operands, choose constraint code to use.
2984 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2985 cIndex != eIndex; ++cIndex) {
2986 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2987
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2988 // If this is an output operand with a matching input operand, look up the
2989 // matching input. If their types mismatch, e.g. one is an integer, the
2990 // other is floating point, or their sizes are different, flag it as an
2991 // error.
2992 if (OpInfo.hasMatchingInput()) {
2993 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2994
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2995 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
Eric Christopher5427ede2011-07-14 20:13:52 +0000[diff] [blame]2996 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
2997 getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT);
2998 std::pair<unsigned, const TargetRegisterClass*> InputRC =
2999 getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT);
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3000 if ((OpInfo.ConstraintVT.isInteger() !=
3001 Input.ConstraintVT.isInteger()) ||
Eric Christopher5427ede2011-07-14 20:13:52 +0000[diff] [blame]3002 (MatchRC.second != InputRC.second)) {
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3003 report_fatal_error("Unsupported asm: input constraint"
3004 " with a matching output constraint of"
3005 " incompatible type!");
3006 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3007 }
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3008
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3009 }
3010 }
3011
3012 return ConstraintOperands;
3013}
3014
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]3015
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3016/// getConstraintGenerality - Return an integer indicating how general CT
3017/// is.
3018static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3019 switch (CT) {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3020 case TargetLowering::C_Other:
3021 case TargetLowering::C_Unknown:
3022 return 0;
3023 case TargetLowering::C_Register:
3024 return 1;
3025 case TargetLowering::C_RegisterClass:
3026 return 2;
3027 case TargetLowering::C_Memory:
3028 return 3;
3029 }
Chandler Carruth732f05c2012-01-10 18:08:01 +0000[diff] [blame]3030 llvm_unreachable("Invalid constraint type");
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3031}
3032
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3033/// Examine constraint type and operand type and determine a weight value.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3034/// This object must already have been set up with the operand type
3035/// and the current alternative constraint selected.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3036TargetLowering::ConstraintWeight
3037 TargetLowering::getMultipleConstraintMatchWeight(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3038 AsmOperandInfo &info, int maIndex) const {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3039 InlineAsm::ConstraintCodeVector *rCodes;
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]3040 if (maIndex >= (int)info.multipleAlternatives.size())
3041 rCodes = &info.Codes;
3042 else
3043 rCodes = &info.multipleAlternatives[maIndex].Codes;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3044 ConstraintWeight BestWeight = CW_Invalid;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3045
3046 // Loop over the options, keeping track of the most general one.
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]3047 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3048 ConstraintWeight weight =
3049 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3050 if (weight > BestWeight)
3051 BestWeight = weight;
3052 }
3053
3054 return BestWeight;
3055}
3056
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3057/// Examine constraint type and operand type and determine a weight value.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3058/// This object must already have been set up with the operand type
3059/// and the current alternative constraint selected.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3060TargetLowering::ConstraintWeight
3061 TargetLowering::getSingleConstraintMatchWeight(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3062 AsmOperandInfo &info, const char *constraint) const {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3063 ConstraintWeight weight = CW_Invalid;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3064 Value *CallOperandVal = info.CallOperandVal;
3065 // If we don't have a value, we can't do a match,
3066 // but allow it at the lowest weight.
3067 if (CallOperandVal == NULL)
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3068 return CW_Default;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3069 // Look at the constraint type.
3070 switch (*constraint) {
3071 case 'i': // immediate integer.
3072 case 'n': // immediate integer with a known value.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3073 if (isa<ConstantInt>(CallOperandVal))
3074 weight = CW_Constant;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3075 break;
3076 case 's': // non-explicit intregal immediate.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3077 if (isa<GlobalValue>(CallOperandVal))
3078 weight = CW_Constant;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3079 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3080 case 'E': // immediate float if host format.
3081 case 'F': // immediate float.
3082 if (isa<ConstantFP>(CallOperandVal))
3083 weight = CW_Constant;
3084 break;
3085 case '<': // memory operand with autodecrement.
3086 case '>': // memory operand with autoincrement.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3087 case 'm': // memory operand.
3088 case 'o': // offsettable memory operand
3089 case 'V': // non-offsettable memory operand
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3090 weight = CW_Memory;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3091 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3092 case 'r': // general register.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3093 case 'g': // general register, memory operand or immediate integer.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3094 // note: Clang converts "g" to "imr".
3095 if (CallOperandVal->getType()->isIntegerTy())
3096 weight = CW_Register;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3097 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3098 case 'X': // any operand.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3099 default:
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3100 weight = CW_Default;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3101 break;
3102 }
3103 return weight;
3104}
3105
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3106/// ChooseConstraint - If there are multiple different constraints that we
3107/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
Chris Lattner24e1a9d2008-04-27 01:49:46 +0000[diff] [blame]3108/// This is somewhat tricky: constraints fall into four classes:
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3109/// Other -> immediates and magic values
3110/// Register -> one specific register
3111/// RegisterClass -> a group of regs
3112/// Memory -> memory
3113/// Ideally, we would pick the most specific constraint possible: if we have
3114/// something that fits into a register, we would pick it. The problem here
3115/// is that if we have something that could either be in a register or in
3116/// memory that use of the register could cause selection of *other*
3117/// operands to fail: they might only succeed if we pick memory. Because of
3118/// this the heuristic we use is:
3119///
3120/// 1) If there is an 'other' constraint, and if the operand is valid for
3121/// that constraint, use it. This makes us take advantage of 'i'
3122/// constraints when available.
3123/// 2) Otherwise, pick the most general constraint present. This prefers
3124/// 'm' over 'r', for example.
3125///
3126static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]3127 const TargetLowering &TLI,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3128 SDValue Op, SelectionDAG *DAG) {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3129 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3130 unsigned BestIdx = 0;
3131 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3132 int BestGenerality = -1;
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3133
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3134 // Loop over the options, keeping track of the most general one.
3135 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3136 TargetLowering::ConstraintType CType =
3137 TLI.getConstraintType(OpInfo.Codes[i]);
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3138
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3139 // If this is an 'other' constraint, see if the operand is valid for it.
3140 // For example, on X86 we might have an 'rI' constraint. If the operand
3141 // is an integer in the range [0..31] we want to use I (saving a load
3142 // of a register), otherwise we must use 'r'.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3143 if (CType == TargetLowering::C_Other && Op.getNode()) {
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3144 assert(OpInfo.Codes[i].size() == 1 &&
3145 "Unhandled multi-letter 'other' constraint");
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3146 std::vector<SDValue> ResultOps;
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]3147 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3148 ResultOps, *DAG);
3149 if (!ResultOps.empty()) {
3150 BestType = CType;
3151 BestIdx = i;
3152 break;
3153 }
3154 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3155
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3156 // Things with matching constraints can only be registers, per gcc
3157 // documentation. This mainly affects "g" constraints.
3158 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3159 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3160
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3161 // This constraint letter is more general than the previous one, use it.
3162 int Generality = getConstraintGenerality(CType);
3163 if (Generality > BestGenerality) {
3164 BestType = CType;
3165 BestIdx = i;
3166 BestGenerality = Generality;
3167 }
3168 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3169
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3170 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3171 OpInfo.ConstraintType = BestType;
3172}
3173
3174/// ComputeConstraintToUse - Determines the constraint code and constraint
3175/// type to use for the specific AsmOperandInfo, setting
3176/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3177void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3178 SDValue Op,
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3179 SelectionDAG *DAG) const {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3180 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3181
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3182 // Single-letter constraints ('r') are very common.
3183 if (OpInfo.Codes.size() == 1) {
3184 OpInfo.ConstraintCode = OpInfo.Codes[0];
3185 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3186 } else {
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]3187 ChooseConstraint(OpInfo, *this, Op, DAG);
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3188 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3189
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3190 // 'X' matches anything.
3191 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3192 // Labels and constants are handled elsewhere ('X' is the only thing
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3193 // that matches labels). For Functions, the type here is the type of
Dale Johannesen5339c552009-07-20 23:27:39 +0000[diff] [blame]3194 // the result, which is not what we want to look at; leave them alone.
3195 Value *v = OpInfo.CallOperandVal;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3196 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3197 OpInfo.CallOperandVal = v;
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3198 return;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3199 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3200
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3201 // Otherwise, try to resolve it to something we know about by looking at
3202 // the actual operand type.
3203 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3204 OpInfo.ConstraintCode = Repl;
3205 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3206 }
3207 }
3208}
3209
3210//===----------------------------------------------------------------------===//
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]3211// Loop Strength Reduction hooks
3212//===----------------------------------------------------------------------===//
3213
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3214/// isLegalAddressingMode - Return true if the addressing mode represented
3215/// by AM is legal for this target, for a load/store of the specified type.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3216bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]3217 Type *Ty) const {
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3218 // The default implementation of this implements a conservative RISCy, r+r and
3219 // r+i addr mode.
3220
3221 // Allows a sign-extended 16-bit immediate field.
3222 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3223 return false;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3224
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3225 // No global is ever allowed as a base.
3226 if (AM.BaseGV)
3227 return false;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3228
3229 // Only support r+r,
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3230 switch (AM.Scale) {
3231 case 0: // "r+i" or just "i", depending on HasBaseReg.
3232 break;
3233 case 1:
3234 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3235 return false;
3236 // Otherwise we have r+r or r+i.
3237 break;
3238 case 2:
3239 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3240 return false;
3241 // Allow 2*r as r+r.
3242 break;
3243 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3244
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3245 return true;
3246}
3247
Benjamin Kramer9c640302011-07-08 10:31:30 +0000[diff] [blame]3248/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
3249/// with the multiplicative inverse of the constant.
3250SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
3251 SelectionDAG &DAG) const {
3252 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
3253 APInt d = C->getAPIntValue();
3254 assert(d != 0 && "Division by zero!");
3255
3256 // Shift the value upfront if it is even, so the LSB is one.
3257 unsigned ShAmt = d.countTrailingZeros();
3258 if (ShAmt) {
3259 // TODO: For UDIV use SRL instead of SRA.
3260 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
3261 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3262 d = d.ashr(ShAmt);
3263 }
3264
3265 // Calculate the multiplicative inverse, using Newton's method.
3266 APInt t, xn = d;
3267 while ((t = d*xn) != 1)
3268 xn *= APInt(d.getBitWidth(), 2) - t;
3269
3270 Op2 = DAG.getConstant(xn, Op1.getValueType());
3271 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3272}
3273
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3274/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3275/// return a DAG expression to select that will generate the same value by
3276/// multiplying by a magic number. See:
3277/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3278SDValue TargetLowering::
3279BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3280 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]3281 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3282 DebugLoc dl= N->getDebugLoc();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3283
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3284 // Check to see if we can do this.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3285 // FIXME: We should be more aggressive here.
3286 if (!isTypeLegal(VT))
3287 return SDValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3288
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3289 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
Jay Foad4e5ea552009-04-30 10:15:35 +0000[diff] [blame]3290 APInt::ms magics = d.magic();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3291
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3292 // Multiply the numerator (operand 0) by the magic value
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3293 // FIXME: We should support doing a MUL in a wider type
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3294 SDValue Q;
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3295 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3296 isOperationLegalOrCustom(ISD::MULHS, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3297 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3298 DAG.getConstant(magics.m, VT));
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3299 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3300 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3301 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3302 N->getOperand(0),
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3303 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3304 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3305 return SDValue(); // No mulhs or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3306 // If d > 0 and m < 0, add the numerator
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3307 if (d.isStrictlyPositive() && magics.m.isNegative()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3308 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3309 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3310 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3311 }
3312 // If d < 0 and m > 0, subtract the numerator.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3313 if (d.isNegative() && magics.m.isStrictlyPositive()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3314 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3315 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3316 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3317 }
3318 // Shift right algebraic if shift value is nonzero
3319 if (magics.s > 0) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3320 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3321 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3322 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3323 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3324 }
3325 // Extract the sign bit and add it to the quotient
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3326 SDValue T =
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3327 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3328 getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3329 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3330 Created->push_back(T.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3331 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3332}
3333
3334/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3335/// return a DAG expression to select that will generate the same value by
3336/// multiplying by a magic number. See:
3337/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3338SDValue TargetLowering::
3339BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3340 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]3341 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3342 DebugLoc dl = N->getDebugLoc();
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3343
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3344 // Check to see if we can do this.
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3345 // FIXME: We should be more aggressive here.
3346 if (!isTypeLegal(VT))
3347 return SDValue();
3348
3349 // FIXME: We should use a narrower constant when the upper
3350 // bits are known to be zero.
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3351 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3352 APInt::mu magics = N1C.magicu();
3353
3354 SDValue Q = N->getOperand(0);
3355
3356 // If the divisor is even, we can avoid using the expensive fixup by shifting
3357 // the divided value upfront.
3358 if (magics.a != 0 && !N1C[0]) {
3359 unsigned Shift = N1C.countTrailingZeros();
3360 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3361 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3362 if (Created)
3363 Created->push_back(Q.getNode());
3364
3365 // Get magic number for the shifted divisor.
3366 magics = N1C.lshr(Shift).magicu(Shift);
3367 assert(magics.a == 0 && "Should use cheap fixup now");
3368 }
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3369
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3370 // Multiply the numerator (operand 0) by the magic value
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3371 // FIXME: We should support doing a MUL in a wider type
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3372 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3373 isOperationLegalOrCustom(ISD::MULHU, VT))
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3374 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3375 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3376 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3377 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3378 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3379 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3380 return SDValue(); // No mulhu or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3381 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3382 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3383
3384 if (magics.a == 0) {
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3385 assert(magics.s < N1C.getBitWidth() &&
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3386 "We shouldn't generate an undefined shift!");
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3387 return DAG.getNode(ISD::SRL, dl, VT, Q,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3388 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3389 } else {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3390 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3391 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3392 Created->push_back(NPQ.getNode());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3393 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3394 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3395 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3396 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3397 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3398 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3399 Created->push_back(NPQ.getNode());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3400 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3401 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3402 }
3403}