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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 78e4fcecef1f0b2808a8a1c2b7ecab8d387efa88 / . / test / CodeGen / Thumb2 / thumb2-add.ll
blob: 66fca132f04ac377431226ae14820b9cacfe8579 [file] [log] [blame]
Chandler Carruth78e4fce2011-07-02 21:34:52 +0000[diff] [blame^]1; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
Anton Korobeynikov52237112009-06-17 18:13:58 +0000[diff] [blame]2
3define i32 @t2ADDrc_255(i32 %lhs) {
Chandler Carruth78e4fce2011-07-02 21:34:52 +0000[diff] [blame^]4; CHECK: t2ADDrc_255:
5; CHECK-NOT: bx lr
6; CHECK: add{{.*}} #255
7; CHECK: bx lr
8
Dan Gohmanaceba312010-01-05 17:55:26 +0000[diff] [blame]9 %Rd = add i32 %lhs, 255
Anton Korobeynikov52237112009-06-17 18:13:58 +0000[diff] [blame]10 ret i32 %Rd
11}
12
13define i32 @t2ADDrc_256(i32 %lhs) {
Chandler Carruth78e4fce2011-07-02 21:34:52 +0000[diff] [blame^]14; CHECK: t2ADDrc_256:
15; CHECK-NOT: bx lr
16; CHECK: add{{.*}} #256
17; CHECK: bx lr
18
Dan Gohmanaceba312010-01-05 17:55:26 +0000[diff] [blame]19 %Rd = add i32 %lhs, 256
Anton Korobeynikov52237112009-06-17 18:13:58 +0000[diff] [blame]20 ret i32 %Rd
21}
22
23define i32 @t2ADDrc_257(i32 %lhs) {
Chandler Carruth78e4fce2011-07-02 21:34:52 +0000[diff] [blame^]24; CHECK: t2ADDrc_257:
25; CHECK-NOT: bx lr
26; CHECK: add{{.*}} #257
27; CHECK: bx lr
28
Dan Gohmanaceba312010-01-05 17:55:26 +0000[diff] [blame]29 %Rd = add i32 %lhs, 257
Anton Korobeynikov52237112009-06-17 18:13:58 +0000[diff] [blame]30 ret i32 %Rd
31}
32
33define i32 @t2ADDrc_4094(i32 %lhs) {
Chandler Carruth78e4fce2011-07-02 21:34:52 +0000[diff] [blame^]34; CHECK: t2ADDrc_4094:
35; CHECK-NOT: bx lr
36; CHECK: add{{.*}} #4094
37; CHECK: bx lr
38
Dan Gohmanaceba312010-01-05 17:55:26 +0000[diff] [blame]39 %Rd = add i32 %lhs, 4094
Anton Korobeynikov52237112009-06-17 18:13:58 +0000[diff] [blame]40 ret i32 %Rd
41}
42
43define i32 @t2ADDrc_4095(i32 %lhs) {
Chandler Carruth78e4fce2011-07-02 21:34:52 +0000[diff] [blame^]44; CHECK: t2ADDrc_4095:
45; CHECK-NOT: bx lr
46; CHECK: add{{.*}} #4095
47; CHECK: bx lr
48
Dan Gohmanaceba312010-01-05 17:55:26 +0000[diff] [blame]49 %Rd = add i32 %lhs, 4095
Anton Korobeynikov52237112009-06-17 18:13:58 +0000[diff] [blame]50 ret i32 %Rd
51}
52
53define i32 @t2ADDrc_4096(i32 %lhs) {
Chandler Carruth78e4fce2011-07-02 21:34:52 +0000[diff] [blame^]54; CHECK: t2ADDrc_4096:
55; CHECK-NOT: bx lr
56; CHECK: add{{.*}} #4096
57; CHECK: bx lr
58
Dan Gohmanaceba312010-01-05 17:55:26 +0000[diff] [blame]59 %Rd = add i32 %lhs, 4096
Anton Korobeynikov52237112009-06-17 18:13:58 +0000[diff] [blame]60 ret i32 %Rd
61}
62
63define i32 @t2ADDrr(i32 %lhs, i32 %rhs) {
Chandler Carruth78e4fce2011-07-02 21:34:52 +0000[diff] [blame^]64; CHECK: t2ADDrr:
65; CHECK-NOT: bx lr
66; CHECK: add
67; CHECK: bx lr
68
Dan Gohmanaceba312010-01-05 17:55:26 +0000[diff] [blame]69 %Rd = add i32 %lhs, %rhs
Anton Korobeynikov52237112009-06-17 18:13:58 +0000[diff] [blame]70 ret i32 %Rd
71}
72
73define i32 @t2ADDrs(i32 %lhs, i32 %rhs) {
Chandler Carruth78e4fce2011-07-02 21:34:52 +0000[diff] [blame^]74; CHECK: t2ADDrs:
75; CHECK-NOT: bx lr
76; CHECK: add{{.*}} lsl #8
77; CHECK: bx lr
78
Anton Korobeynikov52237112009-06-17 18:13:58 +0000[diff] [blame]79 %tmp = shl i32 %rhs, 8
Dan Gohmanaceba312010-01-05 17:55:26 +0000[diff] [blame]80 %Rd = add i32 %lhs, %tmp
Anton Korobeynikov52237112009-06-17 18:13:58 +0000[diff] [blame]81 ret i32 %Rd
82}
83