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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000030#include "llvm/ADT/Statistic.h"
31#include "llvm/ADT/STLExtras.h"
Chris Lattner27f29162004-10-26 15:35:58 +000032#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000033using namespace llvm;
34
35namespace {
Chris Lattnerac0b6ae2006-12-06 17:46:33 +000036 static Statistic NumSpills("spiller", "Number of register spills");
37 static Statistic NumStores("spiller", "Number of stores added");
38 static Statistic NumLoads ("spiller", "Number of loads added");
39 static Statistic NumReused("spiller", "Number of values reused");
40 static Statistic NumDSE ("spiller", "Number of dead stores elided");
41 static Statistic NumDCE ("spiller", "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000042
Chris Lattner8c4d88d2004-09-30 01:54:45 +000043 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000044
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000045 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000046 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000047 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000048 cl::Prefix,
49 cl::values(clEnumVal(simple, " simple spiller"),
50 clEnumVal(local, " local spiller"),
51 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000052 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000053}
54
Chris Lattner8c4d88d2004-09-30 01:54:45 +000055//===----------------------------------------------------------------------===//
56// VirtRegMap implementation
57//===----------------------------------------------------------------------===//
58
Chris Lattner29268692006-09-05 02:12:02 +000059VirtRegMap::VirtRegMap(MachineFunction &mf)
60 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
61 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT) {
62 grow();
63}
64
Chris Lattner8c4d88d2004-09-30 01:54:45 +000065void VirtRegMap::grow() {
Chris Lattner7f690e62004-09-30 02:15:18 +000066 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
67 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000068}
69
Chris Lattner8c4d88d2004-09-30 01:54:45 +000070int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
71 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000072 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000073 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000074 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
75 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
76 RC->getAlignment());
77 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000078 ++NumSpills;
79 return frameIndex;
80}
81
82void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
83 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000084 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000085 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000086 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000087}
88
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000089void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +000090 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000091 // Move previous memory references folded to new instruction.
92 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +000093 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000094 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
95 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +000096 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +000097 }
Chris Lattnerdbea9732004-09-30 16:35:08 +000098
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000099 ModRef MRInfo;
Evan Cheng5c2a4602006-12-08 08:02:34 +0000100 const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor();
101 if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 ||
Evan Chengcc22a7a2006-12-08 18:45:48 +0000102 TID->findTiedToSrcOperand(OpNo) != -1) {
Chris Lattner29268692006-09-05 02:12:02 +0000103 // Folded a two-address operand.
104 MRInfo = isModRef;
105 } else if (OldMI->getOperand(OpNo).isDef()) {
106 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000107 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000108 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000109 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000110
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000111 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000112 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000113}
114
Chris Lattner7f690e62004-09-30 02:15:18 +0000115void VirtRegMap::print(std::ostream &OS) const {
Bill Wendlinge8156192006-12-07 01:30:32 +0000116 OStream LOS(OS);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000117 print(LOS);
118}
119
Bill Wendlinge8156192006-12-07 01:30:32 +0000120void VirtRegMap::print(OStream &OS) const {
Chris Lattner7f690e62004-09-30 02:15:18 +0000121 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000122
Chris Lattner7f690e62004-09-30 02:15:18 +0000123 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000124 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000125 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
126 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
127 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000128
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000129 }
130
131 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000132 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
133 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
134 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
135 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000136}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000137
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000138void VirtRegMap::dump() const {
Bill Wendlinge8156192006-12-07 01:30:32 +0000139 OStream OS = DOUT;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000140 print(OS);
141}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000142
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000143
144//===----------------------------------------------------------------------===//
145// Simple Spiller Implementation
146//===----------------------------------------------------------------------===//
147
148Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000149
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000150namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000151 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000152 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000153 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000154}
155
Chris Lattner35f27052006-05-01 21:16:03 +0000156bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000157 DOUT << "********** REWRITE MACHINE CODE **********\n";
158 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000159 const TargetMachine &TM = MF.getTarget();
160 const MRegisterInfo &MRI = *TM.getRegisterInfo();
161 bool *PhysRegsUsed = MF.getUsedPhysregs();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000162
Chris Lattner4ea1b822004-09-30 02:33:48 +0000163 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
164 // each vreg once (in the case where a spilled vreg is used by multiple
165 // operands). This is always smaller than the number of operands to the
166 // current machine instr, so it should be small.
167 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000168
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000169 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
170 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000171 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000172 MachineBasicBlock &MBB = *MBBI;
173 for (MachineBasicBlock::iterator MII = MBB.begin(),
174 E = MBB.end(); MII != E; ++MII) {
175 MachineInstr &MI = *MII;
176 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000177 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000178 if (MO.isRegister() && MO.getReg())
179 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
180 unsigned VirtReg = MO.getReg();
181 unsigned PhysReg = VRM.getPhys(VirtReg);
182 if (VRM.hasStackSlot(VirtReg)) {
183 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000184 const TargetRegisterClass* RC =
185 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000186
Chris Lattner886dd912005-04-04 21:35:34 +0000187 if (MO.isUse() &&
188 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
189 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000190 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000191 LoadedRegs.push_back(VirtReg);
192 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000193 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000194 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000195
Chris Lattner886dd912005-04-04 21:35:34 +0000196 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000197 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000198 ++NumStores;
199 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000200 }
Chris Lattner886dd912005-04-04 21:35:34 +0000201 PhysRegsUsed[PhysReg] = true;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000202 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000203 } else {
204 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000205 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000206 }
Chris Lattner886dd912005-04-04 21:35:34 +0000207
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000208 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000209 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000210 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000211 }
212 return true;
213}
214
215//===----------------------------------------------------------------------===//
216// Local Spiller Implementation
217//===----------------------------------------------------------------------===//
218
219namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000220 /// LocalSpiller - This spiller does a simple pass over the machine basic
221 /// block to attempt to keep spills in registers as much as possible for
222 /// blocks that have low register pressure (the vreg may be spilled due to
223 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000224 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000225 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000226 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000227 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000228 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000229 MRI = MF.getTarget().getRegisterInfo();
230 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000231 DOUT << "\n**** Local spiller rewriting function '"
232 << MF.getFunction()->getName() << "':\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000233
Chris Lattner7fb64342004-10-01 19:04:51 +0000234 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
235 MBB != E; ++MBB)
236 RewriteMBB(*MBB, VRM);
237 return true;
238 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000239 private:
Chris Lattner35f27052006-05-01 21:16:03 +0000240 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
Chris Lattner7fb64342004-10-01 19:04:51 +0000241 void ClobberPhysReg(unsigned PR, std::map<int, unsigned> &SpillSlots,
Chris Lattner07cf1412006-02-03 00:36:31 +0000242 std::multimap<unsigned, int> &PhysRegs);
Chris Lattner7fb64342004-10-01 19:04:51 +0000243 void ClobberPhysRegOnly(unsigned PR, std::map<int, unsigned> &SpillSlots,
Chris Lattner07cf1412006-02-03 00:36:31 +0000244 std::multimap<unsigned, int> &PhysRegs);
245 void ModifyStackSlot(int Slot, std::map<int, unsigned> &SpillSlots,
246 std::multimap<unsigned, int> &PhysRegs);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000247 };
248}
249
Chris Lattner66cf80f2006-02-03 23:13:58 +0000250/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
251/// top down, keep track of which spills slots are available in each register.
Chris Lattner593c9582006-02-03 23:28:46 +0000252///
253/// Note that not all physregs are created equal here. In particular, some
254/// physregs are reloads that we are allowed to clobber or ignore at any time.
255/// Other physregs are values that the register allocated program is using that
256/// we cannot CHANGE, but we can read if we like. We keep track of this on a
257/// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable
258/// entries. The predicate 'canClobberPhysReg()' checks this bit and
259/// addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000260namespace {
261class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000262 const MRegisterInfo *MRI;
263 const TargetInstrInfo *TII;
264
265 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
266 // register values that are still available, due to being loaded or stored to,
267 // but not invalidated yet.
268 std::map<int, unsigned> SpillSlotsAvailable;
269
270 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
271 // which stack slot values are currently held by a physreg. This is used to
272 // invalidate entries in SpillSlotsAvailable when a physreg is modified.
273 std::multimap<unsigned, int> PhysRegsAvailable;
274
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000275 void disallowClobberPhysRegOnly(unsigned PhysReg);
276
Chris Lattner66cf80f2006-02-03 23:13:58 +0000277 void ClobberPhysRegOnly(unsigned PhysReg);
278public:
279 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
280 : MRI(mri), TII(tii) {
281 }
282
283 /// getSpillSlotPhysReg - If the specified stack slot is available in a
284 /// physical register, return that PhysReg, otherwise return 0.
285 unsigned getSpillSlotPhysReg(int Slot) const {
286 std::map<int, unsigned>::const_iterator I = SpillSlotsAvailable.find(Slot);
287 if (I != SpillSlotsAvailable.end())
Chris Lattner593c9582006-02-03 23:28:46 +0000288 return I->second >> 1; // Remove the CanClobber bit.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000289 return 0;
290 }
Chris Lattner540fec62006-02-25 01:51:33 +0000291
292 const MRegisterInfo *getRegInfo() const { return MRI; }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000293
294 /// addAvailable - Mark that the specified stack slot is available in the
Chris Lattner593c9582006-02-03 23:28:46 +0000295 /// specified physreg. If CanClobber is true, the physreg can be modified at
296 /// any time without changing the semantics of the program.
297 void addAvailable(int Slot, unsigned Reg, bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000298 // If this stack slot is thought to be available in some other physreg,
299 // remove its record.
300 ModifyStackSlot(Slot);
301
Chris Lattner66cf80f2006-02-03 23:13:58 +0000302 PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
Jeff Cohen003cecb2006-02-04 03:27:39 +0000303 SpillSlotsAvailable[Slot] = (Reg << 1) | (unsigned)CanClobber;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000304
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000305 DOUT << "Remembering SS#" << Slot << " in physreg "
306 << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000307 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000308
Chris Lattner593c9582006-02-03 23:28:46 +0000309 /// canClobberPhysReg - Return true if the spiller is allowed to change the
310 /// value of the specified stackslot register if it desires. The specified
311 /// stack slot must be available in a physreg for this query to make sense.
312 bool canClobberPhysReg(int Slot) const {
313 assert(SpillSlotsAvailable.count(Slot) && "Slot not available!");
314 return SpillSlotsAvailable.find(Slot)->second & 1;
315 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000316
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000317 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
318 /// stackslot register. The register is still available but is no longer
319 /// allowed to be modifed.
320 void disallowClobberPhysReg(unsigned PhysReg);
321
Chris Lattner66cf80f2006-02-03 23:13:58 +0000322 /// ClobberPhysReg - This is called when the specified physreg changes
323 /// value. We use this to invalidate any info about stuff we thing lives in
324 /// it and any of its aliases.
325 void ClobberPhysReg(unsigned PhysReg);
326
327 /// ModifyStackSlot - This method is called when the value in a stack slot
328 /// changes. This removes information about which register the previous value
329 /// for this slot lives in (as the previous value is dead now).
330 void ModifyStackSlot(int Slot);
331};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000332}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000333
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000334/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
335/// stackslot register. The register is still available but is no longer
336/// allowed to be modifed.
337void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
338 std::multimap<unsigned, int>::iterator I =
339 PhysRegsAvailable.lower_bound(PhysReg);
340 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
341 int Slot = I->second;
342 I++;
343 assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg &&
344 "Bidirectional map mismatch!");
345 SpillSlotsAvailable[Slot] &= ~1;
346 DOUT << "PhysReg " << MRI->getName(PhysReg)
347 << " copied, it is available for use but can no longer be modified\n";
348 }
349}
350
351/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
352/// stackslot register and its aliases. The register and its aliases may
353/// still available but is no longer allowed to be modifed.
354void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
355 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
356 disallowClobberPhysRegOnly(*AS);
357 disallowClobberPhysRegOnly(PhysReg);
358}
359
Chris Lattner66cf80f2006-02-03 23:13:58 +0000360/// ClobberPhysRegOnly - This is called when the specified physreg changes
361/// value. We use this to invalidate any info about stuff we thing lives in it.
362void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
363 std::multimap<unsigned, int>::iterator I =
364 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000365 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000366 int Slot = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000367 PhysRegsAvailable.erase(I++);
Chris Lattner593c9582006-02-03 23:28:46 +0000368 assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000369 "Bidirectional map mismatch!");
370 SpillSlotsAvailable.erase(Slot);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000371 DOUT << "PhysReg " << MRI->getName(PhysReg)
372 << " clobbered, invalidating SS#" << Slot << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000373 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000374}
375
Chris Lattner66cf80f2006-02-03 23:13:58 +0000376/// ClobberPhysReg - This is called when the specified physreg changes
377/// value. We use this to invalidate any info about stuff we thing lives in
378/// it and any of its aliases.
379void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000380 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000381 ClobberPhysRegOnly(*AS);
382 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000383}
384
Chris Lattner07cf1412006-02-03 00:36:31 +0000385/// ModifyStackSlot - This method is called when the value in a stack slot
386/// changes. This removes information about which register the previous value
387/// for this slot lives in (as the previous value is dead now).
Chris Lattner66cf80f2006-02-03 23:13:58 +0000388void AvailableSpills::ModifyStackSlot(int Slot) {
389 std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(Slot);
390 if (It == SpillSlotsAvailable.end()) return;
Chris Lattner593c9582006-02-03 23:28:46 +0000391 unsigned Reg = It->second >> 1;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000392 SpillSlotsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000393
394 // This register may hold the value of multiple stack slots, only remove this
395 // stack slot from the set of values the register contains.
396 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
397 for (; ; ++I) {
398 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
399 "Map inverse broken!");
400 if (I->second == Slot) break;
401 }
402 PhysRegsAvailable.erase(I);
403}
404
405
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000406
Chris Lattner7fb64342004-10-01 19:04:51 +0000407// ReusedOp - For each reused operand, we keep track of a bit of information, in
408// case we need to rollback upon processing a new operand. See comments below.
409namespace {
410 struct ReusedOp {
411 // The MachineInstr operand that reused an available value.
412 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000413
Chris Lattner7fb64342004-10-01 19:04:51 +0000414 // StackSlot - The spill slot of the value being reused.
415 unsigned StackSlot;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000416
Chris Lattner7fb64342004-10-01 19:04:51 +0000417 // PhysRegReused - The physical register the value was available in.
418 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000419
Chris Lattner7fb64342004-10-01 19:04:51 +0000420 // AssignedPhysReg - The physreg that was assigned for use by the reload.
421 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000422
423 // VirtReg - The virtual register itself.
424 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000425
Chris Lattner8a61a752005-10-06 17:19:06 +0000426 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
427 unsigned vreg)
428 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
429 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000430 };
Chris Lattner540fec62006-02-25 01:51:33 +0000431
432 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
433 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000434 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000435 MachineInstr &MI;
436 std::vector<ReusedOp> Reuses;
Evan Chenge077ef62006-11-04 00:21:55 +0000437 bool *PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000438 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000439 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
440 PhysRegsClobbered = new bool[mri->getNumRegs()];
441 std::fill(PhysRegsClobbered, PhysRegsClobbered+mri->getNumRegs(), false);
442 }
443 ~ReuseInfo() {
444 delete[] PhysRegsClobbered;
445 }
Chris Lattner540fec62006-02-25 01:51:33 +0000446
447 bool hasReuses() const {
448 return !Reuses.empty();
449 }
450
451 /// addReuse - If we choose to reuse a virtual register that is already
452 /// available instead of reloading it, remember that we did so.
453 void addReuse(unsigned OpNo, unsigned StackSlot,
454 unsigned PhysRegReused, unsigned AssignedPhysReg,
455 unsigned VirtReg) {
456 // If the reload is to the assigned register anyway, no undo will be
457 // required.
458 if (PhysRegReused == AssignedPhysReg) return;
459
460 // Otherwise, remember this.
461 Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused,
462 AssignedPhysReg, VirtReg));
463 }
Evan Chenge077ef62006-11-04 00:21:55 +0000464
465 void markClobbered(unsigned PhysReg) {
466 PhysRegsClobbered[PhysReg] = true;
467 }
468
469 bool isClobbered(unsigned PhysReg) const {
470 return PhysRegsClobbered[PhysReg];
471 }
Chris Lattner540fec62006-02-25 01:51:33 +0000472
473 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
474 /// is some other operand that is using the specified register, either pick
475 /// a new register to use, or evict the previous reload and use this reg.
476 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
477 AvailableSpills &Spills,
478 std::map<int, MachineInstr*> &MaybeDeadStores) {
479 if (Reuses.empty()) return PhysReg; // This is most often empty.
480
481 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
482 ReusedOp &Op = Reuses[ro];
483 // If we find some other reuse that was supposed to use this register
484 // exactly for its reload, we can change this reload to use ITS reload
485 // register.
486 if (Op.PhysRegReused == PhysReg) {
487 // Yup, use the reload register that we didn't use before.
Evan Chenge077ef62006-11-04 00:21:55 +0000488 unsigned NewReg = Op.AssignedPhysReg;
Chris Lattner47cb7172006-02-25 02:03:40 +0000489 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores);
Chris Lattner540fec62006-02-25 01:51:33 +0000490 } else {
491 // Otherwise, we might also have a problem if a previously reused
492 // value aliases the new register. If so, codegen the previous reload
493 // and use this one.
494 unsigned PRRU = Op.PhysRegReused;
495 const MRegisterInfo *MRI = Spills.getRegInfo();
496 if (MRI->areAliases(PRRU, PhysReg)) {
497 // Okay, we found out that an alias of a reused register
498 // was used. This isn't good because it means we have
499 // to undo a previous reuse.
500 MachineBasicBlock *MBB = MI->getParent();
501 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000502 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
503
504 // Copy Op out of the vector and remove it, we're going to insert an
505 // explicit load for it.
506 ReusedOp NewOp = Op;
507 Reuses.erase(Reuses.begin()+ro);
508
509 // Ok, we're going to try to reload the assigned physreg into the
510 // slot that we were supposed to in the first place. However, that
511 // register could hold a reuse. Check to see if it conflicts or
512 // would prefer us to use a different register.
513 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
514 MI, Spills, MaybeDeadStores);
515
516 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
517 NewOp.StackSlot, AliasRC);
518 Spills.ClobberPhysReg(NewPhysReg);
519 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000520
521 // Any stores to this stack slot are not dead anymore.
Chris Lattner28bad082006-02-25 02:17:31 +0000522 MaybeDeadStores.erase(NewOp.StackSlot);
Chris Lattner540fec62006-02-25 01:51:33 +0000523
Chris Lattnere53f4a02006-05-04 17:52:23 +0000524 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000525
Chris Lattner28bad082006-02-25 02:17:31 +0000526 Spills.addAvailable(NewOp.StackSlot, NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000527 ++NumLoads;
528 DEBUG(MachineBasicBlock::iterator MII = MI;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000529 DOUT << '\t' << *prior(MII));
Chris Lattner540fec62006-02-25 01:51:33 +0000530
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000531 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000532 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000533
534 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000535 return PhysReg;
536 }
537 }
538 }
539 return PhysReg;
540 }
541 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000542}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000543
Chris Lattner7fb64342004-10-01 19:04:51 +0000544
545/// rewriteMBB - Keep track of which spills are available even after the
546/// register allocator is done with them. If possible, avoid reloading vregs.
Chris Lattner35f27052006-05-01 21:16:03 +0000547void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000548
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000549 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000550
Chris Lattner66cf80f2006-02-03 23:13:58 +0000551 // Spills - Keep track of which spilled values are available in physregs so
552 // that we can choose to reuse the physregs instead of emitting reloads.
553 AvailableSpills Spills(MRI, TII);
554
Chris Lattner52b25db2004-10-01 19:47:12 +0000555 // MaybeDeadStores - When we need to write a value back into a stack slot,
556 // keep track of the inserted store. If the stack slot value is never read
557 // (because the value was used from some available register, for example), and
558 // subsequently stored to, the original store is dead. This map keeps track
559 // of inserted stores that are not used. If we see a subsequent store to the
560 // same stack slot, the original store is deleted.
561 std::map<int, MachineInstr*> MaybeDeadStores;
562
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000563 bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
564
Chris Lattner7fb64342004-10-01 19:04:51 +0000565 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
566 MII != E; ) {
567 MachineInstr &MI = *MII;
568 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
569
Chris Lattner540fec62006-02-25 01:51:33 +0000570 /// ReusedOperands - Keep track of operand reuse in case we need to undo
571 /// reuse.
Evan Chenge077ef62006-11-04 00:21:55 +0000572 ReuseInfo ReusedOperands(MI, MRI);
573
574 // Loop over all of the implicit defs, clearing them from our available
575 // sets.
576 const unsigned *ImpDef = TII->getImplicitDefs(MI.getOpcode());
577 if (ImpDef) {
578 for ( ; *ImpDef; ++ImpDef) {
579 PhysRegsUsed[*ImpDef] = true;
580 ReusedOperands.markClobbered(*ImpDef);
581 Spills.ClobberPhysReg(*ImpDef);
582 }
583 }
584
Chris Lattner7fb64342004-10-01 19:04:51 +0000585 // Process all of the spilled uses and all non spilled reg references.
586 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
587 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000588 if (!MO.isRegister() || MO.getReg() == 0)
589 continue; // Ignore non-register operands.
590
591 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
592 // Ignore physregs for spilling, but remember that it is used by this
593 // function.
Chris Lattner886dd912005-04-04 21:35:34 +0000594 PhysRegsUsed[MO.getReg()] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000595 ReusedOperands.markClobbered(MO.getReg());
Chris Lattner50ea01e2005-09-09 20:29:51 +0000596 continue;
597 }
598
599 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
600 "Not a virtual or a physical register?");
601
602 unsigned VirtReg = MO.getReg();
603 if (!VRM.hasStackSlot(VirtReg)) {
604 // This virtual register was assigned a physreg!
605 unsigned Phys = VRM.getPhys(VirtReg);
606 PhysRegsUsed[Phys] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000607 if (MO.isDef())
608 ReusedOperands.markClobbered(Phys);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000609 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000610 continue;
611 }
612
613 // This virtual register is now known to be a spilled value.
614 if (!MO.isUse())
615 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000616
Chris Lattner50ea01e2005-09-09 20:29:51 +0000617 int StackSlot = VRM.getStackSlot(VirtReg);
618 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000619
Chris Lattner50ea01e2005-09-09 20:29:51 +0000620 // Check to see if this stack slot is available.
Chris Lattneraddc55a2006-04-28 01:46:50 +0000621 if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot))) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000622
Chris Lattner29268692006-09-05 02:12:02 +0000623 // This spilled operand might be part of a two-address operand. If this
624 // is the case, then changing it will necessarily require changing the
625 // def part of the instruction as well. However, in some cases, we
626 // aren't allowed to modify the reused register. If none of these cases
627 // apply, reuse it.
628 bool CanReuse = true;
Evan Cheng51cdcd12006-12-07 01:21:59 +0000629 int ti = MI.getInstrDescriptor()->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000630 if (ti != -1 &&
631 MI.getOperand(ti).isReg() &&
632 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000633 // Okay, we have a two address operand. We can reuse this physreg as
Evan Chenge077ef62006-11-04 00:21:55 +0000634 // long as we are allowed to clobber the value and there is an earlier
635 // def that has already clobbered the physreg.
636 CanReuse = Spills.canClobberPhysReg(StackSlot) &&
637 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +0000638 }
639
640 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000641 // If this stack slot value is already available, reuse it!
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000642 DOUT << "Reusing SS#" << StackSlot << " from physreg "
643 << MRI->getName(PhysReg) << " for vreg"
644 << VirtReg <<" instead of reloading into physreg "
645 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000646 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000647
648 // The only technical detail we have is that we don't know that
649 // PhysReg won't be clobbered by a reloaded stack slot that occurs
650 // later in the instruction. In particular, consider 'op V1, V2'.
651 // If V1 is available in physreg R0, we would choose to reuse it
652 // here, instead of reloading it into the register the allocator
653 // indicated (say R1). However, V2 might have to be reloaded
654 // later, and it might indicate that it needs to live in R0. When
655 // this occurs, we need to have information available that
656 // indicates it is safe to use R1 for the reload instead of R0.
657 //
658 // To further complicate matters, we might conflict with an alias,
659 // or R0 and R1 might not be compatible with each other. In this
660 // case, we actually insert a reload for V1 in R1, ensuring that
661 // we can get at R0 or its alias.
662 ReusedOperands.addReuse(i, StackSlot, PhysReg,
663 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000664 if (ti != -1)
665 // Only mark it clobbered if this is a use&def operand.
666 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000667 ++NumReused;
668 continue;
669 }
670
671 // Otherwise we have a situation where we have a two-address instruction
672 // whose mod/ref operand needs to be reloaded. This reload is already
673 // available in some register "PhysReg", but if we used PhysReg as the
674 // operand to our 2-addr instruction, the instruction would modify
675 // PhysReg. This isn't cool if something later uses PhysReg and expects
676 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000677 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000678 // To avoid this problem, and to avoid doing a load right after a store,
679 // we emit a copy from PhysReg into the designated register for this
680 // operand.
681 unsigned DesignatedReg = VRM.getPhys(VirtReg);
682 assert(DesignatedReg && "Must map virtreg to physreg!");
683
684 // Note that, if we reused a register for a previous operand, the
685 // register we want to reload into might not actually be
686 // available. If this occurs, use the register indicated by the
687 // reuser.
688 if (ReusedOperands.hasReuses())
689 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
690 Spills, MaybeDeadStores);
691
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000692 // If the mapped designated register is actually the physreg we have
693 // incoming, we don't need to inserted a dead copy.
694 if (DesignatedReg == PhysReg) {
695 // If this stack slot value is already available, reuse it!
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000696 DOUT << "Reusing SS#" << StackSlot << " from physreg "
697 << MRI->getName(PhysReg) << " for vreg"
698 << VirtReg
699 << " instead of reloading into same physreg.\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000700 MI.getOperand(i).setReg(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000701 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000702 ++NumReused;
703 continue;
704 }
705
Chris Lattneraddc55a2006-04-28 01:46:50 +0000706 const TargetRegisterClass* RC =
707 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
708
709 PhysRegsUsed[DesignatedReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000710 ReusedOperands.markClobbered(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000711 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
712
713 // This invalidates DesignatedReg.
714 Spills.ClobberPhysReg(DesignatedReg);
715
716 Spills.addAvailable(StackSlot, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000717 MI.getOperand(i).setReg(DesignatedReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000718 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000719 ++NumReused;
720 continue;
721 }
722
723 // Otherwise, reload it and remember that we have it.
724 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000725 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000726 const TargetRegisterClass* RC =
727 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000728
Chris Lattner50ea01e2005-09-09 20:29:51 +0000729 // Note that, if we reused a register for a previous operand, the
730 // register we want to reload into might not actually be
731 // available. If this occurs, use the register indicated by the
732 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000733 if (ReusedOperands.hasReuses())
734 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
735 Spills, MaybeDeadStores);
736
Chris Lattner50ea01e2005-09-09 20:29:51 +0000737 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000738 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000739 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000740 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000741 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000742
743 // Any stores to this stack slot are not dead anymore.
744 MaybeDeadStores.erase(StackSlot);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000745 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000746 ++NumLoads;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000747 MI.getOperand(i).setReg(PhysReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000748 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000749 }
750
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000751 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000752
Chris Lattner7fb64342004-10-01 19:04:51 +0000753 // If we have folded references to memory operands, make sure we clear all
754 // physical registers that may contain the value of the spilled virtual
755 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000756 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
757 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000758 DOUT << "Folded vreg: " << I->second.first << " MR: "
759 << I->second.second;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000760 unsigned VirtReg = I->second.first;
761 VirtRegMap::ModRef MR = I->second.second;
Chris Lattnercea86882005-09-19 06:56:21 +0000762 if (!VRM.hasStackSlot(VirtReg)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000763 DOUT << ": No stack slot!\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000764 continue;
765 }
766 int SS = VRM.getStackSlot(VirtReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000767 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000768
769 // If this folded instruction is just a use, check to see if it's a
770 // straight load from the virt reg slot.
771 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
772 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000773 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Chris Lattner6ec36262006-10-12 17:45:38 +0000774 if (FrameIdx == SS) {
775 // If this spill slot is available, turn it into a copy (or nothing)
776 // instead of leaving it as a load!
777 if (unsigned InReg = Spills.getSpillSlotPhysReg(SS)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000778 DOUT << "Promoted Load To Copy: " << MI;
Chris Lattner6ec36262006-10-12 17:45:38 +0000779 MachineFunction &MF = *MBB.getParent();
780 if (DestReg != InReg) {
781 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
782 MF.getSSARegMap()->getRegClass(VirtReg));
783 // Revisit the copy so we make sure to notice the effects of the
784 // operation on the destreg (either needing to RA it if it's
785 // virtual or needing to clobber any values if it's physical).
786 NextMII = &MI;
787 --NextMII; // backtrack to the copy.
788 }
789 VRM.RemoveFromFoldedVirtMap(&MI);
790 MBB.erase(&MI);
791 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +0000792 }
Chris Lattnercea86882005-09-19 06:56:21 +0000793 }
794 }
795 }
796
797 // If this reference is not a use, any previous store is now dead.
798 // Otherwise, the store to this stack slot is not dead anymore.
799 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
800 if (MDSI != MaybeDeadStores.end()) {
801 if (MR & VirtRegMap::isRef) // Previous store is not dead.
802 MaybeDeadStores.erase(MDSI);
803 else {
804 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +0000805 assert(VirtRegMap::isMod && "Can't be modref!");
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000806 DOUT << "Removed dead store:\t" << *MDSI->second;
Chris Lattner35f27052006-05-01 21:16:03 +0000807 MBB.erase(MDSI->second);
Chris Lattner229924a2006-05-01 22:03:24 +0000808 VRM.RemoveFromFoldedVirtMap(MDSI->second);
Chris Lattner35f27052006-05-01 21:16:03 +0000809 MaybeDeadStores.erase(MDSI);
810 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +0000811 }
812 }
813
814 // If the spill slot value is available, and this is a new definition of
815 // the value, the value is not available anymore.
816 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +0000817 // Notice that the value in this stack slot has been modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000818 Spills.ModifyStackSlot(SS);
Chris Lattnercd816392006-02-02 23:29:36 +0000819
820 // If this is *just* a mod of the value, check to see if this is just a
821 // store to the spill slot (i.e. the spill got merged into the copy). If
822 // so, realize that the vreg is available now, and add the store to the
823 // MaybeDeadStore info.
824 int StackSlot;
825 if (!(MR & VirtRegMap::isRef)) {
826 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
827 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
828 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +0000829 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +0000830 // this as a potentially dead store in case there is a subsequent
831 // store into the stack slot without a read from it.
832 MaybeDeadStores[StackSlot] = &MI;
833
Chris Lattnercd816392006-02-02 23:29:36 +0000834 // If the stack slot value was previously available in some other
835 // register, change it now. Otherwise, make the register available,
836 // in PhysReg.
Chris Lattner593c9582006-02-03 23:28:46 +0000837 Spills.addAvailable(StackSlot, SrcReg, false /*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +0000838 }
839 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000840 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000841 }
842
Chris Lattner7fb64342004-10-01 19:04:51 +0000843 // Process all of the spilled defs.
844 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
845 MachineOperand &MO = MI.getOperand(i);
846 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
847 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000848
Chris Lattner7fb64342004-10-01 19:04:51 +0000849 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +0000850 // Check to see if this is a noop copy. If so, eliminate the
851 // instruction before considering the dest reg to be changed.
852 unsigned Src, Dst;
853 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
854 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000855 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner29268692006-09-05 02:12:02 +0000856 MBB.erase(&MI);
857 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000858 Spills.disallowClobberPhysReg(VirtReg);
Chris Lattner29268692006-09-05 02:12:02 +0000859 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +0000860 }
Chris Lattner6ec36262006-10-12 17:45:38 +0000861
862 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +0000863 Spills.ClobberPhysReg(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000864 ReusedOperands.markClobbered(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +0000865
866 // Check to see if this instruction is a load from a stack slot into
867 // a register. If so, this provides the stack slot value in the reg.
868 int FrameIdx;
869 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
870 assert(DestReg == VirtReg && "Unknown load situation!");
871
872 // Otherwise, if it wasn't available, remember that it is now!
873 Spills.addAvailable(FrameIdx, DestReg);
874 goto ProcessNextInst;
875 }
876
Chris Lattner29268692006-09-05 02:12:02 +0000877 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000878 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000879
Chris Lattner84e752a2006-02-03 03:06:49 +0000880 // The only vregs left are stack slot definitions.
881 int StackSlot = VRM.getStackSlot(VirtReg);
882 const TargetRegisterClass *RC =
883 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000884
Chris Lattner29268692006-09-05 02:12:02 +0000885 // If this def is part of a two-address operand, make sure to execute
886 // the store from the correct physical register.
887 unsigned PhysReg;
Evan Chengcc22a7a2006-12-08 18:45:48 +0000888 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000889 if (TiedOp != -1)
890 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chenge077ef62006-11-04 00:21:55 +0000891 else {
Chris Lattner29268692006-09-05 02:12:02 +0000892 PhysReg = VRM.getPhys(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000893 if (ReusedOperands.isClobbered(PhysReg)) {
894 // Another def has taken the assigned physreg. It must have been a
895 // use&def which got it due to reuse. Undo the reuse!
896 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
897 Spills, MaybeDeadStores);
898 }
899 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000900
Chris Lattner84e752a2006-02-03 03:06:49 +0000901 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000902 ReusedOperands.markClobbered(PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000903 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000904 DOUT << "Store:\t" << *next(MII);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000905 MI.getOperand(i).setReg(PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000906
Chris Lattner109afed2006-02-03 03:16:14 +0000907 // Check to see if this is a noop copy. If so, eliminate the
908 // instruction before considering the dest reg to be changed.
909 {
910 unsigned Src, Dst;
911 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
912 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000913 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner109afed2006-02-03 03:16:14 +0000914 MBB.erase(&MI);
Chris Lattner229924a2006-05-01 22:03:24 +0000915 VRM.RemoveFromFoldedVirtMap(&MI);
Chris Lattner109afed2006-02-03 03:16:14 +0000916 goto ProcessNextInst;
917 }
918 }
919
Chris Lattner84e752a2006-02-03 03:06:49 +0000920 // If there is a dead store to this stack slot, nuke it now.
921 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
922 if (LastStore) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000923 DOUT << "Removed dead store:\t" << *LastStore;
Chris Lattner84e752a2006-02-03 03:06:49 +0000924 ++NumDSE;
925 MBB.erase(LastStore);
Chris Lattner229924a2006-05-01 22:03:24 +0000926 VRM.RemoveFromFoldedVirtMap(LastStore);
Chris Lattner7fb64342004-10-01 19:04:51 +0000927 }
Chris Lattner84e752a2006-02-03 03:06:49 +0000928 LastStore = next(MII);
929
930 // If the stack slot value was previously available in some other
931 // register, change it now. Otherwise, make the register available,
932 // in PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000933 Spills.ModifyStackSlot(StackSlot);
934 Spills.ClobberPhysReg(PhysReg);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000935 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000936 ++NumStores;
Chris Lattner7fb64342004-10-01 19:04:51 +0000937 }
938 }
Chris Lattnercea86882005-09-19 06:56:21 +0000939 ProcessNextInst:
Chris Lattner7fb64342004-10-01 19:04:51 +0000940 MII = NextMII;
941 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000942}
943
Chris Lattnerf7da2c72006-08-24 22:43:55 +0000944
945
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000946llvm::Spiller* llvm::createSpiller() {
947 switch (SpillerOpt) {
948 default: assert(0 && "Unreachable!");
949 case local:
950 return new LocalSpiller();
951 case simple:
952 return new SimpleSpiller();
953 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000954}