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Chris Lattnere138b3d2008-01-01 20:36:19 +00001//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
Misha Brukmanedf128a2005-04-21 22:36:52 +00002//
John Criswellb576c942003-10-20 19:43:21 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanedf128a2005-04-21 22:36:52 +00007//
John Criswellb576c942003-10-20 19:43:21 +00008//===----------------------------------------------------------------------===//
Brian Gaeke21326fc2004-02-13 04:39:32 +00009//
10// Methods common to all machine instructions.
11//
Chris Lattner035dfbe2002-08-09 20:08:06 +000012//===----------------------------------------------------------------------===//
Vikram S. Adve70bc4b52001-07-21 12:41:50 +000013
Chris Lattner822b4fb2001-09-07 17:18:30 +000014#include "llvm/CodeGen/MachineInstr.h"
Evan Chengfb112882009-03-23 08:01:15 +000015#include "llvm/Constants.h"
Dan Gohman8c2b5252009-10-30 01:27:03 +000016#include "llvm/Function.h"
Evan Chengfb112882009-03-23 08:01:15 +000017#include "llvm/InlineAsm.h"
Chris Lattner72aaa3c2010-03-13 08:14:18 +000018#include "llvm/Metadata.h"
Chris Lattner5e9cd432009-12-28 08:30:43 +000019#include "llvm/Type.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000020#include "llvm/Value.h"
Dan Gohmancd26ec52009-09-23 01:33:16 +000021#include "llvm/Assembly/Writer.h"
Evan Cheng506049f2010-03-03 01:44:33 +000022#include "llvm/CodeGen/MachineConstantPool.h"
Chris Lattner8517e1f2004-02-19 16:17:08 +000023#include "llvm/CodeGen/MachineFunction.h"
Dan Gohmanc76909a2009-09-25 20:36:54 +000024#include "llvm/CodeGen/MachineMemOperand.h"
Chris Lattner62ed6b92008-01-01 01:12:31 +000025#include "llvm/CodeGen/MachineRegisterInfo.h"
Dan Gohman69de1932008-02-06 22:27:42 +000026#include "llvm/CodeGen/PseudoSourceValue.h"
Chris Lattner72aaa3c2010-03-13 08:14:18 +000027#include "llvm/MC/MCSymbol.h"
Chris Lattner10491642002-10-30 00:48:05 +000028#include "llvm/Target/TargetMachine.h"
Evan Chengbb81d972008-01-31 09:59:15 +000029#include "llvm/Target/TargetInstrInfo.h"
Chris Lattnerf14cf852008-01-07 07:42:25 +000030#include "llvm/Target/TargetInstrDesc.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +000031#include "llvm/Target/TargetRegisterInfo.h"
Dan Gohmane33f44c2009-10-07 17:38:06 +000032#include "llvm/Analysis/AliasAnalysis.h"
Argyrios Kyrtzidisa26eae62009-04-30 23:22:31 +000033#include "llvm/Analysis/DebugInfo.h"
David Greene3b325332010-01-04 23:48:20 +000034#include "llvm/Support/Debug.h"
Torok Edwinc25e7582009-07-11 20:10:48 +000035#include "llvm/Support/ErrorHandling.h"
Dan Gohman2c3f7ae2008-07-17 23:49:46 +000036#include "llvm/Support/LeakDetector.h"
Dan Gohmance42e402008-07-07 20:32:02 +000037#include "llvm/Support/MathExtras.h"
Chris Lattneredfb72c2008-08-24 20:37:32 +000038#include "llvm/Support/raw_ostream.h"
Dan Gohmanb8d2f552008-08-20 15:58:01 +000039#include "llvm/ADT/FoldingSet.h"
Chris Lattner0742b592004-02-23 18:38:20 +000040using namespace llvm;
Brian Gaeked0fde302003-11-11 22:41:34 +000041
Chris Lattnerf7382302007-12-30 21:56:09 +000042//===----------------------------------------------------------------------===//
43// MachineOperand Implementation
44//===----------------------------------------------------------------------===//
45
Chris Lattner62ed6b92008-01-01 01:12:31 +000046/// AddRegOperandToRegInfo - Add this register operand to the specified
47/// MachineRegisterInfo. If it is null, then the next/prev fields should be
48/// explicitly nulled out.
49void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
Dan Gohmand735b802008-10-03 15:45:36 +000050 assert(isReg() && "Can only add reg operand to use lists");
Chris Lattner62ed6b92008-01-01 01:12:31 +000051
52 // If the reginfo pointer is null, just explicitly null out or next/prev
53 // pointers, to ensure they are not garbage.
54 if (RegInfo == 0) {
55 Contents.Reg.Prev = 0;
56 Contents.Reg.Next = 0;
57 return;
58 }
59
60 // Otherwise, add this operand to the head of the registers use/def list.
Chris Lattner80fe5312008-01-01 21:08:22 +000061 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
Chris Lattner62ed6b92008-01-01 01:12:31 +000062
Chris Lattner80fe5312008-01-01 21:08:22 +000063 // For SSA values, we prefer to keep the definition at the start of the list.
64 // we do this by skipping over the definition if it is at the head of the
65 // list.
66 if (*Head && (*Head)->isDef())
67 Head = &(*Head)->Contents.Reg.Next;
68
69 Contents.Reg.Next = *Head;
Chris Lattner62ed6b92008-01-01 01:12:31 +000070 if (Contents.Reg.Next) {
71 assert(getReg() == Contents.Reg.Next->getReg() &&
72 "Different regs on the same list!");
73 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
74 }
75
Chris Lattner80fe5312008-01-01 21:08:22 +000076 Contents.Reg.Prev = Head;
77 *Head = this;
Chris Lattner62ed6b92008-01-01 01:12:31 +000078}
79
Dan Gohman3bc1a372009-04-15 01:17:37 +000080/// RemoveRegOperandFromRegInfo - Remove this register operand from the
81/// MachineRegisterInfo it is linked with.
82void MachineOperand::RemoveRegOperandFromRegInfo() {
83 assert(isOnRegUseList() && "Reg operand is not on a use list");
84 // Unlink this from the doubly linked list of operands.
85 MachineOperand *NextOp = Contents.Reg.Next;
86 *Contents.Reg.Prev = NextOp;
87 if (NextOp) {
88 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
89 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
90 }
91 Contents.Reg.Prev = 0;
92 Contents.Reg.Next = 0;
93}
94
Chris Lattner62ed6b92008-01-01 01:12:31 +000095void MachineOperand::setReg(unsigned Reg) {
96 if (getReg() == Reg) return; // No change.
97
98 // Otherwise, we have to change the register. If this operand is embedded
99 // into a machine function, we need to update the old and new register's
100 // use/def lists.
101 if (MachineInstr *MI = getParent())
102 if (MachineBasicBlock *MBB = MI->getParent())
103 if (MachineFunction *MF = MBB->getParent()) {
104 RemoveRegOperandFromRegInfo();
Jakob Stoklund Olesen25947462010-10-19 20:56:32 +0000105 SmallContents.RegNo = Reg;
Chris Lattner62ed6b92008-01-01 01:12:31 +0000106 AddRegOperandToRegInfo(&MF->getRegInfo());
107 return;
108 }
109
110 // Otherwise, just change the register, no problem. :)
Jakob Stoklund Olesen25947462010-10-19 20:56:32 +0000111 SmallContents.RegNo = Reg;
Chris Lattner62ed6b92008-01-01 01:12:31 +0000112}
113
Jakob Stoklund Olesen2da53372010-05-28 18:18:53 +0000114void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
115 const TargetRegisterInfo &TRI) {
116 assert(TargetRegisterInfo::isVirtualRegister(Reg));
117 if (SubIdx && getSubReg())
118 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
119 setReg(Reg);
Jakob Stoklund Olesena5135f62010-06-01 22:39:25 +0000120 if (SubIdx)
121 setSubReg(SubIdx);
Jakob Stoklund Olesen2da53372010-05-28 18:18:53 +0000122}
123
124void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
125 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
126 if (getSubReg()) {
127 Reg = TRI.getSubReg(Reg, getSubReg());
Jakob Stoklund Olesencf724f02011-05-08 19:21:08 +0000128 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
129 // That won't happen in legal code.
Jakob Stoklund Olesen2da53372010-05-28 18:18:53 +0000130 setSubReg(0);
131 }
132 setReg(Reg);
133}
134
Chris Lattner62ed6b92008-01-01 01:12:31 +0000135/// ChangeToImmediate - Replace this operand with a new immediate operand of
136/// the specified value. If an operand is known to be an immediate already,
137/// the setImm method should be used.
138void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
139 // If this operand is currently a register operand, and if this is in a
140 // function, deregister the operand from the register's use/def list.
Dan Gohmand735b802008-10-03 15:45:36 +0000141 if (isReg() && getParent() && getParent()->getParent() &&
Chris Lattner62ed6b92008-01-01 01:12:31 +0000142 getParent()->getParent()->getParent())
143 RemoveRegOperandFromRegInfo();
144
145 OpKind = MO_Immediate;
146 Contents.ImmVal = ImmVal;
147}
148
149/// ChangeToRegister - Replace this operand with a new register operand of
150/// the specified value. If an operand is known to be an register already,
151/// the setReg method should be used.
152void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
Dale Johannesen9653f9e2010-02-10 00:41:49 +0000153 bool isKill, bool isDead, bool isUndef,
154 bool isDebug) {
Chris Lattner62ed6b92008-01-01 01:12:31 +0000155 // If this operand is already a register operand, use setReg to update the
156 // register's use/def lists.
Dan Gohmand735b802008-10-03 15:45:36 +0000157 if (isReg()) {
Dale Johannesene0091802008-09-14 01:44:36 +0000158 assert(!isEarlyClobber());
Chris Lattner62ed6b92008-01-01 01:12:31 +0000159 setReg(Reg);
160 } else {
161 // Otherwise, change this to a register and set the reg#.
162 OpKind = MO_Register;
Jakob Stoklund Olesen25947462010-10-19 20:56:32 +0000163 SmallContents.RegNo = Reg;
Chris Lattner62ed6b92008-01-01 01:12:31 +0000164
165 // If this operand is embedded in a function, add the operand to the
166 // register's use/def list.
167 if (MachineInstr *MI = getParent())
168 if (MachineBasicBlock *MBB = MI->getParent())
169 if (MachineFunction *MF = MBB->getParent())
170 AddRegOperandToRegInfo(&MF->getRegInfo());
171 }
172
173 IsDef = isDef;
174 IsImp = isImp;
175 IsKill = isKill;
176 IsDead = isDead;
Evan Cheng4784f1f2009-06-30 08:49:04 +0000177 IsUndef = isUndef;
Dale Johannesene0091802008-09-14 01:44:36 +0000178 IsEarlyClobber = false;
Dale Johannesen9653f9e2010-02-10 00:41:49 +0000179 IsDebug = isDebug;
Chris Lattner62ed6b92008-01-01 01:12:31 +0000180 SubReg = 0;
181}
182
Chris Lattnerf7382302007-12-30 21:56:09 +0000183/// isIdenticalTo - Return true if this operand is identical to the specified
184/// operand.
185bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
Chris Lattner31530612009-06-24 17:54:48 +0000186 if (getType() != Other.getType() ||
187 getTargetFlags() != Other.getTargetFlags())
188 return false;
Chris Lattnerf7382302007-12-30 21:56:09 +0000189
190 switch (getType()) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000191 default: llvm_unreachable("Unrecognized operand type");
Chris Lattnerf7382302007-12-30 21:56:09 +0000192 case MachineOperand::MO_Register:
193 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
194 getSubReg() == Other.getSubReg();
195 case MachineOperand::MO_Immediate:
196 return getImm() == Other.getImm();
Nate Begemane8b7ccf2008-02-14 07:39:30 +0000197 case MachineOperand::MO_FPImmediate:
198 return getFPImm() == Other.getFPImm();
Chris Lattnerf7382302007-12-30 21:56:09 +0000199 case MachineOperand::MO_MachineBasicBlock:
200 return getMBB() == Other.getMBB();
201 case MachineOperand::MO_FrameIndex:
Chris Lattner8aa797a2007-12-30 23:10:15 +0000202 return getIndex() == Other.getIndex();
Chris Lattnerf7382302007-12-30 21:56:09 +0000203 case MachineOperand::MO_ConstantPoolIndex:
Chris Lattner8aa797a2007-12-30 23:10:15 +0000204 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
Chris Lattnerf7382302007-12-30 21:56:09 +0000205 case MachineOperand::MO_JumpTableIndex:
Chris Lattner8aa797a2007-12-30 23:10:15 +0000206 return getIndex() == Other.getIndex();
Chris Lattnerf7382302007-12-30 21:56:09 +0000207 case MachineOperand::MO_GlobalAddress:
208 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
209 case MachineOperand::MO_ExternalSymbol:
210 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
211 getOffset() == Other.getOffset();
Dan Gohman8c2b5252009-10-30 01:27:03 +0000212 case MachineOperand::MO_BlockAddress:
213 return getBlockAddress() == Other.getBlockAddress();
Chris Lattner72aaa3c2010-03-13 08:14:18 +0000214 case MachineOperand::MO_MCSymbol:
215 return getMCSymbol() == Other.getMCSymbol();
Chris Lattner24ad3ed2010-04-07 18:03:19 +0000216 case MachineOperand::MO_Metadata:
217 return getMetadata() == Other.getMetadata();
Chris Lattnerf7382302007-12-30 21:56:09 +0000218 }
219}
220
221/// print - Print the specified machine operand.
222///
Mon P Wang5ca6bd12008-10-10 01:43:55 +0000223void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
Dan Gohman80f6c582009-11-09 19:38:45 +0000224 // If the instruction is embedded into a basic block, we can find the
225 // target info for the instruction.
226 if (!TM)
227 if (const MachineInstr *MI = getParent())
228 if (const MachineBasicBlock *MBB = MI->getParent())
229 if (const MachineFunction *MF = MBB->getParent())
230 TM = &MF->getTarget();
Jakob Stoklund Olesen43142682011-01-09 03:05:53 +0000231 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
Dan Gohman80f6c582009-11-09 19:38:45 +0000232
Chris Lattnerf7382302007-12-30 21:56:09 +0000233 switch (getType()) {
234 case MachineOperand::MO_Register:
Jakob Stoklund Olesen43142682011-01-09 03:05:53 +0000235 OS << PrintReg(getReg(), TRI, getSubReg());
Dan Gohman2ccc8392008-12-18 21:51:27 +0000236
Evan Cheng4784f1f2009-06-30 08:49:04 +0000237 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
238 isEarlyClobber()) {
Chris Lattner31530612009-06-24 17:54:48 +0000239 OS << '<';
Chris Lattnerf7382302007-12-30 21:56:09 +0000240 bool NeedComma = false;
Evan Cheng07897072009-10-14 23:37:31 +0000241 if (isDef()) {
Chris Lattner31530612009-06-24 17:54:48 +0000242 if (NeedComma) OS << ',';
Dale Johannesen913d3df2008-09-12 17:49:03 +0000243 if (isEarlyClobber())
244 OS << "earlyclobber,";
Evan Cheng07897072009-10-14 23:37:31 +0000245 if (isImplicit())
246 OS << "imp-";
Chris Lattnerf7382302007-12-30 21:56:09 +0000247 OS << "def";
248 NeedComma = true;
Evan Cheng5affca02009-10-21 07:56:02 +0000249 } else if (isImplicit()) {
Evan Cheng07897072009-10-14 23:37:31 +0000250 OS << "imp-use";
Evan Cheng5affca02009-10-21 07:56:02 +0000251 NeedComma = true;
252 }
Evan Cheng07897072009-10-14 23:37:31 +0000253
Evan Cheng4784f1f2009-06-30 08:49:04 +0000254 if (isKill() || isDead() || isUndef()) {
Chris Lattner31530612009-06-24 17:54:48 +0000255 if (NeedComma) OS << ',';
Bill Wendling181eb732008-02-24 00:56:13 +0000256 if (isKill()) OS << "kill";
257 if (isDead()) OS << "dead";
Evan Cheng4784f1f2009-06-30 08:49:04 +0000258 if (isUndef()) {
259 if (isKill() || isDead())
260 OS << ',';
261 OS << "undef";
262 }
Chris Lattnerf7382302007-12-30 21:56:09 +0000263 }
Chris Lattner31530612009-06-24 17:54:48 +0000264 OS << '>';
Chris Lattnerf7382302007-12-30 21:56:09 +0000265 }
266 break;
267 case MachineOperand::MO_Immediate:
268 OS << getImm();
269 break;
Devang Patel8594d422011-06-24 20:46:11 +0000270 case MachineOperand::MO_CImmediate:
271 getCImm()->getValue().print(OS, false);
272 break;
Nate Begemane8b7ccf2008-02-14 07:39:30 +0000273 case MachineOperand::MO_FPImmediate:
Chris Lattnercf0fe8d2009-10-05 05:54:46 +0000274 if (getFPImm()->getType()->isFloatTy())
Nate Begemane8b7ccf2008-02-14 07:39:30 +0000275 OS << getFPImm()->getValueAPF().convertToFloat();
Chris Lattner31530612009-06-24 17:54:48 +0000276 else
Nate Begemane8b7ccf2008-02-14 07:39:30 +0000277 OS << getFPImm()->getValueAPF().convertToDouble();
Nate Begemane8b7ccf2008-02-14 07:39:30 +0000278 break;
Chris Lattnerf7382302007-12-30 21:56:09 +0000279 case MachineOperand::MO_MachineBasicBlock:
Dan Gohman0ba90f32009-10-31 20:19:03 +0000280 OS << "<BB#" << getMBB()->getNumber() << ">";
Chris Lattnerf7382302007-12-30 21:56:09 +0000281 break;
282 case MachineOperand::MO_FrameIndex:
Chris Lattner31530612009-06-24 17:54:48 +0000283 OS << "<fi#" << getIndex() << '>';
Chris Lattnerf7382302007-12-30 21:56:09 +0000284 break;
285 case MachineOperand::MO_ConstantPoolIndex:
Chris Lattner8aa797a2007-12-30 23:10:15 +0000286 OS << "<cp#" << getIndex();
Chris Lattnerf7382302007-12-30 21:56:09 +0000287 if (getOffset()) OS << "+" << getOffset();
Chris Lattner31530612009-06-24 17:54:48 +0000288 OS << '>';
Chris Lattnerf7382302007-12-30 21:56:09 +0000289 break;
290 case MachineOperand::MO_JumpTableIndex:
Chris Lattner31530612009-06-24 17:54:48 +0000291 OS << "<jt#" << getIndex() << '>';
Chris Lattnerf7382302007-12-30 21:56:09 +0000292 break;
293 case MachineOperand::MO_GlobalAddress:
Dan Gohman8d4e3b52009-11-06 18:03:10 +0000294 OS << "<ga:";
295 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
Chris Lattnerf7382302007-12-30 21:56:09 +0000296 if (getOffset()) OS << "+" << getOffset();
Chris Lattner31530612009-06-24 17:54:48 +0000297 OS << '>';
Chris Lattnerf7382302007-12-30 21:56:09 +0000298 break;
299 case MachineOperand::MO_ExternalSymbol:
300 OS << "<es:" << getSymbolName();
301 if (getOffset()) OS << "+" << getOffset();
Chris Lattner31530612009-06-24 17:54:48 +0000302 OS << '>';
Chris Lattnerf7382302007-12-30 21:56:09 +0000303 break;
Dan Gohman8c2b5252009-10-30 01:27:03 +0000304 case MachineOperand::MO_BlockAddress:
Dale Johannesen5f72a5e2010-01-13 00:00:24 +0000305 OS << '<';
Dan Gohman0ba90f32009-10-31 20:19:03 +0000306 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
Dan Gohman8c2b5252009-10-30 01:27:03 +0000307 OS << '>';
308 break;
Dale Johannesen5f72a5e2010-01-13 00:00:24 +0000309 case MachineOperand::MO_Metadata:
310 OS << '<';
311 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
312 OS << '>';
313 break;
Chris Lattner72aaa3c2010-03-13 08:14:18 +0000314 case MachineOperand::MO_MCSymbol:
315 OS << "<MCSym=" << *getMCSymbol() << '>';
316 break;
Chris Lattnerf7382302007-12-30 21:56:09 +0000317 default:
Torok Edwinc23197a2009-07-14 16:55:14 +0000318 llvm_unreachable("Unrecognized operand type");
Chris Lattnerf7382302007-12-30 21:56:09 +0000319 }
Chris Lattner31530612009-06-24 17:54:48 +0000320
321 if (unsigned TF = getTargetFlags())
322 OS << "[TF=" << TF << ']';
Chris Lattnerf7382302007-12-30 21:56:09 +0000323}
324
325//===----------------------------------------------------------------------===//
Dan Gohmance42e402008-07-07 20:32:02 +0000326// MachineMemOperand Implementation
327//===----------------------------------------------------------------------===//
328
Chris Lattner40a858f2010-09-21 05:39:30 +0000329/// getAddrSpace - Return the LLVM IR address space number that this pointer
330/// points into.
331unsigned MachinePointerInfo::getAddrSpace() const {
332 if (V == 0) return 0;
333 return cast<PointerType>(V->getType())->getAddressSpace();
334}
335
Chris Lattnere8639032010-09-21 06:22:23 +0000336/// getConstantPool - Return a MachinePointerInfo record that refers to the
337/// constant pool.
338MachinePointerInfo MachinePointerInfo::getConstantPool() {
339 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
340}
341
342/// getFixedStack - Return a MachinePointerInfo record that refers to the
343/// the specified FrameIndex.
344MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
345 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
346}
347
Chris Lattner1daa6f42010-09-21 06:43:24 +0000348MachinePointerInfo MachinePointerInfo::getJumpTable() {
349 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
350}
351
352MachinePointerInfo MachinePointerInfo::getGOT() {
353 return MachinePointerInfo(PseudoSourceValue::getGOT());
354}
Chris Lattner40a858f2010-09-21 05:39:30 +0000355
Chris Lattnerfc448ff2010-09-21 18:51:21 +0000356MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
357 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
358}
359
Chris Lattnerda39c392010-09-21 04:32:08 +0000360MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
Dan Gohmanf96e4bd2010-10-20 00:31:05 +0000361 uint64_t s, unsigned int a,
362 const MDNode *TBAAInfo)
Chris Lattnerda39c392010-09-21 04:32:08 +0000363 : PtrInfo(ptrinfo), Size(s),
Dan Gohmanf96e4bd2010-10-20 00:31:05 +0000364 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
365 TBAAInfo(TBAAInfo) {
Chris Lattnerda39c392010-09-21 04:32:08 +0000366 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
367 "invalid pointer value");
Dan Gohman28f02fd2009-09-21 19:47:04 +0000368 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
Dan Gohmanc5e1f982008-07-16 15:56:42 +0000369 assert((isLoad() || isStore()) && "Not a load/store!");
Dan Gohmance42e402008-07-07 20:32:02 +0000370}
371
Dan Gohmanb8d2f552008-08-20 15:58:01 +0000372/// Profile - Gather unique data for the object.
373///
374void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
Chris Lattnere8e2e802010-09-21 04:23:39 +0000375 ID.AddInteger(getOffset());
Dan Gohmanb8d2f552008-08-20 15:58:01 +0000376 ID.AddInteger(Size);
Chris Lattnere8e2e802010-09-21 04:23:39 +0000377 ID.AddPointer(getValue());
Dan Gohmanb8d2f552008-08-20 15:58:01 +0000378 ID.AddInteger(Flags);
379}
380
Dan Gohmanc76909a2009-09-25 20:36:54 +0000381void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
382 // The Value and Offset may differ due to CSE. But the flags and size
383 // should be the same.
384 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
385 assert(MMO->getSize() == getSize() && "Size mismatch!");
386
387 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
388 // Update the alignment value.
David Greeneba2b2972010-02-15 16:48:31 +0000389 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
390 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
Dan Gohmanc76909a2009-09-25 20:36:54 +0000391 // Also update the base and offset, because the new alignment may
392 // not be applicable with the old ones.
Chris Lattnere8e2e802010-09-21 04:23:39 +0000393 PtrInfo = MMO->PtrInfo;
Dan Gohmanc76909a2009-09-25 20:36:54 +0000394 }
395}
396
Dan Gohman4b2ebc12009-09-25 23:33:20 +0000397/// getAlignment - Return the minimum known alignment in bytes of the
398/// actual memory reference.
399uint64_t MachineMemOperand::getAlignment() const {
400 return MinAlign(getBaseAlignment(), getOffset());
401}
402
Dan Gohmanc76909a2009-09-25 20:36:54 +0000403raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
404 assert((MMO.isLoad() || MMO.isStore()) &&
Dan Gohmancd26ec52009-09-23 01:33:16 +0000405 "SV has to be a load, store or both.");
406
Dan Gohmanc76909a2009-09-25 20:36:54 +0000407 if (MMO.isVolatile())
Dan Gohmancd26ec52009-09-23 01:33:16 +0000408 OS << "Volatile ";
409
Dan Gohmanc76909a2009-09-25 20:36:54 +0000410 if (MMO.isLoad())
Dan Gohmancd26ec52009-09-23 01:33:16 +0000411 OS << "LD";
Dan Gohmanc76909a2009-09-25 20:36:54 +0000412 if (MMO.isStore())
Dan Gohmancd26ec52009-09-23 01:33:16 +0000413 OS << "ST";
Dan Gohmanc76909a2009-09-25 20:36:54 +0000414 OS << MMO.getSize();
Dan Gohmancd26ec52009-09-23 01:33:16 +0000415
416 // Print the address information.
417 OS << "[";
Dan Gohmanc76909a2009-09-25 20:36:54 +0000418 if (!MMO.getValue())
Dan Gohmancd26ec52009-09-23 01:33:16 +0000419 OS << "<unknown>";
420 else
Dan Gohmanc76909a2009-09-25 20:36:54 +0000421 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
Dan Gohmancd26ec52009-09-23 01:33:16 +0000422
423 // If the alignment of the memory reference itself differs from the alignment
424 // of the base pointer, print the base alignment explicitly, next to the base
425 // pointer.
Dan Gohmanc76909a2009-09-25 20:36:54 +0000426 if (MMO.getBaseAlignment() != MMO.getAlignment())
427 OS << "(align=" << MMO.getBaseAlignment() << ")";
Dan Gohmancd26ec52009-09-23 01:33:16 +0000428
Dan Gohmanc76909a2009-09-25 20:36:54 +0000429 if (MMO.getOffset() != 0)
430 OS << "+" << MMO.getOffset();
Dan Gohmancd26ec52009-09-23 01:33:16 +0000431 OS << "]";
432
433 // Print the alignment of the reference.
Dan Gohmanc76909a2009-09-25 20:36:54 +0000434 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
435 MMO.getBaseAlignment() != MMO.getSize())
436 OS << "(align=" << MMO.getAlignment() << ")";
Dan Gohmancd26ec52009-09-23 01:33:16 +0000437
Dan Gohmanf96e4bd2010-10-20 00:31:05 +0000438 // Print TBAA info.
439 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
440 OS << "(tbaa=";
441 if (TBAAInfo->getNumOperands() > 0)
442 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
443 else
444 OS << "<unknown>";
445 OS << ")";
446 }
447
Bill Wendlingd65ba722011-04-29 23:45:22 +0000448 // Print nontemporal info.
449 if (MMO.isNonTemporal())
450 OS << "(nontemporal)";
451
Dan Gohmancd26ec52009-09-23 01:33:16 +0000452 return OS;
453}
454
Dan Gohmance42e402008-07-07 20:32:02 +0000455//===----------------------------------------------------------------------===//
Chris Lattnerf7382302007-12-30 21:56:09 +0000456// MachineInstr Implementation
457//===----------------------------------------------------------------------===//
458
Evan Chengc0f64ff2006-11-27 23:37:22 +0000459/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
Evan Cheng67f660c2006-11-30 07:08:44 +0000460/// TID NULL and no operands.
Evan Chengc0f64ff2006-11-27 23:37:22 +0000461MachineInstr::MachineInstr()
Anton Korobeynikov6dd97472011-03-05 18:43:04 +0000462 : TID(0), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
463 MemRefs(0), MemRefsEnd(0),
Chris Lattnera4f2bb02010-04-02 20:17:23 +0000464 Parent(0) {
Dan Gohman2c3f7ae2008-07-17 23:49:46 +0000465 // Make sure that we get added to a machine basicblock
466 LeakDetector::addGarbageObject(this);
Chris Lattner72791222002-10-28 20:59:49 +0000467}
468
Evan Cheng67f660c2006-11-30 07:08:44 +0000469void MachineInstr::addImplicitDefUseOperands() {
470 if (TID->ImplicitDefs)
Chris Lattnera4161ee2007-12-30 00:12:25 +0000471 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
Chris Lattner8019f412007-12-30 00:41:17 +0000472 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
Evan Cheng67f660c2006-11-30 07:08:44 +0000473 if (TID->ImplicitUses)
Chris Lattnera4161ee2007-12-30 00:12:25 +0000474 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
Chris Lattner8019f412007-12-30 00:41:17 +0000475 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
Evan Chengd7de4962006-11-13 23:34:06 +0000476}
477
Bob Wilson0855cad2010-04-09 04:34:03 +0000478/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
479/// implicit operands. It reserves space for the number of operands specified by
480/// the TargetInstrDesc.
Chris Lattner749c6f62008-01-07 07:27:27 +0000481MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
Anton Korobeynikov6dd97472011-03-05 18:43:04 +0000482 : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
Chris Lattnera4f2bb02010-04-02 20:17:23 +0000483 MemRefs(0), MemRefsEnd(0), Parent(0) {
Bob Wilson1793ab92010-04-09 04:46:43 +0000484 if (!NoImp)
485 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
Chris Lattner349c4952008-01-07 03:13:06 +0000486 Operands.reserve(NumImplicitOps + TID->getNumOperands());
Evan Chengfa945722007-10-13 02:23:01 +0000487 if (!NoImp)
488 addImplicitDefUseOperands();
Dan Gohman2c3f7ae2008-07-17 23:49:46 +0000489 // Make sure that we get added to a machine basicblock
490 LeakDetector::addGarbageObject(this);
Evan Chengd7de4962006-11-13 23:34:06 +0000491}
492
Dale Johannesen06efc022009-01-27 23:20:29 +0000493/// MachineInstr ctor - As above, but with a DebugLoc.
494MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
495 bool NoImp)
Anton Korobeynikov6dd97472011-03-05 18:43:04 +0000496 : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
497 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
Bob Wilson1793ab92010-04-09 04:46:43 +0000498 if (!NoImp)
499 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
Dale Johannesen06efc022009-01-27 23:20:29 +0000500 Operands.reserve(NumImplicitOps + TID->getNumOperands());
501 if (!NoImp)
502 addImplicitDefUseOperands();
503 // Make sure that we get added to a machine basicblock
504 LeakDetector::addGarbageObject(this);
505}
506
507/// MachineInstr ctor - Work exactly the same as the ctor two above, except
508/// that the MachineInstr is created and added to the end of the specified
509/// basic block.
Dale Johannesen06efc022009-01-27 23:20:29 +0000510MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
Anton Korobeynikov6dd97472011-03-05 18:43:04 +0000511 : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
Chris Lattnera4f2bb02010-04-02 20:17:23 +0000512 MemRefs(0), MemRefsEnd(0), Parent(0) {
Dale Johannesen06efc022009-01-27 23:20:29 +0000513 assert(MBB && "Cannot use inserting ctor with null basic block!");
Bob Wilson1793ab92010-04-09 04:46:43 +0000514 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
Dale Johannesen06efc022009-01-27 23:20:29 +0000515 Operands.reserve(NumImplicitOps + TID->getNumOperands());
516 addImplicitDefUseOperands();
517 // Make sure that we get added to a machine basicblock
518 LeakDetector::addGarbageObject(this);
519 MBB->push_back(this); // Add instruction to end of basic block!
520}
521
522/// MachineInstr ctor - As above, but with a DebugLoc.
523///
524MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
Chris Lattner749c6f62008-01-07 07:27:27 +0000525 const TargetInstrDesc &tid)
Anton Korobeynikov6dd97472011-03-05 18:43:04 +0000526 : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
527 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
Chris Lattnerddd7fcb2002-10-29 23:19:00 +0000528 assert(MBB && "Cannot use inserting ctor with null basic block!");
Bob Wilson1793ab92010-04-09 04:46:43 +0000529 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
Chris Lattner349c4952008-01-07 03:13:06 +0000530 Operands.reserve(NumImplicitOps + TID->getNumOperands());
Evan Cheng67f660c2006-11-30 07:08:44 +0000531 addImplicitDefUseOperands();
Dan Gohman2c3f7ae2008-07-17 23:49:46 +0000532 // Make sure that we get added to a machine basicblock
533 LeakDetector::addGarbageObject(this);
Chris Lattnerddd7fcb2002-10-29 23:19:00 +0000534 MBB->push_back(this); // Add instruction to end of basic block!
535}
536
Misha Brukmance22e762004-07-09 14:45:17 +0000537/// MachineInstr ctor - Copies MachineInstr arg exactly
538///
Evan Cheng1ed99222008-07-19 00:37:25 +0000539MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
Anton Korobeynikov6dd97472011-03-05 18:43:04 +0000540 : TID(&MI.getDesc()), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
Dan Gohmanc76909a2009-09-25 20:36:54 +0000541 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
542 Parent(0), debugLoc(MI.getDebugLoc()) {
Chris Lattner943b5e12006-05-04 19:14:44 +0000543 Operands.reserve(MI.getNumOperands());
Tanya Lattnerb5159ed2004-05-23 20:58:02 +0000544
Misha Brukmance22e762004-07-09 14:45:17 +0000545 // Add operands
Evan Cheng1ed99222008-07-19 00:37:25 +0000546 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
547 addOperand(MI.getOperand(i));
548 NumImplicitOps = MI.NumImplicitOps;
Tanya Lattner0c63e032004-05-24 03:14:18 +0000549
Anton Korobeynikov6dd97472011-03-05 18:43:04 +0000550 // Copy all the flags.
551 Flags = MI.Flags;
552
Dan Gohman8e5f2c62008-07-07 23:14:23 +0000553 // Set parent to null.
Chris Lattnerf20c1a42007-12-31 04:56:33 +0000554 Parent = 0;
Dan Gohman6116a732008-07-21 18:47:29 +0000555
556 LeakDetector::addGarbageObject(this);
Tanya Lattner466b5342004-05-23 19:35:12 +0000557}
558
Misha Brukmance22e762004-07-09 14:45:17 +0000559MachineInstr::~MachineInstr() {
Dan Gohman2c3f7ae2008-07-17 23:49:46 +0000560 LeakDetector::removeGarbageObject(this);
Chris Lattnere12d6ab2007-12-30 06:11:04 +0000561#ifndef NDEBUG
Chris Lattner62ed6b92008-01-01 01:12:31 +0000562 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
Chris Lattnere12d6ab2007-12-30 06:11:04 +0000563 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
Dan Gohmand735b802008-10-03 15:45:36 +0000564 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
Chris Lattner62ed6b92008-01-01 01:12:31 +0000565 "Reg operand def/use list corrupted");
566 }
Chris Lattnere12d6ab2007-12-30 06:11:04 +0000567#endif
Alkis Evlogimenosaad5c052004-02-16 07:17:43 +0000568}
569
Chris Lattner62ed6b92008-01-01 01:12:31 +0000570/// getRegInfo - If this instruction is embedded into a MachineFunction,
571/// return the MachineRegisterInfo object for the current function, otherwise
572/// return null.
573MachineRegisterInfo *MachineInstr::getRegInfo() {
574 if (MachineBasicBlock *MBB = getParent())
Dan Gohman4e526b92008-07-08 23:59:09 +0000575 return &MBB->getParent()->getRegInfo();
Chris Lattner62ed6b92008-01-01 01:12:31 +0000576 return 0;
577}
578
579/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
580/// this instruction from their respective use lists. This requires that the
581/// operands already be on their use lists.
582void MachineInstr::RemoveRegOperandsFromUseLists() {
583 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
Dan Gohmand735b802008-10-03 15:45:36 +0000584 if (Operands[i].isReg())
Chris Lattner62ed6b92008-01-01 01:12:31 +0000585 Operands[i].RemoveRegOperandFromRegInfo();
586 }
587}
588
589/// AddRegOperandsToUseLists - Add all of the register operands in
590/// this instruction from their respective use lists. This requires that the
591/// operands not be on their use lists yet.
592void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
593 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
Dan Gohmand735b802008-10-03 15:45:36 +0000594 if (Operands[i].isReg())
Chris Lattner62ed6b92008-01-01 01:12:31 +0000595 Operands[i].AddRegOperandToRegInfo(&RegInfo);
596 }
597}
598
599
600/// addOperand - Add the specified operand to the instruction. If it is an
601/// implicit operand, it is added to the end of the operand list. If it is
602/// an explicit operand it is added at the end of the explicit operand list
603/// (before the first implicit operand).
604void MachineInstr::addOperand(const MachineOperand &Op) {
Dan Gohmand735b802008-10-03 15:45:36 +0000605 bool isImpReg = Op.isReg() && Op.isImplicit();
Chris Lattner62ed6b92008-01-01 01:12:31 +0000606 assert((isImpReg || !OperandsComplete()) &&
607 "Trying to add an operand to a machine instr that is already done!");
608
Dan Gohmanbcf28c02008-12-09 22:45:08 +0000609 MachineRegisterInfo *RegInfo = getRegInfo();
610
Chris Lattner62ed6b92008-01-01 01:12:31 +0000611 // If we are adding the operand to the end of the list, our job is simpler.
612 // This is true most of the time, so this is a reasonable optimization.
613 if (isImpReg || NumImplicitOps == 0) {
614 // We can only do this optimization if we know that the operand list won't
615 // reallocate.
616 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
617 Operands.push_back(Op);
618
619 // Set the parent of the operand.
620 Operands.back().ParentMI = this;
621
622 // If the operand is a register, update the operand's use list.
Jim Grosbach06801722009-12-16 19:43:02 +0000623 if (Op.isReg()) {
Dan Gohmanbcf28c02008-12-09 22:45:08 +0000624 Operands.back().AddRegOperandToRegInfo(RegInfo);
Jim Grosbach06801722009-12-16 19:43:02 +0000625 // If the register operand is flagged as early, mark the operand as such
626 unsigned OpNo = Operands.size() - 1;
627 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
628 Operands[OpNo].setIsEarlyClobber(true);
629 }
Chris Lattner62ed6b92008-01-01 01:12:31 +0000630 return;
631 }
632 }
633
634 // Otherwise, we have to insert a real operand before any implicit ones.
635 unsigned OpNo = Operands.size()-NumImplicitOps;
636
Chris Lattner62ed6b92008-01-01 01:12:31 +0000637 // If this instruction isn't embedded into a function, then we don't need to
638 // update any operand lists.
639 if (RegInfo == 0) {
640 // Simple insertion, no reginfo update needed for other register operands.
641 Operands.insert(Operands.begin()+OpNo, Op);
642 Operands[OpNo].ParentMI = this;
643
644 // Do explicitly set the reginfo for this operand though, to ensure the
645 // next/prev fields are properly nulled out.
Jim Grosbach06801722009-12-16 19:43:02 +0000646 if (Operands[OpNo].isReg()) {
Chris Lattner62ed6b92008-01-01 01:12:31 +0000647 Operands[OpNo].AddRegOperandToRegInfo(0);
Jim Grosbach06801722009-12-16 19:43:02 +0000648 // If the register operand is flagged as early, mark the operand as such
649 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
650 Operands[OpNo].setIsEarlyClobber(true);
651 }
Chris Lattner62ed6b92008-01-01 01:12:31 +0000652
653 } else if (Operands.size()+1 <= Operands.capacity()) {
654 // Otherwise, we have to remove register operands from their register use
655 // list, add the operand, then add the register operands back to their use
656 // list. This also must handle the case when the operand list reallocates
657 // to somewhere else.
658
659 // If insertion of this operand won't cause reallocation of the operand
660 // list, just remove the implicit operands, add the operand, then re-add all
661 // the rest of the operands.
662 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
Dan Gohmand735b802008-10-03 15:45:36 +0000663 assert(Operands[i].isReg() && "Should only be an implicit reg!");
Chris Lattner62ed6b92008-01-01 01:12:31 +0000664 Operands[i].RemoveRegOperandFromRegInfo();
665 }
666
667 // Add the operand. If it is a register, add it to the reg list.
668 Operands.insert(Operands.begin()+OpNo, Op);
669 Operands[OpNo].ParentMI = this;
670
Jim Grosbach06801722009-12-16 19:43:02 +0000671 if (Operands[OpNo].isReg()) {
Chris Lattner62ed6b92008-01-01 01:12:31 +0000672 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
Jim Grosbach06801722009-12-16 19:43:02 +0000673 // If the register operand is flagged as early, mark the operand as such
674 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
675 Operands[OpNo].setIsEarlyClobber(true);
676 }
Chris Lattner62ed6b92008-01-01 01:12:31 +0000677
678 // Re-add all the implicit ops.
679 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
Dan Gohmand735b802008-10-03 15:45:36 +0000680 assert(Operands[i].isReg() && "Should only be an implicit reg!");
Chris Lattner62ed6b92008-01-01 01:12:31 +0000681 Operands[i].AddRegOperandToRegInfo(RegInfo);
682 }
683 } else {
684 // Otherwise, we will be reallocating the operand list. Remove all reg
685 // operands from their list, then readd them after the operand list is
686 // reallocated.
687 RemoveRegOperandsFromUseLists();
688
689 Operands.insert(Operands.begin()+OpNo, Op);
690 Operands[OpNo].ParentMI = this;
691
692 // Re-add all the operands.
693 AddRegOperandsToUseLists(*RegInfo);
Jim Grosbach06801722009-12-16 19:43:02 +0000694
695 // If the register operand is flagged as early, mark the operand as such
696 if (Operands[OpNo].isReg()
697 && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
698 Operands[OpNo].setIsEarlyClobber(true);
Chris Lattner62ed6b92008-01-01 01:12:31 +0000699 }
700}
701
702/// RemoveOperand - Erase an operand from an instruction, leaving it with one
703/// fewer operand than it started with.
704///
705void MachineInstr::RemoveOperand(unsigned OpNo) {
706 assert(OpNo < Operands.size() && "Invalid operand number");
707
708 // Special case removing the last one.
709 if (OpNo == Operands.size()-1) {
710 // If needed, remove from the reg def/use list.
Dan Gohmand735b802008-10-03 15:45:36 +0000711 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
Chris Lattner62ed6b92008-01-01 01:12:31 +0000712 Operands.back().RemoveRegOperandFromRegInfo();
713
714 Operands.pop_back();
715 return;
716 }
717
718 // Otherwise, we are removing an interior operand. If we have reginfo to
719 // update, remove all operands that will be shifted down from their reg lists,
720 // move everything down, then re-add them.
721 MachineRegisterInfo *RegInfo = getRegInfo();
722 if (RegInfo) {
723 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
Dan Gohmand735b802008-10-03 15:45:36 +0000724 if (Operands[i].isReg())
Chris Lattner62ed6b92008-01-01 01:12:31 +0000725 Operands[i].RemoveRegOperandFromRegInfo();
726 }
727 }
728
729 Operands.erase(Operands.begin()+OpNo);
730
731 if (RegInfo) {
732 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
Dan Gohmand735b802008-10-03 15:45:36 +0000733 if (Operands[i].isReg())
Chris Lattner62ed6b92008-01-01 01:12:31 +0000734 Operands[i].AddRegOperandToRegInfo(RegInfo);
735 }
736 }
737}
738
Dan Gohmanc76909a2009-09-25 20:36:54 +0000739/// addMemOperand - Add a MachineMemOperand to the machine instruction.
740/// This function should be used only occasionally. The setMemRefs function
741/// is the primary method for setting up a MachineInstr's MemRefs list.
Dan Gohman8e5f2c62008-07-07 23:14:23 +0000742void MachineInstr::addMemOperand(MachineFunction &MF,
Dan Gohmanc76909a2009-09-25 20:36:54 +0000743 MachineMemOperand *MO) {
744 mmo_iterator OldMemRefs = MemRefs;
745 mmo_iterator OldMemRefsEnd = MemRefsEnd;
Dan Gohman8e5f2c62008-07-07 23:14:23 +0000746
Dan Gohmanc76909a2009-09-25 20:36:54 +0000747 size_t NewNum = (MemRefsEnd - MemRefs) + 1;
748 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
749 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
Dan Gohman8e5f2c62008-07-07 23:14:23 +0000750
Dan Gohmanc76909a2009-09-25 20:36:54 +0000751 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
752 NewMemRefs[NewNum - 1] = MO;
753
754 MemRefs = NewMemRefs;
755 MemRefsEnd = NewMemRefsEnd;
756}
Chris Lattner62ed6b92008-01-01 01:12:31 +0000757
Evan Cheng506049f2010-03-03 01:44:33 +0000758bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
759 MICheckType Check) const {
Evan Cheng34cdf6e2010-03-03 21:54:14 +0000760 // If opcodes or number of operands are not the same then the two
761 // instructions are obviously not identical.
762 if (Other->getOpcode() != getOpcode() ||
763 Other->getNumOperands() != getNumOperands())
764 return false;
765
766 // Check operands to make sure they match.
767 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
768 const MachineOperand &MO = getOperand(i);
769 const MachineOperand &OMO = Other->getOperand(i);
Evan Chengcbc988b2011-05-12 00:56:58 +0000770 if (!MO.isReg()) {
771 if (!MO.isIdenticalTo(OMO))
772 return false;
773 continue;
774 }
775
Evan Cheng34cdf6e2010-03-03 21:54:14 +0000776 // Clients may or may not want to ignore defs when testing for equality.
777 // For example, machine CSE pass only cares about finding common
778 // subexpressions, so it's safe to ignore virtual register defs.
Evan Chengcbc988b2011-05-12 00:56:58 +0000779 if (MO.isDef()) {
Evan Cheng34cdf6e2010-03-03 21:54:14 +0000780 if (Check == IgnoreDefs)
781 continue;
Evan Chengcbc988b2011-05-12 00:56:58 +0000782 else if (Check == IgnoreVRegDefs) {
783 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
784 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
785 if (MO.getReg() != OMO.getReg())
786 return false;
787 } else {
788 if (!MO.isIdenticalTo(OMO))
Evan Cheng34cdf6e2010-03-03 21:54:14 +0000789 return false;
Evan Chengcbc988b2011-05-12 00:56:58 +0000790 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
791 return false;
792 }
793 } else {
794 if (!MO.isIdenticalTo(OMO))
795 return false;
796 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
797 return false;
798 }
Evan Cheng34cdf6e2010-03-03 21:54:14 +0000799 }
800 return true;
Evan Cheng506049f2010-03-03 01:44:33 +0000801}
802
Chris Lattner48d7c062006-04-17 21:35:41 +0000803/// removeFromParent - This method unlinks 'this' from the containing basic
804/// block, and returns it, but does not delete it.
805MachineInstr *MachineInstr::removeFromParent() {
806 assert(getParent() && "Not embedded in a basic block!");
807 getParent()->remove(this);
808 return this;
809}
810
811
Dan Gohman8e5f2c62008-07-07 23:14:23 +0000812/// eraseFromParent - This method unlinks 'this' from the containing basic
813/// block, and deletes it.
814void MachineInstr::eraseFromParent() {
815 assert(getParent() && "Not embedded in a basic block!");
816 getParent()->erase(this);
817}
818
819
Brian Gaeke21326fc2004-02-13 04:39:32 +0000820/// OperandComplete - Return true if it's illegal to add a new operand
821///
Chris Lattner2a90ba62004-02-12 16:09:53 +0000822bool MachineInstr::OperandsComplete() const {
Chris Lattner349c4952008-01-07 03:13:06 +0000823 unsigned short NumOperands = TID->getNumOperands();
Chris Lattner8f707e12008-01-07 05:19:29 +0000824 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
Vikram S. Adve34977822003-05-31 07:39:06 +0000825 return true; // Broken: we have all the operands of this instruction!
Chris Lattner413746e2002-10-28 20:48:39 +0000826 return false;
827}
828
Evan Cheng19e3f312007-05-15 01:26:09 +0000829/// getNumExplicitOperands - Returns the number of non-implicit operands.
830///
831unsigned MachineInstr::getNumExplicitOperands() const {
Chris Lattner349c4952008-01-07 03:13:06 +0000832 unsigned NumOperands = TID->getNumOperands();
Chris Lattner8f707e12008-01-07 05:19:29 +0000833 if (!TID->isVariadic())
Evan Cheng19e3f312007-05-15 01:26:09 +0000834 return NumOperands;
835
Dan Gohman9407cd42009-04-15 17:59:11 +0000836 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
837 const MachineOperand &MO = getOperand(i);
Dan Gohmand735b802008-10-03 15:45:36 +0000838 if (!MO.isReg() || !MO.isImplicit())
Evan Cheng19e3f312007-05-15 01:26:09 +0000839 NumOperands++;
840 }
841 return NumOperands;
842}
843
Evan Chengc36b7062011-01-07 23:50:32 +0000844bool MachineInstr::isStackAligningInlineAsm() const {
845 if (isInlineAsm()) {
846 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
847 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
848 return true;
849 }
850 return false;
851}
Chris Lattner8ace2cd2006-10-20 22:39:59 +0000852
Evan Chengfaa51072007-04-26 19:00:32 +0000853/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
Jim Grosbachf9ca50e2009-09-17 17:57:26 +0000854/// the specific register or -1 if it is not found. It further tightens
Evan Cheng76d7e762007-02-23 01:04:26 +0000855/// the search criteria to a use that kills the register if isKill is true.
Evan Cheng6130f662008-03-05 00:59:57 +0000856int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
857 const TargetRegisterInfo *TRI) const {
Evan Cheng576d1232006-12-06 08:27:42 +0000858 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
Evan Chengf277ee42007-05-29 18:35:22 +0000859 const MachineOperand &MO = getOperand(i);
Dan Gohmand735b802008-10-03 15:45:36 +0000860 if (!MO.isReg() || !MO.isUse())
Evan Cheng6130f662008-03-05 00:59:57 +0000861 continue;
862 unsigned MOReg = MO.getReg();
863 if (!MOReg)
864 continue;
865 if (MOReg == Reg ||
866 (TRI &&
867 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
868 TargetRegisterInfo::isPhysicalRegister(Reg) &&
869 TRI->isSubRegister(MOReg, Reg)))
Evan Cheng76d7e762007-02-23 01:04:26 +0000870 if (!isKill || MO.isKill())
Evan Cheng32eb1f12007-03-26 22:37:45 +0000871 return i;
Evan Cheng576d1232006-12-06 08:27:42 +0000872 }
Evan Cheng32eb1f12007-03-26 22:37:45 +0000873 return -1;
Evan Cheng576d1232006-12-06 08:27:42 +0000874}
Jakob Stoklund Olesen7ebc4d62010-05-19 20:36:22 +0000875
Jakob Stoklund Olesen18b2c9d2010-05-21 20:02:01 +0000876/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
877/// indicating if this instruction reads or writes Reg. This also considers
878/// partial defines.
879std::pair<bool,bool>
880MachineInstr::readsWritesVirtualRegister(unsigned Reg,
881 SmallVectorImpl<unsigned> *Ops) const {
882 bool PartDef = false; // Partial redefine.
883 bool FullDef = false; // Full define.
884 bool Use = false;
Jakob Stoklund Olesen7ebc4d62010-05-19 20:36:22 +0000885
886 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
887 const MachineOperand &MO = getOperand(i);
888 if (!MO.isReg() || MO.getReg() != Reg)
889 continue;
Jakob Stoklund Olesen18b2c9d2010-05-21 20:02:01 +0000890 if (Ops)
891 Ops->push_back(i);
Jakob Stoklund Olesen7ebc4d62010-05-19 20:36:22 +0000892 if (MO.isUse())
Jakob Stoklund Olesen18b2c9d2010-05-21 20:02:01 +0000893 Use |= !MO.isUndef();
894 else if (MO.getSubReg())
Jakob Stoklund Olesen7ebc4d62010-05-19 20:36:22 +0000895 PartDef = true;
896 else
897 FullDef = true;
898 }
Jakob Stoklund Olesen18b2c9d2010-05-21 20:02:01 +0000899 // A partial redefine uses Reg unless there is also a full define.
900 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
Jakob Stoklund Olesen7ebc4d62010-05-19 20:36:22 +0000901}
902
Evan Cheng6130f662008-03-05 00:59:57 +0000903/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
Dan Gohman703bfe62008-05-06 00:20:10 +0000904/// the specified register or -1 if it is not found. If isDead is true, defs
905/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
906/// also checks if there is a def of a super-register.
Evan Cheng1015ba72010-05-21 20:53:24 +0000907int
908MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
909 const TargetRegisterInfo *TRI) const {
910 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
Evan Chengb371f452007-02-19 21:49:54 +0000911 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
Evan Cheng6130f662008-03-05 00:59:57 +0000912 const MachineOperand &MO = getOperand(i);
Dan Gohmand735b802008-10-03 15:45:36 +0000913 if (!MO.isReg() || !MO.isDef())
Evan Cheng6130f662008-03-05 00:59:57 +0000914 continue;
915 unsigned MOReg = MO.getReg();
Evan Cheng1015ba72010-05-21 20:53:24 +0000916 bool Found = (MOReg == Reg);
917 if (!Found && TRI && isPhys &&
918 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
919 if (Overlap)
920 Found = TRI->regsOverlap(MOReg, Reg);
921 else
922 Found = TRI->isSubRegister(MOReg, Reg);
923 }
924 if (Found && (!isDead || MO.isDead()))
925 return i;
Evan Chengb371f452007-02-19 21:49:54 +0000926 }
Evan Cheng6130f662008-03-05 00:59:57 +0000927 return -1;
Evan Chengb371f452007-02-19 21:49:54 +0000928}
Evan Cheng19e3f312007-05-15 01:26:09 +0000929
Evan Chengf277ee42007-05-29 18:35:22 +0000930/// findFirstPredOperandIdx() - Find the index of the first operand in the
931/// operand list that is used to represent the predicate. It returns -1 if
932/// none is found.
933int MachineInstr::findFirstPredOperandIdx() const {
Chris Lattner749c6f62008-01-07 07:27:27 +0000934 const TargetInstrDesc &TID = getDesc();
935 if (TID.isPredicable()) {
Evan Cheng19e3f312007-05-15 01:26:09 +0000936 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
Chris Lattner749c6f62008-01-07 07:27:27 +0000937 if (TID.OpInfo[i].isPredicate())
Evan Chengf277ee42007-05-29 18:35:22 +0000938 return i;
Evan Cheng19e3f312007-05-15 01:26:09 +0000939 }
940
Evan Chengf277ee42007-05-29 18:35:22 +0000941 return -1;
Evan Cheng19e3f312007-05-15 01:26:09 +0000942}
Evan Chengb371f452007-02-19 21:49:54 +0000943
Bob Wilsond9df5012009-04-09 17:16:43 +0000944/// isRegTiedToUseOperand - Given the index of a register def operand,
945/// check if the register def is tied to a source operand, due to either
946/// two-address elimination or inline assembly constraints. Returns the
947/// first tied use operand index by reference is UseOpIdx is not null.
Jakob Stoklund Olesence9be2c2009-04-29 20:57:16 +0000948bool MachineInstr::
949isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
Chris Lattner518bb532010-02-09 19:54:29 +0000950 if (isInlineAsm()) {
Evan Chengc36b7062011-01-07 23:50:32 +0000951 assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
Bob Wilsond9df5012009-04-09 17:16:43 +0000952 const MachineOperand &MO = getOperand(DefOpIdx);
Chris Lattnerc30aa7b2009-04-09 23:33:34 +0000953 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
Evan Chengfb112882009-03-23 08:01:15 +0000954 return false;
Evan Chengef5d0702009-06-24 02:05:51 +0000955 // Determine the actual operand index that corresponds to this index.
Evan Chengfb112882009-03-23 08:01:15 +0000956 unsigned DefNo = 0;
Evan Chengef5d0702009-06-24 02:05:51 +0000957 unsigned DefPart = 0;
Evan Chengc36b7062011-01-07 23:50:32 +0000958 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
959 i < e; ) {
Evan Chengfb112882009-03-23 08:01:15 +0000960 const MachineOperand &FMO = getOperand(i);
Jakob Stoklund Olesen45d34fe2009-07-19 19:09:59 +0000961 // After the normal asm operands there may be additional imp-def regs.
962 if (!FMO.isImm())
963 return false;
Evan Chengfb112882009-03-23 08:01:15 +0000964 // Skip over this def.
Evan Chengef5d0702009-06-24 02:05:51 +0000965 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
966 unsigned PrevDef = i + 1;
967 i = PrevDef + NumOps;
968 if (i > DefOpIdx) {
969 DefPart = DefOpIdx - PrevDef;
Evan Chengfb112882009-03-23 08:01:15 +0000970 break;
Evan Chengef5d0702009-06-24 02:05:51 +0000971 }
Evan Chengfb112882009-03-23 08:01:15 +0000972 ++DefNo;
973 }
Evan Chengc36b7062011-01-07 23:50:32 +0000974 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
975 i != e; ++i) {
Evan Chengfb112882009-03-23 08:01:15 +0000976 const MachineOperand &FMO = getOperand(i);
977 if (!FMO.isImm())
978 continue;
979 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
980 continue;
981 unsigned Idx;
Evan Chengef5d0702009-06-24 02:05:51 +0000982 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
Bob Wilsond9df5012009-04-09 17:16:43 +0000983 Idx == DefNo) {
984 if (UseOpIdx)
Evan Chengef5d0702009-06-24 02:05:51 +0000985 *UseOpIdx = (unsigned)i + 1 + DefPart;
Evan Chengfb112882009-03-23 08:01:15 +0000986 return true;
Bob Wilsond9df5012009-04-09 17:16:43 +0000987 }
Evan Chengfb112882009-03-23 08:01:15 +0000988 }
Evan Chengef5d0702009-06-24 02:05:51 +0000989 return false;
Evan Chengfb112882009-03-23 08:01:15 +0000990 }
991
Bob Wilsond9df5012009-04-09 17:16:43 +0000992 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
Chris Lattner749c6f62008-01-07 07:27:27 +0000993 const TargetInstrDesc &TID = getDesc();
Evan Chengef0732d2008-07-10 07:35:43 +0000994 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
995 const MachineOperand &MO = getOperand(i);
Dan Gohman2ce7f202008-12-05 05:45:42 +0000996 if (MO.isReg() && MO.isUse() &&
Bob Wilsond9df5012009-04-09 17:16:43 +0000997 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
998 if (UseOpIdx)
999 *UseOpIdx = (unsigned)i;
Evan Chengef0732d2008-07-10 07:35:43 +00001000 return true;
Bob Wilsond9df5012009-04-09 17:16:43 +00001001 }
Evan Cheng32dfbea2007-10-12 08:50:34 +00001002 }
1003 return false;
1004}
1005
Evan Chenga24752f2009-03-19 20:30:06 +00001006/// isRegTiedToDefOperand - Return true if the operand of the specified index
1007/// is a register use and it is tied to an def operand. It also returns the def
1008/// operand index by reference.
Jakob Stoklund Olesence9be2c2009-04-29 20:57:16 +00001009bool MachineInstr::
1010isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
Chris Lattner518bb532010-02-09 19:54:29 +00001011 if (isInlineAsm()) {
Evan Chengfb112882009-03-23 08:01:15 +00001012 const MachineOperand &MO = getOperand(UseOpIdx);
Chris Lattner0c8382c2009-04-09 16:50:43 +00001013 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
Evan Chengfb112882009-03-23 08:01:15 +00001014 return false;
Jakob Stoklund Olesen57e599a2009-07-16 20:58:34 +00001015
1016 // Find the flag operand corresponding to UseOpIdx
1017 unsigned FlagIdx, NumOps=0;
Evan Chengc36b7062011-01-07 23:50:32 +00001018 for (FlagIdx = InlineAsm::MIOp_FirstOperand;
1019 FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
Jakob Stoklund Olesen57e599a2009-07-16 20:58:34 +00001020 const MachineOperand &UFMO = getOperand(FlagIdx);
Jakob Stoklund Olesen45d34fe2009-07-19 19:09:59 +00001021 // After the normal asm operands there may be additional imp-def regs.
1022 if (!UFMO.isImm())
1023 return false;
Jakob Stoklund Olesen57e599a2009-07-16 20:58:34 +00001024 NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
1025 assert(NumOps < getNumOperands() && "Invalid inline asm flag");
1026 if (UseOpIdx < FlagIdx+NumOps+1)
1027 break;
Evan Chengef5d0702009-06-24 02:05:51 +00001028 }
Jakob Stoklund Olesen57e599a2009-07-16 20:58:34 +00001029 if (FlagIdx >= UseOpIdx)
Evan Chengef5d0702009-06-24 02:05:51 +00001030 return false;
Jakob Stoklund Olesen57e599a2009-07-16 20:58:34 +00001031 const MachineOperand &UFMO = getOperand(FlagIdx);
Evan Chengfb112882009-03-23 08:01:15 +00001032 unsigned DefNo;
1033 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1034 if (!DefOpIdx)
1035 return true;
1036
Evan Chengc36b7062011-01-07 23:50:32 +00001037 unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
Dale Johannesenf1e309e2010-07-02 20:16:09 +00001038 // Remember to adjust the index. First operand is asm string, second is
Evan Chengc36b7062011-01-07 23:50:32 +00001039 // the HasSideEffects and AlignStack bits, then there is a flag for each.
Evan Chengfb112882009-03-23 08:01:15 +00001040 while (DefNo) {
1041 const MachineOperand &FMO = getOperand(DefIdx);
1042 assert(FMO.isImm());
1043 // Skip over this def.
1044 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1045 --DefNo;
1046 }
Evan Chengef5d0702009-06-24 02:05:51 +00001047 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
Evan Chengfb112882009-03-23 08:01:15 +00001048 return true;
1049 }
1050 return false;
1051 }
1052
Evan Chenga24752f2009-03-19 20:30:06 +00001053 const TargetInstrDesc &TID = getDesc();
1054 if (UseOpIdx >= TID.getNumOperands())
1055 return false;
1056 const MachineOperand &MO = getOperand(UseOpIdx);
1057 if (!MO.isReg() || !MO.isUse())
1058 return false;
1059 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
1060 if (DefIdx == -1)
1061 return false;
1062 if (DefOpIdx)
1063 *DefOpIdx = (unsigned)DefIdx;
1064 return true;
1065}
1066
Dan Gohmane6cd7572010-05-13 20:34:42 +00001067/// clearKillInfo - Clears kill flags on all operands.
1068///
1069void MachineInstr::clearKillInfo() {
1070 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1071 MachineOperand &MO = getOperand(i);
1072 if (MO.isReg() && MO.isUse())
1073 MO.setIsKill(false);
1074 }
1075}
1076
Evan Cheng576d1232006-12-06 08:27:42 +00001077/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1078///
1079void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1080 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1081 const MachineOperand &MO = MI->getOperand(i);
Dan Gohmand735b802008-10-03 15:45:36 +00001082 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
Evan Cheng576d1232006-12-06 08:27:42 +00001083 continue;
1084 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1085 MachineOperand &MOp = getOperand(j);
1086 if (!MOp.isIdenticalTo(MO))
1087 continue;
1088 if (MO.isKill())
1089 MOp.setIsKill();
1090 else
1091 MOp.setIsDead();
1092 break;
1093 }
1094 }
1095}
1096
Evan Cheng19e3f312007-05-15 01:26:09 +00001097/// copyPredicates - Copies predicate operand(s) from MI.
1098void MachineInstr::copyPredicates(const MachineInstr *MI) {
Chris Lattner749c6f62008-01-07 07:27:27 +00001099 const TargetInstrDesc &TID = MI->getDesc();
Evan Chengb27087f2008-03-13 00:44:09 +00001100 if (!TID.isPredicable())
1101 return;
1102 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1103 if (TID.OpInfo[i].isPredicate()) {
1104 // Predicated operands must be last operands.
1105 addOperand(MI->getOperand(i));
Evan Cheng19e3f312007-05-15 01:26:09 +00001106 }
1107 }
1108}
1109
Jakob Stoklund Olesen9edf7de2010-06-02 22:47:25 +00001110void MachineInstr::substituteRegister(unsigned FromReg,
1111 unsigned ToReg,
1112 unsigned SubIdx,
1113 const TargetRegisterInfo &RegInfo) {
1114 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1115 if (SubIdx)
1116 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1117 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1118 MachineOperand &MO = getOperand(i);
1119 if (!MO.isReg() || MO.getReg() != FromReg)
1120 continue;
1121 MO.substPhysReg(ToReg, RegInfo);
1122 }
1123 } else {
1124 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1125 MachineOperand &MO = getOperand(i);
1126 if (!MO.isReg() || MO.getReg() != FromReg)
1127 continue;
1128 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1129 }
1130 }
1131}
1132
Evan Cheng9f1c8312008-07-03 09:09:37 +00001133/// isSafeToMove - Return true if it is safe to move this instruction. If
1134/// SawStore is set to true, it means that there is a store (or call) between
1135/// the instruction's location and its intended destination.
Dan Gohmanb3b930a2008-11-18 19:04:29 +00001136bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
Evan Chengac1abde2010-03-02 19:03:01 +00001137 AliasAnalysis *AA,
1138 bool &SawStore) const {
Evan Chengb27087f2008-03-13 00:44:09 +00001139 // Ignore stuff that we obviously can't move.
1140 if (TID->mayStore() || TID->isCall()) {
1141 SawStore = true;
1142 return false;
1143 }
Evan Cheng30a343a2011-01-07 21:08:26 +00001144
1145 if (isLabel() || isDebugValue() ||
Evan Chengc36b7062011-01-07 23:50:32 +00001146 TID->isTerminator() || hasUnmodeledSideEffects())
Evan Chengb27087f2008-03-13 00:44:09 +00001147 return false;
1148
1149 // See if this instruction does a load. If so, we have to guarantee that the
1150 // loaded value doesn't change between the load and the its intended
1151 // destination. The check for isInvariantLoad gives the targe the chance to
1152 // classify the load as always returning a constant, e.g. a constant pool
1153 // load.
Dan Gohmana70dca12009-10-09 23:27:56 +00001154 if (TID->mayLoad() && !isInvariantLoad(AA))
Evan Chengb27087f2008-03-13 00:44:09 +00001155 // Otherwise, this is a real load. If there is a store between the load and
Evan Cheng7cc2c402009-07-28 21:49:18 +00001156 // end of block, or if the load is volatile, we can't move it.
Dan Gohmand790a5c2008-10-02 15:04:30 +00001157 return !SawStore && !hasVolatileMemoryRef();
Dan Gohman3e4fb702008-09-24 00:06:15 +00001158
Evan Chengb27087f2008-03-13 00:44:09 +00001159 return true;
1160}
1161
Evan Chengdf3b9932008-08-27 20:33:50 +00001162/// isSafeToReMat - Return true if it's safe to rematerialize the specified
1163/// instruction which defined the specified register instead of copying it.
Dan Gohmanb3b930a2008-11-18 19:04:29 +00001164bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
Evan Chengac1abde2010-03-02 19:03:01 +00001165 AliasAnalysis *AA,
1166 unsigned DstReg) const {
Evan Chengdf3b9932008-08-27 20:33:50 +00001167 bool SawStore = false;
Dan Gohmana70dca12009-10-09 23:27:56 +00001168 if (!TII->isTriviallyReMaterializable(this, AA) ||
Evan Chengac1abde2010-03-02 19:03:01 +00001169 !isSafeToMove(TII, AA, SawStore))
Evan Chengdf3b9932008-08-27 20:33:50 +00001170 return false;
1171 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
Dan Gohmancbad42c2008-11-18 19:49:32 +00001172 const MachineOperand &MO = getOperand(i);
Dan Gohmand735b802008-10-03 15:45:36 +00001173 if (!MO.isReg())
Evan Chengdf3b9932008-08-27 20:33:50 +00001174 continue;
1175 // FIXME: For now, do not remat any instruction with register operands.
1176 // Later on, we can loosen the restriction is the register operands have
1177 // not been modified between the def and use. Note, this is different from
Evan Cheng8763c1c2008-08-27 20:58:54 +00001178 // MachineSink because the code is no longer in two-address form (at least
Evan Chengdf3b9932008-08-27 20:33:50 +00001179 // partially).
1180 if (MO.isUse())
1181 return false;
1182 else if (!MO.isDead() && MO.getReg() != DstReg)
1183 return false;
1184 }
1185 return true;
1186}
1187
Dan Gohman3e4fb702008-09-24 00:06:15 +00001188/// hasVolatileMemoryRef - Return true if this instruction may have a
1189/// volatile memory reference, or if the information describing the
1190/// memory reference is not available. Return false if it is known to
1191/// have no volatile memory references.
1192bool MachineInstr::hasVolatileMemoryRef() const {
1193 // An instruction known never to access memory won't have a volatile access.
1194 if (!TID->mayStore() &&
1195 !TID->mayLoad() &&
1196 !TID->isCall() &&
Evan Chengc36b7062011-01-07 23:50:32 +00001197 !hasUnmodeledSideEffects())
Dan Gohman3e4fb702008-09-24 00:06:15 +00001198 return false;
1199
1200 // Otherwise, if the instruction has no memory reference information,
1201 // conservatively assume it wasn't preserved.
1202 if (memoperands_empty())
1203 return true;
1204
1205 // Check the memory reference information for volatile references.
Dan Gohmanc76909a2009-09-25 20:36:54 +00001206 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1207 if ((*I)->isVolatile())
Dan Gohman3e4fb702008-09-24 00:06:15 +00001208 return true;
1209
1210 return false;
1211}
1212
Dan Gohmane33f44c2009-10-07 17:38:06 +00001213/// isInvariantLoad - Return true if this instruction is loading from a
1214/// location whose value is invariant across the function. For example,
Dan Gohmanf451cb82010-02-10 16:03:48 +00001215/// loading a value from the constant pool or from the argument area
Dan Gohmane33f44c2009-10-07 17:38:06 +00001216/// of a function if it does not change. This should only return true of
1217/// *all* loads the instruction does are invariant (if it does multiple loads).
1218bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1219 // If the instruction doesn't load at all, it isn't an invariant load.
1220 if (!TID->mayLoad())
1221 return false;
1222
1223 // If the instruction has lost its memoperands, conservatively assume that
1224 // it may not be an invariant load.
1225 if (memoperands_empty())
1226 return false;
1227
1228 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1229
1230 for (mmo_iterator I = memoperands_begin(),
1231 E = memoperands_end(); I != E; ++I) {
1232 if ((*I)->isVolatile()) return false;
1233 if ((*I)->isStore()) return false;
1234
1235 if (const Value *V = (*I)->getValue()) {
1236 // A load from a constant PseudoSourceValue is invariant.
1237 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1238 if (PSV->isConstant(MFI))
1239 continue;
1240 // If we have an AliasAnalysis, ask it whether the memory is constant.
Dan Gohmanf96e4bd2010-10-20 00:31:05 +00001241 if (AA && AA->pointsToConstantMemory(
1242 AliasAnalysis::Location(V, (*I)->getSize(),
1243 (*I)->getTBAAInfo())))
Dan Gohmane33f44c2009-10-07 17:38:06 +00001244 continue;
1245 }
1246
1247 // Otherwise assume conservatively.
1248 return false;
1249 }
1250
1251 // Everything checks out.
1252 return true;
1253}
1254
Evan Cheng229694f2009-12-03 02:31:43 +00001255/// isConstantValuePHI - If the specified instruction is a PHI that always
1256/// merges together the same virtual register, return the register, otherwise
1257/// return 0.
1258unsigned MachineInstr::isConstantValuePHI() const {
Chris Lattner518bb532010-02-09 19:54:29 +00001259 if (!isPHI())
Evan Cheng229694f2009-12-03 02:31:43 +00001260 return 0;
Evan Chengd8f079c2009-12-07 23:10:34 +00001261 assert(getNumOperands() >= 3 &&
1262 "It's illegal to have a PHI without source operands");
Evan Cheng229694f2009-12-03 02:31:43 +00001263
1264 unsigned Reg = getOperand(1).getReg();
1265 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1266 if (getOperand(i).getReg() != Reg)
1267 return 0;
1268 return Reg;
1269}
1270
Evan Chengc36b7062011-01-07 23:50:32 +00001271bool MachineInstr::hasUnmodeledSideEffects() const {
1272 if (getDesc().hasUnmodeledSideEffects())
1273 return true;
1274 if (isInlineAsm()) {
1275 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1276 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1277 return true;
1278 }
1279
1280 return false;
1281}
1282
Evan Chenga57fabe2010-04-08 20:02:37 +00001283/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1284///
1285bool MachineInstr::allDefsAreDead() const {
1286 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1287 const MachineOperand &MO = getOperand(i);
1288 if (!MO.isReg() || MO.isUse())
1289 continue;
1290 if (!MO.isDead())
1291 return false;
1292 }
1293 return true;
1294}
1295
Evan Chengc8f46c42010-10-22 21:49:09 +00001296/// copyImplicitOps - Copy implicit register operands from specified
1297/// instruction to this instruction.
1298void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1299 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1300 i != e; ++i) {
1301 const MachineOperand &MO = MI->getOperand(i);
1302 if (MO.isReg() && MO.isImplicit())
1303 addOperand(MO);
1304 }
1305}
1306
Brian Gaeke21326fc2004-02-13 04:39:32 +00001307void MachineInstr::dump() const {
David Greene3b325332010-01-04 23:48:20 +00001308 dbgs() << " " << *this;
Mon P Wang5ca6bd12008-10-10 01:43:55 +00001309}
1310
Devang Patelda0e89f2010-06-29 21:51:32 +00001311static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1312 raw_ostream &CommentOS) {
1313 const LLVMContext &Ctx = MF->getFunction()->getContext();
1314 if (!DL.isUnknown()) { // Print source line info.
1315 DIScope Scope(DL.getScope(Ctx));
1316 // Omit the directory, because it's likely to be long and uninteresting.
1317 if (Scope.Verify())
1318 CommentOS << Scope.getFilename();
1319 else
1320 CommentOS << "<unknown>";
1321 CommentOS << ':' << DL.getLine();
1322 if (DL.getCol() != 0)
1323 CommentOS << ':' << DL.getCol();
1324 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1325 if (!InlinedAtDL.isUnknown()) {
1326 CommentOS << " @[ ";
1327 printDebugLoc(InlinedAtDL, MF, CommentOS);
1328 CommentOS << " ]";
1329 }
1330 }
1331}
1332
Mon P Wang5ca6bd12008-10-10 01:43:55 +00001333void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
Dan Gohman80f6c582009-11-09 19:38:45 +00001334 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1335 const MachineFunction *MF = 0;
Jakob Stoklund Olesena0c5bf12010-07-28 18:35:46 +00001336 const MachineRegisterInfo *MRI = 0;
Dan Gohman80f6c582009-11-09 19:38:45 +00001337 if (const MachineBasicBlock *MBB = getParent()) {
1338 MF = MBB->getParent();
1339 if (!TM && MF)
1340 TM = &MF->getTarget();
Jakob Stoklund Olesena0c5bf12010-07-28 18:35:46 +00001341 if (MF)
1342 MRI = &MF->getRegInfo();
Dan Gohman80f6c582009-11-09 19:38:45 +00001343 }
Dan Gohman0ba90f32009-10-31 20:19:03 +00001344
Jakob Stoklund Olesena0c5bf12010-07-28 18:35:46 +00001345 // Save a list of virtual registers.
1346 SmallVector<unsigned, 8> VirtRegs;
1347
Dan Gohman0ba90f32009-10-31 20:19:03 +00001348 // Print explicitly defined operands on the left of an assignment syntax.
Dan Gohman80f6c582009-11-09 19:38:45 +00001349 unsigned StartOp = 0, e = getNumOperands();
Dan Gohman0ba90f32009-10-31 20:19:03 +00001350 for (; StartOp < e && getOperand(StartOp).isReg() &&
1351 getOperand(StartOp).isDef() &&
1352 !getOperand(StartOp).isImplicit();
1353 ++StartOp) {
1354 if (StartOp != 0) OS << ", ";
1355 getOperand(StartOp).print(OS, TM);
Jakob Stoklund Olesena0c5bf12010-07-28 18:35:46 +00001356 unsigned Reg = getOperand(StartOp).getReg();
Jakob Stoklund Olesenc9df0252011-01-10 02:58:51 +00001357 if (TargetRegisterInfo::isVirtualRegister(Reg))
Jakob Stoklund Olesena0c5bf12010-07-28 18:35:46 +00001358 VirtRegs.push_back(Reg);
Chris Lattner6a592272002-10-30 01:55:38 +00001359 }
Tanya Lattnerb1407622004-06-25 00:13:11 +00001360
Dan Gohman0ba90f32009-10-31 20:19:03 +00001361 if (StartOp != 0)
1362 OS << " = ";
1363
1364 // Print the opcode name.
Chris Lattner749c6f62008-01-07 07:27:27 +00001365 OS << getDesc().getName();
Misha Brukmanedf128a2005-04-21 22:36:52 +00001366
Dan Gohman0ba90f32009-10-31 20:19:03 +00001367 // Print the rest of the operands.
Dan Gohman80f6c582009-11-09 19:38:45 +00001368 bool OmittedAnyCallClobbers = false;
1369 bool FirstOp = true;
Jakob Stoklund Olesen7a2ecd32011-06-27 04:08:29 +00001370 unsigned AsmDescOp = ~0u;
1371 unsigned AsmOpCount = 0;
Evan Chengc36b7062011-01-07 23:50:32 +00001372
1373 if (isInlineAsm()) {
1374 // Print asm string.
1375 OS << " ";
1376 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1377
1378 // Print HasSideEffects, IsAlignStack
1379 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1380 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1381 OS << " [sideeffect]";
1382 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1383 OS << " [alignstack]";
1384
Jakob Stoklund Olesen7a2ecd32011-06-27 04:08:29 +00001385 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
Evan Chengc36b7062011-01-07 23:50:32 +00001386 FirstOp = false;
1387 }
1388
1389
Chris Lattner6a592272002-10-30 01:55:38 +00001390 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
Dan Gohman80f6c582009-11-09 19:38:45 +00001391 const MachineOperand &MO = getOperand(i);
1392
Jakob Stoklund Olesenc9df0252011-01-10 02:58:51 +00001393 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
Jakob Stoklund Olesena0c5bf12010-07-28 18:35:46 +00001394 VirtRegs.push_back(MO.getReg());
1395
Dan Gohman80f6c582009-11-09 19:38:45 +00001396 // Omit call-clobbered registers which aren't used anywhere. This makes
1397 // call instructions much less noisy on targets where calls clobber lots
1398 // of registers. Don't rely on MO.isDead() because we may be called before
1399 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1400 if (MF && getDesc().isCall() &&
1401 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1402 unsigned Reg = MO.getReg();
Jakob Stoklund Olesenc9df0252011-01-10 02:58:51 +00001403 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
Dan Gohman80f6c582009-11-09 19:38:45 +00001404 const MachineRegisterInfo &MRI = MF->getRegInfo();
1405 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1406 bool HasAliasLive = false;
1407 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1408 unsigned AliasReg = *Alias; ++Alias)
1409 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1410 HasAliasLive = true;
1411 break;
1412 }
1413 if (!HasAliasLive) {
1414 OmittedAnyCallClobbers = true;
1415 continue;
1416 }
1417 }
1418 }
1419 }
1420
1421 if (FirstOp) FirstOp = false; else OS << ",";
Chris Lattner6a592272002-10-30 01:55:38 +00001422 OS << " ";
Jakob Stoklund Olesenb1bb4af2010-01-19 22:08:34 +00001423 if (i < getDesc().NumOperands) {
1424 const TargetOperandInfo &TOI = getDesc().OpInfo[i];
1425 if (TOI.isPredicate())
1426 OS << "pred:";
1427 if (TOI.isOptionalDef())
1428 OS << "opt:";
1429 }
Evan Cheng59b36552010-04-28 20:03:13 +00001430 if (isDebugValue() && MO.isMetadata()) {
1431 // Pretty print DBG_VALUE instructions.
1432 const MDNode *MD = MO.getMetadata();
1433 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1434 OS << "!\"" << MDS->getString() << '\"';
1435 else
1436 MO.print(OS, TM);
Jakob Stoklund Olesenb1e11452010-07-04 23:24:23 +00001437 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1438 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
Jakob Stoklund Olesen7a2ecd32011-06-27 04:08:29 +00001439 } else if (i == AsmDescOp && MO.isImm()) {
1440 // Pretty print the inline asm operand descriptor.
1441 OS << '$' << AsmOpCount++;
1442 unsigned Flag = MO.getImm();
1443 switch (InlineAsm::getKind(Flag)) {
1444 case InlineAsm::Kind_RegUse: OS << ":[reguse]"; break;
1445 case InlineAsm::Kind_RegDef: OS << ":[regdef]"; break;
1446 case InlineAsm::Kind_Imm: OS << ":[imm]"; break;
1447 case InlineAsm::Kind_Mem: OS << ":[mem]"; break;
1448 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec]"; break;
1449 default: OS << ":[??" << InlineAsm::getKind(Flag) << ']'; break;
1450 }
1451
1452 unsigned TiedTo = 0;
1453 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1454 OS << " [tiedto:$" << TiedTo << ']';
1455
1456 // Compute the index of the next operand descriptor.
1457 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
Evan Cheng59b36552010-04-28 20:03:13 +00001458 } else
1459 MO.print(OS, TM);
Dan Gohman80f6c582009-11-09 19:38:45 +00001460 }
1461
1462 // Briefly indicate whether any call clobbers were omitted.
1463 if (OmittedAnyCallClobbers) {
Bill Wendling164558e2009-12-25 13:45:50 +00001464 if (!FirstOp) OS << ",";
Dan Gohman80f6c582009-11-09 19:38:45 +00001465 OS << " ...";
Chris Lattner10491642002-10-30 00:48:05 +00001466 }
Misha Brukmanedf128a2005-04-21 22:36:52 +00001467
Dan Gohman0ba90f32009-10-31 20:19:03 +00001468 bool HaveSemi = false;
Anton Korobeynikov6dd97472011-03-05 18:43:04 +00001469 if (Flags) {
1470 if (!HaveSemi) OS << ";"; HaveSemi = true;
1471 OS << " flags: ";
1472
1473 if (Flags & FrameSetup)
1474 OS << "FrameSetup";
1475 }
1476
Dan Gohman8e5f2c62008-07-07 23:14:23 +00001477 if (!memoperands_empty()) {
Dan Gohman0ba90f32009-10-31 20:19:03 +00001478 if (!HaveSemi) OS << ";"; HaveSemi = true;
1479
1480 OS << " mem:";
Dan Gohmanc76909a2009-09-25 20:36:54 +00001481 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1482 i != e; ++i) {
1483 OS << **i;
Oscar Fuentesee56c422010-08-02 06:00:15 +00001484 if (llvm::next(i) != e)
Dan Gohmancd26ec52009-09-23 01:33:16 +00001485 OS << " ";
Dan Gohman69de1932008-02-06 22:27:42 +00001486 }
1487 }
1488
Jakob Stoklund Olesena0c5bf12010-07-28 18:35:46 +00001489 // Print the regclass of any virtual registers encountered.
1490 if (MRI && !VirtRegs.empty()) {
1491 if (!HaveSemi) OS << ";"; HaveSemi = true;
1492 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1493 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
Jakob Stoklund Olesen43142682011-01-09 03:05:53 +00001494 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
Jakob Stoklund Olesena0c5bf12010-07-28 18:35:46 +00001495 for (unsigned j = i+1; j != VirtRegs.size();) {
1496 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1497 ++j;
1498 continue;
1499 }
1500 if (VirtRegs[i] != VirtRegs[j])
Jakob Stoklund Olesen43142682011-01-09 03:05:53 +00001501 OS << "," << PrintReg(VirtRegs[j]);
Jakob Stoklund Olesena0c5bf12010-07-28 18:35:46 +00001502 VirtRegs.erase(VirtRegs.begin()+j);
1503 }
1504 }
1505 }
1506
Anton Korobeynikov6dd97472011-03-05 18:43:04 +00001507 // Print debug location information.
Dan Gohman80f6c582009-11-09 19:38:45 +00001508 if (!debugLoc.isUnknown() && MF) {
Anton Korobeynikov6dd97472011-03-05 18:43:04 +00001509 if (!HaveSemi) OS << ";"; HaveSemi = true;
Dan Gohman75ae5932009-11-23 21:29:08 +00001510 OS << " dbg:";
Devang Patelda0e89f2010-06-29 21:51:32 +00001511 printDebugLoc(debugLoc, MF, OS);
Bill Wendlingb5ef2732009-02-19 21:44:55 +00001512 }
1513
Anton Korobeynikov6dd97472011-03-05 18:43:04 +00001514 OS << '\n';
Chris Lattner10491642002-10-30 00:48:05 +00001515}
1516
Owen Andersonb487e722008-01-24 01:10:07 +00001517bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
Dan Gohman6f0d0242008-02-10 18:45:23 +00001518 const TargetRegisterInfo *RegInfo,
Owen Andersonb487e722008-01-24 01:10:07 +00001519 bool AddIfNotFound) {
Evan Cheng9b6d7b92008-04-16 09:41:59 +00001520 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
Dan Gohman2ebc11a2008-07-03 01:18:51 +00001521 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
Dan Gohman3f629402008-09-03 15:56:16 +00001522 bool Found = false;
Evan Cheng9b6d7b92008-04-16 09:41:59 +00001523 SmallVector<unsigned,4> DeadOps;
Bill Wendling4a23d722008-03-03 22:14:33 +00001524 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1525 MachineOperand &MO = getOperand(i);
Jakob Stoklund Olesenefb8e3e2009-08-04 20:09:25 +00001526 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
Evan Cheng9b6d7b92008-04-16 09:41:59 +00001527 continue;
1528 unsigned Reg = MO.getReg();
1529 if (!Reg)
1530 continue;
Bill Wendling4a23d722008-03-03 22:14:33 +00001531
Evan Cheng9b6d7b92008-04-16 09:41:59 +00001532 if (Reg == IncomingReg) {
Dan Gohman3f629402008-09-03 15:56:16 +00001533 if (!Found) {
1534 if (MO.isKill())
1535 // The register is already marked kill.
1536 return true;
Jakob Stoklund Olesenece48182009-08-02 19:13:03 +00001537 if (isPhysReg && isRegTiedToDefOperand(i))
1538 // Two-address uses of physregs must not be marked kill.
1539 return true;
Dan Gohman3f629402008-09-03 15:56:16 +00001540 MO.setIsKill();
1541 Found = true;
1542 }
1543 } else if (hasAliases && MO.isKill() &&
1544 TargetRegisterInfo::isPhysicalRegister(Reg)) {
Evan Cheng9b6d7b92008-04-16 09:41:59 +00001545 // A super-register kill already exists.
1546 if (RegInfo->isSuperRegister(IncomingReg, Reg))
Dan Gohman2ebc11a2008-07-03 01:18:51 +00001547 return true;
1548 if (RegInfo->isSubRegister(IncomingReg, Reg))
Evan Cheng9b6d7b92008-04-16 09:41:59 +00001549 DeadOps.push_back(i);
Bill Wendling4a23d722008-03-03 22:14:33 +00001550 }
1551 }
1552
Evan Cheng9b6d7b92008-04-16 09:41:59 +00001553 // Trim unneeded kill operands.
1554 while (!DeadOps.empty()) {
1555 unsigned OpIdx = DeadOps.back();
1556 if (getOperand(OpIdx).isImplicit())
1557 RemoveOperand(OpIdx);
1558 else
1559 getOperand(OpIdx).setIsKill(false);
1560 DeadOps.pop_back();
1561 }
1562
Bill Wendling4a23d722008-03-03 22:14:33 +00001563 // If not found, this means an alias of one of the operands is killed. Add a
Owen Andersonb487e722008-01-24 01:10:07 +00001564 // new implicit operand if required.
Dan Gohman3f629402008-09-03 15:56:16 +00001565 if (!Found && AddIfNotFound) {
Bill Wendling4a23d722008-03-03 22:14:33 +00001566 addOperand(MachineOperand::CreateReg(IncomingReg,
1567 false /*IsDef*/,
1568 true /*IsImp*/,
1569 true /*IsKill*/));
Owen Andersonb487e722008-01-24 01:10:07 +00001570 return true;
1571 }
Dan Gohman3f629402008-09-03 15:56:16 +00001572 return Found;
Owen Andersonb487e722008-01-24 01:10:07 +00001573}
1574
1575bool MachineInstr::addRegisterDead(unsigned IncomingReg,
Dan Gohman6f0d0242008-02-10 18:45:23 +00001576 const TargetRegisterInfo *RegInfo,
Owen Andersonb487e722008-01-24 01:10:07 +00001577 bool AddIfNotFound) {
Evan Cheng9b6d7b92008-04-16 09:41:59 +00001578 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
Evan Cheng01b2e232008-06-27 22:11:49 +00001579 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
Dan Gohman3f629402008-09-03 15:56:16 +00001580 bool Found = false;
Evan Cheng9b6d7b92008-04-16 09:41:59 +00001581 SmallVector<unsigned,4> DeadOps;
Owen Andersonb487e722008-01-24 01:10:07 +00001582 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1583 MachineOperand &MO = getOperand(i);
Dan Gohmand735b802008-10-03 15:45:36 +00001584 if (!MO.isReg() || !MO.isDef())
Evan Cheng9b6d7b92008-04-16 09:41:59 +00001585 continue;
1586 unsigned Reg = MO.getReg();
Dan Gohman3f629402008-09-03 15:56:16 +00001587 if (!Reg)
1588 continue;
1589
Evan Cheng9b6d7b92008-04-16 09:41:59 +00001590 if (Reg == IncomingReg) {
Jakob Stoklund Olesenb793bc12011-04-05 16:53:50 +00001591 MO.setIsDead();
1592 Found = true;
Dan Gohman3f629402008-09-03 15:56:16 +00001593 } else if (hasAliases && MO.isDead() &&
1594 TargetRegisterInfo::isPhysicalRegister(Reg)) {
Evan Cheng9b6d7b92008-04-16 09:41:59 +00001595 // There exists a super-register that's marked dead.
1596 if (RegInfo->isSuperRegister(IncomingReg, Reg))
Dan Gohman2ebc11a2008-07-03 01:18:51 +00001597 return true;
Owen Anderson22ae9992008-08-14 18:34:18 +00001598 if (RegInfo->getSubRegisters(IncomingReg) &&
1599 RegInfo->getSuperRegisters(Reg) &&
1600 RegInfo->isSubRegister(IncomingReg, Reg))
Evan Cheng9b6d7b92008-04-16 09:41:59 +00001601 DeadOps.push_back(i);
Owen Andersonb487e722008-01-24 01:10:07 +00001602 }
1603 }
1604
Evan Cheng9b6d7b92008-04-16 09:41:59 +00001605 // Trim unneeded dead operands.
1606 while (!DeadOps.empty()) {
1607 unsigned OpIdx = DeadOps.back();
1608 if (getOperand(OpIdx).isImplicit())
1609 RemoveOperand(OpIdx);
1610 else
1611 getOperand(OpIdx).setIsDead(false);
1612 DeadOps.pop_back();
1613 }
1614
Dan Gohman3f629402008-09-03 15:56:16 +00001615 // If not found, this means an alias of one of the operands is dead. Add a
1616 // new implicit operand if required.
Chris Lattner31530612009-06-24 17:54:48 +00001617 if (Found || !AddIfNotFound)
1618 return Found;
1619
1620 addOperand(MachineOperand::CreateReg(IncomingReg,
1621 true /*IsDef*/,
1622 true /*IsImp*/,
1623 false /*IsKill*/,
1624 true /*IsDead*/));
1625 return true;
Owen Andersonb487e722008-01-24 01:10:07 +00001626}
Jakob Stoklund Olesen8efadf92010-01-06 00:29:28 +00001627
1628void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1629 const TargetRegisterInfo *RegInfo) {
Jakob Stoklund Olesen63e6a482010-05-21 16:32:16 +00001630 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1631 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1632 if (MO)
1633 return;
1634 } else {
1635 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1636 const MachineOperand &MO = getOperand(i);
1637 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1638 MO.getSubReg() == 0)
1639 return;
1640 }
1641 }
1642 addOperand(MachineOperand::CreateReg(IncomingReg,
1643 true /*IsDef*/,
1644 true /*IsImp*/));
Jakob Stoklund Olesen8efadf92010-01-06 00:29:28 +00001645}
Evan Cheng67eaa082010-03-03 23:37:30 +00001646
Dan Gohmandb497122010-06-18 23:28:01 +00001647void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
1648 const TargetRegisterInfo &TRI) {
1649 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1650 MachineOperand &MO = getOperand(i);
1651 if (!MO.isReg() || !MO.isDef()) continue;
1652 unsigned Reg = MO.getReg();
1653 if (Reg == 0) continue;
1654 bool Dead = true;
1655 for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(),
1656 E = UsedRegs.end(); I != E; ++I)
1657 if (TRI.regsOverlap(*I, Reg)) {
1658 Dead = false;
1659 break;
1660 }
1661 // If there are no uses, including partial uses, the def is dead.
1662 if (Dead) MO.setIsDead();
1663 }
1664}
1665
Evan Cheng67eaa082010-03-03 23:37:30 +00001666unsigned
1667MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1668 unsigned Hash = MI->getOpcode() * 37;
1669 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1670 const MachineOperand &MO = MI->getOperand(i);
1671 uint64_t Key = (uint64_t)MO.getType() << 32;
1672 switch (MO.getType()) {
Chris Lattner72aaa3c2010-03-13 08:14:18 +00001673 default: break;
1674 case MachineOperand::MO_Register:
Jakob Stoklund Olesenc9df0252011-01-10 02:58:51 +00001675 if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
Chris Lattner72aaa3c2010-03-13 08:14:18 +00001676 continue; // Skip virtual register defs.
1677 Key |= MO.getReg();
1678 break;
1679 case MachineOperand::MO_Immediate:
1680 Key |= MO.getImm();
1681 break;
1682 case MachineOperand::MO_FrameIndex:
1683 case MachineOperand::MO_ConstantPoolIndex:
1684 case MachineOperand::MO_JumpTableIndex:
1685 Key |= MO.getIndex();
1686 break;
1687 case MachineOperand::MO_MachineBasicBlock:
1688 Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1689 break;
1690 case MachineOperand::MO_GlobalAddress:
1691 Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1692 break;
1693 case MachineOperand::MO_BlockAddress:
1694 Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1695 break;
1696 case MachineOperand::MO_MCSymbol:
1697 Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1698 break;
Evan Cheng67eaa082010-03-03 23:37:30 +00001699 }
1700 Key += ~(Key << 32);
1701 Key ^= (Key >> 22);
1702 Key += ~(Key << 13);
1703 Key ^= (Key >> 8);
1704 Key += (Key << 3);
1705 Key ^= (Key >> 15);
1706 Key += ~(Key << 27);
1707 Key ^= (Key >> 31);
1708 Hash = (unsigned)Key + Hash * 37;
1709 }
1710 return Hash;
1711}