blob: d148bbe41f2f3203b875971098f7869177fb030f [file] [log] [blame]
Bob Wilson5dde8932011-04-19 18:11:49 +00001; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s
2; Avoid some 's' 16-bit instruction which partially update CPSR (and add false
3; dependency) when it isn't dependent on last CPSR defining instruction.
4; rdar://8928208
5
6define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
7 entry:
8; CHECK: t:
Jim Grosbach7a32fa12011-08-19 22:19:48 +00009; CHECK: muls r2, r2, r3
Bob Wilson5dde8932011-04-19 18:11:49 +000010; CHECK-NEXT: mul r0, r0, r1
Jim Grosbach7a32fa12011-08-19 22:19:48 +000011; CHECK-NEXT: muls r0, r0, r2
Bob Wilson5dde8932011-04-19 18:11:49 +000012 %0 = mul nsw i32 %a, %b
13 %1 = mul nsw i32 %c, %d
14 %2 = mul nsw i32 %0, %1
15 ret i32 %2
16}