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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 7ab15f6d4b9b9fd03c8ab6327ac2b1b3c4b4d04b / . / lib / CodeGen / SelectionDAG / TargetLowering.cpp
blob: 819e64084f2a68c4c4dfcbf60e6feb837d69298b [file] [log] [blame]
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]2//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]7//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
Chris Lattneraf76e592009-08-22 20:48:53 +0000[diff] [blame]15#include "llvm/MC/MCAsmInfo.h"
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]16#include "llvm/MC/MCExpr.h"
Owen Anderson07000c62006-05-12 06:33:49 +0000[diff] [blame]17#include "llvm/Target/TargetData.h"
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]18#include "llvm/Target/TargetLoweringObjectFile.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]19#include "llvm/Target/TargetMachine.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]20#include "llvm/Target/TargetRegisterInfo.h"
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]21#include "llvm/GlobalVariable.h"
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]22#include "llvm/DerivedTypes.h"
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]23#include "llvm/CodeGen/Analysis.h"
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]25#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]26#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]27#include "llvm/CodeGen/SelectionDAG.h"
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]28#include "llvm/ADT/STLExtras.h"
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]29#include "llvm/Support/CommandLine.h"
Torok Edwinc25e7582009-07-11 20:10:48 +0000[diff] [blame]30#include "llvm/Support/ErrorHandling.h"
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]31#include "llvm/Support/MathExtras.h"
Nick Lewycky476b2422010-12-19 20:43:38 +0000[diff] [blame]32#include <cctype>
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]33using namespace llvm;
34
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]35/// We are in the process of implementing a new TypeLegalization action
36/// - the promotion of vector elements. This feature is disabled by default
37/// and only enabled using this flag.
38static cl::opt<bool>
39AllowPromoteIntElem("promote-elements", cl::Hidden,
40 cl::desc("Allow promotion of integer vector element types"));
41
Rafael Espindola9a580232009-02-27 13:37:18 +0000[diff] [blame]42namespace llvm {
43TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
44 bool isLocal = GV->hasLocalLinkage();
45 bool isDeclaration = GV->isDeclaration();
46 // FIXME: what should we do for protected and internal visibility?
47 // For variables, is internal different from hidden?
48 bool isHidden = GV->hasHiddenVisibility();
49
50 if (reloc == Reloc::PIC_) {
51 if (isLocal || isHidden)
52 return TLSModel::LocalDynamic;
53 else
54 return TLSModel::GeneralDynamic;
55 } else {
56 if (!isDeclaration || isHidden)
57 return TLSModel::LocalExec;
58 else
59 return TLSModel::InitialExec;
60 }
61}
62}
63
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]64/// InitLibcallNames - Set default libcall names.
65///
Evan Cheng79cca502007-01-12 22:51:10 +0000[diff] [blame]66static void InitLibcallNames(const char **Names) {
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]67 Names[RTLIB::SHL_I16] = "__ashlhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]68 Names[RTLIB::SHL_I32] = "__ashlsi3";
69 Names[RTLIB::SHL_I64] = "__ashldi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]70 Names[RTLIB::SHL_I128] = "__ashlti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]71 Names[RTLIB::SRL_I16] = "__lshrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]72 Names[RTLIB::SRL_I32] = "__lshrsi3";
73 Names[RTLIB::SRL_I64] = "__lshrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]74 Names[RTLIB::SRL_I128] = "__lshrti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]75 Names[RTLIB::SRA_I16] = "__ashrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]76 Names[RTLIB::SRA_I32] = "__ashrsi3";
77 Names[RTLIB::SRA_I64] = "__ashrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]78 Names[RTLIB::SRA_I128] = "__ashrti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]79 Names[RTLIB::MUL_I8] = "__mulqi3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]80 Names[RTLIB::MUL_I16] = "__mulhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]81 Names[RTLIB::MUL_I32] = "__mulsi3";
82 Names[RTLIB::MUL_I64] = "__muldi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]83 Names[RTLIB::MUL_I128] = "__multi3";
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]84 Names[RTLIB::MULO_I32] = "__mulosi4";
85 Names[RTLIB::MULO_I64] = "__mulodi4";
86 Names[RTLIB::MULO_I128] = "__muloti4";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]87 Names[RTLIB::SDIV_I8] = "__divqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]88 Names[RTLIB::SDIV_I16] = "__divhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]89 Names[RTLIB::SDIV_I32] = "__divsi3";
90 Names[RTLIB::SDIV_I64] = "__divdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]91 Names[RTLIB::SDIV_I128] = "__divti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]92 Names[RTLIB::UDIV_I8] = "__udivqi3";
Anton Korobeynikovfb3f84f2009-05-08 18:50:54 +0000[diff] [blame]93 Names[RTLIB::UDIV_I16] = "__udivhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]94 Names[RTLIB::UDIV_I32] = "__udivsi3";
95 Names[RTLIB::UDIV_I64] = "__udivdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]96 Names[RTLIB::UDIV_I128] = "__udivti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]97 Names[RTLIB::SREM_I8] = "__modqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]98 Names[RTLIB::SREM_I16] = "__modhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]99 Names[RTLIB::SREM_I32] = "__modsi3";
100 Names[RTLIB::SREM_I64] = "__moddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]101 Names[RTLIB::SREM_I128] = "__modti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]102 Names[RTLIB::UREM_I8] = "__umodqi3";
Anton Korobeynikov9fe9c8e2009-05-03 13:19:57 +0000[diff] [blame]103 Names[RTLIB::UREM_I16] = "__umodhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]104 Names[RTLIB::UREM_I32] = "__umodsi3";
105 Names[RTLIB::UREM_I64] = "__umoddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]106 Names[RTLIB::UREM_I128] = "__umodti3";
Evan Cheng8e23e812011-04-01 00:42:02 +0000[diff] [blame]107
108 // These are generally not available.
109 Names[RTLIB::SDIVREM_I8] = 0;
110 Names[RTLIB::SDIVREM_I16] = 0;
111 Names[RTLIB::SDIVREM_I32] = 0;
112 Names[RTLIB::SDIVREM_I64] = 0;
113 Names[RTLIB::SDIVREM_I128] = 0;
114 Names[RTLIB::UDIVREM_I8] = 0;
115 Names[RTLIB::UDIVREM_I16] = 0;
116 Names[RTLIB::UDIVREM_I32] = 0;
117 Names[RTLIB::UDIVREM_I64] = 0;
118 Names[RTLIB::UDIVREM_I128] = 0;
119
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]120 Names[RTLIB::NEG_I32] = "__negsi2";
121 Names[RTLIB::NEG_I64] = "__negdi2";
122 Names[RTLIB::ADD_F32] = "__addsf3";
123 Names[RTLIB::ADD_F64] = "__adddf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]124 Names[RTLIB::ADD_F80] = "__addxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]125 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]126 Names[RTLIB::SUB_F32] = "__subsf3";
127 Names[RTLIB::SUB_F64] = "__subdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]128 Names[RTLIB::SUB_F80] = "__subxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]129 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]130 Names[RTLIB::MUL_F32] = "__mulsf3";
131 Names[RTLIB::MUL_F64] = "__muldf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]132 Names[RTLIB::MUL_F80] = "__mulxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]133 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]134 Names[RTLIB::DIV_F32] = "__divsf3";
135 Names[RTLIB::DIV_F64] = "__divdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]136 Names[RTLIB::DIV_F80] = "__divxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]137 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]138 Names[RTLIB::REM_F32] = "fmodf";
139 Names[RTLIB::REM_F64] = "fmod";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]140 Names[RTLIB::REM_F80] = "fmodl";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]141 Names[RTLIB::REM_PPCF128] = "fmodl";
Cameron Zwarich33390842011-07-08 21:39:21 +0000[diff] [blame]142 Names[RTLIB::FMA_F32] = "fmaf";
143 Names[RTLIB::FMA_F64] = "fma";
144 Names[RTLIB::FMA_F80] = "fmal";
145 Names[RTLIB::FMA_PPCF128] = "fmal";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]146 Names[RTLIB::POWI_F32] = "__powisf2";
147 Names[RTLIB::POWI_F64] = "__powidf2";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]148 Names[RTLIB::POWI_F80] = "__powixf2";
149 Names[RTLIB::POWI_PPCF128] = "__powitf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]150 Names[RTLIB::SQRT_F32] = "sqrtf";
151 Names[RTLIB::SQRT_F64] = "sqrt";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]152 Names[RTLIB::SQRT_F80] = "sqrtl";
153 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000[diff] [blame]154 Names[RTLIB::LOG_F32] = "logf";
155 Names[RTLIB::LOG_F64] = "log";
156 Names[RTLIB::LOG_F80] = "logl";
157 Names[RTLIB::LOG_PPCF128] = "logl";
158 Names[RTLIB::LOG2_F32] = "log2f";
159 Names[RTLIB::LOG2_F64] = "log2";
160 Names[RTLIB::LOG2_F80] = "log2l";
161 Names[RTLIB::LOG2_PPCF128] = "log2l";
162 Names[RTLIB::LOG10_F32] = "log10f";
163 Names[RTLIB::LOG10_F64] = "log10";
164 Names[RTLIB::LOG10_F80] = "log10l";
165 Names[RTLIB::LOG10_PPCF128] = "log10l";
166 Names[RTLIB::EXP_F32] = "expf";
167 Names[RTLIB::EXP_F64] = "exp";
168 Names[RTLIB::EXP_F80] = "expl";
169 Names[RTLIB::EXP_PPCF128] = "expl";
170 Names[RTLIB::EXP2_F32] = "exp2f";
171 Names[RTLIB::EXP2_F64] = "exp2";
172 Names[RTLIB::EXP2_F80] = "exp2l";
173 Names[RTLIB::EXP2_PPCF128] = "exp2l";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]174 Names[RTLIB::SIN_F32] = "sinf";
175 Names[RTLIB::SIN_F64] = "sin";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]176 Names[RTLIB::SIN_F80] = "sinl";
177 Names[RTLIB::SIN_PPCF128] = "sinl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]178 Names[RTLIB::COS_F32] = "cosf";
179 Names[RTLIB::COS_F64] = "cos";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]180 Names[RTLIB::COS_F80] = "cosl";
181 Names[RTLIB::COS_PPCF128] = "cosl";
Dan Gohmane54be102007-10-11 23:09:10 +0000[diff] [blame]182 Names[RTLIB::POW_F32] = "powf";
183 Names[RTLIB::POW_F64] = "pow";
184 Names[RTLIB::POW_F80] = "powl";
185 Names[RTLIB::POW_PPCF128] = "powl";
Dan Gohman2bb1e3e2008-08-21 18:38:14 +0000[diff] [blame]186 Names[RTLIB::CEIL_F32] = "ceilf";
187 Names[RTLIB::CEIL_F64] = "ceil";
188 Names[RTLIB::CEIL_F80] = "ceill";
189 Names[RTLIB::CEIL_PPCF128] = "ceill";
190 Names[RTLIB::TRUNC_F32] = "truncf";
191 Names[RTLIB::TRUNC_F64] = "trunc";
192 Names[RTLIB::TRUNC_F80] = "truncl";
193 Names[RTLIB::TRUNC_PPCF128] = "truncl";
194 Names[RTLIB::RINT_F32] = "rintf";
195 Names[RTLIB::RINT_F64] = "rint";
196 Names[RTLIB::RINT_F80] = "rintl";
197 Names[RTLIB::RINT_PPCF128] = "rintl";
198 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
199 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
200 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
201 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
202 Names[RTLIB::FLOOR_F32] = "floorf";
203 Names[RTLIB::FLOOR_F64] = "floor";
204 Names[RTLIB::FLOOR_F80] = "floorl";
205 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Duncan Sandsd2c817e2010-03-14 21:08:40 +0000[diff] [blame]206 Names[RTLIB::COPYSIGN_F32] = "copysignf";
207 Names[RTLIB::COPYSIGN_F64] = "copysign";
208 Names[RTLIB::COPYSIGN_F80] = "copysignl";
209 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]210 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]211 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
212 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]213 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]214 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
215 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
216 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
217 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]218 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
219 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]220 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
221 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]222 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]223 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
224 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]225 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
226 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]227 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
Duncan Sandsbe1ad4d2008-07-10 15:33:02 +0000[diff] [blame]228 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]229 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]230 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]231 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]232 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]233 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]234 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
235 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]236 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
237 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]238 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]239 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
240 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]241 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
242 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]243 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]244 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
245 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]246 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]247 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]248 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]249 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]250 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
251 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
Duncan Sands9bed0f52008-07-11 16:57:02 +0000[diff] [blame]252 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
253 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]254 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
255 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]256 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
257 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
Dan Gohmand91446d2008-03-05 01:08:17 +0000[diff] [blame]258 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
259 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
260 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
261 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]262 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
263 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]264 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
265 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]266 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
267 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]268 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
269 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
270 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
271 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
272 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
273 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]274 Names[RTLIB::OEQ_F32] = "__eqsf2";
275 Names[RTLIB::OEQ_F64] = "__eqdf2";
276 Names[RTLIB::UNE_F32] = "__nesf2";
277 Names[RTLIB::UNE_F64] = "__nedf2";
278 Names[RTLIB::OGE_F32] = "__gesf2";
279 Names[RTLIB::OGE_F64] = "__gedf2";
280 Names[RTLIB::OLT_F32] = "__ltsf2";
281 Names[RTLIB::OLT_F64] = "__ltdf2";
282 Names[RTLIB::OLE_F32] = "__lesf2";
283 Names[RTLIB::OLE_F64] = "__ledf2";
284 Names[RTLIB::OGT_F32] = "__gtsf2";
285 Names[RTLIB::OGT_F64] = "__gtdf2";
286 Names[RTLIB::UO_F32] = "__unordsf2";
287 Names[RTLIB::UO_F64] = "__unorddf2";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]288 Names[RTLIB::O_F32] = "__unordsf2";
289 Names[RTLIB::O_F64] = "__unorddf2";
Sanjiv Guptaa114baa2009-07-30 09:12:56 +0000[diff] [blame]290 Names[RTLIB::MEMCPY] = "memcpy";
291 Names[RTLIB::MEMMOVE] = "memmove";
292 Names[RTLIB::MEMSET] = "memset";
Duncan Sandsb0f1e172009-05-22 20:36:31 +0000[diff] [blame]293 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]294 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
295 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
296 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
297 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
Jim Grosbachef6eb9c2010-06-18 23:03:10 +0000[diff] [blame]298 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
299 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
300 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
301 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]302 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
303 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
304 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
305 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
306 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
307 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
308 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
309 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
310 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
311 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
312 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
313 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
314 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
315 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
316 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
317 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
318 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
319 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
320 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4";
321 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
322 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
323 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
324 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
325 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]326}
327
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]328/// InitLibcallCallingConvs - Set default libcall CallingConvs.
329///
330static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
331 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
332 CCs[i] = CallingConv::C;
333 }
334}
335
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]336/// getFPEXT - Return the FPEXT_*_* value for the given types, or
337/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]338RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]339 if (OpVT == MVT::f32) {
340 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]341 return FPEXT_F32_F64;
342 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]343
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]344 return UNKNOWN_LIBCALL;
345}
346
347/// getFPROUND - Return the FPROUND_*_* value for the given types, or
348/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]349RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]350 if (RetVT == MVT::f32) {
351 if (OpVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]352 return FPROUND_F64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]353 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]354 return FPROUND_F80_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]355 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]356 return FPROUND_PPCF128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]357 } else if (RetVT == MVT::f64) {
358 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]359 return FPROUND_F80_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]360 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]361 return FPROUND_PPCF128_F64;
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]362 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]363
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]364 return UNKNOWN_LIBCALL;
365}
366
367/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
368/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]369RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]370 if (OpVT == MVT::f32) {
371 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]372 return FPTOSINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]373 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]374 return FPTOSINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]375 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]376 return FPTOSINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]377 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]378 return FPTOSINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]379 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]380 return FPTOSINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]381 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]382 if (RetVT == MVT::i8)
383 return FPTOSINT_F64_I8;
384 if (RetVT == MVT::i16)
385 return FPTOSINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]386 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]387 return FPTOSINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]388 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]389 return FPTOSINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]390 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]391 return FPTOSINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]392 } else if (OpVT == MVT::f80) {
393 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]394 return FPTOSINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]395 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]396 return FPTOSINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]397 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]398 return FPTOSINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]399 } else if (OpVT == MVT::ppcf128) {
400 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]401 return FPTOSINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]402 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]403 return FPTOSINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]404 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]405 return FPTOSINT_PPCF128_I128;
406 }
407 return UNKNOWN_LIBCALL;
408}
409
410/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
411/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]412RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]413 if (OpVT == MVT::f32) {
414 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]415 return FPTOUINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]416 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]417 return FPTOUINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]418 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]419 return FPTOUINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]420 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]421 return FPTOUINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]422 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]423 return FPTOUINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]424 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]425 if (RetVT == MVT::i8)
426 return FPTOUINT_F64_I8;
427 if (RetVT == MVT::i16)
428 return FPTOUINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]429 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]430 return FPTOUINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]431 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]432 return FPTOUINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]433 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]434 return FPTOUINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]435 } else if (OpVT == MVT::f80) {
436 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]437 return FPTOUINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]438 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]439 return FPTOUINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]440 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]441 return FPTOUINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]442 } else if (OpVT == MVT::ppcf128) {
443 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]444 return FPTOUINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]445 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]446 return FPTOUINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]447 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]448 return FPTOUINT_PPCF128_I128;
449 }
450 return UNKNOWN_LIBCALL;
451}
452
453/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
454/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]455RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]456 if (OpVT == MVT::i32) {
457 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]458 return SINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]459 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]460 return SINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]461 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]462 return SINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]463 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]464 return SINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]465 } else if (OpVT == MVT::i64) {
466 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]467 return SINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]468 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]469 return SINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]470 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]471 return SINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]472 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]473 return SINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]474 } else if (OpVT == MVT::i128) {
475 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]476 return SINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]477 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]478 return SINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]479 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]480 return SINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]481 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]482 return SINTTOFP_I128_PPCF128;
483 }
484 return UNKNOWN_LIBCALL;
485}
486
487/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
488/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]489RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]490 if (OpVT == MVT::i32) {
491 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]492 return UINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]493 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]494 return UINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]495 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]496 return UINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]497 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]498 return UINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]499 } else if (OpVT == MVT::i64) {
500 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]501 return UINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]502 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]503 return UINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]504 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]505 return UINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]506 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]507 return UINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]508 } else if (OpVT == MVT::i128) {
509 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]510 return UINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]511 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]512 return UINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]513 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]514 return UINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]515 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]516 return UINTTOFP_I128_PPCF128;
517 }
518 return UNKNOWN_LIBCALL;
519}
520
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]521/// InitCmpLibcallCCs - Set default comparison libcall CC.
522///
523static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
524 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
525 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
526 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
527 CCs[RTLIB::UNE_F32] = ISD::SETNE;
528 CCs[RTLIB::UNE_F64] = ISD::SETNE;
529 CCs[RTLIB::OGE_F32] = ISD::SETGE;
530 CCs[RTLIB::OGE_F64] = ISD::SETGE;
531 CCs[RTLIB::OLT_F32] = ISD::SETLT;
532 CCs[RTLIB::OLT_F64] = ISD::SETLT;
533 CCs[RTLIB::OLE_F32] = ISD::SETLE;
534 CCs[RTLIB::OLE_F64] = ISD::SETLE;
535 CCs[RTLIB::OGT_F32] = ISD::SETGT;
536 CCs[RTLIB::OGT_F64] = ISD::SETGT;
537 CCs[RTLIB::UO_F32] = ISD::SETNE;
538 CCs[RTLIB::UO_F64] = ISD::SETNE;
539 CCs[RTLIB::O_F32] = ISD::SETEQ;
540 CCs[RTLIB::O_F64] = ISD::SETEQ;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]541}
542
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]543/// NOTE: The constructor takes ownership of TLOF.
Dan Gohmanf0757b02010-04-21 01:34:56 +0000[diff] [blame]544TargetLowering::TargetLowering(const TargetMachine &tm,
545 const TargetLoweringObjectFile *tlof)
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]546 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof),
547 mayPromoteElements(AllowPromoteIntElem) {
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]548 // All operations default to being supported.
549 memset(OpActions, 0, sizeof(OpActions));
Evan Cheng03294662008-10-14 21:26:46 +0000[diff] [blame]550 memset(LoadExtActions, 0, sizeof(LoadExtActions));
Chris Lattnerddf89562008-01-17 19:59:44 +0000[diff] [blame]551 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
Chris Lattnerc9133f92008-01-18 19:36:20 +0000[diff] [blame]552 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
Evan Cheng7f042682008-10-15 02:05:31 +0000[diff] [blame]553 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Dan Gohman93f81e22007-07-09 20:49:44 +0000[diff] [blame]554
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]555 // Set default actions for various operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]556 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]557 // Default all indexed load / store to expand.
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]558 for (unsigned IM = (unsigned)ISD::PRE_INC;
559 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]560 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
561 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]562 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]563
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]564 // These operations default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]565 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]567 }
Evan Chengd2cde682008-03-10 19:38:10 +0000[diff] [blame]568
569 // Most targets ignore the @llvm.prefetch intrinsic.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]570 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]571
572 // ConstantFP nodes default to expand. Targets can either change this to
Evan Chengeb2f9692009-10-27 19:56:55 +0000[diff] [blame]573 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
Nate Begemane1795842008-02-14 08:57:00 +0000[diff] [blame]574 // to optimize expansions for certain constants.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]575 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
576 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
577 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]578
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]579 // These library functions default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]580 setOperationAction(ISD::FLOG , MVT::f64, Expand);
581 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
582 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
583 setOperationAction(ISD::FEXP , MVT::f64, Expand);
584 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
585 setOperationAction(ISD::FLOG , MVT::f32, Expand);
586 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
587 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
588 setOperationAction(ISD::FEXP , MVT::f32, Expand);
589 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]590
Chris Lattner41bab0b2008-01-15 21:58:08 +0000[diff] [blame]591 // Default ISD::TRAP to expand (which turns it into abort).
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]592 setOperationAction(ISD::TRAP, MVT::Other, Expand);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]593
Owen Andersona69571c2006-05-03 01:29:57 +0000[diff] [blame]594 IsLittleEndian = TD->isLittleEndian();
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]595 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]596 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]597 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Evan Chenga03a5dc2006-02-14 08:38:30 +0000[diff] [blame]598 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
Evan Cheng05219282011-01-06 06:52:41 +0000[diff] [blame]599 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
600 = maxStoresPerMemmoveOptSize = 4;
Evan Cheng6ebf7bc2009-05-13 21:42:09 +0000[diff] [blame]601 benefitFromCodePlacementOpt = false;
Anton Korobeynikovd27a2582006-12-10 23:12:42 +0000[diff] [blame]602 UseUnderscoreSetJmp = false;
603 UseUnderscoreLongJmp = false;
Chris Lattner66180392007-02-25 01:28:05 +0000[diff] [blame]604 SelectIsExpensive = false;
Nate Begeman405e3ec2005-10-21 00:02:42 +0000[diff] [blame]605 IntDivIsCheap = false;
606 Pow2DivIsCheap = false;
Chris Lattnerde189be2010-11-30 18:12:52 +0000[diff] [blame]607 JumpIsExpensive = false;
Chris Lattneree4a7652006-01-25 18:57:15 +0000[diff] [blame]608 StackPointerRegisterToSaveRestore = 0;
Jim Laskey9bb3c932007-02-22 18:04:49 +0000[diff] [blame]609 ExceptionPointerRegister = 0;
610 ExceptionSelectorRegister = 0;
Duncan Sands03228082008-11-23 15:47:28 +0000[diff] [blame]611 BooleanContents = UndefinedBooleanContent;
Evan Cheng211ffa12010-05-19 20:19:50 +0000[diff] [blame]612 SchedPreferenceInfo = Sched::Latency;
Chris Lattner7acf5f32006-09-05 17:39:15 +0000[diff] [blame]613 JumpBufSize = 0;
Duraid Madina0c9e0ff2006-09-04 07:44:11 +0000[diff] [blame]614 JumpBufAlignment = 0;
Eli Friedmanfc5d3052011-05-06 20:34:06 +0000[diff] [blame]615 MinFunctionAlignment = 0;
616 PrefFunctionAlignment = 0;
Evan Chengfb8075d2008-02-28 00:43:03 +0000[diff] [blame]617 PrefLoopAlignment = 0;
Rafael Espindolacbeeae22010-07-11 04:01:49 +0000[diff] [blame]618 MinStackArgumentAlignment = 1;
Jim Grosbach9a526492010-06-23 16:07:42 +0000[diff] [blame]619 ShouldFoldAtomicFences = false;
Eli Friedman26689ac2011-08-03 21:06:02 +0000[diff] [blame]620 InsertFencesForAtomic = false;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]621
622 InitLibcallNames(LibcallRoutineNames);
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]623 InitCmpLibcallCCs(CmpLibcallCCs);
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]624 InitLibcallCallingConvs(LibcallCallingConvs);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]625}
626
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]627TargetLowering::~TargetLowering() {
628 delete &TLOF;
629}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]630
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]631MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
632 return MVT::getIntegerVT(8*TD->getPointerSize());
633}
634
Mon P Wangf7ea6c32010-02-10 23:37:45 +0000[diff] [blame]635/// canOpTrap - Returns true if the operation can trap for the value type.
636/// VT must be a legal type.
637bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
638 assert(isTypeLegal(VT));
639 switch (Op) {
640 default:
641 return false;
642 case ISD::FDIV:
643 case ISD::FREM:
644 case ISD::SDIV:
645 case ISD::UDIV:
646 case ISD::SREM:
647 case ISD::UREM:
648 return true;
649 }
650}
651
652
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]653static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]654 unsigned &NumIntermediates,
655 EVT &RegisterVT,
656 TargetLowering *TLI) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]657 // Figure out the right, legal destination reg to copy into.
658 unsigned NumElts = VT.getVectorNumElements();
659 MVT EltTy = VT.getVectorElementType();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]660
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]661 unsigned NumVectorRegs = 1;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]662
663 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]664 // could break down into LHS/RHS like LegalizeDAG does.
665 if (!isPowerOf2_32(NumElts)) {
666 NumVectorRegs = NumElts;
667 NumElts = 1;
668 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]669
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]670 // Divide the input until we get to a supported size. This will always
671 // end with a scalar if the target doesn't support vectors.
672 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
673 NumElts >>= 1;
674 NumVectorRegs <<= 1;
675 }
676
677 NumIntermediates = NumVectorRegs;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]678
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]679 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
680 if (!TLI->isTypeLegal(NewVT))
681 NewVT = EltTy;
682 IntermediateVT = NewVT;
683
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]684 unsigned NewVTSize = NewVT.getSizeInBits();
685
686 // Convert sizes such as i33 to i64.
687 if (!isPowerOf2_32(NewVTSize))
688 NewVTSize = NextPowerOf2(NewVTSize);
689
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]690 EVT DestVT = TLI->getRegisterType(NewVT);
691 RegisterVT = DestVT;
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]692 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]693 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]694
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]695 // Otherwise, promotion or legal types use the same number of registers as
696 // the vector decimated to the appropriate level.
697 return NumVectorRegs;
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]698}
699
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]700/// isLegalRC - Return true if the value types that can be represented by the
701/// specified register class are all legal.
702bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
703 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
704 I != E; ++I) {
705 if (isTypeLegal(*I))
706 return true;
707 }
708 return false;
709}
710
711/// hasLegalSuperRegRegClasses - Return true if the specified register class
712/// has one or more super-reg register classes that are legal.
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]713bool
714TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]715 if (*RC->superregclasses_begin() == 0)
716 return false;
717 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
718 E = RC->superregclasses_end(); I != E; ++I) {
719 const TargetRegisterClass *RRC = *I;
720 if (isLegalRC(RRC))
721 return true;
722 }
723 return false;
724}
725
726/// findRepresentativeClass - Return the largest legal super-reg register class
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]727/// of the register class for the specified type and its associated "cost".
728std::pair<const TargetRegisterClass*, uint8_t>
729TargetLowering::findRepresentativeClass(EVT VT) const {
730 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
731 if (!RC)
732 return std::make_pair(RC, 0);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]733 const TargetRegisterClass *BestRC = RC;
734 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
735 E = RC->superregclasses_end(); I != E; ++I) {
736 const TargetRegisterClass *RRC = *I;
737 if (RRC->isASubClass() || !isLegalRC(RRC))
738 continue;
739 if (!hasLegalSuperRegRegClasses(RRC))
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]740 return std::make_pair(RRC, 1);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]741 BestRC = RRC;
742 }
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]743 return std::make_pair(BestRC, 1);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]744}
745
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]746
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]747/// computeRegisterProperties - Once all of the register classes are added,
748/// this allows us to compute derived properties we expose.
749void TargetLowering::computeRegisterProperties() {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]750 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]751 "Too many value types for ValueTypeActions to hold!");
752
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]753 // Everything defaults to needing one register.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]754 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]755 NumRegistersForVT[i] = 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]756 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]757 }
758 // ...except isVoid, which doesn't need any registers.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]759 NumRegistersForVT[MVT::isVoid] = 0;
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]760
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]761 // Find the largest integer register class.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]762 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]763 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]764 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]765
766 // Every integer value type larger than this largest register takes twice as
767 // many registers to represent as the previous ValueType.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]768 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
Dan Gohman8a55ce42009-09-23 21:02:20 +0000[diff] [blame]769 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
770 if (!ExpandedVT.isInteger())
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]771 break;
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]772 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]773 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
774 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]775 ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger);
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]776 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]777
778 // Inspect all of the ValueType's smaller than the largest integer
779 // register to see which ones need promotion.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]780 unsigned LegalIntReg = LargestIntReg;
781 for (unsigned IntReg = LargestIntReg - 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]782 IntReg >= (unsigned)MVT::i1; --IntReg) {
783 EVT IVT = (MVT::SimpleValueType)IntReg;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]784 if (isTypeLegal(IVT)) {
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]785 LegalIntReg = IntReg;
786 } else {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]787 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]788 (MVT::SimpleValueType)LegalIntReg;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]789 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]790 }
791 }
792
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]793 // ppcf128 type is really two f64's.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]794 if (!isTypeLegal(MVT::ppcf128)) {
795 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
796 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
797 TransformToType[MVT::ppcf128] = MVT::f64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]798 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]799 }
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]800
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]801 // Decide how to handle f64. If the target does not have native f64 support,
802 // expand it to i64 and we will be generating soft float library calls.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]803 if (!isTypeLegal(MVT::f64)) {
804 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
805 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
806 TransformToType[MVT::f64] = MVT::i64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]807 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]808 }
809
810 // Decide how to handle f32. If the target does not have native support for
811 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]812 if (!isTypeLegal(MVT::f32)) {
813 if (isTypeLegal(MVT::f64)) {
814 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
815 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
816 TransformToType[MVT::f32] = MVT::f64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]817 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]818 } else {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]819 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
820 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
821 TransformToType[MVT::f32] = MVT::i32;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]822 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]823 }
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]824 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]825
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]826 // Loop over all of the vector value types to see which need transformations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]827 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
828 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]829 MVT VT = (MVT::SimpleValueType)i;
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]830 if (isTypeLegal(VT)) continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]831
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]832 // Determine if there is a legal wider type. If so, we should promote to
833 // that wider vector type.
834 EVT EltVT = VT.getVectorElementType();
835 unsigned NElts = VT.getVectorNumElements();
836 if (NElts != 1) {
837 bool IsLegalWiderType = false;
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]838 // If we allow the promotion of vector elements using a flag,
839 // then return TypePromoteInteger on vector elements.
840 // First try to promote the elements of integer vectors. If no legal
841 // promotion was found, fallback to the widen-vector method.
842 if (mayPromoteElements)
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]843 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
844 EVT SVT = (MVT::SimpleValueType)nVT;
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]845 // Promote vectors of integers to vectors with the same number
846 // of elements, with a wider element type.
847 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
848 && SVT.getVectorNumElements() == NElts &&
849 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
850 TransformToType[i] = SVT;
851 RegisterTypeForVT[i] = SVT;
852 NumRegistersForVT[i] = 1;
853 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
854 IsLegalWiderType = true;
855 break;
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]856 }
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]857 }
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]858
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]859 if (IsLegalWiderType) continue;
860
861 // Try to widen the vector.
862 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
863 EVT SVT = (MVT::SimpleValueType)nVT;
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]864 if (SVT.getVectorElementType() == EltVT &&
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]865 SVT.getVectorNumElements() > NElts &&
Dale Johannesene93d99c2010-10-20 21:32:10 +0000[diff] [blame]866 isTypeLegal(SVT)) {
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]867 TransformToType[i] = SVT;
868 RegisterTypeForVT[i] = SVT;
869 NumRegistersForVT[i] = 1;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]870 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]871 IsLegalWiderType = true;
872 break;
873 }
874 }
875 if (IsLegalWiderType) continue;
876 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]877
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]878 MVT IntermediateVT;
879 EVT RegisterVT;
880 unsigned NumIntermediates;
881 NumRegistersForVT[i] =
882 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
883 RegisterVT, this);
884 RegisterTypeForVT[i] = RegisterVT;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]885
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]886 EVT NVT = VT.getPow2VectorType();
887 if (NVT == VT) {
888 // Type is already a power of 2. The default action is to split.
889 TransformToType[i] = MVT::Other;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]890 unsigned NumElts = VT.getVectorNumElements();
891 ValueTypeActions.setTypeAction(VT,
892 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]893 } else {
894 TransformToType[i] = NVT;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]895 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]896 }
Chris Lattner3a5935842006-03-16 19:50:01 +0000[diff] [blame]897 }
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]898
899 // Determine the 'representative' register class for each value type.
900 // An representative register class is the largest (meaning one which is
901 // not a sub-register class / subreg register class) legal register class for
902 // a group of value types. For example, on i386, i8, i16, and i32
903 // representative would be GR32; while on x86_64 it's GR64.
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]904 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]905 const TargetRegisterClass* RRC;
906 uint8_t Cost;
907 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
908 RepRegClassForVT[i] = RRC;
909 RepRegClassCostForVT[i] = Cost;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]910 }
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]911}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]912
Evan Cheng72261582005-12-20 06:22:03 +0000[diff] [blame]913const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
914 return NULL;
915}
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]916
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]917
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]918MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
Owen Anderson1d0be152009-08-13 21:58:54 +0000[diff] [blame]919 return PointerTy.SimpleTy;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]920}
921
Sanjiv Gupta8f17a362009-12-28 02:40:33 +0000[diff] [blame]922MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
923 return MVT::i32; // return the default value
924}
925
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]926/// getVectorTypeBreakdown - Vector types are broken down into some number of
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]927/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
928/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
929/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]930///
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]931/// This method returns the number of registers needed, and the VT for each
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]932/// register. It also returns the VT and quantity of the intermediate values
933/// before they are promoted/expanded.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]934///
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]935unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]936 EVT &IntermediateVT,
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]937 unsigned &NumIntermediates,
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]938 EVT &RegisterVT) const {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]939 unsigned NumElts = VT.getVectorNumElements();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]940
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]941 // If there is a wider vector type with the same element type as this one,
942 // we should widen to that legal vector type. This handles things like
943 // <2 x float> -> <4 x float>.
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]944 if (NumElts != 1 && getTypeAction(Context, VT) == TypeWidenVector) {
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]945 RegisterVT = getTypeToTransformTo(Context, VT);
946 if (isTypeLegal(RegisterVT)) {
947 IntermediateVT = RegisterVT;
948 NumIntermediates = 1;
949 return 1;
950 }
951 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]952
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]953 // Figure out the right, legal destination reg to copy into.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]954 EVT EltTy = VT.getVectorElementType();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]955
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]956 unsigned NumVectorRegs = 1;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]957
958 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Nate Begemand73ab882007-11-27 19:28:48 +0000[diff] [blame]959 // could break down into LHS/RHS like LegalizeDAG does.
960 if (!isPowerOf2_32(NumElts)) {
961 NumVectorRegs = NumElts;
962 NumElts = 1;
963 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]964
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]965 // Divide the input until we get to a supported size. This will always
966 // end with a scalar if the target doesn't support vectors.
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]967 while (NumElts > 1 && !isTypeLegal(
968 EVT::getVectorVT(Context, EltTy, NumElts))) {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]969 NumElts >>= 1;
970 NumVectorRegs <<= 1;
971 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]972
973 NumIntermediates = NumVectorRegs;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]974
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]975 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]976 if (!isTypeLegal(NewVT))
977 NewVT = EltTy;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]978 IntermediateVT = NewVT;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]979
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]980 EVT DestVT = getRegisterType(Context, NewVT);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]981 RegisterVT = DestVT;
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]982 unsigned NewVTSize = NewVT.getSizeInBits();
983
984 // Convert sizes such as i33 to i64.
985 if (!isPowerOf2_32(NewVTSize))
986 NewVTSize = NextPowerOf2(NewVTSize);
987
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]988 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]989 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]990
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]991 // Otherwise, promotion or legal types use the same number of registers as
992 // the vector decimated to the appropriate level.
993 return NumVectorRegs;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]994}
995
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]996/// Get the EVTs and ArgFlags collections that represent the legalized return
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]997/// type of the given function. This does not require a DAG or a return value,
998/// and is suitable for use before any DAGs for the function are constructed.
999/// TODO: Move this out of TargetLowering.cpp.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]1000void llvm::GetReturnInfo(Type* ReturnType, Attributes attr,
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1001 SmallVectorImpl<ISD::OutputArg> &Outs,
1002 const TargetLowering &TLI,
1003 SmallVectorImpl<uint64_t> *Offsets) {
1004 SmallVector<EVT, 4> ValueVTs;
1005 ComputeValueVTs(TLI, ReturnType, ValueVTs);
1006 unsigned NumValues = ValueVTs.size();
1007 if (NumValues == 0) return;
1008 unsigned Offset = 0;
1009
1010 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1011 EVT VT = ValueVTs[j];
1012 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1013
1014 if (attr & Attribute::SExt)
1015 ExtendKind = ISD::SIGN_EXTEND;
1016 else if (attr & Attribute::ZExt)
1017 ExtendKind = ISD::ZERO_EXTEND;
1018
1019 // FIXME: C calling convention requires the return type to be promoted to
1020 // at least 32-bit. But this is not necessary for non-C calling
1021 // conventions. The frontend should mark functions whose return values
1022 // require promoting with signext or zeroext attributes.
1023 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1024 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1025 if (VT.bitsLT(MinVT))
1026 VT = MinVT;
1027 }
1028
1029 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1030 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1031 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
1032 PartVT.getTypeForEVT(ReturnType->getContext()));
1033
1034 // 'inreg' on function refers to return value
1035 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1036 if (attr & Attribute::InReg)
1037 Flags.setInReg();
1038
1039 // Propagate extension type if any
1040 if (attr & Attribute::SExt)
1041 Flags.setSExt();
1042 else if (attr & Attribute::ZExt)
1043 Flags.setZExt();
1044
1045 for (unsigned i = 0; i < NumParts; ++i) {
1046 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
1047 if (Offsets) {
1048 Offsets->push_back(Offset);
1049 Offset += PartSize;
1050 }
1051 }
1052 }
1053}
1054
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]1055/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]1056/// function arguments in the caller parameter area. This is the actual
1057/// alignment, not its logarithm.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]1058unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]1059 return TD->getCallFrameTypeAlignment(Ty);
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]1060}
1061
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1062/// getJumpTableEncoding - Return the entry encoding for a jump table in the
1063/// current function. The returned value is a member of the
1064/// MachineJumpTableInfo::JTEntryKind enum.
1065unsigned TargetLowering::getJumpTableEncoding() const {
1066 // In non-pic modes, just use the address of a block.
1067 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1068 return MachineJumpTableInfo::EK_BlockAddress;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1069
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1070 // In PIC mode, if the target supports a GPRel32 directive, use it.
1071 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1072 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1073
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1074 // Otherwise, use a label difference.
1075 return MachineJumpTableInfo::EK_LabelDifference32;
1076}
1077
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1078SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1079 SelectionDAG &DAG) const {
Chris Lattnerf1214cb2010-01-26 06:53:37 +0000[diff] [blame]1080 // If our PIC model is GP relative, use the global offset table as the base.
1081 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
Dale Johannesenb300d2a2009-02-07 00:55:49 +0000[diff] [blame]1082 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
Evan Chengcc415862007-11-09 01:32:10 +0000[diff] [blame]1083 return Table;
1084}
1085
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1086/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1087/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1088/// MCExpr.
1089const MCExpr *
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1090TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1091 unsigned JTI,MCContext &Ctx) const{
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]1092 // The normal PIC reloc base is the label at the start of the jump table.
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1093 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1094}
1095
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1096bool
1097TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1098 // Assume that everything is safe in static mode.
1099 if (getTargetMachine().getRelocationModel() == Reloc::Static)
1100 return true;
1101
1102 // In dynamic-no-pic mode, assume that known defined values are safe.
1103 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1104 GA &&
1105 !GA->getGlobal()->isDeclaration() &&
Duncan Sands667d4b82009-03-07 15:45:40 +0000[diff] [blame]1106 !GA->getGlobal()->isWeakForLinker())
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1107 return true;
1108
1109 // Otherwise assume nothing is safe.
1110 return false;
1111}
1112
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]1113//===----------------------------------------------------------------------===//
1114// Optimization Methods
1115//===----------------------------------------------------------------------===//
1116
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1117/// ShrinkDemandedConstant - Check to see if the specified operand of the
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1118/// specified instruction is a constant integer. If so, check to see if there
1119/// are any bits set in the constant that are not demanded. If so, shrink the
1120/// constant and return true.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1121bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1122 const APInt &Demanded) {
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1123 DebugLoc dl = Op.getDebugLoc();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1124
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1125 // FIXME: ISD::SELECT, ISD::SELECT_CC
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1126 switch (Op.getOpcode()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1127 default: break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1128 case ISD::XOR:
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1129 case ISD::AND:
1130 case ISD::OR: {
1131 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1132 if (!C) return false;
1133
1134 if (Op.getOpcode() == ISD::XOR &&
1135 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1136 return false;
1137
1138 // if we can expand it to have all bits set, do it
1139 if (C->getAPIntValue().intersects(~Demanded)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1140 EVT VT = Op.getValueType();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1141 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1142 DAG.getConstant(Demanded &
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1143 C->getAPIntValue(),
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1144 VT));
1145 return CombineTo(Op, New);
1146 }
1147
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1148 break;
1149 }
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1150 }
1151
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1152 return false;
1153}
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1154
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1155/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1156/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1157/// cast, but it could be generalized for targets with other types of
1158/// implicit widening casts.
1159bool
1160TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1161 unsigned BitWidth,
1162 const APInt &Demanded,
1163 DebugLoc dl) {
1164 assert(Op.getNumOperands() == 2 &&
1165 "ShrinkDemandedOp only supports binary operators!");
1166 assert(Op.getNode()->getNumValues() == 1 &&
1167 "ShrinkDemandedOp only supports nodes with one result!");
1168
1169 // Don't do this if the node has another user, which may require the
1170 // full value.
1171 if (!Op.getNode()->hasOneUse())
1172 return false;
1173
1174 // Search for the smallest integer type with free casts to and from
1175 // Op's type. For expedience, just check power-of-2 integer types.
1176 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1177 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1178 if (!isPowerOf2_32(SmallVTBits))
1179 SmallVTBits = NextPowerOf2(SmallVTBits);
1180 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1181 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1182 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1183 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1184 // We found a type with free casts.
1185 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1186 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1187 Op.getNode()->getOperand(0)),
1188 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1189 Op.getNode()->getOperand(1)));
1190 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1191 return CombineTo(Op, Z);
1192 }
1193 }
1194 return false;
1195}
1196
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1197/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
Chad Rosier8c1ec5a2011-06-11 02:27:46 +0000[diff] [blame]1198/// DemandedMask bits of the result of Op are ever used downstream. If we can
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1199/// use this information to simplify Op, create a new simplified DAG node and
1200/// return true, returning the original and new nodes in Old and New. Otherwise,
1201/// analyze the expression and return a mask of KnownOne and KnownZero bits for
1202/// the expression (used to simplify the caller). The KnownZero/One bits may
1203/// only be accurate for those bits in the DemandedMask.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1204bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1205 const APInt &DemandedMask,
1206 APInt &KnownZero,
1207 APInt &KnownOne,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1208 TargetLoweringOpt &TLO,
1209 unsigned Depth) const {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1210 unsigned BitWidth = DemandedMask.getBitWidth();
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1211 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1212 "Mask size mismatches value type size!");
1213 APInt NewMask = DemandedMask;
Dale Johannesen6f38cb62009-02-07 19:59:05 +0000[diff] [blame]1214 DebugLoc dl = Op.getDebugLoc();
Chris Lattner3fc5b012007-05-17 18:19:23 +0000[diff] [blame]1215
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1216 // Don't know anything.
1217 KnownZero = KnownOne = APInt(BitWidth, 0);
1218
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1219 // Other users may use these bits.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1220 if (!Op.getNode()->hasOneUse()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1221 if (Depth != 0) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1222 // If not at the root, Just compute the KnownZero/KnownOne bits to
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1223 // simplify things downstream.
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1224 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1225 return false;
1226 }
1227 // If this is the root being simplified, allow it to have multiple uses,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1228 // just set the NewMask to all bits.
1229 NewMask = APInt::getAllOnesValue(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1230 } else if (DemandedMask == 0) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1231 // Not demanding any bits from Op.
1232 if (Op.getOpcode() != ISD::UNDEF)
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]1233 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1234 return false;
1235 } else if (Depth == 6) { // Limit search depth.
1236 return false;
1237 }
1238
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1239 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1240 switch (Op.getOpcode()) {
1241 case ISD::Constant:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1242 // We know all of the bits for a constant!
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1243 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
1244 KnownZero = ~KnownOne & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1245 return false; // Don't fall through, will infinitely loop.
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1246 case ISD::AND:
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1247 // If the RHS is a constant, check to see if the LHS would be zero without
1248 // using the bits from the RHS. Below, we use knowledge about the RHS to
1249 // simplify the LHS, here we're using information from the LHS to simplify
1250 // the RHS.
1251 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1252 APInt LHSZero, LHSOne;
Dale Johannesen97fd9a52011-01-10 21:53:07 +0000[diff] [blame]1253 // Do not increment Depth here; that can cause an infinite loop.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1254 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
Dale Johannesen97fd9a52011-01-10 21:53:07 +0000[diff] [blame]1255 LHSZero, LHSOne, Depth);
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1256 // If the LHS already has zeros where RHSC does, this and is dead.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1257 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1258 return TLO.CombineTo(Op, Op.getOperand(0));
1259 // If any of the set bits in the RHS are known zero on the LHS, shrink
1260 // the constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1261 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1262 return true;
1263 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1264
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1265 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1266 KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1267 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1268 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1269 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1270 KnownZero2, KnownOne2, TLO, Depth+1))
1271 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1272 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1273
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1274 // If all of the demanded bits are known one on one side, return the other.
1275 // These bits cannot contribute to the result of the 'and'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1276 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1277 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1278 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1279 return TLO.CombineTo(Op, Op.getOperand(1));
1280 // If all of the demanded bits in the inputs are known zeros, return zero.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1281 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1282 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1283 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1284 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1285 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1286 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1287 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1288 return true;
1289
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1290 // Output known-1 bits are only known if set in both the LHS & RHS.
1291 KnownOne &= KnownOne2;
1292 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1293 KnownZero |= KnownZero2;
1294 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1295 case ISD::OR:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1296 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1297 KnownOne, TLO, Depth+1))
1298 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1299 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1300 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1301 KnownZero2, KnownOne2, TLO, Depth+1))
1302 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1303 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1304
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1305 // If all of the demanded bits are known zero on one side, return the other.
1306 // These bits cannot contribute to the result of the 'or'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1307 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1308 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1309 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1310 return TLO.CombineTo(Op, Op.getOperand(1));
1311 // If all of the potentially set bits on one side are known to be set on
1312 // the other side, just use the 'other' side.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1313 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1314 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1315 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1316 return TLO.CombineTo(Op, Op.getOperand(1));
1317 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1318 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1319 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1320 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1321 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1322 return true;
1323
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1324 // Output known-0 bits are only known if clear in both the LHS & RHS.
1325 KnownZero &= KnownZero2;
1326 // Output known-1 are known to be set if set in either the LHS | RHS.
1327 KnownOne |= KnownOne2;
1328 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1329 case ISD::XOR:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1330 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1331 KnownOne, TLO, Depth+1))
1332 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1333 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1334 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1335 KnownOne2, TLO, Depth+1))
1336 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1337 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1338
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1339 // If all of the demanded bits are known zero on one side, return the other.
1340 // These bits cannot contribute to the result of the 'xor'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1341 if ((KnownZero & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1342 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1343 if ((KnownZero2 & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1344 return TLO.CombineTo(Op, Op.getOperand(1));
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1345 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1346 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1347 return true;
1348
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1349 // If all of the unknown bits are known to be zero on one side or the other
1350 // (but not both) turn this into an *inclusive* or.
1351 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1352 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1353 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1354 Op.getOperand(0),
1355 Op.getOperand(1)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1356
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1357 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1358 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1359 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1360 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1361
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1362 // If all of the demanded bits on one side are known, and all of the set
1363 // bits on that side are also known to be set on the other side, turn this
1364 // into an AND, as we know the bits will be cleared.
1365 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1366 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1367 if ((KnownOne & KnownOne2) == KnownOne) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1368 EVT VT = Op.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1369 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1370 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1371 Op.getOperand(0), ANDC));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1372 }
1373 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1374
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1375 // If the RHS is a constant, see if we can simplify it.
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1376 // for XOR, we prefer to force bits to 1 if they will make a -1.
1377 // if we can't force bits, try to shrink constant
1378 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1379 APInt Expanded = C->getAPIntValue() | (~NewMask);
1380 // if we can expand it to have all bits set, do it
1381 if (Expanded.isAllOnesValue()) {
1382 if (Expanded != C->getAPIntValue()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1383 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1384 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1385 TLO.DAG.getConstant(Expanded, VT));
1386 return TLO.CombineTo(Op, New);
1387 }
1388 // if it already has all the bits set, nothing to change
1389 // but don't shrink either!
1390 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1391 return true;
1392 }
1393 }
1394
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1395 KnownZero = KnownZeroOut;
1396 KnownOne = KnownOneOut;
1397 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1398 case ISD::SELECT:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1399 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1400 KnownOne, TLO, Depth+1))
1401 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1402 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1403 KnownOne2, TLO, Depth+1))
1404 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1405 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1406 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1407
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1408 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1409 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1410 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1411
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1412 // Only known if known in both the LHS and RHS.
1413 KnownOne &= KnownOne2;
1414 KnownZero &= KnownZero2;
1415 break;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1416 case ISD::SELECT_CC:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1417 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1418 KnownOne, TLO, Depth+1))
1419 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1420 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1421 KnownOne2, TLO, Depth+1))
1422 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1423 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1424 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1425
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1426 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1427 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1428 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1429
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1430 // Only known if known in both the LHS and RHS.
1431 KnownOne &= KnownOne2;
1432 KnownZero &= KnownZero2;
1433 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1434 case ISD::SHL:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1435 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1436 unsigned ShAmt = SA->getZExtValue();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1437 SDValue InOp = Op.getOperand(0);
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1438
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1439 // If the shift count is an invalid immediate, don't do anything.
1440 if (ShAmt >= BitWidth)
1441 break;
1442
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1443 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1444 // single shift. We can do this if the bottom bits (which are shifted
1445 // out) are never demanded.
1446 if (InOp.getOpcode() == ISD::SRL &&
1447 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1448 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1449 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1450 unsigned Opc = ISD::SHL;
1451 int Diff = ShAmt-C1;
1452 if (Diff < 0) {
1453 Diff = -Diff;
1454 Opc = ISD::SRL;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1455 }
1456
1457 SDValue NewSA =
Chris Lattner4e7e6cd2007-05-30 16:30:06 +0000[diff] [blame]1458 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1459 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1460 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1461 InOp.getOperand(0), NewSA));
1462 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1463 }
1464
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1465 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1466 KnownZero, KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1467 return true;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1468
1469 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1470 // are not demanded. This will likely allow the anyext to be folded away.
1471 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1472 SDValue InnerOp = InOp.getNode()->getOperand(0);
1473 EVT InnerVT = InnerOp.getValueType();
1474 if ((APInt::getHighBitsSet(BitWidth,
1475 BitWidth - InnerVT.getSizeInBits()) &
1476 DemandedMask) == 0 &&
1477 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]1478 EVT ShTy = getShiftAmountTy(InnerVT);
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1479 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1480 ShTy = InnerVT;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1481 SDValue NarrowShl =
1482 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1483 TLO.DAG.getConstant(ShAmt, ShTy));
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1484 return
1485 TLO.CombineTo(Op,
1486 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1487 NarrowShl));
1488 }
1489 }
1490
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1491 KnownZero <<= SA->getZExtValue();
1492 KnownOne <<= SA->getZExtValue();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1493 // low bits known zero.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1494 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1495 }
1496 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1497 case ISD::SRL:
1498 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1499 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1500 unsigned ShAmt = SA->getZExtValue();
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1501 unsigned VTSize = VT.getSizeInBits();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1502 SDValue InOp = Op.getOperand(0);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1503
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1504 // If the shift count is an invalid immediate, don't do anything.
1505 if (ShAmt >= BitWidth)
1506 break;
1507
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1508 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1509 // single shift. We can do this if the top bits (which are shifted out)
1510 // are never demanded.
1511 if (InOp.getOpcode() == ISD::SHL &&
1512 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1513 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1514 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1515 unsigned Opc = ISD::SRL;
1516 int Diff = ShAmt-C1;
1517 if (Diff < 0) {
1518 Diff = -Diff;
1519 Opc = ISD::SHL;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1520 }
1521
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1522 SDValue NewSA =
Chris Lattner8c7d2d52007-04-17 22:53:02 +0000[diff] [blame]1523 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1524 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1525 InOp.getOperand(0), NewSA));
1526 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1527 }
1528
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1529 // Compute the new bits that are at the top now.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1530 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1531 KnownZero, KnownOne, TLO, Depth+1))
1532 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1533 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1534 KnownZero = KnownZero.lshr(ShAmt);
1535 KnownOne = KnownOne.lshr(ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1536
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1537 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1538 KnownZero |= HighBits; // High bits known zero.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1539 }
1540 break;
1541 case ISD::SRA:
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1542 // If this is an arithmetic shift right and only the low-bit is set, we can
1543 // always convert this into a logical shr, even if the shift amount is
1544 // variable. The low bit of the shift cannot be an input sign bit unless
1545 // the shift amount is >= the size of the datatype, which is undefined.
1546 if (DemandedMask == 1)
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1547 return TLO.CombineTo(Op,
1548 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1549 Op.getOperand(0), Op.getOperand(1)));
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1550
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1551 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1552 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1553 unsigned ShAmt = SA->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1554
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1555 // If the shift count is an invalid immediate, don't do anything.
1556 if (ShAmt >= BitWidth)
1557 break;
1558
1559 APInt InDemandedMask = (NewMask << ShAmt);
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1560
1561 // If any of the demanded bits are produced by the sign extension, we also
1562 // demand the input sign bit.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1563 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1564 if (HighBits.intersects(NewMask))
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1565 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1566
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1567 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1568 KnownZero, KnownOne, TLO, Depth+1))
1569 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1570 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1571 KnownZero = KnownZero.lshr(ShAmt);
1572 KnownOne = KnownOne.lshr(ShAmt);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1573
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1574 // Handle the sign bit, adjusted to where it is now in the mask.
1575 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1576
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1577 // If the input sign bit is known to be zero, or if none of the top bits
1578 // are demanded, turn this into an unsigned shift right.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1579 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1580 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1581 Op.getOperand(0),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1582 Op.getOperand(1)));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1583 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1584 KnownOne |= HighBits;
1585 }
1586 }
1587 break;
1588 case ISD::SIGN_EXTEND_INREG: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1589 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1590
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1591 // Sign extension. Compute the demanded bits in the result that are not
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1592 // present in the input.
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1593 APInt NewBits =
1594 APInt::getHighBitsSet(BitWidth,
Eli Friedman1d17d192010-08-02 04:42:25 +0000[diff] [blame]1595 BitWidth - EVT.getScalarType().getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1596
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1597 // If none of the extended bits are demanded, eliminate the sextinreg.
Eli Friedman1d17d192010-08-02 04:42:25 +0000[diff] [blame]1598 if ((NewBits & NewMask) == 0)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1599 return TLO.CombineTo(Op, Op.getOperand(0));
1600
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1601 APInt InSignBit =
1602 APInt::getSignBit(EVT.getScalarType().getSizeInBits()).zext(BitWidth);
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1603 APInt InputDemandedBits =
1604 APInt::getLowBitsSet(BitWidth,
1605 EVT.getScalarType().getSizeInBits()) &
1606 NewMask;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1607
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1608 // Since the sign extended bits are demanded, we know that the sign
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1609 // bit is demanded.
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1610 InputDemandedBits |= InSignBit;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1611
1612 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1613 KnownZero, KnownOne, TLO, Depth+1))
1614 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1615 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1616
1617 // If the sign bit of the input is known set or clear, then we know the
1618 // top bits of the result.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1619
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1620 // If the input sign bit is known zero, convert this into a zero extension.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1621 if (KnownZero.intersects(InSignBit))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1622 return TLO.CombineTo(Op,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1623 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1624
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1625 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1626 KnownOne |= NewBits;
1627 KnownZero &= ~NewBits;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1628 } else { // Input sign bit unknown
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1629 KnownZero &= ~NewBits;
1630 KnownOne &= ~NewBits;
1631 }
1632 break;
1633 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1634 case ISD::ZERO_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1635 unsigned OperandBitWidth =
1636 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1637 APInt InMask = NewMask.trunc(OperandBitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1638
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1639 // If none of the top bits are demanded, convert this into an any_extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1640 APInt NewBits =
1641 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1642 if (!NewBits.intersects(NewMask))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1643 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1644 Op.getValueType(),
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1645 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1646
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1647 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1648 KnownZero, KnownOne, TLO, Depth+1))
1649 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1650 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1651 KnownZero = KnownZero.zext(BitWidth);
1652 KnownOne = KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1653 KnownZero |= NewBits;
1654 break;
1655 }
1656 case ISD::SIGN_EXTEND: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1657 EVT InVT = Op.getOperand(0).getValueType();
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1658 unsigned InBits = InVT.getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1659 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
Dan Gohman97360282008-03-11 21:29:43 +0000[diff] [blame]1660 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1661 APInt NewBits = ~InMask & NewMask;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1662
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1663 // If none of the top bits are demanded, convert this into an any_extend.
1664 if (NewBits == 0)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1665 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1666 Op.getValueType(),
1667 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1668
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1669 // Since some of the sign extended bits are demanded, we know that the sign
1670 // bit is demanded.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1671 APInt InDemandedBits = InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1672 InDemandedBits |= InSignBit;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1673 InDemandedBits = InDemandedBits.trunc(InBits);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1674
1675 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1676 KnownOne, TLO, Depth+1))
1677 return true;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1678 KnownZero = KnownZero.zext(BitWidth);
1679 KnownOne = KnownOne.zext(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1680
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1681 // If the sign bit is known zero, convert this to a zero extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1682 if (KnownZero.intersects(InSignBit))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1683 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1684 Op.getValueType(),
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1685 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1686
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1687 // If the sign bit is known one, the top bits match.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1688 if (KnownOne.intersects(InSignBit)) {
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1689 KnownOne |= NewBits;
1690 KnownZero &= ~NewBits;
1691 } else { // Otherwise, top bits aren't known.
1692 KnownOne &= ~NewBits;
1693 KnownZero &= ~NewBits;
1694 }
1695 break;
1696 }
1697 case ISD::ANY_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1698 unsigned OperandBitWidth =
1699 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1700 APInt InMask = NewMask.trunc(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1701 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1702 KnownZero, KnownOne, TLO, Depth+1))
1703 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1704 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1705 KnownZero = KnownZero.zext(BitWidth);
1706 KnownOne = KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1707 break;
1708 }
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1709 case ISD::TRUNCATE: {
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1710 // Simplify the input, using demanded bit information, and compute the known
1711 // zero/one bits live out.
Dan Gohman042919c2010-03-01 17:59:21 +0000[diff] [blame]1712 unsigned OperandBitWidth =
1713 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1714 APInt TruncMask = NewMask.zext(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1715 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1716 KnownZero, KnownOne, TLO, Depth+1))
1717 return true;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1718 KnownZero = KnownZero.trunc(BitWidth);
1719 KnownOne = KnownOne.trunc(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1720
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1721 // If the input is only used by this truncate, see if we can shrink it based
1722 // on the known demanded bits.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1723 if (Op.getOperand(0).getNode()->hasOneUse()) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1724 SDValue In = Op.getOperand(0);
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1725 switch (In.getOpcode()) {
1726 default: break;
1727 case ISD::SRL:
1728 // Shrink SRL by a constant if none of the high bits shifted in are
1729 // demanded.
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1730 if (TLO.LegalTypes() &&
1731 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1732 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1733 // undesirable.
1734 break;
1735 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1736 if (!ShAmt)
1737 break;
Owen Anderson7adf8622011-04-13 23:22:23 +0000[diff] [blame]1738 SDValue Shift = In.getOperand(1);
1739 if (TLO.LegalTypes()) {
1740 uint64_t ShVal = ShAmt->getZExtValue();
1741 Shift =
1742 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1743 }
1744
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1745 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1746 OperandBitWidth - BitWidth);
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1747 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1748
1749 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1750 // None of the shifted in bits are needed. Add a truncate of the
1751 // shift input, then shift it.
1752 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1753 Op.getValueType(),
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1754 In.getOperand(0));
1755 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1756 Op.getValueType(),
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1757 NewTrunc,
Owen Anderson7adf8622011-04-13 23:22:23 +0000[diff] [blame]1758 Shift));
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1759 }
1760 break;
1761 }
1762 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1763
1764 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1765 break;
1766 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1767 case ISD::AssertZext: {
Owen Anderson7ab15f62011-09-03 00:26:49 +0000[diff] [blame^]1768 // AssertZext demands all of the high bits, plus any of the low bits
1769 // demanded by its users.
1770 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1771 APInt InMask = APInt::getLowBitsSet(BitWidth,
1772 VT.getSizeInBits());
1773 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1774 KnownZero, KnownOne, TLO, Depth+1))
1775 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1776 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman400f75c2010-06-03 20:21:33 +0000[diff] [blame]1777
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1778 KnownZero |= ~InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1779 break;
1780 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1781 case ISD::BITCAST:
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1782 // If this is an FP->Int bitcast and if the sign bit is the only
1783 // thing demanded, turn this into a FGETSIGN.
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]1784 if (!Op.getOperand(0).getValueType().isVector() &&
1785 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1786 Op.getOperand(0).getValueType().isFloatingPoint()) {
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1787 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1788 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1789 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1790 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1791 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1792 // place. We expect the SHL to be eliminated by other optimizations.
Stuart Hastings090bf192011-06-01 18:32:25 +0000[diff] [blame]1793 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1794 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1795 if (!OpVTLegal && OpVTSizeInBits > 32)
Stuart Hastings090bf192011-06-01 18:32:25 +0000[diff] [blame]1796 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1797 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
Stuart Hastingsbdce3722011-06-01 14:04:17 +0000[diff] [blame]1798 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
Stuart Hastings3dfc4b122011-05-19 18:48:20 +0000[diff] [blame]1799 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1800 Op.getValueType(),
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1801 Sign, ShAmt));
1802 }
1803 }
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1804 break;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1805 case ISD::ADD:
1806 case ISD::MUL:
1807 case ISD::SUB: {
1808 // Add, Sub, and Mul don't demand any bits in positions beyond that
1809 // of the highest bit demanded of them.
1810 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1811 BitWidth - NewMask.countLeadingZeros());
1812 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1813 KnownOne2, TLO, Depth+1))
1814 return true;
1815 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1816 KnownOne2, TLO, Depth+1))
1817 return true;
1818 // See if the operation should be performed at a smaller bit width.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1819 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1820 return true;
1821 }
1822 // FALL THROUGH
Dan Gohman54eed372008-05-06 00:53:29 +0000[diff] [blame]1823 default:
Chris Lattner1482b5f2006-04-02 06:15:09 +0000[diff] [blame]1824 // Just use ComputeMaskedBits to compute output bits.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1825 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
Chris Lattnera6bc5a42006-02-27 01:00:42 +0000[diff] [blame]1826 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1827 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1828
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1829 // If we know the value of all of the demanded bits, return this as a
1830 // constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1831 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1832 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1833
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1834 return false;
1835}
1836
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1837/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1838/// in Mask are known to be either zero or one and return them in the
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1839/// KnownZero/KnownOne bitsets.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1840void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]1841 const APInt &Mask,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1842 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]1843 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1844 const SelectionDAG &DAG,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1845 unsigned Depth) const {
Chris Lattner1b5232a2006-04-02 06:19:46 +0000[diff] [blame]1846 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1847 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1848 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1849 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1850 "Should use MaskedValueIsZero if you don't know whether Op"
1851 " is a target node!");
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]1852 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]1853}
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]1854
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1855/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1856/// targets that want to expose additional information about sign bits to the
1857/// DAG Combiner.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1858unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1859 unsigned Depth) const {
1860 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1861 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1862 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1863 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1864 "Should use ComputeNumSignBits if you don't know whether Op"
1865 " is a target node!");
1866 return 1;
1867}
1868
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1869/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1870/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1871/// determine which bit is set.
1872///
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1873static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1874 // A left-shift of a constant one will have exactly one bit set, because
1875 // shifting the bit off the end is undefined.
1876 if (Val.getOpcode() == ISD::SHL)
1877 if (ConstantSDNode *C =
1878 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1879 if (C->getAPIntValue() == 1)
1880 return true;
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1881
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1882 // Similarly, a right-shift of a constant sign-bit will have exactly
1883 // one bit set.
1884 if (Val.getOpcode() == ISD::SRL)
1885 if (ConstantSDNode *C =
1886 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1887 if (C->getAPIntValue().isSignBit())
1888 return true;
1889
1890 // More could be done here, though the above checks are enough
1891 // to handle some common cases.
1892
1893 // Fall back to ComputeMaskedBits to catch other known cases.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1894 EVT OpVT = Val.getValueType();
Dan Gohman5b870af2010-03-02 02:14:38 +0000[diff] [blame]1895 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1896 APInt Mask = APInt::getAllOnesValue(BitWidth);
1897 APInt KnownZero, KnownOne;
1898 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1899 return (KnownZero.countPopulation() == BitWidth - 1) &&
1900 (KnownOne.countPopulation() == 1);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1901}
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1902
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1903/// SimplifySetCC - Try to simplify a setcc built with the specified operands
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1904/// and cc. If it is unable to simplify it, return a null SDValue.
1905SDValue
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1906TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1907 ISD::CondCode Cond, bool foldBooleans,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1908 DAGCombinerInfo &DCI, DebugLoc dl) const {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1909 SelectionDAG &DAG = DCI.DAG;
1910
1911 // These setcc operations always fold.
1912 switch (Cond) {
1913 default: break;
1914 case ISD::SETFALSE:
1915 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1916 case ISD::SETTRUE:
1917 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1918 }
1919
Chris Lattner7a2bdde2011-04-15 05:18:47 +0000[diff] [blame]1920 // Ensure that the constant occurs on the RHS, and fold constant
1921 // comparisons.
1922 if (isa<ConstantSDNode>(N0.getNode()))
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1923 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]1924
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1925 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
Dan Gohman6c6cd1c2008-03-03 22:22:56 +0000[diff] [blame]1926 const APInt &C1 = N1C->getAPIntValue();
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1927
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1928 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1929 // equality comparison, then we're just comparing whether X itself is
1930 // zero.
1931 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1932 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1933 N0.getOperand(1).getOpcode() == ISD::Constant) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1934 const APInt &ShAmt
1935 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1936 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1937 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1938 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1939 // (srl (ctlz x), 5) == 0 -> X != 0
1940 // (srl (ctlz x), 5) != 1 -> X != 0
1941 Cond = ISD::SETNE;
1942 } else {
1943 // (srl (ctlz x), 5) != 0 -> X == 0
1944 // (srl (ctlz x), 5) == 1 -> X == 0
1945 Cond = ISD::SETEQ;
1946 }
1947 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1948 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1949 Zero, Cond);
1950 }
1951 }
1952
Benjamin Kramerd8228922011-01-17 12:04:57 +0000[diff] [blame]1953 SDValue CTPOP = N0;
1954 // Look through truncs that don't change the value of a ctpop.
1955 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1956 CTPOP = N0.getOperand(0);
1957
1958 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
Benjamin Kramerc9b6a3e2011-01-17 18:00:28 +0000[diff] [blame]1959 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
Benjamin Kramerd8228922011-01-17 12:04:57 +0000[diff] [blame]1960 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1961 EVT CTVT = CTPOP.getValueType();
1962 SDValue CTOp = CTPOP.getOperand(0);
1963
1964 // (ctpop x) u< 2 -> (x & x-1) == 0
1965 // (ctpop x) u> 1 -> (x & x-1) != 0
1966 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1967 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1968 DAG.getConstant(1, CTVT));
1969 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1970 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1971 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1972 }
1973
1974 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1975 }
1976
Benjamin Kramere7cf0622011-04-22 18:47:44 +0000[diff] [blame]1977 // (zext x) == C --> x == (trunc C)
1978 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1979 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1980 unsigned MinBits = N0.getValueSizeInBits();
1981 SDValue PreZExt;
1982 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1983 // ZExt
1984 MinBits = N0->getOperand(0).getValueSizeInBits();
1985 PreZExt = N0->getOperand(0);
1986 } else if (N0->getOpcode() == ISD::AND) {
1987 // DAGCombine turns costly ZExts into ANDs
1988 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1989 if ((C->getAPIntValue()+1).isPowerOf2()) {
1990 MinBits = C->getAPIntValue().countTrailingOnes();
1991 PreZExt = N0->getOperand(0);
1992 }
1993 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1994 // ZEXTLOAD
1995 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1996 MinBits = LN0->getMemoryVT().getSizeInBits();
1997 PreZExt = N0;
1998 }
1999 }
2000
2001 // Make sure we're not loosing bits from the constant.
2002 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
2003 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2004 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2005 // Will get folded away.
2006 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2007 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
2008 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2009 }
2010 }
2011 }
2012
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2013 // If the LHS is '(and load, const)', the RHS is 0,
2014 // the test is for equality or unsigned, and all 1 bits of the const are
2015 // in the same partial word, see if we can shorten the load.
2016 if (DCI.isBeforeLegalize() &&
2017 N0.getOpcode() == ISD::AND && C1 == 0 &&
2018 N0.getNode()->hasOneUse() &&
2019 isa<LoadSDNode>(N0.getOperand(0)) &&
2020 N0.getOperand(0).getNode()->hasOneUse() &&
2021 isa<ConstantSDNode>(N0.getOperand(1))) {
2022 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2023 APInt bestMask;
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2024 unsigned bestWidth = 0, bestOffset = 0;
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2025 if (!Lod->isVolatile() && Lod->isUnindexed()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2026 unsigned origWidth = N0.getValueType().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2027 unsigned maskWidth = origWidth;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2028 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2029 // 8 bits, but have to be careful...
2030 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2031 origWidth = Lod->getMemoryVT().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2032 const APInt &Mask =
2033 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2034 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2035 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2036 for (unsigned offset=0; offset<origWidth/width; offset++) {
2037 if ((newMask & Mask) == Mask) {
2038 if (!TD->isLittleEndian())
2039 bestOffset = (origWidth/width - offset - 1) * (width/8);
2040 else
2041 bestOffset = (uint64_t)offset * (width/8);
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2042 bestMask = Mask.lshr(offset * (width/8) * 8);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2043 bestWidth = width;
2044 break;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]2045 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2046 newMask = newMask << width;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]2047 }
2048 }
2049 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2050 if (bestWidth) {
Chris Lattnerc0c7fca2011-04-14 04:12:47 +0000[diff] [blame]2051 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2052 if (newVT.isRound()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2053 EVT PtrType = Lod->getOperand(1).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2054 SDValue Ptr = Lod->getBasePtr();
2055 if (bestOffset != 0)
2056 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2057 DAG.getConstant(bestOffset, PtrType));
2058 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2059 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
Chris Lattnerecf42c42010-09-21 16:36:31 +0000[diff] [blame]2060 Lod->getPointerInfo().getWithOffset(bestOffset),
David Greene1e559442010-02-15 17:00:31 +0000[diff] [blame]2061 false, false, NewAlign);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2062 return DAG.getSetCC(dl, VT,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2063 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2064 DAG.getConstant(bestMask.trunc(bestWidth),
2065 newVT)),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2066 DAG.getConstant(0LL, newVT), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2067 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2068 }
2069 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2070
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2071 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2072 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2073 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2074
2075 // If the comparison constant has bits in the upper part, the
2076 // zero-extended value could never match.
2077 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2078 C1.getBitWidth() - InSize))) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2079 switch (Cond) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2080 case ISD::SETUGT:
2081 case ISD::SETUGE:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2082 case ISD::SETEQ: return DAG.getConstant(0, VT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2083 case ISD::SETULT:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2084 case ISD::SETULE:
2085 case ISD::SETNE: return DAG.getConstant(1, VT);
2086 case ISD::SETGT:
2087 case ISD::SETGE:
2088 // True if the sign bit of C1 is set.
2089 return DAG.getConstant(C1.isNegative(), VT);
2090 case ISD::SETLT:
2091 case ISD::SETLE:
2092 // True if the sign bit of C1 isn't set.
2093 return DAG.getConstant(C1.isNonNegative(), VT);
2094 default:
Jakob Stoklund Olesen78d12642009-07-24 18:22:59 +0000[diff] [blame]2095 break;
2096 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2097 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2098
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2099 // Otherwise, we can perform the comparison with the low bits.
2100 switch (Cond) {
2101 case ISD::SETEQ:
2102 case ISD::SETNE:
2103 case ISD::SETUGT:
2104 case ISD::SETUGE:
2105 case ISD::SETULT:
2106 case ISD::SETULE: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2107 EVT newVT = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2108 if (DCI.isBeforeLegalizeOps() ||
2109 (isOperationLegal(ISD::SETCC, newVT) &&
2110 getCondCodeAction(Cond, newVT)==Legal))
2111 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]2112 DAG.getConstant(C1.trunc(InSize), newVT),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2113 Cond);
2114 break;
2115 }
2116 default:
2117 break; // todo, be more careful with signed comparisons
2118 }
2119 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2120 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2121 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2122 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2123 EVT ExtDstTy = N0.getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2124 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2125
Eli Friedmanad78a882010-07-30 06:44:31 +0000[diff] [blame]2126 // If the constant doesn't fit into the number of bits for the source of
2127 // the sign extension, it is impossible for both sides to be equal.
2128 if (C1.getMinSignedBits() > ExtSrcTyBits)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2129 return DAG.getConstant(Cond == ISD::SETNE, VT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2130
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2131 SDValue ZextOp;
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2132 EVT Op0Ty = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2133 if (Op0Ty == ExtSrcTy) {
2134 ZextOp = N0.getOperand(0);
2135 } else {
2136 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2137 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2138 DAG.getConstant(Imm, Op0Ty));
2139 }
2140 if (!DCI.isCalledByLegalizer())
2141 DCI.AddToWorklist(ZextOp.getNode());
2142 // Otherwise, make this a use of a zext.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2143 return DAG.getSetCC(dl, VT, ZextOp,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2144 DAG.getConstant(C1 & APInt::getLowBitsSet(
2145 ExtDstTyBits,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2146 ExtSrcTyBits),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2147 ExtDstTy),
2148 Cond);
2149 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2150 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2151 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2152 if (N0.getOpcode() == ISD::SETCC &&
2153 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2154 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2155 if (TrueWhenTrue)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2156 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2157 // Invert the condition.
2158 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2159 CC = ISD::getSetCCInverse(CC,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2160 N0.getOperand(0).getValueType().isInteger());
2161 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2162 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2163
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2164 if ((N0.getOpcode() == ISD::XOR ||
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2165 (N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2166 N0.getOperand(0).getOpcode() == ISD::XOR &&
2167 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2168 isa<ConstantSDNode>(N0.getOperand(1)) &&
2169 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2170 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2171 // can only do this if the top bits are known zero.
2172 unsigned BitWidth = N0.getValueSizeInBits();
2173 if (DAG.MaskedValueIsZero(N0,
2174 APInt::getHighBitsSet(BitWidth,
2175 BitWidth-1))) {
2176 // Okay, get the un-inverted input value.
2177 SDValue Val;
2178 if (N0.getOpcode() == ISD::XOR)
2179 Val = N0.getOperand(0);
2180 else {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2181 assert(N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2182 N0.getOperand(0).getOpcode() == ISD::XOR);
2183 // ((X^1)&1)^1 -> X & 1
2184 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2185 N0.getOperand(0).getOperand(0),
2186 N0.getOperand(1));
2187 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2188
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2189 return DAG.getSetCC(dl, VT, Val, N1,
2190 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2191 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2192 } else if (N1C->getAPIntValue() == 1 &&
2193 (VT == MVT::i1 ||
2194 getBooleanContents() == ZeroOrOneBooleanContent)) {
2195 SDValue Op0 = N0;
2196 if (Op0.getOpcode() == ISD::TRUNCATE)
2197 Op0 = Op0.getOperand(0);
2198
2199 if ((Op0.getOpcode() == ISD::XOR) &&
2200 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2201 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2202 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2203 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2204 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2205 Cond);
2206 } else if (Op0.getOpcode() == ISD::AND &&
2207 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2208 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2209 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2210 if (Op0.getValueType().bitsGT(VT))
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2211 Op0 = DAG.getNode(ISD::AND, dl, VT,
2212 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2213 DAG.getConstant(1, VT));
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2214 else if (Op0.getValueType().bitsLT(VT))
2215 Op0 = DAG.getNode(ISD::AND, dl, VT,
2216 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2217 DAG.getConstant(1, VT));
2218
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2219 return DAG.getSetCC(dl, VT, Op0,
2220 DAG.getConstant(0, Op0.getValueType()),
2221 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2222 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2223 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2224 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2225
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2226 APInt MinVal, MaxVal;
2227 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2228 if (ISD::isSignedIntSetCC(Cond)) {
2229 MinVal = APInt::getSignedMinValue(OperandBitSize);
2230 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2231 } else {
2232 MinVal = APInt::getMinValue(OperandBitSize);
2233 MaxVal = APInt::getMaxValue(OperandBitSize);
2234 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2235
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2236 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2237 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2238 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2239 // X >= C0 --> X > (C0-1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2240 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2241 DAG.getConstant(C1-1, N1.getValueType()),
2242 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2243 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2244
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2245 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2246 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2247 // X <= C0 --> X < (C0+1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2248 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2249 DAG.getConstant(C1+1, N1.getValueType()),
2250 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2251 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2252
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2253 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2254 return DAG.getConstant(0, VT); // X < MIN --> false
2255 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2256 return DAG.getConstant(1, VT); // X >= MIN --> true
2257 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2258 return DAG.getConstant(0, VT); // X > MAX --> false
2259 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2260 return DAG.getConstant(1, VT); // X <= MAX --> true
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2261
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2262 // Canonicalize setgt X, Min --> setne X, Min
2263 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2264 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2265 // Canonicalize setlt X, Max --> setne X, Max
2266 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2267 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2268
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2269 // If we have setult X, 1, turn it into seteq X, 0
2270 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2271 return DAG.getSetCC(dl, VT, N0,
2272 DAG.getConstant(MinVal, N0.getValueType()),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2273 ISD::SETEQ);
2274 // If we have setugt X, Max-1, turn it into seteq X, Max
2275 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2276 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2277 DAG.getConstant(MaxVal, N0.getValueType()),
2278 ISD::SETEQ);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2279
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2280 // If we have "setcc X, C0", check to see if we can shrink the immediate
2281 // by changing cc.
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2282
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2283 // SETUGT X, SINTMAX -> SETLT X, 0
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2284 if (Cond == ISD::SETUGT &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2285 C1 == APInt::getSignedMaxValue(OperandBitSize))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2286 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2287 DAG.getConstant(0, N1.getValueType()),
2288 ISD::SETLT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2289
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2290 // SETULT X, SINTMIN -> SETGT X, -1
2291 if (Cond == ISD::SETULT &&
2292 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2293 SDValue ConstMinusOne =
2294 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2295 N1.getValueType());
2296 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2297 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2298
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2299 // Fold bit comparisons when we can.
2300 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2301 (VT == N0.getValueType() ||
2302 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2303 N0.getOpcode() == ISD::AND)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2304 if (ConstantSDNode *AndRHS =
2305 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2306 EVT ShiftTy = DCI.isBeforeLegalize() ?
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2307 getPointerTy() : getShiftAmountTy(N0.getValueType());
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2308 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2309 // Perform the xform if the AND RHS is a single bit.
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2310 if (AndRHS->getAPIntValue().isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2311 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2312 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2313 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2314 }
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2315 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2316 // (X & 8) == 8 --> (X & 8) >> 3
2317 // Perform the xform if C1 is a single bit.
2318 if (C1.isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2319 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2320 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2321 DAG.getConstant(C1.logBase2(), ShiftTy)));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2322 }
2323 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2324 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2325 }
2326
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2327 if (isa<ConstantFPSDNode>(N0.getNode())) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2328 // Constant fold or commute setcc.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2329 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2330 if (O.getNode()) return O;
2331 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2332 // If the RHS of an FP comparison is a constant, simplify it away in
2333 // some cases.
2334 if (CFP->getValueAPF().isNaN()) {
2335 // If an operand is known to be a nan, we can fold it.
2336 switch (ISD::getUnorderedFlavor(Cond)) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2337 default: llvm_unreachable("Unknown flavor!");
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2338 case 0: // Known false.
2339 return DAG.getConstant(0, VT);
2340 case 1: // Known true.
2341 return DAG.getConstant(1, VT);
Chris Lattner1c3e1e22007-12-30 21:21:10 +0000[diff] [blame]2342 case 2: // Undefined.
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]2343 return DAG.getUNDEF(VT);
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2344 }
2345 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2346
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2347 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2348 // constant if knowing that the operand is non-nan is enough. We prefer to
2349 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2350 // materialize 0.0.
2351 if (Cond == ISD::SETO || Cond == ISD::SETUO)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2352 return DAG.getSetCC(dl, VT, N0, N0, Cond);
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2353
2354 // If the condition is not legal, see if we can find an equivalent one
2355 // which is legal.
2356 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2357 // If the comparison was an awkward floating-point == or != and one of
2358 // the comparison operands is infinity or negative infinity, convert the
2359 // condition to a less-awkward <= or >=.
2360 if (CFP->getValueAPF().isInfinity()) {
2361 if (CFP->getValueAPF().isNegative()) {
2362 if (Cond == ISD::SETOEQ &&
2363 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2364 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2365 if (Cond == ISD::SETUEQ &&
2366 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2367 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2368 if (Cond == ISD::SETUNE &&
2369 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2370 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2371 if (Cond == ISD::SETONE &&
2372 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2373 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2374 } else {
2375 if (Cond == ISD::SETOEQ &&
2376 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2377 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2378 if (Cond == ISD::SETUEQ &&
2379 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2380 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2381 if (Cond == ISD::SETUNE &&
2382 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2383 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2384 if (Cond == ISD::SETONE &&
2385 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2386 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2387 }
2388 }
2389 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2390 }
2391
2392 if (N0 == N1) {
2393 // We can always fold X == X for integer setcc's.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2394 if (N0.getValueType().isInteger())
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2395 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2396 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2397 if (UOF == 2) // FP operators that are undefined on NaNs.
2398 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2399 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2400 return DAG.getConstant(UOF, VT);
2401 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2402 // if it is not already.
2403 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2404 if (NewCond != Cond)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2405 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2406 }
2407
2408 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2409 N0.getValueType().isInteger()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2410 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2411 N0.getOpcode() == ISD::XOR) {
2412 // Simplify (X+Y) == (X+Z) --> Y == Z
2413 if (N0.getOpcode() == N1.getOpcode()) {
2414 if (N0.getOperand(0) == N1.getOperand(0))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2415 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2416 if (N0.getOperand(1) == N1.getOperand(1))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2417 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2418 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2419 // If X op Y == Y op X, try other combinations.
2420 if (N0.getOperand(0) == N1.getOperand(1))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2421 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2422 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2423 if (N0.getOperand(1) == N1.getOperand(0))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2424 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2425 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2426 }
2427 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2428
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2429 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2430 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2431 // Turn (X+C1) == C2 --> X == C2-C1
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2432 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2433 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2434 DAG.getConstant(RHSC->getAPIntValue()-
2435 LHSR->getAPIntValue(),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2436 N0.getValueType()), Cond);
2437 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2438
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2439 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2440 if (N0.getOpcode() == ISD::XOR)
2441 // If we know that all of the inverted bits are zero, don't bother
2442 // performing the inversion.
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2443 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2444 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2445 DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2446 DAG.getConstant(LHSR->getAPIntValue() ^
2447 RHSC->getAPIntValue(),
2448 N0.getValueType()),
2449 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2450 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2451
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2452 // Turn (C1-X) == C2 --> X == C1-C2
2453 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2454 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2455 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2456 DAG.getSetCC(dl, VT, N0.getOperand(1),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2457 DAG.getConstant(SUBC->getAPIntValue() -
2458 RHSC->getAPIntValue(),
2459 N0.getValueType()),
2460 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2461 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2462 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2463 }
2464
2465 // Simplify (X+Z) == X --> Z == 0
2466 if (N0.getOperand(0) == N1)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2467 return DAG.getSetCC(dl, VT, N0.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2468 DAG.getConstant(0, N0.getValueType()), Cond);
2469 if (N0.getOperand(1) == N1) {
2470 if (DAG.isCommutativeBinOp(N0.getOpcode()))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2471 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2472 DAG.getConstant(0, N0.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2473 else if (N0.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2474 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2475 // (Z-X) == X --> Z == X<<1
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2476 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2477 N1,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2478 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2479 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2480 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2481 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2482 }
2483 }
2484 }
2485
2486 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2487 N1.getOpcode() == ISD::XOR) {
2488 // Simplify X == (X+Z) --> Z == 0
2489 if (N1.getOperand(0) == N0) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2490 return DAG.getSetCC(dl, VT, N1.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2491 DAG.getConstant(0, N1.getValueType()), Cond);
2492 } else if (N1.getOperand(1) == N0) {
2493 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2494 return DAG.getSetCC(dl, VT, N1.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2495 DAG.getConstant(0, N1.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2496 } else if (N1.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2497 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2498 // X == (Z-X) --> X<<1 == Z
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2499 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2500 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2501 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2502 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2503 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2504 }
2505 }
2506 }
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2507
Dan Gohman2c65c3d2009-01-29 16:18:12 +0000[diff] [blame]2508 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2509 // Note that where y is variable and is known to have at most
2510 // one bit set (for example, if it is z&1) we cannot do this;
2511 // the expressions are not equivalent when y==0.
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2512 if (N0.getOpcode() == ISD::AND)
2513 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2514 if (ValueHasExactlyOneBitSet(N1, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2515 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2516 SDValue Zero = DAG.getConstant(0, N1.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2517 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2518 }
2519 }
2520 if (N1.getOpcode() == ISD::AND)
2521 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2522 if (ValueHasExactlyOneBitSet(N0, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2523 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2524 SDValue Zero = DAG.getConstant(0, N0.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2525 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2526 }
2527 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2528 }
2529
2530 // Fold away ALL boolean setcc's.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2531 SDValue Temp;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2532 if (N0.getValueType() == MVT::i1 && foldBooleans) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2533 switch (Cond) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2534 default: llvm_unreachable("Unknown integer setcc!");
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2535 case ISD::SETEQ: // X == Y -> ~(X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2536 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2537 N0 = DAG.getNOT(dl, Temp, MVT::i1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2538 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2539 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2540 break;
2541 case ISD::SETNE: // X != Y --> (X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2542 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2543 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2544 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2545 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2546 Temp = DAG.getNOT(dl, N0, MVT::i1);
2547 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2548 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2549 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2550 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2551 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2552 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2553 Temp = DAG.getNOT(dl, N1, MVT::i1);
2554 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2555 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2556 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2557 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2558 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2559 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2560 Temp = DAG.getNOT(dl, N0, MVT::i1);
2561 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2562 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2563 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2564 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2565 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2566 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2567 Temp = DAG.getNOT(dl, N1, MVT::i1);
2568 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2569 break;
2570 }
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2571 if (VT != MVT::i1) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2572 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2573 DCI.AddToWorklist(N0.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2574 // FIXME: If running after legalize, we probably can't do this.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2575 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2576 }
2577 return N0;
2578 }
2579
2580 // Could not fold it.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2581 return SDValue();
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2582}
2583
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2584/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2585/// node is a GlobalAddress + offset.
Chris Lattner0a9481f2011-02-13 22:25:43 +0000[diff] [blame]2586bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2587 int64_t &Offset) const {
2588 if (isa<GlobalAddressSDNode>(N)) {
Dan Gohman9ea3f562008-06-09 22:05:52 +0000[diff] [blame]2589 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2590 GA = GASD->getGlobal();
2591 Offset += GASD->getOffset();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2592 return true;
2593 }
2594
2595 if (N->getOpcode() == ISD::ADD) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2596 SDValue N1 = N->getOperand(0);
2597 SDValue N2 = N->getOperand(1);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2598 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2599 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2600 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2601 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2602 return true;
2603 }
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2604 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2605 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2606 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2607 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2608 return true;
2609 }
2610 }
2611 }
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2612
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2613 return false;
2614}
2615
2616
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2617SDValue TargetLowering::
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2618PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2619 // Default implementation: no optimization.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2620 return SDValue();
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2621}
2622
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2623//===----------------------------------------------------------------------===//
2624// Inline Assembler Implementation Methods
2625//===----------------------------------------------------------------------===//
2626
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2627
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2628TargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2629TargetLowering::getConstraintType(const std::string &Constraint) const {
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2630 if (Constraint.size() == 1) {
2631 switch (Constraint[0]) {
2632 default: break;
2633 case 'r': return C_RegisterClass;
2634 case 'm': // memory
2635 case 'o': // offsetable
2636 case 'V': // not offsetable
2637 return C_Memory;
2638 case 'i': // Simple Integer or Relocatable Constant
2639 case 'n': // Simple Integer
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2640 case 'E': // Floating Point Constant
2641 case 'F': // Floating Point Constant
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2642 case 's': // Relocatable Constant
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2643 case 'p': // Address.
Chris Lattnerc13dd1c2007-03-25 04:35:41 +0000[diff] [blame]2644 case 'X': // Allow ANY value.
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2645 case 'I': // Target registers.
2646 case 'J':
2647 case 'K':
2648 case 'L':
2649 case 'M':
2650 case 'N':
2651 case 'O':
2652 case 'P':
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2653 case '<':
2654 case '>':
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2655 return C_Other;
2656 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2657 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2658
2659 if (Constraint.size() > 1 && Constraint[0] == '{' &&
Chris Lattner065421f2007-03-25 02:18:14 +0000[diff] [blame]2660 Constraint[Constraint.size()-1] == '}')
2661 return C_Register;
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2662 return C_Unknown;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2663}
2664
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2665/// LowerXConstraint - try to replace an X constraint, which matches anything,
2666/// with another that has more specific requirements based on the type of the
2667/// corresponding operand.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2668const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2669 if (ConstraintVT.isInteger())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2670 return "r";
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2671 if (ConstraintVT.isFloatingPoint())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2672 return "f"; // works for many targets
2673 return 0;
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2674}
2675
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2676/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2677/// vector. If it is invalid, don't add anything to Ops.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2678void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2679 std::string &Constraint,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2680 std::vector<SDValue> &Ops,
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2681 SelectionDAG &DAG) const {
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2682
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2683 if (Constraint.length() > 1) return;
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2684
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2685 char ConstraintLetter = Constraint[0];
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2686 switch (ConstraintLetter) {
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2687 default: break;
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2688 case 'X': // Allows any operand; labels (basic block) use this.
2689 if (Op.getOpcode() == ISD::BasicBlock) {
2690 Ops.push_back(Op);
2691 return;
2692 }
2693 // fall through
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2694 case 'i': // Simple Integer or Relocatable Constant
2695 case 'n': // Simple Integer
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2696 case 's': { // Relocatable Constant
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2697 // These operands are interested in values of the form (GV+C), where C may
2698 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2699 // is possible and fine if either GV or C are missing.
2700 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2701 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2702
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2703 // If we have "(add GV, C)", pull out GV/C
2704 if (Op.getOpcode() == ISD::ADD) {
2705 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2706 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2707 if (C == 0 || GA == 0) {
2708 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2709 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2710 }
2711 if (C == 0 || GA == 0)
2712 C = 0, GA = 0;
2713 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2714
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2715 // If we find a valid operand, map to the TargetXXX version so that the
2716 // value itself doesn't get selected.
2717 if (GA) { // Either &GV or &GV+C
2718 if (ConstraintLetter != 'n') {
2719 int64_t Offs = GA->getOffset();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2720 if (C) Offs += C->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2721 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
Devang Patel07538ad2010-07-15 18:45:27 +0000[diff] [blame]2722 C ? C->getDebugLoc() : DebugLoc(),
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2723 Op.getValueType(), Offs));
2724 return;
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2725 }
2726 }
2727 if (C) { // just C, no GV.
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2728 // Simple constants are not allowed for 's'.
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2729 if (ConstraintLetter != 's') {
Dale Johannesen78e3e522009-02-12 20:58:09 +0000[diff] [blame]2730 // gcc prints these as sign extended. Sign extend value to 64 bits
2731 // now; without this it would get ZExt'd later in
2732 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2733 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2734 MVT::i64));
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2735 return;
2736 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2737 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2738 break;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2739 }
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2740 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2741}
2742
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2743std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
Chris Lattner4217ca8dc2006-02-21 23:11:00 +0000[diff] [blame]2744getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2745 EVT VT) const {
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2746 if (Constraint[0] != '{')
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2747 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
Chris Lattnera55079a2006-02-01 01:29:47 +0000[diff] [blame]2748 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2749
2750 // Remove the braces from around the name.
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2751 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2752
2753 // Figure out which register class contains this reg.
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]2754 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2755 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2756 E = RI->regclass_end(); RCI != E; ++RCI) {
2757 const TargetRegisterClass *RC = *RCI;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2758
2759 // If none of the value types for this register class are valid, we
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]2760 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2761 bool isLegal = false;
2762 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2763 I != E; ++I) {
2764 if (isTypeLegal(*I)) {
2765 isLegal = true;
2766 break;
2767 }
2768 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2769
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]2770 if (!isLegal) continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2771
2772 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2773 I != E; ++I) {
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2774 if (RegName.equals_lower(RI->getName(*I)))
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2775 return std::make_pair(*I, RC);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2776 }
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2777 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2778
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2779 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2780}
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]2781
2782//===----------------------------------------------------------------------===//
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2783// Constraint Selection.
2784
Chris Lattner6bdcda32008-10-17 16:47:46 +0000[diff] [blame]2785/// isMatchingInputConstraint - Return true of this is an input operand that is
2786/// a matching constraint like "4".
2787bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]2788 assert(!ConstraintCode.empty() && "No known constraint!");
2789 return isdigit(ConstraintCode[0]);
2790}
2791
2792/// getMatchedOperand - If this is an input matching constraint, this method
2793/// returns the output operand it matches.
2794unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2795 assert(!ConstraintCode.empty() && "No known constraint!");
2796 return atoi(ConstraintCode.c_str());
2797}
2798
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2799
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2800/// ParseConstraints - Split up the constraint string from the inline
2801/// assembly value into the specific constraints and their prefixes,
2802/// and also tie in the associated operand values.
2803/// If this returns an empty vector, and if the constraint string itself
2804/// isn't empty, there was an error parsing.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2805TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2806 ImmutableCallSite CS) const {
2807 /// ConstraintOperands - Information about all of the constraints.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2808 AsmOperandInfoVector ConstraintOperands;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2809 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2810 unsigned maCount = 0; // Largest number of multiple alternative constraints.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2811
2812 // Do a prepass over the constraints, canonicalizing them, and building up the
2813 // ConstraintOperands list.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2814 InlineAsm::ConstraintInfoVector
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2815 ConstraintInfos = IA->ParseConstraints();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2816
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2817 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2818 unsigned ResNo = 0; // ResNo - The result number of the next output.
2819
2820 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2821 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2822 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2823
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2824 // Update multiple alternative constraint count.
2825 if (OpInfo.multipleAlternatives.size() > maCount)
2826 maCount = OpInfo.multipleAlternatives.size();
2827
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2828 OpInfo.ConstraintVT = MVT::Other;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2829
2830 // Compute the value type for each operand.
2831 switch (OpInfo.Type) {
2832 case InlineAsm::isOutput:
2833 // Indirect outputs just consume an argument.
2834 if (OpInfo.isIndirect) {
2835 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2836 break;
2837 }
2838
2839 // The return value of the call is this value. As such, there is no
2840 // corresponding argument.
2841 assert(!CS.getType()->isVoidTy() &&
2842 "Bad inline asm!");
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2843 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2844 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2845 } else {
2846 assert(ResNo == 0 && "Asm only has one result!");
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2847 OpInfo.ConstraintVT = getValueType(CS.getType());
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2848 }
2849 ++ResNo;
2850 break;
2851 case InlineAsm::isInput:
2852 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2853 break;
2854 case InlineAsm::isClobber:
2855 // Nothing to do.
2856 break;
2857 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2858
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2859 if (OpInfo.CallOperandVal) {
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2860 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2861 if (OpInfo.isIndirect) {
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2862 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2863 if (!PtrTy)
2864 report_fatal_error("Indirect operand for inline asm not a pointer!");
2865 OpTy = PtrTy->getElementType();
2866 }
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2867
Eric Christophercef81b72011-05-09 20:04:43 +0000[diff] [blame]2868 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2869 if (StructType *STy = dyn_cast<StructType>(OpTy))
Eric Christophercef81b72011-05-09 20:04:43 +0000[diff] [blame]2870 if (STy->getNumElements() == 1)
2871 OpTy = STy->getElementType(0);
2872
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2873 // If OpTy is not a single value, it may be a struct/union that we
2874 // can tile with integers.
2875 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2876 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2877 switch (BitSize) {
2878 default: break;
2879 case 1:
2880 case 8:
2881 case 16:
2882 case 32:
2883 case 64:
2884 case 128:
Dale Johannesen71365d32010-11-09 01:15:07 +0000[diff] [blame]2885 OpInfo.ConstraintVT =
2886 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2887 break;
2888 }
2889 } else if (dyn_cast<PointerType>(OpTy)) {
2890 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
2891 } else {
2892 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2893 }
2894 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2895 }
2896
2897 // If we have multiple alternative constraints, select the best alternative.
2898 if (ConstraintInfos.size()) {
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2899 if (maCount) {
2900 unsigned bestMAIndex = 0;
2901 int bestWeight = -1;
2902 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2903 int weight = -1;
2904 unsigned maIndex;
2905 // Compute the sums of the weights for each alternative, keeping track
2906 // of the best (highest weight) one so far.
2907 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2908 int weightSum = 0;
2909 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2910 cIndex != eIndex; ++cIndex) {
2911 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2912 if (OpInfo.Type == InlineAsm::isClobber)
2913 continue;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2914
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2915 // If this is an output operand with a matching input operand,
2916 // look up the matching input. If their types mismatch, e.g. one
2917 // is an integer, the other is floating point, or their sizes are
2918 // different, flag it as an maCantMatch.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2919 if (OpInfo.hasMatchingInput()) {
2920 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2921 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2922 if ((OpInfo.ConstraintVT.isInteger() !=
2923 Input.ConstraintVT.isInteger()) ||
2924 (OpInfo.ConstraintVT.getSizeInBits() !=
2925 Input.ConstraintVT.getSizeInBits())) {
2926 weightSum = -1; // Can't match.
2927 break;
2928 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2929 }
2930 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2931 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2932 if (weight == -1) {
2933 weightSum = -1;
2934 break;
2935 }
2936 weightSum += weight;
2937 }
2938 // Update best.
2939 if (weightSum > bestWeight) {
2940 bestWeight = weightSum;
2941 bestMAIndex = maIndex;
2942 }
2943 }
2944
2945 // Now select chosen alternative in each constraint.
2946 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2947 cIndex != eIndex; ++cIndex) {
2948 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2949 if (cInfo.Type == InlineAsm::isClobber)
2950 continue;
2951 cInfo.selectAlternative(bestMAIndex);
2952 }
2953 }
2954 }
2955
2956 // Check and hook up tied operands, choose constraint code to use.
2957 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2958 cIndex != eIndex; ++cIndex) {
2959 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2960
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2961 // If this is an output operand with a matching input operand, look up the
2962 // matching input. If their types mismatch, e.g. one is an integer, the
2963 // other is floating point, or their sizes are different, flag it as an
2964 // error.
2965 if (OpInfo.hasMatchingInput()) {
2966 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2967
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2968 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
Eric Christopher5427ede2011-07-14 20:13:52 +0000[diff] [blame]2969 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
2970 getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT);
2971 std::pair<unsigned, const TargetRegisterClass*> InputRC =
2972 getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT);
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2973 if ((OpInfo.ConstraintVT.isInteger() !=
2974 Input.ConstraintVT.isInteger()) ||
Eric Christopher5427ede2011-07-14 20:13:52 +0000[diff] [blame]2975 (MatchRC.second != InputRC.second)) {
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2976 report_fatal_error("Unsupported asm: input constraint"
2977 " with a matching output constraint of"
2978 " incompatible type!");
2979 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2980 }
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2981
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2982 }
2983 }
2984
2985 return ConstraintOperands;
2986}
2987
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]2988
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2989/// getConstraintGenerality - Return an integer indicating how general CT
2990/// is.
2991static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2992 switch (CT) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2993 default: llvm_unreachable("Unknown constraint type!");
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2994 case TargetLowering::C_Other:
2995 case TargetLowering::C_Unknown:
2996 return 0;
2997 case TargetLowering::C_Register:
2998 return 1;
2999 case TargetLowering::C_RegisterClass:
3000 return 2;
3001 case TargetLowering::C_Memory:
3002 return 3;
3003 }
3004}
3005
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3006/// Examine constraint type and operand type and determine a weight value.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3007/// This object must already have been set up with the operand type
3008/// and the current alternative constraint selected.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3009TargetLowering::ConstraintWeight
3010 TargetLowering::getMultipleConstraintMatchWeight(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3011 AsmOperandInfo &info, int maIndex) const {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3012 InlineAsm::ConstraintCodeVector *rCodes;
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]3013 if (maIndex >= (int)info.multipleAlternatives.size())
3014 rCodes = &info.Codes;
3015 else
3016 rCodes = &info.multipleAlternatives[maIndex].Codes;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3017 ConstraintWeight BestWeight = CW_Invalid;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3018
3019 // Loop over the options, keeping track of the most general one.
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]3020 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3021 ConstraintWeight weight =
3022 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3023 if (weight > BestWeight)
3024 BestWeight = weight;
3025 }
3026
3027 return BestWeight;
3028}
3029
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3030/// Examine constraint type and operand type and determine a weight value.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3031/// This object must already have been set up with the operand type
3032/// and the current alternative constraint selected.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3033TargetLowering::ConstraintWeight
3034 TargetLowering::getSingleConstraintMatchWeight(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3035 AsmOperandInfo &info, const char *constraint) const {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3036 ConstraintWeight weight = CW_Invalid;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3037 Value *CallOperandVal = info.CallOperandVal;
3038 // If we don't have a value, we can't do a match,
3039 // but allow it at the lowest weight.
3040 if (CallOperandVal == NULL)
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3041 return CW_Default;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3042 // Look at the constraint type.
3043 switch (*constraint) {
3044 case 'i': // immediate integer.
3045 case 'n': // immediate integer with a known value.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3046 if (isa<ConstantInt>(CallOperandVal))
3047 weight = CW_Constant;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3048 break;
3049 case 's': // non-explicit intregal immediate.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3050 if (isa<GlobalValue>(CallOperandVal))
3051 weight = CW_Constant;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3052 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3053 case 'E': // immediate float if host format.
3054 case 'F': // immediate float.
3055 if (isa<ConstantFP>(CallOperandVal))
3056 weight = CW_Constant;
3057 break;
3058 case '<': // memory operand with autodecrement.
3059 case '>': // memory operand with autoincrement.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3060 case 'm': // memory operand.
3061 case 'o': // offsettable memory operand
3062 case 'V': // non-offsettable memory operand
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3063 weight = CW_Memory;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3064 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3065 case 'r': // general register.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3066 case 'g': // general register, memory operand or immediate integer.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3067 // note: Clang converts "g" to "imr".
3068 if (CallOperandVal->getType()->isIntegerTy())
3069 weight = CW_Register;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3070 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3071 case 'X': // any operand.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3072 default:
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3073 weight = CW_Default;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3074 break;
3075 }
3076 return weight;
3077}
3078
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3079/// ChooseConstraint - If there are multiple different constraints that we
3080/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
Chris Lattner24e1a9d2008-04-27 01:49:46 +0000[diff] [blame]3081/// This is somewhat tricky: constraints fall into four classes:
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3082/// Other -> immediates and magic values
3083/// Register -> one specific register
3084/// RegisterClass -> a group of regs
3085/// Memory -> memory
3086/// Ideally, we would pick the most specific constraint possible: if we have
3087/// something that fits into a register, we would pick it. The problem here
3088/// is that if we have something that could either be in a register or in
3089/// memory that use of the register could cause selection of *other*
3090/// operands to fail: they might only succeed if we pick memory. Because of
3091/// this the heuristic we use is:
3092///
3093/// 1) If there is an 'other' constraint, and if the operand is valid for
3094/// that constraint, use it. This makes us take advantage of 'i'
3095/// constraints when available.
3096/// 2) Otherwise, pick the most general constraint present. This prefers
3097/// 'm' over 'r', for example.
3098///
3099static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]3100 const TargetLowering &TLI,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3101 SDValue Op, SelectionDAG *DAG) {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3102 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3103 unsigned BestIdx = 0;
3104 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3105 int BestGenerality = -1;
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3106
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3107 // Loop over the options, keeping track of the most general one.
3108 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3109 TargetLowering::ConstraintType CType =
3110 TLI.getConstraintType(OpInfo.Codes[i]);
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3111
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3112 // If this is an 'other' constraint, see if the operand is valid for it.
3113 // For example, on X86 we might have an 'rI' constraint. If the operand
3114 // is an integer in the range [0..31] we want to use I (saving a load
3115 // of a register), otherwise we must use 'r'.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3116 if (CType == TargetLowering::C_Other && Op.getNode()) {
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3117 assert(OpInfo.Codes[i].size() == 1 &&
3118 "Unhandled multi-letter 'other' constraint");
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3119 std::vector<SDValue> ResultOps;
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]3120 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3121 ResultOps, *DAG);
3122 if (!ResultOps.empty()) {
3123 BestType = CType;
3124 BestIdx = i;
3125 break;
3126 }
3127 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3128
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3129 // Things with matching constraints can only be registers, per gcc
3130 // documentation. This mainly affects "g" constraints.
3131 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3132 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3133
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3134 // This constraint letter is more general than the previous one, use it.
3135 int Generality = getConstraintGenerality(CType);
3136 if (Generality > BestGenerality) {
3137 BestType = CType;
3138 BestIdx = i;
3139 BestGenerality = Generality;
3140 }
3141 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3142
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3143 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3144 OpInfo.ConstraintType = BestType;
3145}
3146
3147/// ComputeConstraintToUse - Determines the constraint code and constraint
3148/// type to use for the specific AsmOperandInfo, setting
3149/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3150void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3151 SDValue Op,
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3152 SelectionDAG *DAG) const {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3153 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3154
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3155 // Single-letter constraints ('r') are very common.
3156 if (OpInfo.Codes.size() == 1) {
3157 OpInfo.ConstraintCode = OpInfo.Codes[0];
3158 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3159 } else {
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]3160 ChooseConstraint(OpInfo, *this, Op, DAG);
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3161 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3162
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3163 // 'X' matches anything.
3164 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3165 // Labels and constants are handled elsewhere ('X' is the only thing
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3166 // that matches labels). For Functions, the type here is the type of
Dale Johannesen5339c552009-07-20 23:27:39 +0000[diff] [blame]3167 // the result, which is not what we want to look at; leave them alone.
3168 Value *v = OpInfo.CallOperandVal;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3169 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3170 OpInfo.CallOperandVal = v;
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3171 return;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3172 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3173
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3174 // Otherwise, try to resolve it to something we know about by looking at
3175 // the actual operand type.
3176 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3177 OpInfo.ConstraintCode = Repl;
3178 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3179 }
3180 }
3181}
3182
3183//===----------------------------------------------------------------------===//
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]3184// Loop Strength Reduction hooks
3185//===----------------------------------------------------------------------===//
3186
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3187/// isLegalAddressingMode - Return true if the addressing mode represented
3188/// by AM is legal for this target, for a load/store of the specified type.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3189bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]3190 Type *Ty) const {
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3191 // The default implementation of this implements a conservative RISCy, r+r and
3192 // r+i addr mode.
3193
3194 // Allows a sign-extended 16-bit immediate field.
3195 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3196 return false;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3197
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3198 // No global is ever allowed as a base.
3199 if (AM.BaseGV)
3200 return false;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3201
3202 // Only support r+r,
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3203 switch (AM.Scale) {
3204 case 0: // "r+i" or just "i", depending on HasBaseReg.
3205 break;
3206 case 1:
3207 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3208 return false;
3209 // Otherwise we have r+r or r+i.
3210 break;
3211 case 2:
3212 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3213 return false;
3214 // Allow 2*r as r+r.
3215 break;
3216 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3217
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3218 return true;
3219}
3220
Benjamin Kramer9c640302011-07-08 10:31:30 +0000[diff] [blame]3221/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
3222/// with the multiplicative inverse of the constant.
3223SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
3224 SelectionDAG &DAG) const {
3225 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
3226 APInt d = C->getAPIntValue();
3227 assert(d != 0 && "Division by zero!");
3228
3229 // Shift the value upfront if it is even, so the LSB is one.
3230 unsigned ShAmt = d.countTrailingZeros();
3231 if (ShAmt) {
3232 // TODO: For UDIV use SRL instead of SRA.
3233 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
3234 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3235 d = d.ashr(ShAmt);
3236 }
3237
3238 // Calculate the multiplicative inverse, using Newton's method.
3239 APInt t, xn = d;
3240 while ((t = d*xn) != 1)
3241 xn *= APInt(d.getBitWidth(), 2) - t;
3242
3243 Op2 = DAG.getConstant(xn, Op1.getValueType());
3244 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3245}
3246
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3247/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3248/// return a DAG expression to select that will generate the same value by
3249/// multiplying by a magic number. See:
3250/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3251SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3252 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]3253 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3254 DebugLoc dl= N->getDebugLoc();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3255
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3256 // Check to see if we can do this.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3257 // FIXME: We should be more aggressive here.
3258 if (!isTypeLegal(VT))
3259 return SDValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3260
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3261 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
Jay Foad4e5ea552009-04-30 10:15:35 +0000[diff] [blame]3262 APInt::ms magics = d.magic();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3263
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3264 // Multiply the numerator (operand 0) by the magic value
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3265 // FIXME: We should support doing a MUL in a wider type
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3266 SDValue Q;
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]3267 if (isOperationLegalOrCustom(ISD::MULHS, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3268 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3269 DAG.getConstant(magics.m, VT));
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]3270 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3271 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3272 N->getOperand(0),
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3273 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3274 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3275 return SDValue(); // No mulhs or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3276 // If d > 0 and m < 0, add the numerator
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3277 if (d.isStrictlyPositive() && magics.m.isNegative()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3278 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3279 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3280 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3281 }
3282 // If d < 0 and m > 0, subtract the numerator.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3283 if (d.isNegative() && magics.m.isStrictlyPositive()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3284 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3285 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3286 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3287 }
3288 // Shift right algebraic if shift value is nonzero
3289 if (magics.s > 0) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3290 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3291 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3292 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3293 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3294 }
3295 // Extract the sign bit and add it to the quotient
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3296 SDValue T =
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3297 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3298 getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3299 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3300 Created->push_back(T.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3301 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3302}
3303
3304/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3305/// return a DAG expression to select that will generate the same value by
3306/// multiplying by a magic number. See:
3307/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3308SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
3309 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]3310 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3311 DebugLoc dl = N->getDebugLoc();
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3312
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3313 // Check to see if we can do this.
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3314 // FIXME: We should be more aggressive here.
3315 if (!isTypeLegal(VT))
3316 return SDValue();
3317
3318 // FIXME: We should use a narrower constant when the upper
3319 // bits are known to be zero.
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3320 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3321 APInt::mu magics = N1C.magicu();
3322
3323 SDValue Q = N->getOperand(0);
3324
3325 // If the divisor is even, we can avoid using the expensive fixup by shifting
3326 // the divided value upfront.
3327 if (magics.a != 0 && !N1C[0]) {
3328 unsigned Shift = N1C.countTrailingZeros();
3329 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3330 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3331 if (Created)
3332 Created->push_back(Q.getNode());
3333
3334 // Get magic number for the shifted divisor.
3335 magics = N1C.lshr(Shift).magicu(Shift);
3336 assert(magics.a == 0 && "Should use cheap fixup now");
3337 }
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3338
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3339 // Multiply the numerator (operand 0) by the magic value
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3340 // FIXME: We should support doing a MUL in a wider type
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]3341 if (isOperationLegalOrCustom(ISD::MULHU, VT))
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3342 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]3343 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3344 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3345 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3346 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3347 return SDValue(); // No mulhu or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3348 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3349 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3350
3351 if (magics.a == 0) {
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3352 assert(magics.s < N1C.getBitWidth() &&
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3353 "We shouldn't generate an undefined shift!");
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3354 return DAG.getNode(ISD::SRL, dl, VT, Q,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3355 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3356 } else {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3357 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3358 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3359 Created->push_back(NPQ.getNode());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3360 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3361 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3362 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3363 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3364 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3365 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3366 Created->push_back(NPQ.getNode());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3367 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3368 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3369 }
3370}