Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 1 | //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===// |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 2 | // |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 7 | // |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 10 | // This file contains the SPARC implementation of the MRegisterInfo class. |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 14 | #include "Sparc.h" |
| 15 | #include "SparcRegisterInfo.h" |
| 16 | #include "SparcSubtarget.h" |
Chris Lattner | e1274de | 2004-02-29 05:18:30 +0000 | [diff] [blame] | 17 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 18 | #include "llvm/CodeGen/MachineFunction.h" |
Brian Gaeke | 6c5526e | 2004-04-02 20:53:37 +0000 | [diff] [blame] | 19 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 20 | #include "llvm/CodeGen/MachineLocation.h" |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 21 | #include "llvm/Type.h" |
Brian Gaeke | 74dfcf1 | 2004-09-02 02:37:43 +0000 | [diff] [blame] | 22 | #include "llvm/ADT/STLExtras.h" |
Chris Lattner | 38343f6 | 2004-07-04 17:19:21 +0000 | [diff] [blame] | 23 | #include <iostream> |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 24 | using namespace llvm; |
| 25 | |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame^] | 26 | SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st, |
| 27 | const TargetInstrInfo &tii) |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 28 | : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame^] | 29 | Subtarget(st), TII(tii) { |
Chris Lattner | 69d3909 | 2006-02-04 06:58:46 +0000 | [diff] [blame] | 30 | } |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 31 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 32 | void SparcRegisterInfo:: |
Chris Lattner | 57f1b67 | 2004-08-15 21:56:44 +0000 | [diff] [blame] | 33 | storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 34 | unsigned SrcReg, int FI, |
Chris Lattner | 331355c | 2005-12-17 20:18:49 +0000 | [diff] [blame] | 35 | const TargetRegisterClass *RC) const { |
Brian Gaeke | 6713d98 | 2004-06-17 22:34:48 +0000 | [diff] [blame] | 36 | // On the order of operands here: think "[FrameIdx + 0] = SrcReg". |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 37 | if (RC == SP::IntRegsRegisterClass) |
| 38 | BuildMI(MBB, I, SP::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg); |
| 39 | else if (RC == SP::FPRegsRegisterClass) |
| 40 | BuildMI(MBB, I, SP::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg); |
| 41 | else if (RC == SP::DFPRegsRegisterClass) |
| 42 | BuildMI(MBB, I, SP::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg); |
Brian Gaeke | 6bd5551 | 2004-06-27 22:59:56 +0000 | [diff] [blame] | 43 | else |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 44 | assert(0 && "Can't store this register to stack slot"); |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 45 | } |
| 46 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 47 | void SparcRegisterInfo:: |
Chris Lattner | 57f1b67 | 2004-08-15 21:56:44 +0000 | [diff] [blame] | 48 | loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 49 | unsigned DestReg, int FI, |
Chris Lattner | 331355c | 2005-12-17 20:18:49 +0000 | [diff] [blame] | 50 | const TargetRegisterClass *RC) const { |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 51 | if (RC == SP::IntRegsRegisterClass) |
| 52 | BuildMI(MBB, I, SP::LDri, 2, DestReg).addFrameIndex(FI).addImm(0); |
| 53 | else if (RC == SP::FPRegsRegisterClass) |
| 54 | BuildMI(MBB, I, SP::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0); |
| 55 | else if (RC == SP::DFPRegsRegisterClass) |
| 56 | BuildMI(MBB, I, SP::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0); |
Brian Gaeke | 6bd5551 | 2004-06-27 22:59:56 +0000 | [diff] [blame] | 57 | else |
Chris Lattner | 01d0efb | 2004-08-15 22:15:11 +0000 | [diff] [blame] | 58 | assert(0 && "Can't load this register from stack slot"); |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 59 | } |
| 60 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 61 | void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, |
| 62 | MachineBasicBlock::iterator I, |
| 63 | unsigned DestReg, unsigned SrcReg, |
| 64 | const TargetRegisterClass *RC) const { |
| 65 | if (RC == SP::IntRegsRegisterClass) |
| 66 | BuildMI(MBB, I, SP::ORrr, 2, DestReg).addReg(SP::G0).addReg(SrcReg); |
| 67 | else if (RC == SP::FPRegsRegisterClass) |
| 68 | BuildMI(MBB, I, SP::FMOVS, 1, DestReg).addReg(SrcReg); |
| 69 | else if (RC == SP::DFPRegsRegisterClass) |
| 70 | BuildMI(MBB, I, Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD, |
Chris Lattner | 69d3909 | 2006-02-04 06:58:46 +0000 | [diff] [blame] | 71 | 1, DestReg).addReg(SrcReg); |
Brian Gaeke | 6bd5551 | 2004-06-27 22:59:56 +0000 | [diff] [blame] | 72 | else |
| 73 | assert (0 && "Can't copy this register"); |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 74 | } |
| 75 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 76 | MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI, |
| 77 | unsigned OpNum, |
| 78 | int FI) const { |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 79 | bool isFloat = false; |
| 80 | switch (MI->getOpcode()) { |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 81 | case SP::ORrr: |
| 82 | if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&& |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 83 | MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) { |
| 84 | if (OpNum == 0) // COPY -> STORE |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame^] | 85 | return BuildMI(TII, SP::STri, 3).addFrameIndex(FI).addImm(0) |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 86 | .addReg(MI->getOperand(2).getReg()); |
| 87 | else // COPY -> LOAD |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame^] | 88 | return BuildMI(TII, SP::LDri, 2, MI->getOperand(0).getReg()) |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 89 | .addFrameIndex(FI).addImm(0); |
| 90 | } |
| 91 | break; |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 92 | case SP::FMOVS: |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 93 | isFloat = true; |
| 94 | // FALLTHROUGH |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 95 | case SP::FMOVD: |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 96 | if (OpNum == 0) // COPY -> STORE |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame^] | 97 | return BuildMI(TII, isFloat ? SP::STFri : SP::STDFri, 3) |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 98 | .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg()); |
| 99 | else // COPY -> LOAD |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame^] | 100 | return BuildMI(TII, isFloat ? SP::LDFri : SP::LDDFri, 2, |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 101 | MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0); |
| 102 | break; |
| 103 | } |
| 104 | return 0; |
| 105 | } |
| 106 | |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 107 | const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const { |
| 108 | static const unsigned CalleeSaveRegs[] = { 0 }; |
| 109 | return CalleeSaveRegs; |
| 110 | } |
| 111 | |
| 112 | const TargetRegisterClass* const* |
| 113 | SparcRegisterInfo::getCalleeSaveRegClasses() const { |
| 114 | static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 }; |
| 115 | return CalleeSaveRegClasses; |
| 116 | } |
| 117 | |
| 118 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 119 | void SparcRegisterInfo:: |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 120 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 121 | MachineBasicBlock::iterator I) const { |
Brian Gaeke | 85c0835 | 2004-10-10 19:57:21 +0000 | [diff] [blame] | 122 | MachineInstr &MI = *I; |
Chris Lattner | 43875e6 | 2005-12-19 02:51:12 +0000 | [diff] [blame] | 123 | int Size = MI.getOperand(0).getImmedValue(); |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 124 | if (MI.getOpcode() == SP::ADJCALLSTACKDOWN) |
Chris Lattner | 43875e6 | 2005-12-19 02:51:12 +0000 | [diff] [blame] | 125 | Size = -Size; |
| 126 | if (Size) |
Chris Lattner | 63b3d71 | 2006-05-04 17:21:20 +0000 | [diff] [blame] | 127 | BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addImm(Size); |
Chris Lattner | 43875e6 | 2005-12-19 02:51:12 +0000 | [diff] [blame] | 128 | MBB.erase(I); |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | void |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 132 | SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { |
Brian Gaeke | 6c5526e | 2004-04-02 20:53:37 +0000 | [diff] [blame] | 133 | unsigned i = 0; |
| 134 | MachineInstr &MI = *II; |
| 135 | while (!MI.getOperand(i).isFrameIndex()) { |
| 136 | ++i; |
| 137 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 138 | } |
| 139 | |
| 140 | int FrameIndex = MI.getOperand(i).getFrameIndex(); |
| 141 | |
Brian Gaeke | 3a8ad62 | 2004-04-06 22:10:22 +0000 | [diff] [blame] | 142 | // Addressable stack objects are accessed using neg. offsets from %fp |
Chris Lattner | b8ce4c4 | 2004-08-14 22:57:22 +0000 | [diff] [blame] | 143 | MachineFunction &MF = *MI.getParent()->getParent(); |
Brian Gaeke | 3a8ad62 | 2004-04-06 22:10:22 +0000 | [diff] [blame] | 144 | int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + |
| 145 | MI.getOperand(i+1).getImmedValue(); |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 146 | |
| 147 | // Replace frame index with a frame pointer reference. |
| 148 | if (Offset >= -4096 && Offset <= 4095) { |
| 149 | // If the offset is small enough to fit in the immediate field, directly |
| 150 | // encode it. |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 151 | MI.getOperand(i).ChangeToRegister(SP::I6, false); |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 152 | MI.getOperand(i+1).ChangeToImmediate(Offset); |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 153 | } else { |
| 154 | // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to |
| 155 | // scavenge a register here instead of reserving G1 all of the time. |
| 156 | unsigned OffHi = (unsigned)Offset >> 10U; |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 157 | BuildMI(*MI.getParent(), II, SP::SETHIi, 1, SP::G1).addImm(OffHi); |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 158 | // Emit G1 = G1 + I6 |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 159 | BuildMI(*MI.getParent(), II, SP::ADDrr, 2, |
| 160 | SP::G1).addReg(SP::G1).addReg(SP::I6); |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 161 | // Insert: G1+%lo(offset) into the user. |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 162 | MI.getOperand(i).ChangeToRegister(SP::G1, false); |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 163 | MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1)); |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 164 | } |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 165 | } |
| 166 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 167 | void SparcRegisterInfo:: |
Chris Lattner | e1274de | 2004-02-29 05:18:30 +0000 | [diff] [blame] | 168 | processFunctionBeforeFrameFinalized(MachineFunction &MF) const {} |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 169 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 170 | void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const { |
Chris Lattner | e1274de | 2004-02-29 05:18:30 +0000 | [diff] [blame] | 171 | MachineBasicBlock &MBB = MF.front(); |
Brian Gaeke | 6c5526e | 2004-04-02 20:53:37 +0000 | [diff] [blame] | 172 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Chris Lattner | e1274de | 2004-02-29 05:18:30 +0000 | [diff] [blame] | 173 | |
Brian Gaeke | 6c5526e | 2004-04-02 20:53:37 +0000 | [diff] [blame] | 174 | // Get the number of bytes to allocate from the FrameInfo |
Brian Gaeke | ef8e48a | 2004-04-13 18:28:37 +0000 | [diff] [blame] | 175 | int NumBytes = (int) MFI->getStackSize(); |
Brian Gaeke | 6c5526e | 2004-04-02 20:53:37 +0000 | [diff] [blame] | 176 | |
Brian Gaeke | 85c0835 | 2004-10-10 19:57:21 +0000 | [diff] [blame] | 177 | // Emit the correct save instruction based on the number of bytes in |
| 178 | // the frame. Minimum stack frame size according to V8 ABI is: |
Brian Gaeke | 6c5526e | 2004-04-02 20:53:37 +0000 | [diff] [blame] | 179 | // 16 words for register window spill |
| 180 | // 1 word for address of returned aggregate-value |
| 181 | // + 6 words for passing parameters on the stack |
| 182 | // ---------- |
| 183 | // 23 words * 4 bytes per word = 92 bytes |
| 184 | NumBytes += 92; |
Brian Gaeke | 6713d98 | 2004-06-17 22:34:48 +0000 | [diff] [blame] | 185 | // Round up to next doubleword boundary -- a double-word boundary |
| 186 | // is required by the ABI. |
| 187 | NumBytes = (NumBytes + 7) & ~7; |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 188 | NumBytes = -NumBytes; |
| 189 | |
| 190 | if (NumBytes >= -4096) { |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 191 | BuildMI(MBB, MBB.begin(), SP::SAVEri, 2, |
| 192 | SP::O6).addImm(NumBytes).addReg(SP::O6); |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 193 | } else { |
| 194 | MachineBasicBlock::iterator InsertPt = MBB.begin(); |
| 195 | // Emit this the hard way. This clobbers G1 which we always know is |
| 196 | // available here. |
| 197 | unsigned OffHi = (unsigned)NumBytes >> 10U; |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 198 | BuildMI(MBB, InsertPt, SP::SETHIi, 1, SP::G1).addImm(OffHi); |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 199 | // Emit G1 = G1 + I6 |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 200 | BuildMI(MBB, InsertPt, SP::ORri, 2, SP::G1) |
| 201 | .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1)); |
| 202 | BuildMI(MBB, InsertPt, SP::SAVErr, 2, |
| 203 | SP::O6).addReg(SP::O6).addReg(SP::G1); |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 204 | } |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 205 | } |
| 206 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 207 | void SparcRegisterInfo::emitEpilogue(MachineFunction &MF, |
| 208 | MachineBasicBlock &MBB) const { |
Chris Lattner | e1274de | 2004-02-29 05:18:30 +0000 | [diff] [blame] | 209 | MachineBasicBlock::iterator MBBI = prior(MBB.end()); |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 210 | assert(MBBI->getOpcode() == SP::RETL && |
Brian Gaeke | d69b3c5 | 2004-03-06 05:31:21 +0000 | [diff] [blame] | 211 | "Can only put epilog before 'retl' instruction!"); |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 212 | BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0); |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 213 | } |
| 214 | |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 215 | unsigned SparcRegisterInfo::getRARegister() const { |
| 216 | assert(0 && "What is the return address register"); |
| 217 | return 0; |
| 218 | } |
| 219 | |
Jim Laskey | a997918 | 2006-03-28 13:48:33 +0000 | [diff] [blame] | 220 | unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const { |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 221 | assert(0 && "What is the frame register"); |
| 222 | return SP::G1; |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 223 | } |
| 224 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 225 | #include "SparcGenRegisterInfo.inc" |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 226 | |