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Evan Chengb9803a82009-11-06 23:52:48 +00001//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Bob Wilson656edcf2010-09-08 23:39:54 +000010// This file contains a pass that expands pseudo instructions into target
Evan Chengb9803a82009-11-06 23:52:48 +000011// instructions to allow proper scheduling, if-conversion, and other late
12// optimizations. This pass should be run after register allocation but before
Bob Wilson656edcf2010-09-08 23:39:54 +000013// the post-regalloc scheduling pass.
Evan Chengb9803a82009-11-06 23:52:48 +000014//
15//===----------------------------------------------------------------------===//
16
17#define DEBUG_TYPE "arm-pseudo"
18#include "ARM.h"
19#include "ARMBaseInstrInfo.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner4dbbe342010-07-20 21:17:29 +000022#include "llvm/Target/TargetRegisterInfo.h"
Evan Chengb9803a82009-11-06 23:52:48 +000023using namespace llvm;
24
25namespace {
26 class ARMExpandPseudo : public MachineFunctionPass {
27 public:
28 static char ID;
Owen Anderson90c579d2010-08-06 18:33:48 +000029 ARMExpandPseudo() : MachineFunctionPass(ID) {}
Evan Chengb9803a82009-11-06 23:52:48 +000030
31 const TargetInstrInfo *TII;
Evan Chengd929f772010-05-13 00:17:02 +000032 const TargetRegisterInfo *TRI;
Evan Chengb9803a82009-11-06 23:52:48 +000033
34 virtual bool runOnMachineFunction(MachineFunction &Fn);
35
36 virtual const char *getPassName() const {
37 return "ARM pseudo instruction expansion pass";
38 }
39
40 private:
Evan Cheng43130072010-05-12 23:13:12 +000041 void TransferImpOps(MachineInstr &OldMI,
42 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
Evan Chengb9803a82009-11-06 23:52:48 +000043 bool ExpandMBB(MachineBasicBlock &MBB);
Bob Wilson8466fa12010-09-13 23:01:35 +000044 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
45 void ExpandVST(MachineBasicBlock::iterator &MBBI);
46 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
Bob Wilsonbd916c52010-09-13 23:55:10 +000047 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
48 unsigned Opc, bool IsExt, unsigned NumRegs);
Evan Chengb9803a82009-11-06 23:52:48 +000049 };
50 char ARMExpandPseudo::ID = 0;
51}
52
Evan Cheng43130072010-05-12 23:13:12 +000053/// TransferImpOps - Transfer implicit operands on the pseudo instruction to
54/// the instructions created from the expansion.
55void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
56 MachineInstrBuilder &UseMI,
57 MachineInstrBuilder &DefMI) {
58 const TargetInstrDesc &Desc = OldMI.getDesc();
59 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
60 i != e; ++i) {
61 const MachineOperand &MO = OldMI.getOperand(i);
62 assert(MO.isReg() && MO.getReg());
63 if (MO.isUse())
Bob Wilson63569c92010-09-09 00:15:32 +000064 UseMI.addOperand(MO);
Evan Cheng43130072010-05-12 23:13:12 +000065 else
Bob Wilson63569c92010-09-09 00:15:32 +000066 DefMI.addOperand(MO);
Evan Cheng43130072010-05-12 23:13:12 +000067 }
68}
69
Bob Wilson8466fa12010-09-13 23:01:35 +000070namespace {
71 // Constants for register spacing in NEON load/store instructions.
72 // For quad-register load-lane and store-lane pseudo instructors, the
73 // spacing is initially assumed to be EvenDblSpc, and that is changed to
74 // OddDblSpc depending on the lane number operand.
75 enum NEONRegSpacing {
76 SingleSpc,
77 EvenDblSpc,
78 OddDblSpc
79 };
80
81 // Entries for NEON load/store information table. The table is sorted by
82 // PseudoOpc for fast binary-search lookups.
83 struct NEONLdStTableEntry {
84 unsigned PseudoOpc;
85 unsigned RealOpc;
86 bool IsLoad;
87 bool HasWriteBack;
88 NEONRegSpacing RegSpacing;
89 unsigned char NumRegs; // D registers loaded or stored
90 unsigned char RegElts; // elements per D register; used for lane ops
91
92 // Comparison methods for binary search of the table.
93 bool operator<(const NEONLdStTableEntry &TE) const {
94 return PseudoOpc < TE.PseudoOpc;
95 }
96 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
97 return TE.PseudoOpc < PseudoOpc;
98 }
99 friend bool ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
100 const NEONLdStTableEntry &TE) {
101 return PseudoOpc < TE.PseudoOpc;
102 }
103 };
104}
105
106static const NEONLdStTableEntry NEONLdStTable[] = {
107{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 },
108{ ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 },
109{ ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, SingleSpc, 3, 1 },
110{ ARM::VLD1d64TPseudo_UPD, ARM::VLD1d64T_UPD, true, true, SingleSpc, 3, 1 },
111
112{ ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, SingleSpc, 2, 4 },
113{ ARM::VLD1q16Pseudo_UPD, ARM::VLD1q16_UPD, true, true, SingleSpc, 2, 4 },
114{ ARM::VLD1q32Pseudo, ARM::VLD1q32, true, false, SingleSpc, 2, 2 },
115{ ARM::VLD1q32Pseudo_UPD, ARM::VLD1q32_UPD, true, true, SingleSpc, 2, 2 },
116{ ARM::VLD1q64Pseudo, ARM::VLD1q64, true, false, SingleSpc, 2, 1 },
117{ ARM::VLD1q64Pseudo_UPD, ARM::VLD1q64_UPD, true, true, SingleSpc, 2, 1 },
118{ ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, SingleSpc, 2, 8 },
119{ ARM::VLD1q8Pseudo_UPD, ARM::VLD1q8_UPD, true, true, SingleSpc, 2, 8 },
120
121{ ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, SingleSpc, 2, 4 },
122{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, SingleSpc, 2, 4 },
123{ ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, SingleSpc, 2, 2 },
124{ ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, SingleSpc, 2, 2 },
125{ ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, SingleSpc, 2, 8 },
126{ ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, SingleSpc, 2, 8 },
127{ ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, EvenDblSpc, 2, 4 },
128{ ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, EvenDblSpc, 2, 4 },
129{ ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, EvenDblSpc, 2, 2 },
130{ ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, EvenDblSpc, 2, 2 },
131
132{ ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, SingleSpc, 2, 4 },
133{ ARM::VLD2d16Pseudo_UPD, ARM::VLD2d16_UPD, true, true, SingleSpc, 2, 4 },
134{ ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, SingleSpc, 2, 2 },
135{ ARM::VLD2d32Pseudo_UPD, ARM::VLD2d32_UPD, true, true, SingleSpc, 2, 2 },
136{ ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, SingleSpc, 2, 8 },
137{ ARM::VLD2d8Pseudo_UPD, ARM::VLD2d8_UPD, true, true, SingleSpc, 2, 8 },
138
139{ ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, SingleSpc, 4, 4 },
140{ ARM::VLD2q16Pseudo_UPD, ARM::VLD2q16_UPD, true, true, SingleSpc, 4, 4 },
141{ ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, SingleSpc, 4, 2 },
142{ ARM::VLD2q32Pseudo_UPD, ARM::VLD2q32_UPD, true, true, SingleSpc, 4, 2 },
143{ ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, SingleSpc, 4, 8 },
144{ ARM::VLD2q8Pseudo_UPD, ARM::VLD2q8_UPD, true, true, SingleSpc, 4, 8 },
145
146{ ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, SingleSpc, 3, 4 },
147{ ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, SingleSpc, 3, 4 },
148{ ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, SingleSpc, 3, 2 },
149{ ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, SingleSpc, 3, 2 },
150{ ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, SingleSpc, 3, 8 },
151{ ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, SingleSpc, 3, 8 },
152{ ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, EvenDblSpc, 3, 4 },
153{ ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, EvenDblSpc, 3, 4 },
154{ ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, EvenDblSpc, 3, 2 },
155{ ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, EvenDblSpc, 3, 2 },
156
157{ ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, SingleSpc, 3, 4 },
158{ ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, SingleSpc, 3, 4 },
159{ ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, SingleSpc, 3, 2 },
160{ ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, SingleSpc, 3, 2 },
161{ ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, SingleSpc, 3, 8 },
162{ ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, SingleSpc, 3, 8 },
163
164{ ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, EvenDblSpc, 3, 4 },
165{ ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, OddDblSpc, 3, 4 },
166{ ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, EvenDblSpc, 3, 2 },
167{ ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, OddDblSpc, 3, 2 },
168{ ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, EvenDblSpc, 3, 8 },
169{ ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, OddDblSpc, 3, 8 },
170
171{ ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, SingleSpc, 4, 4 },
172{ ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, SingleSpc, 4, 4 },
173{ ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, SingleSpc, 4, 2 },
174{ ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, SingleSpc, 4, 2 },
175{ ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, SingleSpc, 4, 8 },
176{ ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, SingleSpc, 4, 8 },
177{ ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, EvenDblSpc, 4, 4 },
178{ ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, EvenDblSpc, 4, 4 },
179{ ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, EvenDblSpc, 4, 2 },
180{ ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, EvenDblSpc, 4, 2 },
181
182{ ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, SingleSpc, 4, 4 },
183{ ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, SingleSpc, 4, 4 },
184{ ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, SingleSpc, 4, 2 },
185{ ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, SingleSpc, 4, 2 },
186{ ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, SingleSpc, 4, 8 },
187{ ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, SingleSpc, 4, 8 },
188
189{ ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, EvenDblSpc, 4, 4 },
190{ ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, OddDblSpc, 4, 4 },
191{ ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, EvenDblSpc, 4, 2 },
192{ ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, OddDblSpc, 4, 2 },
193{ ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, EvenDblSpc, 4, 8 },
194{ ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, OddDblSpc, 4, 8 },
195
196{ ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, SingleSpc, 4, 1 },
197{ ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, SingleSpc, 4, 1 },
198{ ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, SingleSpc, 3, 1 },
199{ ARM::VST1d64TPseudo_UPD, ARM::VST1d64T_UPD, false, true, SingleSpc, 3, 1 },
200
201{ ARM::VST1q16Pseudo, ARM::VST1q16, false, false, SingleSpc, 2, 4 },
202{ ARM::VST1q16Pseudo_UPD, ARM::VST1q16_UPD, false, true, SingleSpc, 2, 4 },
203{ ARM::VST1q32Pseudo, ARM::VST1q32, false, false, SingleSpc, 2, 2 },
204{ ARM::VST1q32Pseudo_UPD, ARM::VST1q32_UPD, false, true, SingleSpc, 2, 2 },
205{ ARM::VST1q64Pseudo, ARM::VST1q64, false, false, SingleSpc, 2, 1 },
206{ ARM::VST1q64Pseudo_UPD, ARM::VST1q64_UPD, false, true, SingleSpc, 2, 1 },
207{ ARM::VST1q8Pseudo, ARM::VST1q8, false, false, SingleSpc, 2, 8 },
208{ ARM::VST1q8Pseudo_UPD, ARM::VST1q8_UPD, false, true, SingleSpc, 2, 8 },
209
210{ ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, SingleSpc, 2, 4 },
211{ ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, SingleSpc, 2, 4 },
212{ ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, SingleSpc, 2, 2 },
213{ ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, SingleSpc, 2, 2 },
214{ ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, SingleSpc, 2, 8 },
215{ ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, SingleSpc, 2, 8 },
216{ ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, EvenDblSpc, 2, 4},
217{ ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, EvenDblSpc, 2, 4},
218{ ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, EvenDblSpc, 2, 2},
219{ ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, EvenDblSpc, 2, 2},
220
221{ ARM::VST2d16Pseudo, ARM::VST2d16, false, false, SingleSpc, 2, 4 },
222{ ARM::VST2d16Pseudo_UPD, ARM::VST2d16_UPD, false, true, SingleSpc, 2, 4 },
223{ ARM::VST2d32Pseudo, ARM::VST2d32, false, false, SingleSpc, 2, 2 },
224{ ARM::VST2d32Pseudo_UPD, ARM::VST2d32_UPD, false, true, SingleSpc, 2, 2 },
225{ ARM::VST2d8Pseudo, ARM::VST2d8, false, false, SingleSpc, 2, 8 },
226{ ARM::VST2d8Pseudo_UPD, ARM::VST2d8_UPD, false, true, SingleSpc, 2, 8 },
227
228{ ARM::VST2q16Pseudo, ARM::VST2q16, false, false, SingleSpc, 4, 4 },
229{ ARM::VST2q16Pseudo_UPD, ARM::VST2q16_UPD, false, true, SingleSpc, 4, 4 },
230{ ARM::VST2q32Pseudo, ARM::VST2q32, false, false, SingleSpc, 4, 2 },
231{ ARM::VST2q32Pseudo_UPD, ARM::VST2q32_UPD, false, true, SingleSpc, 4, 2 },
232{ ARM::VST2q8Pseudo, ARM::VST2q8, false, false, SingleSpc, 4, 8 },
233{ ARM::VST2q8Pseudo_UPD, ARM::VST2q8_UPD, false, true, SingleSpc, 4, 8 },
234
235{ ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, SingleSpc, 3, 4 },
236{ ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, SingleSpc, 3, 4 },
237{ ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, SingleSpc, 3, 2 },
238{ ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, SingleSpc, 3, 2 },
239{ ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, SingleSpc, 3, 8 },
240{ ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, SingleSpc, 3, 8 },
241{ ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, EvenDblSpc, 3, 4},
242{ ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, EvenDblSpc, 3, 4},
243{ ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, EvenDblSpc, 3, 2},
244{ ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, EvenDblSpc, 3, 2},
245
246{ ARM::VST3d16Pseudo, ARM::VST3d16, false, false, SingleSpc, 3, 4 },
247{ ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, SingleSpc, 3, 4 },
248{ ARM::VST3d32Pseudo, ARM::VST3d32, false, false, SingleSpc, 3, 2 },
249{ ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, SingleSpc, 3, 2 },
250{ ARM::VST3d8Pseudo, ARM::VST3d8, false, false, SingleSpc, 3, 8 },
251{ ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, SingleSpc, 3, 8 },
252
253{ ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, EvenDblSpc, 3, 4 },
254{ ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, OddDblSpc, 3, 4 },
255{ ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, EvenDblSpc, 3, 2 },
256{ ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, OddDblSpc, 3, 2 },
257{ ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, EvenDblSpc, 3, 8 },
258{ ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, OddDblSpc, 3, 8 },
259
260{ ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, SingleSpc, 4, 4 },
261{ ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, SingleSpc, 4, 4 },
262{ ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, SingleSpc, 4, 2 },
263{ ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, SingleSpc, 4, 2 },
264{ ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, SingleSpc, 4, 8 },
265{ ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, SingleSpc, 4, 8 },
266{ ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, EvenDblSpc, 4, 4},
267{ ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, EvenDblSpc, 4, 4},
268{ ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, EvenDblSpc, 4, 2},
269{ ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, EvenDblSpc, 4, 2},
270
271{ ARM::VST4d16Pseudo, ARM::VST4d16, false, false, SingleSpc, 4, 4 },
272{ ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, SingleSpc, 4, 4 },
273{ ARM::VST4d32Pseudo, ARM::VST4d32, false, false, SingleSpc, 4, 2 },
274{ ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, SingleSpc, 4, 2 },
275{ ARM::VST4d8Pseudo, ARM::VST4d8, false, false, SingleSpc, 4, 8 },
276{ ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, SingleSpc, 4, 8 },
277
278{ ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, EvenDblSpc, 4, 4 },
279{ ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, OddDblSpc, 4, 4 },
280{ ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, EvenDblSpc, 4, 2 },
281{ ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, OddDblSpc, 4, 2 },
282{ ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, EvenDblSpc, 4, 8 },
283{ ARM::VST4q8oddPseudo_UPD , ARM::VST4q8_UPD, false, true, OddDblSpc, 4, 8 }
284};
285
286/// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
287/// load or store pseudo instruction.
288static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
289 unsigned NumEntries = array_lengthof(NEONLdStTable);
290
291#ifndef NDEBUG
292 // Make sure the table is sorted.
293 static bool TableChecked = false;
294 if (!TableChecked) {
295 for (unsigned i = 0; i != NumEntries-1; ++i)
296 assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
297 "NEONLdStTable is not sorted!");
298 TableChecked = true;
299 }
300#endif
301
302 const NEONLdStTableEntry *I =
303 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
304 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
305 return I;
306 return NULL;
307}
308
309/// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
310/// corresponding to the specified register spacing. Not all of the results
311/// are necessarily valid, e.g., a Q register only has 2 D subregisters.
312static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
313 const TargetRegisterInfo *TRI, unsigned &D0,
314 unsigned &D1, unsigned &D2, unsigned &D3) {
315 if (RegSpc == SingleSpc) {
316 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
317 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
318 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
319 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
320 } else if (RegSpc == EvenDblSpc) {
321 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
322 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
323 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
324 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
325 } else {
326 assert(RegSpc == OddDblSpc && "unknown register spacing");
327 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
328 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
329 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
330 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
Bob Wilsonbd916c52010-09-13 23:55:10 +0000331 }
Bob Wilson8466fa12010-09-13 23:01:35 +0000332}
333
Bob Wilson82a9c842010-09-02 16:17:29 +0000334/// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
335/// operands to real VLD instructions with D register operands.
Bob Wilson8466fa12010-09-13 23:01:35 +0000336void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
Bob Wilsonffde0802010-09-02 16:00:54 +0000337 MachineInstr &MI = *MBBI;
338 MachineBasicBlock &MBB = *MI.getParent();
339
Bob Wilson8466fa12010-09-13 23:01:35 +0000340 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
341 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
342 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
343 unsigned NumRegs = TableEntry->NumRegs;
344
345 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
346 TII->get(TableEntry->RealOpc));
Bob Wilsonffde0802010-09-02 16:00:54 +0000347 unsigned OpIdx = 0;
348
349 bool DstIsDead = MI.getOperand(OpIdx).isDead();
350 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
351 unsigned D0, D1, D2, D3;
Bob Wilson8466fa12010-09-13 23:01:35 +0000352 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
Bob Wilsonf5721912010-09-03 18:16:02 +0000353 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
354 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
Bob Wilsonffde0802010-09-02 16:00:54 +0000355 if (NumRegs > 2)
Bob Wilsonf5721912010-09-03 18:16:02 +0000356 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
Bob Wilsonffde0802010-09-02 16:00:54 +0000357 if (NumRegs > 3)
Bob Wilsonf5721912010-09-03 18:16:02 +0000358 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
Bob Wilsonffde0802010-09-02 16:00:54 +0000359
Bob Wilson8466fa12010-09-13 23:01:35 +0000360 if (TableEntry->HasWriteBack)
Bob Wilson63569c92010-09-09 00:15:32 +0000361 MIB.addOperand(MI.getOperand(OpIdx++));
362
Bob Wilsonffde0802010-09-02 16:00:54 +0000363 // Copy the addrmode6 operands.
Bob Wilson63569c92010-09-09 00:15:32 +0000364 MIB.addOperand(MI.getOperand(OpIdx++));
365 MIB.addOperand(MI.getOperand(OpIdx++));
366 // Copy the am6offset operand.
Bob Wilson8466fa12010-09-13 23:01:35 +0000367 if (TableEntry->HasWriteBack)
Bob Wilson63569c92010-09-09 00:15:32 +0000368 MIB.addOperand(MI.getOperand(OpIdx++));
Bob Wilsonffde0802010-09-02 16:00:54 +0000369
Bob Wilson19d644d2010-09-09 00:38:32 +0000370 // For an instruction writing double-spaced subregs, the pseudo instruction
Bob Wilson823611b2010-09-16 04:25:37 +0000371 // has an extra operand that is a use of the super-register. Record the
372 // operand index and skip over it.
373 unsigned SrcOpIdx = 0;
374 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
375 SrcOpIdx = OpIdx++;
376
377 // Copy the predicate operands.
378 MIB.addOperand(MI.getOperand(OpIdx++));
379 MIB.addOperand(MI.getOperand(OpIdx++));
380
381 // Copy the super-register source operand used for double-spaced subregs over
Bob Wilson19d644d2010-09-09 00:38:32 +0000382 // to the new instruction as an implicit operand.
Bob Wilson823611b2010-09-16 04:25:37 +0000383 if (SrcOpIdx != 0) {
384 MachineOperand MO = MI.getOperand(SrcOpIdx);
Bob Wilson19d644d2010-09-09 00:38:32 +0000385 MO.setImplicit(true);
386 MIB.addOperand(MO);
387 }
Bob Wilsonf5721912010-09-03 18:16:02 +0000388 // Add an implicit def for the super-register.
389 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
Bob Wilson19d644d2010-09-09 00:38:32 +0000390 TransferImpOps(MI, MIB, MIB);
Bob Wilsonffde0802010-09-02 16:00:54 +0000391 MI.eraseFromParent();
392}
393
Bob Wilson01ba4612010-08-26 18:51:29 +0000394/// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
395/// operands to real VST instructions with D register operands.
Bob Wilson8466fa12010-09-13 23:01:35 +0000396void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
Bob Wilson709d5922010-08-25 23:27:42 +0000397 MachineInstr &MI = *MBBI;
398 MachineBasicBlock &MBB = *MI.getParent();
399
Bob Wilson8466fa12010-09-13 23:01:35 +0000400 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
401 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
402 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
403 unsigned NumRegs = TableEntry->NumRegs;
404
405 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
406 TII->get(TableEntry->RealOpc));
Bob Wilson709d5922010-08-25 23:27:42 +0000407 unsigned OpIdx = 0;
Bob Wilson8466fa12010-09-13 23:01:35 +0000408 if (TableEntry->HasWriteBack)
Bob Wilson63569c92010-09-09 00:15:32 +0000409 MIB.addOperand(MI.getOperand(OpIdx++));
410
Bob Wilson709d5922010-08-25 23:27:42 +0000411 // Copy the addrmode6 operands.
Bob Wilson63569c92010-09-09 00:15:32 +0000412 MIB.addOperand(MI.getOperand(OpIdx++));
413 MIB.addOperand(MI.getOperand(OpIdx++));
414 // Copy the am6offset operand.
Bob Wilson8466fa12010-09-13 23:01:35 +0000415 if (TableEntry->HasWriteBack)
Bob Wilson63569c92010-09-09 00:15:32 +0000416 MIB.addOperand(MI.getOperand(OpIdx++));
Bob Wilson709d5922010-08-25 23:27:42 +0000417
418 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
Bob Wilson823611b2010-09-16 04:25:37 +0000419 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
Bob Wilson709d5922010-08-25 23:27:42 +0000420 unsigned D0, D1, D2, D3;
Bob Wilson8466fa12010-09-13 23:01:35 +0000421 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
Bob Wilson7e701972010-08-30 18:10:48 +0000422 MIB.addReg(D0).addReg(D1);
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000423 if (NumRegs > 2)
Bob Wilson7e701972010-08-30 18:10:48 +0000424 MIB.addReg(D2);
Bob Wilson01ba4612010-08-26 18:51:29 +0000425 if (NumRegs > 3)
Bob Wilson7e701972010-08-30 18:10:48 +0000426 MIB.addReg(D3);
Bob Wilson823611b2010-09-16 04:25:37 +0000427
428 // Copy the predicate operands.
429 MIB.addOperand(MI.getOperand(OpIdx++));
430 MIB.addOperand(MI.getOperand(OpIdx++));
431
Bob Wilson7e701972010-08-30 18:10:48 +0000432 if (SrcIsKill)
433 // Add an implicit kill for the super-reg.
434 (*MIB).addRegisterKilled(SrcReg, TRI, true);
Bob Wilsonbd916c52010-09-13 23:55:10 +0000435 TransferImpOps(MI, MIB, MIB);
Bob Wilson709d5922010-08-25 23:27:42 +0000436 MI.eraseFromParent();
437}
438
Bob Wilson8466fa12010-09-13 23:01:35 +0000439/// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
440/// register operands to real instructions with D register operands.
441void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
442 MachineInstr &MI = *MBBI;
443 MachineBasicBlock &MBB = *MI.getParent();
444
445 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
446 assert(TableEntry && "NEONLdStTable lookup failed");
447 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
448 unsigned NumRegs = TableEntry->NumRegs;
449 unsigned RegElts = TableEntry->RegElts;
450
451 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
452 TII->get(TableEntry->RealOpc));
453 unsigned OpIdx = 0;
454 // The lane operand is always the 3rd from last operand, before the 2
455 // predicate operands.
456 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
457
458 // Adjust the lane and spacing as needed for Q registers.
459 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
460 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
461 RegSpc = OddDblSpc;
462 Lane -= RegElts;
463 }
464 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
465
Bob Wilsonfe3ac082010-09-14 21:12:05 +0000466 unsigned D0, D1, D2, D3;
467 unsigned DstReg = 0;
468 bool DstIsDead = false;
Bob Wilson8466fa12010-09-13 23:01:35 +0000469 if (TableEntry->IsLoad) {
470 DstIsDead = MI.getOperand(OpIdx).isDead();
471 DstReg = MI.getOperand(OpIdx++).getReg();
472 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
473 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
474 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
475 if (NumRegs > 2)
476 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
477 if (NumRegs > 3)
478 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
479 }
480
481 if (TableEntry->HasWriteBack)
482 MIB.addOperand(MI.getOperand(OpIdx++));
483
484 // Copy the addrmode6 operands.
485 MIB.addOperand(MI.getOperand(OpIdx++));
486 MIB.addOperand(MI.getOperand(OpIdx++));
487 // Copy the am6offset operand.
488 if (TableEntry->HasWriteBack)
489 MIB.addOperand(MI.getOperand(OpIdx++));
490
491 // Grab the super-register source.
492 MachineOperand MO = MI.getOperand(OpIdx++);
493 if (!TableEntry->IsLoad)
494 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
495
496 // Add the subregs as sources of the new instruction.
497 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
498 getKillRegState(MO.isKill()));
499 MIB.addReg(D0, SrcFlags).addReg(D1, SrcFlags);
500 if (NumRegs > 2)
501 MIB.addReg(D2, SrcFlags);
502 if (NumRegs > 3)
503 MIB.addReg(D3, SrcFlags);
504
505 // Add the lane number operand.
506 MIB.addImm(Lane);
Bob Wilson823611b2010-09-16 04:25:37 +0000507 OpIdx += 1;
Bob Wilson8466fa12010-09-13 23:01:35 +0000508
Bob Wilson823611b2010-09-16 04:25:37 +0000509 // Copy the predicate operands.
510 MIB.addOperand(MI.getOperand(OpIdx++));
511 MIB.addOperand(MI.getOperand(OpIdx++));
512
Bob Wilson8466fa12010-09-13 23:01:35 +0000513 // Copy the super-register source to be an implicit source.
514 MO.setImplicit(true);
515 MIB.addOperand(MO);
516 if (TableEntry->IsLoad)
517 // Add an implicit def for the super-register.
518 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
519 TransferImpOps(MI, MIB, MIB);
520 MI.eraseFromParent();
521}
522
Bob Wilsonbd916c52010-09-13 23:55:10 +0000523/// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
524/// register operands to real instructions with D register operands.
525void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
526 unsigned Opc, bool IsExt, unsigned NumRegs) {
527 MachineInstr &MI = *MBBI;
528 MachineBasicBlock &MBB = *MI.getParent();
529
530 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
531 unsigned OpIdx = 0;
532
533 // Transfer the destination register operand.
534 MIB.addOperand(MI.getOperand(OpIdx++));
535 if (IsExt)
536 MIB.addOperand(MI.getOperand(OpIdx++));
537
538 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
539 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
540 unsigned D0, D1, D2, D3;
541 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
542 MIB.addReg(D0).addReg(D1);
543 if (NumRegs > 2)
544 MIB.addReg(D2);
545 if (NumRegs > 3)
546 MIB.addReg(D3);
547
548 // Copy the other source register operand.
Bob Wilson823611b2010-09-16 04:25:37 +0000549 MIB.addOperand(MI.getOperand(OpIdx++));
Bob Wilsonbd916c52010-09-13 23:55:10 +0000550
Bob Wilson823611b2010-09-16 04:25:37 +0000551 // Copy the predicate operands.
552 MIB.addOperand(MI.getOperand(OpIdx++));
553 MIB.addOperand(MI.getOperand(OpIdx++));
554
Bob Wilsonbd916c52010-09-13 23:55:10 +0000555 if (SrcIsKill)
556 // Add an implicit kill for the super-reg.
557 (*MIB).addRegisterKilled(SrcReg, TRI, true);
558 TransferImpOps(MI, MIB, MIB);
559 MI.eraseFromParent();
560}
561
Evan Chengb9803a82009-11-06 23:52:48 +0000562bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
563 bool Modified = false;
564
565 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
566 while (MBBI != E) {
567 MachineInstr &MI = *MBBI;
Chris Lattner7896c9f2009-12-03 00:50:42 +0000568 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
Evan Chengb9803a82009-11-06 23:52:48 +0000569
Bob Wilson709d5922010-08-25 23:27:42 +0000570 bool ModifiedOp = true;
Evan Chengb9803a82009-11-06 23:52:48 +0000571 unsigned Opcode = MI.getOpcode();
572 switch (Opcode) {
Bob Wilson709d5922010-08-25 23:27:42 +0000573 default:
574 ModifiedOp = false;
575 break;
576
Bob Wilsonbd916c52010-09-13 23:55:10 +0000577 case ARM::tLDRpci_pic:
Evan Chengb9803a82009-11-06 23:52:48 +0000578 case ARM::t2LDRpci_pic: {
579 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
580 ? ARM::tLDRpci : ARM::t2LDRpci;
581 unsigned DstReg = MI.getOperand(0).getReg();
Evan Cheng43130072010-05-12 23:13:12 +0000582 bool DstIsDead = MI.getOperand(0).isDead();
583 MachineInstrBuilder MIB1 =
584 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
585 TII->get(NewLdOpc), DstReg)
586 .addOperand(MI.getOperand(1)));
587 (*MIB1).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
588 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
589 TII->get(ARM::tPICADD))
590 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
591 .addReg(DstReg)
592 .addOperand(MI.getOperand(2));
593 TransferImpOps(MI, MIB1, MIB2);
Evan Chengb9803a82009-11-06 23:52:48 +0000594 MI.eraseFromParent();
Evan Chengb9803a82009-11-06 23:52:48 +0000595 break;
596 }
Evan Cheng43130072010-05-12 23:13:12 +0000597
Anton Korobeynikov6d1e29d2010-08-30 22:50:36 +0000598 case ARM::MOVi32imm:
Evan Chengb9803a82009-11-06 23:52:48 +0000599 case ARM::t2MOVi32imm: {
Evan Cheng43130072010-05-12 23:13:12 +0000600 unsigned PredReg = 0;
601 ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
Evan Chengb9803a82009-11-06 23:52:48 +0000602 unsigned DstReg = MI.getOperand(0).getReg();
Evan Cheng43130072010-05-12 23:13:12 +0000603 bool DstIsDead = MI.getOperand(0).isDead();
604 const MachineOperand &MO = MI.getOperand(1);
605 MachineInstrBuilder LO16, HI16;
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000606
Anton Korobeynikov6d1e29d2010-08-30 22:50:36 +0000607 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
608 TII->get(Opcode == ARM::MOVi32imm ?
609 ARM::MOVi16 : ARM::t2MOVi16),
Evan Cheng43130072010-05-12 23:13:12 +0000610 DstReg);
Anton Korobeynikov6d1e29d2010-08-30 22:50:36 +0000611 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
612 TII->get(Opcode == ARM::MOVi32imm ?
613 ARM::MOVTi16 : ARM::t2MOVTi16))
Evan Cheng43130072010-05-12 23:13:12 +0000614 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
615 .addReg(DstReg);
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000616
Evan Cheng43130072010-05-12 23:13:12 +0000617 if (MO.isImm()) {
618 unsigned Imm = MO.getImm();
619 unsigned Lo16 = Imm & 0xffff;
620 unsigned Hi16 = (Imm >> 16) & 0xffff;
621 LO16 = LO16.addImm(Lo16);
622 HI16 = HI16.addImm(Hi16);
623 } else {
624 const GlobalValue *GV = MO.getGlobal();
625 unsigned TF = MO.getTargetFlags();
626 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
627 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
Evan Chengb9803a82009-11-06 23:52:48 +0000628 }
Evan Cheng43130072010-05-12 23:13:12 +0000629 (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
630 (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
631 LO16.addImm(Pred).addReg(PredReg);
632 HI16.addImm(Pred).addReg(PredReg);
633 TransferImpOps(MI, LO16, HI16);
Evan Chengb9803a82009-11-06 23:52:48 +0000634 MI.eraseFromParent();
Evan Chengd929f772010-05-13 00:17:02 +0000635 break;
636 }
637
638 case ARM::VMOVQQ: {
639 unsigned DstReg = MI.getOperand(0).getReg();
640 bool DstIsDead = MI.getOperand(0).isDead();
Jakob Stoklund Olesen558661d2010-05-24 16:54:32 +0000641 unsigned EvenDst = TRI->getSubReg(DstReg, ARM::qsub_0);
642 unsigned OddDst = TRI->getSubReg(DstReg, ARM::qsub_1);
Evan Chengd929f772010-05-13 00:17:02 +0000643 unsigned SrcReg = MI.getOperand(1).getReg();
644 bool SrcIsKill = MI.getOperand(1).isKill();
Jakob Stoklund Olesen558661d2010-05-24 16:54:32 +0000645 unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::qsub_0);
646 unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::qsub_1);
Evan Chengd929f772010-05-13 00:17:02 +0000647 MachineInstrBuilder Even =
648 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
649 TII->get(ARM::VMOVQ))
Jim Grosbach18f30e62010-06-02 21:53:11 +0000650 .addReg(EvenDst,
651 getDefRegState(true) | getDeadRegState(DstIsDead))
652 .addReg(EvenSrc, getKillRegState(SrcIsKill)));
Evan Chengd929f772010-05-13 00:17:02 +0000653 MachineInstrBuilder Odd =
654 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
655 TII->get(ARM::VMOVQ))
Jim Grosbach18f30e62010-06-02 21:53:11 +0000656 .addReg(OddDst,
657 getDefRegState(true) | getDeadRegState(DstIsDead))
658 .addReg(OddSrc, getKillRegState(SrcIsKill)));
Evan Chengd929f772010-05-13 00:17:02 +0000659 TransferImpOps(MI, Even, Odd);
660 MI.eraseFromParent();
Bob Wilsonea606bb2010-09-16 00:31:32 +0000661 break;
Bob Wilson709d5922010-08-25 23:27:42 +0000662 }
663
Bob Wilson9d4ebc02010-09-16 00:31:02 +0000664 case ARM::VLDMQ: {
665 MachineInstrBuilder MIB =
666 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::VLDMD));
667 unsigned OpIdx = 0;
668 // Grab the Q register destination.
669 bool DstIsDead = MI.getOperand(OpIdx).isDead();
670 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
671 // Copy the addrmode4 operands.
672 MIB.addOperand(MI.getOperand(OpIdx++));
673 MIB.addOperand(MI.getOperand(OpIdx++));
674 // Copy the predicate operands.
675 MIB.addOperand(MI.getOperand(OpIdx++));
676 MIB.addOperand(MI.getOperand(OpIdx++));
677 // Add the destination operands (D subregs).
678 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
679 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
680 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
681 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
682 // Add an implicit def for the super-register.
683 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
684 TransferImpOps(MI, MIB, MIB);
685 MI.eraseFromParent();
686 break;
687 }
688
689 case ARM::VSTMQ: {
690 MachineInstrBuilder MIB =
691 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::VSTMD));
692 unsigned OpIdx = 0;
693 // Grab the Q register source.
694 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
695 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
696 // Copy the addrmode4 operands.
697 MIB.addOperand(MI.getOperand(OpIdx++));
698 MIB.addOperand(MI.getOperand(OpIdx++));
699 // Copy the predicate operands.
700 MIB.addOperand(MI.getOperand(OpIdx++));
701 MIB.addOperand(MI.getOperand(OpIdx++));
702 // Add the source operands (D subregs).
703 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
704 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
705 MIB.addReg(D0).addReg(D1);
706 if (SrcIsKill)
707 // Add an implicit kill for the Q register.
708 (*MIB).addRegisterKilled(SrcReg, TRI, true);
709 TransferImpOps(MI, MIB, MIB);
710 MI.eraseFromParent();
711 break;
712 }
713
Bob Wilsonffde0802010-09-02 16:00:54 +0000714 case ARM::VLD1q8Pseudo:
Bob Wilsonffde0802010-09-02 16:00:54 +0000715 case ARM::VLD1q16Pseudo:
Bob Wilsonffde0802010-09-02 16:00:54 +0000716 case ARM::VLD1q32Pseudo:
Bob Wilsonffde0802010-09-02 16:00:54 +0000717 case ARM::VLD1q64Pseudo:
Bob Wilsonffde0802010-09-02 16:00:54 +0000718 case ARM::VLD1q8Pseudo_UPD:
Bob Wilsonffde0802010-09-02 16:00:54 +0000719 case ARM::VLD1q16Pseudo_UPD:
Bob Wilsonffde0802010-09-02 16:00:54 +0000720 case ARM::VLD1q32Pseudo_UPD:
Bob Wilsonffde0802010-09-02 16:00:54 +0000721 case ARM::VLD1q64Pseudo_UPD:
Bob Wilsonffde0802010-09-02 16:00:54 +0000722 case ARM::VLD2d8Pseudo:
Bob Wilsonffde0802010-09-02 16:00:54 +0000723 case ARM::VLD2d16Pseudo:
Bob Wilsonffde0802010-09-02 16:00:54 +0000724 case ARM::VLD2d32Pseudo:
Bob Wilsonffde0802010-09-02 16:00:54 +0000725 case ARM::VLD2q8Pseudo:
Bob Wilsonffde0802010-09-02 16:00:54 +0000726 case ARM::VLD2q16Pseudo:
Bob Wilsonffde0802010-09-02 16:00:54 +0000727 case ARM::VLD2q32Pseudo:
Bob Wilsonffde0802010-09-02 16:00:54 +0000728 case ARM::VLD2d8Pseudo_UPD:
Bob Wilsonffde0802010-09-02 16:00:54 +0000729 case ARM::VLD2d16Pseudo_UPD:
Bob Wilsonffde0802010-09-02 16:00:54 +0000730 case ARM::VLD2d32Pseudo_UPD:
Bob Wilsonffde0802010-09-02 16:00:54 +0000731 case ARM::VLD2q8Pseudo_UPD:
Bob Wilsonffde0802010-09-02 16:00:54 +0000732 case ARM::VLD2q16Pseudo_UPD:
Bob Wilsonffde0802010-09-02 16:00:54 +0000733 case ARM::VLD2q32Pseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000734 case ARM::VLD3d8Pseudo:
Bob Wilsonf5721912010-09-03 18:16:02 +0000735 case ARM::VLD3d16Pseudo:
Bob Wilsonf5721912010-09-03 18:16:02 +0000736 case ARM::VLD3d32Pseudo:
Bob Wilsonffde0802010-09-02 16:00:54 +0000737 case ARM::VLD1d64TPseudo:
Bob Wilsonf5721912010-09-03 18:16:02 +0000738 case ARM::VLD3d8Pseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000739 case ARM::VLD3d16Pseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000740 case ARM::VLD3d32Pseudo_UPD:
Bob Wilsonffde0802010-09-02 16:00:54 +0000741 case ARM::VLD1d64TPseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000742 case ARM::VLD3q8Pseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000743 case ARM::VLD3q16Pseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000744 case ARM::VLD3q32Pseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000745 case ARM::VLD3q8oddPseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000746 case ARM::VLD3q16oddPseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000747 case ARM::VLD3q32oddPseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000748 case ARM::VLD4d8Pseudo:
Bob Wilsonf5721912010-09-03 18:16:02 +0000749 case ARM::VLD4d16Pseudo:
Bob Wilsonf5721912010-09-03 18:16:02 +0000750 case ARM::VLD4d32Pseudo:
Bob Wilsonffde0802010-09-02 16:00:54 +0000751 case ARM::VLD1d64QPseudo:
Bob Wilsonf5721912010-09-03 18:16:02 +0000752 case ARM::VLD4d8Pseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000753 case ARM::VLD4d16Pseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000754 case ARM::VLD4d32Pseudo_UPD:
Bob Wilsonffde0802010-09-02 16:00:54 +0000755 case ARM::VLD1d64QPseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000756 case ARM::VLD4q8Pseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000757 case ARM::VLD4q16Pseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000758 case ARM::VLD4q32Pseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000759 case ARM::VLD4q8oddPseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000760 case ARM::VLD4q16oddPseudo_UPD:
Bob Wilsonf5721912010-09-03 18:16:02 +0000761 case ARM::VLD4q32oddPseudo_UPD:
Bob Wilson8466fa12010-09-13 23:01:35 +0000762 ExpandVLD(MBBI);
763 break;
Bob Wilsonffde0802010-09-02 16:00:54 +0000764
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000765 case ARM::VST1q8Pseudo:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000766 case ARM::VST1q16Pseudo:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000767 case ARM::VST1q32Pseudo:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000768 case ARM::VST1q64Pseudo:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000769 case ARM::VST1q8Pseudo_UPD:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000770 case ARM::VST1q16Pseudo_UPD:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000771 case ARM::VST1q32Pseudo_UPD:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000772 case ARM::VST1q64Pseudo_UPD:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000773 case ARM::VST2d8Pseudo:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000774 case ARM::VST2d16Pseudo:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000775 case ARM::VST2d32Pseudo:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000776 case ARM::VST2q8Pseudo:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000777 case ARM::VST2q16Pseudo:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000778 case ARM::VST2q32Pseudo:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000779 case ARM::VST2d8Pseudo_UPD:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000780 case ARM::VST2d16Pseudo_UPD:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000781 case ARM::VST2d32Pseudo_UPD:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000782 case ARM::VST2q8Pseudo_UPD:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000783 case ARM::VST2q16Pseudo_UPD:
Bob Wilsone5ce4f62010-08-28 05:12:57 +0000784 case ARM::VST2q32Pseudo_UPD:
Bob Wilson01ba4612010-08-26 18:51:29 +0000785 case ARM::VST3d8Pseudo:
Bob Wilson01ba4612010-08-26 18:51:29 +0000786 case ARM::VST3d16Pseudo:
Bob Wilson01ba4612010-08-26 18:51:29 +0000787 case ARM::VST3d32Pseudo:
Bob Wilson01ba4612010-08-26 18:51:29 +0000788 case ARM::VST1d64TPseudo:
Bob Wilson01ba4612010-08-26 18:51:29 +0000789 case ARM::VST3d8Pseudo_UPD:
Bob Wilson01ba4612010-08-26 18:51:29 +0000790 case ARM::VST3d16Pseudo_UPD:
Bob Wilson01ba4612010-08-26 18:51:29 +0000791 case ARM::VST3d32Pseudo_UPD:
Bob Wilson01ba4612010-08-26 18:51:29 +0000792 case ARM::VST1d64TPseudo_UPD:
Bob Wilson01ba4612010-08-26 18:51:29 +0000793 case ARM::VST3q8Pseudo_UPD:
Bob Wilson01ba4612010-08-26 18:51:29 +0000794 case ARM::VST3q16Pseudo_UPD:
Bob Wilson01ba4612010-08-26 18:51:29 +0000795 case ARM::VST3q32Pseudo_UPD:
Bob Wilson01ba4612010-08-26 18:51:29 +0000796 case ARM::VST3q8oddPseudo_UPD:
Bob Wilson01ba4612010-08-26 18:51:29 +0000797 case ARM::VST3q16oddPseudo_UPD:
Bob Wilson01ba4612010-08-26 18:51:29 +0000798 case ARM::VST3q32oddPseudo_UPD:
Bob Wilson709d5922010-08-25 23:27:42 +0000799 case ARM::VST4d8Pseudo:
Bob Wilson709d5922010-08-25 23:27:42 +0000800 case ARM::VST4d16Pseudo:
Bob Wilson709d5922010-08-25 23:27:42 +0000801 case ARM::VST4d32Pseudo:
Bob Wilson70e48b22010-08-26 05:33:30 +0000802 case ARM::VST1d64QPseudo:
Bob Wilson709d5922010-08-25 23:27:42 +0000803 case ARM::VST4d8Pseudo_UPD:
Bob Wilson709d5922010-08-25 23:27:42 +0000804 case ARM::VST4d16Pseudo_UPD:
Bob Wilson709d5922010-08-25 23:27:42 +0000805 case ARM::VST4d32Pseudo_UPD:
Bob Wilson70e48b22010-08-26 05:33:30 +0000806 case ARM::VST1d64QPseudo_UPD:
Bob Wilson709d5922010-08-25 23:27:42 +0000807 case ARM::VST4q8Pseudo_UPD:
Bob Wilson709d5922010-08-25 23:27:42 +0000808 case ARM::VST4q16Pseudo_UPD:
Bob Wilson709d5922010-08-25 23:27:42 +0000809 case ARM::VST4q32Pseudo_UPD:
Bob Wilson709d5922010-08-25 23:27:42 +0000810 case ARM::VST4q8oddPseudo_UPD:
Bob Wilson709d5922010-08-25 23:27:42 +0000811 case ARM::VST4q16oddPseudo_UPD:
Bob Wilson709d5922010-08-25 23:27:42 +0000812 case ARM::VST4q32oddPseudo_UPD:
Bob Wilson8466fa12010-09-13 23:01:35 +0000813 ExpandVST(MBBI);
814 break;
815
816 case ARM::VLD2LNd8Pseudo:
817 case ARM::VLD2LNd16Pseudo:
818 case ARM::VLD2LNd32Pseudo:
819 case ARM::VLD2LNq16Pseudo:
820 case ARM::VLD2LNq32Pseudo:
821 case ARM::VLD2LNd8Pseudo_UPD:
822 case ARM::VLD2LNd16Pseudo_UPD:
823 case ARM::VLD2LNd32Pseudo_UPD:
824 case ARM::VLD2LNq16Pseudo_UPD:
825 case ARM::VLD2LNq32Pseudo_UPD:
826 case ARM::VLD3LNd8Pseudo:
827 case ARM::VLD3LNd16Pseudo:
828 case ARM::VLD3LNd32Pseudo:
829 case ARM::VLD3LNq16Pseudo:
830 case ARM::VLD3LNq32Pseudo:
831 case ARM::VLD3LNd8Pseudo_UPD:
832 case ARM::VLD3LNd16Pseudo_UPD:
833 case ARM::VLD3LNd32Pseudo_UPD:
834 case ARM::VLD3LNq16Pseudo_UPD:
835 case ARM::VLD3LNq32Pseudo_UPD:
836 case ARM::VLD4LNd8Pseudo:
837 case ARM::VLD4LNd16Pseudo:
838 case ARM::VLD4LNd32Pseudo:
839 case ARM::VLD4LNq16Pseudo:
840 case ARM::VLD4LNq32Pseudo:
841 case ARM::VLD4LNd8Pseudo_UPD:
842 case ARM::VLD4LNd16Pseudo_UPD:
843 case ARM::VLD4LNd32Pseudo_UPD:
844 case ARM::VLD4LNq16Pseudo_UPD:
845 case ARM::VLD4LNq32Pseudo_UPD:
846 case ARM::VST2LNd8Pseudo:
847 case ARM::VST2LNd16Pseudo:
848 case ARM::VST2LNd32Pseudo:
849 case ARM::VST2LNq16Pseudo:
850 case ARM::VST2LNq32Pseudo:
851 case ARM::VST2LNd8Pseudo_UPD:
852 case ARM::VST2LNd16Pseudo_UPD:
853 case ARM::VST2LNd32Pseudo_UPD:
854 case ARM::VST2LNq16Pseudo_UPD:
855 case ARM::VST2LNq32Pseudo_UPD:
856 case ARM::VST3LNd8Pseudo:
857 case ARM::VST3LNd16Pseudo:
858 case ARM::VST3LNd32Pseudo:
859 case ARM::VST3LNq16Pseudo:
860 case ARM::VST3LNq32Pseudo:
861 case ARM::VST3LNd8Pseudo_UPD:
862 case ARM::VST3LNd16Pseudo_UPD:
863 case ARM::VST3LNd32Pseudo_UPD:
864 case ARM::VST3LNq16Pseudo_UPD:
865 case ARM::VST3LNq32Pseudo_UPD:
866 case ARM::VST4LNd8Pseudo:
867 case ARM::VST4LNd16Pseudo:
868 case ARM::VST4LNd32Pseudo:
869 case ARM::VST4LNq16Pseudo:
870 case ARM::VST4LNq32Pseudo:
871 case ARM::VST4LNd8Pseudo_UPD:
872 case ARM::VST4LNd16Pseudo_UPD:
873 case ARM::VST4LNd32Pseudo_UPD:
874 case ARM::VST4LNq16Pseudo_UPD:
875 case ARM::VST4LNq32Pseudo_UPD:
876 ExpandLaneOp(MBBI);
877 break;
Bob Wilsonbd916c52010-09-13 23:55:10 +0000878
879 case ARM::VTBL2Pseudo:
880 ExpandVTBL(MBBI, ARM::VTBL2, false, 2); break;
881 case ARM::VTBL3Pseudo:
882 ExpandVTBL(MBBI, ARM::VTBL3, false, 3); break;
883 case ARM::VTBL4Pseudo:
884 ExpandVTBL(MBBI, ARM::VTBL4, false, 4); break;
885 case ARM::VTBX2Pseudo:
886 ExpandVTBL(MBBI, ARM::VTBX2, true, 2); break;
887 case ARM::VTBX3Pseudo:
888 ExpandVTBL(MBBI, ARM::VTBX3, true, 3); break;
889 case ARM::VTBX4Pseudo:
890 ExpandVTBL(MBBI, ARM::VTBX4, true, 4); break;
Bob Wilson709d5922010-08-25 23:27:42 +0000891 }
892
893 if (ModifiedOp)
Evan Chengd929f772010-05-13 00:17:02 +0000894 Modified = true;
Evan Chengb9803a82009-11-06 23:52:48 +0000895 MBBI = NMBBI;
896 }
897
898 return Modified;
899}
900
901bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
902 TII = MF.getTarget().getInstrInfo();
Evan Chengd929f772010-05-13 00:17:02 +0000903 TRI = MF.getTarget().getRegisterInfo();
Evan Chengb9803a82009-11-06 23:52:48 +0000904
905 bool Modified = false;
906 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
907 ++MFI)
908 Modified |= ExpandMBB(*MFI);
909 return Modified;
910}
911
912/// createARMExpandPseudoPass - returns an instance of the pseudo instruction
913/// expansion pass.
914FunctionPass *llvm::createARMExpandPseudoPass() {
915 return new ARMExpandPseudo();
916}