blob: 501f763bda28290ee48a92ac7a65ea044bc21312 [file] [log] [blame]
Evan Cheng859df5e2010-06-20 00:54:38 +00001; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O3 -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8
2; rdar://8110842
3
4declare arm_apcscc i32 @__maskrune(i32, i32)
5
6define arm_apcscc i32 @strncmpic(i8* nocapture %s1, i8* nocapture %s2, i32 %n) nounwind {
7entry:
8 br i1 undef, label %bb11, label %bb19
9
10bb11: ; preds = %entry
11 %0 = sext i8 0 to i32 ; <i32> [#uses=1]
12 br i1 undef, label %bb.i.i10, label %bb1.i.i11
13
14bb.i.i10: ; preds = %bb11
15 br label %isupper144.exit12
16
17bb1.i.i11: ; preds = %bb11
18 %1 = tail call arm_apcscc i32 @__maskrune(i32 %0, i32 32768) nounwind ; <i32> [#uses=1]
19 %2 = icmp ne i32 %1, 0 ; <i1> [#uses=1]
20 %3 = zext i1 %2 to i32 ; <i32> [#uses=1]
21 %.pre = load i8* undef, align 1 ; <i8> [#uses=1]
22 br label %isupper144.exit12
23
24isupper144.exit12: ; preds = %bb1.i.i11, %bb.i.i10
25 %4 = phi i8 [ %.pre, %bb1.i.i11 ], [ 0, %bb.i.i10 ] ; <i8> [#uses=1]
26 %5 = phi i32 [ %3, %bb1.i.i11 ], [ undef, %bb.i.i10 ] ; <i32> [#uses=1]
27 %6 = icmp eq i32 %5, 0 ; <i1> [#uses=1]
28 %7 = sext i8 %4 to i32 ; <i32> [#uses=1]
29 %storemerge1 = select i1 %6, i32 %7, i32 undef ; <i32> [#uses=1]
30 %8 = sub nsw i32 %storemerge1, 0 ; <i32> [#uses=1]
31 ret i32 %8
32
33bb19: ; preds = %entry
34 ret i32 0
35}